diff options
Diffstat (limited to 'src/base/io/ioReadVerilog.c')
| -rw-r--r-- | src/base/io/ioReadVerilog.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c index 5956a9bc..090cf254 100644 --- a/src/base/io/ioReadVerilog.c +++ b/src/base/io/ioReadVerilog.c @@ -45,13 +45,12 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) { Abc_Ntk_t * pNtk; Abc_Lib_t * pDesign; - int i; // parse the verilog file - pDesign = Ver_ParseFile( pFileName, NULL, 1, fCheck ); + pDesign = Ver_ParseFile( pFileName, NULL, fCheck, 1 ); if ( pDesign == NULL ) return NULL; - +/* // extract the master network pNtk = Vec_PtrEntryLast( pDesign->vModules ); pNtk->pDesign = pDesign; @@ -75,6 +74,28 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) // check that there is no cyclic dependency Abc_NtkIsAcyclicHierarchy( pNtk ); } +*/ + // extract the master network + pNtk = Vec_PtrEntry( pDesign->vModules, 0 ); + pNtk->pDesign = pDesign; + pDesign->pManFunc = NULL; + +//Io_WriteVerilog( pNtk, "_temp.v" ); + + // verify the design for cyclic dependence + assert( Vec_PtrSize(pDesign->vModules) > 0 ); + if ( Vec_PtrSize(pDesign->vModules) == 1 ) + { +// printf( "Warning: The design is not hierarchical.\n" ); + Abc_LibFree( pDesign, pNtk ); + pNtk->pDesign = NULL; + pNtk->pSpec = Extra_UtilStrsav( pFileName ); + } + else + { + // check that there is no cyclic dependency + Abc_NtkIsAcyclicHierarchy( pNtk ); + } return pNtk; } |