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-rw-r--r--src/base/cba/cbaWriteVer.c96
1 files changed, 65 insertions, 31 deletions
diff --git a/src/base/cba/cbaWriteVer.c b/src/base/cba/cbaWriteVer.c
index d11c1d0e..22819fe1 100644
--- a/src/base/cba/cbaWriteVer.c
+++ b/src/base/cba/cbaWriteVer.c
@@ -42,25 +42,27 @@ typedef enum {
CBA_NODE_XNOR, // 9 .XNOR
CBA_NODE_MUX, // 10: MUX
CBA_NODE_MAJ, // 11: MAJ
- CBA_NODE_UNKNOWN // 12: unknown
+ CBA_NODE_KNOWN // 12: unknown
+ CBA_NODE_UNKNOWN // 13: unknown
} Cba_NodeType_t;
*/
const char * s_NodeTypes[CBA_NODE_UNKNOWN+1] = {
- NULL, // 0: unused
- "const", // 1: constant
- "buf", // 2: buffer
- "not", // 3: inverter
- "and", // 4: AND
- "or", // 5: OR
- "xor", // 6: XOR
- "nand", // 7: NAND
- "nor", // 8: NOR
- "xnor", // 9 .XNOR
- "mux", // 10: MUX
- "maj", // 11: MAJ
- "???" // 12: unknown
+ NULL, // 0: unused
+ "const", // 1: constant
+ "buf", // 2: buffer
+ "not", // 3: inverter
+ "and", // 4: AND
+ "nand", // 5: OR
+ "or", // 6: XOR
+ "nor", // 7: NAND
+ "xor", // 8: NOR
+ "xnor", // 9: .XNOR
+ "mux", // 10: MUX
+ "maj", // 11: MAJ
+ "???" // 12: known
+ "???" // 13: unknown
};
////////////////////////////////////////////////////////////////////////
@@ -83,29 +85,50 @@ void Cba_PrsWriteVerilogMux( FILE * pFile, Cba_Ntk_t * p, Vec_Int_t * vFanins )
int NameId, RangeId, i;
char * pStrs[4] = { " = ", " ? ", " : ", ";\n" };
assert( Vec_IntSize(vFanins) == 8 );
- fprintf( pFile, "assign " );
+ fprintf( pFile, " assign " );
Vec_IntForEachEntryDouble( vFanins, NameId, RangeId, i )
- fprintf( pFile, "%s%s%s", Cba_NtkStr(p, NameId), RangeId ? Cba_NtkStr(p, RangeId) : "", pStrs[i/2] );
+ {
+ fprintf( pFile, "%s%s%s", Cba_NtkStr(p, NameId), RangeId > 0 ? Cba_NtkStr(p, RangeId) : "", pStrs[i/2] );
+ }
+}
+void Cba_PrsWriteVerilogConcat( FILE * pFile, Cba_Ntk_t * p, int Id )
+{
+ extern void Cba_PrsWriteVerilogArray2( FILE * pFile, Cba_Ntk_t * p, Vec_Int_t * vFanins );
+ fprintf( pFile, "{" );
+ Cba_PrsWriteVerilogArray2( pFile, p, Cba_ObjFanins(p, Id) );
+ fprintf( pFile, "}" );
}
void Cba_PrsWriteVerilogArray2( FILE * pFile, Cba_Ntk_t * p, Vec_Int_t * vFanins )
{
int NameId, RangeId, i;
assert( Vec_IntSize(vFanins) % 2 == 0 );
Vec_IntForEachEntryDouble( vFanins, NameId, RangeId, i )
- fprintf( pFile, "%s%s%s", Cba_NtkStr(p, NameId), RangeId ? Cba_NtkStr(p, RangeId) : "", (i == Vec_IntSize(vFanins) - 2) ? "" : " ," );
+ {
+ assert( RangeId >= -2 );
+ if ( RangeId == -2 )
+ Cba_PrsWriteVerilogConcat( pFile, p, NameId-1 );
+ else if ( RangeId == -1 )
+ fprintf( pFile, "%s", Cba_NtkStr(p, NameId) );
+ else
+ fprintf( pFile, "%s%s", Cba_NtkStr(p, NameId), RangeId ? Cba_NtkStr(p, RangeId) : "" );
+ fprintf( pFile, "%s", (i == Vec_IntSize(vFanins) - 2) ? "" : ", " );
+ }
}
void Cba_PrsWriteVerilogArray3( FILE * pFile, Cba_Ntk_t * p, Vec_Int_t * vFanins )
{
int FormId, NameId, RangeId, i;
assert( Vec_IntSize(vFanins) % 3 == 0 );
Vec_IntForEachEntryTriple( vFanins, FormId, NameId, RangeId, i )
- fprintf( pFile, ".%s(%s%s)%s", Cba_NtkStr(p, FormId), Cba_NtkStr(p, NameId), RangeId ? Cba_NtkStr(p, RangeId) : "", (i == Vec_IntSize(vFanins) - 3) ? "" : " ," );
-}
-void Cba_PrsWriteVerilogConcat( FILE * pFile, Cba_Ntk_t * p, int Id )
-{
- fprintf( pFile, "{" );
- Cba_PrsWriteVerilogArray2( pFile, p, Cba_ObjFanins(p, Id) );
- fprintf( pFile, "}" );
+ {
+ fprintf( pFile, ".%s(", Cba_NtkStr(p, FormId) );
+ if ( RangeId == -2 )
+ Cba_PrsWriteVerilogConcat( pFile, p, NameId-1 );
+ else if ( RangeId == -1 )
+ fprintf( pFile, "%s", Cba_NtkStr(p, NameId) );
+ else
+ fprintf( pFile, "%s%s", Cba_NtkStr(p, NameId), RangeId ? Cba_NtkStr(p, RangeId) : "" );
+ fprintf( pFile, ")%s", (i == Vec_IntSize(vFanins) - 3) ? "" : ", " );
+ }
}
void Cba_PrsWriteVerilogNodes( FILE * pFile, Cba_Ntk_t * p )
{
@@ -116,13 +139,17 @@ void Cba_PrsWriteVerilogNodes( FILE * pFile, Cba_Ntk_t * p )
Func = Cba_ObjFuncId(p, i);
if ( Func >= CBA_NODE_BUF && Func <= CBA_NODE_XNOR )
{
- fprintf( pFile, "%s (", s_NodeTypes[Func] );
+ fprintf( pFile, " %s (", s_NodeTypes[Func] );
Cba_PrsWriteVerilogArray2( pFile, p, Cba_ObjFanins(p, i) );
fprintf( pFile, ");\n" );
}
else if ( Func == CBA_NODE_MUX )
Cba_PrsWriteVerilogMux( pFile, p, Cba_ObjFanins(p, i) );
- else assert( 0 );
+ else
+ {
+ char * pName = Cba_NtkStr(p, Func);
+ assert( 0 );
+ }
}
}
void Cba_PrsWriteVerilogBoxes( FILE * pFile, Cba_Ntk_t * p )
@@ -131,7 +158,7 @@ void Cba_PrsWriteVerilogBoxes( FILE * pFile, Cba_Ntk_t * p )
Cba_NtkForEachObjType( p, Type, i )
if ( Type == CBA_PRS_BOX ) // .subckt/.gate/box (formal/actual binding)
{
- fprintf( pFile, "%s %s (", Cba_ObjFuncStr(p, i), Cba_ObjInstStr(p, i) );
+ fprintf( pFile, " %s %s (", Cba_ObjFuncStr(p, i), Cba_ObjInstStr(p, i) );
Cba_PrsWriteVerilogArray3( pFile, p, Cba_ObjFanins(p, i) );
fprintf( pFile, ");\n" );
}
@@ -142,14 +169,14 @@ void Cba_PrsWriteVerilogSignals( FILE * pFile, Cba_Ntk_t * p, int SigType )
char * pSigNames[4] = { "inout", "input", "output", "wire" };
Vec_Int_t * vSigs[4] = { &p->vInouts, &p->vInputs, &p->vOutputs, &p->vWires };
Vec_IntForEachEntryDouble( vSigs[SigType], NameId, RangeId, i )
- fprintf( pFile, "%s %s%s;\n", pSigNames[SigType], RangeId ? Cba_NtkStr(p, RangeId) : "", Cba_NtkStr(p, NameId) );
+ fprintf( pFile, " %s %s%s;\n", pSigNames[SigType], RangeId ? Cba_NtkStr(p, RangeId) : "", Cba_NtkStr(p, NameId) );
}
void Cba_PrsWriteVerilogSignalList( FILE * pFile, Cba_Ntk_t * p, int SigType, int fSkipComma )
{
int NameId, RangeId, i;
Vec_Int_t * vSigs[4] = { &p->vInouts, &p->vInputs, &p->vOutputs, &p->vWires };
Vec_IntForEachEntryDouble( vSigs[SigType], NameId, RangeId, i )
- fprintf( pFile, " %s%s", Cba_NtkStr(p, NameId), (fSkipComma && i == Vec_IntSize(vSigs[SigType]) - 2) ? "" : "," );
+ fprintf( pFile, "%s%s", Cba_NtkStr(p, NameId), (fSkipComma && i == Vec_IntSize(vSigs[SigType]) - 2) ? "" : ", " );
}
void Cba_PrsWriteVerilogNtk( FILE * pFile, Cba_Ntk_t * p )
{
@@ -160,15 +187,22 @@ void Cba_PrsWriteVerilogNtk( FILE * pFile, Cba_Ntk_t * p )
// write header
fprintf( pFile, "module %s (\n", Cba_NtkName(p) );
for ( s = 0; s < 3; s++ )
+ {
+ if ( s == 0 && Vec_IntSize(&p->vInouts) == 0 )
+ continue;
+ fprintf( pFile, " " );
Cba_PrsWriteVerilogSignalList( pFile, p, s, s==2 );
- fprintf( pFile, ");\n" );
+ fprintf( pFile, "\n" );
+ }
+ fprintf( pFile, " );\n" );
// write declarations
for ( s = 0; s < 4; s++ )
Cba_PrsWriteVerilogSignals( pFile, p, s );
+ fprintf( pFile, "\n" );
// write objects
Cba_PrsWriteVerilogNodes( pFile, p );
Cba_PrsWriteVerilogBoxes( pFile, p );
- fprintf( pFile, "endmodule\n" );
+ fprintf( pFile, "endmodule\n\n" );
}
void Cba_PrsWriteVerilog( char * pFileName, Cba_Man_t * pDes )
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-13 21:46:44 +0000