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-rw-r--r--src/base/abci/abcRewrite.c27
1 files changed, 16 insertions, 11 deletions
diff --git a/src/base/abci/abcRewrite.c b/src/base/abci/abcRewrite.c
index a119ccd2..f36600fa 100644
--- a/src/base/abci/abcRewrite.c
+++ b/src/base/abci/abcRewrite.c
@@ -22,6 +22,9 @@
#include "rwr.h"
#include "dec.h"
+ABC_NAMESPACE_IMPL_START
+
+
/*
The ideas realized in this package are inspired by the paper:
Per Bjesse, Arne Boralv, "DAG-aware circuit compression for
@@ -57,7 +60,7 @@ extern void Abc_PlaceUpdate( Vec_Ptr_t * vAddedCells, Vec_Ptr_t * vUpdatedNets
***********************************************************************/
int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerbose, int fVeryVerbose, int fPlaceEnable )
{
- extern void Dec_GraphUpdateNetwork( Abc_Obj_t * pRoot, Dec_Graph_t * pGraph, bool fUpdateLevel, int nGain );
+ extern void Dec_GraphUpdateNetwork( Abc_Obj_t * pRoot, Dec_Graph_t * pGraph, int fUpdateLevel, int nGain );
ProgressBar * pProgress;
Cut_Man_t * pManCut;
Rwr_Man_t * pManRwr;
@@ -69,7 +72,7 @@ int Abc_NtkRewrite( Abc_Ntk_t * pNtk, int fUpdateLevel, int fUseZeros, int fVerb
assert( Abc_NtkIsStrash(pNtk) );
// cleanup the AIG
- Abc_AigCleanup(pNtk->pManFunc);
+ Abc_AigCleanup((Abc_Aig_t *)pNtk->pManFunc);
/*
{
Vec_Vec_t * vParts;
@@ -125,12 +128,12 @@ Rwr_ManAddTimeCuts( pManRwr, clock() - clk );
// if we end up here, a rewriting step is accepted
// get hold of the new subgraph to be added to the AIG
- pGraph = Rwr_ManReadDecs(pManRwr);
+ pGraph = (Dec_Graph_t *)Rwr_ManReadDecs(pManRwr);
fCompl = Rwr_ManReadCompl(pManRwr);
// reset the array of the changed nodes
if ( fPlaceEnable )
- Abc_AigUpdateReset( pNtk->pManFunc );
+ Abc_AigUpdateReset( (Abc_Aig_t *)pNtk->pManFunc );
// complement the FF if needed
if ( fCompl ) Dec_GraphComplement( pGraph );
@@ -242,7 +245,7 @@ void Abc_NodePrintCuts( Abc_Obj_t * pNode )
printf( "\nNode %s\n", Abc_ObjName(pNode) );
vCuts = (Vec_Ptr_t *)pNode->pCopy;
- Vec_PtrForEachEntry( vCuts, pCut, k )
+ Vec_PtrForEachEntry( Cut_Cut_t *, vCuts, pCut, k )
{
Extra_PrintBinary( stdout, (unsigned *)&pCut->uSign, 16 );
printf( " " );
@@ -267,9 +270,9 @@ void Abc_ManRewritePrintDivs( Vec_Ptr_t * vDivs, int nLeaves )
{
Abc_Obj_t * pFanin, * pNode, * pRoot;
int i, k;
- pRoot = Vec_PtrEntryLast(vDivs);
+ pRoot = (Abc_Obj_t *)Vec_PtrEntryLast(vDivs);
// print the nodes
- Vec_PtrForEachEntry( vDivs, pNode, i )
+ Vec_PtrForEachEntry( Abc_Obj_t *, vDivs, pNode, i )
{
if ( i < nLeaves )
{
@@ -278,7 +281,7 @@ void Abc_ManRewritePrintDivs( Vec_Ptr_t * vDivs, int nLeaves )
}
printf( "%6d : %2d = ", pNode->Id, i );
// find the first fanin
- Vec_PtrForEachEntry( vDivs, pFanin, k )
+ Vec_PtrForEachEntry( Abc_Obj_t *, vDivs, pFanin, k )
if ( Abc_ObjFanin0(pNode) == pFanin )
break;
if ( k < nLeaves )
@@ -287,7 +290,7 @@ void Abc_ManRewritePrintDivs( Vec_Ptr_t * vDivs, int nLeaves )
printf( "%d", k );
printf( "%s ", Abc_ObjFaninC0(pNode)? "\'" : "" );
// find the second fanin
- Vec_PtrForEachEntry( vDivs, pFanin, k )
+ Vec_PtrForEachEntry( Abc_Obj_t *, vDivs, pFanin, k )
if ( Abc_ObjFanin1(pNode) == pFanin )
break;
if ( k < nLeaves )
@@ -342,7 +345,7 @@ void Abc_ManShowCutCone( Abc_Obj_t * pNode, Vec_Ptr_t * vLeaves )
int i;
vDivs = Vec_PtrAlloc( 100 );
Abc_NtkIncrementTravId( pNtk );
- Vec_PtrForEachEntry( vLeaves, pObj, i )
+ Vec_PtrForEachEntry( Abc_Obj_t *, vLeaves, pObj, i )
{
Abc_NodeSetTravIdCurrent( Abc_ObjRegular(pObj) );
Vec_PtrPush( vDivs, Abc_ObjRegular(pObj) );
@@ -397,7 +400,7 @@ void Abc_RwrExpWithCut( Abc_Obj_t * pNode, Vec_Ptr_t * vLeaves )
Abc_RwrExpWithCut_rec( Abc_ObjFanin0(pNode), vLeaves, 1 );
Abc_RwrExpWithCut_rec( Abc_ObjFanin1(pNode), vLeaves, 0 );
CountA = CountB = 0;
- Vec_PtrForEachEntry( vLeaves, pObj, i )
+ Vec_PtrForEachEntry( Abc_Obj_t *, vLeaves, pObj, i )
{
CountA += Abc_ObjRegular(pObj)->fMarkA;
CountB += Abc_ObjRegular(pObj)->fMarkB;
@@ -413,3 +416,5 @@ void Abc_RwrExpWithCut( Abc_Obj_t * pNode, Vec_Ptr_t * vLeaves )
////////////////////////////////////////////////////////////////////////
+ABC_NAMESPACE_IMPL_END
+