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Diffstat (limited to 'regtest_output2.txt')
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diff --git a/regtest_output2.txt b/regtest_output2.txt new file mode 100644 index 00000000..ef250dc8 --- /dev/null +++ b/regtest_output2.txt @@ -0,0 +1,97 @@ +UC Berkeley, ABC 1.01 (compiled May 9 2006 09:22:13) +abc 02> so regtest.script +abc - > r examples/apex4.pla; resyn; sharem; fpga; cec; ps; clp; share; resyn; map; cec; ps +Networks are equivalent. +examples/apex4: i/o = 9/ 19 lat = 0 nd = 1183 cube = 2195 lev = 7 +The shared BDD size is 900 nodes. +A simple supergate library is derived from gate library "mcnc_temp.genlib". +Loaded 20 unique 5-input supergates from "mcnc_temp.super". Time = 0.03 sec +Networks are equivalent. +examples/apex4: i/o = 9/ 19 lat = 0 nd = 1789 area = 4554.00 delay = 11.50 lev = 11 +abc - > r examples/C2670.blif; resyn; fpga; cec; ps; u; map; cec; ps +Networks are equivalent. +C2670.iscas : i/o = 233/ 140 lat = 0 nd = 218 cube = 444 lev = 7 +Networks are equivalent. +C2670.iscas : i/o = 233/ 140 lat = 0 nd = 471 area = 1166.00 delay = 15.50 lev = 14 +abc - > r examples/frg2.blif; dsd; muxes; cec; clp; share; resyn; map; cec; ps +Networks are equivalent. +The shared BDD size is 1111 nodes. +Networks are equivalent. +frg2 : i/o = 143/ 139 lat = 0 nd = 540 area = 1373.00 delay = 9.70 lev = 9 +abc - > r examples/pj1.blif; resyn; fpga; cec; ps; u; map; cec; ps +Networks are equivalent. +exCombCkt : i/o = 1769/1063 lat = 0 nd = 5582 cube = 10389 lev = 15 +Networks are equivalent. +exCombCkt : i/o = 1769/1063 lat = 0 nd = 10291 area = 24781.00 delay = 29.80 lev = 27 +abc - > r examples/s38584.bench; resyn; fpga; cec; ps; u; map; cec; ps +Networks are equivalent. +examples/s38584: i/o = 12/ 278 lat = 1452 nd = 4404 cube = 7515 lev = 9 +Networks are equivalent. +examples/s38584: i/o = 12/ 278 lat = 1452 nd = 8506 area = 19313.00 delay = 20.60 lev = 17 +abc - > r examples/ac.v; resyn; fpga; cec; ps; u; map; cec; ps +Networks are equivalent. +ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 4082 cube = 7776 lev = 4 +Networks are equivalent. +ac97_ctrl : i/o = 84/ 48 lat = 2199 nd = 8274 area = 19707.00 delay = 8.10 lev = 8 +abc - > r examples/s444.blif; b; esd -v; dsd; cec; ps +The shared BDD size is 181 nodes. +BDD nodes in the transition relation before reordering 557. +BDD nodes in the transition relation after reordering 456. +Reachability analysis completed in 151 iterations. +The number of minterms in the reachable state set = 8865. +BDD nodes in the unreachable states before reordering 124. +BDD nodes in the unreachable states after reordering 113. +Networks are equivalent. +s444 : i/o = 3/ 6 lat = 21 nd = 81 cube = 119 lev = 7 +abc - > r examples/i10.blif; fpga; cec; ps; u; map; cec; ps +The network was strashed and balanced before FPGA mapping. +Networks are equivalent. +i10 : i/o = 257/ 224 lat = 0 nd = 890 cube = 1593 lev = 13 +The network was strashed and balanced before mapping. +Networks are equivalent. +i10 : i/o = 257/ 224 lat = 0 nd = 1700 area = 4245.00 delay = 30.80 lev = 28 +abc - > r examples/i10.blif; choice; fpga; cec; ps; u; map; cec; ps +Currently stored 3 networks with 5794 nodes will be fraiged. +Total fraiging time = 0.74 sec +Performing FPGA mapping with choices. +Networks are equivalent. +i10 : i/o = 257/ 224 lat = 0 nd = 799 cube = 1484 lev = 12 +Performing mapping with choices. +Networks are equivalent. +i10 : i/o = 257/ 224 lat = 0 nd = 1485 area = 3528.00 delay = 25.40 lev = 23 +abc - > r examples/s6669.blif; fpga; ps; sec; u; sfpga; ps; sec; u; fpga; ret; ps; sec +The network was strashed and balanced before FPGA mapping. +s6669 : i/o = 83/ 55 lat = 239 nd = 679 bdd = 3060 lev = 20 +Networks are equivalent after fraiging. +The network was strashed and balanced before FPGA mapping/retiming. +The number of LUTs with incompatible edges = 25. +The number of LUTs with more than 4 inputs = 18. +s6669 : i/o = 83/ 55 lat = 404 nd = 829 bdd = 3867 lev = 6 +Networks are equivalent after fraiging. +The network was strashed and balanced before FPGA mapping. +s6669 : i/o = 83/ 55 lat = 347 nd = 773 bdd = 3262 lev = 9 +Networks are equivalent after fraiging. +abc - > r examples/s5378.blif; map -s; ps; sec; u; smap; ps; sec; u; map; ret; ps; sec +The network was strashed and balanced before mapping. +s5378 : i/o = 35/ 49 lat = 164 nd = 1009 area = 2352.00 delay = 12.40 lev = 11 +Networks are equivalent after fraiging. +The number of nodes with equal fanins = 5. +The network was strashed and balanced before SC mapping/retiming. +The mininum clock period computed is 10.00. +The resulting network is derived as BDD logic network (this is temporary). +s5378 : i/o = 35/ 49 lat = 399 nd = 1230 bdd = 4548 lev = 7 +Networks are equivalent after fraiging. +The network was strashed and balanced before mapping. +s5378 : i/o = 35/ 49 lat = 359 nd = 1083 area = 2426.00 delay = 13.00 lev = 11 +Networks are equivalent after fraiging. +abc - > time +elapse: 188.97 seconds, total: 188.97 seconds +abc 123> + + + + + + + + |