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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2015-07-21 17:59:07 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2015-07-21 17:59:07 -0700 |
| commit | 9bd16029f154903b0ece7206d9ab84e393a5ef18 (patch) | |
| tree | 644c4cf0323d3bd7647789821851cc905df7d515 /src | |
| parent | ae46690b066a55d591133f18f75b384abb4bc084 (diff) | |
| download | abc-9bd16029f154903b0ece7206d9ab84e393a5ef18.tar.gz abc-9bd16029f154903b0ece7206d9ab84e393a5ef18.tar.bz2 abc-9bd16029f154903b0ece7206d9ab84e393a5ef18.zip | |
Renaming Cba into Bac.
Diffstat (limited to 'src')
| -rw-r--r-- | src/base/bac/bacWriteVer.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/base/bac/bacWriteVer.c b/src/base/bac/bacWriteVer.c index 83826fe7..45742850 100644 --- a/src/base/bac/bacWriteVer.c +++ b/src/base/bac/bacWriteVer.c @@ -64,7 +64,7 @@ static void Psr_ManWriteVerilogSignal( FILE * pFile, Psr_Ntk_t * p, int Sig ) Psr_ManWriteVerilogConcat( pFile, p, Value ); else assert( 0 ); } -static void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) +void Psr_ManWriteVerilogArray( FILE * pFile, Psr_Ntk_t * p, Vec_Int_t * vSigs, int Start, int Stop, int fOdd ) { int i, Sig; assert( Vec_IntSize(vSigs) > 0 ); |