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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2012-08-24 11:12:51 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2012-08-24 11:12:51 -0700 |
| commit | 942600414dba2e32bf2529517e17eaee5991d29c (patch) | |
| tree | e58e0f65b13952d1773f11731c48a955a7068206 /src/proof/fra/fraClaus.c | |
| parent | 12c776ed6e5a17a491fdb986ccce99649a06850e (diff) | |
| download | abc-942600414dba2e32bf2529517e17eaee5991d29c.tar.gz abc-942600414dba2e32bf2529517e17eaee5991d29c.tar.bz2 abc-942600414dba2e32bf2529517e17eaee5991d29c.zip | |
Added simulation of comb circuits with user-specified patterns in command 'sim'.
Diffstat (limited to 'src/proof/fra/fraClaus.c')
| -rw-r--r-- | src/proof/fra/fraClaus.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/proof/fra/fraClaus.c b/src/proof/fra/fraClaus.c index 95ab0c99..c4f50559 100644 --- a/src/proof/fra/fraClaus.c +++ b/src/proof/fra/fraClaus.c @@ -668,7 +668,7 @@ ABC_PRT( "Infoseq", clock() - clk ); clk = clock(); // srand( 0xAABBAABB ); Aig_ManRandom(1); - pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref ); + pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref, 0 ); if ( p->fVerbose ) { ABC_PRT( "Sim-cmb", clock() - clk ); @@ -753,7 +753,7 @@ if ( p->fVerbose ) clk = clock(); // srand( 0xAABBAABB ); Aig_ManRandom(1); - pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref ); + pComb = Fra_SmlSimulateComb( p->pAig, p->nSimWords + p->nSimWordsPref, 0 ); if ( p->fVerbose ) { //ABC_PRT( "Sim-cmb", clock() - clk ); @@ -1628,7 +1628,7 @@ void Fra_ClausEstimateCoverage( Clu_Man_t * p ) // simulate the circuit with nCombSimWords * 32 = 64K patterns // srand( 0xAABBAABB ); Aig_ManRandom(1); - pComb = Fra_SmlSimulateComb( p->pAig, nCombSimWords ); + pComb = Fra_SmlSimulateComb( p->pAig, nCombSimWords, 0 ); // create mapping from SAT vars to node IDs pVar2Id = ABC_ALLOC( int, p->pCnf->nVars ); memset( pVar2Id, 0, sizeof(int) * p->pCnf->nVars ); |