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author | Alan Mishchenko <alanmi@berkeley.edu> | 2020-05-03 12:09:55 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2020-05-03 12:09:55 -0700 |
commit | 559f8f5b5eca41b30e3ee7946a32a03437ad80b8 (patch) | |
tree | bb9bf8256f6371ff9828d89facacdc4cc65094eb /src/map | |
parent | 3e150dd5532205d6b13aa28fdc526f5e8c0e72a1 (diff) | |
download | abc-559f8f5b5eca41b30e3ee7946a32a03437ad80b8.tar.gz abc-559f8f5b5eca41b30e3ee7946a32a03437ad80b8.tar.bz2 abc-559f8f5b5eca41b30e3ee7946a32a03437ad80b8.zip |
Adding dumping of genlib library in Verilog.
Diffstat (limited to 'src/map')
-rw-r--r-- | src/map/mio/exp.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/map/mio/exp.h b/src/map/mio/exp.h index 828d81c9..adbc2f58 100644 --- a/src/map/mio/exp.h +++ b/src/map/mio/exp.h @@ -123,7 +123,7 @@ static inline void Exp_Print( int nVars, Vec_Int_t * p ) } static inline void Exp_PrintNodeVerilog( FILE * pFile, int nVars, Vec_Int_t * p, Vec_Ptr_t * vNames, int Node, int fCompl ) { - extern void Exp_PrintLitVerilog( FILE * pFile, int nVars, Vec_Int_t * p, Vec_Ptr_t * vNames, int Lit ); + static void Exp_PrintLitVerilog( FILE * pFile, int nVars, Vec_Int_t * p, Vec_Ptr_t * vNames, int Lit ); if ( Vec_IntEntry(p, 2*Node+1) >= 2*nVars ) fprintf( pFile, "(" ); Exp_PrintLitVerilog( pFile, nVars, p, vNames, Vec_IntEntry(p, 2*Node+1) ^ fCompl ); |