Version abc80702

11 files changed, 50 insertions, 50 deletions

diff --git a/src/map/fpga/fpga.c b/src/map/fpga/fpga.c
index 31edf689..fa2a138c 100644
--- a/src/map/fpga/fpga.c
+++ b/src/map/fpga/fpga.c
@@ -138,7 +138,7 @@ int Fpga_CommandReadLibrary( Abc_Frame_t * pAbc, int argc, char **argv )
     if ( (pFile = fopen( FileName, "r" )) == NULL )
     {
         fprintf( pErr, "Cannot open input file \"%s\". ", FileName );
-        if ( FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL ) )
+        if ( (FileName = Extra_FileGetSimilarName( FileName, ".genlib", ".lib", ".gen", ".g", NULL )) )
             fprintf( pErr, "Did you mean \"%s\"?", FileName );
         fprintf( pErr, "\n" );
         return 1;
diff --git a/src/map/fpga/fpgaCreate.c b/src/map/fpga/fpgaCreate.c
index be71d74e..c0bae1c7 100644
--- a/src/map/fpga/fpgaCreate.c
+++ b/src/map/fpga/fpgaCreate.c
@@ -28,7 +28,7 @@ static void            Fpga_TableResize( Fpga_Man_t * p );
 static Fpga_Node_t *   Fpga_TableLookup( Fpga_Man_t * p, Fpga_Node_t * p1, Fpga_Node_t * p2 );
 
 // hash key for the structural hash table
-static inline unsigned Fpga_HashKey2( Fpga_Node_t * p0, Fpga_Node_t * p1, int TableSize ) { return ((unsigned)(p0) + (unsigned)(p1) * 12582917) % TableSize; }
+static inline unsigned Fpga_HashKey2( Fpga_Node_t * p0, Fpga_Node_t * p1, int TableSize ) { return (unsigned)(((PORT_PTRUINT_T)(p0) + (PORT_PTRUINT_T)(p1) * 12582917) % TableSize); }
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -252,8 +252,8 @@ void Fpga_ManFree( Fpga_Man_t * p )
 ***********************************************************************/
 void Fpga_ManPrintTimeStats( Fpga_Man_t * p )
 {
-    extern char * pNetName;
-    extern int TotalLuts;
+//    extern char * pNetName;
+//    extern int TotalLuts;
 //    FILE * pTable;
 
     
diff --git a/src/map/fpga/fpgaCut.c b/src/map/fpga/fpgaCut.c
index ce688179..de558456 100644
--- a/src/map/fpga/fpgaCut.c
+++ b/src/map/fpga/fpgaCut.c
@@ -418,8 +418,8 @@ Fpga_Cut_t * Fpga_CutMergeLists( Fpga_Man_t * p, Fpga_CutTable_t * pTable,
             // create the signature
             pCut->uSign = pTemp1->uSign | pTemp2->uSign;
             // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
+            pCut->pNext = pLists[(int)pCut->nLeaves];
+            pLists[(int)pCut->nLeaves] = pCut;
             // count this cut and quit if limit is reached
             Counter++;
             if ( Counter == FPGA_CUTS_MAX_COMPUTE )
@@ -453,8 +453,8 @@ Fpga_Cut_t * Fpga_CutMergeLists( Fpga_Man_t * p, Fpga_CutTable_t * pTable,
             // create the signature
             pCut->uSign = pTemp1->uSign | pTemp2->uSign;
             // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
+            pCut->pNext = pLists[(int)pCut->nLeaves];
+            pLists[(int)pCut->nLeaves] = pCut;
             // count this cut and quit if limit is reached
             Counter++;
             if ( Counter == FPGA_CUTS_MAX_COMPUTE )
@@ -493,8 +493,8 @@ Fpga_Cut_t * Fpga_CutMergeLists( Fpga_Man_t * p, Fpga_CutTable_t * pTable,
             // create the signature
             pCut->uSign = pTemp1->uSign | pTemp2->uSign;
             // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
+            pCut->pNext = pLists[(int)pCut->nLeaves];
+            pLists[(int)pCut->nLeaves] = pCut;
             // count this cut and quit if limit is reached
             Counter++;
             if ( Counter == FPGA_CUTS_MAX_COMPUTE )
@@ -560,8 +560,8 @@ Fpga_Cut_t * Fpga_CutMergeLists2( Fpga_Man_t * p, Fpga_CutTable_t * pTable,
             pCut->pOne = Fpga_CutNotCond( pTemp1, fComp1 );
             pCut->pTwo = Fpga_CutNotCond( pTemp2, fComp2 );
             // add it to the corresponding list
-            pCut->pNext = pLists[pCut->nLeaves];
-            pLists[pCut->nLeaves] = pCut;
+            pCut->pNext = pLists[(int)pCut->nLeaves];
+            pLists[(int)pCut->nLeaves] = pCut;
             // count this cut and quit if limit is reached
             Counter++;
             if ( Counter == FPGA_CUTS_MAX_COMPUTE )
diff --git a/src/map/fpga/fpgaCutUtils.c b/src/map/fpga/fpgaCutUtils.c
index e60a1dee..0f003ee7 100644
--- a/src/map/fpga/fpgaCutUtils.c
+++ b/src/map/fpga/fpgaCutUtils.c
@@ -142,7 +142,7 @@ Fpga_Cut_t * Fpga_CutCreateSimple( Fpga_Man_t * p, Fpga_Node_t * pNode )
 ***********************************************************************/
 float Fpga_CutGetRootArea( Fpga_Man_t * p, Fpga_Cut_t * pCut )
 {
-    return p->pLutLib->pLutAreas[pCut->nLeaves];
+    return p->pLutLib->pLutAreas[(int)pCut->nLeaves];
 }
 
 /**Function*************************************************************
@@ -158,7 +158,8 @@ float Fpga_CutGetRootArea( Fpga_Man_t * p, Fpga_Cut_t * pCut )
 ***********************************************************************/
 Fpga_Cut_t * Fpga_CutListAppend( Fpga_Cut_t * pSetAll, Fpga_Cut_t * pSets )
 {
-    Fpga_Cut_t * pPrev, * pTemp;
+    Fpga_Cut_t * pPrev = NULL; // Suppress "might be used uninitialized"
+    Fpga_Cut_t * pTemp;
     if ( pSetAll == NULL )
         return pSets;
     if ( pSets == NULL )
@@ -277,7 +278,7 @@ void Fpga_CutGetParameters( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
     Fpga_Cut_t * pFaninCut;
     int i;
     pCut->tArrival = -FPGA_FLOAT_LARGE;
-    pCut->aFlow    = pMan->pLutLib->pLutAreas[pCut->nLeaves];
+    pCut->aFlow    = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
     for ( i = 0; i < pCut->nLeaves; i++ )
     {
         pFaninCut = pCut->ppLeaves[i]->pCutBest;
@@ -292,7 +293,7 @@ void Fpga_CutGetParameters( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
     }
     // use the first pin to compute the delay of the LUT 
     // (this mapper does not support the variable pin delay model)
-    pCut->tArrival += pMan->pLutLib->pLutDelays[pCut->nLeaves][0];
+    pCut->tArrival += pMan->pLutLib->pLutDelays[(int)pCut->nLeaves][0];
 }
 
 
@@ -311,7 +312,7 @@ float Fpga_CutGetAreaFlow( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
 {
     Fpga_Cut_t * pCutFanin;
     int i;
-    pCut->aFlow = pMan->pLutLib->pLutAreas[pCut->nLeaves];
+    pCut->aFlow = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
     for ( i = 0; i < pCut->nLeaves; i++ )
     {
         // get the cut implementing this phase of the fanin
@@ -388,7 +389,7 @@ float Fpga_CutRef( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut, in
 //        Fpga_CutInsertFanouts( pMan, pNode, pCut );
 
     // start the area of this cut
-    aArea = pMan->pLutLib->pLutAreas[pCut->nLeaves];
+    aArea = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
     // go through the children
     for ( i = 0; i < pCut->nLeaves; i++ )
     {
@@ -425,7 +426,7 @@ float Fpga_CutDeref( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_Cut_t * pCut,
 //        Fpga_CutRemoveFanouts( pMan, pNode, pCut );
 
     // start the area of this cut
-    aArea = pMan->pLutLib->pLutAreas[pCut->nLeaves];
+    aArea = pMan->pLutLib->pLutAreas[(int)pCut->nLeaves];
     // go through the children
     for ( i = 0; i < pCut->nLeaves; i++ )
     {
diff --git a/src/map/fpga/fpgaInt.h b/src/map/fpga/fpgaInt.h
index 1e4ac1d4..a308cbb3 100644
--- a/src/map/fpga/fpgaInt.h
+++ b/src/map/fpga/fpgaInt.h
@@ -64,19 +64,19 @@
 #define FPGA_INT_LARGE            (10000000)
 
 // the macro to compute the signature
-#define FPGA_SEQ_SIGN(p)        (1 << (((unsigned)p)%31));
+#define FPGA_SEQ_SIGN(p)        (1 << (((PORT_PTRUINT_T)p)%31));
 
 // internal macros to work with cuts
-#define Fpga_CutIsComplement(p)  (((int)((unsigned long) (p) & 01)))
-#define Fpga_CutRegular(p)       ((Fpga_Cut_t *)((unsigned long)(p) & ~01)) 
-#define Fpga_CutNot(p)           ((Fpga_Cut_t *)((unsigned long)(p) ^ 01)) 
-#define Fpga_CutNotCond(p,c)     ((Fpga_Cut_t *)((unsigned long)(p) ^ (c)))
+#define Fpga_CutIsComplement(p)  (((int)((PORT_PTRUINT_T)(p) & 01)))
+#define Fpga_CutRegular(p)       ((Fpga_Cut_t *)((PORT_PTRUINT_T)(p) & ~01)) 
+#define Fpga_CutNot(p)           ((Fpga_Cut_t *)((PORT_PTRUINT_T)(p) ^ 01)) 
+#define Fpga_CutNotCond(p,c)     ((Fpga_Cut_t *)((PORT_PTRUINT_T)(p) ^ (c)))
 
 // the cut nodes
-#define Fpga_SeqIsComplement( p )      (((int)((unsigned long) (p) & 01)))
-#define Fpga_SeqRegular( p )           ((Fpga_Node_t *)((unsigned long)(p) & ~015))
-#define Fpga_SeqIndex( p )             ((((unsigned long)(p)) >> 1) & 07)
-#define Fpga_SeqIndexCreate( p, Ind )  (((unsigned long)(p)) | (1 << (((unsigned)(Ind)) & 07)))
+#define Fpga_SeqIsComplement( p )      (((int)((PORT_PTRUINT_T) (p) & 01)))
+#define Fpga_SeqRegular( p )           ((Fpga_Node_t *)((PORT_PTRUINT_T)(p) & ~015))
+#define Fpga_SeqIndex( p )             ((((PORT_PTRUINT_T)(p)) >> 1) & 07)
+#define Fpga_SeqIndexCreate( p, Ind )  (((PORT_PTRUINT_T)(p)) | (1 << (((PORT_PTRUINT_T)(Ind)) & 07)))
 
 // internal macros for referencing of nodes
 #define Fpga_NodeReadRef(p)      ((Fpga_Regular(p))->nRefs)
@@ -275,9 +275,9 @@ struct Fpga_NodeVecStruct_t_
           pFanout  = pFanout2,                                   \
           pFanout2 = Fpga_NodeReadNextFanout(pNode, pFanout) )
 
-static inline Fpga_FloatMoreThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 > Arg2 + p->fEpsilon; }
-static inline Fpga_FloatLessThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 < Arg2 - p->fEpsilon; }
-static inline Fpga_FloatEqual( Fpga_Man_t * p, float Arg1, float Arg2 )    { return Arg1 > Arg2 - p->fEpsilon && Arg1 < Arg2 + p->fEpsilon; }
+static inline int Fpga_FloatMoreThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 > Arg2 + p->fEpsilon; }
+static inline int Fpga_FloatLessThan( Fpga_Man_t * p, float Arg1, float Arg2 ) { return Arg1 < Arg2 - p->fEpsilon; }
+static inline int Fpga_FloatEqual( Fpga_Man_t * p, float Arg1, float Arg2 )    { return Arg1 > Arg2 - p->fEpsilon && Arg1 < Arg2 + p->fEpsilon; }
 
 ////////////////////////////////////////////////////////////////////////
 ///                       GLOBAL VARIABLES                           ///
diff --git a/src/map/fpga/fpgaLib.c b/src/map/fpga/fpgaLib.c
index 77fc3a6f..b9615a8c 100644
--- a/src/map/fpga/fpgaLib.c
+++ b/src/map/fpga/fpgaLib.c
@@ -91,7 +91,7 @@ Fpga_LutLib_t * Fpga_LutLibRead( char * FileName, int fVerbose )
 
         // read delays
         k = 0;
-        while ( pToken = strtok( NULL, " \t\n" ) )
+        while ( (pToken = strtok( NULL, " \t\n" )) )
             p->pLutDelays[i][k++] = (float)atof(pToken);
 
         // check for out-of-bound
@@ -141,7 +141,7 @@ Fpga_LutLib_t * Fpga_LutLibRead( char * FileName, int fVerbose )
         {
             if ( p->pLutDelays[i][0] <= 0.0 )
                 printf( "Warning: LUT %d has delay %f. Pin delays should be non-negative numbers. Technology mapping may not work correctly.\n", 
-                    k, i, p->pLutDelays[i][0] );
+                    i, p->pLutDelays[i][0] );
         }
     }
 
diff --git a/src/map/fpga/fpgaMatch.c b/src/map/fpga/fpgaMatch.c
index 73fa1258..30448750 100644
--- a/src/map/fpga/fpgaMatch.c
+++ b/src/map/fpga/fpgaMatch.c
@@ -153,10 +153,10 @@ clk = clock();
         // (2) area recovery (subsequent traversals), area-flow first, delay as a tie-breaker
         if ( (fDelayOriented && 
                (Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival) || 
-                Fpga_FloatEqual(p, pNode->pCutBest->tArrival, pCut->tArrival) && Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) )) ||
+                (Fpga_FloatEqual(p, pNode->pCutBest->tArrival, pCut->tArrival) && Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow)) )) ||
              (!fDelayOriented && 
                (Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) || 
-                Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival)))  )
+                (Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival))))  )
         {
             pNode->pCutBest = pCut;
         }
@@ -301,7 +301,7 @@ clk = clock();
         }
         // choose the best cut as follows: exact area first, delay as a tie-breaker
         if ( Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) || 
-             Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival) )
+             (Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival)) )
         {
             pNode->pCutBest = pCut;
         }
@@ -386,7 +386,7 @@ int Fpga_MappingMatchesSwitch( Fpga_Man_t * p )
 int Fpga_MatchNodeSwitch( Fpga_Man_t * p, Fpga_Node_t * pNode )
 {
     Fpga_Cut_t * pCut, * pCutBestOld;
-    float aAreaCutBest;
+    float aAreaCutBest = FPGA_FLOAT_LARGE;
     int clk;
     // make sure that at least one cut other than the trivial is present
     if ( pNode->pCuts->pNext == NULL )
@@ -422,7 +422,7 @@ clk = clock();
         }
         // choose the best cut as follows: exact area first, delay as a tie-breaker
         if ( Fpga_FloatMoreThan(p, pNode->pCutBest->aFlow, pCut->aFlow) || 
-             Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival) )
+             (Fpga_FloatEqual(p, pNode->pCutBest->aFlow, pCut->aFlow) && Fpga_FloatMoreThan(p, pNode->pCutBest->tArrival, pCut->tArrival)) )
         {
             pNode->pCutBest = pCut;
         }
diff --git a/src/map/fpga/fpgaTime.c b/src/map/fpga/fpgaTime.c
index 879cad4d..d9bf7947 100644
--- a/src/map/fpga/fpgaTime.c
+++ b/src/map/fpga/fpgaTime.c
@@ -46,7 +46,7 @@ float Fpga_TimeCutComputeArrival( Fpga_Man_t * pMan, Fpga_Cut_t * pCut )
     for ( i = 0; i < pCut->nLeaves; i++ )
         if ( tArrival < pCut->ppLeaves[i]->pCutBest->tArrival )
             tArrival = pCut->ppLeaves[i]->pCutBest->tArrival;
-    tArrival += pMan->pLutLib->pLutDelays[pCut->nLeaves][0];
+    tArrival += pMan->pLutLib->pLutDelays[(int)pCut->nLeaves][0];
     return tArrival;
 }
 
@@ -216,7 +216,7 @@ void Fpga_TimePropagateRequired( Fpga_Man_t * p, Fpga_NodeVec_t * vNodes )
         if ( !Fpga_NodeIsAnd(pNode) )
             continue;
         // get the required time for children
-        fRequired = pNode->tRequired - p->pLutLib->pLutDelays[pNode->pCutBest->nLeaves][0];
+        fRequired = pNode->tRequired - p->pLutLib->pLutDelays[(int)pNode->pCutBest->nLeaves][0];
         // update the required time of the children
         for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
         {
diff --git a/src/map/fpga/fpgaTruth.c b/src/map/fpga/fpgaTruth.c
index e3eb487f..8ffb7819 100644
--- a/src/map/fpga/fpgaTruth.c
+++ b/src/map/fpga/fpgaTruth.c
@@ -44,7 +44,7 @@ DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_
     assert( !Fpga_IsComplement(pCut) );
     // if the cut is visited, return the result
     if ( pCut->uSign )
-        return (DdNode *)pCut->uSign;
+        return (DdNode *)(PORT_PTRUINT_T)pCut->uSign;
     // compute the functions of the children
     bFunc0 = Fpga_TruthsCutBdd_rec( dd, Fpga_CutRegular(pCut->pOne), vVisited );   Cudd_Ref( bFunc0 );
     bFunc0 = Cudd_NotCond( bFunc0, Fpga_CutIsComplement(pCut->pOne) );
@@ -56,7 +56,7 @@ DdNode * Fpga_TruthsCutBdd_rec( DdManager * dd, Fpga_Cut_t * pCut, Fpga_NodeVec_
     Cudd_RecursiveDeref( dd, bFunc0 );
     Cudd_RecursiveDeref( dd, bFunc1 );
     assert( pCut->uSign == 0 );
-    pCut->uSign = (unsigned)bFunc;
+    pCut->uSign = (unsigned)(PORT_PTRUINT_T)bFunc;
     // add this cut to the visited list
     Fpga_NodeVecPush( vVisited, (Fpga_Node_t *)pCut );
     return bFunc;
@@ -81,7 +81,7 @@ void * Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut )
     assert( pCut->nLeaves > 1 );
     // set the leaf variables
     for ( i = 0; i < pCut->nLeaves; i++ )
-        pCut->ppLeaves[i]->pCuts->uSign = (unsigned)Cudd_bddIthVar( dd, i );
+        pCut->ppLeaves[i]->pCuts->uSign = (unsigned)(PORT_PTRUINT_T)Cudd_bddIthVar( dd, i );
     // recursively compute the function
     vVisited = Fpga_NodeVecAlloc( 10 );
     bFunc = Fpga_TruthsCutBdd_rec( dd, pCut, vVisited );   Cudd_Ref( bFunc );
@@ -91,7 +91,7 @@ void * Fpga_TruthsCutBdd( void * dd, Fpga_Cut_t * pCut )
     for ( i = 0; i < vVisited->nSize; i++ )
     {
         pCut = (Fpga_Cut_t *)vVisited->pArray[i];
-        Cudd_RecursiveDeref( dd, (DdNode*)pCut->uSign );
+        Cudd_RecursiveDeref( dd, (DdNode*)(PORT_PTRUINT_T)pCut->uSign );
         pCut->uSign = 0;
     }
 //    printf( "%d ", vVisited->nSize );
diff --git a/src/map/fpga/fpgaUtils.c b/src/map/fpga/fpgaUtils.c
index b951fd8f..77c2e2b0 100644
--- a/src/map/fpga/fpgaUtils.c
+++ b/src/map/fpga/fpgaUtils.c
@@ -31,7 +31,6 @@ static void  Fpga_MappingFindLatest( Fpga_Man_t * p, int * pNodes, int nNodesMax
 static void  Fpga_DfsLim_rec( Fpga_Node_t * pNode, int Level, Fpga_NodeVec_t * vNodes );
 static int   Fpga_CollectNodeTfo_rec( Fpga_Node_t * pNode, Fpga_Node_t * pPivot, Fpga_NodeVec_t * vVisited, Fpga_NodeVec_t * vTfo );
 static Fpga_NodeVec_t * Fpga_MappingOrderCosByLevel( Fpga_Man_t * pMan );
-static Fpga_Man_t * s_pMan = NULL;
 
 ////////////////////////////////////////////////////////////////////////
 ///                     FUNCTION DEFINITIONS                         ///
@@ -182,7 +181,7 @@ float Fpga_MappingArea( Fpga_Man_t * pMan )
     for ( i = 0; i < pMan->vMapping->nSize; i++ )
     {
         pNode = pMan->vMapping->pArray[i];
-        aTotal += pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
+        aTotal += pMan->pLutLib->pLutAreas[(int)pNode->pCutBest->nLeaves];
     }
     return aTotal;
 }
@@ -217,7 +216,7 @@ float Fpga_MappingArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fpga_NodeVec
     // mark the node as visited
     pNode->fMark0 = 1;
     // add the node to the list
-    aArea += pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
+    aArea += pMan->pLutLib->pLutAreas[(int)pNode->pCutBest->nLeaves];
     // add the node to the list
     Fpga_NodeVecPush( vNodes, pNode );
     return aArea;
@@ -276,7 +275,7 @@ float Fpga_MappingSetRefsAndArea_rec( Fpga_Man_t * pMan, Fpga_Node_t * pNode, Fp
     pNode->pData0 = (char *)ppStore[pNode->Level]; 
     ppStore[pNode->Level] = pNode;
     // visit the transitive fanin of the selected cut
-    aArea = pMan->pLutLib->pLutAreas[pNode->pCutBest->nLeaves];
+    aArea = pMan->pLutLib->pLutAreas[(int)pNode->pCutBest->nLeaves];
     for ( i = 0; i < pNode->pCutBest->nLeaves; i++ )
         aArea += Fpga_MappingSetRefsAndArea_rec( pMan, pNode->pCutBest->ppLeaves[i], ppStore );
     return aArea;
diff --git a/src/map/fpga/fpgaVec.c b/src/map/fpga/fpgaVec.c
index 70a4a7ac..79b6b43d 100644
--- a/src/map/fpga/fpgaVec.c
+++ b/src/map/fpga/fpgaVec.c
@@ -370,8 +370,8 @@ void Fpga_NodeVecPushOrder( Fpga_NodeVec_t * vNodes, Fpga_Node_t * pNode, int fI
     {
         pNode1 = vNodes->pArray[i  ];
         pNode2 = vNodes->pArray[i-1];
-        if ( fIncreasing && pNode1->pCutBest->tArrival >= pNode2->pCutBest->tArrival ||
-            !fIncreasing && pNode1->pCutBest->tArrival <= pNode2->pCutBest->tArrival )
+        if (( fIncreasing && pNode1->pCutBest->tArrival >= pNode2->pCutBest->tArrival) ||
+            (!fIncreasing && pNode1->pCutBest->tArrival <= pNode2->pCutBest->tArrival) )
             break;
         vNodes->pArray[i  ] = pNode2;
         vNodes->pArray[i-1] = pNode1;