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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2016-02-01 15:56:53 -0800 |
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| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2016-02-01 15:56:53 -0800 |
| commit | 02725c9eca9512572013d54286cd63cd52bed9ea (patch) | |
| tree | 9fdd41d65c0218204e7a130e42bd745dad5b9f4e /src/demo.c | |
| parent | 81dade194e30b6fa5f98352a76459c062d27e66f (diff) | |
| download | abc-02725c9eca9512572013d54286cd63cd52bed9ea.tar.gz abc-02725c9eca9512572013d54286cd63cd52bed9ea.tar.bz2 abc-02725c9eca9512572013d54286cd63cd52bed9ea.zip | |
An add-on to write Verilog for circuits mapped into simple gates.
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