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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2021-04-26 18:52:44 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2021-04-26 18:52:44 -0700 |
| commit | de71e5f61038748b59bcbb2bf6f0c8666b45190a (patch) | |
| tree | 40d41d6d824d1f1dd22da69ea14b5c05bb5ace84 /src/base | |
| parent | 75981f7feebc4065980f99551654ac101edb4afa (diff) | |
| download | abc-de71e5f61038748b59bcbb2bf6f0c8666b45190a.tar.gz abc-de71e5f61038748b59bcbb2bf6f0c8666b45190a.tar.bz2 abc-de71e5f61038748b59bcbb2bf6f0c8666b45190a.zip | |
Passing node labels.
Diffstat (limited to 'src/base')
| -rw-r--r-- | src/base/abc/abcObj.c | 1 | ||||
| -rw-r--r-- | src/base/abci/abcDar.c | 1 | ||||
| -rw-r--r-- | src/base/io/ioWriteVerilog.c | 8 |
3 files changed, 10 insertions, 0 deletions
diff --git a/src/base/abc/abcObj.c b/src/base/abc/abcObj.c index 533f1f73..65ea91dc 100644 --- a/src/base/abc/abcObj.c +++ b/src/base/abc/abcObj.c @@ -393,6 +393,7 @@ Abc_Obj_t * Abc_NtkDupObj( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pObj, int fCopyName } else if ( Abc_ObjIsLatch(pObj) ) // copy the reset value pObjNew->pData = pObj->pData; + pObjNew->fPersist = pObj->fPersist; // transfer HAIG // pObjNew->pEquiv = pObj->pEquiv; // remember the new node in the old node diff --git a/src/base/abci/abcDar.c b/src/base/abci/abcDar.c index 56eb139a..8911780d 100644 --- a/src/base/abci/abcDar.c +++ b/src/base/abci/abcDar.c @@ -858,6 +858,7 @@ Abc_Ntk_t * Abc_NtkFromMappedGia( Gia_Man_t * p, int fFindEnables, int fUseBuffs Gia_LutForEachFanin( p, i, iFan, k ) Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ManObj(p, iFan))) ); pObjNew->pData = Abc_ObjHopFromGia( (Hop_Man_t *)pNtkNew->pManFunc, p, i, vReflect ); + pObjNew->fPersist = Gia_ObjLutIsMux(p, i); pObj->Value = Abc_ObjId( pObjNew ); } Vec_PtrFree( vReflect ); diff --git a/src/base/io/ioWriteVerilog.c b/src/base/io/ioWriteVerilog.c index ad49e93a..4c55b599 100644 --- a/src/base/io/ioWriteVerilog.c +++ b/src/base/io/ioWriteVerilog.c @@ -567,6 +567,14 @@ void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk, int fOnlyAnds ) Hop_IthVar((Hop_Man_t *)pNtk->pManFunc, k)->pData = Extra_UtilStrsav(Io_WriteVerilogGetName(Abc_ObjName(pFanin))); // write the formula Hop_ObjPrintVerilog( pFile, pFunc, vLevels, 0, fOnlyAnds ); + if ( pObj->fPersist ) + { + Abc_Obj_t * pFan0 = Abc_ObjFanin0(Abc_ObjFanin(pObj, 0)); + Abc_Obj_t * pFan1 = Abc_ObjFanin0(Abc_ObjFanin(pObj, 1)); + int Cond = Abc_ObjIsNode(pFan0) && Abc_ObjIsNode(pFan1) && !pFan0->fPersist && !pFan1->fPersist; + fprintf( pFile, "; // MUXF7 %s\n", Cond ? "":"to be legalized" ); + } + else fprintf( pFile, ";\n" ); // clear the input names Abc_ObjForEachFanin( pObj, pFanin, k ) |