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author | Alan Mishchenko <alanmi@berkeley.edu> | 2014-04-09 12:51:08 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2014-04-09 12:51:08 -0700 |
commit | 46ab68ba17a6b50c5fd2a4c0566dc3e805bc11bd (patch) | |
tree | b6e04e1af0041f482b6085770154f2e0b6d7d48e /src/base/main/mainInt.h | |
parent | b94b810297bb95ef47190e1274f591cd2c78352d (diff) | |
download | abc-46ab68ba17a6b50c5fd2a4c0566dc3e805bc11bd.tar.gz abc-46ab68ba17a6b50c5fd2a4c0566dc3e805bc11bd.tar.bz2 abc-46ab68ba17a6b50c5fd2a4c0566dc3e805bc11bd.zip |
Cleanup and bug fixing in hierarchy handling.
Diffstat (limited to 'src/base/main/mainInt.h')
-rw-r--r-- | src/base/main/mainInt.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/base/main/mainInt.h b/src/base/main/mainInt.h index c5b7de58..73844c2b 100644 --- a/src/base/main/mainInt.h +++ b/src/base/main/mainInt.h @@ -92,7 +92,6 @@ struct Abc_Frame_t_ void * pLibGen; // the current genlib void * pLibGen2; // the current genlib void * pLibSuper; // the current supergate library - void * pLibVer; // the current Verilog library void * pLibScl; // the current Liberty library // timing constraints char * pDrivingCell; // name of the driving cell |