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author | Alan Mishchenko <alanmi@berkeley.edu> | 2006-08-22 08:01:00 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2006-08-22 08:01:00 -0700 |
commit | 956842d9cc321eee3907889b820132e6e2b5ec62 (patch) | |
tree | 67a2a804c594eabc54d290cbd607a6ae65e583f6 /src/base/io | |
parent | 2fd3c1a25bb7a7ce334d2de5bac96bce446855d8 (diff) | |
download | abc-956842d9cc321eee3907889b820132e6e2b5ec62.tar.gz abc-956842d9cc321eee3907889b820132e6e2b5ec62.tar.bz2 abc-956842d9cc321eee3907889b820132e6e2b5ec62.zip |
Version abc60822
Diffstat (limited to 'src/base/io')
-rw-r--r-- | src/base/io/io.c | 89 | ||||
-rw-r--r-- | src/base/io/ioReadBaf.c | 2 | ||||
-rw-r--r-- | src/base/io/ioWriteDot.c | 2 | ||||
-rw-r--r-- | src/base/io/ioWriteList.c | 4 | ||||
-rw-r--r-- | src/base/io/ioWriteVerAux.c | 1 |
5 files changed, 26 insertions, 72 deletions
diff --git a/src/base/io/io.c b/src/base/io/io.c index 6da1f4d8..0cc3c7d9 100644 --- a/src/base/io/io.c +++ b/src/base/io/io.c @@ -667,13 +667,13 @@ usage: ***********************************************************************/ int IoCommandReadVer( Abc_Frame_t * pAbc, int argc, char ** argv ) { - Abc_Ntk_t * pNtk, * pTemp; - st_table * tDesign; + Abc_Ntk_t * pNtk; + Abc_Lib_t * pDesign; char * FileName; FILE * pFile; int fCheck; int c; - extern st_table * Ver_ParseFile( char * pFileName, st_table * pGateLib, int fCheck ); + extern Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck ); fCheck = 1; Extra_UtilGetoptReset(); @@ -709,41 +709,21 @@ int IoCommandReadVer( Abc_Frame_t * pAbc, int argc, char ** argv ) fclose( pFile ); // set the new network - tDesign = Ver_ParseFile( FileName, Abc_FrameReadLibVer(), fCheck ); - if ( tDesign == NULL ) + pDesign = Ver_ParseFile( FileName, Abc_FrameReadLibVer(), fCheck ); + if ( pDesign == NULL ) { fprintf( pAbc->Err, "Reading network from the verilog file has failed.\n" ); return 1; } - - if ( st_count(tDesign) == 1 ) - { - st_generator * gen; - char * pName; - // find the network - st_foreach_item( tDesign, gen, (char**)&pName, (char**)&pNtk ) - { - st_free_gen(gen); - break; - } - st_free_table( tDesign ); - - // convert it into a logic network - pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); - Abc_NtkDelete( pTemp ); - if ( pNtk == NULL ) - { - fprintf( pAbc->Err, "Converting to logic network after reading has failed.\n" ); - return 1; - } - // replace the current network - Abc_FrameReplaceCurrentNetwork( pAbc, pNtk ); - } - else + // derive root design + pNtk = Abc_LibDeriveRoot( pDesign ); + if ( pNtk == NULL ) { - printf( "The design includes more than one module and is currently not used.\n" ); + fprintf( pAbc->Err, "Deriving root module has failed.\n" ); + return 1; } - + // replace the current network + Abc_FrameReplaceCurrentNetwork( pAbc, pNtk ); return 0; usage: @@ -768,14 +748,12 @@ usage: ***********************************************************************/ int IoCommandReadVerLib( Abc_Frame_t * pAbc, int argc, char ** argv ) { - Abc_Ntk_t * pNtk, * pTemp; - st_table * tDesign; + Abc_Lib_t * pLibrary; char * FileName; FILE * pFile; int fCheck; int c; - extern st_table * Ver_ParseFile( char * pFileName, st_table * pGateLib, int fCheck ); - extern void Ver_ParseFreeLibrary( st_table * pLibVer ); + extern Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck ); fCheck = 1; Extra_UtilGetoptReset(); @@ -811,41 +789,18 @@ int IoCommandReadVerLib( Abc_Frame_t * pAbc, int argc, char ** argv ) fclose( pFile ); // set the new network - tDesign = Ver_ParseFile( FileName, NULL, fCheck ); - if ( tDesign == NULL ) + pLibrary = Ver_ParseFile( FileName, NULL, fCheck ); + if ( pLibrary == NULL ) { fprintf( pAbc->Err, "Reading library from the verilog file has failed.\n" ); return 1; } - printf( "The library contains %d gates.\n", st_count(tDesign) ); - - // convert gates into AIGs - { - st_table * tLibrary; - st_generator * gen; - char * pName; - // transform the gates into the library AIGs - tLibrary = st_init_table( strcmp, st_strhash ); - st_foreach_item( tDesign, gen, (char**)&pName, (char**)&pNtk ) - { - // convert the netlist into SOP logic network - pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); - Abc_NtkDelete( pTemp ); - // perform structural hashing - pNtk = Abc_NtkStrash( pTemp = pNtk, 0, 1 ); - Abc_NtkDelete( pTemp ); - // insert the new network into the new library - st_insert( tLibrary, pNtk->pName, (char *)pNtk ); - } - st_free_table( tDesign ); - - // free old library - if ( Abc_FrameReadLibVer() ) - Ver_ParseFreeLibrary( Abc_FrameReadLibVer() ); - // read new library - Abc_FrameSetLibVer( tLibrary ); - } - + printf( "The library contains %d gates.\n", st_count(pLibrary->tModules) ); + // free old library + if ( Abc_FrameReadLibVer() ) + Abc_LibFree( Abc_FrameReadLibVer() ); + // read new library + Abc_FrameSetLibVer( pLibrary ); return 0; usage: diff --git a/src/base/io/ioReadBaf.c b/src/base/io/ioReadBaf.c index 8f4a8ec4..83b642a0 100644 --- a/src/base/io/ioReadBaf.c +++ b/src/base/io/ioReadBaf.c @@ -79,7 +79,7 @@ Abc_Ntk_t * Io_ReadBaf( char * pFileName, int fCheck ) // prepare the array of nodes vNodes = Vec_PtrAlloc( 1 + nInputs + nLatches + nAnds ); - Vec_PtrPush( vNodes, Abc_NtkConst1(pNtkNew) ); + Vec_PtrPush( vNodes, Abc_AigConst1(pNtkNew) ); // create the PIs for ( i = 0; i < nInputs; i++ ) diff --git a/src/base/io/ioWriteDot.c b/src/base/io/ioWriteDot.c index ed6acb24..8ce837e2 100644 --- a/src/base/io/ioWriteDot.c +++ b/src/base/io/ioWriteDot.c @@ -415,7 +415,7 @@ void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesSho { if ( !Abc_NtkBddToSop(pNtk, 0) ) { - printf( "Converting to SOPs has failed.\n" ); + printf( "Io_WriteDotNtk(): Converting to SOPs has failed.\n" ); return; } } diff --git a/src/base/io/ioWriteList.c b/src/base/io/ioWriteList.c index f0981a8e..c2bea884 100644 --- a/src/base/io/ioWriteList.c +++ b/src/base/io/ioWriteList.c @@ -117,8 +117,8 @@ void Io_WriteList( Abc_Ntk_t * pNtk, char * pFileName, int fUseHost ) fprintf( pFile, "# written by ABC on %s\n", Extra_TimeStamp() ); // write the constant node - if ( Abc_ObjFanoutNum( Abc_NtkConst1(pNtk) ) > 0 ) - Io_WriteListEdge( pFile, Abc_NtkConst1(pNtk) ); + if ( Abc_ObjFanoutNum( Abc_AigConst1(pNtk) ) > 0 ) + Io_WriteListEdge( pFile, Abc_AigConst1(pNtk) ); // write the PI edges Abc_NtkForEachPi( pNtk, pObj, i ) diff --git a/src/base/io/ioWriteVerAux.c b/src/base/io/ioWriteVerAux.c index f0814c84..9fd71750 100644 --- a/src/base/io/ioWriteVerAux.c +++ b/src/base/io/ioWriteVerAux.c @@ -265,7 +265,6 @@ void Io_WriteVerilogAuxNodes( FILE * pFile, Abc_Ntk_t * pNtk ) Abc_Obj_t * pObj; int i, nCubes, nFanins, Counter, nDigits, fPadZeros; char * pName; - extern int Abc_SopIsExorType( char * pSop ); nDigits = Extra_Base10Log( Abc_NtkNodeNum(pNtk) ); Counter = 1; |