diff options
author | Alan Mishchenko <alanmi@berkeley.edu> | 2005-08-12 08:01:00 -0700 |
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committer | Alan Mishchenko <alanmi@berkeley.edu> | 2005-08-12 08:01:00 -0700 |
commit | 80983617b3f2843a176c8de1fee84de17a507fe9 (patch) | |
tree | b86f3532e055c1fc6492a5a361404f7b75964c77 /src/base/io | |
parent | 273ba03041ee4cac93385f180d1397b49f8094ca (diff) | |
download | abc-80983617b3f2843a176c8de1fee84de17a507fe9.tar.gz abc-80983617b3f2843a176c8de1fee84de17a507fe9.tar.bz2 abc-80983617b3f2843a176c8de1fee84de17a507fe9.zip |
Version abc50812
Diffstat (limited to 'src/base/io')
-rw-r--r-- | src/base/io/io.c | 161 | ||||
-rw-r--r-- | src/base/io/io.h | 16 | ||||
-rw-r--r-- | src/base/io/ioRead.c | 2 | ||||
-rw-r--r-- | src/base/io/ioReadBench.c | 124 | ||||
-rw-r--r-- | src/base/io/ioReadBlif.c | 217 | ||||
-rw-r--r-- | src/base/io/ioReadPla.c | 39 | ||||
-rw-r--r-- | src/base/io/ioReadVerilog.c | 219 | ||||
-rw-r--r-- | src/base/io/ioUtil.c | 201 | ||||
-rw-r--r-- | src/base/io/ioWriteBench.c | 129 | ||||
-rw-r--r-- | src/base/io/ioWriteBlif.c | 204 | ||||
-rw-r--r-- | src/base/io/ioWriteBlifLogic.c | 402 | ||||
-rw-r--r-- | src/base/io/ioWriteGate.c | 263 | ||||
-rw-r--r-- | src/base/io/ioWritePla.c | 17 | ||||
-rw-r--r-- | src/base/io/module.make | 3 |
14 files changed, 684 insertions, 1313 deletions
diff --git a/src/base/io/io.c b/src/base/io/io.c index 5e72d307..b1f44abd 100644 --- a/src/base/io/io.c +++ b/src/base/io/io.c @@ -32,7 +32,6 @@ static int IoCommandReadVerilog ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandReadPla ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteBlif ( Abc_Frame_t * pAbc, int argc, char **argv ); -static int IoCommandWriteGate ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteBench ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWriteCnf ( Abc_Frame_t * pAbc, int argc, char **argv ); static int IoCommandWritePla ( Abc_Frame_t * pAbc, int argc, char **argv ); @@ -61,7 +60,6 @@ void Io_Init( Abc_Frame_t * pAbc ) Cmd_CommandAdd( pAbc, "I/O", "read_pla", IoCommandReadPla, 1 ); Cmd_CommandAdd( pAbc, "I/O", "write_blif", IoCommandWriteBlif, 0 ); - Cmd_CommandAdd( pAbc, "I/O", "write_gate", IoCommandWriteGate, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write_bench", IoCommandWriteBench, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write_cnf", IoCommandWriteCnf, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write_pla", IoCommandWritePla, 0 ); @@ -214,7 +212,7 @@ int IoCommandReadBlif( Abc_Frame_t * pAbc, int argc, char ** argv ) return 1; } - pNtk = Abc_NtkLogic( pTemp = pNtk ); + pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); Abc_NtkDelete( pTemp ); if ( pNtk == NULL ) { @@ -294,7 +292,7 @@ int IoCommandReadBench( Abc_Frame_t * pAbc, int argc, char ** argv ) return 1; } - pNtk = Abc_NtkLogic( pTemp = pNtk ); + pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); Abc_NtkDelete( pTemp ); if ( pNtk == NULL ) { @@ -374,7 +372,7 @@ int IoCommandReadVerilog( Abc_Frame_t * pAbc, int argc, char ** argv ) return 1; } - pNtk = Abc_NtkLogic( pTemp = pNtk ); + pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); Abc_NtkDelete( pTemp ); if ( pNtk == NULL ) { @@ -454,7 +452,7 @@ int IoCommandReadPla( Abc_Frame_t * pAbc, int argc, char ** argv ) return 1; } - pNtk = Abc_NtkLogic( pTemp = pNtk ); + pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); Abc_NtkDelete( pTemp ); if ( pNtk == NULL ) { @@ -488,8 +486,8 @@ usage: ***********************************************************************/ int IoCommandWriteBlif( Abc_Frame_t * pAbc, int argc, char **argv ) { + Abc_Ntk_t * pNtk; char * FileName; - int fMadeComb; int fWriteLatches; int c; @@ -509,7 +507,8 @@ int IoCommandWriteBlif( Abc_Frame_t * pAbc, int argc, char **argv ) } } - if ( pAbc->pNtkCur == NULL ) + pNtk = pAbc->pNtkCur; + if ( pNtk == NULL ) { fprintf( pAbc->Out, "Empty network.\n" ); return 0; @@ -519,38 +518,15 @@ int IoCommandWriteBlif( Abc_Frame_t * pAbc, int argc, char **argv ) { goto usage; } - - if ( Abc_NtkIsLogicMap(pAbc->pNtkCur) ) - { - fprintf( pAbc->Out, "Use \"write_gate\" or unmap the network (\"unmap\").\n" ); - return 1; - } - - // get the input file name FileName = argv[util_optind]; - // write the file - if ( Abc_NtkIsNetlist(pAbc->pNtkCur) ) - { - if ( !fWriteLatches ) - fMadeComb = Abc_NtkMakeComb( pAbc->pNtkCur ); - Io_WriteBlif( pAbc->pNtkCur, FileName ); - if ( !fWriteLatches && fMadeComb ) - Abc_NtkMakeSeq( pAbc->pNtkCur ); - } - else if ( Abc_NtkIsLogicSop(pAbc->pNtkCur) || Abc_NtkIsAig(pAbc->pNtkCur) ) - { - Io_WriteBlifLogic( pAbc->pNtkCur, FileName, fWriteLatches ); - } - else if ( Abc_NtkIsLogicBdd(pAbc->pNtkCur) ) - { -// printf( "Converting node functions from BDD to SOP.\n" ); - Abc_NtkBddToSop(pAbc->pNtkCur); - Io_WriteBlifLogic( pAbc->pNtkCur, FileName, fWriteLatches ); - } - else + + // check the network type + if ( !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsAig(pNtk) ) { - assert( 0 ); + fprintf( pAbc->Out, "Currently can only write logic networks and AIGs.\n" ); + return 0; } + Io_WriteBlifLogic( pNtk, FileName, fWriteLatches ); return 0; usage: @@ -573,14 +549,13 @@ usage: SeeAlso [] ***********************************************************************/ -int IoCommandWriteGate( Abc_Frame_t * pAbc, int argc, char **argv ) +int IoCommandWriteBench( Abc_Frame_t * pAbc, int argc, char **argv ) { - Abc_Ntk_t * pNtk; + Abc_Ntk_t * pNtk, * pNtkTemp; char * FileName; int fWriteLatches; int c; - pNtk = pAbc->pNtkCur; fWriteLatches = 1; util_getopt_reset(); while ( ( c = util_getopt( argc, argv, "lh" ) ) != EOF ) @@ -597,84 +572,19 @@ int IoCommandWriteGate( Abc_Frame_t * pAbc, int argc, char **argv ) } } + pNtk = pAbc->pNtkCur; if ( pNtk == NULL ) { fprintf( pAbc->Out, "Empty network.\n" ); return 0; } - if ( !Abc_NtkIsLogicMap(pNtk) ) - { - fprintf( pAbc->Out, "The network is not mapped.\n" ); - return 0; - } -/* - if ( Abc_NtkLatchNum(pNtk) > 0 ) - { - fprintf( pAbc->Out, "The network has latches.\n" ); - return 0; - } -*/ if ( argc != util_optind + 1 ) { goto usage; } - // get the input file name FileName = argv[util_optind]; - // write the file - Io_WriteGate( pNtk, FileName ); - return 0; - -usage: - fprintf( pAbc->Err, "usage: write_gate [-h] <file>\n" ); - fprintf( pAbc->Err, "\t write the network into a mapped BLIF file (.gate ...)\n" ); -// fprintf( pAbc->Err, "\t-l : toggle writing latches [default = %s]\n", fWriteLatches? "yes":"no" ); - fprintf( pAbc->Err, "\t-h : print the help massage\n" ); - fprintf( pAbc->Err, "\tfile : the name of the file to write\n" ); - return 1; -} - -/**Function************************************************************* - - Synopsis [] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int IoCommandWriteBench( Abc_Frame_t * pAbc, int argc, char **argv ) -{ - Abc_Ntk_t * pNtk; - char * FileName; - int fWriteLatches; - int c; - - pNtk = pAbc->pNtkCur; - fWriteLatches = 1; - util_getopt_reset(); - while ( ( c = util_getopt( argc, argv, "lh" ) ) != EOF ) - { - switch ( c ) - { - case 'l': - fWriteLatches ^= 1; - break; - case 'h': - goto usage; - default: - goto usage; - } - } - - if ( pNtk == NULL ) - { - fprintf( pAbc->Out, "Empty network.\n" ); - return 0; - } if ( !Abc_NtkIsAig(pNtk) ) { @@ -682,15 +592,15 @@ int IoCommandWriteBench( Abc_Frame_t * pAbc, int argc, char **argv ) return 0; } - if ( argc != util_optind + 1 ) + // derive the netlist + pNtkTemp = Abc_NtkLogicToNetlistBench(pNtk); + if ( pNtkTemp == NULL ) { - goto usage; + fprintf( pAbc->Out, "Writing BENCH has failed.\n" ); + return 0; } - - // get the input file name - FileName = argv[util_optind]; - // write the file - Io_WriteBench( pNtk, FileName ); + Io_WriteBench( pNtkTemp, FileName ); + Abc_NtkDelete( pNtkTemp ); return 0; usage: @@ -772,6 +682,7 @@ usage: ***********************************************************************/ int IoCommandWritePla( Abc_Frame_t * pAbc, int argc, char **argv ) { + Abc_Ntk_t * pNtk, * pNtkTemp; char * FileName; int c; @@ -787,31 +698,41 @@ int IoCommandWritePla( Abc_Frame_t * pAbc, int argc, char **argv ) } } - if ( pAbc->pNtkCur == NULL ) + pNtk = pAbc->pNtkCur; + if ( pNtk == NULL ) { fprintf( pAbc->Out, "Empty network.\n" ); return 0; } - if ( Abc_NtkGetLevelNum(pAbc->pNtkCur) > 1 ) + if ( Abc_NtkGetLevelNum(pNtk) > 1 ) { fprintf( pAbc->Out, "PLA writing is available for collapsed networks.\n" ); return 0; } + if ( Abc_NtkLatchNum(pNtk) > 0 ) + { + fprintf( pAbc->Out, "Latches are writed at PI/PO pairs in the PLA file.\n" ); + return 0; + } + if ( argc != util_optind + 1 ) { goto usage; } - // get the input file name FileName = argv[util_optind]; - // write the file - if ( !Io_WritePla( pAbc->pNtkCur, FileName ) ) + + // derive the netlist + pNtkTemp = Abc_NtkLogicToNetlist(pNtk); + if ( pNtkTemp == NULL ) { - printf( "Writing PLA has failed.\n" ); - return 1; + fprintf( pAbc->Out, "Writing PLA has failed.\n" ); + return 0; } + Io_WritePla( pNtkTemp, FileName ); + Abc_NtkDelete( pNtkTemp ); return 0; usage: diff --git a/src/base/io/io.h b/src/base/io/io.h index d4cea912..2465fa9f 100644 --- a/src/base/io/io.h +++ b/src/base/io/io.h @@ -53,18 +53,22 @@ extern Abc_Ntk_t * Io_ReadBlif( char * pFileName, int fCheck ); extern Abc_Ntk_t * Io_ReadBench( char * pFileName, int fCheck ); /*=== abcReadVerilog.c ==========================================================*/ extern Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ); -extern void Io_ReadSetNonDrivenNets( Abc_Ntk_t * pNet ); /*=== abcReadPla.c ==========================================================*/ extern Abc_Ntk_t * Io_ReadPla( char * pFileName, int fCheck ); +/*=== abcUtil.c ==========================================================*/ +extern Abc_Obj_t * Io_ReadCreatePi( Abc_Ntk_t * pNtk, char * pName ); +extern Abc_Obj_t * Io_ReadCreatePo( Abc_Ntk_t * pNtk, char * pName ); +extern Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO ); +extern Abc_Obj_t * Io_ReadCreateNode( Abc_Ntk_t * pNtk, char * pNameOut, char * pNamesIn[], int nInputs ); +extern Abc_Obj_t * Io_ReadCreateConst( Abc_Ntk_t * pNtk, char * pName, bool fConst1 ); +extern Abc_Obj_t * Io_ReadCreateInv( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut ); +extern Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut ); /*=== abcWriteBlif.c ==========================================================*/ -extern void Io_WriteBlif( Abc_Ntk_t * pNtk, char * pFileName ); -extern void Io_WriteTimingInfo( FILE * pFile, Abc_Ntk_t * pNtk ); -/*=== abcWriteBlifLogic.c ==========================================================*/ +extern void Io_WriteBlif( Abc_Ntk_t * pNtk, char * pFileName, int fWriteLatches ); extern void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * pFileName, int fWriteLatches ); +extern void Io_WriteTimingInfo( FILE * pFile, Abc_Ntk_t * pNtk ); /*=== abcWriteBench.c ==========================================================*/ extern int Io_WriteBench( Abc_Ntk_t * pNtk, char * FileName ); -/*=== abcWriteGate.c ==========================================================*/ -extern int Io_WriteGate( Abc_Ntk_t * pNtk, char * FileName ); /*=== abcWriteCnf.c ==========================================================*/ extern int Io_WriteCnf( Abc_Ntk_t * pNtk, char * FileName ); /*=== abcWritePla.c ==========================================================*/ diff --git a/src/base/io/ioRead.c b/src/base/io/ioRead.c index aef5d57a..8a0c11a5 100644 --- a/src/base/io/ioRead.c +++ b/src/base/io/ioRead.c @@ -58,7 +58,7 @@ Abc_Ntk_t * Io_Read( char * pFileName, int fCheck ) } if ( pNtk == NULL ) return NULL; - pNtk = Abc_NtkLogic( pTemp = pNtk ); + pNtk = Abc_NtkNetlistToLogic( pTemp = pNtk ); Abc_NtkDelete( pTemp ); if ( pNtk == NULL ) { diff --git a/src/base/io/ioReadBench.c b/src/base/io/ioReadBench.c index 0660adc7..9667fcc7 100644 --- a/src/base/io/ioReadBench.c +++ b/src/base/io/ioReadBench.c @@ -82,17 +82,13 @@ Abc_Ntk_t * Io_ReadBenchNetwork( Extra_FileReader_t * p ) ProgressBar * pProgress; Vec_Ptr_t * vTokens; Abc_Ntk_t * pNtk; - Abc_Obj_t * pNet, * pLatch, * pNode; + Abc_Obj_t * pNet, * pNode; Vec_Str_t * vString; - char * pType; - int SymbolIn, SymbolOut, i, iLine; + char * pType, ** ppNames; + int iLine, nNames; // allocate the empty network - pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST ); - - // set the specs - pNtk->pName = util_strsav( Extra_FileReaderGetFileName(p) ); - pNtk->pSpec = util_strsav( Extra_FileReaderGetFileName(p) ); + pNtk = Abc_NtkStartRead( Extra_FileReaderGetFileName(p) ); // go through the lines of the file vString = Vec_StrAlloc( 100 ); @@ -110,115 +106,61 @@ Abc_Ntk_t * Io_ReadBenchNetwork( Extra_FileReader_t * p ) // get the type of the line if ( strncmp( vTokens->pArray[0], "INPUT", 5 ) == 0 ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[1] ); - if ( Abc_ObjIsPi(pNet) ) - printf( "Warning: PI net \"%s\" appears twice in the list.\n", vTokens->pArray[1] ); - else - Abc_NtkMarkNetPi( pNet ); - } + Io_ReadCreatePi( pNtk, vTokens->pArray[1] ); else if ( strncmp( vTokens->pArray[0], "OUTPUT", 5 ) == 0 ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[1] ); - if ( Abc_ObjIsPo(pNet) ) - printf( "Warning: PO net \"%s\" appears twice in the list.\n", vTokens->pArray[1] ); - else - Abc_NtkMarkNetPo( pNet ); - } + Io_ReadCreatePo( pNtk, vTokens->pArray[1] ); else { // get the node name and the node type pType = vTokens->pArray[1]; if ( strcmp(pType, "DFF") == 0 ) - { - // create a new node and add it to the network - pLatch = Abc_NtkCreateLatch( pNtk ); - // create the LO (PI) - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[0] ); - Abc_ObjAddFanin( pNet, pLatch ); - Abc_ObjSetSubtype( pNet, ABC_OBJ_SUBTYPE_LO ); - // save the LI (PO) - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[2] ); - Abc_ObjAddFanin( pLatch, pNet ); - Abc_ObjSetSubtype( pNet, ABC_OBJ_SUBTYPE_LI ); - } + Io_ReadCreateLatch( pNtk, vTokens->pArray[2], vTokens->pArray[0] ); else { // create a new node and add it to the network - pNode = Abc_NtkCreateNode( pNtk ); - // get the input symbol to be inserted - if ( !strncmp(pType, "BUF", 3) || !strcmp(pType, "AND") || !strcmp(pType, "NAND") ) - SymbolIn = '1'; - else if ( !strncmp(pType, "NOT", 3) || !strcmp(pType, "OR") || !strcmp(pType, "NOR") ) - SymbolIn = '0'; - else if ( !strcmp(pType, "XOR") || !strcmp(pType, "NXOR") ) - SymbolIn = '*'; - else + ppNames = (char **)vTokens->pArray + 2; + nNames = vTokens->nSize - 2; + pNode = Io_ReadCreateNode( pNtk, vTokens->pArray[0], ppNames, nNames ); + // assign the cover + if ( strcmp(pType, "AND") == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateAnd(pNtk->pManFunc, nNames) ); + else if ( strcmp(pType, "OR") == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateOr(pNtk->pManFunc, nNames, NULL) ); + else if ( strcmp(pType, "NAND") == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateNand(pNtk->pManFunc, nNames) ); + else if ( strcmp(pType, "NOR") == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateNor(pNtk->pManFunc, nNames) ); + else if ( strcmp(pType, "XOR") == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateXor(pNtk->pManFunc, nNames) ); + else if ( strcmp(pType, "NXOR") == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateNxor(pNtk->pManFunc, nNames) ); + else if ( strncmp(pType, "BUF", 3) == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateBuf(pNtk->pManFunc) ); + else if ( strcmp(pType, "NOT") == 0 ) + Abc_ObjSetData( pNode, Abc_SopCreateInv(pNtk->pManFunc) ); + else { printf( "Cannot determine gate type \"%s\" in line %d.\n", pType, Extra_FileReaderGetLineNumber(p, 0) ); Abc_NtkDelete( pNtk ); return NULL; } - // get the output symbol - if ( !strcmp(pType, "NAND") || !strcmp(pType, "OR") || !strcmp(pType, "NXOR") ) - SymbolOut = '0'; - else - SymbolOut = '1'; - - // add the fanout net - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[0] ); - Abc_ObjAddFanin( pNet, pNode ); - // add the fanin nets - for ( i = 2; i < vTokens->nSize; i++ ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[i] ); - Abc_ObjAddFanin( pNode, pNet ); - } - if ( SymbolIn != '*' ) - { - // fill in the function - Vec_StrFill( vString, vTokens->nSize - 2, (char)SymbolIn ); - Vec_StrPush( vString, ' ' ); - Vec_StrPush( vString, (char)SymbolOut ); - Vec_StrPush( vString, '\n' ); - Vec_StrPush( vString, '\0' ); - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, vString->pArray) ); - } - else - { // write XOR/NXOR gates - assert( i == 4 ); - if ( SymbolOut == '1' ) - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, "01 1\n10 1\n") ); - else - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, "00 1\n11 1\n") ); - } } } } Extra_ProgressBarStop( pProgress ); + Vec_StrFree( vString ); + // check if constant have been added if ( pNet = Abc_NtkFindNet( pNtk, "vdd" ) ) - { - // create the constant 1 node - pNode = Abc_NtkCreateNode( pNtk ); - Abc_ObjAddFanin( pNet, pNode ); - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, " 1\n") ); - } + Io_ReadCreateConst( pNtk, "vdd", 1 ); if ( pNet = Abc_NtkFindNet( pNtk, "gnd" ) ) - { - // create the constant 1 node - pNode = Abc_NtkCreateNode( pNtk ); - Abc_ObjAddFanin( pNet, pNode ); - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, " 0\n") ); - } + Io_ReadCreateConst( pNtk, "gnd", 0 ); - Io_ReadSetNonDrivenNets( pNtk ); - Vec_StrFree( vString ); + Abc_NtkFinalizeRead( pNtk ); return pNtk; } - //////////////////////////////////////////////////////////////////////// /// END OF FILE /// //////////////////////////////////////////////////////////////////////// diff --git a/src/base/io/ioReadBlif.c b/src/base/io/ioReadBlif.c index 10346729..693f1104 100644 --- a/src/base/io/ioReadBlif.c +++ b/src/base/io/ioReadBlif.c @@ -19,6 +19,8 @@ ***********************************************************************/ #include "io.h" +#include "main.h" +#include "mio.h" //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// @@ -28,19 +30,19 @@ typedef struct Io_ReadBlif_t_ Io_ReadBlif_t; // all reading info struct Io_ReadBlif_t_ { // general info about file - char * pFileName; // the name of the file - Extra_FileReader_t* pReader; // the input file reader + char * pFileName; // the name of the file + Extra_FileReader_t * pReader; // the input file reader // current processing info - Abc_Ntk_t * pNtk; // the primary network - Abc_Ntk_t * pNtkExdc; // the exdc network - int fParsingExdc; // this flag is on, when we are parsing EXDC network - int LineCur; // the line currently parsed + Abc_Ntk_t * pNtk; // the primary network + Abc_Ntk_t * pNtkExdc; // the exdc network + int fParsingExdc; // this flag is on, when we are parsing EXDC network + int LineCur; // the line currently parsed // temporary storage for tokens - Vec_Ptr_t * vNewTokens; // the temporary storage for the tokens - Vec_Str_t * vCubes; // the temporary storage for the tokens + Vec_Ptr_t * vNewTokens; // the temporary storage for the tokens + Vec_Str_t * vCubes; // the temporary storage for the tokens // the error message - FILE * Output; // the output stream - char sError[1000]; // the error string generated during parsing + FILE * Output; // the output stream + char sError[1000]; // the error string generated during parsing }; static Io_ReadBlif_t * Io_ReadBlifFile( char * pFileName ); @@ -48,11 +50,13 @@ static void Io_ReadBlifFree( Io_ReadBlif_t * p ); static void Io_ReadBlifPrintErrorMessage( Io_ReadBlif_t * p ); static Vec_Ptr_t * Io_ReadBlifGetTokens( Io_ReadBlif_t * p ); static Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p ); +static char * Io_ReadBlifCleanName( char * pName ); static int Io_ReadBlifNetworkInputs( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ); static int Io_ReadBlifNetworkOutputs( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ); static int Io_ReadBlifNetworkLatch( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ); static int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ); +static int Io_ReadBlifNetworkGate( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ); static int Io_ReadBlifNetworkInputArrival( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ); static int Io_ReadBlifNetworkDefaultInputArrival( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ); @@ -271,7 +275,7 @@ Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p ) { ProgressBar * pProgress; Vec_Ptr_t * vTokens; - char * pModelName; + char * pModelName, * pDirective; int iLine, fTokensReady, fStatus; // read the model name @@ -288,12 +292,12 @@ Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p ) } pModelName = vTokens->pArray[1]; // allocate the empty network - p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST ); + p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP ); p->pNtk->pName = util_strsav( pModelName ); p->pNtk->pSpec = util_strsav( p->pFileName ); } else - p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST ); + p->pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP ); // read the inputs/outputs pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p->pReader) ); @@ -305,32 +309,35 @@ Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p ) // consider different line types fTokensReady = 0; - if ( !strcmp( vTokens->pArray[0], ".names" ) ) + pDirective = vTokens->pArray[0]; + if ( !strcmp( pDirective, ".names" ) ) { fStatus = Io_ReadBlifNetworkNames( p, &vTokens ); fTokensReady = 1; } - else if ( !strcmp( vTokens->pArray[0], ".latch" ) ) + else if ( !strcmp( pDirective, ".gate" ) ) + fStatus = Io_ReadBlifNetworkGate( p, vTokens ); + else if ( !strcmp( pDirective, ".latch" ) ) fStatus = Io_ReadBlifNetworkLatch( p, vTokens ); - else if ( !strcmp( vTokens->pArray[0], ".inputs" ) ) + else if ( !strcmp( pDirective, ".inputs" ) ) fStatus = Io_ReadBlifNetworkInputs( p, vTokens ); - else if ( !strcmp( vTokens->pArray[0], ".outputs" ) ) + else if ( !strcmp( pDirective, ".outputs" ) ) fStatus = Io_ReadBlifNetworkOutputs( p, vTokens ); - else if ( !strcmp( vTokens->pArray[0], ".input_arrival" ) ) + else if ( !strcmp( pDirective, ".input_arrival" ) ) fStatus = Io_ReadBlifNetworkInputArrival( p, vTokens ); - else if ( !strcmp( vTokens->pArray[0], ".default_input_arrival" ) ) + else if ( !strcmp( pDirective, ".default_input_arrival" ) ) fStatus = Io_ReadBlifNetworkDefaultInputArrival( p, vTokens ); - else if ( !strcmp( vTokens->pArray[0], ".exdc" ) ) + else if ( !strcmp( pDirective, ".exdc" ) ) { p->fParsingExdc = 1; break; } - else if ( !strcmp( vTokens->pArray[0], ".end" ) ) + else if ( !strcmp( pDirective, ".end" ) ) break; else printf( "%s (line %d): Skipping directive \"%s\".\n", p->pFileName, - Extra_FileReaderGetLineNumber(p->pReader, 0), vTokens->pArray[0] ); + Extra_FileReaderGetLineNumber(p->pReader, 0), pDirective ); if ( vTokens == NULL ) // some files do not have ".end" in the end break; if ( fStatus == 1 ) return NULL; } Extra_ProgressBarStop( pProgress ); - Io_ReadSetNonDrivenNets( p->pNtk ); + Abc_NtkFinalizeRead( p->pNtk ); return p->pNtk; } @@ -347,17 +354,9 @@ Abc_Ntk_t * Io_ReadBlifNetwork( Io_ReadBlif_t * p ) ***********************************************************************/ int Io_ReadBlifNetworkInputs( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) { - Abc_Ntk_t * pNtk = p->pNtk; - Abc_Obj_t * pNet; int i; for ( i = 1; i < vTokens->nSize; i++ ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[i] ); - if ( Abc_ObjIsPi(pNet) ) - printf( "Warning: PI net \"%s\" appears twice in the list.\n", vTokens->pArray[i] ); - else - Abc_NtkMarkNetPi( pNet ); - } + Io_ReadCreatePi( p->pNtk, vTokens->pArray[i] ); return 0; } @@ -374,17 +373,9 @@ int Io_ReadBlifNetworkInputs( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) ***********************************************************************/ int Io_ReadBlifNetworkOutputs( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) { - Abc_Ntk_t * pNtk = p->pNtk; - Abc_Obj_t * pNet; int i; for ( i = 1; i < vTokens->nSize; i++ ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[i] ); - if ( Abc_ObjIsPo(pNet) ) - printf( "Warning: PO net \"%s\" appears twice in the list.\n", vTokens->pArray[i] ); - else - Abc_NtkMarkNetPo( pNet ); - } + Io_ReadCreatePo( p->pNtk, vTokens->pArray[i] ); return 0; } @@ -402,7 +393,7 @@ int Io_ReadBlifNetworkOutputs( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) int Io_ReadBlifNetworkLatch( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) { Abc_Ntk_t * pNtk = p->pNtk; - Abc_Obj_t * pNet, * pLatch; + Abc_Obj_t * pLatch; int ResetValue; if ( vTokens->nSize < 3 ) @@ -412,16 +403,8 @@ int Io_ReadBlifNetworkLatch( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) Io_ReadBlifPrintErrorMessage( p ); return 1; } - // create a new node and add it to the network - pLatch = Abc_NtkCreateLatch( pNtk ); - // create the LO (PI) - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[2] ); - Abc_ObjAddFanin( pNet, pLatch ); - Abc_ObjSetSubtype( pNet, ABC_OBJ_SUBTYPE_LO ); - // save the LI (PO) - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[1] ); - Abc_ObjAddFanin( pLatch, pNet ); - Abc_ObjSetSubtype( pNet, ABC_OBJ_SUBTYPE_LI ); + // create the latch + pLatch = Io_ReadCreateLatch( pNtk, vTokens->pArray[1], vTokens->pArray[2] ); // get the latch reset value if ( vTokens->nSize == 3 ) ResetValue = 2; @@ -455,12 +438,11 @@ int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ) { Vec_Ptr_t * vTokens = *pvTokens; Abc_Ntk_t * pNtk = p->pNtk; - Abc_Obj_t * pNet, * pNode; - char * pToken, Char; - int i, nFanins; + Abc_Obj_t * pNode; + char * pToken, Char, ** ppNames; + int nFanins, nNames; // create a new node and add it to the network - pNode = Abc_NtkCreateNode( pNtk ); if ( vTokens->nSize < 2 ) { p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); @@ -468,19 +450,17 @@ int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ) Io_ReadBlifPrintErrorMessage( p ); return 1; } - // go through the nets - for ( i = 1; i < vTokens->nSize - 1; i++ ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[i] ); - Abc_ObjAddFanin( pNode, pNet ); - } - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[vTokens->nSize - 1] ); - Abc_ObjAddFanin( pNet, pNode ); + + // create the node + ppNames = (char **)vTokens->pArray + 1; + nNames = vTokens->nSize - 2; + pNode = Io_ReadCreateNode( pNtk, ppNames[nNames], ppNames, nNames ); // derive the functionality of the node p->vCubes->nSize = 0; nFanins = vTokens->nSize - 2; if ( nFanins == 0 ) + { while ( vTokens = Io_ReadBlifGetTokens(p) ) { pToken = vTokens->pArray[0]; @@ -500,7 +480,9 @@ int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ) Vec_StrPush( p->vCubes, Char ); Vec_StrPush( p->vCubes, '\n' ); } + } else + { while ( vTokens = Io_ReadBlifGetTokens(p) ) { pToken = vTokens->pArray[0]; @@ -515,8 +497,7 @@ int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ) return 1; } // create the cube - for ( i = 0; i < nFanins; i++ ) - Vec_StrPush( p->vCubes, ((char *)vTokens->pArray[0])[i] ); + Vec_StrAppend( p->vCubes, vTokens->pArray[0] ); // check the char Char = ((char *)vTokens->pArray[1])[0]; if ( Char != '0' && Char != '1' ) @@ -530,6 +511,7 @@ int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ) Vec_StrPush( p->vCubes, Char ); Vec_StrPush( p->vCubes, '\n' ); } + } // if there is nothing there if ( p->vCubes->nSize == 0 ) { @@ -539,13 +521,116 @@ int Io_ReadBlifNetworkNames( Io_ReadBlif_t * p, Vec_Ptr_t ** pvTokens ) Vec_StrPush( p->vCubes, '\n' ); } Vec_StrPush( p->vCubes, 0 ); + // set the pointer to the functionality of the node Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, p->vCubes->pArray) ); + // return the last array of tokens *pvTokens = vTokens; return 0; } +/**Function************************************************************* + + Synopsis [] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +int Io_ReadBlifNetworkGate( Io_ReadBlif_t * p, Vec_Ptr_t * vTokens ) +{ + Mio_Library_t * pGenlib; + Mio_Gate_t * pGate; + Abc_Obj_t * pNode; + char ** ppNames; + int i, nNames; + + // check that the library is available + pGenlib = Abc_FrameReadLibGen(Abc_FrameGetGlobalFrame()); + if ( pGenlib == NULL ) + { + p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); + sprintf( p->sError, "The current library is not available." ); + Io_ReadBlifPrintErrorMessage( p ); + return 1; + } + + // create a new node and add it to the network + if ( vTokens->nSize < 2 ) + { + p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); + sprintf( p->sError, "The .gate line has less than two tokens." ); + Io_ReadBlifPrintErrorMessage( p ); + return 1; + } + + // get the gate + pGate = Mio_LibraryReadGateByName( pGenlib, vTokens->pArray[1] ); + if ( pGate == NULL ) + { + p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); + sprintf( p->sError, "Cannot find gate \"%s\" in the library.", vTokens->pArray[1] ); + Io_ReadBlifPrintErrorMessage( p ); + return 1; + } + + // if this is the first line with gate, update the network type + if ( Abc_NtkNodeNum(p->pNtk) == 0 ) + { + assert( p->pNtk->Type = ABC_NTK_NETLIST_SOP ); + p->pNtk->Type = ABC_NTK_NETLIST_MAP; + Extra_MmFlexStop( p->pNtk->pManFunc, 0 ); + p->pNtk->pManFunc = pGenlib; + } + + // remove the formal parameter names + for ( i = 2; i < vTokens->nSize; i++ ) + { + vTokens->pArray[i] = Io_ReadBlifCleanName( vTokens->pArray[i] ); + if ( vTokens->pArray[i] == NULL ) + { + p->LineCur = Extra_FileReaderGetLineNumber(p->pReader, 0); + sprintf( p->sError, "Invalid gate input assignment." ); + Io_ReadBlifPrintErrorMessage( p ); + return 1; + } + } + + // create the node + ppNames = (char **)vTokens->pArray + 2; + nNames = vTokens->nSize - 3; + pNode = Io_ReadCreateNode( p->pNtk, ppNames[nNames], ppNames, nNames ); + + // set the pointer to the functionality of the node + Abc_ObjSetData( pNode, pGate ); + return 0; +} + + +/**Function************************************************************* + + Synopsis [] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +char * Io_ReadBlifCleanName( char * pName ) +{ + int i, Length; + Length = strlen(pName); + for ( i = 0; i < Length; i++ ) + if ( pName[i] == '=' ) + return pName + i + 1; + return NULL; +} /**Function************************************************************* diff --git a/src/base/io/ioReadPla.c b/src/base/io/ioReadPla.c index 16b87fc9..951fb229 100644 --- a/src/base/io/ioReadPla.c +++ b/src/base/io/ioReadPla.c @@ -82,7 +82,7 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) ProgressBar * pProgress; Vec_Ptr_t * vTokens; Abc_Ntk_t * pNtk; - Abc_Obj_t * pNet, * pNode; + Abc_Obj_t * pTerm, * pNode; Vec_Str_t ** ppSops; char Buffer[100]; int nInputs = -1, nOutputs = -1, nProducts = -1; @@ -90,11 +90,7 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) int i, k, iLine, nDigits, nCubes; // allocate the empty network - pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST ); - - // set the specs - pNtk->pName = util_strsav( Extra_FileReaderGetFileName(p) ); - pNtk->pSpec = util_strsav( Extra_FileReaderGetFileName(p) ); + pNtk = Abc_NtkStartRead( Extra_FileReaderGetFileName(p) ); // go through the lines of the file nCubes = 0; @@ -126,26 +122,14 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) if ( vTokens->nSize - 1 != nInputs ) printf( "Warning: Mismatch between the number of PIs on the .i line (%d) and the number of PIs on the .ilb line (%d).\n", nInputs, vTokens->nSize - 1 ); for ( i = 1; i < vTokens->nSize; i++ ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[i] ); - if ( Abc_ObjIsPi(pNet) ) - printf( "Warning: PI net \"%s\" appears twice in the list.\n", vTokens->pArray[1] ); - else - Abc_NtkMarkNetPi( pNet ); - } + Io_ReadCreatePi( pNtk, vTokens->pArray[i] ); } else if ( strcmp( vTokens->pArray[0], ".ob" ) == 0 ) { if ( vTokens->nSize - 1 != nOutputs ) printf( "Warning: Mismatch between the number of POs on the .o line (%d) and the number of POs on the .ob line (%d).\n", nOutputs, vTokens->nSize - 1 ); for ( i = 1; i < vTokens->nSize; i++ ) - { - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[i] ); - if ( Abc_ObjIsPo(pNet) ) - printf( "Warning: PO net \"%s\" appears twice in the list.\n", vTokens->pArray[1] ); - else - Abc_NtkMarkNetPo( pNet ); - } + Io_ReadCreatePo( pNtk, vTokens->pArray[i] ); } else { @@ -162,8 +146,7 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) for ( i = 0; i < nInputs; i++ ) { sprintf( Buffer, "x%0*d", nDigits, i ); - pNet = Abc_NtkFindOrCreateNet( pNtk, Buffer ); - Abc_NtkMarkNetPi( pNet ); + Io_ReadCreatePi( pNtk, Buffer ); } } if ( Abc_NtkPoNum(pNtk) == 0 ) @@ -178,8 +161,7 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) for ( i = 0; i < nOutputs; i++ ) { sprintf( Buffer, "z%0*d", nDigits, i ); - pNet = Abc_NtkFindOrCreateNet( pNtk, Buffer ); - Abc_NtkMarkNetPo( pNet ); + Io_ReadCreatePo( pNtk, Buffer ); } } if ( Abc_NtkNodeNum(pNtk) == 0 ) @@ -187,13 +169,13 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) // create the PO drivers and add them // start the SOP covers ppSops = ALLOC( Vec_Str_t *, nOutputs ); - Abc_NtkForEachPo( pNtk, pNet, i ) + Abc_NtkForEachPo( pNtk, pTerm, i ) { ppSops[i] = Vec_StrAlloc( 100 ); pNode = Abc_NtkCreateNode(pNtk); for ( k = 0; k < nInputs; k++ ) Abc_ObjAddFanin( pNode, Abc_NtkPi(pNtk,k) ); - Abc_ObjAddFanin( pNet, pNode ); + Abc_ObjAddFanin( Abc_ObjFanout0(pTerm), pNode ); } } // read the cubes @@ -237,9 +219,9 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) nCubes, nProducts ); // add the SOP covers - Abc_NtkForEachPo( pNtk, pNet, i ) + Abc_NtkForEachPo( pNtk, pTerm, i ) { - pNode = Abc_ObjFanin0(pNet); + pNode = Abc_ObjFanin0Ntk(pTerm); if ( ppSops[i]->nSize == 0 ) { Abc_ObjRemoveFanins(pNode); @@ -251,6 +233,7 @@ Abc_Ntk_t * Io_ReadPlaNetwork( Extra_FileReader_t * p ) Vec_StrFree( ppSops[i] ); } free( ppSops ); + Abc_NtkFinalizeRead( pNtk ); return pNtk; } diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c index a3b5a0bf..755fb1db 100644 --- a/src/base/io/ioReadVerilog.c +++ b/src/base/io/ioReadVerilog.c @@ -271,10 +271,16 @@ Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p ) pModelName = vTokens->pArray[1]; // allocate the empty network - pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST ); + pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST_SOP ); pNtk->pName = util_strsav( pModelName ); pNtk->pSpec = util_strsav( p->pFileName ); + // create constant nodes and nets + Abc_NtkFindOrCreateNet( pNtk, "1'b0" ); + Abc_NtkFindOrCreateNet( pNtk, "1'b1" ); + Io_ReadCreateConst( pNtk, "1'b0", 0 ); + Io_ReadCreateConst( pNtk, "1'b1", 1 ); + // read the inputs/outputs pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p->pReader) ); for ( i = 0; vTokens = Extra_FileReaderGetTokens(p->pReader); i++ ) @@ -348,7 +354,7 @@ Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p ) for ( i = 0; i < p->vSkipped->nSize; i++ ) free( p->vSkipped->pArray[i] ); } - Io_ReadSetNonDrivenNets( pNtk ); + Abc_NtkFinalizeRead( pNtk ); return pNtk; } @@ -365,48 +371,25 @@ Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p ) ***********************************************************************/ bool Io_ReadVerNetworkAssign( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens ) { - Abc_Obj_t * pNet, * pNode; - assert( strcmp( vTokens->pArray[0], "assign" ) == 0 ); - - if ( strcmp( vTokens->pArray[3], "1'b0" ) != 0 && strcmp( vTokens->pArray[3], "1'b1" ) != 0 ) + // make sure the driving variable exists + if ( !Abc_NtkFindNet( pNtk, vTokens->pArray[3] ) ) { - // handle assignment to a variable - if ( vTokens->nSize == 4 && (pNet = Abc_NtkFindNet(pNtk, vTokens->pArray[3])) ) - { - // allocate the buffer node - pNode = Abc_NtkCreateNode( pNtk ); - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, "1 1\n") ); - // add the fanin net - Abc_ObjAddFanin( pNode, pNet ); - // add the fanout net - pNet = Abc_NtkFindNet(pNtk, vTokens->pArray[1]); - Abc_ObjAddFanin( pNet, pNode ); - return 1; - } - // produce error in case of more complex assignment p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "The assign operator is handled only for assignment to a variable and a constant." ); + sprintf( p->sError, "Cannot find net \"%s\". The assign operator is handled only for assignment to a variable and a constant.", vTokens->pArray[3] ); Io_ReadVerPrintErrorMessage( p ); return 0; } - // allocate constant node - pNode = Abc_NtkCreateNode( pNtk ); - // set the constant function - if ( ((char *)vTokens->pArray[3])[3] == '0' ) - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, " 0\n") ); - else - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, " 1\n") ); - // set the fanout net - pNet = Abc_NtkFindNet( pNtk, vTokens->pArray[1] ); - if ( pNet == NULL ) + // make sure the driven variable exists + if ( !Abc_NtkFindNet( pNtk, vTokens->pArray[1] ) ) { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 1 ); + p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); sprintf( p->sError, "Cannot find net \"%s\".", vTokens->pArray[1] ); Io_ReadVerPrintErrorMessage( p ); return 0; } - Abc_ObjAddFanin( pNet, pNode ); + // create a buffer + Io_ReadCreateBuf( pNtk, vTokens->pArray[3], vTokens->pArray[1] ); return 1; } @@ -423,8 +406,8 @@ bool Io_ReadVerNetworkAssign( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vT ***********************************************************************/ bool Io_ReadVerNetworkSignal( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ) { - char Buffer[1000]; Abc_Obj_t * pNet; + char Buffer[1000]; char * pToken; int nSignals, k, Start, s; @@ -455,26 +438,27 @@ bool Io_ReadVerNetworkSignal( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vT for ( s = 0; s < nSignals; s++ ) { sprintf( Buffer, "%s[%d]", pToken, s ); - pNet = Abc_NtkFindOrCreateNet( pNtk, Buffer ); if ( LineType == VER_INPUT || LineType == VER_INOUT ) - Abc_NtkMarkNetPi( pNet ); + Io_ReadCreatePi( pNtk, Buffer ); if ( LineType == VER_OUTPUT || LineType == VER_INOUT ) - Abc_NtkMarkNetPo( pNet ); + Io_ReadCreatePo( pNtk, Buffer ); + if ( LineType != VER_INPUT && LineType != VER_OUTPUT && LineType != VER_INOUT ) + pNet = Abc_NtkFindOrCreateNet( pNtk, Buffer ); } } else { - pNet = Abc_NtkFindOrCreateNet( pNtk, pToken ); if ( LineType == VER_INPUT || LineType == VER_INOUT ) - Abc_NtkMarkNetPi( pNet ); + Io_ReadCreatePi( pNtk, pToken ); if ( LineType == VER_OUTPUT || LineType == VER_INOUT ) - Abc_NtkMarkNetPo( pNet ); + Io_ReadCreatePo( pNtk, pToken ); + if ( LineType != VER_INPUT && LineType != VER_OUTPUT && LineType != VER_INOUT ) + pNet = Abc_NtkFindOrCreateNet( pNtk, pToken ); } } return 1; } - /**Function************************************************************* Synopsis [Reads a simple gate from the verilog file.] @@ -488,17 +472,15 @@ bool Io_ReadVerNetworkSignal( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vT ***********************************************************************/ bool Io_ReadVerNetworkGateSimple( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ) { - Abc_Obj_t * pNode, * pNet, * pNodeConst, * pNetConst; + Abc_Obj_t * pNet, * pNode; char * pToken; int nFanins, k; // create the node pNode = Abc_NtkCreateNode( pNtk ); - // set the function - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) ); - // skip the gate type and gate name // add the fanin nets nFanins = s_CadenceGates[LineType][1][0] - '0'; + // skip the gate type and gate name for ( k = 2; k < vTokens->nSize - 1; k++ ) { pToken = vTokens->pArray[k]; @@ -510,23 +492,6 @@ bool Io_ReadVerNetworkGateSimple( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t Abc_ObjAddFanin( pNode, pNet ); continue; } - // handle the case of a constant - if ( strcmp( pToken, "1'b0" ) == 0 || strcmp( pToken, "1'b1" ) == 0 ) - { - // create the net and link it to the node - pNetConst = Abc_NtkFindOrCreateNet( pNtk, pToken ); - Abc_ObjAddFanin( pNode, pNetConst ); - // allocate constant node - pNodeConst = Abc_NtkCreateNode( pNtk ); - // set the constant function - if ( pToken[3] == '0' ) - Abc_ObjSetData( pNodeConst, Abc_SopRegister(pNtk->pManFunc, " 0\n") ); - else - Abc_ObjSetData( pNodeConst, Abc_SopRegister(pNtk->pManFunc, " 1\n") ); - // add this node as the fanin of the constant net - Abc_ObjAddFanin( pNetConst, pNodeConst ); - continue; - } p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); sprintf( p->sError, "Cannot find net \"%s\".", pToken ); Io_ReadVerPrintErrorMessage( p ); @@ -558,6 +523,8 @@ bool Io_ReadVerNetworkGateSimple( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t return 0; } Abc_ObjAddFanin( pNet, pNode ); + // set the function + Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) ); return 1; } @@ -580,9 +547,7 @@ bool Io_ReadVerNetworkGateComplex( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t // create the nodes pNode1 = Abc_NtkCreateNode( pNtk ); - Abc_ObjSetData( pNode1, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) ); pNode2 = Abc_NtkCreateNode( pNtk ); - Abc_ObjSetData( pNode2, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][4]) ); // skip the gate type and gate name // add the fanin nets nFanins = s_CadenceGates[LineType][1][0] - '0'; @@ -649,6 +614,8 @@ bool Io_ReadVerNetworkGateComplex( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t return 0; } Abc_ObjAddFanin( pNet, pNode2 ); + Abc_ObjSetData( pNode1, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) ); + Abc_ObjSetData( pNode2, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][4]) ); return 1; } @@ -665,7 +632,7 @@ bool Io_ReadVerNetworkGateComplex( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t ***********************************************************************/ bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens ) { - Abc_Obj_t * pLatch, * pNet, * pNode; + Abc_Obj_t * pLatch, * pNet; char * pToken, * pToken2, * pTokenRN, * pTokenSN, * pTokenSI, * pTokenSE, * pTokenD, * pTokenQ, * pTokenQN; int k, fRN1, fSN1; @@ -717,59 +684,20 @@ bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTo Io_ReadVerPrintErrorMessage( p ); return 0; } - - // create the latch - pLatch = Abc_NtkCreateLatch( pNtk ); - // create the LO (PI) - pNet = Abc_NtkFindOrCreateNet( pNtk, vTokens->pArray[1] ); - Abc_ObjAddFanin( pNet, pLatch ); - Abc_ObjSetSubtype( pNet, ABC_OBJ_SUBTYPE_LO ); - // save the LI (PO) - pNet = Abc_NtkFindNet( pNtk, pTokenD ); - if ( pNet == NULL ) + if ( Abc_NtkFindNet( pNtk, pTokenD ) == NULL ) { - // check the case if it is not a constant input - if ( strcmp( pTokenD, "1'b0" ) && strcmp( pTokenD, "1'b1" ) ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find latch input net \"%s\".", pTokenD ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - - // create the constant net - if ( strcmp( pTokenD, "1'b0" ) == 0 ) - pNet = Abc_NtkFindOrCreateNet( pNtk, "Constant0" ); - else - pNet = Abc_NtkFindOrCreateNet( pNtk, "Constant1" ); - - // drive it with the constant node - if ( Abc_ObjFaninNum( pNet ) == 0 ) - { - // allocate constant node - pNode = Abc_NtkCreateNode( pNtk ); - // set the constant function - if ( strcmp( pTokenD, "1'b0" ) == 0 ) - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, " 0\n") ); - else - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, " 1\n") ); - // add the fanout net - Abc_ObjAddFanin( pNet, pNode ); - } + p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); + sprintf( p->sError, "Cannot find latch input net \"%s\".", pTokenD ); + Io_ReadVerPrintErrorMessage( p ); + return 0; } - Abc_ObjAddFanin( pLatch, pNet ); - Abc_ObjSetSubtype( pNet, ABC_OBJ_SUBTYPE_LI ); + + // create the latch + pLatch = Io_ReadCreateLatch( pNtk, pTokenD, vTokens->pArray[1] ); // create the buffer if Q signal is available if ( pTokenQ ) { - // create the node - pNode = Abc_NtkCreateNode( pNtk); - // set the function - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, "1 1\n") ); - // create fanin and fanout nets - pNet = Abc_NtkFindNet( pNtk, vTokens->pArray[1] ); - Abc_ObjAddFanin( pNode, pNet ); pNet = Abc_NtkFindNet( pNtk, pTokenQ ); if ( pNet == NULL ) { @@ -778,17 +706,10 @@ bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTo Io_ReadVerPrintErrorMessage( p ); return 0; } - Abc_ObjAddFanin( pNet, pNode ); + Io_ReadCreateBuf( pNtk, vTokens->pArray[1], pTokenQ ); } if ( pTokenQN ) { - // create the node - pNode = Abc_NtkCreateNode( pNtk ); - // set the function - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, "0 1\n") ); - // create fanin and fanout nets - pNet = Abc_NtkFindNet( pNtk, vTokens->pArray[1] ); - Abc_ObjAddFanin( pNode, pNet ); pNet = Abc_NtkFindNet( pNtk, pTokenQN ); if ( pNet == NULL ) { @@ -797,7 +718,7 @@ bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTo Io_ReadVerPrintErrorMessage( p ); return 0; } - Abc_ObjAddFanin( pNet, pNode ); + Io_ReadCreateInv( pNtk, vTokens->pArray[1], pTokenQN ); } // set the initial value @@ -824,62 +745,6 @@ bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTo return 1; } -/**Function************************************************************* - - Synopsis [Reads the verilog file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_ReadSetNonDrivenNets( Abc_Ntk_t * pNtk ) -{ - Vec_Ptr_t * vNets; - Abc_Obj_t * pNet, * pNode; - int i; - - // check for non-driven nets - vNets = Vec_PtrAlloc( 100 ); - Abc_NtkForEachNet( pNtk, pNet, i ) - { - if ( !Abc_ObjIsPi(pNet) && Abc_ObjFaninNum(pNet) == 0 ) - { - // add the constant 0 driver - pNode = Abc_NtkCreateNode( pNtk ); - // set the constant function - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, " 0\n") ); - // add the fanout net - Abc_ObjAddFanin( pNet, pNode ); - // add the net to those for which the warning will be printed - Vec_PtrPush( vNets, pNet->pData ); - } - } - - // print the warning - if ( vNets->nSize > 0 ) - { - printf( "The reader added constant-zero driver to %d non-driven nets:\n", vNets->nSize ); - for ( i = 0; i < vNets->nSize; i++ ) - { - if ( i == 0 ) - printf( "%s", vNets->pArray[i] ); - else if ( i == 1 ) - printf( ", %s", vNets->pArray[i] ); - else if ( i == 2 ) - { - printf( ", %s, etc.", vNets->pArray[i] ); - break; - } - } - printf( "\n" ); - } - Vec_PtrFree( vNets ); -} - - //////////////////////////////////////////////////////////////////////// /// END OF FILE /// //////////////////////////////////////////////////////////////////////// diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c new file mode 100644 index 00000000..132684cc --- /dev/null +++ b/src/base/io/ioUtil.c @@ -0,0 +1,201 @@ +/**CFile**************************************************************** + + FileName [ioUtil.c] + + SystemName [ABC: Logic synthesis and verification system.] + + PackageName [Command processing package.] + + Synopsis [Procedures to write the network in BENCH format.] + + Author [Alan Mishchenko] + + Affiliation [UC Berkeley] + + Date [Ver. 1.0. Started - June 20, 2005.] + + Revision [$Id: ioUtil.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $] + +***********************************************************************/ + +#include "io.h" + +//////////////////////////////////////////////////////////////////////// +/// DECLARATIONS /// +//////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////// +/// FUNCTION DEFITIONS /// +//////////////////////////////////////////////////////////////////////// + +/**Function************************************************************* + + Synopsis [Creates PI terminal and net.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Io_ReadCreatePi( Abc_Ntk_t * pNtk, char * pName ) +{ + Abc_Obj_t * pNet, * pTerm; + // get the PI net + pNet = Abc_NtkFindNet( pNtk, pName ); + if ( pNet ) + printf( "Warning: PI \"%s\" appears twice in the list.\n", pName ); + pNet = Abc_NtkFindOrCreateNet( pNtk, pName ); + // add the PI node + pTerm = Abc_NtkCreatePi( pNtk ); + Abc_ObjAddFanin( pNet, pTerm ); + return pTerm; +} + +/**Function************************************************************* + + Synopsis [Creates PO terminal and net.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Io_ReadCreatePo( Abc_Ntk_t * pNtk, char * pName ) +{ + Abc_Obj_t * pNet, * pTerm; + // get the PO net + pNet = Abc_NtkFindNet( pNtk, pName ); + if ( pNet && Abc_ObjFaninNum(pNet) == 0 ) + printf( "Warning: PO \"%s\" appears twice in the list.\n", pName ); + pNet = Abc_NtkFindOrCreateNet( pNtk, pName ); + // add the PO node + pTerm = Abc_NtkCreatePo( pNtk ); + Abc_ObjAddFanin( pTerm, pNet ); + return pTerm; +} + +/**Function************************************************************* + + Synopsis [Create a latch with the given input/output.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Io_ReadCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO ) +{ + Abc_Obj_t * pLatch, * pNet; + // create a new latch and add it to the network + pLatch = Abc_NtkCreateLatch( pNtk ); + // get the LI net + pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLI ); + Abc_ObjAddFanin( pLatch, pNet ); + // get the LO net + pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO ); + Abc_ObjAddFanin( pNet, pLatch ); + return pLatch; +} + +/**Function************************************************************* + + Synopsis [Create node and the net driven by it.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Io_ReadCreateNode( Abc_Ntk_t * pNtk, char * pNameOut, char * pNamesIn[], int nInputs ) +{ + Abc_Obj_t * pNet, * pNode; + int i; + // create a new node + pNode = Abc_NtkCreateNode( pNtk ); + // add the fanin nets + for ( i = 0; i < nInputs; i++ ) + { + pNet = Abc_NtkFindOrCreateNet( pNtk, pNamesIn[i] ); + Abc_ObjAddFanin( pNode, pNet ); + } + // add the fanout net + pNet = Abc_NtkFindOrCreateNet( pNtk, pNameOut ); + Abc_ObjAddFanin( pNet, pNode ); + return pNode; +} + +/**Function************************************************************* + + Synopsis [Create a constant 0 node driving the net with this name.] + + Description [Assumes that the net already exists.] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Io_ReadCreateConst( Abc_Ntk_t * pNtk, char * pName, bool fConst1 ) +{ + Abc_Obj_t * pNet, * pTerm; + pTerm = fConst1? Abc_NodeCreateConst1(pNtk) : Abc_NodeCreateConst0(pNtk); + pNet = Abc_NtkFindNet(pNtk, pName); assert( pNet ); + Abc_ObjAddFanin( pNet, pTerm ); + return pTerm; +} + +/**Function************************************************************* + + Synopsis [Create an inverter or buffer for the given net.] + + Description [Assumes that the nets already exist.] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Io_ReadCreateInv( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut ) +{ + Abc_Obj_t * pNet, * pNode; + pNet = Abc_NtkFindNet(pNtk, pNameIn); assert( pNet ); + pNode = Abc_NodeCreateInv(pNtk, pNet); + pNet = Abc_NtkFindNet(pNtk, pNameOut); assert( pNet ); + Abc_ObjAddFanin( pNet, pNode ); + return pNode; +} + +/**Function************************************************************* + + Synopsis [Create an inverter or buffer for the given net.] + + Description [Assumes that the nets already exist.] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Io_ReadCreateBuf( Abc_Ntk_t * pNtk, char * pNameIn, char * pNameOut ) +{ + Abc_Obj_t * pNet, * pNode; + pNet = Abc_NtkFindNet(pNtk, pNameIn); assert( pNet ); + pNode = Abc_NodeCreateBuf(pNtk, pNet); + pNet = Abc_NtkFindNet(pNtk, pNameOut); assert( pNet ); + Abc_ObjAddFanin( pNet, pNode ); + return pNet; +} + +//////////////////////////////////////////////////////////////////////// +/// END OF FILE /// +//////////////////////////////////////////////////////////////////////// + + diff --git a/src/base/io/ioWriteBench.c b/src/base/io/ioWriteBench.c index 0b7591c0..980015b2 100644 --- a/src/base/io/ioWriteBench.c +++ b/src/base/io/ioWriteBench.c @@ -26,8 +26,6 @@ static int Io_WriteBenchOne( FILE * pFile, Abc_Ntk_t * pNtk ); static int Io_WriteBenchOneNode( FILE * pFile, Abc_Obj_t * pNode ); -static char * Io_BenchNodeName( Abc_Obj_t * pObj, int fPhase ); -static char * Io_BenchNodeNameInv( Abc_Obj_t * pObj ); //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFITIONS /// @@ -48,7 +46,7 @@ int Io_WriteBench( Abc_Ntk_t * pNtk, char * pFileName ) { Abc_Ntk_t * pExdc; FILE * pFile; - assert( Abc_NtkIsAig(pNtk) ); + assert( Abc_NtkIsNetlistSop(pNtk) ); pFile = fopen( pFileName, "w" ); if ( pFile == NULL ) { @@ -61,12 +59,7 @@ int Io_WriteBench( Abc_Ntk_t * pNtk, char * pFileName ) // write EXDC network if it exists pExdc = Abc_NtkExdc( pNtk ); if ( pExdc ) - { printf( "Io_WriteBench: EXDC is not written (warning).\n" ); -// fprintf( pFile, "\n" ); -// fprintf( pFile, ".exdc\n" ); -// Io_LogicWriteOne( pFile, pExdc ); - } // finalize the file fclose( pFile ); return 1; @@ -89,51 +82,23 @@ int Io_WriteBenchOne( FILE * pFile, Abc_Ntk_t * pNtk ) Abc_Obj_t * pNode; int i; - assert( Abc_NtkIsLogicSop(pNtk) || Abc_NtkIsAig(pNtk) ); - // write the PIs/POs/latches Abc_NtkForEachPi( pNtk, pNode, i ) - fprintf( pFile, "INPUT(%s)\n", Abc_NtkNamePi(pNtk,i) ); + fprintf( pFile, "INPUT(%s)\n", Abc_ObjName(Abc_ObjFanout0(pNode)) ); Abc_NtkForEachPo( pNtk, pNode, i ) - fprintf( pFile, "OUTPUT(%s)\n", Abc_NtkNamePo(pNtk,i) ); + fprintf( pFile, "OUTPUT(%s)\n", Abc_ObjName(Abc_ObjFanin0(pNode)) ); Abc_NtkForEachLatch( pNtk, pNode, i ) fprintf( pFile, "%-11s = DFF(%s)\n", - Abc_NtkNameLatch(pNtk,i), Abc_NtkNameLatchInput(pNtk,i) ); - - // set the node names - Abc_NtkCleanCopy( pNtk ); - Abc_NtkForEachCi( pNtk, pNode, i ) - pNode->pCopy = (Abc_Obj_t *)Abc_NtkNameCi(pNtk,i); - - // write intervers for COs appearing in negative polarity - Abc_NtkForEachCi( pNtk, pNode, i ) - { - if ( Abc_AigNodeIsUsedCompl(pNode) ) - fprintf( pFile, "%-11s = NOT(%s)\n", - Io_BenchNodeNameInv(pNode), - Abc_NtkNameCi(pNtk,i) ); - } + Abc_ObjName(pNode), Abc_ObjName(Abc_ObjFanin0(pNode)) ); // write internal nodes pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) ); Abc_NtkForEachNode( pNtk, pNode, i ) { Extra_ProgressBarUpdate( pProgress, i, NULL ); - if ( Abc_NodeIsConst(pNode) ) - continue; Io_WriteBenchOneNode( pFile, pNode ); } Extra_ProgressBarStop( pProgress ); - - // write buffers for CO - Abc_NtkForEachCo( pNtk, pNode, i ) - { - fprintf( pFile, "%-11s = BUFF(%s)\n", - (i < Abc_NtkPoNum(pNtk))? Abc_NtkNamePo(pNtk,i) : - Abc_NtkNameLatchInput( pNtk, i-Abc_NtkPoNum(pNtk) ), - Io_BenchNodeName( Abc_ObjFanin0(pNode), !Abc_ObjFaninC0(pNode) ) ); - } - Abc_NtkCleanCopy( pNtk ); return 1; } @@ -151,70 +116,36 @@ int Io_WriteBenchOne( FILE * pFile, Abc_Ntk_t * pNtk ) ***********************************************************************/ int Io_WriteBenchOneNode( FILE * pFile, Abc_Obj_t * pNode ) { - assert( Abc_ObjIsNode(pNode) ); - // write the AND gate - fprintf( pFile, "%-11s", Io_BenchNodeName( pNode, 1 ) ); - fprintf( pFile, " = AND(%s, ", Io_BenchNodeName( Abc_ObjFanin0(pNode), !Abc_ObjFaninC0(pNode) ) ); - fprintf( pFile, "%s)\n", Io_BenchNodeName( Abc_ObjFanin1(pNode), !Abc_ObjFaninC1(pNode) ) ); - - // write the inverter if necessary - if ( Abc_AigNodeIsUsedCompl(pNode) ) - { - fprintf( pFile, "%-11s = NOT(", Io_BenchNodeName( pNode, 0 ) ); - fprintf( pFile, "%s)\n", Io_BenchNodeName( pNode, 1 ) ); - } - return 1; -} - -/**Function************************************************************* - - Synopsis [Returns the name of an internal AIG node.] - - Description [] - - SideEffects [] + int nFanins; - SeeAlso [] - -***********************************************************************/ -char * Io_BenchNodeName( Abc_Obj_t * pObj, int fPhase ) -{ - static char Buffer[500]; - if ( pObj->pCopy ) // PIs and latches - { - sprintf( Buffer, "%s%s", (char *)pObj->pCopy, (fPhase? "":"_c") ); - return Buffer; + assert( Abc_ObjIsNode(pNode) ); + nFanins = Abc_ObjFaninNum(pNode); + if ( nFanins == 0 ) + { // write the constant 1 node + assert( Abc_NodeIsConst1(pNode) ); + fprintf( pFile, "%-11s", Abc_ObjName(Abc_ObjFanout0(pNode)) ); + fprintf( pFile, " = vdd\n" ); } - assert( Abc_ObjIsNode(pObj) ); - if ( Abc_NodeIsConst(pObj) ) // constant node - { - if ( fPhase ) - sprintf( Buffer, "%s", "vdd" ); + else if ( nFanins == 1 ) + { // write the interver/buffer + if ( Abc_NodeIsBuf(pNode) ) + { + fprintf( pFile, "%-11s = BUFF(", Abc_ObjName(Abc_ObjFanout0(pNode)) ); + fprintf( pFile, "%s)\n", Abc_ObjName(Abc_ObjFanin0(pNode)) ); + } else - sprintf( Buffer, "%s", "gnd" ); - return Buffer; + { + fprintf( pFile, "%-11s = NOT(", Abc_ObjName(Abc_ObjFanout0(pNode)) ); + fprintf( pFile, "%s)\n", Abc_ObjName(Abc_ObjFanin0(pNode)) ); + } } - // internal nodes - sprintf( Buffer, "%s%s", Abc_ObjName(pObj), (fPhase? "":"_c") ); - return Buffer; -} - -/**Function************************************************************* - - Synopsis [Returns the name of an internal AIG node.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -char * Io_BenchNodeNameInv( Abc_Obj_t * pObj ) -{ - static char Buffer[500]; - sprintf( Buffer, "%s%s", Abc_ObjName(pObj), "_c" ); - return Buffer; + else + { // write the AND gate + fprintf( pFile, "%-11s", Abc_ObjName(Abc_ObjFanout0(pNode)) ); + fprintf( pFile, " = AND(%s, ", Abc_ObjName(Abc_ObjFanin0(pNode)) ); + fprintf( pFile, "%s)\n", Abc_ObjName(Abc_ObjFanin1(pNode)) ); + } + return 1; } //////////////////////////////////////////////////////////////////////// diff --git a/src/base/io/ioWriteBlif.c b/src/base/io/ioWriteBlif.c index d9c69273..79de62b8 100644 --- a/src/base/io/ioWriteBlif.c +++ b/src/base/io/ioWriteBlif.c @@ -19,14 +19,17 @@ ***********************************************************************/ #include "io.h" +#include "main.h" +#include "mio.h" //////////////////////////////////////////////////////////////////////// /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// -static void Io_NtkWriteOne( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_NtkWritePis( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_NtkWritePos( FILE * pFile, Abc_Ntk_t * pNtk ); +static void Io_NtkWriteOne( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ); +static void Io_NtkWritePis( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ); +static void Io_NtkWritePos( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ); +static void Io_NtkWriteNodeGate( FILE * pFile, Abc_Obj_t * pNode ); static void Io_NtkWriteNodeFanins( FILE * pFile, Abc_Obj_t * pNode ); static void Io_NtkWriteNode( FILE * pFile, Abc_Obj_t * pNode ); static void Io_NtkWriteLatch( FILE * pFile, Abc_Obj_t * pLatch ); @@ -46,7 +49,32 @@ static void Io_NtkWriteLatch( FILE * pFile, Abc_Obj_t * pLatch ); SeeAlso [] ***********************************************************************/ -void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName ) +void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) +{ + Abc_Ntk_t * pNtkTemp; + // derive the netlist + pNtkTemp = Abc_NtkLogicToNetlist(pNtk); + if ( pNtkTemp == NULL ) + { + fprintf( stdout, "Writing BLIF has failed.\n" ); + return; + } + Io_WriteBlif( pNtkTemp, FileName, fWriteLatches ); + Abc_NtkDelete( pNtkTemp ); +} + +/**Function************************************************************* + + Synopsis [Write the network into a BLIF file with the given name.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) { Abc_Ntk_t * pExdc; FILE * pFile; @@ -60,14 +88,14 @@ void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName ) // write the model name fprintf( pFile, ".model %s\n", Abc_NtkName(pNtk) ); // write the network - Io_NtkWriteOne( pFile, pNtk ); + Io_NtkWriteOne( pFile, pNtk, fWriteLatches ); // write EXDC network if it exists pExdc = Abc_NtkExdc( pNtk ); if ( pExdc ) { fprintf( pFile, "\n" ); fprintf( pFile, ".exdc\n" ); - Io_NtkWriteOne( pFile, pExdc ); + Io_NtkWriteOne( pFile, pExdc, fWriteLatches ); } // finalize the file fprintf( pFile, ".end\n" ); @@ -88,7 +116,7 @@ void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName ) SeeAlso [] ***********************************************************************/ -void Io_NtkWriteOne( FILE * pFile, Abc_Ntk_t * pNtk ) +void Io_NtkWriteOne( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ) { ProgressBar * pProgress; Abc_Obj_t * pNode, * pLatch; @@ -96,19 +124,19 @@ void Io_NtkWriteOne( FILE * pFile, Abc_Ntk_t * pNtk ) // write the PIs fprintf( pFile, ".inputs" ); - Io_NtkWritePis( pFile, pNtk ); + Io_NtkWritePis( pFile, pNtk, fWriteLatches ); fprintf( pFile, "\n" ); // write the POs fprintf( pFile, ".outputs" ); - Io_NtkWritePos( pFile, pNtk ); + Io_NtkWritePos( pFile, pNtk, fWriteLatches ); fprintf( pFile, "\n" ); // write the timing info Io_WriteTimingInfo( pFile, pNtk ); // write the latches - if ( !Abc_NtkIsComb(pNtk) ) + if ( fWriteLatches && !Abc_NtkIsComb(pNtk) ) { fprintf( pFile, "\n" ); Abc_NtkForEachLatch( pNtk, pLatch, i ) @@ -138,9 +166,9 @@ void Io_NtkWriteOne( FILE * pFile, Abc_Ntk_t * pNtk ) SeeAlso [] ***********************************************************************/ -void Io_NtkWritePis( FILE * pFile, Abc_Ntk_t * pNtk ) +void Io_NtkWritePis( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ) { - Abc_Obj_t * pNet; + Abc_Obj_t * pTerm, * pNet; int LineLength; int AddedLength; int NameCounter; @@ -148,20 +176,44 @@ void Io_NtkWritePis( FILE * pFile, Abc_Ntk_t * pNtk ) LineLength = 7; NameCounter = 0; - Abc_NtkForEachPi( pNtk, pNet, i ) + + if ( fWriteLatches ) { - // get the line length after this name is written - AddedLength = strlen(Abc_ObjName(pNet)) + 1; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; + Abc_NtkForEachPi( pNtk, pTerm, i ) + { + pNet = Abc_ObjFanout0(pTerm); + // get the line length after this name is written + AddedLength = strlen(Abc_ObjName(pNet)) + 1; + if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) + { // write the line extender + fprintf( pFile, " \\\n" ); + // reset the line length + LineLength = 0; + NameCounter = 0; + } + fprintf( pFile, " %s", Abc_ObjName(pNet) ); + LineLength += AddedLength; + NameCounter++; + } + } + else + { + Abc_NtkForEachCi( pNtk, pTerm, i ) + { + pNet = Abc_ObjFanout0(pTerm); + // get the line length after this name is written + AddedLength = strlen(Abc_ObjName(pNet)) + 1; + if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) + { // write the line extender + fprintf( pFile, " \\\n" ); + // reset the line length + LineLength = 0; + NameCounter = 0; + } + fprintf( pFile, " %s", Abc_ObjName(pNet) ); + LineLength += AddedLength; + NameCounter++; } - fprintf( pFile, " %s", Abc_ObjName(pNet) ); - LineLength += AddedLength; - NameCounter++; } } @@ -176,9 +228,9 @@ void Io_NtkWritePis( FILE * pFile, Abc_Ntk_t * pNtk ) SeeAlso [] ***********************************************************************/ -void Io_NtkWritePos( FILE * pFile, Abc_Ntk_t * pNtk ) +void Io_NtkWritePos( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ) { - Abc_Obj_t * pNet; + Abc_Obj_t * pTerm, * pNet; int LineLength; int AddedLength; int NameCounter; @@ -186,20 +238,44 @@ void Io_NtkWritePos( FILE * pFile, Abc_Ntk_t * pNtk ) LineLength = 8; NameCounter = 0; - Abc_NtkForEachPo( pNtk, pNet, i ) + + if ( fWriteLatches ) { - // get the line length after this name is written - AddedLength = strlen(Abc_ObjName(pNet)) + 1; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; + Abc_NtkForEachPo( pNtk, pTerm, i ) + { + pNet = Abc_ObjFanin0(pTerm); + // get the line length after this name is written + AddedLength = strlen(Abc_ObjName(pNet)) + 1; + if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) + { // write the line extender + fprintf( pFile, " \\\n" ); + // reset the line length + LineLength = 0; + NameCounter = 0; + } + fprintf( pFile, " %s", Abc_ObjName(pNet) ); + LineLength += AddedLength; + NameCounter++; + } + } + else + { + Abc_NtkForEachCo( pNtk, pTerm, i ) + { + pNet = Abc_ObjFanin0(pTerm); + // get the line length after this name is written + AddedLength = strlen(Abc_ObjName(pNet)) + 1; + if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) + { // write the line extender + fprintf( pFile, " \\\n" ); + // reset the line length + LineLength = 0; + NameCounter = 0; + } + fprintf( pFile, " %s", Abc_ObjName(pNet) ); + LineLength += AddedLength; + NameCounter++; } - fprintf( pFile, " %s", Abc_ObjName(pNet) ); - LineLength += AddedLength; - NameCounter++; } } @@ -224,8 +300,8 @@ void Io_NtkWriteLatch( FILE * pFile, Abc_Obj_t * pLatch ) Reset = (int)Abc_ObjData( pLatch ); // write the latch line fprintf( pFile, ".latch" ); - fprintf( pFile, " %10s", Abc_ObjName(pNetLi) ); - fprintf( pFile, " %10s", Abc_ObjName(pNetLo) ); + fprintf( pFile, " %10s", Abc_ObjName(pNetLi) ); + fprintf( pFile, " %10s", Abc_ObjName(pNetLo) ); fprintf( pFile, " %d\n", Reset ); } @@ -243,12 +319,46 @@ void Io_NtkWriteLatch( FILE * pFile, Abc_Obj_t * pLatch ) ***********************************************************************/ void Io_NtkWriteNode( FILE * pFile, Abc_Obj_t * pNode ) { - // write the .names line - fprintf( pFile, ".names" ); - Io_NtkWriteNodeFanins( pFile, pNode ); - fprintf( pFile, "\n" ); - // write the cubes - fprintf( pFile, "%s", Abc_ObjData(pNode) ); + if ( Abc_NtkIsNetlistMap(pNode->pNtk) ) + { + // write the .gate line + fprintf( pFile, ".gate" ); + Io_NtkWriteNodeGate( pFile, pNode ); + fprintf( pFile, "\n" ); + } + else + { + // write the .names line + fprintf( pFile, ".names" ); + Io_NtkWriteNodeFanins( pFile, pNode ); + fprintf( pFile, "\n" ); + // write the cubes + fprintf( pFile, "%s", Abc_ObjData(pNode) ); + } +} + +/**Function************************************************************* + + Synopsis [Writes the primary input list.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +void Io_NtkWriteNodeGate( FILE * pFile, Abc_Obj_t * pNode ) +{ + Mio_Gate_t * pGate = pNode->pData; + Mio_Pin_t * pGatePin; + int i; + // write the node + fprintf( pFile, " %s ", Mio_GateReadName(pGate) ); + for ( pGatePin = Mio_GateReadPins(pGate), i = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), i++ ) + fprintf( pFile, "%s=%s ", Mio_PinReadName(pGatePin), Abc_ObjName( Abc_ObjFanin(pNode,i) ) ); + assert ( i == Abc_ObjFaninNum(pNode) ); + fprintf( pFile, "%s=%s", Mio_GateReadOutName(pGate), Abc_ObjName(pNode) ); } /**Function************************************************************* @@ -332,7 +442,7 @@ void Io_WriteTimingInfo( FILE * pFile, Abc_Ntk_t * pNtk ) pTime = Abc_NodeReadArrival(pNode); if ( pTime->Rise == pTimeDef->Rise && pTime->Fall == pTimeDef->Fall ) continue; - fprintf( pFile, ".input_arrival %s %g %g\n", Abc_NtkNamePi(pNtk,i), pTime->Rise, pTime->Fall ); + fprintf( pFile, ".input_arrival %s %g %g\n", Abc_ObjName(pNode), pTime->Rise, pTime->Fall ); } } diff --git a/src/base/io/ioWriteBlifLogic.c b/src/base/io/ioWriteBlifLogic.c deleted file mode 100644 index aa1d65b9..00000000 --- a/src/base/io/ioWriteBlifLogic.c +++ /dev/null @@ -1,402 +0,0 @@ -/**CFile**************************************************************** - - FileName [ioWriteBlifLogic.c] - - SystemName [ABC: Logic synthesis and verification system.] - - PackageName [Command processing package.] - - Synopsis [Procedures to write BLIF files for a logic network.] - - Author [Alan Mishchenko] - - Affiliation [UC Berkeley] - - Date [Ver. 1.0. Started - June 20, 2005.] - - Revision [$Id: ioWriteBlifLogic.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $] - -***********************************************************************/ - -#include "io.h" - -//////////////////////////////////////////////////////////////////////// -/// DECLARATIONS /// -//////////////////////////////////////////////////////////////////////// - -static void Io_LogicWriteOne( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ); -static void Io_LogicWritePis( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ); -static void Io_LogicWritePos( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ); -static void Io_LogicWriteNodeFanins( FILE * pFile, Abc_Obj_t * pNode, int fMark ); -static void Io_LogicWriteNode( FILE * pFile, Abc_Obj_t * pNode ); - -//////////////////////////////////////////////////////////////////////// -/// FUNCTION DEFITIONS /// -//////////////////////////////////////////////////////////////////////// - -/**Function************************************************************* - - Synopsis [Write the network into a BLIF file with the given name.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteBlifLogic( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) -{ - Abc_Ntk_t * pExdc; - FILE * pFile; - assert( !Abc_NtkIsNetlist(pNtk) ); - pFile = fopen( FileName, "w" ); - if ( pFile == NULL ) - { - fprintf( stdout, "Io_WriteBlifLogic(): Cannot open the output file.\n" ); - return; - } - // write the model name - fprintf( pFile, ".model %s\n", Abc_NtkName(pNtk) ); - // write the network - Io_LogicWriteOne( pFile, pNtk, fWriteLatches ); - // write EXDC network if it exists - pExdc = Abc_NtkExdc( pNtk ); - if ( pExdc ) - { - fprintf( pFile, "\n" ); - fprintf( pFile, ".exdc\n" ); - Io_LogicWriteOne( pFile, pExdc, 0 ); - } - // finalize the file - fprintf( pFile, ".end\n" ); - fclose( pFile ); -} - -/**Function************************************************************* - - Synopsis [Write one network.] - - Description [Writes a network composed of PIs, POs, internal nodes, - and latches. The following rules are used to print the names of - internal nodes: ] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_LogicWriteOne( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ) -{ - ProgressBar * pProgress; - Abc_Obj_t * pNode, * pLatch, * pDriver; - Vec_Ptr_t * vNodes; - int i; - - assert( Abc_NtkIsLogicSop(pNtk) || Abc_NtkIsAig(pNtk) ); - - // print a warning about choice nodes - if ( i = Abc_NtkCountChoiceNodes( pNtk ) ) - printf( "Warning: The AIG is written into the file, including %d choice nodes.\n", i ); - - // write the PIs - fprintf( pFile, ".inputs" ); - Io_LogicWritePis( pFile, pNtk, fWriteLatches ); - fprintf( pFile, "\n" ); - - // write the POs - fprintf( pFile, ".outputs" ); - Io_LogicWritePos( pFile, pNtk, fWriteLatches ); - fprintf( pFile, "\n" ); - - if ( fWriteLatches ) - { - // write the timing info - Io_WriteTimingInfo( pFile, pNtk ); - // write the latches - if ( Abc_NtkLatchNum(pNtk) ) - { - fprintf( pFile, "\n" ); - Abc_NtkForEachLatch( pNtk, pLatch, i ) - fprintf( pFile, ".latch %10s %10s %d\n", - Abc_NtkNameLatchInput(pNtk,i), Abc_NtkNameLatch(pNtk,i), (int)pLatch->pData ); - fprintf( pFile, "\n" ); - } - } - - // set the node names - Abc_NtkLogicTransferNames( pNtk ); - - // collect internal nodes - if ( Abc_NtkIsAig(pNtk) ) - vNodes = Abc_AigDfs( pNtk ); - else - vNodes = Abc_NtkDfs( pNtk ); - // write internal nodes - pProgress = Extra_ProgressBarStart( stdout, vNodes->nSize ); - for ( i = 0; i < vNodes->nSize; i++ ) - { - Extra_ProgressBarUpdate( pProgress, i, NULL ); - Io_LogicWriteNode( pFile, Vec_PtrEntry(vNodes, i) ); - } - Extra_ProgressBarStop( pProgress ); - Vec_PtrFree( vNodes ); - - // write inverters/buffers for each CO - Abc_NtkForEachLatch( pNtk, pLatch, i ) - { - pDriver = Abc_ObjFanin0(pLatch); - // consider the case when the latch is driving itself - if ( pDriver == pLatch ) - { - fprintf( pFile, ".names %s %s\n%d 1\n", - Abc_NtkNameLatch(pNtk,i), Abc_NtkNameLatchInput(pNtk,i), !Abc_ObjFaninC0(pLatch) ); - continue; - } - // skip if they have the same name - if ( pDriver->pCopy && strcmp( (char *)pDriver->pCopy, Abc_NtkNameLatchInput(pNtk,i) ) == 0 ) - { - /* - Abc_Obj_t * pFanout; - int k; - printf( "latch name = %s.\n", (char *)pLatch->pCopy ); - printf( "driver name = %s.\n", (char *)pDriver->pCopy ); - Abc_ObjForEachFanout( pDriver, pFanout, k ) - printf( "driver's fanout name = %s. Fanins = %d. Compl0 = %d. \n", - Abc_ObjName(pFanout), Abc_ObjFaninNum(pFanout), Abc_ObjFaninC0(pFanout) ); - */ - assert( !Abc_ObjFaninC0(pLatch) ); - continue; - } - // write inverter/buffer depending on whether the edge is complemented - fprintf( pFile, ".names %s %s\n%d 1\n", - Abc_ObjName(pDriver), Abc_NtkNameLatchInput(pNtk,i), !Abc_ObjFaninC0(pLatch) ); - } - Abc_NtkForEachPo( pNtk, pNode, i ) - { - pDriver = Abc_ObjFanin0(pNode); - // skip if they have the same name - if ( pDriver->pCopy && strcmp( (char *)pDriver->pCopy, Abc_NtkNamePo(pNtk,i) ) == 0 ) - { - assert( !Abc_ObjFaninC0(pNode) ); - continue; - } - // write inverter/buffer depending on whether the PO is complemented - fprintf( pFile, ".names %s %s\n%d 1\n", - Abc_ObjName(pDriver), Abc_NtkNamePo(pNtk,i), !Abc_ObjFaninC0(pNode) ); - } - Abc_NtkCleanCopy( pNtk ); -} - - -/**Function************************************************************* - - Synopsis [Writes the primary input list.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_LogicWritePis( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ) -{ - char * pName; - int LineLength; - int AddedLength; - int NameCounter; - int nLimit; - int i; - - LineLength = 7; - NameCounter = 0; - nLimit = fWriteLatches? Abc_NtkPiNum(pNtk) : Abc_NtkCiNum(pNtk); - for ( i = 0; i < nLimit; i++ ) - { - pName = pNtk->vNamesPi->pArray[i]; - // get the line length after this name is written - AddedLength = strlen(pName) + 1; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; - } - fprintf( pFile, " %s", pName ); - LineLength += AddedLength; - NameCounter++; - } -} - -/**Function************************************************************* - - Synopsis [Writes the primary input list.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_LogicWritePos( FILE * pFile, Abc_Ntk_t * pNtk, int fWriteLatches ) -{ - char * pName; - int LineLength; - int AddedLength; - int NameCounter; - int nLimit; - int i; - - LineLength = 8; - NameCounter = 0; - nLimit = fWriteLatches? Abc_NtkPoNum(pNtk) : Abc_NtkCoNum(pNtk); - for ( i = 0; i < nLimit; i++ ) - { - pName = pNtk->vNamesPo->pArray[i]; - // get the line length after this name is written - AddedLength = strlen(pName) + 1; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; - } - fprintf( pFile, " %s", pName ); - LineLength += AddedLength; - NameCounter++; - } -} - - -/**Function************************************************************* - - Synopsis [Write the node into a file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_LogicWriteNode( FILE * pFile, Abc_Obj_t * pNode ) -{ - Abc_Obj_t * pTemp; - int i, k, nFanins, fMark; - - assert( !Abc_ObjIsComplement( pNode ) ); - assert( Abc_ObjIsNode(pNode) ); - - // set the mark that is true if the node is a choice node - fMark = Abc_NtkIsAig(pNode->pNtk) && Abc_NodeIsChoice(pNode); - - // write the .names line - fprintf( pFile, ".names" ); - Io_LogicWriteNodeFanins( pFile, pNode, fMark ); - fprintf( pFile, "\n" ); - // write the cubes - if ( Abc_NtkIsLogicSop(pNode->pNtk) ) - fprintf( pFile, "%s", Abc_ObjData(pNode) ); - else if ( Abc_NtkIsAig(pNode->pNtk) ) - { - if ( pNode == Abc_AigConst1(pNode->pNtk->pManFunc) ) - { - fprintf( pFile, " 1\n" ); - return; - } - - assert( Abc_ObjFaninNum(pNode) == 2 ); - // write the AND gate - for ( i = 0; i < 2; i++ ) - fprintf( pFile, "%d", !Abc_ObjFaninC(pNode,i) ); - fprintf( pFile, " 1\n" ); - // write the choice node if present - if ( fMark ) - { - // count the number of fanins of the choice node and write the names line - nFanins = 1; - fprintf( pFile, ".names %sc", Abc_ObjName(pNode) ); - for ( pTemp = pNode->pData; pTemp; pTemp = pTemp->pData, nFanins++ ) - fprintf( pFile, " %s", Abc_ObjName(pTemp) ); - fprintf( pFile, " %s\n", Abc_ObjName(pNode) ); - // write the cubes for each of the fanins - for ( i = 0, pTemp = pNode; pTemp; pTemp = pTemp->pData, i++ ) - { - for ( k = 0; k < nFanins; k++ ) - if ( k == i ) - fprintf( pFile, "%d", (int)(pNode->fPhase == pTemp->fPhase) ); - else - fprintf( pFile, "-" ); - fprintf( pFile, " 1\n" ); - } - } - } - else - { - assert( 0 ); - } -} - -/**Function************************************************************* - - Synopsis [Writes the primary input list.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_LogicWriteNodeFanins( FILE * pFile, Abc_Obj_t * pNode, int fMark ) -{ - Abc_Obj_t * pFanin; - int LineLength; - int AddedLength; - int NameCounter; - char * pName; - int i; - - LineLength = 6; - NameCounter = 0; - Abc_ObjForEachFanin( pNode, pFanin, i ) - { - // get the fanin name - pName = Abc_ObjName(pFanin); - // get the line length after the fanin name is written - AddedLength = strlen(pName) + 1; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; - } - fprintf( pFile, " %s", pName ); - LineLength += AddedLength; - NameCounter++; - } - - // get the output name - pName = Abc_ObjName(pNode); - // get the line length after the output name is written - AddedLength = strlen(pName) + 1; - if ( NameCounter && LineLength + AddedLength > 75 ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; - } - fprintf( pFile, " %s%s", pName, fMark? "c" : "" ); -} - -//////////////////////////////////////////////////////////////////////// -/// END OF FILE /// -//////////////////////////////////////////////////////////////////////// - - diff --git a/src/base/io/ioWriteGate.c b/src/base/io/ioWriteGate.c deleted file mode 100644 index 3a3c45eb..00000000 --- a/src/base/io/ioWriteGate.c +++ /dev/null @@ -1,263 +0,0 @@ -/**CFile**************************************************************** - - FileName [ioWriteGate.c] - - SystemName [ABC: Logic synthesis and verification system.] - - PackageName [Command processing package.] - - Synopsis [Procedures to write the mapped network.] - - Author [Alan Mishchenko] - - Affiliation [UC Berkeley] - - Date [Ver. 1.0. Started - June 20, 2005.] - - Revision [$Id: ioWriteGate.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $] - -***********************************************************************/ - -#include "io.h" -#include "main.h" -#include "mio.h" - -//////////////////////////////////////////////////////////////////////// -/// DECLARATIONS /// -//////////////////////////////////////////////////////////////////////// - -static void Io_WriteGateOne( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_WriteGatePis( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_WriteGatePos( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_WriteGateNode( FILE * pFile, Abc_Obj_t * pNode, Mio_Gate_t * pGate ); -static char * Io_ReadNodeName( Abc_Obj_t * pNode ); - -//////////////////////////////////////////////////////////////////////// -/// FUNCTION DEFITIONS /// -//////////////////////////////////////////////////////////////////////// - -/**Function************************************************************* - - Synopsis [Writes mapped network into a BLIF file compatible with SIS.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int Io_WriteGate( Abc_Ntk_t * pNtk, char * pFileName ) -{ - Abc_Ntk_t * pExdc; - FILE * pFile; - - assert( Abc_NtkIsLogicMap(pNtk) ); - pFile = fopen( pFileName, "w" ); - if ( pFile == NULL ) - { - fprintf( stdout, "Io_WriteGate(): Cannot open the output file.\n" ); - return 0; - } - // write the model name - fprintf( pFile, ".model %s\n", Abc_NtkName(pNtk) ); - // write the network - Io_WriteGateOne( pFile, pNtk ); - // write EXDC network if it exists - pExdc = Abc_NtkExdc( pNtk ); - if ( pExdc ) - printf( "Io_WriteGate: EXDC is not written (warning).\n" ); - // finalize the file - fprintf( pFile, ".end\n" ); - fclose( pFile ); - return 1; -} - -/**Function************************************************************* - - Synopsis [Write one network.] - - Description [Writes a network composed of PIs, POs, internal nodes, - and latches. The following rules are used to print the names of - internal nodes: ] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteGateOne( FILE * pFile, Abc_Ntk_t * pNtk ) -{ - ProgressBar * pProgress; - Abc_Obj_t * pNode, * pLatch; - int i; - - assert( Abc_NtkIsLogicMap(pNtk) ); - assert( Abc_NtkLogicHasSimplePos(pNtk) ); - - // write the PIs - fprintf( pFile, ".inputs" ); - Io_WriteGatePis( pFile, pNtk ); - fprintf( pFile, "\n" ); - - // write the POs - fprintf( pFile, ".outputs" ); - Io_WriteGatePos( pFile, pNtk ); - fprintf( pFile, "\n" ); - - // write the timing info - Io_WriteTimingInfo( pFile, pNtk ); - - // write the latches - if ( Abc_NtkLatchNum(pNtk) ) - { - fprintf( pFile, "\n" ); - Abc_NtkForEachLatch( pNtk, pLatch, i ) - fprintf( pFile, ".latch %s %s %d\n", - Abc_NtkNameLatchInput(pNtk,i), Abc_NtkNameLatch(pNtk,i), (int)pLatch->pData ); - fprintf( pFile, "\n" ); - } - // set the node names - Abc_NtkLogicTransferNames( pNtk ); - // write internal nodes - pProgress = Extra_ProgressBarStart( stdout, Abc_NtkNodeNum(pNtk) ); - Abc_NtkForEachNode( pNtk, pNode, i ) - { - Extra_ProgressBarUpdate( pProgress, i, NULL ); - Io_WriteGateNode( pFile, pNode, pNode->pData ); - } - Extra_ProgressBarStop( pProgress ); - Abc_NtkCleanCopy( pNtk ); -} - - -/**Function************************************************************* - - Synopsis [Writes the primary input list.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteGatePis( FILE * pFile, Abc_Ntk_t * pNtk ) -{ - Abc_Obj_t * pNode; - char * pName; - int LineLength; - int AddedLength; - int NameCounter; - int i; - - LineLength = 7; - NameCounter = 0; - Abc_NtkForEachPi( pNtk, pNode, i ) - { - pName = pNtk->vNamesPi->pArray[i]; - // get the line length after this name is written - AddedLength = strlen(pName) + 1; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; - } - fprintf( pFile, " %s", pName ); - LineLength += AddedLength; - NameCounter++; - } -} - -/**Function************************************************************* - - Synopsis [Writes the primary input list.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteGatePos( FILE * pFile, Abc_Ntk_t * pNtk ) -{ - Abc_Obj_t * pNode; - int LineLength; - int AddedLength; - int NameCounter; - char * pName; - int i; - - LineLength = 8; - NameCounter = 0; - Abc_NtkForEachPo( pNtk, pNode, i ) - { - pName = pNtk->vNamesPo->pArray[i]; - // get the line length after this name is written - AddedLength = strlen(pName) + 1; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, " \\\n" ); - // reset the line length - LineLength = 0; - NameCounter = 0; - } - fprintf( pFile, " %s", pName ); - LineLength += AddedLength; - NameCounter++; - } -} - -/**Function************************************************************* - - Synopsis [Write the node into a file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteGateNode( FILE * pFile, Abc_Obj_t * pNode, Mio_Gate_t * pGate ) -{ - Mio_Pin_t * pGatePin; - int i; - // do not write the buffer whose input and output have the same name - if ( Abc_ObjFaninNum(pNode) == 1 && Abc_ObjFanin0(pNode)->pCopy && pNode->pCopy ) - if ( strcmp( (char*)Abc_ObjFanin0(pNode)->pCopy, (char*)pNode->pCopy ) == 0 ) - return; - // write the node - fprintf( pFile, ".gate %s ", Mio_GateReadName(pGate) ); - for ( pGatePin = Mio_GateReadPins(pGate), i = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), i++ ) - fprintf( pFile, "%s=%s ", Mio_PinReadName(pGatePin), Io_ReadNodeName( Abc_ObjFanin(pNode,i) ) ); - assert ( i == Abc_ObjFaninNum(pNode) ); - fprintf( pFile, "%s=%s\n", Mio_GateReadOutName(pGate), Io_ReadNodeName(pNode) ); -} - -/**Function************************************************************* - - Synopsis [Returns the name of the node to write.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -char * Io_ReadNodeName( Abc_Obj_t * pNode ) -{ - if ( pNode->pCopy ) - return (char *)pNode->pCopy; - return Abc_ObjName(pNode); -} - -//////////////////////////////////////////////////////////////////////// -/// END OF FILE /// -//////////////////////////////////////////////////////////////////////// - - diff --git a/src/base/io/ioWritePla.c b/src/base/io/ioWritePla.c index 01d2f59b..48e358e3 100644 --- a/src/base/io/ioWritePla.c +++ b/src/base/io/ioWritePla.c @@ -46,7 +46,7 @@ int Io_WritePla( Abc_Ntk_t * pNtk, char * pFileName ) Abc_Ntk_t * pExdc; FILE * pFile; - assert( Abc_NtkIsLogicSop(pNtk) ); + assert( Abc_NtkIsNetlistSop(pNtk) ); assert( Abc_NtkGetLevelNum(pNtk) == 1 ); pFile = fopen( pFileName, "w" ); @@ -61,12 +61,7 @@ int Io_WritePla( Abc_Ntk_t * pNtk, char * pFileName ) // write EXDC network if it exists pExdc = Abc_NtkExdc( pNtk ); if ( pExdc ) - { printf( "Io_WritePla: EXDC is not written (warning).\n" ); -// fprintf( pFile, "\n" ); -// fprintf( pFile, ".exdc\n" ); -// Io_LogicWriteOne( pFile, pExdc ); - } // finalize the file fclose( pFile ); return 1; @@ -91,9 +86,9 @@ int Io_WritePlaOne( FILE * pFile, Abc_Ntk_t * pNtk ) int i, k, nProducts, nInputs, nOutputs, nFanins; nProducts = 0; - Abc_NtkForEachPo( pNtk, pNode, i ) + Abc_NtkForEachCo( pNtk, pNode, i ) { - pDriver = Abc_ObjFanin0(pNode); + pDriver = Abc_ObjFanin0Ntk(pNode); if ( !Abc_ObjIsNode(pDriver) ) { nProducts++; @@ -121,11 +116,11 @@ int Io_WritePlaOne( FILE * pFile, Abc_Ntk_t * pNtk ) fprintf( pFile, ".o %d\n", nOutputs ); fprintf( pFile, ".ilb" ); Abc_NtkForEachCi( pNtk, pNode, i ) - fprintf( pFile, " %s", Abc_NtkNameCi(pNtk, i) ); + fprintf( pFile, " %s", Abc_ObjName(Abc_ObjFanout0(pNode)) ); fprintf( pFile, "\n" ); fprintf( pFile, ".ob" ); Abc_NtkForEachCo( pNtk, pNode, i ) - fprintf( pFile, " %s", Abc_NtkNameCo(pNtk, i) ); + fprintf( pFile, " %s", Abc_ObjName(Abc_ObjFanin0(pNode)) ); fprintf( pFile, "\n" ); fprintf( pFile, ".p %d\n", nProducts ); @@ -143,7 +138,7 @@ int Io_WritePlaOne( FILE * pFile, Abc_Ntk_t * pNtk ) pCubeOut[i] = '1'; // consider special cases of nodes - pDriver = Abc_ObjFanin0(pNode); + pDriver = Abc_ObjFanin0Ntk(pNode); if ( !Abc_ObjIsNode(pDriver) ) { pCubeIn[(int)pDriver->pCopy] = '1' - Abc_ObjFaninC0(pNode); diff --git a/src/base/io/module.make b/src/base/io/module.make index 3e5be57a..899f8166 100644 --- a/src/base/io/module.make +++ b/src/base/io/module.make @@ -4,9 +4,8 @@ SRC += src/base/io/io.c \ src/base/io/ioReadBlif.c \ src/base/io/ioReadPla.c \ src/base/io/ioReadVerilog.c \ + src/base/io/ioUtil.c \ src/base/io/ioWriteBench.c \ src/base/io/ioWriteBlif.c \ - src/base/io/ioWriteBlifLogic.c \ src/base/io/ioWriteCnf.c \ - src/base/io/ioWriteGate.c \ src/base/io/ioWritePla.c |