Version abc71226

4 files changed, 140 insertions, 44 deletions

diff --git a/src/aig/ntl/ntl.h b/src/aig/ntl/ntl.h
index ab93895d..1a3695e8 100644
--- a/src/aig/ntl/ntl.h
+++ b/src/aig/ntl/ntl.h
@@ -30,6 +30,7 @@ extern "C" {
 ////////////////////////////////////////////////////////////////////////
 
 #include "aig.h"
+#include "tim.h"
 
 ////////////////////////////////////////////////////////////////////////
 ///                         PARAMETERS                               ///
@@ -70,7 +71,7 @@ struct Ntl_Man_t_
     Vec_Ptr_t *        vCos;           // the primary outputs of the extracted part 
     Vec_Ptr_t *        vNodes;         // the nodes of the abstracted part
     Aig_Man_t *        pAig;           // the extracted AIG
-    Aig_TMan_t *       pManTime;       // the timing manager
+    Tim_Man_t *        pManTime;       // the timing manager
 };
 
 struct Ntl_Mod_t_
@@ -219,6 +220,8 @@ static inline void        Ntl_ObjSetFanout( Ntl_Obj_t * p, Ntl_Net_t * pNet, int
 extern int             Ntl_ManExtract( Ntl_Man_t * p );
 extern int             Ntl_ManInsert( Ntl_Man_t * p, Vec_Ptr_t * vMapping );
 extern int             Ntl_ManInsertTest( Ntl_Man_t * p );
+extern int             Ntl_ManInsertTestFpga( Ntl_Man_t * p );
+extern int             Ntl_ManInsertTestIf( Ntl_Man_t * p );
 /*=== ntlCheck.c ==========================================================*/
 extern int             Ntl_ManCheck( Ntl_Man_t * pMan );
 extern int             Ntl_ModelCheck( Ntl_Mod_t * pModel );
@@ -235,6 +238,8 @@ extern void            Ntl_ModelFree( Ntl_Mod_t * p );
 /*=== ntlMap.c ============================================================*/
 extern Vec_Ptr_t *     Ntl_MappingAlloc( int nLuts, int nVars );
 extern Vec_Ptr_t *     Ntl_MappingFromAig( Aig_Man_t * p );
+extern Vec_Ptr_t *     Ntl_MappingFpga( Aig_Man_t * p );
+extern Vec_Ptr_t *     Ntl_MappingIf( Aig_Man_t * p );
 /*=== ntlObj.c ============================================================*/
 extern Ntl_Obj_t *     Ntl_ModelCreatePi( Ntl_Mod_t * pModel );
 extern Ntl_Obj_t *     Ntl_ModelCreatePo( Ntl_Mod_t * pModel, Ntl_Net_t * pNet );
diff --git a/src/aig/ntl/ntlAig.c b/src/aig/ntl/ntlAig.c
index bc8a8c35..c81280d7 100644
--- a/src/aig/ntl/ntlAig.c
+++ b/src/aig/ntl/ntlAig.c
@@ -413,27 +413,33 @@ int Ntl_ManInsert( Ntl_Man_t * p, Vec_Ptr_t * vMapping )
     Ntl_Net_t * pNet, * pNetCo;
     Ntl_Lut_t * pLut;
     int i, k, nDigits;
-    nDigits = Aig_Base10Log( Vec_PtrSize(vMapping) );
+    // remove old nodes
+    pRoot = Vec_PtrEntry( p->vModels, 0 );
+    Ntl_ModelForEachNode( pRoot, pNode, i )
+        Vec_PtrWriteEntry( pRoot->vObjs, pNode->Id, NULL );
     // start mapping of AIG nodes into their copies
     vCopies = Vec_PtrStart( Aig_ManObjNumMax(p->pAig) );
     Ntl_ManForEachCiNet( p, pNet, i )
         Vec_PtrWriteEntry( vCopies, pNet->pFunc->Id, pNet );
     // create a new node for each LUT
     vCover = Vec_IntAlloc( 1 << 16 );
-    pRoot = Vec_PtrEntry( p->vModels, 0 );
+    nDigits = Aig_Base10Log( Vec_PtrSize(vMapping) );
     Vec_PtrForEachEntry( vMapping, pLut, i )
     {
         pNode = Ntl_ModelCreateNode( pRoot, pLut->nFanins );
         pNode->pSop = Ntl_SopFromTruth( p, pLut->pTruth, pLut->nFanins, vCover );
-        for ( k = 0; k < pLut->nFanins; k++ )
+        if ( !Kit_TruthIsConst0(pLut->pTruth, pLut->nFanins) && !Kit_TruthIsConst1(pLut->pTruth, pLut->nFanins) )
         {
-            pNet = Vec_PtrEntry( vCopies, pLut->pFanins[k] );
-            if ( pNet == NULL )
+            for ( k = 0; k < pLut->nFanins; k++ )
             {
-                printf( "Ntl_ManInsert(): Internal error: Net not found.\n" );
-                return 0;
+                pNet = Vec_PtrEntry( vCopies, pLut->pFanins[k] );
+                if ( pNet == NULL )
+                {
+                    printf( "Ntl_ManInsert(): Internal error: Net not found.\n" );
+                    return 0;
+                }
+                Ntl_ObjSetFanin( pNode, pNet, k );
             }
-            Ntl_ObjSetFanin( pNode, pNet, k );
         }
         sprintf( Buffer, "lut%0*d", nDigits, i );
         if ( (pNet = Ntl_ModelFindNet( pRoot, Buffer )) )
@@ -450,15 +456,18 @@ int Ntl_ManInsert( Ntl_Man_t * p, Vec_Ptr_t * vMapping )
         Vec_PtrWriteEntry( vCopies, pLut->Id, pNet );
     }
     Vec_IntFree( vCover );
-    // remove old nodes
-    Ntl_ManForEachNode( p, pNode, i )
-        Vec_PtrWriteEntry( pRoot->vObjs, pNode->Id, NULL );
+    // mark CIs and outputs of the registers
+    Ntl_ManForEachCiNet( p, pNetCo, i )
+        pNetCo->nVisits = 101;
     // update the CO pointers
     Ntl_ManForEachCoNet( p, pNetCo, i )
     {
+        if ( pNetCo->nVisits == 101 )
+            continue;
+        pNetCo->nVisits = 101;
+        pNet = Vec_PtrEntry( vCopies, Aig_Regular(pNetCo->pFunc)->Id );
         pNode = Ntl_ModelCreateNode( pRoot, 1 );
         pNode->pSop = Aig_IsComplement(pNetCo->pFunc)? Ntl_ManStoreSop( p, "0 1\n" ) : Ntl_ManStoreSop( p, "1 1\n" );
-        pNet = Vec_PtrEntry( vCopies, Aig_Regular(pNetCo->pFunc)->Id );
         Ntl_ObjSetFanin( pNode, pNet, 0 );
         // update the CO driver net
         pNetCo->pDriver = NULL;
@@ -474,6 +483,39 @@ int Ntl_ManInsert( Ntl_Man_t * p, Vec_Ptr_t * vMapping )
 
 /**Function*************************************************************
 
+  Synopsis    [Extracts AIG from the netlist.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ntl_ManPerformSynthesis( Ntl_Man_t * p )
+{
+    extern Aig_Man_t * Dar_ManBalance( Aig_Man_t * p, int fUpdateLevel );
+    extern Aig_Man_t * Dar_ManCompress( Aig_Man_t * pAig, int fBalance, int fUpdateLevel, int fVerbose );
+    Aig_Man_t * pTemp;
+    Ntl_Net_t * pNet;
+    int i;
+    // perform synthesis
+printf( "Pre-synthesis AIG:  " );
+Aig_ManPrintStats( p->pAig );
+//    p->pAig = Dar_ManBalance( pTemp = p->pAig, 1 );
+    p->pAig = Dar_ManCompress( pTemp = p->pAig, 1, 1, 0 );
+    Ntl_ManForEachCiNet( p, pNet, i )
+        pNet->pFunc = Aig_ManPi( p->pAig, i );
+    Ntl_ManForEachCoNet( p, pNet, i )
+        pNet->pFunc = Aig_ObjChild0( Aig_ManPo( p->pAig, i ) );
+    Aig_ManStop( pTemp );
+printf( "Post-synthesis AIG: " );
+Aig_ManPrintStats( p->pAig );
+    return 1;
+}
+
+/**Function*************************************************************
+
   Synopsis    [Testing procedure for insertion of mapping into the netlist.]
 
   Description []
@@ -490,12 +532,38 @@ int Ntl_ManInsertTest( Ntl_Man_t * p )
     if ( !Ntl_ManExtract( p ) )
         return 0;
     assert( p->pAig != NULL );
+    Ntl_ManPerformSynthesis( p );
     vMapping = Ntl_MappingFromAig( p->pAig );
     RetValue = Ntl_ManInsert( p, vMapping );
     Vec_PtrFree( vMapping );
     return RetValue;
 }
 
+/**Function*************************************************************
+
+  Synopsis    [Testing procedure for insertion of mapping into the netlist.]
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+int Ntl_ManInsertTestIf( Ntl_Man_t * p )
+{
+    Vec_Ptr_t * vMapping;
+    int RetValue;
+    if ( !Ntl_ManExtract( p ) )
+        return 0;
+    assert( p->pAig != NULL );
+    Ntl_ManPerformSynthesis( p );
+    vMapping = Ntl_MappingIf( p->pAig );
+    RetValue = Ntl_ManInsert( p, vMapping );
+    Vec_PtrFree( vMapping );
+    return RetValue;
+}
+
 
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
diff --git a/src/aig/ntl/ntlMap.c b/src/aig/ntl/ntlMap.c
index 7ee0fba0..d4c7d81b 100644
--- a/src/aig/ntl/ntlMap.c
+++ b/src/aig/ntl/ntlMap.c
@@ -246,7 +246,7 @@ Vec_Ptr_t * Ntl_ManFromFpga( Aig_Man_t * p, Fpga_Man_t * pMan )
     Aig_Obj_t * pObj;
     Ntl_Lut_t * pLut;
     unsigned * pTruth;
-    int i, k = 0, nLeaves, nWords, nVarsMax;
+    int i, k, nLuts, nLeaves, nWords, nVarsMax;
     // create mapping of FPGA nodes into AIG nodes
     vFpgaToAig = Vec_IntStart( Aig_ManObjNumMax(p) );
     Vec_IntFill( vFpgaToAig, Aig_ManObjNumMax(p), -1 );
@@ -254,18 +254,26 @@ Vec_Ptr_t * Ntl_ManFromFpga( Aig_Man_t * p, Fpga_Man_t * pMan )
     {
         if ( Aig_ObjIsPo(pObj) )
             continue;
+        if ( Aig_ObjIsConst1(pObj) && pObj->pData == NULL )
+            continue;
         pNode = pObj->pData;
         assert( pNode != NULL );
         Vec_IntWriteEntry( vFpgaToAig, Fpga_NodeReadNum(pNode), pObj->Id );
     }
     // create the mapping
+
+
+    // make sure nodes are in the top order!!!
+
+
     nVarsMax = Fpga_ManReadVarMax( pMan );
     nWords   = Aig_TruthWordNum( nVarsMax );
     vFpgaMap = Fpga_ManReadMapping( pMan );
     vMapping = Ntl_MappingAlloc( vFpgaMap->nSize + (int)(Aig_ManConst1(p)->nRefs > 0), nVarsMax );
+    nLuts    = 0;
     if ( Aig_ManConst1(p)->nRefs > 0 )
     {
-        pLut = Vec_PtrEntry( vMapping, k++ );
+        pLut = Vec_PtrEntry( vMapping, nLuts++ );
         pLut->Id = 0;
         pLut->nFanins = 0;
         memset( pLut->pTruth, 0xFF, 4 * nWords );
@@ -281,7 +289,7 @@ Vec_Ptr_t * Ntl_ManFromFpga( Aig_Man_t * p, Fpga_Man_t * pMan )
         nLeaves  = Fpga_CutReadLeavesNum( pCutBest ); 
         ppLeaves = Fpga_CutReadLeaves( pCutBest );
         // fill the LUT
-        pLut = Vec_PtrEntry( vMapping, k++ );
+        pLut = Vec_PtrEntry( vMapping, nLuts++ );
         pLut->Id = Vec_IntEntry( vFpgaToAig, Fpga_NodeReadNum(pNode) );
         pLut->nFanins = nLeaves;
         for ( k = 0; k < nLeaves; k++ )
@@ -290,7 +298,7 @@ Vec_Ptr_t * Ntl_ManFromFpga( Aig_Man_t * p, Fpga_Man_t * pMan )
         pTruth = Ntl_FpgaComputeTruth( pCutBest, vTruthElem, vTruthStore, vVisited, nVarsMax );
         memcpy( pLut->pTruth, pTruth, 4 * nWords );
     }
-    assert( k == Vec_PtrSize(vMapping) );
+    assert( nLuts == Vec_PtrSize(vMapping) );
     Vec_IntFree( vFpgaToAig );
     Vec_PtrFree( vVisited );
     Vec_PtrFree( vTruthElem );
@@ -309,13 +317,13 @@ Vec_Ptr_t * Ntl_ManFromFpga( Aig_Man_t * p, Fpga_Man_t * pMan )
   SeeAlso     []
 
 ***********************************************************************/
-Vec_Ptr_t * Ntl_ManFpga( Aig_Man_t * p )
+Vec_Ptr_t * Ntl_MappingFpga( Aig_Man_t * p )
 {
     Vec_Ptr_t * vMapping;
     Fpga_Man_t * pMan;
     // print a warning about choice nodes
     if ( p->pEquivs )
-        printf( "Ntl_ManFpga(): Performing FPGA mapping with choices.\n" );
+        printf( "Ntl_MappingFpga(): Performing FPGA mapping with choices.\n" );
     // perform FPGA mapping
     pMan = Ntl_ManToFpga( p );    
     if ( pMan == NULL )
@@ -351,11 +359,12 @@ Vec_Ptr_t * Ntl_ManFpga( Aig_Man_t * p )
 ***********************************************************************/
 void Ntk_ManSetIfParsDefault( If_Par_t * pPars )
 {
-    extern void * Abc_FrameReadLibLut();
+//    extern void * Abc_FrameReadLibLut();
     // set defaults
     memset( pPars, 0, sizeof(If_Par_t) );
     // user-controlable paramters
-    pPars->nLutSize    = -1;
+//    pPars->nLutSize    = -1;
+    pPars->nLutSize    =  6;
     pPars->nCutsMax    =  8;
     pPars->nFlowIters  =  1;
     pPars->nAreaIters  =  2;
@@ -363,21 +372,22 @@ void Ntk_ManSetIfParsDefault( If_Par_t * pPars )
     pPars->fPreprocess =  1;
     pPars->fArea       =  0;
     pPars->fFancy      =  0;
-    pPars->fExpRed     =  1;
+    pPars->fExpRed     =  0;
     pPars->fLatchPaths =  0;
     pPars->fEdge       =  1;
     pPars->fCutMin     =  1;
     pPars->fSeqMap     =  0;
-    pPars->fVerbose    =  0;
+    pPars->fVerbose    =  1;
     // internal parameters
     pPars->fTruth      =  1;
     pPars->nLatches    =  0;
     pPars->fLiftLeaves =  0;
-    pPars->pLutLib     =  Abc_FrameReadLibLut();
+//    pPars->pLutLib     =  Abc_FrameReadLibLut();
+    pPars->pLutLib     =  NULL;
     pPars->pTimesArr   =  NULL; 
     pPars->pTimesArr   =  NULL;   
     pPars->pFuncCost   =  NULL;   
-
+/*
     if ( pPars->nLutSize == -1 )
     {
         if ( pPars->pLutLib == NULL )
@@ -388,6 +398,7 @@ void Ntk_ManSetIfParsDefault( If_Par_t * pPars )
         // get LUT size from the library
         pPars->nLutSize = pPars->pLutLib->LutMax;
     }
+*/
 }
 
 /**Function*************************************************************
@@ -417,16 +428,18 @@ If_Man_t * Ntk_ManToIf( Aig_Man_t * p, If_Par_t * pPars )
     vNodes = Aig_ManDfsPio( p );
     Vec_PtrForEachEntry( vNodes, pNode, i )
     {
-        if ( Aig_ObjIsConst1(pNode) )
-            Aig_ManConst1(p)->pData = If_ManConst1( pIfMan );
+        if ( Aig_ObjIsAnd(pNode) )
+            pNode->pData = (Aig_Obj_t *)If_ManCreateAnd( pIfMan, 
+                If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ), 
+                If_NotCond( (If_Obj_t *)Aig_ObjFanin1(pNode)->pData, Aig_ObjFaninC1(pNode) ) );
         else if ( Aig_ObjIsPi(pNode) )
             pNode->pData = If_ManCreateCi( pIfMan );
         else if ( Aig_ObjIsPo(pNode) )
             If_ManCreateCo( pIfMan, If_NotCond( Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ) );
+        else if ( Aig_ObjIsConst1(pNode) )
+            Aig_ManConst1(p)->pData = If_ManConst1( pIfMan );
         else // add the node to the mapper
-            pNode->pData = (Aig_Obj_t *)If_ManCreateAnd( pIfMan, 
-                If_NotCond( (If_Obj_t *)Aig_ObjFanin0(pNode)->pData, Aig_ObjFaninC0(pNode) ), 
-                If_NotCond( (If_Obj_t *)Aig_ObjFanin1(pNode)->pData, Aig_ObjFaninC1(pNode) ) );
+            assert( 0 );
         // set up the choice node
 //        if ( Aig_AigNodeIsChoice( pNode ) )
 //        {
@@ -461,7 +474,7 @@ Vec_Ptr_t * Ntk_ManFromIf( Aig_Man_t * p, If_Man_t * pMan )
     Aig_Obj_t * pObj;
     Ntl_Lut_t * pLut;
     int * ppLeaves;
-    int i, k = 0, nLeaves, nWords, nVarsMax;
+    int i, k, nLuts, nLeaves, nWords, nVarsMax;
     // create mapping of If nodes into AIG nodes
     vIfToAig = Vec_IntStart( Aig_ManObjNumMax(p) );
     Vec_IntFill( vIfToAig, Aig_ManObjNumMax(p), -1 );
@@ -469,18 +482,24 @@ Vec_Ptr_t * Ntk_ManFromIf( Aig_Man_t * p, If_Man_t * pMan )
     {
         if ( Aig_ObjIsPo(pObj) )
             continue;
+        if ( Aig_ObjIsConst1(pObj) && pObj->pData == NULL )
+            continue;
+        if ( Aig_ObjIsPi(pObj) && pObj->pData == NULL )
+            continue;
         pNode = pObj->pData;
         assert( pNode != NULL );
         Vec_IntWriteEntry( vIfToAig, pNode->Id, pObj->Id );
     }
     // create the mapping
+    If_ManScanMappingDirect( pMan );
     nVarsMax = pMan->pPars->nLutSize;
     nWords   = Aig_TruthWordNum( nVarsMax );
     vIfMap   = pMan->vMapped;
     vMapping = Ntl_MappingAlloc( Vec_PtrSize(vIfMap) + (int)(Aig_ManConst1(p)->nRefs > 0), nVarsMax );
+    nLuts    = 0;
     if ( Aig_ManConst1(p)->nRefs > 0 )
     {
-        pLut = Vec_PtrEntry( vMapping, k++ );
+        pLut = Vec_PtrEntry( vMapping, nLuts++ );
         pLut->Id = 0;
         pLut->nFanins = 0;
         memset( pLut->pTruth, 0xFF, 4 * nWords );
@@ -492,7 +511,7 @@ Vec_Ptr_t * Ntk_ManFromIf( Aig_Man_t * p, If_Man_t * pMan )
         nLeaves  = If_CutLeaveNum( pCutBest ); 
         ppLeaves = If_CutLeaves( pCutBest );
         // fill the LUT
-        pLut = Vec_PtrEntry( vMapping, k++ );
+        pLut = Vec_PtrEntry( vMapping, nLuts++ );
         pLut->Id = Vec_IntEntry( vIfToAig, pNode->Id );
         pLut->nFanins = nLeaves;
         If_CutForEachLeaf( pMan, pCutBest, pLeaf, k )
@@ -500,7 +519,7 @@ Vec_Ptr_t * Ntk_ManFromIf( Aig_Man_t * p, If_Man_t * pMan )
         // compute the truth table
         memcpy( pLut->pTruth, If_CutTruth(pCutBest), 4 * nWords );
     }
-    assert( k == Vec_PtrSize(vMapping) );
+    assert( nLuts == Vec_PtrSize(vMapping) );
     Vec_IntFree( vIfToAig );
     return vMapping;
 }
@@ -516,13 +535,17 @@ Vec_Ptr_t * Ntk_ManFromIf( Aig_Man_t * p, If_Man_t * pMan )
   SeeAlso     []
 
 ***********************************************************************/
-Vec_Ptr_t * Ntk_ManIf( Aig_Man_t * p )
+Vec_Ptr_t * Ntl_MappingIf( Aig_Man_t * p )
 {
     Vec_Ptr_t * vMapping;
     If_Par_t Pars, * pPars = &Pars;
     If_Man_t * pIfMan;
     // perform FPGA mapping
     Ntk_ManSetIfParsDefault( pPars );
+    // set the arrival times
+    pPars->pTimesArr = ALLOC( float, Aig_ManPiNum(p) );
+    memset( pPars->pTimesArr, 0, sizeof(float) * Aig_ManPiNum(p) );
+    // translate into the mapper
     pIfMan = Ntk_ManToIf( p, pPars );    
     if ( pIfMan == NULL )
         return NULL;
diff --git a/src/aig/ntl/ntlTime.c b/src/aig/ntl/ntlTime.c
index d4bd1375..c81686fa 100644
--- a/src/aig/ntl/ntlTime.c
+++ b/src/aig/ntl/ntlTime.c
@@ -76,32 +76,32 @@ float * Ntl_ManCreateDelayTable( Vec_Int_t * vDelays, int nIns, int nOuts )
   SeeAlso     []
 
 ***********************************************************************/
-Aig_TMan_t * Ntl_ManCreateTiming( Ntl_Man_t * p )
+Tim_Man_t * Ntl_ManCreateTiming( Ntl_Man_t * p )
 {
-    Aig_TMan_t * pMan;
+    Tim_Man_t * pMan;
     Vec_Ptr_t * vDelayTables;
     Ntl_Mod_t * pRoot, * pModel;
     Ntl_Obj_t * pObj;
     int i, curPi, curPo, Entry;
     assert( p->pAig != NULL );
     // start the timing manager
-    pMan = Aig_TManStart( Aig_ManPiNum(p->pAig), Aig_ManPoNum(p->pAig) );
+    pMan = Tim_ManStart( Aig_ManPiNum(p->pAig), Aig_ManPoNum(p->pAig) );
     // add arrival time info for the true PIs
     pRoot = Vec_PtrEntry( p->vModels, 0 );
     Ntl_ModelForEachPi( pRoot, pObj, i )
-        Aig_TManInitPiArrival( pMan, i, 0.0 );
+        Tim_ManInitPiArrival( pMan, i, 0.0 );
     // unpack the data in the arrival times
     if ( pRoot->vArrivals )
         Vec_IntForEachEntry( pRoot->vArrivals, Entry, i )
-            Aig_TManInitPiArrival( pMan, Entry, Vec_IntEntry(pRoot->vArrivals,++i) );
+            Tim_ManInitPiArrival( pMan, Entry, Vec_IntEntry(pRoot->vArrivals,++i) );
     // add the required time into for the true POs
     pRoot = Vec_PtrEntry( p->vModels, 0 );
     Ntl_ModelForEachPo( pRoot, pObj, i )
-        Aig_TManInitPoRequired( pMan, i, AIG_INFINITY );
+        Tim_ManInitPoRequired( pMan, i, AIG_INFINITY );
     // unpack the data in the required times
     if ( pRoot->vRequireds )
         Vec_IntForEachEntry( pRoot->vRequireds, Entry, i )
-            Aig_TManInitPoRequired( pMan, Entry, Vec_IntEntry(pRoot->vRequireds,++i) );
+            Tim_ManInitPoRequired( pMan, Entry, Vec_IntEntry(pRoot->vRequireds,++i) );
     // derive timing tables
     vDelayTables = Vec_PtrAlloc( Vec_PtrSize(p->vModels) );
     Ntl_ManForEachModel( p, pModel, i )
@@ -110,13 +110,13 @@ Aig_TMan_t * Ntl_ManCreateTiming( Ntl_Man_t * p )
             pModel->pDelayTable = Ntl_ManCreateDelayTable( pModel->vDelays, Ntl_ModelPiNum(pModel), Ntl_ModelPoNum(pModel) );
         Vec_PtrPush( vDelayTables, pModel->pDelayTable );
     }
-    Aig_TManSetDelayTables( pMan, vDelayTables );
+    Tim_ManSetDelayTables( pMan, vDelayTables );
     // set up the boxes
     curPi = Ntl_ModelPiNum(pRoot);
     curPo = Ntl_ModelPoNum(pRoot);
     Ntl_ManForEachBox( p, pObj, i )
     {
-        Aig_TManCreateBoxFirst( pMan, curPo, Ntl_ObjFanoutNum(pObj), curPi, Ntl_ObjFaninNum(pObj), pObj->pImplem->pDelayTable );
+        Tim_ManCreateBoxFirst( pMan, curPo, Ntl_ObjFanoutNum(pObj), curPi, Ntl_ObjFaninNum(pObj), pObj->pImplem->pDelayTable );
         curPo += Ntl_ObjFanoutNum(pObj);
         curPi += Ntl_ObjFaninNum(pObj);
     }