Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes.

2 files changed, 11 insertions, 11 deletions

diff --git a/src/aig/hop/hop.h b/src/aig/hop/hop.h
index bf9f0c7b..6b8085cc 100644
--- a/src/aig/hop/hop.h
+++ b/src/aig/hop/hop.h
@@ -337,7 +337,7 @@ extern int             Hop_ObjIsMuxType( Hop_Obj_t * pObj );
 extern int             Hop_ObjRecognizeExor( Hop_Obj_t * pObj, Hop_Obj_t ** ppFan0, Hop_Obj_t ** ppFan1 );
 extern Hop_Obj_t *     Hop_ObjRecognizeMux( Hop_Obj_t * pObj, Hop_Obj_t ** ppObjT, Hop_Obj_t ** ppObjE );
 extern void            Hop_ObjPrintEqn( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level );
-extern void            Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level );
+extern void            Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level, int fOnlyAnds );
 extern void            Hop_ObjPrintVerbose( Hop_Obj_t * pObj, int fHaig );
 extern void            Hop_ManPrintVerbose( Hop_Man_t * p, int fHaig );
 extern void            Hop_ManDumpBlif( Hop_Man_t * p, char * pFileName );
diff --git a/src/aig/hop/hopUtil.c b/src/aig/hop/hopUtil.c
index 8cc7bdde..02cb08e3 100644
--- a/src/aig/hop/hopUtil.c
+++ b/src/aig/hop/hopUtil.c
@@ -366,7 +366,7 @@ void Hop_ObjPrintEqn( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int L
   SeeAlso     []
 
 ***********************************************************************/
-void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level )
+void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, int Level, int fOnlyAnds )
 {
     Vec_Ptr_t * vSuper;
     Hop_Obj_t * pFanin, * pFanin0, * pFanin1, * pFaninC;
@@ -387,7 +387,7 @@ void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, i
         return;
     }
     // EXOR case
-    if ( Hop_ObjIsExor(pObj) )
+    if ( !fOnlyAnds && Hop_ObjIsExor(pObj) )
     {
         Vec_VecExpand( vLevels, Level );
         vSuper = Vec_VecEntry( vLevels, Level );
@@ -395,7 +395,7 @@ void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, i
         fprintf( pFile, "%s", (Level==0? "" : "(") );
         Vec_PtrForEachEntry( Hop_Obj_t *, vSuper, pFanin, i )
         {
-            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin, (fCompl && i==0)), vLevels, Level+1 );
+            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin, (fCompl && i==0)), vLevels, Level+1, fOnlyAnds );
             if ( i < Vec_PtrSize(vSuper) - 1 )
                 fprintf( pFile, " ^ " );
         }
@@ -403,25 +403,25 @@ void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, i
         return;
     }
     // MUX case
-    if ( Hop_ObjIsMuxType(pObj) )
+    if ( !fOnlyAnds && Hop_ObjIsMuxType(pObj) )
     {
         if ( Hop_ObjRecognizeExor( pObj, &pFanin0, &pFanin1 ) )
         {
             fprintf( pFile, "%s", (Level==0? "" : "(") );
-            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin0, fCompl), vLevels, Level+1 );
+            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin0, fCompl), vLevels, Level+1, fOnlyAnds );
             fprintf( pFile, " ^ " );
-            Hop_ObjPrintVerilog( pFile, pFanin1, vLevels, Level+1 );
+            Hop_ObjPrintVerilog( pFile, pFanin1, vLevels, Level+1, fOnlyAnds );
             fprintf( pFile, "%s", (Level==0? "" : ")") );
         }
         else 
         {
             pFaninC = Hop_ObjRecognizeMux( pObj, &pFanin1, &pFanin0 );
             fprintf( pFile, "%s", (Level==0? "" : "(") );
-            Hop_ObjPrintVerilog( pFile, pFaninC, vLevels, Level+1 );
+            Hop_ObjPrintVerilog( pFile, pFaninC, vLevels, Level+1, fOnlyAnds );
             fprintf( pFile, " ? " );
-            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin1, fCompl), vLevels, Level+1 );
+            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin1, fCompl), vLevels, Level+1, fOnlyAnds );
             fprintf( pFile, " : " );
-            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin0, fCompl), vLevels, Level+1 );
+            Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin0, fCompl), vLevels, Level+1, fOnlyAnds );
             fprintf( pFile, "%s", (Level==0? "" : ")") );
         }
         return;
@@ -433,7 +433,7 @@ void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, i
     fprintf( pFile, "%s", (Level==0? "" : "(") );
     Vec_PtrForEachEntry( Hop_Obj_t *, vSuper, pFanin, i )
     {
-        Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin, fCompl), vLevels, Level+1 );
+        Hop_ObjPrintVerilog( pFile, Hop_NotCond(pFanin, fCompl), vLevels, Level+1, fOnlyAnds );
         if ( i < Vec_PtrSize(vSuper) - 1 )
             fprintf( pFile, " %s ", fCompl? "|" : "&" );
     }