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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2021-08-17 16:52:29 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2021-08-17 16:52:29 -0700 |
| commit | 4da6cc890433e8d782f8a1805fa9ec617955464d (patch) | |
| tree | 9db4715495b190ef385d88e4943d6a35f9df1d6f /abclib.dsp | |
| parent | e9b487666d7cab3cc8a02faa34160d2ed4cb6178 (diff) | |
| download | abc-4da6cc890433e8d782f8a1805fa9ec617955464d.tar.gz abc-4da6cc890433e8d782f8a1805fa9ec617955464d.tar.bz2 abc-4da6cc890433e8d782f8a1805fa9ec617955464d.zip | |
Improving AIG to Verilog converter.
Diffstat (limited to 'abclib.dsp')
| -rw-r--r-- | abclib.dsp | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -5103,7 +5103,7 @@ SOURCE=.\src\aig\gia\giaResub2.c # End Source File # Begin Source File -SOURCE=.\src\aig\gia\giaResub3_new5.c +SOURCE=.\src\aig\gia\giaResub3.c # End Source File # Begin Source File |