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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2014-09-26 16:11:36 -0700 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2014-09-26 16:11:36 -0700 |
| commit | 69bd355467df6347b6f071c58346c61f44be05e5 (patch) | |
| tree | 6b1b1bbed18b3f98066dc1f0357e3a8389f0710c /abcexe.dsp | |
| parent | 6aa1c94ea50b9357205c033c4e6240ba277890b6 (diff) | |
| download | abc-69bd355467df6347b6f071c58346c61f44be05e5.tar.gz abc-69bd355467df6347b6f071c58346c61f44be05e5.tar.bz2 abc-69bd355467df6347b6f071c58346c61f44be05e5.zip | |
Support for sequential designs in word-level Verilog.
Diffstat (limited to 'abcexe.dsp')
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