diff options
| author | Alan Mishchenko <alanmi@berkeley.edu> | 2007-02-11 08:01:00 -0800 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2007-02-11 08:01:00 -0800 |
| commit | 5f3e4c0fe21ba5e24db0c187a616a28afc0dabae (patch) | |
| tree | 30a84432ebcd370992d24ffced01ac0034072f30 | |
| parent | b9e0c95b690cf363f99b182ba8e7688aef091d95 (diff) | |
| download | abc-5f3e4c0fe21ba5e24db0c187a616a28afc0dabae.tar.gz abc-5f3e4c0fe21ba5e24db0c187a616a28afc0dabae.tar.bz2 abc-5f3e4c0fe21ba5e24db0c187a616a28afc0dabae.zip | |
Version abc70211
| -rw-r--r-- | abc.dsp | 10 | ||||
| -rw-r--r-- | abc.plg | 933 | ||||
| -rw-r--r-- | abc.rc | 4 | ||||
| -rw-r--r-- | abclib.plg | 903 | ||||
| -rw-r--r-- | abctestlib.plg | 35 | ||||
| -rw-r--r-- | src/aig/hop/hopUtil.c | 2 | ||||
| -rw-r--r-- | src/base/abc/abcCheck.c | 45 | ||||
| -rw-r--r-- | src/base/abc/abcHie.c | 100 | ||||
| -rw-r--r-- | src/base/abc/abcObj.c | 10 | ||||
| -rw-r--r-- | src/base/abci/abcPrint.c | 3 | ||||
| -rw-r--r-- | src/base/io/io.c | 6 | ||||
| -rw-r--r-- | src/base/io/io.h | 8 | ||||
| -rw-r--r-- | src/base/io/ioReadVerilog.c | 720 | ||||
| -rw-r--r-- | src/base/io/ioUtil.c | 92 | ||||
| -rw-r--r-- | src/base/io/ioWriteBlif.c | 1 | ||||
| -rw-r--r-- | src/base/io/ioWriteVerAux.c | 444 | ||||
| -rw-r--r-- | src/base/io/ioWriteVerilog.c (renamed from src/base/io/ioWriteVer.c) | 434 | ||||
| -rw-r--r-- | src/base/io/module.make | 4 | ||||
| -rw-r--r-- | src/base/ver/ver.h | 1 | ||||
| -rw-r--r-- | src/base/ver/verCore.c | 263 | ||||
| -rw-r--r-- | src/base/ver/verFormula.c | 5 | ||||
| -rw-r--r-- | src/base/ver/verParse.c | 2 | ||||
| -rw-r--r-- | src/base/ver/verStream.c | 6 |
23 files changed, 2434 insertions, 1597 deletions
@@ -454,6 +454,10 @@ SOURCE=.\src\base\io\ioReadPla.c # End Source File # Begin Source File +SOURCE=.\src\base\io\ioReadVerilog.c +# End Source File +# Begin Source File + SOURCE=.\src\base\io\ioUtil.c # End Source File # Begin Source File @@ -502,11 +506,7 @@ SOURCE=.\src\base\io\ioWritePla.c # End Source File # Begin Source File -SOURCE=.\src\base\io\ioWriteVer.c -# End Source File -# Begin Source File - -SOURCE=.\src\base\io\ioWriteVerAux.c +SOURCE=.\src\base\io\ioWriteVerilog.c # End Source File # End Group # Begin Group "main" diff --git a/abc.plg b/abc.plg new file mode 100644 index 00000000..11148eb3 --- /dev/null +++ b/abc.plg @@ -0,0 +1,933 @@ +<html> +<body> +<pre> +<h1>Build Log</h1> +<h3> +--------------------Configuration: abc - Win32 Debug-------------------- +</h3> +<h3>Command Lines</h3> +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSPDDB.tmp" with contents +[ +/nologo /MLd /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\opt\kit" /I "src\opt\res" /I "src\map\fpga" /I "src\map\if" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\aig\ivy" /I "src\aig\hop" /I "src\aig\rwt" /I "src\aig\deco" /I "src\aig\mem" /I "src\temp\esop" /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /FR"Debug/" /Fp"Debug/abc.pch" /YX /Fo"Debug/" /Fd"Debug/" /FD /GZ /c +"C:\_projects\abc\src\base\ver\verCore.c" +"C:\_projects\abc\src\base\ver\verParse.c" +] +Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSPDDB.tmp" +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSPDDC.tmp" with contents +[ +kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /incremental:yes /pdb:"Debug/abc.pdb" /debug /machine:I386 /out:"_TEST/abc.exe" /pdbtype:sept +.\Debug\abcAig.obj +.\Debug\abcCheck.obj +.\Debug\abcDfs.obj +.\Debug\abcFanio.obj +.\Debug\abcFunc.obj +.\Debug\abcHie.obj +.\Debug\abcLatch.obj +.\Debug\abcLib.obj +.\Debug\abcMinBase.obj +.\Debug\abcNames.obj +.\Debug\abcNetlist.obj +.\Debug\abcNtk.obj +.\Debug\abcObj.obj +.\Debug\abcRefs.obj +.\Debug\abcShow.obj +.\Debug\abcSop.obj +.\Debug\abcUtil.obj +.\Debug\abc.obj +.\Debug\abcAttach.obj +.\Debug\abcAuto.obj +.\Debug\abcBalance.obj +.\Debug\abcBmc.obj +.\Debug\abcClpBdd.obj +.\Debug\abcClpSop.obj +.\Debug\abcCut.obj +.\Debug\abcDebug.obj +.\Debug\abcDress.obj +.\Debug\abcDsd.obj +.\Debug\abcEspresso.obj +.\Debug\abcExtract.obj +.\Debug\abcFpga.obj +.\Debug\abcFpgaFast.obj +.\Debug\abcFraig.obj +.\Debug\abcFxu.obj +.\Debug\abcGen.obj +.\Debug\abcIf.obj +.\Debug\abcIvy.obj +.\Debug\abcLut.obj +.\Debug\abcMap.obj +.\Debug\abcMini.obj +.\Debug\abcMiter.obj +.\Debug\abcMulti.obj +.\Debug\abcMv.obj +.\Debug\abcNtbdd.obj +.\Debug\abcOdc.obj +.\Debug\abcOrder.obj +.\Debug\abcPrint.obj +.\Debug\abcProve.obj +.\Debug\abcReconv.obj +.\Debug\abcRefactor.obj +.\Debug\abcRenode.obj +.\Debug\abcReorder.obj +.\Debug\abcRestruct.obj +.\Debug\abcResub.obj +.\Debug\abcRewrite.obj +.\Debug\abcRr.obj +.\Debug\abcSat.obj +.\Debug\abcStrash.obj +.\Debug\abcSweep.obj +.\Debug\abcSymm.obj +.\Debug\abcTiming.obj +.\Debug\abcUnate.obj +.\Debug\abcUnreach.obj +.\Debug\abcVerify.obj +.\Debug\abcXsim.obj +.\Debug\cmd.obj +.\Debug\cmdAlias.obj +.\Debug\cmdApi.obj +.\Debug\cmdFlag.obj +.\Debug\cmdHist.obj +.\Debug\cmdUtils.obj +.\Debug\io.obj +.\Debug\ioReadAiger.obj +.\Debug\ioReadBaf.obj +.\Debug\ioReadBench.obj +.\Debug\ioReadBlif.obj +.\Debug\ioReadBlifAig.obj +.\Debug\ioReadBlifMv.obj +.\Debug\ioReadEdif.obj +.\Debug\ioReadEqn.obj +.\Debug\ioReadPla.obj +.\Debug\ioUtil.obj +.\Debug\ioWriteAiger.obj +.\Debug\ioWriteBaf.obj +.\Debug\ioWriteBench.obj +.\Debug\ioWriteBlif.obj +.\Debug\ioWriteBlifMv.obj +.\Debug\ioWriteCnf.obj +.\Debug\ioWriteDot.obj +.\Debug\ioWriteEqn.obj +.\Debug\ioWriteGml.obj +.\Debug\ioWriteList.obj +.\Debug\ioWritePla.obj +.\Debug\libSupport.obj +.\Debug\main.obj +.\Debug\mainFrame.obj +.\Debug\mainInit.obj +.\Debug\mainUtils.obj +.\Debug\verCore.obj +.\Debug\verFormula.obj +.\Debug\verParse.obj +.\Debug\verStream.obj +.\Debug\hopBalance.obj +.\Debug\hopCheck.obj +.\Debug\hopDfs.obj +.\Debug\hopMan.obj +.\Debug\hopMem.obj +.\Debug\hopObj.obj +.\Debug\hopOper.obj +.\Debug\hopTable.obj +.\Debug\hopUtil.obj +.\Debug\ivyBalance.obj +.\Debug\ivyCanon.obj +.\Debug\ivyCheck.obj +.\Debug\ivyCut.obj +.\Debug\ivyCutTrav.obj +.\Debug\ivyDfs.obj +.\Debug\ivyDsd.obj +.\Debug\ivyFanout.obj +.\Debug\ivyFastMap.obj +.\Debug\ivyFraig.obj +.\Debug\ivyHaig.obj +.\Debug\ivyMan.obj +.\Debug\ivyMem.obj +.\Debug\ivyMulti.obj +.\Debug\ivyObj.obj +.\Debug\ivyOper.obj +.\Debug\ivyResyn.obj +.\Debug\ivyRwr.obj +.\Debug\ivySeq.obj +.\Debug\ivyShow.obj +.\Debug\ivyTable.obj +.\Debug\ivyUtil.obj +.\Debug\rwtDec.obj +.\Debug\rwtMan.obj +.\Debug\rwtUtil.obj +.\Debug\mem.obj +.\Debug\cuddAddAbs.obj +.\Debug\cuddAddApply.obj +.\Debug\cuddAddFind.obj +.\Debug\cuddAddInv.obj +.\Debug\cuddAddIte.obj +.\Debug\cuddAddNeg.obj +.\Debug\cuddAddWalsh.obj +.\Debug\cuddAndAbs.obj +.\Debug\cuddAnneal.obj +.\Debug\cuddApa.obj +.\Debug\cuddAPI.obj +.\Debug\cuddApprox.obj +.\Debug\cuddBddAbs.obj +.\Debug\cuddBddCorr.obj +.\Debug\cuddBddIte.obj +.\Debug\cuddBridge.obj +.\Debug\cuddCache.obj +.\Debug\cuddCheck.obj +.\Debug\cuddClip.obj +.\Debug\cuddCof.obj +.\Debug\cuddCompose.obj +.\Debug\cuddDecomp.obj +.\Debug\cuddEssent.obj +.\Debug\cuddExact.obj +.\Debug\cuddExport.obj +.\Debug\cuddGenCof.obj +.\Debug\cuddGenetic.obj +.\Debug\cuddGroup.obj +.\Debug\cuddHarwell.obj +.\Debug\cuddInit.obj +.\Debug\cuddInteract.obj +.\Debug\cuddLCache.obj +.\Debug\cuddLevelQ.obj +.\Debug\cuddLinear.obj +.\Debug\cuddLiteral.obj +.\Debug\cuddMatMult.obj +.\Debug\cuddPriority.obj +.\Debug\cuddRead.obj +.\Debug\cuddRef.obj +.\Debug\cuddReorder.obj +.\Debug\cuddSat.obj +.\Debug\cuddSign.obj +.\Debug\cuddSolve.obj +.\Debug\cuddSplit.obj +.\Debug\cuddSubsetHB.obj +.\Debug\cuddSubsetSP.obj +.\Debug\cuddSymmetry.obj +.\Debug\cuddTable.obj +.\Debug\cuddUtil.obj +.\Debug\cuddWindow.obj +.\Debug\cuddZddCount.obj +.\Debug\cuddZddFuncs.obj +.\Debug\cuddZddGroup.obj +.\Debug\cuddZddIsop.obj +.\Debug\cuddZddLin.obj +.\Debug\cuddZddMisc.obj +.\Debug\cuddZddPort.obj +.\Debug\cuddZddReord.obj +.\Debug\cuddZddSetop.obj +.\Debug\cuddZddSymm.obj +.\Debug\cuddZddUtil.obj +.\Debug\epd.obj +.\Debug\mtrBasic.obj +.\Debug\mtrGroup.obj +.\Debug\parseCore.obj +.\Debug\parseEqn.obj +.\Debug\parseStack.obj +.\Debug\dsdApi.obj +.\Debug\dsdCheck.obj +.\Debug\dsdLocal.obj +.\Debug\dsdMan.obj +.\Debug\dsdProc.obj +.\Debug\dsdTree.obj +.\Debug\reoApi.obj +.\Debug\reoCore.obj +.\Debug\reoProfile.obj +.\Debug\reoSift.obj +.\Debug\reoSwap.obj +.\Debug\reoTest.obj +.\Debug\reoTransfer.obj +.\Debug\reoUnits.obj +.\Debug\msatActivity.obj +.\Debug\msatClause.obj +.\Debug\msatClauseVec.obj +.\Debug\msatMem.obj +.\Debug\msatOrderH.obj +.\Debug\msatQueue.obj +.\Debug\msatRead.obj +.\Debug\msatSolverApi.obj +.\Debug\msatSolverCore.obj +.\Debug\msatSolverIo.obj +.\Debug\msatSolverSearch.obj +.\Debug\msatSort.obj +.\Debug\msatVec.obj +.\Debug\fraigApi.obj +.\Debug\fraigCanon.obj +.\Debug\fraigChoice.obj +.\Debug\fraigFanout.obj +.\Debug\fraigFeed.obj +.\Debug\fraigMan.obj +.\Debug\fraigMem.obj +.\Debug\fraigNode.obj +.\Debug\fraigPrime.obj +.\Debug\fraigSat.obj +.\Debug\fraigTable.obj +.\Debug\fraigUtil.obj +.\Debug\fraigVec.obj +.\Debug\csat_apis.obj +.\Debug\satInter.obj +.\Debug\satMem.obj +.\Debug\satSolver.obj +.\Debug\satStore.obj +.\Debug\satTrace.obj +.\Debug\satUtil.obj +.\Debug\pr.obj +.\Debug\fxu.obj +.\Debug\fxuCreate.obj +.\Debug\fxuHeapD.obj +.\Debug\fxuHeapS.obj +.\Debug\fxuList.obj +.\Debug\fxuMatrix.obj +.\Debug\fxuPair.obj +.\Debug\fxuPrint.obj +.\Debug\fxuReduce.obj +.\Debug\fxuSelect.obj +.\Debug\fxuSingle.obj +.\Debug\fxuUpdate.obj +.\Debug\rwrDec.obj +.\Debug\rwrEva.obj +.\Debug\rwrExp.obj +.\Debug\rwrLib.obj +.\Debug\rwrMan.obj +.\Debug\rwrPrint.obj +.\Debug\rwrTemp.obj +.\Debug\rwrUtil.obj +.\Debug\cutApi.obj +.\Debug\cutCut.obj +.\Debug\cutExpand.obj +.\Debug\cutMan.obj +.\Debug\cutMerge.obj +.\Debug\cutNode.obj +.\Debug\cutOracle.obj +.\Debug\cutPre22.obj +.\Debug\cutSeq.obj +.\Debug\cutTruth.obj +.\Debug\decAbc.obj +.\Debug\decFactor.obj +.\Debug\decMan.obj +.\Debug\decPrint.obj +.\Debug\decUtil.obj +.\Debug\simMan.obj +.\Debug\simSat.obj +.\Debug\simSeq.obj +.\Debug\simSupp.obj +.\Debug\simSwitch.obj +.\Debug\simSym.obj +.\Debug\simSymSat.obj +.\Debug\simSymSim.obj +.\Debug\simSymStr.obj +.\Debug\simUtils.obj +.\Debug\retArea.obj +.\Debug\retCore.obj +.\Debug\retDelay.obj +.\Debug\retFlow.obj +.\Debug\retIncrem.obj +.\Debug\retInit.obj +.\Debug\retLvalue.obj +.\Debug\kitBdd.obj +.\Debug\kitFactor.obj +.\Debug\kitGraph.obj +.\Debug\kitHop.obj +.\Debug\kitIsop.obj +.\Debug\kitSop.obj +.\Debug\kitTruth.obj +.\Debug\resCore.obj +.\Debug\resDivs.obj +.\Debug\resFilter.obj +.\Debug\resSat.obj +.\Debug\resSim.obj +.\Debug\resStrash.obj +.\Debug\resUpdate.obj +.\Debug\resWin.obj +.\Debug\bdcCore.obj +.\Debug\bdcDec.obj +.\Debug\bdcTable.obj +.\Debug\fpga.obj +.\Debug\fpgaCore.obj +.\Debug\fpgaCreate.obj +.\Debug\fpgaCut.obj +.\Debug\fpgaCutUtils.obj +.\Debug\fpgaFanout.obj +.\Debug\fpgaLib.obj +.\Debug\fpgaMatch.obj +.\Debug\fpgaSwitch.obj +.\Debug\fpgaTime.obj +.\Debug\fpgaTruth.obj +.\Debug\fpgaUtils.obj +.\Debug\fpgaVec.obj +.\Debug\mapper.obj +.\Debug\mapperCanon.obj +.\Debug\mapperCore.obj +.\Debug\mapperCreate.obj +.\Debug\mapperCut.obj +.\Debug\mapperCutUtils.obj +.\Debug\mapperFanout.obj +.\Debug\mapperLib.obj +.\Debug\mapperMatch.obj +.\Debug\mapperRefs.obj +.\Debug\mapperSuper.obj +.\Debug\mapperSwitch.obj +.\Debug\mapperTable.obj +.\Debug\mapperTime.obj +.\Debug\mapperTree.obj +.\Debug\mapperTruth.obj +.\Debug\mapperUtils.obj +.\Debug\mapperVec.obj +.\Debug\mio.obj +.\Debug\mioApi.obj +.\Debug\mioFunc.obj +.\Debug\mioRead.obj +.\Debug\mioUtils.obj +.\Debug\super.obj +.\Debug\superAnd.obj +.\Debug\superGate.obj +.\Debug\superWrite.obj +.\Debug\ifCore.obj +.\Debug\ifCut.obj +.\Debug\ifMan.obj +.\Debug\ifMap.obj +.\Debug\ifPrepro.obj +.\Debug\ifReduce.obj +.\Debug\ifSeq.obj +.\Debug\ifTime.obj +.\Debug\ifTruth.obj +.\Debug\ifUtil.obj +.\Debug\extraBddAuto.obj +.\Debug\extraBddKmap.obj +.\Debug\extraBddMisc.obj +.\Debug\extraBddSymm.obj +.\Debug\extraBddUnate.obj +.\Debug\extraUtilBitMatrix.obj +.\Debug\extraUtilCanon.obj +.\Debug\extraUtilFile.obj +.\Debug\extraUtilMemory.obj +.\Debug\extraUtilMisc.obj +.\Debug\extraUtilProgress.obj +.\Debug\extraUtilReader.obj +.\Debug\extraUtilTruth.obj +.\Debug\extraUtilUtil.obj +.\Debug\st.obj +.\Debug\stmm.obj +.\Debug\mvc.obj +.\Debug\mvcApi.obj +.\Debug\mvcCompare.obj +.\Debug\mvcContain.obj +.\Debug\mvcCover.obj +.\Debug\mvcCube.obj +.\Debug\mvcDivide.obj +.\Debug\mvcDivisor.obj +.\Debug\mvcList.obj +.\Debug\mvcLits.obj +.\Debug\mvcMan.obj +.\Debug\mvcOpAlg.obj +.\Debug\mvcOpBool.obj +.\Debug\mvcPrint.obj +.\Debug\mvcSort.obj +.\Debug\mvcUtils.obj +.\Debug\cofactor.obj +.\Debug\cols.obj +.\Debug\compl.obj +.\Debug\contain.obj +.\Debug\cubehack.obj +.\Debug\cubestr.obj +.\Debug\cvrin.obj +.\Debug\cvrm.obj +.\Debug\cvrmisc.obj +.\Debug\cvrout.obj +.\Debug\dominate.obj +.\Debug\equiv.obj +.\Debug\espresso.obj +.\Debug\essen.obj +.\Debug\exact.obj +.\Debug\expand.obj +.\Debug\gasp.obj +.\Debug\gimpel.obj +.\Debug\globals.obj +.\Debug\hack.obj +.\Debug\indep.obj +.\Debug\irred.obj +.\Debug\map.obj +.\Debug\matrix.obj +.\Debug\mincov.obj +.\Debug\opo.obj +.\Debug\pair.obj +.\Debug\part.obj +.\Debug\primes.obj +.\Debug\reduce.obj +.\Debug\rows.obj +.\Debug\set.obj +.\Debug\setc.obj +.\Debug\sharp.obj +.\Debug\sminterf.obj +.\Debug\solution.obj +.\Debug\sparse.obj +.\Debug\unate.obj +.\Debug\verify.obj +.\Debug\nmApi.obj +.\Debug\nmTable.obj +.\Debug\ioWriteVerilog.obj +.\Debug\ioReadVerilog.obj +] +Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSPDDC.tmp" +<h3>Output Window</h3> +Compiling... +verCore.c +verParse.c +Linking... +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSPDDD.tmp" with contents +[ +/nologo /o"Debug/abc.bsc" +.\Debug\abcAig.sbr +.\Debug\abcCheck.sbr +.\Debug\abcDfs.sbr +.\Debug\abcFanio.sbr +.\Debug\abcFunc.sbr +.\Debug\abcHie.sbr +.\Debug\abcLatch.sbr +.\Debug\abcLib.sbr +.\Debug\abcMinBase.sbr +.\Debug\abcNames.sbr +.\Debug\abcNetlist.sbr +.\Debug\abcNtk.sbr +.\Debug\abcObj.sbr +.\Debug\abcRefs.sbr +.\Debug\abcShow.sbr +.\Debug\abcSop.sbr +.\Debug\abcUtil.sbr +.\Debug\abc.sbr +.\Debug\abcAttach.sbr +.\Debug\abcAuto.sbr +.\Debug\abcBalance.sbr +.\Debug\abcBmc.sbr +.\Debug\abcClpBdd.sbr +.\Debug\abcClpSop.sbr +.\Debug\abcCut.sbr +.\Debug\abcDebug.sbr +.\Debug\abcDress.sbr +.\Debug\abcDsd.sbr +.\Debug\abcEspresso.sbr +.\Debug\abcExtract.sbr +.\Debug\abcFpga.sbr +.\Debug\abcFpgaFast.sbr +.\Debug\abcFraig.sbr +.\Debug\abcFxu.sbr +.\Debug\abcGen.sbr +.\Debug\abcIf.sbr +.\Debug\abcIvy.sbr +.\Debug\abcLut.sbr +.\Debug\abcMap.sbr +.\Debug\abcMini.sbr +.\Debug\abcMiter.sbr +.\Debug\abcMulti.sbr +.\Debug\abcMv.sbr +.\Debug\abcNtbdd.sbr +.\Debug\abcOdc.sbr +.\Debug\abcOrder.sbr +.\Debug\abcPrint.sbr +.\Debug\abcProve.sbr +.\Debug\abcReconv.sbr +.\Debug\abcRefactor.sbr +.\Debug\abcRenode.sbr +.\Debug\abcReorder.sbr +.\Debug\abcRestruct.sbr +.\Debug\abcResub.sbr +.\Debug\abcRewrite.sbr +.\Debug\abcRr.sbr +.\Debug\abcSat.sbr +.\Debug\abcStrash.sbr +.\Debug\abcSweep.sbr +.\Debug\abcSymm.sbr +.\Debug\abcTiming.sbr +.\Debug\abcUnate.sbr +.\Debug\abcUnreach.sbr +.\Debug\abcVerify.sbr +.\Debug\abcXsim.sbr +.\Debug\cmd.sbr +.\Debug\cmdAlias.sbr +.\Debug\cmdApi.sbr +.\Debug\cmdFlag.sbr +.\Debug\cmdHist.sbr +.\Debug\cmdUtils.sbr +.\Debug\io.sbr +.\Debug\ioReadAiger.sbr +.\Debug\ioReadBaf.sbr +.\Debug\ioReadBench.sbr +.\Debug\ioReadBlif.sbr +.\Debug\ioReadBlifAig.sbr +.\Debug\ioReadBlifMv.sbr +.\Debug\ioReadEdif.sbr +.\Debug\ioReadEqn.sbr +.\Debug\ioReadPla.sbr +.\Debug\ioUtil.sbr +.\Debug\ioWriteAiger.sbr +.\Debug\ioWriteBaf.sbr +.\Debug\ioWriteBench.sbr +.\Debug\ioWriteBlif.sbr +.\Debug\ioWriteBlifMv.sbr +.\Debug\ioWriteCnf.sbr +.\Debug\ioWriteDot.sbr +.\Debug\ioWriteEqn.sbr +.\Debug\ioWriteGml.sbr +.\Debug\ioWriteList.sbr +.\Debug\ioWritePla.sbr +.\Debug\libSupport.sbr +.\Debug\main.sbr +.\Debug\mainFrame.sbr +.\Debug\mainInit.sbr +.\Debug\mainUtils.sbr +.\Debug\verCore.sbr +.\Debug\verFormula.sbr +.\Debug\verParse.sbr +.\Debug\verStream.sbr +.\Debug\hopBalance.sbr +.\Debug\hopCheck.sbr +.\Debug\hopDfs.sbr +.\Debug\hopMan.sbr +.\Debug\hopMem.sbr +.\Debug\hopObj.sbr +.\Debug\hopOper.sbr +.\Debug\hopTable.sbr +.\Debug\hopUtil.sbr +.\Debug\ivyBalance.sbr +.\Debug\ivyCanon.sbr +.\Debug\ivyCheck.sbr +.\Debug\ivyCut.sbr +.\Debug\ivyCutTrav.sbr +.\Debug\ivyDfs.sbr +.\Debug\ivyDsd.sbr +.\Debug\ivyFanout.sbr +.\Debug\ivyFastMap.sbr +.\Debug\ivyFraig.sbr +.\Debug\ivyHaig.sbr +.\Debug\ivyMan.sbr +.\Debug\ivyMem.sbr +.\Debug\ivyMulti.sbr +.\Debug\ivyObj.sbr +.\Debug\ivyOper.sbr +.\Debug\ivyResyn.sbr +.\Debug\ivyRwr.sbr +.\Debug\ivySeq.sbr +.\Debug\ivyShow.sbr +.\Debug\ivyTable.sbr +.\Debug\ivyUtil.sbr +.\Debug\rwtDec.sbr +.\Debug\rwtMan.sbr +.\Debug\rwtUtil.sbr +.\Debug\mem.sbr +.\Debug\cuddAddAbs.sbr +.\Debug\cuddAddApply.sbr +.\Debug\cuddAddFind.sbr +.\Debug\cuddAddInv.sbr +.\Debug\cuddAddIte.sbr +.\Debug\cuddAddNeg.sbr +.\Debug\cuddAddWalsh.sbr +.\Debug\cuddAndAbs.sbr +.\Debug\cuddAnneal.sbr +.\Debug\cuddApa.sbr +.\Debug\cuddAPI.sbr +.\Debug\cuddApprox.sbr +.\Debug\cuddBddAbs.sbr +.\Debug\cuddBddCorr.sbr +.\Debug\cuddBddIte.sbr +.\Debug\cuddBridge.sbr +.\Debug\cuddCache.sbr +.\Debug\cuddCheck.sbr +.\Debug\cuddClip.sbr +.\Debug\cuddCof.sbr +.\Debug\cuddCompose.sbr +.\Debug\cuddDecomp.sbr +.\Debug\cuddEssent.sbr +.\Debug\cuddExact.sbr +.\Debug\cuddExport.sbr +.\Debug\cuddGenCof.sbr +.\Debug\cuddGenetic.sbr +.\Debug\cuddGroup.sbr +.\Debug\cuddHarwell.sbr +.\Debug\cuddInit.sbr +.\Debug\cuddInteract.sbr +.\Debug\cuddLCache.sbr +.\Debug\cuddLevelQ.sbr +.\Debug\cuddLinear.sbr +.\Debug\cuddLiteral.sbr +.\Debug\cuddMatMult.sbr +.\Debug\cuddPriority.sbr +.\Debug\cuddRead.sbr +.\Debug\cuddRef.sbr +.\Debug\cuddReorder.sbr +.\Debug\cuddSat.sbr +.\Debug\cuddSign.sbr +.\Debug\cuddSolve.sbr +.\Debug\cuddSplit.sbr +.\Debug\cuddSubsetHB.sbr +.\Debug\cuddSubsetSP.sbr +.\Debug\cuddSymmetry.sbr +.\Debug\cuddTable.sbr +.\Debug\cuddUtil.sbr +.\Debug\cuddWindow.sbr +.\Debug\cuddZddCount.sbr +.\Debug\cuddZddFuncs.sbr +.\Debug\cuddZddGroup.sbr +.\Debug\cuddZddIsop.sbr +.\Debug\cuddZddLin.sbr +.\Debug\cuddZddMisc.sbr +.\Debug\cuddZddPort.sbr +.\Debug\cuddZddReord.sbr +.\Debug\cuddZddSetop.sbr +.\Debug\cuddZddSymm.sbr +.\Debug\cuddZddUtil.sbr +.\Debug\epd.sbr +.\Debug\mtrBasic.sbr +.\Debug\mtrGroup.sbr +.\Debug\parseCore.sbr +.\Debug\parseEqn.sbr +.\Debug\parseStack.sbr +.\Debug\dsdApi.sbr +.\Debug\dsdCheck.sbr +.\Debug\dsdLocal.sbr +.\Debug\dsdMan.sbr +.\Debug\dsdProc.sbr +.\Debug\dsdTree.sbr +.\Debug\reoApi.sbr +.\Debug\reoCore.sbr +.\Debug\reoProfile.sbr +.\Debug\reoSift.sbr +.\Debug\reoSwap.sbr +.\Debug\reoTest.sbr +.\Debug\reoTransfer.sbr +.\Debug\reoUnits.sbr +.\Debug\msatActivity.sbr +.\Debug\msatClause.sbr +.\Debug\msatClauseVec.sbr +.\Debug\msatMem.sbr +.\Debug\msatOrderH.sbr +.\Debug\msatQueue.sbr +.\Debug\msatRead.sbr +.\Debug\msatSolverApi.sbr +.\Debug\msatSolverCore.sbr +.\Debug\msatSolverIo.sbr +.\Debug\msatSolverSearch.sbr +.\Debug\msatSort.sbr +.\Debug\msatVec.sbr +.\Debug\fraigApi.sbr +.\Debug\fraigCanon.sbr +.\Debug\fraigChoice.sbr +.\Debug\fraigFanout.sbr +.\Debug\fraigFeed.sbr +.\Debug\fraigMan.sbr +.\Debug\fraigMem.sbr +.\Debug\fraigNode.sbr +.\Debug\fraigPrime.sbr +.\Debug\fraigSat.sbr +.\Debug\fraigTable.sbr +.\Debug\fraigUtil.sbr +.\Debug\fraigVec.sbr +.\Debug\csat_apis.sbr +.\Debug\satInter.sbr +.\Debug\satMem.sbr +.\Debug\satSolver.sbr +.\Debug\satStore.sbr +.\Debug\satTrace.sbr +.\Debug\satUtil.sbr +.\Debug\pr.sbr +.\Debug\fxu.sbr +.\Debug\fxuCreate.sbr +.\Debug\fxuHeapD.sbr +.\Debug\fxuHeapS.sbr +.\Debug\fxuList.sbr +.\Debug\fxuMatrix.sbr +.\Debug\fxuPair.sbr +.\Debug\fxuPrint.sbr +.\Debug\fxuReduce.sbr +.\Debug\fxuSelect.sbr +.\Debug\fxuSingle.sbr +.\Debug\fxuUpdate.sbr +.\Debug\rwrDec.sbr +.\Debug\rwrEva.sbr +.\Debug\rwrExp.sbr +.\Debug\rwrLib.sbr +.\Debug\rwrMan.sbr +.\Debug\rwrPrint.sbr +.\Debug\rwrTemp.sbr +.\Debug\rwrUtil.sbr +.\Debug\cutApi.sbr +.\Debug\cutCut.sbr +.\Debug\cutExpand.sbr +.\Debug\cutMan.sbr +.\Debug\cutMerge.sbr +.\Debug\cutNode.sbr +.\Debug\cutOracle.sbr +.\Debug\cutPre22.sbr +.\Debug\cutSeq.sbr +.\Debug\cutTruth.sbr +.\Debug\decAbc.sbr +.\Debug\decFactor.sbr +.\Debug\decMan.sbr +.\Debug\decPrint.sbr +.\Debug\decUtil.sbr +.\Debug\simMan.sbr +.\Debug\simSat.sbr +.\Debug\simSeq.sbr +.\Debug\simSupp.sbr +.\Debug\simSwitch.sbr +.\Debug\simSym.sbr +.\Debug\simSymSat.sbr +.\Debug\simSymSim.sbr +.\Debug\simSymStr.sbr +.\Debug\simUtils.sbr +.\Debug\retArea.sbr +.\Debug\retCore.sbr +.\Debug\retDelay.sbr +.\Debug\retFlow.sbr +.\Debug\retIncrem.sbr +.\Debug\retInit.sbr +.\Debug\retLvalue.sbr +.\Debug\kitBdd.sbr +.\Debug\kitFactor.sbr +.\Debug\kitGraph.sbr +.\Debug\kitHop.sbr +.\Debug\kitIsop.sbr +.\Debug\kitSop.sbr +.\Debug\kitTruth.sbr +.\Debug\resCore.sbr +.\Debug\resDivs.sbr +.\Debug\resFilter.sbr +.\Debug\resSat.sbr +.\Debug\resSim.sbr +.\Debug\resStrash.sbr +.\Debug\resUpdate.sbr +.\Debug\resWin.sbr +.\Debug\bdcCore.sbr +.\Debug\bdcDec.sbr +.\Debug\bdcTable.sbr +.\Debug\fpga.sbr +.\Debug\fpgaCore.sbr +.\Debug\fpgaCreate.sbr +.\Debug\fpgaCut.sbr +.\Debug\fpgaCutUtils.sbr +.\Debug\fpgaFanout.sbr +.\Debug\fpgaLib.sbr +.\Debug\fpgaMatch.sbr +.\Debug\fpgaSwitch.sbr +.\Debug\fpgaTime.sbr +.\Debug\fpgaTruth.sbr +.\Debug\fpgaUtils.sbr +.\Debug\fpgaVec.sbr +.\Debug\mapper.sbr +.\Debug\mapperCanon.sbr +.\Debug\mapperCore.sbr +.\Debug\mapperCreate.sbr +.\Debug\mapperCut.sbr +.\Debug\mapperCutUtils.sbr +.\Debug\mapperFanout.sbr +.\Debug\mapperLib.sbr +.\Debug\mapperMatch.sbr +.\Debug\mapperRefs.sbr +.\Debug\mapperSuper.sbr +.\Debug\mapperSwitch.sbr +.\Debug\mapperTable.sbr +.\Debug\mapperTime.sbr +.\Debug\mapperTree.sbr +.\Debug\mapperTruth.sbr +.\Debug\mapperUtils.sbr +.\Debug\mapperVec.sbr +.\Debug\mio.sbr +.\Debug\mioApi.sbr +.\Debug\mioFunc.sbr +.\Debug\mioRead.sbr +.\Debug\mioUtils.sbr +.\Debug\super.sbr +.\Debug\superAnd.sbr +.\Debug\superGate.sbr +.\Debug\superWrite.sbr +.\Debug\ifCore.sbr +.\Debug\ifCut.sbr +.\Debug\ifMan.sbr +.\Debug\ifMap.sbr +.\Debug\ifPrepro.sbr +.\Debug\ifReduce.sbr +.\Debug\ifSeq.sbr +.\Debug\ifTime.sbr +.\Debug\ifTruth.sbr +.\Debug\ifUtil.sbr +.\Debug\extraBddAuto.sbr +.\Debug\extraBddKmap.sbr +.\Debug\extraBddMisc.sbr +.\Debug\extraBddSymm.sbr +.\Debug\extraBddUnate.sbr +.\Debug\extraUtilBitMatrix.sbr +.\Debug\extraUtilCanon.sbr +.\Debug\extraUtilFile.sbr +.\Debug\extraUtilMemory.sbr +.\Debug\extraUtilMisc.sbr +.\Debug\extraUtilProgress.sbr +.\Debug\extraUtilReader.sbr +.\Debug\extraUtilTruth.sbr +.\Debug\extraUtilUtil.sbr +.\Debug\st.sbr +.\Debug\stmm.sbr +.\Debug\mvc.sbr +.\Debug\mvcApi.sbr +.\Debug\mvcCompare.sbr +.\Debug\mvcContain.sbr +.\Debug\mvcCover.sbr +.\Debug\mvcCube.sbr +.\Debug\mvcDivide.sbr +.\Debug\mvcDivisor.sbr +.\Debug\mvcList.sbr +.\Debug\mvcLits.sbr +.\Debug\mvcMan.sbr +.\Debug\mvcOpAlg.sbr +.\Debug\mvcOpBool.sbr +.\Debug\mvcPrint.sbr +.\Debug\mvcSort.sbr +.\Debug\mvcUtils.sbr +.\Debug\cofactor.sbr +.\Debug\cols.sbr +.\Debug\compl.sbr +.\Debug\contain.sbr +.\Debug\cubehack.sbr +.\Debug\cubestr.sbr +.\Debug\cvrin.sbr +.\Debug\cvrm.sbr +.\Debug\cvrmisc.sbr +.\Debug\cvrout.sbr +.\Debug\dominate.sbr +.\Debug\equiv.sbr +.\Debug\espresso.sbr +.\Debug\essen.sbr +.\Debug\exact.sbr +.\Debug\expand.sbr +.\Debug\gasp.sbr +.\Debug\gimpel.sbr +.\Debug\globals.sbr +.\Debug\hack.sbr +.\Debug\indep.sbr +.\Debug\irred.sbr +.\Debug\map.sbr +.\Debug\matrix.sbr +.\Debug\mincov.sbr +.\Debug\opo.sbr +.\Debug\pair.sbr +.\Debug\part.sbr +.\Debug\primes.sbr +.\Debug\reduce.sbr +.\Debug\rows.sbr +.\Debug\set.sbr +.\Debug\setc.sbr +.\Debug\sharp.sbr +.\Debug\sminterf.sbr +.\Debug\solution.sbr +.\Debug\sparse.sbr +.\Debug\unate.sbr +.\Debug\verify.sbr +.\Debug\nmApi.sbr +.\Debug\nmTable.sbr +.\Debug\ioWriteVerilog.sbr +.\Debug\ioReadVerilog.sbr] +Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSPDDD.tmp" +Creating browse info file... +<h3>Output Window</h3> + + + +<h3>Results</h3> +abc.exe - 0 error(s), 0 warning(s) +</pre> +</body> +</html> @@ -118,6 +118,8 @@ alias fflitmin "compress2rs; ren; sop; ps -f" alias t0 "r res.blif; aig; mfs" alias t "r res2.blif; aig; mfs" -alias tt "rh a/quip_opt/nut_002_opt.blif" +alias tt "rh a/quip_opt/nut_001_opt.blif" +alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif" +alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v" diff --git a/abclib.plg b/abclib.plg new file mode 100644 index 00000000..11a53466 --- /dev/null +++ b/abclib.plg @@ -0,0 +1,903 @@ +<html> +<body> +<pre> +<h1>Build Log</h1> +<h3> +--------------------Configuration: abclib - Win32 Debug-------------------- +</h3> +<h3>Command Lines</h3> +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP137A.tmp" with contents +[ +/nologo /MLd /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\bsat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\opt\kit" /I "src\map\fpga" /I "src\map\if" /I "src\map\mapper" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /I "src\misc\espresso" /I "src\misc\nm" /I "src\misc\hash" /I "src\aig\ivy" /I "src\aig\hop" /I "src\aig\rwt" /I "src\aig\deco" /I "src\aig\mem" /I "src\temp\esop" /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"abclib\DebugLib/" /Fp"abclib\DebugLib/abclib.pch" /YX /Fo"abclib\DebugLib/" /Fd"abclib\DebugLib/" /FD /GZ /c +"C:\_projects\abc\src\sat\asat\jfront.c" +] +Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP137A.tmp" +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP137B.tmp" with contents +[ +/nologo /out:"abclib\abclib_debug.lib" +.\abclib\DebugLib\abcAig.obj +.\abclib\DebugLib\abcCheck.obj +.\abclib\DebugLib\abcDfs.obj +.\abclib\DebugLib\abcFanio.obj +.\abclib\DebugLib\abcFunc.obj +.\abclib\DebugLib\abcLatch.obj +.\abclib\DebugLib\abcLib.obj +.\abclib\DebugLib\abcMinBase.obj +.\abclib\DebugLib\abcNames.obj +.\abclib\DebugLib\abcNetlist.obj +.\abclib\DebugLib\abcNtk.obj +.\abclib\DebugLib\abcObj.obj +.\abclib\DebugLib\abcRefs.obj +.\abclib\DebugLib\abcShow.obj +.\abclib\DebugLib\abcSop.obj +.\abclib\DebugLib\abcUtil.obj +.\abclib\DebugLib\abc.obj +.\abclib\DebugLib\abcAttach.obj +.\abclib\DebugLib\abcAuto.obj +.\abclib\DebugLib\abcBalance.obj +.\abclib\DebugLib\abcBmc.obj +.\abclib\DebugLib\abcClpBdd.obj +.\abclib\DebugLib\abcClpSop.obj +.\abclib\DebugLib\abcCut.obj +.\abclib\DebugLib\abcDebug.obj +.\abclib\DebugLib\abcDress.obj +.\abclib\DebugLib\abcDsd.obj +.\abclib\DebugLib\abcEspresso.obj +.\abclib\DebugLib\abcExtract.obj +.\abclib\DebugLib\abcFpga.obj +.\abclib\DebugLib\abcFpgaFast.obj +.\abclib\DebugLib\abcFraig.obj +.\abclib\DebugLib\abcFxu.obj +.\abclib\DebugLib\abcGen.obj +.\abclib\DebugLib\abcIf.obj +.\abclib\DebugLib\abcIvy.obj +.\abclib\DebugLib\abcLut.obj +.\abclib\DebugLib\abcMap.obj +.\abclib\DebugLib\abcMini.obj +.\abclib\DebugLib\abcMiter.obj +.\abclib\DebugLib\abcMulti.obj +.\abclib\DebugLib\abcMv.obj +.\abclib\DebugLib\abcNtbdd.obj +.\abclib\DebugLib\abcOrder.obj +.\abclib\DebugLib\abcPrint.obj +.\abclib\DebugLib\abcProve.obj +.\abclib\DebugLib\abcReconv.obj +.\abclib\DebugLib\abcRefactor.obj +.\abclib\DebugLib\abcRenode.obj +.\abclib\DebugLib\abcReorder.obj +.\abclib\DebugLib\abcRestruct.obj +.\abclib\DebugLib\abcResub.obj +.\abclib\DebugLib\abcRewrite.obj +.\abclib\DebugLib\abcRr.obj +.\abclib\DebugLib\abcSat.obj +.\abclib\DebugLib\abcStrash.obj +.\abclib\DebugLib\abcSweep.obj +.\abclib\DebugLib\abcSymm.obj +.\abclib\DebugLib\abcTiming.obj +.\abclib\DebugLib\abcUnate.obj +.\abclib\DebugLib\abcUnreach.obj +.\abclib\DebugLib\abcVerify.obj +.\abclib\DebugLib\abcXsim.obj +.\abclib\DebugLib\cmd.obj +.\abclib\DebugLib\cmdAlias.obj +.\abclib\DebugLib\cmdApi.obj +.\abclib\DebugLib\cmdFlag.obj +.\abclib\DebugLib\cmdHist.obj +.\abclib\DebugLib\cmdUtils.obj +.\abclib\DebugLib\io.obj +.\abclib\DebugLib\ioReadAiger.obj +.\abclib\DebugLib\ioReadBaf.obj +.\abclib\DebugLib\ioReadBench.obj +.\abclib\DebugLib\ioReadBlif.obj +.\abclib\DebugLib\ioReadBlifAig.obj +.\abclib\DebugLib\ioReadEdif.obj +.\abclib\DebugLib\ioReadEqn.obj +.\abclib\DebugLib\ioReadPla.obj +.\abclib\DebugLib\ioUtil.obj +.\abclib\DebugLib\ioWriteAiger.obj +.\abclib\DebugLib\ioWriteBaf.obj +.\abclib\DebugLib\ioWriteBench.obj +.\abclib\DebugLib\ioWriteBlif.obj +.\abclib\DebugLib\ioWriteCnf.obj +.\abclib\DebugLib\ioWriteDot.obj +.\abclib\DebugLib\ioWriteEqn.obj +.\abclib\DebugLib\ioWriteGml.obj +.\abclib\DebugLib\ioWriteList.obj +.\abclib\DebugLib\ioWritePla.obj +.\abclib\DebugLib\ioWriteVer.obj +.\abclib\DebugLib\ioWriteVerAux.obj +.\abclib\DebugLib\libSupport.obj +.\abclib\DebugLib\main.obj +.\abclib\DebugLib\mainFrame.obj +.\abclib\DebugLib\mainInit.obj +.\abclib\DebugLib\mainUtils.obj +.\abclib\DebugLib\verCore.obj +.\abclib\DebugLib\verFormula.obj +.\abclib\DebugLib\verParse.obj +.\abclib\DebugLib\verStream.obj +.\abclib\DebugLib\verWords.obj +.\abclib\DebugLib\cuddAddAbs.obj +.\abclib\DebugLib\cuddAddApply.obj +.\abclib\DebugLib\cuddAddFind.obj +.\abclib\DebugLib\cuddAddInv.obj +.\abclib\DebugLib\cuddAddIte.obj +.\abclib\DebugLib\cuddAddNeg.obj +.\abclib\DebugLib\cuddAddWalsh.obj +.\abclib\DebugLib\cuddAndAbs.obj +.\abclib\DebugLib\cuddAnneal.obj +.\abclib\DebugLib\cuddApa.obj +.\abclib\DebugLib\cuddAPI.obj +.\abclib\DebugLib\cuddApprox.obj +.\abclib\DebugLib\cuddBddAbs.obj +.\abclib\DebugLib\cuddBddCorr.obj +.\abclib\DebugLib\cuddBddIte.obj +.\abclib\DebugLib\cuddBridge.obj +.\abclib\DebugLib\cuddCache.obj +.\abclib\DebugLib\cuddCheck.obj +.\abclib\DebugLib\cuddClip.obj +.\abclib\DebugLib\cuddCof.obj +.\abclib\DebugLib\cuddCompose.obj +.\abclib\DebugLib\cuddDecomp.obj +.\abclib\DebugLib\cuddEssent.obj +.\abclib\DebugLib\cuddExact.obj +.\abclib\DebugLib\cuddExport.obj +.\abclib\DebugLib\cuddGenCof.obj +.\abclib\DebugLib\cuddGenetic.obj +.\abclib\DebugLib\cuddGroup.obj +.\abclib\DebugLib\cuddHarwell.obj +.\abclib\DebugLib\cuddInit.obj +.\abclib\DebugLib\cuddInteract.obj +.\abclib\DebugLib\cuddLCache.obj +.\abclib\DebugLib\cuddLevelQ.obj +.\abclib\DebugLib\cuddLinear.obj +.\abclib\DebugLib\cuddLiteral.obj +.\abclib\DebugLib\cuddMatMult.obj +.\abclib\DebugLib\cuddPriority.obj +.\abclib\DebugLib\cuddRead.obj +.\abclib\DebugLib\cuddRef.obj +.\abclib\DebugLib\cuddReorder.obj +.\abclib\DebugLib\cuddSat.obj +.\abclib\DebugLib\cuddSign.obj +.\abclib\DebugLib\cuddSolve.obj +.\abclib\DebugLib\cuddSplit.obj +.\abclib\DebugLib\cuddSubsetHB.obj +.\abclib\DebugLib\cuddSubsetSP.obj +.\abclib\DebugLib\cuddSymmetry.obj +.\abclib\DebugLib\cuddTable.obj +.\abclib\DebugLib\cuddUtil.obj +.\abclib\DebugLib\cuddWindow.obj +.\abclib\DebugLib\cuddZddCount.obj +.\abclib\DebugLib\cuddZddFuncs.obj +.\abclib\DebugLib\cuddZddGroup.obj +.\abclib\DebugLib\cuddZddIsop.obj +.\abclib\DebugLib\cuddZddLin.obj +.\abclib\DebugLib\cuddZddMisc.obj +.\abclib\DebugLib\cuddZddPort.obj +.\abclib\DebugLib\cuddZddReord.obj +.\abclib\DebugLib\cuddZddSetop.obj +.\abclib\DebugLib\cuddZddSymm.obj +.\abclib\DebugLib\cuddZddUtil.obj +.\abclib\DebugLib\epd.obj +.\abclib\DebugLib\mtrBasic.obj +.\abclib\DebugLib\mtrGroup.obj +.\abclib\DebugLib\parseCore.obj +.\abclib\DebugLib\parseEqn.obj +.\abclib\DebugLib\parseStack.obj +.\abclib\DebugLib\dsdApi.obj +.\abclib\DebugLib\dsdCheck.obj +.\abclib\DebugLib\dsdLocal.obj +.\abclib\DebugLib\dsdMan.obj +.\abclib\DebugLib\dsdProc.obj +.\abclib\DebugLib\dsdTree.obj +.\abclib\DebugLib\reoApi.obj +.\abclib\DebugLib\reoCore.obj +.\abclib\DebugLib\reoProfile.obj +.\abclib\DebugLib\reoSift.obj +.\abclib\DebugLib\reoSwap.obj +.\abclib\DebugLib\reoTest.obj +.\abclib\DebugLib\reoTransfer.obj +.\abclib\DebugLib\reoUnits.obj +.\abclib\DebugLib\added.obj +.\abclib\DebugLib\asatmem.obj +.\abclib\DebugLib\solver.obj +.\abclib\DebugLib\msatActivity.obj +.\abclib\DebugLib\msatClause.obj +.\abclib\DebugLib\msatClauseVec.obj +.\abclib\DebugLib\msatMem.obj +.\abclib\DebugLib\msatOrderH.obj +.\abclib\DebugLib\msatQueue.obj +.\abclib\DebugLib\msatRead.obj +.\abclib\DebugLib\msatSolverApi.obj +.\abclib\DebugLib\msatSolverCore.obj +.\abclib\DebugLib\msatSolverIo.obj +.\abclib\DebugLib\msatSolverSearch.obj +.\abclib\DebugLib\msatSort.obj +.\abclib\DebugLib\msatVec.obj +.\abclib\DebugLib\fraigApi.obj +.\abclib\DebugLib\fraigCanon.obj +.\abclib\DebugLib\fraigChoice.obj +.\abclib\DebugLib\fraigFanout.obj +.\abclib\DebugLib\fraigFeed.obj +.\abclib\DebugLib\fraigMan.obj +.\abclib\DebugLib\fraigMem.obj +.\abclib\DebugLib\fraigNode.obj +.\abclib\DebugLib\fraigPrime.obj +.\abclib\DebugLib\fraigSat.obj +.\abclib\DebugLib\fraigTable.obj +.\abclib\DebugLib\fraigUtil.obj +.\abclib\DebugLib\fraigVec.obj +.\abclib\DebugLib\csat_apis.obj +.\abclib\DebugLib\satMem.obj +.\abclib\DebugLib\satSolver.obj +.\abclib\DebugLib\satUtil.obj +.\abclib\DebugLib\fxu.obj +.\abclib\DebugLib\fxuCreate.obj +.\abclib\DebugLib\fxuHeapD.obj +.\abclib\DebugLib\fxuHeapS.obj +.\abclib\DebugLib\fxuList.obj +.\abclib\DebugLib\fxuMatrix.obj +.\abclib\DebugLib\fxuPair.obj +.\abclib\DebugLib\fxuPrint.obj +.\abclib\DebugLib\fxuReduce.obj +.\abclib\DebugLib\fxuSelect.obj +.\abclib\DebugLib\fxuSingle.obj +.\abclib\DebugLib\fxuUpdate.obj +.\abclib\DebugLib\rwrDec.obj +.\abclib\DebugLib\rwrEva.obj +.\abclib\DebugLib\rwrExp.obj +.\abclib\DebugLib\rwrLib.obj +.\abclib\DebugLib\rwrMan.obj +.\abclib\DebugLib\rwrPrint.obj +.\abclib\DebugLib\rwrTemp.obj +.\abclib\DebugLib\rwrUtil.obj +.\abclib\DebugLib\cutApi.obj +.\abclib\DebugLib\cutCut.obj +.\abclib\DebugLib\cutExpand.obj +.\abclib\DebugLib\cutMan.obj +.\abclib\DebugLib\cutMerge.obj +.\abclib\DebugLib\cutNode.obj +.\abclib\DebugLib\cutOracle.obj +.\abclib\DebugLib\cutPre22.obj +.\abclib\DebugLib\cutSeq.obj +.\abclib\DebugLib\cutTruth.obj +.\abclib\DebugLib\decAbc.obj +.\abclib\DebugLib\decFactor.obj +.\abclib\DebugLib\decMan.obj +.\abclib\DebugLib\decPrint.obj +.\abclib\DebugLib\decUtil.obj +.\abclib\DebugLib\simMan.obj +.\abclib\DebugLib\simSat.obj +.\abclib\DebugLib\simSeq.obj +.\abclib\DebugLib\simSupp.obj +.\abclib\DebugLib\simSwitch.obj +.\abclib\DebugLib\simSym.obj +.\abclib\DebugLib\simSymSat.obj +.\abclib\DebugLib\simSymSim.obj +.\abclib\DebugLib\simSymStr.obj +.\abclib\DebugLib\simUtils.obj +.\abclib\DebugLib\retArea.obj +.\abclib\DebugLib\retCore.obj +.\abclib\DebugLib\retDelay.obj +.\abclib\DebugLib\retFlow.obj +.\abclib\DebugLib\retIncrem.obj +.\abclib\DebugLib\retInit.obj +.\abclib\DebugLib\retLvalue.obj +.\abclib\DebugLib\kitBdd.obj +.\abclib\DebugLib\kitFactor.obj +.\abclib\DebugLib\kitGraph.obj +.\abclib\DebugLib\kitHop.obj +.\abclib\DebugLib\kitIsop.obj +.\abclib\DebugLib\kitSop.obj +.\abclib\DebugLib\kitTruth.obj +.\abclib\DebugLib\fpga.obj +.\abclib\DebugLib\fpgaCore.obj +.\abclib\DebugLib\fpgaCreate.obj +.\abclib\DebugLib\fpgaCut.obj +.\abclib\DebugLib\fpgaCutUtils.obj +.\abclib\DebugLib\fpgaFanout.obj +.\abclib\DebugLib\fpgaLib.obj +.\abclib\DebugLib\fpgaMatch.obj +.\abclib\DebugLib\fpgaSwitch.obj +.\abclib\DebugLib\fpgaTime.obj +.\abclib\DebugLib\fpgaTruth.obj +.\abclib\DebugLib\fpgaUtils.obj +.\abclib\DebugLib\fpgaVec.obj +.\abclib\DebugLib\mapper.obj +.\abclib\DebugLib\mapperCanon.obj +.\abclib\DebugLib\mapperCore.obj +.\abclib\DebugLib\mapperCreate.obj +.\abclib\DebugLib\mapperCut.obj +.\abclib\DebugLib\mapperCutUtils.obj +.\abclib\DebugLib\mapperFanout.obj +.\abclib\DebugLib\mapperLib.obj +.\abclib\DebugLib\mapperMatch.obj +.\abclib\DebugLib\mapperRefs.obj +.\abclib\DebugLib\mapperSuper.obj +.\abclib\DebugLib\mapperSwitch.obj +.\abclib\DebugLib\mapperTable.obj +.\abclib\DebugLib\mapperTime.obj +.\abclib\DebugLib\mapperTree.obj +.\abclib\DebugLib\mapperTruth.obj +.\abclib\DebugLib\mapperUtils.obj +.\abclib\DebugLib\mapperVec.obj +.\abclib\DebugLib\mio.obj +.\abclib\DebugLib\mioApi.obj +.\abclib\DebugLib\mioFunc.obj +.\abclib\DebugLib\mioRead.obj +.\abclib\DebugLib\mioUtils.obj +.\abclib\DebugLib\super.obj +.\abclib\DebugLib\superAnd.obj +.\abclib\DebugLib\superGate.obj +.\abclib\DebugLib\superWrite.obj +.\abclib\DebugLib\ifCore.obj +.\abclib\DebugLib\ifCut.obj +.\abclib\DebugLib\ifMan.obj +.\abclib\DebugLib\ifMap.obj +.\abclib\DebugLib\ifPrepro.obj +.\abclib\DebugLib\ifReduce.obj +.\abclib\DebugLib\ifSeq.obj +.\abclib\DebugLib\ifTime.obj +.\abclib\DebugLib\ifTruth.obj +.\abclib\DebugLib\ifUtil.obj +.\abclib\DebugLib\extraBddAuto.obj +.\abclib\DebugLib\extraBddKmap.obj +.\abclib\DebugLib\extraBddMisc.obj +.\abclib\DebugLib\extraBddSymm.obj +.\abclib\DebugLib\extraBddUnate.obj +.\abclib\DebugLib\extraUtilBitMatrix.obj +.\abclib\DebugLib\extraUtilCanon.obj +.\abclib\DebugLib\extraUtilFile.obj +.\abclib\DebugLib\extraUtilMemory.obj +.\abclib\DebugLib\extraUtilMisc.obj +.\abclib\DebugLib\extraUtilProgress.obj +.\abclib\DebugLib\extraUtilReader.obj +.\abclib\DebugLib\extraUtilTruth.obj +.\abclib\DebugLib\extraUtilUtil.obj +.\abclib\DebugLib\st.obj +.\abclib\DebugLib\stmm.obj +.\abclib\DebugLib\mvc.obj +.\abclib\DebugLib\mvcApi.obj +.\abclib\DebugLib\mvcCompare.obj +.\abclib\DebugLib\mvcContain.obj +.\abclib\DebugLib\mvcCover.obj +.\abclib\DebugLib\mvcCube.obj +.\abclib\DebugLib\mvcDivide.obj +.\abclib\DebugLib\mvcDivisor.obj +.\abclib\DebugLib\mvcList.obj +.\abclib\DebugLib\mvcLits.obj +.\abclib\DebugLib\mvcMan.obj +.\abclib\DebugLib\mvcOpAlg.obj +.\abclib\DebugLib\mvcOpBool.obj +.\abclib\DebugLib\mvcPrint.obj +.\abclib\DebugLib\mvcSort.obj +.\abclib\DebugLib\mvcUtils.obj +.\abclib\DebugLib\cofactor.obj +.\abclib\DebugLib\cols.obj +.\abclib\DebugLib\compl.obj +.\abclib\DebugLib\contain.obj +.\abclib\DebugLib\cubehack.obj +.\abclib\DebugLib\cubestr.obj +.\abclib\DebugLib\cvrin.obj +.\abclib\DebugLib\cvrm.obj +.\abclib\DebugLib\cvrmisc.obj +.\abclib\DebugLib\cvrout.obj +.\abclib\DebugLib\dominate.obj +.\abclib\DebugLib\equiv.obj +.\abclib\DebugLib\espresso.obj +.\abclib\DebugLib\essen.obj +.\abclib\DebugLib\exact.obj +.\abclib\DebugLib\expand.obj +.\abclib\DebugLib\gasp.obj +.\abclib\DebugLib\gimpel.obj +.\abclib\DebugLib\globals.obj +.\abclib\DebugLib\hack.obj +.\abclib\DebugLib\indep.obj +.\abclib\DebugLib\irred.obj +.\abclib\DebugLib\map.obj +.\abclib\DebugLib\matrix.obj +.\abclib\DebugLib\mincov.obj +.\abclib\DebugLib\opo.obj +.\abclib\DebugLib\pair.obj +.\abclib\DebugLib\part.obj +.\abclib\DebugLib\primes.obj +.\abclib\DebugLib\reduce.obj +.\abclib\DebugLib\rows.obj +.\abclib\DebugLib\set.obj +.\abclib\DebugLib\setc.obj +.\abclib\DebugLib\sharp.obj +.\abclib\DebugLib\sminterf.obj +.\abclib\DebugLib\solution.obj +.\abclib\DebugLib\sparse.obj +.\abclib\DebugLib\unate.obj +.\abclib\DebugLib\verify.obj +.\abclib\DebugLib\nmApi.obj +.\abclib\DebugLib\nmTable.obj +.\abclib\DebugLib\hopBalance.obj +.\abclib\DebugLib\hopCheck.obj +.\abclib\DebugLib\hopDfs.obj +.\abclib\DebugLib\hopMan.obj +.\abclib\DebugLib\hopMem.obj +.\abclib\DebugLib\hopObj.obj +.\abclib\DebugLib\hopOper.obj +.\abclib\DebugLib\hopTable.obj +.\abclib\DebugLib\hopUtil.obj +.\abclib\DebugLib\ivyBalance.obj +.\abclib\DebugLib\ivyCanon.obj +.\abclib\DebugLib\ivyCheck.obj +.\abclib\DebugLib\ivyCut.obj +.\abclib\DebugLib\ivyCutTrav.obj +.\abclib\DebugLib\ivyDfs.obj +.\abclib\DebugLib\ivyDsd.obj +.\abclib\DebugLib\ivyFanout.obj +.\abclib\DebugLib\ivyFastMap.obj +.\abclib\DebugLib\ivyFraig.obj +.\abclib\DebugLib\ivyHaig.obj +.\abclib\DebugLib\ivyMan.obj +.\abclib\DebugLib\ivyMem.obj +.\abclib\DebugLib\ivyMulti.obj +.\abclib\DebugLib\ivyObj.obj +.\abclib\DebugLib\ivyOper.obj +.\abclib\DebugLib\ivyResyn.obj +.\abclib\DebugLib\ivyRwr.obj +.\abclib\DebugLib\ivySeq.obj +.\abclib\DebugLib\ivyShow.obj +.\abclib\DebugLib\ivyTable.obj +.\abclib\DebugLib\ivyUtil.obj +.\abclib\DebugLib\rwtDec.obj +.\abclib\DebugLib\rwtMan.obj +.\abclib\DebugLib\rwtUtil.obj +.\abclib\DebugLib\mem.obj +.\abclib\DebugLib\jfront.obj +] +Creating command line "link.exe -lib @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP137B.tmp" +<h3>Output Window</h3> +Compiling... +jfront.c +Creating library... +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP137C.tmp" with contents +[ +/nologo /o"abclib\DebugLib/abclib.bsc" +.\abclib\DebugLib\abcAig.sbr +.\abclib\DebugLib\abcCheck.sbr +.\abclib\DebugLib\abcDfs.sbr +.\abclib\DebugLib\abcFanio.sbr +.\abclib\DebugLib\abcFunc.sbr +.\abclib\DebugLib\abcLatch.sbr +.\abclib\DebugLib\abcLib.sbr +.\abclib\DebugLib\abcMinBase.sbr +.\abclib\DebugLib\abcNames.sbr +.\abclib\DebugLib\abcNetlist.sbr +.\abclib\DebugLib\abcNtk.sbr +.\abclib\DebugLib\abcObj.sbr +.\abclib\DebugLib\abcRefs.sbr +.\abclib\DebugLib\abcShow.sbr +.\abclib\DebugLib\abcSop.sbr +.\abclib\DebugLib\abcUtil.sbr +.\abclib\DebugLib\abc.sbr +.\abclib\DebugLib\abcAttach.sbr +.\abclib\DebugLib\abcAuto.sbr +.\abclib\DebugLib\abcBalance.sbr +.\abclib\DebugLib\abcBmc.sbr +.\abclib\DebugLib\abcClpBdd.sbr +.\abclib\DebugLib\abcClpSop.sbr +.\abclib\DebugLib\abcCut.sbr +.\abclib\DebugLib\abcDebug.sbr +.\abclib\DebugLib\abcDress.sbr +.\abclib\DebugLib\abcDsd.sbr +.\abclib\DebugLib\abcEspresso.sbr +.\abclib\DebugLib\abcExtract.sbr +.\abclib\DebugLib\abcFpga.sbr +.\abclib\DebugLib\abcFpgaFast.sbr +.\abclib\DebugLib\abcFraig.sbr +.\abclib\DebugLib\abcFxu.sbr +.\abclib\DebugLib\abcGen.sbr +.\abclib\DebugLib\abcIf.sbr +.\abclib\DebugLib\abcIvy.sbr +.\abclib\DebugLib\abcLut.sbr +.\abclib\DebugLib\abcMap.sbr +.\abclib\DebugLib\abcMini.sbr +.\abclib\DebugLib\abcMiter.sbr +.\abclib\DebugLib\abcMulti.sbr +.\abclib\DebugLib\abcMv.sbr +.\abclib\DebugLib\abcNtbdd.sbr +.\abclib\DebugLib\abcOrder.sbr +.\abclib\DebugLib\abcPrint.sbr +.\abclib\DebugLib\abcProve.sbr +.\abclib\DebugLib\abcReconv.sbr +.\abclib\DebugLib\abcRefactor.sbr +.\abclib\DebugLib\abcRenode.sbr +.\abclib\DebugLib\abcReorder.sbr +.\abclib\DebugLib\abcRestruct.sbr +.\abclib\DebugLib\abcResub.sbr +.\abclib\DebugLib\abcRewrite.sbr +.\abclib\DebugLib\abcRr.sbr +.\abclib\DebugLib\abcSat.sbr +.\abclib\DebugLib\abcStrash.sbr +.\abclib\DebugLib\abcSweep.sbr +.\abclib\DebugLib\abcSymm.sbr +.\abclib\DebugLib\abcTiming.sbr +.\abclib\DebugLib\abcUnate.sbr +.\abclib\DebugLib\abcUnreach.sbr +.\abclib\DebugLib\abcVerify.sbr +.\abclib\DebugLib\abcXsim.sbr +.\abclib\DebugLib\cmd.sbr +.\abclib\DebugLib\cmdAlias.sbr +.\abclib\DebugLib\cmdApi.sbr +.\abclib\DebugLib\cmdFlag.sbr +.\abclib\DebugLib\cmdHist.sbr +.\abclib\DebugLib\cmdUtils.sbr +.\abclib\DebugLib\io.sbr +.\abclib\DebugLib\ioReadAiger.sbr +.\abclib\DebugLib\ioReadBaf.sbr +.\abclib\DebugLib\ioReadBench.sbr +.\abclib\DebugLib\ioReadBlif.sbr +.\abclib\DebugLib\ioReadBlifAig.sbr +.\abclib\DebugLib\ioReadEdif.sbr +.\abclib\DebugLib\ioReadEqn.sbr +.\abclib\DebugLib\ioReadPla.sbr +.\abclib\DebugLib\ioUtil.sbr +.\abclib\DebugLib\ioWriteAiger.sbr +.\abclib\DebugLib\ioWriteBaf.sbr +.\abclib\DebugLib\ioWriteBench.sbr +.\abclib\DebugLib\ioWriteBlif.sbr +.\abclib\DebugLib\ioWriteCnf.sbr +.\abclib\DebugLib\ioWriteDot.sbr +.\abclib\DebugLib\ioWriteEqn.sbr +.\abclib\DebugLib\ioWriteGml.sbr +.\abclib\DebugLib\ioWriteList.sbr +.\abclib\DebugLib\ioWritePla.sbr +.\abclib\DebugLib\ioWriteVer.sbr +.\abclib\DebugLib\ioWriteVerAux.sbr +.\abclib\DebugLib\libSupport.sbr +.\abclib\DebugLib\main.sbr +.\abclib\DebugLib\mainFrame.sbr +.\abclib\DebugLib\mainInit.sbr +.\abclib\DebugLib\mainUtils.sbr +.\abclib\DebugLib\verCore.sbr +.\abclib\DebugLib\verFormula.sbr +.\abclib\DebugLib\verParse.sbr +.\abclib\DebugLib\verStream.sbr +.\abclib\DebugLib\verWords.sbr +.\abclib\DebugLib\cuddAddAbs.sbr +.\abclib\DebugLib\cuddAddApply.sbr +.\abclib\DebugLib\cuddAddFind.sbr +.\abclib\DebugLib\cuddAddInv.sbr +.\abclib\DebugLib\cuddAddIte.sbr +.\abclib\DebugLib\cuddAddNeg.sbr +.\abclib\DebugLib\cuddAddWalsh.sbr +.\abclib\DebugLib\cuddAndAbs.sbr +.\abclib\DebugLib\cuddAnneal.sbr +.\abclib\DebugLib\cuddApa.sbr +.\abclib\DebugLib\cuddAPI.sbr +.\abclib\DebugLib\cuddApprox.sbr +.\abclib\DebugLib\cuddBddAbs.sbr +.\abclib\DebugLib\cuddBddCorr.sbr +.\abclib\DebugLib\cuddBddIte.sbr +.\abclib\DebugLib\cuddBridge.sbr +.\abclib\DebugLib\cuddCache.sbr +.\abclib\DebugLib\cuddCheck.sbr +.\abclib\DebugLib\cuddClip.sbr +.\abclib\DebugLib\cuddCof.sbr +.\abclib\DebugLib\cuddCompose.sbr +.\abclib\DebugLib\cuddDecomp.sbr +.\abclib\DebugLib\cuddEssent.sbr +.\abclib\DebugLib\cuddExact.sbr +.\abclib\DebugLib\cuddExport.sbr +.\abclib\DebugLib\cuddGenCof.sbr +.\abclib\DebugLib\cuddGenetic.sbr +.\abclib\DebugLib\cuddGroup.sbr +.\abclib\DebugLib\cuddHarwell.sbr +.\abclib\DebugLib\cuddInit.sbr +.\abclib\DebugLib\cuddInteract.sbr +.\abclib\DebugLib\cuddLCache.sbr +.\abclib\DebugLib\cuddLevelQ.sbr +.\abclib\DebugLib\cuddLinear.sbr +.\abclib\DebugLib\cuddLiteral.sbr +.\abclib\DebugLib\cuddMatMult.sbr +.\abclib\DebugLib\cuddPriority.sbr +.\abclib\DebugLib\cuddRead.sbr +.\abclib\DebugLib\cuddRef.sbr +.\abclib\DebugLib\cuddReorder.sbr +.\abclib\DebugLib\cuddSat.sbr +.\abclib\DebugLib\cuddSign.sbr +.\abclib\DebugLib\cuddSolve.sbr +.\abclib\DebugLib\cuddSplit.sbr +.\abclib\DebugLib\cuddSubsetHB.sbr +.\abclib\DebugLib\cuddSubsetSP.sbr +.\abclib\DebugLib\cuddSymmetry.sbr +.\abclib\DebugLib\cuddTable.sbr +.\abclib\DebugLib\cuddUtil.sbr +.\abclib\DebugLib\cuddWindow.sbr +.\abclib\DebugLib\cuddZddCount.sbr +.\abclib\DebugLib\cuddZddFuncs.sbr +.\abclib\DebugLib\cuddZddGroup.sbr +.\abclib\DebugLib\cuddZddIsop.sbr +.\abclib\DebugLib\cuddZddLin.sbr +.\abclib\DebugLib\cuddZddMisc.sbr +.\abclib\DebugLib\cuddZddPort.sbr +.\abclib\DebugLib\cuddZddReord.sbr +.\abclib\DebugLib\cuddZddSetop.sbr +.\abclib\DebugLib\cuddZddSymm.sbr +.\abclib\DebugLib\cuddZddUtil.sbr +.\abclib\DebugLib\epd.sbr +.\abclib\DebugLib\mtrBasic.sbr +.\abclib\DebugLib\mtrGroup.sbr +.\abclib\DebugLib\parseCore.sbr +.\abclib\DebugLib\parseEqn.sbr +.\abclib\DebugLib\parseStack.sbr +.\abclib\DebugLib\dsdApi.sbr +.\abclib\DebugLib\dsdCheck.sbr +.\abclib\DebugLib\dsdLocal.sbr +.\abclib\DebugLib\dsdMan.sbr +.\abclib\DebugLib\dsdProc.sbr +.\abclib\DebugLib\dsdTree.sbr +.\abclib\DebugLib\reoApi.sbr +.\abclib\DebugLib\reoCore.sbr +.\abclib\DebugLib\reoProfile.sbr +.\abclib\DebugLib\reoSift.sbr +.\abclib\DebugLib\reoSwap.sbr +.\abclib\DebugLib\reoTest.sbr +.\abclib\DebugLib\reoTransfer.sbr +.\abclib\DebugLib\reoUnits.sbr +.\abclib\DebugLib\added.sbr +.\abclib\DebugLib\asatmem.sbr +.\abclib\DebugLib\solver.sbr +.\abclib\DebugLib\msatActivity.sbr +.\abclib\DebugLib\msatClause.sbr +.\abclib\DebugLib\msatClauseVec.sbr +.\abclib\DebugLib\msatMem.sbr +.\abclib\DebugLib\msatOrderH.sbr +.\abclib\DebugLib\msatQueue.sbr +.\abclib\DebugLib\msatRead.sbr +.\abclib\DebugLib\msatSolverApi.sbr +.\abclib\DebugLib\msatSolverCore.sbr +.\abclib\DebugLib\msatSolverIo.sbr +.\abclib\DebugLib\msatSolverSearch.sbr +.\abclib\DebugLib\msatSort.sbr +.\abclib\DebugLib\msatVec.sbr +.\abclib\DebugLib\fraigApi.sbr +.\abclib\DebugLib\fraigCanon.sbr +.\abclib\DebugLib\fraigChoice.sbr +.\abclib\DebugLib\fraigFanout.sbr +.\abclib\DebugLib\fraigFeed.sbr +.\abclib\DebugLib\fraigMan.sbr +.\abclib\DebugLib\fraigMem.sbr +.\abclib\DebugLib\fraigNode.sbr +.\abclib\DebugLib\fraigPrime.sbr +.\abclib\DebugLib\fraigSat.sbr +.\abclib\DebugLib\fraigTable.sbr +.\abclib\DebugLib\fraigUtil.sbr +.\abclib\DebugLib\fraigVec.sbr +.\abclib\DebugLib\csat_apis.sbr +.\abclib\DebugLib\satMem.sbr +.\abclib\DebugLib\satSolver.sbr +.\abclib\DebugLib\satUtil.sbr +.\abclib\DebugLib\fxu.sbr +.\abclib\DebugLib\fxuCreate.sbr +.\abclib\DebugLib\fxuHeapD.sbr +.\abclib\DebugLib\fxuHeapS.sbr +.\abclib\DebugLib\fxuList.sbr +.\abclib\DebugLib\fxuMatrix.sbr +.\abclib\DebugLib\fxuPair.sbr +.\abclib\DebugLib\fxuPrint.sbr +.\abclib\DebugLib\fxuReduce.sbr +.\abclib\DebugLib\fxuSelect.sbr +.\abclib\DebugLib\fxuSingle.sbr +.\abclib\DebugLib\fxuUpdate.sbr +.\abclib\DebugLib\rwrDec.sbr +.\abclib\DebugLib\rwrEva.sbr +.\abclib\DebugLib\rwrExp.sbr +.\abclib\DebugLib\rwrLib.sbr +.\abclib\DebugLib\rwrMan.sbr +.\abclib\DebugLib\rwrPrint.sbr +.\abclib\DebugLib\rwrTemp.sbr +.\abclib\DebugLib\rwrUtil.sbr +.\abclib\DebugLib\cutApi.sbr +.\abclib\DebugLib\cutCut.sbr +.\abclib\DebugLib\cutExpand.sbr +.\abclib\DebugLib\cutMan.sbr +.\abclib\DebugLib\cutMerge.sbr +.\abclib\DebugLib\cutNode.sbr +.\abclib\DebugLib\cutOracle.sbr +.\abclib\DebugLib\cutPre22.sbr +.\abclib\DebugLib\cutSeq.sbr +.\abclib\DebugLib\cutTruth.sbr +.\abclib\DebugLib\decAbc.sbr +.\abclib\DebugLib\decFactor.sbr +.\abclib\DebugLib\decMan.sbr +.\abclib\DebugLib\decPrint.sbr +.\abclib\DebugLib\decUtil.sbr +.\abclib\DebugLib\simMan.sbr +.\abclib\DebugLib\simSat.sbr +.\abclib\DebugLib\simSeq.sbr +.\abclib\DebugLib\simSupp.sbr +.\abclib\DebugLib\simSwitch.sbr +.\abclib\DebugLib\simSym.sbr +.\abclib\DebugLib\simSymSat.sbr +.\abclib\DebugLib\simSymSim.sbr +.\abclib\DebugLib\simSymStr.sbr +.\abclib\DebugLib\simUtils.sbr +.\abclib\DebugLib\retArea.sbr +.\abclib\DebugLib\retCore.sbr +.\abclib\DebugLib\retDelay.sbr +.\abclib\DebugLib\retFlow.sbr +.\abclib\DebugLib\retIncrem.sbr +.\abclib\DebugLib\retInit.sbr +.\abclib\DebugLib\retLvalue.sbr +.\abclib\DebugLib\kitBdd.sbr +.\abclib\DebugLib\kitFactor.sbr +.\abclib\DebugLib\kitGraph.sbr +.\abclib\DebugLib\kitHop.sbr +.\abclib\DebugLib\kitIsop.sbr +.\abclib\DebugLib\kitSop.sbr +.\abclib\DebugLib\kitTruth.sbr +.\abclib\DebugLib\fpga.sbr +.\abclib\DebugLib\fpgaCore.sbr +.\abclib\DebugLib\fpgaCreate.sbr +.\abclib\DebugLib\fpgaCut.sbr +.\abclib\DebugLib\fpgaCutUtils.sbr +.\abclib\DebugLib\fpgaFanout.sbr +.\abclib\DebugLib\fpgaLib.sbr +.\abclib\DebugLib\fpgaMatch.sbr +.\abclib\DebugLib\fpgaSwitch.sbr +.\abclib\DebugLib\fpgaTime.sbr +.\abclib\DebugLib\fpgaTruth.sbr +.\abclib\DebugLib\fpgaUtils.sbr +.\abclib\DebugLib\fpgaVec.sbr +.\abclib\DebugLib\mapper.sbr +.\abclib\DebugLib\mapperCanon.sbr +.\abclib\DebugLib\mapperCore.sbr +.\abclib\DebugLib\mapperCreate.sbr +.\abclib\DebugLib\mapperCut.sbr +.\abclib\DebugLib\mapperCutUtils.sbr +.\abclib\DebugLib\mapperFanout.sbr +.\abclib\DebugLib\mapperLib.sbr +.\abclib\DebugLib\mapperMatch.sbr +.\abclib\DebugLib\mapperRefs.sbr +.\abclib\DebugLib\mapperSuper.sbr +.\abclib\DebugLib\mapperSwitch.sbr +.\abclib\DebugLib\mapperTable.sbr +.\abclib\DebugLib\mapperTime.sbr +.\abclib\DebugLib\mapperTree.sbr +.\abclib\DebugLib\mapperTruth.sbr +.\abclib\DebugLib\mapperUtils.sbr +.\abclib\DebugLib\mapperVec.sbr +.\abclib\DebugLib\mio.sbr +.\abclib\DebugLib\mioApi.sbr +.\abclib\DebugLib\mioFunc.sbr +.\abclib\DebugLib\mioRead.sbr +.\abclib\DebugLib\mioUtils.sbr +.\abclib\DebugLib\super.sbr +.\abclib\DebugLib\superAnd.sbr +.\abclib\DebugLib\superGate.sbr +.\abclib\DebugLib\superWrite.sbr +.\abclib\DebugLib\ifCore.sbr +.\abclib\DebugLib\ifCut.sbr +.\abclib\DebugLib\ifMan.sbr +.\abclib\DebugLib\ifMap.sbr +.\abclib\DebugLib\ifPrepro.sbr +.\abclib\DebugLib\ifReduce.sbr +.\abclib\DebugLib\ifSeq.sbr +.\abclib\DebugLib\ifTime.sbr +.\abclib\DebugLib\ifTruth.sbr +.\abclib\DebugLib\ifUtil.sbr +.\abclib\DebugLib\extraBddAuto.sbr +.\abclib\DebugLib\extraBddKmap.sbr +.\abclib\DebugLib\extraBddMisc.sbr +.\abclib\DebugLib\extraBddSymm.sbr +.\abclib\DebugLib\extraBddUnate.sbr +.\abclib\DebugLib\extraUtilBitMatrix.sbr +.\abclib\DebugLib\extraUtilCanon.sbr +.\abclib\DebugLib\extraUtilFile.sbr +.\abclib\DebugLib\extraUtilMemory.sbr +.\abclib\DebugLib\extraUtilMisc.sbr +.\abclib\DebugLib\extraUtilProgress.sbr +.\abclib\DebugLib\extraUtilReader.sbr +.\abclib\DebugLib\extraUtilTruth.sbr +.\abclib\DebugLib\extraUtilUtil.sbr +.\abclib\DebugLib\st.sbr +.\abclib\DebugLib\stmm.sbr +.\abclib\DebugLib\mvc.sbr +.\abclib\DebugLib\mvcApi.sbr +.\abclib\DebugLib\mvcCompare.sbr +.\abclib\DebugLib\mvcContain.sbr +.\abclib\DebugLib\mvcCover.sbr +.\abclib\DebugLib\mvcCube.sbr +.\abclib\DebugLib\mvcDivide.sbr +.\abclib\DebugLib\mvcDivisor.sbr +.\abclib\DebugLib\mvcList.sbr +.\abclib\DebugLib\mvcLits.sbr +.\abclib\DebugLib\mvcMan.sbr +.\abclib\DebugLib\mvcOpAlg.sbr +.\abclib\DebugLib\mvcOpBool.sbr +.\abclib\DebugLib\mvcPrint.sbr +.\abclib\DebugLib\mvcSort.sbr +.\abclib\DebugLib\mvcUtils.sbr +.\abclib\DebugLib\cofactor.sbr +.\abclib\DebugLib\cols.sbr +.\abclib\DebugLib\compl.sbr +.\abclib\DebugLib\contain.sbr +.\abclib\DebugLib\cubehack.sbr +.\abclib\DebugLib\cubestr.sbr +.\abclib\DebugLib\cvrin.sbr +.\abclib\DebugLib\cvrm.sbr +.\abclib\DebugLib\cvrmisc.sbr +.\abclib\DebugLib\cvrout.sbr +.\abclib\DebugLib\dominate.sbr +.\abclib\DebugLib\equiv.sbr +.\abclib\DebugLib\espresso.sbr +.\abclib\DebugLib\essen.sbr +.\abclib\DebugLib\exact.sbr +.\abclib\DebugLib\expand.sbr +.\abclib\DebugLib\gasp.sbr +.\abclib\DebugLib\gimpel.sbr +.\abclib\DebugLib\globals.sbr +.\abclib\DebugLib\hack.sbr +.\abclib\DebugLib\indep.sbr +.\abclib\DebugLib\irred.sbr +.\abclib\DebugLib\map.sbr +.\abclib\DebugLib\matrix.sbr +.\abclib\DebugLib\mincov.sbr +.\abclib\DebugLib\opo.sbr +.\abclib\DebugLib\pair.sbr +.\abclib\DebugLib\part.sbr +.\abclib\DebugLib\primes.sbr +.\abclib\DebugLib\reduce.sbr +.\abclib\DebugLib\rows.sbr +.\abclib\DebugLib\set.sbr +.\abclib\DebugLib\setc.sbr +.\abclib\DebugLib\sharp.sbr +.\abclib\DebugLib\sminterf.sbr +.\abclib\DebugLib\solution.sbr +.\abclib\DebugLib\sparse.sbr +.\abclib\DebugLib\unate.sbr +.\abclib\DebugLib\verify.sbr +.\abclib\DebugLib\nmApi.sbr +.\abclib\DebugLib\nmTable.sbr +.\abclib\DebugLib\hopBalance.sbr +.\abclib\DebugLib\hopCheck.sbr +.\abclib\DebugLib\hopDfs.sbr +.\abclib\DebugLib\hopMan.sbr +.\abclib\DebugLib\hopMem.sbr +.\abclib\DebugLib\hopObj.sbr +.\abclib\DebugLib\hopOper.sbr +.\abclib\DebugLib\hopTable.sbr +.\abclib\DebugLib\hopUtil.sbr +.\abclib\DebugLib\ivyBalance.sbr +.\abclib\DebugLib\ivyCanon.sbr +.\abclib\DebugLib\ivyCheck.sbr +.\abclib\DebugLib\ivyCut.sbr +.\abclib\DebugLib\ivyCutTrav.sbr +.\abclib\DebugLib\ivyDfs.sbr +.\abclib\DebugLib\ivyDsd.sbr +.\abclib\DebugLib\ivyFanout.sbr +.\abclib\DebugLib\ivyFastMap.sbr +.\abclib\DebugLib\ivyFraig.sbr +.\abclib\DebugLib\ivyHaig.sbr +.\abclib\DebugLib\ivyMan.sbr +.\abclib\DebugLib\ivyMem.sbr +.\abclib\DebugLib\ivyMulti.sbr +.\abclib\DebugLib\ivyObj.sbr +.\abclib\DebugLib\ivyOper.sbr +.\abclib\DebugLib\ivyResyn.sbr +.\abclib\DebugLib\ivyRwr.sbr +.\abclib\DebugLib\ivySeq.sbr +.\abclib\DebugLib\ivyShow.sbr +.\abclib\DebugLib\ivyTable.sbr +.\abclib\DebugLib\ivyUtil.sbr +.\abclib\DebugLib\rwtDec.sbr +.\abclib\DebugLib\rwtMan.sbr +.\abclib\DebugLib\rwtUtil.sbr +.\abclib\DebugLib\mem.sbr +.\abclib\DebugLib\jfront.sbr] +Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP137C.tmp" +Creating browse info file... +<h3>Output Window</h3> + + + +<h3>Results</h3> +abclib_debug.lib - 0 error(s), 0 warning(s) +</pre> +</body> +</html> diff --git a/abctestlib.plg b/abctestlib.plg new file mode 100644 index 00000000..0d4fd935 --- /dev/null +++ b/abctestlib.plg @@ -0,0 +1,35 @@ +<html> +<body> +<pre> +<h1>Build Log</h1> +<h3> +--------------------Configuration: abctestlib - Win32 Debug-------------------- +</h3> +<h3>Command Lines</h3> +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1389.tmp" with contents +[ +/nologo /MLd /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /FR"Debug/" /Fp"Debug/abctestlib.pch" /YX /Fo"Debug/" /Fd"Debug/" /FD /GZ /c +"C:\_projects\abc\demo.c" +] +Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1389.tmp" +Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP138A.tmp" with contents +[ +kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib C:\_projects\abc\abclib\abclib_debug.lib /nologo /subsystem:console /incremental:yes /pdb:"Debug/abctestlib.pdb" /debug /machine:I386 /out:"_TEST/abctestlib.exe" /pdbtype:sept +.\Debug\demo.obj +] +Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP138A.tmp" +<h3>Output Window</h3> +Compiling... +demo.c +Linking... +Creating command line "bscmake.exe /nologo /o"Debug/abctestlib.bsc" .\Debug\demo.sbr" +Creating browse info file... +<h3>Output Window</h3> + + + +<h3>Results</h3> +abctestlib.exe - 0 error(s), 0 warning(s) +</pre> +</body> +</html> diff --git a/src/aig/hop/hopUtil.c b/src/aig/hop/hopUtil.c index a49e8397..9b5bf686 100644 --- a/src/aig/hop/hopUtil.c +++ b/src/aig/hop/hopUtil.c @@ -351,7 +351,7 @@ void Hop_ObjPrintVerilog( FILE * pFile, Hop_Obj_t * pObj, Vec_Vec_t * vLevels, i // constant case if ( Hop_ObjIsConst1(pObj) ) { - fprintf( pFile, "%d", !fCompl ); + fprintf( pFile, "1\'b%d", !fCompl ); return; } // PI case diff --git a/src/base/abc/abcCheck.c b/src/base/abc/abcCheck.c index 72597881..e159bcab 100644 --- a/src/base/abc/abcCheck.c +++ b/src/base/abc/abcCheck.c @@ -140,6 +140,9 @@ bool Abc_NtkDoCheck( Abc_Ntk_t * pNtk ) if ( !Abc_NtkCheckPos( pNtk ) ) return 0; + if ( Abc_NtkHasBlackbox(pNtk) ) + return 1; + // check the connectivity of objects Abc_NtkForEachObj( pNtk, pObj, i ) if ( !Abc_NtkCheckObj( pNtk, pObj ) ) @@ -236,41 +239,27 @@ bool Abc_NtkCheckNames( Abc_Ntk_t * pNtk ) Vec_Int_t * vNameIds; char * pName; int i, NameId; -/* + if ( Abc_NtkIsNetlist(pNtk) ) - { + return 1; - // check that each net has a name - Abc_NtkForEachNet( pNtk, pObj, i ) + // check that each CI/CO has a name + Abc_NtkForEachCi( pNtk, pObj, i ) + { + pObj = Abc_ObjFanout0Ntk(pObj); + if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL ) { - if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) ) - { - fprintf( stdout, "NetworkCheck: Net \"%s\" has different name in the name table and at the data pointer.\n", pObj->pData ); - return 0; - } + fprintf( stdout, "NetworkCheck: CI with ID %d is in the network but not in the name table.\n", pObj->Id ); + return 0; } } - else -*/ + Abc_NtkForEachCo( pNtk, pObj, i ) { - // check that each CI/CO has a name - Abc_NtkForEachCi( pNtk, pObj, i ) + pObj = Abc_ObjFanin0Ntk(pObj); + if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL ) { - pObj = Abc_ObjFanout0Ntk(pObj); - if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL ) - { - fprintf( stdout, "NetworkCheck: CI with ID %d is in the network but not in the name table.\n", pObj->Id ); - return 0; - } - } - Abc_NtkForEachCo( pNtk, pObj, i ) - { - pObj = Abc_ObjFanin0Ntk(pObj); - if ( Nm_ManFindNameById(pObj->pNtk->pManName, pObj->Id) == NULL ) - { - fprintf( stdout, "NetworkCheck: CO with ID %d is in the network but not in the name table.\n", pObj->Id ); - return 0; - } + fprintf( stdout, "NetworkCheck: CO with ID %d is in the network but not in the name table.\n", pObj->Id ); + return 0; } } diff --git a/src/base/abc/abcHie.c b/src/base/abc/abcHie.c index a804203f..1047650f 100644 --- a/src/base/abc/abcHie.c +++ b/src/base/abc/abcHie.c @@ -265,7 +265,7 @@ Abc_Ntk_t * Abc_NtkConvertBlackboxes( Abc_Ntk_t * pNtk ) Abc_ObjForEachFanin( pObj, pTerm, k ) { pNet = Abc_ObjFanin0(pTerm); - if ( pNet->pCopy ) + if ( pNet->pCopy && !Abc_ObjIsCi(Abc_ObjFanin0(pNet)) ) { Abc_NodeSetTravIdCurrent( pTerm ); continue; @@ -315,13 +315,14 @@ Abc_Ntk_t * Abc_NtkConvertBlackboxes( Abc_Ntk_t * pNtk ) ***********************************************************************/ Abc_Ntk_t * Abc_NtkInsertNewLogic( Abc_Ntk_t * pNtkH, Abc_Ntk_t * pNtkL ) { + Abc_Lib_t * pDesign; Abc_Ntk_t * pNtkNew; Abc_Obj_t * pObjH, * pObjL, * pNetH, * pNetL, * pTermH; int i, k; assert( Abc_NtkIsNetlist(pNtkH) ); assert( Abc_NtkWhiteboxNum(pNtkH) == 0 ); - assert( Abc_NtkBlackboxNum(pNtkL) > 0 ); + assert( Abc_NtkBlackboxNum(pNtkH) > 0 ); assert( Abc_NtkIsNetlist(pNtkL) ); assert( Abc_NtkWhiteboxNum(pNtkL) == 0 ); @@ -343,38 +344,73 @@ Abc_Ntk_t * Abc_NtkInsertNewLogic( Abc_Ntk_t * pNtkH, Abc_Ntk_t * pNtkL ) pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) ); if ( pNetL == NULL || !Abc_ObjIsPi( Abc_ObjFanin0(pNetL) ) ) { - printf( "There is no PI corresponding to the PI %s.\n", Abc_ObjName(pNetH) ); + printf( "Error in Abc_NtkInsertNewLogic(): There is no PI corresponding to the PI %s.\n", Abc_ObjName(pNetH) ); + Abc_NtkDelete( pNtkNew ); + return NULL; + } + if ( pNetL->pCopy ) + { + printf( "Error in Abc_NtkInsertNewLogic(): Primary input %s is repeated twice.\n", Abc_ObjName(pNetH) ); Abc_NtkDelete( pNtkNew ); return NULL; } - // duplicate + // create the new net pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) ); Abc_NtkDupObj( pNtkNew, Abc_ObjFanin0(pNetL), 0 ); } + + // make sure every BB has a PI/PO in the processed network + Abc_NtkForEachBlackbox( pNtkH, pObjH, i ) + { + // duplicate the box + Abc_NtkDupBox( pNtkNew, pObjH, 0 ); + pObjH->pCopy->pData = pObjH->pData; + // create PIs + Abc_ObjForEachFanout( pObjH, pTermH, k ) + { + pNetH = Abc_ObjFanout0( pTermH ); + pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) ); + if ( pNetL == NULL || !Abc_ObjIsPi( Abc_ObjFanin0(pNetL) ) ) + { + printf( "Error in Abc_NtkInsertNewLogic(): There is no PI corresponding to the inpout %s of blackbox %s.\n", Abc_ObjName(pNetH), Abc_ObjName(pObjH) ); + Abc_NtkDelete( pNtkNew ); + return NULL; + } + if ( pNetL->pCopy ) + { + printf( "Error in Abc_NtkInsertNewLogic(): Box output %s is repeated twice.\n", Abc_ObjName(pNetH) ); + Abc_NtkDelete( pNtkNew ); + return NULL; + } + // create net and map the PI + pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) ); + Abc_ObjFanin0(pNetL)->pCopy = pTermH->pCopy; + } + } + Abc_NtkForEachPo( pNtkH, pObjH, i ) { pNetH = Abc_ObjFanin0(pObjH); pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) ); if ( pNetL == NULL || !Abc_ObjIsPo( Abc_ObjFanout0(pNetL) ) ) { - printf( "There is no PO corresponding to the PO %s.\n", Abc_ObjName(pNetH) ); + printf( "Error in Abc_NtkInsertNewLogic(): There is no PO corresponding to the PO %s.\n", Abc_ObjName(pNetH) ); Abc_NtkDelete( pNtkNew ); return NULL; } - // duplicate + if ( pNetL->pCopy ) + continue; + // create the new net pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) ); Abc_NtkDupObj( pNtkNew, Abc_ObjFanout0(pNetL), 0 ); } - - // make sure every BB has a PI/PO in the processed network Abc_NtkForEachBlackbox( pNtkH, pObjH, i ) { - // duplicate the box - Abc_NtkDupObj( pNtkNew, pObjH, 1 ); - // look and fanins/fanouts of the box Abc_ObjForEachFanin( pObjH, pTermH, k ) { + char * pName; pNetH = Abc_ObjFanin0( pTermH ); + pName = Abc_ObjName(pNetH); pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) ); if ( pNetL == NULL || !Abc_ObjIsPo( Abc_ObjFanout0(pNetL) ) ) { @@ -382,39 +418,39 @@ Abc_Ntk_t * Abc_NtkInsertNewLogic( Abc_Ntk_t * pNtkH, Abc_Ntk_t * pNtkL ) Abc_NtkDelete( pNtkNew ); return NULL; } - // duplicate - pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) ); - Abc_NtkDupObj( pNtkNew, Abc_ObjFanout0(pNetL), 0 ); - // connect - Abc_ObjAddFanin( pObjH->pCopy, Abc_ObjFanout0(pNetL)->pCopy ); - } - Abc_ObjForEachFanout( pObjH, pTermH, k ) - { - pNetH = Abc_ObjFanout0( pTermH ); - pNetL = Abc_NtkFindNet( pNtkL, Abc_ObjName(pNetH) ); - if ( pNetL == NULL || !Abc_ObjIsPi( Abc_ObjFanin0(pNetL) ) ) + // create net and map the PO + if ( pNetL->pCopy ) { - printf( "There is no PI corresponding to the inpout %s of blackbox %s.\n", Abc_ObjName(pNetH), Abc_ObjName(pObjH) ); - Abc_NtkDelete( pNtkNew ); - return NULL; + if ( Abc_ObjFanout0(pNetL)->pCopy == NULL ) + Abc_ObjFanout0(pNetL)->pCopy = pTermH->pCopy; + else + Abc_ObjAddFanin( pTermH->pCopy, pNetL->pCopy ); + continue; } - // duplicate pNetL->pCopy = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pNetH) ); - Abc_NtkDupObj( pNtkNew, Abc_ObjFanin0(pNetL), 0 ); - // connect - Abc_ObjAddFanin( Abc_ObjFanin0(pNetL)->pCopy, pObjH->pCopy ); + Abc_ObjFanout0(pNetL)->pCopy = pTermH->pCopy; } } // duplicate other objects of the logic network Abc_NtkForEachObj( pNtkL, pObjL, i ) - if ( pObjL->pCopy ) - Abc_NtkDupObj( pNtkNew, pObjL, 0 ); + if ( pObjL->pCopy == NULL && !Abc_ObjIsPo(pObjL) ) // skip POs feeding into PIs + Abc_NtkDupObj( pNtkNew, pObjL, Abc_ObjIsNet(pObjL) ); // connect objects Abc_NtkForEachObj( pNtkL, pObjL, i ) Abc_ObjForEachFanin( pObjL, pNetL, k ) - Abc_ObjAddFanin( pObjL->pCopy, pNetL->pCopy ); + if ( pObjL->pCopy ) + Abc_ObjAddFanin( pObjL->pCopy, pNetL->pCopy ); + + // transfer the design + pDesign = pNtkH->pDesign; pNtkH->pDesign = NULL; + assert( Vec_PtrEntry( pDesign->vModules, 0 ) == pNtkH ); + Vec_PtrWriteEntry( pDesign->vModules, 0, pNtkNew ); + pNtkNew->pDesign = pDesign; + +//Abc_NtkPrintStats( stdout, pNtkH, 0 ); +//Abc_NtkPrintStats( stdout, pNtkNew, 0 ); // check integrity if ( !Abc_NtkCheck( pNtkNew ) ) diff --git a/src/base/abc/abcObj.c b/src/base/abc/abcObj.c index d55ccfcf..4931f238 100644 --- a/src/base/abc/abcObj.c +++ b/src/base/abc/abcObj.c @@ -329,7 +329,15 @@ Abc_Obj_t * Abc_NtkDupObj( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pObj, int fCopyName else if ( Abc_ObjIsCo(pObj) ) { if ( !Abc_NtkIsNetlist(pNtkNew) ) - Abc_ObjAssignName( pObjNew, Abc_ObjName(Abc_ObjFanin0Ntk(pObj)), NULL ); + { + if ( Abc_ObjIsPo(pObj) ) + Abc_ObjAssignName( pObjNew, Abc_ObjName(Abc_ObjFanin0Ntk(pObj)), NULL ); + else + { + assert( Abc_ObjIsLatch(Abc_ObjFanout0(pObj)) ); + Abc_ObjAssignName( pObjNew, Abc_ObjName(pObj), NULL ); + } + } } else if ( Abc_ObjIsBox(pObj) || Abc_ObjIsNet(pObj) ) Abc_ObjAssignName( pObjNew, Abc_ObjName(pObj), NULL ); diff --git a/src/base/abci/abcPrint.c b/src/base/abci/abcPrint.c index 59ce1674..0a917bbb 100644 --- a/src/base/abci/abcPrint.c +++ b/src/base/abci/abcPrint.c @@ -62,7 +62,8 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored ) { fprintf( pFile, " net = %5d", Abc_NtkNetNum(pNtk) ); fprintf( pFile, " nd = %5d", Abc_NtkNodeNum(pNtk) ); - fprintf( pFile, " box = %5d", Abc_NtkBoxNum(pNtk) ); + fprintf( pFile, " wbox = %3d", Abc_NtkWhiteboxNum(pNtk) ); + fprintf( pFile, " bbox = %3d", Abc_NtkBlackboxNum(pNtk) ); } else if ( Abc_NtkIsStrash(pNtk) ) { diff --git a/src/base/io/io.c b/src/base/io/io.c index 64451118..e79e1857 100644 --- a/src/base/io/io.c +++ b/src/base/io/io.c @@ -85,7 +85,7 @@ void Io_Init( Abc_Frame_t * pAbc ) Cmd_CommandAdd( pAbc, "I/O", "read_eqn", IoCommandReadEqn, 1 ); Cmd_CommandAdd( pAbc, "I/O", "read_pla", IoCommandReadPla, 1 ); Cmd_CommandAdd( pAbc, "I/O", "read_truth", IoCommandReadTruth, 1 ); -// Cmd_CommandAdd( pAbc, "I/O", "read_verilog", IoCommandReadVerilog, 1 ); + Cmd_CommandAdd( pAbc, "I/O", "read_verilog", IoCommandReadVerilog, 1 ); // Cmd_CommandAdd( pAbc, "I/O", "read_ver", IoCommandReadVer, 1 ); // Cmd_CommandAdd( pAbc, "I/O", "read_verlib", IoCommandReadVerLib, 0 ); @@ -103,7 +103,7 @@ void Io_Init( Abc_Frame_t * pAbc ) Cmd_CommandAdd( pAbc, "I/O", "write_gml", IoCommandWriteGml, 0 ); // Cmd_CommandAdd( pAbc, "I/O", "write_list", IoCommandWriteList, 0 ); Cmd_CommandAdd( pAbc, "I/O", "write_pla", IoCommandWritePla, 0 ); -// Cmd_CommandAdd( pAbc, "I/O", "write_verilog", IoCommandWriteVerilog, 0 ); + Cmd_CommandAdd( pAbc, "I/O", "write_verilog", IoCommandWriteVerilog, 0 ); // Cmd_CommandAdd( pAbc, "I/O", "write_verlib", IoCommandWriteVerLib, 0 ); } @@ -995,7 +995,7 @@ int IoCommandWriteHie( Abc_Frame_t * pAbc, int argc, char **argv ) pFileName = argv[globalUtilOptind+1]; // call the corresponding file writer // Io_Write( pAbc->pNtkCur, pFileName, Io_ReadFileType(pFileName) ); - Io_WriteHie( pAbc->pNtkCur, pFileName, Io_ReadFileType(pFileName), pBaseName ); + Io_WriteHie( pAbc->pNtkCur, pBaseName, pFileName ); return 0; usage: diff --git a/src/base/io/io.h b/src/base/io/io.h index 91be5ee5..8ce7c690 100644 --- a/src/base/io/io.h +++ b/src/base/io/io.h @@ -82,10 +82,10 @@ extern Abc_Ntk_t * Io_ReadBench( char * pFileName, int fCheck ); extern Abc_Ntk_t * Io_ReadEdif( char * pFileName, int fCheck ); /*=== abcReadEqn.c ============================================================*/ extern Abc_Ntk_t * Io_ReadEqn( char * pFileName, int fCheck ); -/*=== abcReadVerilog.c ========================================================*/ -extern Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ); /*=== abcReadPla.c ============================================================*/ extern Abc_Ntk_t * Io_ReadPla( char * pFileName, int fCheck ); +/*=== abcReadVerilog.c ========================================================*/ +extern Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ); /*=== abcWriteAiger.c =========================================================*/ extern void Io_WriteAiger( Abc_Ntk_t * pNtk, char * pFileName ); /*=== abcWriteBaf.c ===========================================================*/ @@ -114,14 +114,14 @@ extern void Io_WriteList( Abc_Ntk_t * pNtk, char * pFileName, int /*=== abcWritePla.c ===========================================================*/ extern int Io_WritePla( Abc_Ntk_t * pNtk, char * FileName ); /*=== abcWriteVerilog.c =======================================================*/ -extern void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * FileName, int fVerLibStyle ); +extern void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * FileName ); /*=== abcUtil.c ===============================================================*/ extern Io_FileType_t Io_ReadFileType( char * pFileName ); extern Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck ); extern Abc_Ntk_t * Io_Read( char * pFileName, Io_FileType_t FileType, int fCheck ); extern Abc_Ntk_t * Io_ReadHie( char * pFileName, Io_FileType_t FileType, int fCheck ); extern void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ); -extern void Io_WriteHie( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType, char * pBaseName ); +extern void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName ); extern Abc_Obj_t * Io_ReadCreatePi( Abc_Ntk_t * pNtk, char * pName ); extern Abc_Obj_t * Io_ReadCreatePo( Abc_Ntk_t * pNtk, char * pName ); extern Abc_Obj_t * Io_ReadCreateAssert( Abc_Ntk_t * pNtk, char * pName ); diff --git a/src/base/io/ioReadVerilog.c b/src/base/io/ioReadVerilog.c index 4550d286..eda2d0b0 100644 --- a/src/base/io/ioReadVerilog.c +++ b/src/base/io/ioReadVerilog.c @@ -6,7 +6,7 @@ PackageName [Command processing package.] - Synopsis [Procedures to read a subset of structural Verilog from IWLS 2005 benchmark.] + Synopsis [Procedure to read network from file.] Author [Alan Mishchenko] @@ -24,99 +24,7 @@ /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// -typedef struct Io_ReadVer_t_ Io_ReadVer_t; // all reading info -struct Io_ReadVer_t_ -{ - // general info about file - char * pFileName; // the name of the file - Extra_FileReader_t* pReader; // the input file reader - // current processing info - st_table * tKeywords; // mapping of keywords into codes - Abc_Ntk_t * pNtk; // the primary network - // the error message - FILE * Output; // the output stream - char sError[1000]; // the error string generated during parsing - int LineCur; // the line currently being parsed - Vec_Ptr_t * vSkipped; // temporary storage for skipped objects -}; - -// verilog keyword types -typedef enum { - VER_NONE = 0, - VER_MODULE = -1, - VER_ENDMODULE = -2, - VER_INPUT = -3, - VER_OUTPUT = -4, - VER_INOUT = -5, - VER_WIRE = -6, - VER_ASSIGN = -7 -} Ver_KeywordType_t; - -// the list of verilog keywords -static char * s_Keywords[10] = -{ - NULL, // unused - "module", // -1 - "endmodule", // -2 - "input", // -3 - "output", // -4 - "inout", // -5 - "wire", // -6 - "assign" // -7 -}; - -// the list of gates in the Cadence library -static char * s_CadenceGates[40][5] = -{ - { "INVX1", "1", "1", "0 1\n", NULL }, // 0 - { "INVX2", "1", "1", "0 1\n", NULL }, // 1 - { "INVX4", "1", "1", "0 1\n", NULL }, // 2 - { "INVX8", "1", "1", "0 1\n", NULL }, // 3 - { "BUFX1", "1", "1", "1 1\n", NULL }, // 4 - { "BUFX3", "1", "1", "1 1\n", NULL }, // 5 - { "NOR2X1", "2", "1", "00 1\n", NULL }, // 6 - { "NOR3X1", "3", "1", "000 1\n", NULL }, // 7 - { "NOR4X1", "4", "1", "0000 1\n", NULL }, // 8 - { "NAND2X1", "2", "1", "11 0\n", NULL }, // 9 - { "NAND2X2", "2", "1", "11 0\n", NULL }, // 10 - { "NAND3X1", "3", "1", "111 0\n", NULL }, // 11 - { "NAND4X1", "4", "1", "1111 0\n", NULL }, // 12 - { "OR2X1", "2", "1", "00 0\n", NULL }, // 13 - { "OR4X1", "4", "1", "0000 0\n", NULL }, // 14 - { "AND2X1", "2", "1", "11 1\n", NULL }, // 15 - { "XOR2X1", "2", "1", "01 1\n10 1\n", NULL }, // 16 - { "MX2X1", "3", "1", "01- 1\n1-1 1\n", NULL }, // 17 - { "OAI21X1", "3", "1", "00- 1\n--0 1\n", NULL }, // 18 - { "OAI22X1", "4", "1", "00-- 1\n--00 1\n", NULL }, // 19 - { "OAI33X1", "6", "1", "000--- 1\n---000 1\n", NULL }, // 20 - { "AOI21X1", "3", "1", "11- 0\n--1 0\n", NULL }, // 21 - { "AOI22X1", "4", "1", "11-- 0\n--11 0\n", NULL }, // 22 - { "CLKBUFX1", "1", "1", "1 1\n", NULL }, // 23 - { "CLKBUFX2", "1", "1", "1 1\n", NULL }, // 24 - { "CLKBUFX3", "1", "1", "1 1\n", NULL }, // 25 - { "ADDHX1", "2", "2", "11 1\n", "01 1\n10 1\n" }, // 26 - { "ADDFX1", "3", "2", "11- 1\n-11 1\n1-1 1\n", "001 1\n010 1\n100 1\n111 1\n" }, // 27 - { "DFFSRX1", "1", "1", NULL, NULL }, // 28 - { "DFFX1", "1", "1", NULL, NULL }, // 29 - { "SDFFSRX1", "1", "1", NULL, NULL }, // 30 - { "TLATSRX1", "1", "1", NULL, NULL }, // 31 - { "TLATX1", "1", "1", NULL, NULL }, // 32 - { "TBUFX1", "1", "1", NULL, NULL }, // 33 - { "TBUFX2", "1", "1", NULL, NULL }, // 34 - { "TBUFX4", "1", "1", NULL, NULL }, // 35 - { "TBUFX8", "1", "1", NULL, NULL }, // 36 - { "TINVX1", "1", "1", NULL, NULL } // 37 -}; - -static Io_ReadVer_t * Io_ReadVerFile( char * pFileName ); -static Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p ); -static bool Io_ReadVerNetworkAssign( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens ); -static bool Io_ReadVerNetworkSignal( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ); -static bool Io_ReadVerNetworkGateSimple( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ); -static bool Io_ReadVerNetworkGateComplex( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ); -static bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens ); -static void Io_ReadVerPrintErrorMessage( Io_ReadVer_t * p ); -static void Io_ReadVerFree( Io_ReadVer_t * p ); +extern Abc_Lib_t * Ver_ParseFile( char * pFileName, Abc_Lib_t * pGateLib, int fCheck, int fUseMemMan ); //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// @@ -124,44 +32,7 @@ static void Io_ReadVerFree( Io_ReadVer_t * p ); /**Function************************************************************* - Synopsis [Reads the network from a Verilog file.] - - Description [Works only for IWLS 2005 benchmarks.] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) -{ - Io_ReadVer_t * p; - Abc_Ntk_t * pNtk; - - // start the file - p = Io_ReadVerFile( pFileName ); - if ( p == NULL ) - return NULL; - - // read the network - pNtk = Io_ReadVerNetwork( p ); - Io_ReadVerFree( p ); - if ( pNtk == NULL ) - return NULL; - - // make sure that everything is okay with the network structure - if ( fCheck && !Abc_NtkCheckRead( pNtk ) ) - { - printf( "Io_ReadVerilog: The network check has failed.\n" ); - Abc_NtkDelete( pNtk ); - return NULL; - } - return pNtk; -} - -/**Function************************************************************* - - Synopsis [Starts the reading data structure.] + Synopsis [Reads hierarchical design from the Verilog file.] Description [] @@ -170,583 +41,32 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) SeeAlso [] ***********************************************************************/ -Io_ReadVer_t * Io_ReadVerFile( char * pFileName ) -{ - Extra_FileReader_t * pReader; - Io_ReadVer_t * p; - int i; - - // start the reader - pReader = Extra_FileReaderAlloc( pFileName, "/", ";", " \t\r\n,()" ); - if ( pReader == NULL ) - return NULL; - - // start the reading data structure - p = ALLOC( Io_ReadVer_t, 1 ); - memset( p, 0, sizeof(Io_ReadVer_t) ); - p->pFileName = pFileName; - p->pReader = pReader; - p->Output = stdout; - p->vSkipped = Vec_PtrAlloc( 100 ); - - // insert the keywords and gate names into the hash table - p->tKeywords = st_init_table(strcmp, st_strhash); - for ( i = 0; i < 10; i++ ) - if ( s_Keywords[i] ) - st_insert( p->tKeywords, (char *)s_Keywords[i], (char *)-i ); - for ( i = 0; i < 40; i++ ) - if ( s_CadenceGates[i][0] ) - st_insert( p->tKeywords, (char *)s_CadenceGates[i][0], (char *)i ); - return p; -} - -/**Function************************************************************* - - Synopsis [Frees the data structure.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_ReadVerFree( Io_ReadVer_t * p ) -{ - Extra_FileReaderFree( p->pReader ); - Vec_PtrFree( p->vSkipped ); - st_free_table( p->tKeywords ); - FREE( p ); -} - -/**Function************************************************************* - - Synopsis [Prints the error message including the file name and line number.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_ReadVerPrintErrorMessage( Io_ReadVer_t * p ) -{ - if ( p->LineCur == 0 ) // the line number is not given - fprintf( p->Output, "%s: %s\n", p->pFileName, p->sError ); - else // print the error message with the line number - fprintf( p->Output, "%s (line %d): %s\n", p->pFileName, p->LineCur, p->sError ); -} - -/**Function************************************************************* - - Synopsis [Reads the verilog file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -Abc_Ntk_t * Io_ReadVerNetwork( Io_ReadVer_t * p ) +Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck ) { - char Buffer[1000]; - ProgressBar * pProgress; - Ver_KeywordType_t LineType; - Vec_Ptr_t * vTokens; Abc_Ntk_t * pNtk; - char * pModelName; - int i; + Abc_Lib_t * pDesign; - // read the model name - vTokens = Extra_FileReaderGetTokens( p->pReader ); - if ( vTokens == NULL || strcmp( vTokens->pArray[0], "module" ) ) - { - p->LineCur = 0; - sprintf( p->sError, "Wrong input file format." ); - Io_ReadVerPrintErrorMessage( p ); + // parse the verilog file + pDesign = Ver_ParseFile( pFileName, NULL, 1, fCheck ); + if ( pDesign == NULL ) return NULL; - } - pModelName = vTokens->pArray[1]; - // allocate the empty network - pNtk = Abc_NtkAlloc( ABC_NTK_NETLIST, ABC_FUNC_SOP, 1 ); - pNtk->pName = Extra_UtilStrsav( pModelName ); - pNtk->pSpec = Extra_UtilStrsav( p->pFileName ); + // extract the master network + pNtk = Vec_PtrEntryLast( pDesign->vModules ); + pNtk->pDesign = pDesign; + pDesign->pManFunc = NULL; - // create constant nodes and nets - Abc_NtkFindOrCreateNet( pNtk, "1'b0" ); - Abc_NtkFindOrCreateNet( pNtk, "1'b1" ); - Io_ReadCreateConst( pNtk, "1'b0", 0 ); - Io_ReadCreateConst( pNtk, "1'b1", 1 ); - - // read the inputs/outputs - pProgress = Extra_ProgressBarStart( stdout, Extra_FileReaderGetFileSize(p->pReader) ); - for ( i = 0; vTokens = Extra_FileReaderGetTokens(p->pReader); i++ ) + // verify the design for cyclic dependence + assert( Vec_PtrSize(pDesign->vModules) > 0 ); + if ( Vec_PtrSize(pDesign->vModules) == 1 ) { - Extra_ProgressBarUpdate( pProgress, Extra_FileReaderGetCurPosition(p->pReader), NULL ); - - // get the line type - if ( !st_lookup( p->tKeywords, vTokens->pArray[0], (char **)&LineType ) ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "The first token \"%s\" cannot be recognized.", vTokens->pArray[0] ); - Io_ReadVerPrintErrorMessage( p ); - return NULL; - } - // consider Verilog directives - if ( LineType < 0 ) - { - if ( LineType == VER_ENDMODULE ) - break; - if ( LineType == VER_ASSIGN ) - { - if ( !Io_ReadVerNetworkAssign( p, pNtk, vTokens ) ) - return NULL; - continue; - } - if ( !Io_ReadVerNetworkSignal( p, pNtk, vTokens, LineType ) ) - return NULL; - continue; - } - // proces single output gates - if ( LineType < 26 ) - { - if ( !Io_ReadVerNetworkGateSimple( p, pNtk, vTokens, LineType ) ) - return NULL; - continue; - } - // process complex gates - if ( LineType < 28 ) - { - if ( !Io_ReadVerNetworkGateComplex( p, pNtk, vTokens, LineType ) ) - return NULL; - continue; - - } - // process the latches - if ( LineType < 33 ) - { - if ( !Io_ReadVerNetworkLatch( p, pNtk, vTokens ) ) - return NULL; - continue; - } - // add the tri-state element to the skipped ones - sprintf( Buffer, "%s %s", vTokens->pArray[0], vTokens->pArray[1] ); - Vec_PtrPush( p->vSkipped, Extra_UtilStrsav(Buffer) ); - } - Extra_ProgressBarStop( pProgress ); - - if ( p->vSkipped->nSize > 0 ) - { - printf( "IoReadVerilog() skipped %d tri-state elements:\n", p->vSkipped->nSize ); - for ( i = 0; i < p->vSkipped->nSize; i++ ) - { - if ( i < 2 ) - printf( "%s,\n", p->vSkipped->pArray[i] ); - else - { - printf( "%s, etc.\n", p->vSkipped->pArray[i] ); - break; - } - } - for ( i = 0; i < p->vSkipped->nSize; i++ ) - free( p->vSkipped->pArray[i] ); - } - Abc_NtkFinalizeRead( pNtk ); - return pNtk; -} - -/**Function************************************************************* - - Synopsis [Reads one assign directive in the verilog file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -bool Io_ReadVerNetworkAssign( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens ) -{ - assert( strcmp( vTokens->pArray[0], "assign" ) == 0 ); - // make sure the driving variable exists - if ( !Abc_NtkFindNet( pNtk, vTokens->pArray[3] ) ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find net \"%s\". The assign operator is handled only for assignment to a variable and a constant.", vTokens->pArray[3] ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - // make sure the driven variable exists - if ( !Abc_NtkFindNet( pNtk, vTokens->pArray[1] ) ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find net \"%s\".", vTokens->pArray[1] ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - // create a buffer - Io_ReadCreateBuf( pNtk, vTokens->pArray[3], vTokens->pArray[1] ); - return 1; -} - -/**Function************************************************************* - - Synopsis [Reads one signal the verilog file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -bool Io_ReadVerNetworkSignal( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ) -{ - Abc_Obj_t * pNet; - char Buffer[1000]; - char * pToken; - int nSignals, k, Start, s; - - nSignals = 0; - pToken = vTokens->pArray[1]; - if ( pToken[0] == '[' ) - { - nSignals = atoi(pToken + 1) + 1; - if ( nSignals < 1 || nSignals > 1024 ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Incorrect number of signals in the expression \"%s\".", pToken ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - if ( nSignals == 1 ) - nSignals = 0; - Start = 2; + printf( "Warning: The design is not hierarchical.\n" ); + Abc_LibFree( pDesign, pNtk ); + pNtk->pDesign = NULL; } else - Start = 1; - for ( k = Start; k < vTokens->nSize; k++ ) - { - pToken = vTokens->pArray[k]; - // print the signal name - if ( nSignals ) - { - for ( s = 0; s < nSignals; s++ ) - { - sprintf( Buffer, "%s[%d]", pToken, s ); - if ( LineType == VER_INPUT || LineType == VER_INOUT ) - Io_ReadCreatePi( pNtk, Buffer ); - if ( LineType == VER_OUTPUT || LineType == VER_INOUT ) - Io_ReadCreatePo( pNtk, Buffer ); - if ( LineType != VER_INPUT && LineType != VER_OUTPUT && LineType != VER_INOUT ) - pNet = Abc_NtkFindOrCreateNet( pNtk, Buffer ); - } - } - else - { - if ( LineType == VER_INPUT || LineType == VER_INOUT ) - Io_ReadCreatePi( pNtk, pToken ); - if ( LineType == VER_OUTPUT || LineType == VER_INOUT ) - Io_ReadCreatePo( pNtk, pToken ); - if ( LineType != VER_INPUT && LineType != VER_OUTPUT && LineType != VER_INOUT ) - pNet = Abc_NtkFindOrCreateNet( pNtk, pToken ); - } - } - return 1; -} - -/**Function************************************************************* - - Synopsis [Reads a simple gate from the verilog file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -bool Io_ReadVerNetworkGateSimple( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ) -{ - Abc_Obj_t * pNet, * pNode; - char * pToken; - int nFanins, k; - - // create the node - pNode = Abc_NtkCreateNode( pNtk ); - // add the fanin nets - nFanins = s_CadenceGates[LineType][1][0] - '0'; - // skip the gate type and gate name - for ( k = 2; k < vTokens->nSize - 1; k++ ) - { - pToken = vTokens->pArray[k]; - if ( pToken[0] == '.' ) - continue; - pNet = Abc_NtkFindNet( pNtk, pToken ); - if ( pNet ) - { - Abc_ObjAddFanin( pNode, pNet ); - continue; - } - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find net \"%s\".", pToken ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - if ( Abc_ObjFaninNum(pNode) != nFanins ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Gate \"%s\" has a wrong number of inputs.", vTokens->pArray[1] ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - - // add the fanout net - pToken = vTokens->pArray[vTokens->nSize - 1]; - if ( pToken[0] == '.' ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Gate \"%s\" does not have a fanout.", vTokens->pArray[1] ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - pNet = Abc_NtkFindNet( pNtk, pToken ); - if ( pNet == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find net \"%s\".", pToken ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - Abc_ObjAddFanin( pNet, pNode ); - // set the function - Abc_ObjSetData( pNode, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) ); - return 1; -} - -/**Function************************************************************* - - Synopsis [Reads a complex gate from the verilog file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -bool Io_ReadVerNetworkGateComplex( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens, int LineType ) -{ - Abc_Obj_t * pNode1, * pNode2, * pNet; - char * pToken, * pToken1, * pToken2; - int nFanins, k; - - // create the nodes - pNode1 = Abc_NtkCreateNode( pNtk ); - pNode2 = Abc_NtkCreateNode( pNtk ); - // skip the gate type and gate name - // add the fanin nets - nFanins = s_CadenceGates[LineType][1][0] - '0'; - for ( k = 2; k < vTokens->nSize; k++ ) - { - pToken = vTokens->pArray[k]; - if ( pToken[0] == '.' ) - continue; - pNet = Abc_NtkFindNet( pNtk, pToken ); - if ( pNet == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find net \"%s\".", pToken ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - Abc_ObjAddFanin( pNode1, pNet ); - Abc_ObjAddFanin( pNode2, pNet ); - if ( Abc_ObjFaninNum(pNode1) == nFanins ) - { - k++; - break; - } - } - // find the tokens corresponding to the output - pToken1 = pToken2 = NULL; - for ( ; k < vTokens->nSize; k++ ) - { - pToken = vTokens->pArray[k]; - if ( pToken[0] == '.' ) - continue; - if ( pToken1 == NULL ) - pToken1 = pToken; - else - pToken2 = pToken; - } - // quit if one of the tokens is not given - if ( pToken1 == NULL || pToken2 == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "An output of a two-output gate \"%s\" is not specified.", vTokens->pArray[1] ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - - // add the fanout net - pNet = Abc_NtkFindNet( pNtk, pToken1 ); - if ( pNet == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find net \"%s\".", pToken1 ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - Abc_ObjAddFanin( pNet, pNode1 ); - - // add the fanout net - pNet = Abc_NtkFindNet( pNtk, pToken2 ); - if ( pNet == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find net \"%s\".", pToken2 ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - Abc_ObjAddFanin( pNet, pNode2 ); - Abc_ObjSetData( pNode1, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][3]) ); - Abc_ObjSetData( pNode2, Abc_SopRegister(pNtk->pManFunc, s_CadenceGates[LineType][4]) ); - return 1; -} - -/**Function************************************************************* - - Synopsis [Reads a latch from the verilog file.] - - Description [This procedure treats T-latch as if it were D-latch.] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -bool Io_ReadVerNetworkLatch( Io_ReadVer_t * p, Abc_Ntk_t * pNtk, Vec_Ptr_t * vTokens ) -{ - Abc_Obj_t * pLatch, * pNet; - char * pLatchName; - char * pToken, * pToken2, * pTokenRN, * pTokenSN, * pTokenSI, * pTokenSE, * pTokenD, * pTokenQ, * pTokenQN; - int k, fRN1, fSN1; - - // get the latch name - pLatchName = vTokens->pArray[1]; - - // collect the FF signals - pTokenRN = pTokenSN = pTokenSI = pTokenSE = pTokenD = pTokenQ = pTokenQN = NULL; - for ( k = 2; k < vTokens->nSize-1; k++ ) - { - pToken = vTokens->pArray[k]; - pToken2 = vTokens->pArray[k+1]; - if ( pToken[1] == 'R' && pToken[2] == 'N' && pToken[3] == 0 ) - pTokenRN = (pToken2[0] == '.')? NULL : pToken2; - else if ( pToken[1] == 'S' && pToken[2] == 'N' && pToken[3] == 0 ) - pTokenSN = (pToken2[0] == '.')? NULL : pToken2; - else if ( pToken[1] == 'S' && pToken[2] == 'I' && pToken[3] == 0 ) - pTokenSI = (pToken2[0] == '.')? NULL : pToken2; - else if ( pToken[1] == 'S' && pToken[2] == 'E' && pToken[3] == 0 ) - pTokenSE = (pToken2[0] == '.')? NULL : pToken2; - else if ( pToken[1] == 'D' && pToken[2] == 0 ) - pTokenD = (pToken2[0] == '.')? NULL : pToken2; - else if ( pToken[1] == 'Q' && pToken[2] == 0 ) - pTokenQ = (pToken2[0] == '.')? NULL : pToken2; - else if ( pToken[1] == 'Q' && pToken[2] == 'N' && pToken[3] == 0 ) - pTokenQN = (pToken2[0] == '.')? NULL : pToken2; - else if ( pToken[1] == 'C' && pToken[2] == 'K' && pToken[3] == 0 ) {} - else - assert( 0 ); - if ( pToken2[0] != '.' ) - k++; - } - - if ( pTokenD == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 1 ); - sprintf( p->sError, "Cannot read pin D of the latch \"%s\".", pLatchName ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - if ( pTokenQ == NULL && pTokenQN == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 1 ); - sprintf( p->sError, "Cannot read pins Q/QN of the latch \"%s\".", pLatchName ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - if ( (pTokenRN == NULL) ^ (pTokenSN == NULL) ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 1 ); - sprintf( p->sError, "Cannot read pins RN/SN of the latch \"%s\".", pLatchName ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - if ( Abc_NtkFindNet( pNtk, pTokenD ) == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find latch input net \"%s\".", pTokenD ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - - // create the latch - pLatch = Io_ReadCreateLatch( pNtk, pTokenD, pLatchName ); - - // create the buffer if Q signal is available - if ( pTokenQ ) - { - pNet = Abc_NtkFindNet( pNtk, pTokenQ ); - if ( pNet == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find latch output net \"%s\".", pTokenQ ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - Io_ReadCreateBuf( pNtk, pLatchName, pTokenQ ); - } - if ( pTokenQN ) - { - pNet = Abc_NtkFindNet( pNtk, pTokenQN ); - if ( pNet == NULL ) - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot find latch output net \"%s\".", pTokenQN ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - Io_ReadCreateInv( pNtk, pLatchName, pTokenQN ); - } - - // set the initial value - if ( pTokenRN == NULL && pTokenSN == NULL ) - Abc_LatchSetInitDc( pLatch ); - else - { - fRN1 = (strcmp( pTokenRN, "1'b1" ) == 0); - fSN1 = (strcmp( pTokenSN, "1'b1" ) == 0); - if ( fRN1 && fSN1 ) - Abc_LatchSetInitDc( pLatch ); - else if ( fRN1 ) - Abc_LatchSetInit1( pLatch ); - else if ( fSN1 ) - Abc_LatchSetInit0( pLatch ); - else - { - p->LineCur = Extra_FileReaderGetLineNumber( p->pReader, 0 ); - sprintf( p->sError, "Cannot read the initial value of latch \"%s\".", pLatchName ); - Io_ReadVerPrintErrorMessage( p ); - return 0; - } - } - return 1; + Abc_NtkIsAcyclicHierarchy( pNtk ); + return pNtk; } //////////////////////////////////////////////////////////////////////// diff --git a/src/base/io/ioUtil.c b/src/base/io/ioUtil.c index ca9f06b4..7b4c7c76 100644 --- a/src/base/io/ioUtil.c +++ b/src/base/io/ioUtil.c @@ -132,6 +132,8 @@ Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck pNtk = Io_ReadEqn( pFileName, fCheck ); else if ( FileType == IO_FILE_PLA ) pNtk = Io_ReadPla( pFileName, fCheck ); + else if ( FileType == IO_FILE_VERILOG ) + pNtk = Io_ReadVerilog( pFileName, fCheck ); else { fprintf( stderr, "Unknown file format.\n" ); @@ -142,6 +144,12 @@ Abc_Ntk_t * Io_ReadNetlist( char * pFileName, Io_FileType_t FileType, int fCheck fprintf( stdout, "Reading network from file has failed.\n" ); return NULL; } + if ( Abc_NtkBlackboxNum(pNtk) || Abc_NtkBlackboxNum(pNtk) ) + { + fprintf( stdout, "The network contains hierarchy. Use \"read_hie\".\n" ); + Abc_NtkDelete( pNtk ); + return NULL; + } return pNtk; } @@ -197,6 +205,8 @@ Abc_Ntk_t * Io_ReadHie( char * pFileName, Io_FileType_t FileType, int fCheck ) pNtk = Io_ReadBlifMv( pFileName, 0, fCheck ); // else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV ) // pNtk = Io_ReadBlifMv( pFileName, 1, fCheck ); + else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG ) + pNtk = Io_ReadVerilog( pFileName, fCheck ); else { printf( "Wrong file type.\n" ); @@ -220,7 +230,7 @@ Abc_Ntk_t * Io_ReadHie( char * pFileName, Io_FileType_t FileType, int fCheck ) // convert blackboxes if ( Abc_NtkBlackboxNum(pNtk) > 0 ) { - printf( "Hierarchical parser is converting %d blackboxes.\n", Abc_NtkBlackboxNum(pNtk) ); + printf( "Hierarchical parser converted %d blackboxes.\n", Abc_NtkBlackboxNum(pNtk) ); pNtk = Abc_NtkConvertBlackboxes( pTemp = pNtk ); Abc_NtkDelete( pTemp ); if ( pNtk == NULL ) @@ -347,7 +357,7 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ) { if ( Abc_NtkIsSopNetlist(pNtkTemp) ) Abc_NtkSopToAig( pNtkTemp ); - Io_WriteVerilog( pNtkTemp, pFileName, 1 ); + Io_WriteVerilog( pNtkTemp, pFileName ); } else fprintf( stderr, "Unknown file format.\n" ); @@ -365,50 +375,64 @@ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ) SeeAlso [] ***********************************************************************/ -void Io_WriteHie( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType, char * pBaseName ) +void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName ) { - Abc_Ntk_t * pNtkTemp, * pNtkBase, * pNtkResult; + Abc_Ntk_t * pNtkTemp, * pNtkResult, * pNtkBase = NULL; // check if the current network is available if ( pNtk == NULL ) { fprintf( stdout, "Empty network.\n" ); return; } - // check if the file extension if given - if ( FileType == IO_FILE_NONE || FileType == IO_FILE_UNKNOWN ) - { - fprintf( stdout, "The generic file writer requires a known file extension.\n" ); + + // read the base network + assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) ); + if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIF ) + pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 ); + else + fprintf( stderr, "Unknown input file format.\n" ); + if ( pNtkBase == NULL ) return; - } - // write the AIG formats - if ( FileType == IO_FILE_BLIF ) + + if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 ) { - pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 ); - if ( Abc_NtkWhiteboxNum(pNtk) > 0 ) - { - pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase ); - Abc_NtkDelete( pNtkTemp ); - } - if ( Abc_NtkBlackboxNum(pNtk) > 0 ) - { - pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 ); - pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult ); - Abc_NtkDelete( pNtkTemp ); - printf( "Hierarchy writer reintroduced %d blackboxes.\n", Abc_NtkBlackboxNum(pNtk) ); - } - else - { - printf( "Warning: The output network does not contain blackboxes.\n" ); - pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 ); - } - Abc_NtkDelete( pNtkBase ); - if ( pNtkResult == NULL ) + pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase ); + if ( pNtkBase == NULL ) return; - Io_WriteBlif( pNtkResult, pFileName, 0 ); - Abc_NtkDelete( pNtkResult ); + Abc_NtkDelete( pNtkTemp ); + } + + // reintroduce the boxes into the netlist + if ( Abc_NtkBlackboxNum(pNtkBase) > 0 ) + { + pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 ); + pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult ); + Abc_NtkDelete( pNtkTemp ); + if ( pNtkResult ) + printf( "Hierarchy writer reintroduced %d blackboxes.\n", Abc_NtkBlackboxNum(pNtkBase) ); + } + else + { + printf( "Warning: The output network does not contain blackboxes.\n" ); + pNtkResult = Abc_NtkLogicToNetlist( pNtk, 0 ); + } + Abc_NtkDelete( pNtkBase ); + if ( pNtkResult == NULL ) + return; + + // write the resulting network + if ( Io_ReadFileType(pFileName) == IO_FILE_BLIF ) + Io_WriteBlif( pNtkResult, pFileName, 1 ); + else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG ) + { + if ( Abc_NtkIsSopNetlist(pNtkResult) ) + Abc_NtkSopToAig( pNtkResult ); + Io_WriteVerilog( pNtkResult, pFileName ); } else - fprintf( stderr, "Unknown file format.\n" ); + fprintf( stderr, "Unknown output file format.\n" ); + + Abc_NtkDelete( pNtkResult ); } /**Function************************************************************* diff --git a/src/base/io/ioWriteBlif.c b/src/base/io/ioWriteBlif.c index 7c9db8bb..94580e33 100644 --- a/src/base/io/ioWriteBlif.c +++ b/src/base/io/ioWriteBlif.c @@ -102,6 +102,7 @@ void Io_WriteBlif( Abc_Ntk_t * pNtk, char * FileName, int fWriteLatches ) { pNtkTemp = pObj->pData; assert( pNtkTemp != NULL && Abc_NtkHasBlackbox(pNtkTemp) ); + fprintf( pFile, "\n\n", Abc_NtkName(pNtk) ); Io_NtkWrite( pFile, pNtkTemp, fWriteLatches ); } } diff --git a/src/base/io/ioWriteVerAux.c b/src/base/io/ioWriteVerAux.c deleted file mode 100644 index 9fd71750..00000000 --- a/src/base/io/ioWriteVerAux.c +++ /dev/null @@ -1,444 +0,0 @@ -/**CFile**************************************************************** - - FileName [ioWriteVerilog.c] - - SystemName [ABC: Logic synthesis and verification system.] - - PackageName [Command processing package.] - - Synopsis [Procedures to output a special subset of Verilog.] - - Author [Alan Mishchenko] - - Affiliation [UC Berkeley] - - Date [Ver. 1.0. Started - June 20, 2005.] - - Revision [$Id: ioWriteVerilog.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $] - -***********************************************************************/ - -#include "io.h" - -//////////////////////////////////////////////////////////////////////// -/// DECLARATIONS /// -//////////////////////////////////////////////////////////////////////// - -static void Io_WriteVerilogAuxInt( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_WriteVerilogAuxPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start ); -static void Io_WriteVerilogAuxPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start ); -static void Io_WriteVerilogAuxWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ); -static void Io_WriteVerilogAuxNodes( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_WriteVerilogAuxArgs( FILE * pFile, Abc_Obj_t * pObj, int nInMax, int fPadZeros ); -static int Io_WriteVerilogAuxCheckNtk( Abc_Ntk_t * pNtk ); -static char * Io_WriteVerilogAuxGetName( Abc_Obj_t * pObj ); - -//////////////////////////////////////////////////////////////////////// -/// FUNCTION DEFINITIONS /// -//////////////////////////////////////////////////////////////////////// - -/**Function************************************************************* - - Synopsis [Write verilog.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogAux( Abc_Ntk_t * pNtk, char * pFileName ) -{ - FILE * pFile; - - if ( !Abc_NtkIsSopNetlist(pNtk) || !Io_WriteVerilogAuxCheckNtk(pNtk) ) - { - printf( "Io_WriteVerilogAux(): Can write Verilog for a very special subset of logic networks.\n" ); - printf( "The current network is not in the subset; writing Verilog is not performed.\n" ); - return; - } - - if ( Abc_NtkLatchNum(pNtk) > 0 ) - printf( "Io_WriteVerilogAux(): Warning: only combinational portion is being written.\n" ); - - // start the output stream - pFile = fopen( pFileName, "w" ); - if ( pFile == NULL ) - { - fprintf( stdout, "Io_WriteVerilogAux(): Cannot open the output file \"%s\".\n", pFileName ); - return; - } - - // write the equations for the network - Io_WriteVerilogAuxInt( pFile, pNtk ); - fprintf( pFile, "\n" ); - fclose( pFile ); -} - -/**Function************************************************************* - - Synopsis [Writes verilog.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogAuxInt( FILE * pFile, Abc_Ntk_t * pNtk ) -{ - // write inputs and outputs - fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() ); - fprintf( pFile, "module %s (\n ", Abc_NtkName(pNtk) ); - Io_WriteVerilogAuxPis( pFile, pNtk, 3 ); - fprintf( pFile, ",\n " ); - Io_WriteVerilogAuxPos( pFile, pNtk, 3 ); - fprintf( pFile, " );\n" ); - // write inputs, outputs and wires - fprintf( pFile, " input" ); - Io_WriteVerilogAuxPis( pFile, pNtk, 5 ); - fprintf( pFile, ";\n" ); - fprintf( pFile, " output" ); - Io_WriteVerilogAuxPos( pFile, pNtk, 5 ); - fprintf( pFile, ";\n" ); - fprintf( pFile, " wire" ); - Io_WriteVerilogAuxWires( pFile, pNtk, 4 ); - fprintf( pFile, ";\n" ); - // write the nodes - Io_WriteVerilogAuxNodes( pFile, pNtk ); - // finalize the file - fprintf( pFile, "endmodule\n\n" ); - fclose( pFile ); -} - -/**Function************************************************************* - - Synopsis [Writes the primary inputs.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogAuxPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) -{ - Abc_Obj_t * pTerm, * pNet; - int LineLength; - int AddedLength; - int NameCounter; - int i; - - LineLength = Start; - NameCounter = 0; - Abc_NtkForEachCi( pNtk, pTerm, i ) - { - pNet = Abc_ObjFanout0(pTerm); - // get the line length after this name is written - AddedLength = strlen(Abc_ObjName(pNet)) + 2; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, "\n " ); - // reset the line length - LineLength = 3; - NameCounter = 0; - } - fprintf( pFile, " %s%s", Abc_ObjName(pNet), (i==Abc_NtkCiNum(pNtk)-1)? "" : "," ); - LineLength += AddedLength; - NameCounter++; - } -} - -/**Function************************************************************* - - Synopsis [Writes the primary outputs.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogAuxPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) -{ - Abc_Obj_t * pTerm, * pNet; - int LineLength; - int AddedLength; - int NameCounter; - int i; - - LineLength = Start; - NameCounter = 0; - Abc_NtkForEachCo( pNtk, pTerm, i ) - { - pNet = Abc_ObjFanin0(pTerm); - // get the line length after this name is written - AddedLength = strlen(Abc_ObjName(pNet)) + 2; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, "\n " ); - // reset the line length - LineLength = 3; - NameCounter = 0; - } - fprintf( pFile, " %s%s", Abc_ObjName(pNet), (i==Abc_NtkCoNum(pNtk)-1)? "" : "," ); - LineLength += AddedLength; - NameCounter++; - } -} - -/**Function************************************************************* - - Synopsis [Writes the wires.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogAuxWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) -{ - Abc_Obj_t * pTerm, * pNet; - int LineLength; - int AddedLength; - int NameCounter; - int i, Counter, nNodes; - - // count the number of wires - nNodes = 0; - Abc_NtkForEachNode( pNtk, pTerm, i ) - { - if ( i == 0 ) - continue; - pNet = Abc_ObjFanout0(pTerm); - if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) - continue; - nNodes++; - } - - // write the wires - Counter = 0; - LineLength = Start; - NameCounter = 0; - Abc_NtkForEachNode( pNtk, pTerm, i ) - { - if ( i == 0 ) - continue; - pNet = Abc_ObjFanout0(pTerm); - if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) - continue; - Counter++; - // get the line length after this name is written - AddedLength = strlen(Abc_ObjName(pNet)) + 2; - if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) - { // write the line extender - fprintf( pFile, "\n " ); - // reset the line length - LineLength = 3; - NameCounter = 0; - } - fprintf( pFile, " %s%s", Io_WriteVerilogAuxGetName(pNet), (Counter==nNodes)? "" : "," ); - LineLength += AddedLength; - NameCounter++; - } -} - -/**Function************************************************************* - - Synopsis [Writes the wires.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogAuxNodes( FILE * pFile, Abc_Ntk_t * pNtk ) -{ - Abc_Obj_t * pObj; - int i, nCubes, nFanins, Counter, nDigits, fPadZeros; - char * pName; - - nDigits = Extra_Base10Log( Abc_NtkNodeNum(pNtk) ); - Counter = 1; - Abc_NtkForEachNode( pNtk, pObj, i ) - { - nFanins = Abc_ObjFaninNum(pObj); - nCubes = Abc_SopGetCubeNum(pObj->pData); - if ( Abc_SopIsAndType(pObj->pData) ) - pName = "ts_and", fPadZeros = 1; - else if ( Abc_SopIsExorType(pObj->pData) ) - pName = "ts_xor", fPadZeros = 1; - else // if ( Abc_SopIsOrType(pObj->pData) ) - pName = "ts_or", fPadZeros = 0; - - assert( nCubes < 2 ); - if ( nCubes == 0 ) - { - fprintf( pFile, " ts_gnd g%0*d ", nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 0, fPadZeros ); - } - else if ( nCubes == 1 && nFanins == 0 ) - { - fprintf( pFile, " ts_vdd g%0*d ", nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 0, fPadZeros ); - } - else if ( nFanins == 1 && Abc_SopIsInv(pObj->pData) ) - { - fprintf( pFile, " ts_inv g%0*d ", nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 1, fPadZeros ); - } - else if ( nFanins == 1 ) - { - fprintf( pFile, " ts_buf g%0*d ", nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 1, fPadZeros ); - } - else if ( nFanins <= 4 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 4, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 4, fPadZeros ); - } - else if ( nFanins <= 6 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 6, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 6, fPadZeros ); - } - else if ( nFanins == 7 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 7, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 7, fPadZeros ); - } - else if ( nFanins == 8 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 8, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 8, fPadZeros ); - } - else if ( nFanins <= 16 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 16, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 16, fPadZeros ); - } - else if ( nFanins <= 32 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 32, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 32, fPadZeros ); - } - else if ( nFanins <= 64 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 64, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 64, fPadZeros ); - } - else if ( nFanins <= 128 ) - { - fprintf( pFile, " %s%d g%0*d ", pName, 128, nDigits, Counter++ ); - Io_WriteVerilogAuxArgs( pFile, pObj, 128, fPadZeros ); - } - } -} - -/**Function************************************************************* - - Synopsis [Writes the inputs.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogAuxArgs( FILE * pFile, Abc_Obj_t * pObj, int nInMax, int fPadZeros ) -{ - Abc_Obj_t * pFanin; - int i, Counter = 2; - fprintf( pFile, "(.z (%s)", Io_WriteVerilogAuxGetName(Abc_ObjFanout0(pObj)) ); - Abc_ObjForEachFanin( pObj, pFanin, i ) - { - if ( Counter++ % 4 == 0 ) - fprintf( pFile, "\n " ); - fprintf( pFile, " .i%d (%s)", i+1, Io_WriteVerilogAuxGetName(Abc_ObjFanin(pObj,i)) ); - } - for ( ; i < nInMax; i++ ) - { - if ( Counter++ % 4 == 0 ) - fprintf( pFile, "\n " ); - fprintf( pFile, " .i%d (%s)", i+1, fPadZeros? "1\'b0" : "1\'b1" ); - } - fprintf( pFile, ");\n" ); -} - -/**Function************************************************************* - - Synopsis [] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int Io_WriteVerilogAuxCheckNtk( Abc_Ntk_t * pNtk ) -{ - Abc_Obj_t * pObj; - char * pSop; - int i, k, nFanins; - Abc_NtkForEachNode( pNtk, pObj, i ) - { - if ( Abc_SopGetCubeNum(pObj->pData) > 1 ) - { - printf( "Node %s contains a cover with more than one cube.\n", Abc_ObjName(pObj) ); - return 0; - } - nFanins = Abc_ObjFaninNum(pObj); - if ( nFanins < 2 ) - continue; - pSop = pObj->pData; - for ( k = 0; k < nFanins; k++ ) - if ( pSop[k] != '1' ) - { - printf( "Node %s contains a cover with non-positive literals.\n", Abc_ObjName(pObj) ); - return 0; - } - } - return 1; -} - -/**Function************************************************************* - - Synopsis [Prepares the name for writing the Verilog file.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -char * Io_WriteVerilogAuxGetName( Abc_Obj_t * pObj ) -{ - static char Buffer[20]; - char * pName; - pName = Abc_ObjName(pObj); - if ( pName[0] != '[' ) - return pName; - // replace opening bracket by the escape sign and closing bracket by space - // as a result of this transformation, the length of the name does not change - strcpy( Buffer, pName ); - Buffer[0] = '\\'; - Buffer[strlen(Buffer)-1] = ' '; - return Buffer; -} - -//////////////////////////////////////////////////////////////////////// -/// END OF FILE /// -//////////////////////////////////////////////////////////////////////// - - diff --git a/src/base/io/ioWriteVer.c b/src/base/io/ioWriteVerilog.c index 20e10583..9524bdef 100644 --- a/src/base/io/ioWriteVer.c +++ b/src/base/io/ioWriteVerilog.c @@ -26,18 +26,15 @@ /// DECLARATIONS /// //////////////////////////////////////////////////////////////////////// -static void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk, int fVerLibStyle ); +static void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk ); static void Io_WriteVerilogPis( FILE * pFile, Abc_Ntk_t * pNtk, int Start ); static void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start ); static void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ); static void Io_WriteVerilogRegs( FILE * pFile, Abc_Ntk_t * pNtk, int Start ); -static void Io_WriteVerilogGates( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_WriteVerilogNodes( FILE * pFile, Abc_Ntk_t * pNtk ); static void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ); -static void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk ); -static int Io_WriteVerilogCheckNtk( Abc_Ntk_t * pNtk ); +static void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk ); +static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ); static char * Io_WriteVerilogGetName( Abc_Obj_t * pObj ); -static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ); //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// @@ -54,29 +51,17 @@ static int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ); SeeAlso [] ***********************************************************************/ -void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName, int fVerLibStyle ) +void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName ) { + Abc_Ntk_t * pNetlist; FILE * pFile; + int i; + // can only write nodes represented using local AIGs if ( !Abc_NtkIsAigNetlist(pNtk) ) { printf( "Io_WriteVerilog(): Can produce Verilog for AIG netlists only.\n" ); return; } - if ( Abc_NtkLatchNum(pNtk) > 0 ) - { - printf( "Io_WriteVerilog(): Currently cannot write verilog for sequential networks.\n" ); - return; - } - -/* - if ( !(Abc_NtkIsNetlist(pNtk) && (Abc_NtkHasMapping(pNtk) || Io_WriteVerilogCheckNtk(pNtk))) ) - { - printf( "Io_WriteVerilog(): Can produce Verilog for a subset of logic networks.\n" ); - printf( "The network should be either an AIG or a network after technology mapping.\n" ); - printf( "The current network is not in the subset; the output files is not written.\n" ); - return; - } -*/ // start the output stream pFile = fopen( pFileName, "w" ); if ( pFile == NULL ) @@ -87,52 +72,28 @@ void Io_WriteVerilog( Abc_Ntk_t * pNtk, char * pFileName, int fVerLibStyle ) // write the equations for the network fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() ); - Io_WriteVerilogInt( pFile, pNtk, fVerLibStyle ); fprintf( pFile, "\n" ); - fclose( pFile ); -} - -/**Function************************************************************* - - Synopsis [Write verilog.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogLibrary( Abc_Lib_t * pLibrary, char * pFileName ) -{ - FILE * pFile; - Abc_Ntk_t * pNtk, * pNetlist; - int i; - // start the output stream - pFile = fopen( pFileName, "w" ); - if ( pFile == NULL ) + // write modules + if ( pNtk->pDesign ) { - fprintf( stdout, "Io_WriteVerilogLibrary(): Cannot open the output file \"%s\".\n", pFileName ); - return; + Vec_PtrForEachEntry( pNtk->pDesign->vModules, pNetlist, i ) + { + assert( Abc_NtkIsNetlist(pNetlist) ); + if ( pNetlist == pNtk ) + continue; + Io_WriteVerilogInt( pFile, pNetlist ); + fprintf( pFile, "\n" ); + } + // write the network last + Io_WriteVerilogInt( pFile, pNtk ); } - - fprintf( pFile, "// Verilog library \"%s\" written by ABC on %s\n", pFileName, Extra_TimeStamp() ); - fprintf( pFile, "\n" ); - // write modules - Vec_PtrForEachEntry( pLibrary->vModules, pNtk, i ) + else { - // create netlist -// pNetlist = Abc_NtkLogicToNetlist( pNtk, 0 ); - assert( Abc_NtkIsNetlist(pNtk) ); - pNetlist = pNtk; - // write the equations for the network - Io_WriteVerilogInt( pFile, pNetlist, 1 ); - fprintf( pFile, "\n" ); - // delete the netlist -// Abc_NtkDelete( pNetlist ); + Io_WriteVerilogInt( pFile, pNtk ); } + fprintf( pFile, "\n" ); fclose( pFile ); } @@ -147,44 +108,54 @@ void Io_WriteVerilogLibrary( Abc_Lib_t * pLibrary, char * pFileName ) SeeAlso [] ***********************************************************************/ -void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk, int fVerLibStyle ) +void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk ) { // write inputs and outputs // fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) ); fprintf( pFile, "module %s ( \n ", Abc_NtkName(pNtk) ); - Io_WriteVerilogPis( pFile, pNtk, 3 ); - fprintf( pFile, ",\n " ); - Io_WriteVerilogPos( pFile, pNtk, 3 ); + if ( Abc_NtkPiNum(pNtk) > 0 ) + { + Io_WriteVerilogPis( pFile, pNtk, 3 ); + fprintf( pFile, ",\n " ); + } + if ( Abc_NtkPoNum(pNtk) > 0 ) + Io_WriteVerilogPos( pFile, pNtk, 3 ); fprintf( pFile, " );\n" ); // write inputs, outputs, registers, and wires -// fprintf( pFile, " input gclk," ); - fprintf( pFile, " input " ); - Io_WriteVerilogPis( pFile, pNtk, 10 ); - fprintf( pFile, ";\n" ); - fprintf( pFile, " output" ); - Io_WriteVerilogPos( pFile, pNtk, 5 ); - fprintf( pFile, ";\n" ); - if ( Abc_NtkLatchNum(pNtk) > 0 ) + if ( Abc_NtkPiNum(pNtk) > 0 ) { - fprintf( pFile, " reg" ); - Io_WriteVerilogRegs( pFile, pNtk, 4 ); - fprintf( pFile, ";\n" ); +// fprintf( pFile, " input gclk," ); + fprintf( pFile, " input " ); + Io_WriteVerilogPis( pFile, pNtk, 10 ); + fprintf( pFile, ";\n" ); } - if ( Io_WriteVerilogWiresCount(pNtk) > 0 ) + if ( Abc_NtkPoNum(pNtk) > 0 ) { - fprintf( pFile, " wire" ); - Io_WriteVerilogWires( pFile, pNtk, 4 ); - fprintf( pFile, ";\n" ); + fprintf( pFile, " output" ); + Io_WriteVerilogPos( pFile, pNtk, 5 ); + fprintf( pFile, ";\n" ); + } + // if this is not a blackbox, write internal signals + if ( !Abc_NtkHasBlackbox(pNtk) ) + { + if ( Abc_NtkLatchNum(pNtk) > 0 ) + { + fprintf( pFile, " reg" ); + Io_WriteVerilogRegs( pFile, pNtk, 4 ); + fprintf( pFile, ";\n" ); + } + if ( Io_WriteVerilogWiresCount(pNtk) > 0 ) + { + fprintf( pFile, " wire" ); + Io_WriteVerilogWires( pFile, pNtk, 4 ); + fprintf( pFile, ";\n" ); + } + // write nodes + Io_WriteVerilogObjects( pFile, pNtk ); + // write registers + if ( Abc_NtkLatchNum(pNtk) > 0 ) + Io_WriteVerilogLatches( pFile, pNtk ); } - // write nodes - if ( fVerLibStyle ) - Io_WriteVerilogVerLibStyle( pFile, pNtk ); - else if ( Abc_NtkHasMapping(pNtk) ) - Io_WriteVerilogGates( pFile, pNtk ); - else - Io_WriteVerilogNodes( pFile, pNtk ); - // write registers - Io_WriteVerilogLatches( pFile, pNtk ); // finalize the file fprintf( pFile, "endmodule\n\n" ); } @@ -269,34 +240,6 @@ void Io_WriteVerilogPos( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) /**Function************************************************************* - Synopsis [Counts the number of wires.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ) -{ - Abc_Obj_t * pTerm, * pNet; - int i, nNodes; - nNodes = Abc_NtkLatchNum(pNtk); - Abc_NtkForEachNode( pNtk, pTerm, i ) - { - if ( i == 0 ) - continue; - pNet = Abc_ObjFanout0(pTerm); - if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) - continue; - nNodes++; - } - return nNodes; -} - -/**Function************************************************************* - Synopsis [Writes the wires.] Description [] @@ -308,11 +251,11 @@ int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ) ***********************************************************************/ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) { - Abc_Obj_t * pTerm, * pNet; + Abc_Obj_t * pObj, * pNet, * pBox, * pTerm; int LineLength; int AddedLength; int NameCounter; - int i, Counter, nNodes; + int i, k, Counter, nNodes; // count the number of wires nNodes = Io_WriteVerilogWiresCount( pNtk ); @@ -321,12 +264,12 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) Counter = 0; LineLength = Start; NameCounter = 0; - Abc_NtkForEachNode( pNtk, pTerm, i ) + Abc_NtkForEachNode( pNtk, pObj, i ) { if ( i == 0 ) continue; - pNet = Abc_ObjFanout0(pTerm); - if ( Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) + pNet = Abc_ObjFanout0(pObj); + if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) continue; Counter++; // get the line length after this name is written @@ -342,9 +285,9 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) LineLength += AddedLength; NameCounter++; } - Abc_NtkForEachLatch( pNtk, pTerm, i ) + Abc_NtkForEachLatch( pNtk, pObj, i ) { - pNet = Abc_ObjFanin0(Abc_ObjFanin0(pTerm)); + pNet = Abc_ObjFanin0(Abc_ObjFanin0(pObj)); Counter++; // get the line length after this name is written AddedLength = strlen(Io_WriteVerilogGetName(pNet)) + 2; @@ -359,6 +302,47 @@ void Io_WriteVerilogWires( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) LineLength += AddedLength; NameCounter++; } + Abc_NtkForEachBox( pNtk, pBox, i ) + { + if ( Abc_ObjIsLatch(pBox) ) + continue; + Abc_ObjForEachFanin( pBox, pTerm, k ) + { + pNet = Abc_ObjFanin0(pTerm); + Counter++; + // get the line length after this name is written + AddedLength = strlen(Io_WriteVerilogGetName(pNet)) + 2; + if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) + { // write the line extender + fprintf( pFile, "\n " ); + // reset the line length + LineLength = 3; + NameCounter = 0; + } + fprintf( pFile, " %s%s", Io_WriteVerilogGetName(pNet), (Counter==nNodes)? "" : "," ); + LineLength += AddedLength; + NameCounter++; + } + Abc_ObjForEachFanout( pBox, pTerm, k ) + { + pNet = Abc_ObjFanout0(pTerm); + if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) + continue; + Counter++; + // get the line length after this name is written + AddedLength = strlen(Io_WriteVerilogGetName(pNet)) + 2; + if ( NameCounter && LineLength + AddedLength + 3 > IO_WRITE_LINE_LENGTH ) + { // write the line extender + fprintf( pFile, "\n " ); + // reset the line length + LineLength = 3; + NameCounter = 0; + } + fprintf( pFile, " %s%s", Io_WriteVerilogGetName(pNet), (Counter==nNodes)? "" : "," ); + LineLength += AddedLength; + NameCounter++; + } + } assert( Counter == nNodes ); } @@ -418,13 +402,13 @@ void Io_WriteVerilogRegs( FILE * pFile, Abc_Ntk_t * pNtk, int Start ) SeeAlso [] ***********************************************************************/ -void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) +void Io_WriteVerilogLatches2( FILE * pFile, Abc_Ntk_t * pNtk ) { Abc_Obj_t * pLatch; int i; Abc_NtkForEachLatch( pNtk, pLatch, i ) { -// fprintf( pFile, " always@(posedge gclk) begin %s", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); +// fprintf( pFile, " always @(posedge gclk) begin %s", Abc_ObjName(Abc_ObjFanout0(pLatch)) ); fprintf( pFile, " always begin %s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); fprintf( pFile, " = %s; end\n", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) ); if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO ) @@ -436,22 +420,49 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) } } -/* // fix by Zhihong +/**Function************************************************************* + + Synopsis [Writes the latches.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) { Abc_Obj_t * pLatch; int i; + if ( Abc_NtkLatchNum(pNtk) == 0 ) + return; + // write the latches +// fprintf( pFile, " always @(posedge %s) begin\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_NtkPi(pNtk,0))) ); + fprintf( pFile, " always begin\n" ); + Abc_NtkForEachLatch( pNtk, pLatch, i ) + { + fprintf( pFile, " %s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); + fprintf( pFile, " <= %s;\n", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) ); + } + fprintf( pFile, " end\n" ); + // check if there are initial values + Abc_NtkForEachLatch( pNtk, pLatch, i ) + if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO || Abc_LatchInit(pLatch) == ABC_INIT_ONE ) + break; + if ( i == Abc_NtkLatchNum(pNtk) ) + return; + // write the initial values + fprintf( pFile, " initial begin\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_NtkPi(pNtk,0))) ); Abc_NtkForEachLatch( pNtk, pLatch, i ) { if ( Abc_LatchInit(pLatch) == ABC_INIT_ZERO ) - fprintf( pFile, " initial begin %s <= 1\'b0; end\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); + fprintf( pFile, " %s <= 1\'b0;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); else if ( Abc_LatchInit(pLatch) == ABC_INIT_ONE ) - fprintf( pFile, " initial begin %s <= 1\'b1; end\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); - fprintf( pFile, " always@(posedge gclk) begin %s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); - fprintf( pFile, " <= %s; end\n", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin0(pLatch))) ); + fprintf( pFile, " %s <= 1\'b1;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout0(pLatch))) ); } + fprintf( pFile, " end\n" ); } -*/ /**Function************************************************************* @@ -464,10 +475,10 @@ void Io_WriteVerilogLatches( FILE * pFile, Abc_Ntk_t * pNtk ) SeeAlso [] ***********************************************************************/ -void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk ) +void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk ) { Vec_Vec_t * vLevels; - Abc_Ntk_t * pNtkGate; + Abc_Ntk_t * pNtkBox; Abc_Obj_t * pObj, * pTerm, * pFanin; Hop_Obj_t * pFunc; int i, k, Counter, nDigits; @@ -478,18 +489,20 @@ void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk ) // write boxes Abc_NtkForEachBox( pNtk, pObj, i ) { - pNtkGate = pObj->pData; - fprintf( pFile, " %s g%0*d", pNtkGate->pName, nDigits, Counter++ ); + if ( Abc_ObjIsLatch(pObj) ) + continue; + pNtkBox = pObj->pData; + fprintf( pFile, " %s g%0*d", pNtkBox->pName, nDigits, Counter++ ); fprintf( pFile, "(" ); - Abc_NtkForEachPi( pNtkGate, pTerm, k ) + Abc_NtkForEachPi( pNtkBox, pTerm, k ) { fprintf( pFile, ".%s ", Io_WriteVerilogGetName(Abc_ObjFanout0(pTerm)) ); - fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjFanin(pObj,k)) ); + fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjFanin0(Abc_ObjFanin(pObj,k))) ); } - Abc_NtkForEachPo( pNtkGate, pTerm, k ) + Abc_NtkForEachPo( pNtkBox, pTerm, k ) { fprintf( pFile, ".%s ", Io_WriteVerilogGetName(Abc_ObjFanin0(pTerm)) ); - fprintf( pFile, "(%s)%s", Io_WriteVerilogGetName(Abc_ObjFanout(pObj,k)), k==Abc_NtkPoNum(pNtkGate)-1? "":", " ); + fprintf( pFile, "(%s)%s", Io_WriteVerilogGetName(Abc_ObjFanout0(Abc_ObjFanout(pObj,k))), k==Abc_NtkPoNum(pNtkBox)-1? "":", " ); } fprintf( pFile, ");\n" ); } @@ -514,40 +527,7 @@ void Io_WriteVerilogVerLibStyle( FILE * pFile, Abc_Ntk_t * pNtk ) /**Function************************************************************* - Synopsis [Writes the gates.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogGates( FILE * pFile, Abc_Ntk_t * pNtk ) -{ - Mio_Gate_t * pGate; - Mio_Pin_t * pGatePin; - Abc_Obj_t * pObj; - int i, k, Counter, nDigits, nFanins; - - Counter = 1; - nDigits = Extra_Base10Log( Abc_NtkNodeNum(pNtk) ); - Abc_NtkForEachNode( pNtk, pObj, i ) - { - pGate = pObj->pData; - nFanins = Abc_ObjFaninNum(pObj); - fprintf( pFile, " %s g%0*d", Mio_GateReadName(pGate), nDigits, Counter++ ); - fprintf( pFile, "(.%s (%s),", Mio_GateReadOutName(pGate), Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) ); - for ( pGatePin = Mio_GateReadPins(pGate), k = 0; pGatePin; pGatePin = Mio_PinReadNext(pGatePin), k++ ) - fprintf( pFile, " .%s (%s)%s", Mio_PinReadName(pGatePin), Io_WriteVerilogGetName(Abc_ObjFanin(pObj,k)), k==nFanins-1? "":"," ); - fprintf( pFile, ");\n" ); - } -} - - -/**Function************************************************************* - - Synopsis [Writes the nodes.] + Synopsis [Counts the number of wires.] Description [] @@ -556,106 +536,34 @@ void Io_WriteVerilogGates( FILE * pFile, Abc_Ntk_t * pNtk ) SeeAlso [] ***********************************************************************/ -void Io_WriteVerilogNodes2( FILE * pFile, Abc_Ntk_t * pNtk ) +int Io_WriteVerilogWiresCount( Abc_Ntk_t * pNtk ) { - Abc_Obj_t * pObj, * pFanin; - int i, k, nFanins; - char * pName; - + Abc_Obj_t * pObj, * pNet, * pBox; + int i, k, nWires; + nWires = Abc_NtkLatchNum(pNtk); Abc_NtkForEachNode( pNtk, pObj, i ) { - assert( Abc_SopGetCubeNum(pObj->pData) == 1 ); - nFanins = Abc_ObjFaninNum(pObj); - if ( nFanins == 0 ) - { -// fprintf( pFile, " assign %s = 1'b%d;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)), !Abc_SopIsComplement(pObj->pData) ); - fprintf( pFile, " assign %s = %d;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)), !Abc_SopIsComplement(pObj->pData) ); + if ( i == 0 ) continue; - } - if ( nFanins == 1 ) - { - pName = Abc_SopIsInv(pObj->pData)? "not" : "and"; - fprintf( pFile, " %s(%s, ", pName, Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) ); - fprintf( pFile, "%s);\n", Io_WriteVerilogGetName(Abc_ObjFanin0(pObj)) ); + pNet = Abc_ObjFanout0(pObj); + if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) continue; - } - pName = Abc_SopIsComplement(pObj->pData)? "or" : "and"; - fprintf( pFile, " %s(%s, ", pName, Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) ); -// Abc_ObjForEachFanin( pObj, pFanin, k ) -// fprintf( pFile, "%s%s", Io_WriteVerilogGetName(pFanin), (k==nFanins-1? "" : ", ") ); - Abc_ObjForEachFanin( pObj, pFanin, k ) - { - char *cube = pObj->pData; - fprintf( pFile, "%s", cube[k] == '0' ? "~" : ""); - fprintf( pFile, "%s%s", Io_WriteVerilogGetName(pFanin), (k==nFanins-1? "" : ", ") ); - } - fprintf( pFile, ");\n" ); + nWires++; } -} - -/**Function************************************************************* - - Synopsis [Writes the nodes.] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -void Io_WriteVerilogNodes( FILE * pFile, Abc_Ntk_t * pNtk ) -{ - Abc_Obj_t * pObj, * pFanin; - int i, k, nFanins; - char pOper[] = " ? ", Symb; - Abc_NtkForEachNode( pNtk, pObj, i ) + Abc_NtkForEachBox( pNtk, pBox, i ) { - assert( Abc_SopGetCubeNum(pObj->pData) == 1 ); - nFanins = Abc_ObjFaninNum(pObj); - if ( nFanins == 0 ) - { - fprintf( pFile, " assign %s = 1'b%d;\n", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)), !Abc_SopIsComplement(pObj->pData) ); + if ( Abc_ObjIsLatch(pBox) ) continue; - } - fprintf( pFile, " assign %s = ", Io_WriteVerilogGetName(Abc_ObjFanout0(pObj)) ); - pOper[1] = Abc_SopIsComplement(pObj->pData) ? '|' : '&'; - Abc_ObjForEachFanin( pObj, pFanin, k ) - { - Symb = ((char*)pObj->pData)[k]; - assert( Symb == '0' || Symb == '1' ); - if ( Symb == '0' ) - fprintf( pFile, "~" ); - fprintf( pFile, "%s%s", Io_WriteVerilogGetName(pFanin), (k==nFanins-1? "" : pOper) ); - } - fprintf( pFile, ";\n" ); - } -} - -/**Function************************************************************* - - Synopsis [] - - Description [] - - SideEffects [] - - SeeAlso [] - -***********************************************************************/ -int Io_WriteVerilogCheckNtk( Abc_Ntk_t * pNtk ) -{ - Abc_Obj_t * pObj; - int i; - Abc_NtkForEachNode( pNtk, pObj, i ) - { - if ( Abc_SopGetCubeNum(pObj->pData) > 1 ) + nWires += Abc_ObjFaninNum(pBox); + Abc_ObjForEachFanout( pBox, pObj, k ) { - printf( "Node %s contains a cover with more than one cube.\n", Abc_ObjName(pObj) ); - return 0; + pNet = Abc_ObjFanout0(pObj); + if ( Abc_ObjFanoutNum(pNet) > 0 && Abc_ObjIsCo(Abc_ObjFanout0(pNet)) ) + continue; + nWires++; } } - return 1; + return nWires; } /**Function************************************************************* diff --git a/src/base/io/module.make b/src/base/io/module.make index fd66dd22..4b6f762c 100644 --- a/src/base/io/module.make +++ b/src/base/io/module.make @@ -8,6 +8,7 @@ SRC += src/base/io/io.c \ src/base/io/ioReadEdif.c \ src/base/io/ioReadEqn.c \ src/base/io/ioReadPla.c \ + src/base/io/ioReadVerilog.c \ src/base/io/ioUtil.c \ src/base/io/ioWriteAiger.c \ src/base/io/ioWriteBaf.c \ @@ -20,5 +21,4 @@ SRC += src/base/io/io.c \ src/base/io/ioWriteGml.c \ src/base/io/ioWriteList.c \ src/base/io/ioWritePla.c \ - src/base/io/ioWriteVer.c \ - src/base/io/ioWriteVerAux.c + src/base/io/ioWriteVerilog.c diff --git a/src/base/ver/ver.h b/src/base/ver/ver.h index c7c18f79..575ae7bb 100644 --- a/src/base/ver/ver.h +++ b/src/base/ver/ver.h @@ -48,6 +48,7 @@ struct Ver_Man_t_ // input file stream char * pFileName; Ver_Stream_t * pReader; + int fNameLast; ProgressBar * pProgress; // current network and library Abc_Ntk_t * pNtkCur; // the network under construction diff --git a/src/base/ver/verCore.c b/src/base/ver/verCore.c index bbef90be..3a1a9584 100644 --- a/src/base/ver/verCore.c +++ b/src/base/ver/verCore.c @@ -60,7 +60,8 @@ static int Ver_ParseGateStandard( Ver_Man_t * pMan, Ver_GateType_t GateType ); static Abc_Obj_t * Ver_ParseCreatePi( Abc_Ntk_t * pNtk, char * pName ); static Abc_Obj_t * Ver_ParseCreatePo( Abc_Ntk_t * pNtk, char * pName ); -static Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO ); +static Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, Abc_Obj_t * pNetLI, Abc_Obj_t * pNetLO ); +static Abc_Obj_t * Ver_ParseCreateInv( Abc_Ntk_t * pNtk, Abc_Obj_t * pNet ); //////////////////////////////////////////////////////////////////////// /// FUNCTION DEFINITIONS /// @@ -281,8 +282,8 @@ int Ver_ParseModule( Ver_Man_t * pMan ) pNtk->pSpec = NULL; // create constant nets - Abc_NtkFindOrCreateNet( pNtk, "1'b0" ); - Abc_NtkFindOrCreateNet( pNtk, "1'b1" ); + Abc_NtkFindOrCreateNet( pNtk, "1\'b0" ); + Abc_NtkFindOrCreateNet( pNtk, "1\'b1" ); // make sure we stopped at the opening paranthesis if ( Ver_StreamPopChar(p) != '(' ) @@ -383,13 +384,13 @@ int Ver_ParseModule( Ver_Man_t * pMan ) } // check if constant 0 net is used - pNet = Abc_NtkFindOrCreateNet( pNtk, "1'b0" ); + pNet = Abc_NtkFindOrCreateNet( pNtk, "1\'b0" ); if ( Abc_ObjFanoutNum(pNet) == 0 ) Abc_NtkDeleteObj(pNet); else Abc_ObjAddFanin( pNet, Abc_NtkCreateNodeConst0(pNtk) ); // check if constant 1 net is used - pNet = Abc_NtkFindOrCreateNet( pNtk, "1'b1" ); + pNet = Abc_NtkFindOrCreateNet( pNtk, "1\'b1" ); if ( Abc_ObjFanoutNum(pNet) == 0 ) Abc_NtkDeleteObj(pNet); else @@ -397,6 +398,13 @@ int Ver_ParseModule( Ver_Man_t * pMan ) // fix the dangling nets Abc_NtkFinalizeRead( pNtk ); + + // check the functionality to blackbox if insides are not defined + if ( Abc_NtkNodeNum(pNtk) == 0 && Abc_NtkBoxNum(pNtk) == 0 ) + { + pNtk->ntkFunc = ABC_FUNC_BLACKBOX; + pNtk->pManFunc = NULL; + } return 1; } @@ -415,6 +423,8 @@ int Ver_ParseSignal( Ver_Man_t * pMan, Ver_SignalType_t SigType ) { Ver_Stream_t * p = pMan->pReader; Abc_Ntk_t * pNtk = pMan->pNtkCur; + char Buffer[1000]; + int Lower, Upper, i; char * pWord; char Symbol; while ( 1 ) @@ -422,12 +432,41 @@ int Ver_ParseSignal( Ver_Man_t * pMan, Ver_SignalType_t SigType ) pWord = Ver_ParseGetName( pMan ); if ( pWord == NULL ) return 0; - if ( SigType == VER_SIG_INPUT || SigType == VER_SIG_INOUT ) - Ver_ParseCreatePi( pNtk, pWord ); - if ( SigType == VER_SIG_OUTPUT || SigType == VER_SIG_INOUT ) - Ver_ParseCreatePo( pNtk, pWord ); - if ( SigType == VER_SIG_WIRE || SigType == VER_SIG_REG ) - Abc_NtkFindOrCreateNet( pNtk, pWord ); + if ( pWord[0] == '[' && !pMan->fNameLast ) + { + Lower = atoi( pWord + 1 ); + while ( *pWord && *pWord != ':' ) + pWord++; + if ( *pWord == 0 ) + Upper = Lower; + else + Upper = atoi( pWord + 1 ); + if ( Lower > Upper ) + i = Lower, Lower = Upper, Upper = i; + // get the signal name + pWord = Ver_ParseGetName( pMan ); + if ( pWord == NULL ) + return 0; + for ( i = Lower; i <= Upper; i++ ) + { + sprintf( Buffer, "%s[%d]", pWord, i ); + if ( SigType == VER_SIG_INPUT || SigType == VER_SIG_INOUT ) + Ver_ParseCreatePi( pNtk, Buffer ); + if ( SigType == VER_SIG_OUTPUT || SigType == VER_SIG_INOUT ) + Ver_ParseCreatePo( pNtk, Buffer ); + if ( SigType == VER_SIG_WIRE || SigType == VER_SIG_REG ) + Abc_NtkFindOrCreateNet( pNtk, Buffer ); + } + } + else + { + if ( SigType == VER_SIG_INPUT || SigType == VER_SIG_INOUT ) + Ver_ParseCreatePi( pNtk, pWord ); + if ( SigType == VER_SIG_OUTPUT || SigType == VER_SIG_INOUT ) + Ver_ParseCreatePo( pNtk, pWord ); + if ( SigType == VER_SIG_WIRE || SigType == VER_SIG_REG ) + Abc_NtkFindOrCreateNet( pNtk, pWord ); + } Symbol = Ver_StreamPopChar(p); if ( Symbol == ',' ) continue; @@ -461,6 +500,11 @@ int Ver_ParseAssign( Ver_Man_t * pMan ) char Symbol; int i, Length, fReduction; +// if ( Ver_StreamGetLineNumber(p) == 2756 ) +// { +// int x = 0; +// } + // convert from the mapped netlist into the BDD netlist if ( pNtk->ntkFunc == ABC_FUNC_BLACKBOX ) { @@ -482,7 +526,9 @@ int Ver_ParseAssign( Ver_Man_t * pMan ) if ( pWord == NULL ) return 0; // consider the case of reduction operations - fReduction = (pWord[0] == '{'); + fReduction = 0; + if ( pWord[0] == '{' && !pMan->fNameLast ) + fReduction = 1; if ( fReduction ) { pWord++; @@ -497,7 +543,7 @@ int Ver_ParseAssign( Ver_Man_t * pMan ) Ver_ParsePrintErrorMessage( pMan ); return 0; } - // get the equal sign + // get the equality sign if ( Ver_StreamPopChar(p) != '=' ) { sprintf( pMan->sError, "Cannot read the assign statement for %s (expected equality sign).", pWord ); @@ -572,28 +618,39 @@ int Ver_ParseAlways( Ver_Man_t * pMan ) Ver_Stream_t * p = pMan->pReader; Abc_Ntk_t * pNtk = pMan->pNtkCur; Abc_Obj_t * pNet, * pNet2; + int fStopAfterOne; char * pWord, * pWord2; char Symbol; // parse the directive pWord = Ver_ParseGetName( pMan ); if ( pWord == NULL ) return 0; - if ( strcmp( pWord, "begin" ) ) + if ( pWord[0] == '@' ) { - sprintf( pMan->sError, "Cannot parse the always statement (expected \"begin\")." ); - Ver_ParsePrintErrorMessage( pMan ); - return 0; + Ver_StreamSkipToChars( p, ")" ); + Ver_StreamPopChar(p); + // parse the directive + pWord = Ver_ParseGetName( pMan ); + if ( pWord == NULL ) + return 0; } + // decide how many statements to parse + fStopAfterOne = 0; + if ( strcmp( pWord, "begin" ) ) + fStopAfterOne = 1; // iterate over the initial states while ( 1 ) { - // get the name of the output signal - pWord = Ver_ParseGetName( pMan ); - if ( pWord == NULL ) - return 0; - // look for the end of directive - if ( !strcmp( pWord, "end" ) ) - break; + if ( !fStopAfterOne ) + { + // get the name of the output signal + pWord = Ver_ParseGetName( pMan ); + if ( pWord == NULL ) + return 0; + // look for the end of directive + if ( !strcmp( pWord, "end" ) ) + break; + } // get the fanout net pNet = Abc_NtkFindNet( pNtk, pWord ); if ( pNet == NULL ) @@ -602,13 +659,16 @@ int Ver_ParseAlways( Ver_Man_t * pMan ) Ver_ParsePrintErrorMessage( pMan ); return 0; } - // get the equal sign - if ( Ver_StreamPopChar(p) != '=' ) + // get the equality sign + Symbol = Ver_StreamPopChar(p); + if ( Symbol != '<' && Symbol != '=' ) { - sprintf( pMan->sError, "Cannot read the always statement for %s (expected equality sign).", pWord ); + sprintf( pMan->sError, "Cannot read the assign statement for %s (expected <= or =).", pWord ); Ver_ParsePrintErrorMessage( pMan ); return 0; } + if ( Symbol == '<' ) + Ver_StreamPopChar(p); // skip the comments if ( !Ver_ParseSkipComments( pMan ) ) return 0; @@ -616,8 +676,14 @@ int Ver_ParseAlways( Ver_Man_t * pMan ) pWord2 = Ver_ParseGetName( pMan ); if ( pWord2 == NULL ) return 0; - // get the fanin net - pNet2 = Abc_NtkFindNet( pNtk, pWord2 ); + // check if the name is complemented + if ( pWord2[0] == '~' ) + { + pNet2 = Abc_NtkFindNet( pNtk, pWord2+1 ); + pNet2 = Ver_ParseCreateInv( pNtk, pNet2 ); + } + else + pNet2 = Abc_NtkFindNet( pNtk, pWord2 ); if ( pNet2 == NULL ) { sprintf( pMan->sError, "Cannot read the always statement for %s (input wire is not defined).", pWord2 ); @@ -625,10 +691,13 @@ int Ver_ParseAlways( Ver_Man_t * pMan ) return 0; } // create the latch - Ver_ParseCreateLatch( pNtk, pNet2->pData, pNet->pData ); + Ver_ParseCreateLatch( pNtk, pNet2, pNet ); // remove the last symbol Symbol = Ver_StreamPopChar(p); assert( Symbol == ';' ); + // quit if only one directive + if ( fStopAfterOne ) + break; } return 1; } @@ -649,28 +718,30 @@ int Ver_ParseInitial( Ver_Man_t * pMan ) Ver_Stream_t * p = pMan->pReader; Abc_Ntk_t * pNtk = pMan->pNtkCur; Abc_Obj_t * pNode, * pNet; + int fStopAfterOne; char * pWord, * pEquation; char Symbol; // parse the directive pWord = Ver_ParseGetName( pMan ); if ( pWord == NULL ) return 0; + // decide how many statements to parse + fStopAfterOne = 0; if ( strcmp( pWord, "begin" ) ) - { - sprintf( pMan->sError, "Cannot parse the initial statement (expected \"begin\")." ); - Ver_ParsePrintErrorMessage( pMan ); - return 0; - } + fStopAfterOne = 1; // iterate over the initial states while ( 1 ) { - // get the name of the output signal - pWord = Ver_ParseGetName( pMan ); - if ( pWord == NULL ) - return 0; - // look for the end of directive - if ( !strcmp( pWord, "end" ) ) - break; + if ( !fStopAfterOne ) + { + // get the name of the output signal + pWord = Ver_ParseGetName( pMan ); + if ( pWord == NULL ) + return 0; + // look for the end of directive + if ( !strcmp( pWord, "end" ) ) + break; + } // get the fanout net pNet = Abc_NtkFindNet( pNtk, pWord ); if ( pNet == NULL ) @@ -679,13 +750,16 @@ int Ver_ParseInitial( Ver_Man_t * pMan ) Ver_ParsePrintErrorMessage( pMan ); return 0; } - // get the equal sign - if ( Ver_StreamPopChar(p) != '=' ) + // get the equality sign + Symbol = Ver_StreamPopChar(p); + if ( Symbol != '<' && Symbol != '=' ) { - sprintf( pMan->sError, "Cannot read the initial statement for %s (expected equality sign).", pWord ); + sprintf( pMan->sError, "Cannot read the assign statement for %s (expected <= or =).", pWord ); Ver_ParsePrintErrorMessage( pMan ); return 0; } + if ( Symbol == '<' ) + Ver_StreamPopChar(p); // skip the comments if ( !Ver_ParseSkipComments( pMan ) ) return 0; @@ -694,24 +768,33 @@ int Ver_ParseInitial( Ver_Man_t * pMan ) if ( pEquation == NULL ) return 0; // find the corresponding latch - pNode = Abc_ObjFanin0(pNet); + if ( Abc_ObjFaninNum(pNet) == 0 ) + { + sprintf( pMan->sError, "Cannot find the latch to assign the initial value." ); + Ver_ParsePrintErrorMessage( pMan ); + return 0; + } + pNode = Abc_ObjFanin0(Abc_ObjFanin0(pNet)); assert( Abc_ObjIsLatch(pNode) ); // set the initial state - if ( pEquation[0] == '2' ) - Abc_LatchSetInitDc( pNode ); - else if ( pEquation[0] == '1') - Abc_LatchSetInit1( pNode ); - else if ( pEquation[0] == '0' ) + if ( !strcmp(pEquation, "0") || !strcmp(pEquation, "1\'b0") ) Abc_LatchSetInit0( pNode ); - else + else if ( !strcmp(pEquation, "1") || !strcmp(pEquation, "1\'b1") ) + Abc_LatchSetInit1( pNode ); +// else if ( !strcmp(pEquation, "2") ) +// Abc_LatchSetInitDc( pNode ); + else { - sprintf( pMan->sError, "Incorrect initial value of the latch %s (expected equality sign).", pWord ); + sprintf( pMan->sError, "Incorrect initial value of the latch %s.", Abc_ObjName(pNet) ); Ver_ParsePrintErrorMessage( pMan ); return 0; } // remove the last symbol Symbol = Ver_StreamPopChar(p); assert( Symbol == ';' ); + // quit if only one directive + if ( fStopAfterOne ) + break; } return 1; } @@ -732,7 +815,7 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate ) Ver_Stream_t * p = pMan->pReader; Abc_Ntk_t * pNtk = pMan->pNtkCur; Abc_Obj_t * pNetFormal, * pNetActual; - Abc_Obj_t * pObj, * pNode; + Abc_Obj_t * pObj, * pNode, * pTerm; char * pWord, Symbol, * pGateName; int i, fCompl, fComplUsed = 0; unsigned * pPolarity; @@ -820,9 +903,9 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate ) } // process the pair - if ( Abc_ObjIsPi(Abc_ObjFanin0Ntk(pNetFormal)) ) // PI net (with polarity!) + if ( Abc_ObjFaninNum(pNetFormal) > 0 && Abc_ObjIsPi(Abc_ObjFanin0Ntk(pNetFormal)) ) // PI net (with polarity!) Abc_ObjFanin0Ntk(pNetFormal)->pCopy = Abc_ObjNotCond( pNetActual, fCompl ); - else if ( Abc_ObjIsPo(Abc_ObjFanout0Ntk(pNetFormal)) ) // P0 net + else if ( Abc_ObjFanoutNum(pNetFormal) > 0 && Abc_ObjIsPo(Abc_ObjFanout0Ntk(pNetFormal)) ) // P0 net { assert( fCompl == 0 ); Abc_ObjFanout0Ntk(pNetFormal)->pCopy = pNetActual; // Abc_ObjNotCond( pNetActual, fCompl ); @@ -862,7 +945,7 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate ) Abc_NtkForEachPi( pNtkGate, pObj, i ) if ( pObj->pCopy == NULL ) { - sprintf( pMan->sError, "Formal input %s of gate %s has no actual input.", Abc_ObjFanout0(pObj)->pData, pNtkGate->pName ); + sprintf( pMan->sError, "Formal input %s of gate %s has no actual input.", Abc_ObjName(Abc_ObjFanout0(pObj)), pNtkGate->pName ); Ver_ParsePrintErrorMessage( pMan ); return 0; } @@ -871,7 +954,7 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate ) Abc_NtkForEachPo( pNtkGate, pObj, i ) if ( pObj->pCopy == NULL ) { - sprintf( pMan->sError, "Formal output %s of gate %s has no actual output.", Abc_ObjFanin0(pObj)->pData, pNtkGate->pName ); + sprintf( pMan->sError, "Formal output %s of gate %s has no actual output.", Abc_ObjName(Abc_ObjFanin0(pObj)), pNtkGate->pName ); Ver_ParsePrintErrorMessage( pMan ); return 0; } @@ -887,12 +970,6 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate ) } // create box to represent this gate pNode = Abc_NtkCreateBlackbox( pMan->pNtkCur ); -/* - if ( pNode->Id == 57548 ) - { - int x = 0; - } -*/ pNode->pNext = (Abc_Obj_t *)pPolarity; pNode->pData = pNtkGate; // connect to fanin nets @@ -904,15 +981,20 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtkGate ) pObj->pCopy = Abc_ObjRegular( pObj->pCopy ); } assert( !Abc_ObjIsComplement(pObj->pCopy) ); - Abc_ObjAddFanin( pNode, pObj->pCopy ); +// Abc_ObjAddFanin( pNode, pObj->pCopy ); + pTerm = Abc_NtkCreateBi( pNtk ); + Abc_ObjAddFanin( pTerm, pObj->pCopy ); + Abc_ObjAddFanin( pNode, pTerm ); } // connect to fanout nets Abc_NtkForEachPo( pNtkGate, pObj, i ) { - if ( pObj->pCopy ) - Abc_ObjAddFanin( pObj->pCopy, pNode ); - else - Abc_ObjAddFanin( Abc_NtkFindOrCreateNet(pNtk, NULL), pNode ); + if ( pObj->pCopy == NULL ) + pObj->pCopy = Abc_NtkFindOrCreateNet(pNtk, NULL); +// Abc_ObjAddFanin( pObj->pCopy, pNode ); + pTerm = Abc_NtkCreateBo( pNtk ); + Abc_ObjAddFanin( pTerm, pNode ); + Abc_ObjAddFanin( pObj->pCopy, pTerm ); } return 1; } @@ -1063,27 +1145,52 @@ Abc_Obj_t * Ver_ParseCreatePo( Abc_Ntk_t * pNtk, char * pName ) Synopsis [Create a latch with the given input/output.] - Description [By default, the latch value is unknown (ABC_INIT_NONE).] + Description [By default, the latch value is a don't-care.] SideEffects [] SeeAlso [] ***********************************************************************/ -Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, char * pNetLI, char * pNetLO ) +Abc_Obj_t * Ver_ParseCreateLatch( Abc_Ntk_t * pNtk, Abc_Obj_t * pNetLI, Abc_Obj_t * pNetLO ) { - Abc_Obj_t * pLatch, * pNet; - // create a new latch and add it to the network + Abc_Obj_t * pLatch, * pTerm; + // add the BO terminal + pTerm = Abc_NtkCreateBi( pNtk ); + Abc_ObjAddFanin( pTerm, pNetLI ); + // add the latch box pLatch = Abc_NtkCreateLatch( pNtk ); - // get the LI net - pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLI ); - Abc_ObjAddFanin( pLatch, pNet ); + Abc_ObjAddFanin( pLatch, pTerm ); + // add the BI terminal + pTerm = Abc_NtkCreateBo( pNtk ); + Abc_ObjAddFanin( pTerm, pLatch ); // get the LO net - pNet = Abc_NtkFindOrCreateNet( pNtk, pNetLO ); - Abc_ObjAddFanin( pNet, pLatch ); + Abc_ObjAddFanin( pNetLO, pTerm ); + // set latch name + Abc_ObjAssignName( pLatch, Abc_ObjName(pNetLO), "L" ); + Abc_LatchSetInitDc( pLatch ); return pLatch; } +/**Function************************************************************* + + Synopsis [Creates inverter and returns its net.] + + Description [] + + SideEffects [] + + SeeAlso [] + +***********************************************************************/ +Abc_Obj_t * Ver_ParseCreateInv( Abc_Ntk_t * pNtk, Abc_Obj_t * pNet ) +{ + Abc_Obj_t * pObj; + pObj = Abc_NtkCreateNodeInv( pNtk, pNet ); + pNet = Abc_NtkCreateObj( pNtk, ABC_OBJ_NET ); + Abc_ObjAddFanin( pNet, pObj ); + return pNet; +} //////////////////////////////////////////////////////////////////////// /// END OF FILE /// diff --git a/src/base/ver/verFormula.c b/src/base/ver/verFormula.c index cfe3e0c8..16192f6a 100644 --- a/src/base/ver/verFormula.c +++ b/src/base/ver/verFormula.c @@ -83,6 +83,11 @@ void * Ver_FormulaParser( char * pFormula, void * pMan, Vec_Ptr_t * vNames, Vec_ Vec_PtrClear( vStackFn ); Vec_IntClear( vStackOp ); + if ( !strcmp(pFormula, "0") || !strcmp(pFormula, "1\'b0") ) + return Hop_ManConst0(pMan); + if ( !strcmp(pFormula, "1") || !strcmp(pFormula, "1\'b1") ) + return Hop_ManConst1(pMan); + // make sure that the number of opening and closing parantheses is the same nParans = 0; for ( pTemp = pFormula; *pTemp; pTemp++ ) diff --git a/src/base/ver/verParse.c b/src/base/ver/verParse.c index 8a78e75b..f3afaca0 100644 --- a/src/base/ver/verParse.c +++ b/src/base/ver/verParse.c @@ -90,6 +90,7 @@ char * Ver_ParseGetName( Ver_Man_t * pMan ) Ver_Stream_t * p = pMan->pReader; char Symbol; char * pWord; + pMan->fNameLast = 0; if ( !Ver_StreamIsOkey(p) ) return NULL; if ( !Ver_ParseSkipComments( pMan ) ) @@ -97,6 +98,7 @@ char * Ver_ParseGetName( Ver_Man_t * pMan ) Symbol = Ver_StreamScanChar( p ); if ( Symbol == '\\' ) { + pMan->fNameLast = 1; Ver_StreamPopChar( p ); pWord = Ver_StreamGetWord( p, " " ); } diff --git a/src/base/ver/verStream.c b/src/base/ver/verStream.c index 7956b13c..0edbcdcb 100644 --- a/src/base/ver/verStream.c +++ b/src/base/ver/verStream.c @@ -279,6 +279,9 @@ char Ver_StreamPopChar( Ver_Stream_t * p ) p->fStop = 1; return -1; } + // count the lines + if ( *p->pBufferCur == '\n' ) + p->nLineCounter++; return *p->pBufferCur++; } @@ -359,6 +362,9 @@ void Ver_StreamSkipToChars( Ver_Stream_t * p, char * pCharsToStop ) if ( *pTemp == 0 ) // pChar is not found in the list continue; // the symbol is found - move position and return + if ( *pChar == '\n' ) + p->nLineCounter--; + // update buffer p->pBufferCur = pChar; return; } |