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| author | Alan Mishchenko <alanmi@berkeley.edu> | 2019-11-18 22:29:09 +0800 |
|---|---|---|
| committer | Alan Mishchenko <alanmi@berkeley.edu> | 2019-11-18 22:29:09 +0800 |
| commit | 0d24b4e4cab591e0b39862f5e4abd6f37725469a (patch) | |
| tree | b386e61907c8a0cb6276c5a454a3438cb12a1be3 | |
| parent | dd5a1f5d3001429bc3abb6fd3a7fc04ff28ee6c5 (diff) | |
| download | abc-0d24b4e4cab591e0b39862f5e4abd6f37725469a.tar.gz abc-0d24b4e4cab591e0b39862f5e4abd6f37725469a.tar.bz2 abc-0d24b4e4cab591e0b39862f5e4abd6f37725469a.zip | |
Bug fix in parsing hierarchical BLIF with mapping.
| -rw-r--r-- | src/aig/gia/giaUtil.c | 2 | ||||
| -rw-r--r-- | src/base/io/ioReadBlifMv.c | 19 |
2 files changed, 18 insertions, 3 deletions
diff --git a/src/aig/gia/giaUtil.c b/src/aig/gia/giaUtil.c index 79c4758d..ad89dfe8 100644 --- a/src/aig/gia/giaUtil.c +++ b/src/aig/gia/giaUtil.c @@ -2377,6 +2377,8 @@ void Gia_ManDumpFiles( Gia_Man_t * p, int nCexesT, int nCexesV ) Vec_BitFree( vBitX ); Vec_BitFree( vBitY ); + + Res = 0; } } diff --git a/src/base/io/ioReadBlifMv.c b/src/base/io/ioReadBlifMv.c index df7a67af..c1808ef5 100644 --- a/src/base/io/ioReadBlifMv.c +++ b/src/base/io/ioReadBlifMv.c @@ -1420,8 +1420,8 @@ static int Io_MvParseLineSubckt( Io_MvMod_t * p, char * pLine ) */ if ( pName2 == NULL ) { - Abc_Obj_t * pNode = Abc_NtkCreateNode( p->pNtk ); - pNode->pData = Abc_SopRegister( (Mem_Flex_t *)p->pNtk->pManFunc, " 0\n" ); + Abc_Obj_t * pNode = Abc_NtkCreateNodeConst0( p->pNtk ); + //pNode->pData = Abc_SopRegister( (Mem_Flex_t *)p->pNtk->pManFunc, " 0\n" ); pNet = Abc_NtkFindOrCreateNet( p->pNtk, Abc_ObjNameSuffix(pNode, "abc") ); Abc_ObjAddFanin( pNet, pNode ); pTerm = Abc_NtkCreateBi( p->pNtk ); @@ -2268,12 +2268,25 @@ static int Io_MvParseLineGateBlif( Io_MvMod_t * p, Vec_Ptr_t * vTokens ) } // if this is the first line with gate, update the network type - if ( Abc_NtkNodeNum(p->pNtk) == 0 ) + if ( Abc_NtkNodeNum(p->pNtk) == 0 && p->pNtk->ntkFunc == ABC_FUNC_SOP ) { assert( p->pNtk->ntkFunc == ABC_FUNC_SOP ); p->pNtk->ntkFunc = ABC_FUNC_MAP; Mem_FlexStop( (Mem_Flex_t *)p->pNtk->pManFunc, 0 ); p->pNtk->pManFunc = pGenlib; + if ( p->pMan && p->pMan->pDesign && Vec_PtrSize(p->pMan->pDesign->vModules) > 0 ) + { + Abc_Ntk_t * pModel; int k; + Vec_PtrForEachEntry( Abc_Ntk_t *, p->pMan->pDesign->vModules, pModel, k ) + { + if ( pModel == p->pNtk ) + continue; + assert( pModel->ntkFunc == ABC_FUNC_SOP ); + pModel->ntkFunc = ABC_FUNC_MAP; + Mem_FlexStop( (Mem_Flex_t *)pModel->pManFunc, 0 ); + pModel->pManFunc = pGenlib; + } + } } // reorder the formal inputs to be in the same order as in the gate |