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** © Copyright 2010 Xilinx, Inc. All rights reserved.
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**   ____  ____ 
**  /   /\/   / 
** /___/  \  /   Vendor: Xilinx 
** \   \   \/    
**  \   \        readme.txt Version: 1.0  
**  /   /        Date Last Modified: 11/17/2010 
** /___/   /\    Date Created: 
** \   \  /  \   Associated Filename: xapp495.zip
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** 
**  Device: 
**  Purpose:
**  Reference: XAPP495.pdf
**  Revision History: 
**    1.0 - Initial Release
**   
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This readme describes how to use the files that come with XAPP495

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** IMPORTANT NOTES **

1) The design files have been tested on Digilent Atlys Board

2) The UCF files are targeted to the Atlys board

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Included files:

DVI transmitter

1.  "dvi_demo/rtl/tx/dvi_encoder.v" --- DVI transmitter top module without instantiation of clocking resources
2.  "dvi_demo/rtl/tx/dvi_encoder_top.v" --- DVI transmitter wrapper with instantiation of clocking resources
3.  "dvi_demo/rtl/tx/encode.v" --- DVI encoder
4.  "dvi_demo/rtl/tx/serdes_n_to_1.v" --- configurable to 5:1 serializaer
5.  "dvi_demo/rtl/tx/convert_30to15_fifo.v" --- 30-bit 2:1 gear box
6.  "dvi_demo/rtl/tx/vtc_demo.v" --- Color bar generator with programmable timing controller

DVI Receiver

1.  "dvi_demo/rtl/tx/dvi_decoder.v" --- DVI receiver top wrapper
2.  "dvi_demo/rtl/tx/decode.v"  --- DVI decoder instantiating the CDR and channel de-skew circuits
3.  "dvi_demo/rtl/tx/chnlbond.v"  --- Channel de-skew module
4.  "dvi_demo/rtl/tx/phsaligner.v"  --- Bitslip and TMDS data validation state machine
5.  "dvi_demo/rtl/tx/serdes_1_to_5_diff_data.v" --- 1:5 de-serializer

DVI Common Modules

1.  "dvi_demo/rtl/common/DRAM16XN.v" --- Width configurable distributed RAM
2.  "dvi_demo/rtl/common/timing.v" --- Video Timing Controller
3.  "dvi_demo/rtl/common/hdclrbar.v" --- SMPTE HD color bar generator
4.  "dvi_demo/rtl/common/debnce.v" --- DIP switch debouncer
5.  "dvi_demo/rtl/common/dcmspi.v" --- DCM_CLKGEN SPI controller
6.  "dvi_demo/rtl/common/synchro.v" --- Clock boundary synchronizer

DVI Evaluation

"dvi_demo/rtl/dvi_demo.v" --- 2x2 DVI Matrix design

UCF

"dvi_demo/ucf/vtc_demo.ucf"  --- Transmitter only design with color bar generation and programmable timing controller
"dvi_demo/ucf/dvi_demo.ucf"  --- 2x2 DVI Matrix design