library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity tmds_phy_spartan6 is
    port (
        reset        : in  std_logic;
        pclk_x2      : in  std_logic;
        ioclk        : in  std_logic;
        serdesstrobe : in  std_logic;
        din          : in  std_logic_vector(9 downto 0);
        upper        : in  std_logic;
        tmds_out_p   : out std_logic;
        tmds_out_n   : out std_logic
        );
end tmds_phy_spartan6;


architecture beh of tmds_phy_spartan6 is

    signal din_s : std_logic_vector(9 downto 0);
    signal p5_n  : std_logic_vector(4 downto 0);
    signal p5    : std_logic_vector(4 downto 0);
    signal s     : std_logic;



begin

    process (pclk_x2)
    begin
        if rising_edge(pclk_x2) then
            if upper = '1' then
                din_s <= din;
                p5    <= din_s(9 downto 5);
                p5_n  <= din_s(4 downto 0);
            else
                p5 <= p5_n;
            end if;
        end if;
    end process;


    serdes : entity work.serdes_n_to_1_spartan6
        generic map(SF => 5)
        port map (
            ioclk        => ioclk,
            serdesstrobe => serdesstrobe,
            reset        => reset,
            gclk         => pclk_x2,
            datain       => p5,
            iob_data_out => s
            );

    obuf : OBUFDS
        generic map (IOSTANDARD => "TMDS_33")
        port map (
            I  => s,
            O  => tmds_out_p,
            OB => tmds_out_n
            );


end beh;