include relpath.mk

BOARD=smh-ac415
FAMILY=Cyclone IV E
PART=EP4CE15F23C8
TOP=hp_lcd_driver
BUILD=build_${BOARD}
OF=output_files

PROJECT = hp_lcd_driver
VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl  output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl
IPS= vram_cyclone4_impl.vhdl  clkgen_cyclone4_a_impl.vhdl clkgen_cyclone4_b_impl.vhdl

DESIGN_NAME=${TOP}

MAP_ARGS = --smart 
FIT_ARGS =
ASM_ARGS =
STA_ARGS =
CPF_ARGS = -c -q 1MHZ -g 3.3 -n p

GEN_VSRCS=${IPS:%.vhdl=${BUILD}/%.vhd}
QIP=${GEN_VSRCS:%.vhd=%.qip}

BASE=${BUILD}/${DESIGN_NAME}
QSF=${BASE}.qsf
QPF=${BASE}.qpf
MAP=${BUILD}/${OF}/$(PROJECT).map.rpt
FIT=${BUILD}/${OF}/$(PROJECT).fit.rpt
ASM=${BUILD}/${OF}/$(PROJECT).asm.rpt
ASM=${BUILD}/${OF}/$(PROJECT).sta.rpt
SOF=${BUILD}/${OF}/${PROJECT}.sof
SVF=${BUILD}/${PROJECT}.svf

default:${SVF}


${BUILD}/%.vhd ${BUILD}/%.qip:%.vhdl
	cat $< > ${BUILD}/${<:%.vhdl=%.vhd}
	(cd ${BUILD} && run_quartus qmegawiz -silent $(call relpath,${BUILD}/${<:%.vhdl=%.vhd},${BUILD}))


${QSF}: ${PRJ} ${DESIGN_NAME}.${BOARD}_qsft
	mkdir -p ${BUILD}
	rm -f  $@
	echo 'set_global_assignment -name TOP_LEVEL_ENTITY ${TOP}' >> $@
	echo 'set_global_assignment -name FAMILY "${FAMILY}"' >> $@
	echo 'set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ${OF}' >> $@
	echo 'set_global_assignment -name DEVICE ${PART}' >> $@
	cat  ${DESIGN_NAME}.${BOARD}_qsft >> $@
	for file in ${GEN_VSRCS} ${VSRCS}; do \
	echo "set_global_assignment -name VHDL_FILE $$(realpath -m --relative-to=${BUILD} $${file})" >> $@; \
	done



${QPF}:
	mkdir -p ${BUILD}
	rm -f $@
	echo 'PROJECT_REVISION = "${TOP}"' > $@


map: ${MAP}
${MAP}: ${VSRCS} ${QPF} ${QSF} ${GEN_VSRCS}  ${QIP}
	(cd ${BUILD} && run_quartus quartus_map $(MAP_ARGS) ${PROJECT}) 

fit: ${FIT}
${FIT}:${MAP}
	(cd ${BUILD} && run_quartus quartus_fit $(FIT_ARGS) $(PROJECT))

asm: ${ASM}
sof: ${ASM}
${SOF} ${ASM}:${FIT}
	(cd ${BUILD} && run_quartus quartus_asm $(ASM_ARGS) $(PROJECT))

sta: ${STA}
${STA}:${FIT}
	(cd ${BUILD} && run_quartus quartus_sta $(STA_ARGS) $(PROJECT))


svf:${SVF}
${SVF}:${SOF}
	(cd ${BUILD} && run_quartus quartus_cpf ${CPF_ARGS} $(call relpath,$<,${BUILD}) $(call relpath,$@,${BUILD}) )



tidy:
	git diff --exit-code -s ${VSRCS}	
	for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done



#
#
##OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg
#
#FIT_ARGS = 
#ASM_ARGS =
#
#SVF=${PROJECT}.svf
#
#
#
#default: ${SVF}
#
#${SVF}: ${BUILD}/${PROJECT}.svf
#	cat $< > $@ || /bin/rm -f $@
#
#program: ${SVF}
#	${OPENOCD} -c "init; svf $<; exit"
#
#all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt  ${BUILD}/${PROJECT}.svf
#
clean:
	rm -rf db ${BUILD} *.orig *.bak incremental_db db

#
#
#
#
#
#

#tidy:
#	for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
#
#