From dafbdab96bcaf604ada97260fccefdd6aca60335 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 6 Aug 2025 05:59:30 +0100 Subject: merged a7 --- fpga/hp_lcd_driver/.gitignore | 4 + fpga/hp_lcd_driver/Makefile | 13 +- fpga/hp_lcd_driver/artix7.mk | 51 + fpga/hp_lcd_driver/artix7_config.tcl | 30 + fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl | 85 + fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl | 33 + fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl | 38 + fpga/hp_lcd_driver/artix7_ip/mmcm_1.tcl | 35 + fpga/hp_lcd_driver/clkgen_artix7.vhdl | 61 + fpga/hp_lcd_driver/hp_lcd_driver.vhdl | 71 +- fpga/hp_lcd_driver/input_formatter.vhdl | 51 +- fpga/hp_lcd_driver/input_stage.vhdl | 28 +- fpga/hp_lcd_driver/output_formatter.vhdl | 4 +- fpga/hp_lcd_driver/output_stage.vhdl | 14 +- fpga/hp_lcd_driver/prog_a7 | 4 + fpga/hp_lcd_driver/rando_a7.mk | 2 + fpga/hp_lcd_driver/rando_a7.tcl | 5 + fpga/hp_lcd_driver/rando_a7.xdc | 117 + fpga/hp_lcd_driver/scripts/vivado | 16 + fpga/hp_lcd_driver/tmds_output_artix7.vhdl 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fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/mig_b.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/ddr3.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/mig_b.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/ddr3.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/mig_b.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/run.f create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/cmd.tcl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/ddr3.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/elab.opt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/mig_b.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/vlog.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/xsim.ini create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/ddr_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/run.f create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/ddr_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/ddr_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/elaborate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/ddr_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/run.f create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/cmd.tcl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/ddr_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/elab.opt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/vlog.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/xsim.ini create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/sys_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/run.f create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/sys_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/elaborate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/sys_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/compile.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/sys_clk.udo create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/wave.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/simulate.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/run.f create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/README.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/cmd.tcl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/elab.opt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/file_info.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/glbl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/sys_clk.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/vlog.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core 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program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.xci create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.xml create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/datasheet.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/docs/phy_only_support_readme.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a100tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a15tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a50tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a75tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/example_top.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/readme.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/example_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_afifo.v create mode 100644 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board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_status.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_wr_data_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_write_data_path.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model.sv create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model_parameters.vh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ies_run.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/readme.txt create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim.do create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim_tb_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/vcs_run.sh create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/wiredly.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_files.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_options.tcl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_run.bat create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/mig.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a100tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a15tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a50tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a75tfgg484_pkg.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3_ooc.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ddr3.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ddr3_mig.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.vhdl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.vhdl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_xmdf.tcl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_a.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_b.prj create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.in create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.out create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/example_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_afifo.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_init_mem_pattern_ctr.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_flow_vcontrol.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_traffic_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_rd_data_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_data_path.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_s7ven_data_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_status.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_wr_data_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_write_data_path.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/io_test/io_test.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/led_ctrl/led_ctrl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/rst_ctrl/rst_ctrl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/ascii_code.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/device_temp_ascii_dis.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/reset_bridge.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_state.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_top.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_baud_gen.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx_ctl.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/xadc_temp/xadc_temp.v create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/debug_nets.ltx create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/top.bin create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/top.bit create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/top.mcs create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/top.prm create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/bitgen_compress.tcl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/write_cfgmem.tcl create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/debug.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/io_test.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/pin.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/timing.xdc create mode 100644 fpga/rando_a7/XC7A35T Artix7 core board/SCH/XILINX ARTIX-7 FPGA A704 V10 Schematics.pdf (limited to 'fpga') diff --git a/fpga/hp_lcd_driver/.gitignore b/fpga/hp_lcd_driver/.gitignore index d7fb5c6..4284f6d 100644 --- a/fpga/hp_lcd_driver/.gitignore +++ b/fpga/hp_lcd_driver/.gitignore @@ -1,5 +1,9 @@ build_spartan6/ build_smh-ac415/ build_smh-ac415b/ +build_rando_a7/ build_loader/ NOT/ +*.swp +*.lic +*.orig diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile index 4e2be26..e9f1df7 100644 --- a/fpga/hp_lcd_driver/Makefile +++ b/fpga/hp_lcd_driver/Makefile @@ -1,22 +1,19 @@ -TARGETS= smh-ac415b #spartan6 #ep4ce6 smh-ac415 +TARGETS= rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415 #fish:smh-ac415 default: ${TARGETS:%=build_%/hp_lcd_driver.svf} + + smh-ac415: build_smh-ac415/hp_lcd_driver.svf spartan6: build_spartan6/hp_lcd_driver.svf +rando_a7: build_rando_a7/out/hp_lcd_driver.bit + build_%/hp_lcd_driver.svf: dummy ${MAKE} -f ${@:build_%/hp_lcd_driver.svf=%}.mk -build_smh-ac415/hp_lcd_driver.svf: build_flash_loader/output_files/flash_loader.sof - -build_flash_loader/output_files/flash_loader.sof: dummy - ${MAKE} -f ep4ce15f23c8_loader.mk - - - clean: for i in ${TARGETS}; do ${MAKE} -f $$i.mk $@; done diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk new file mode 100644 index 0000000..578468c --- /dev/null +++ b/fpga/hp_lcd_driver/artix7.mk @@ -0,0 +1,51 @@ +BUILD=build_${BOARD} + +IP= \ + artix7_ip/blk_mem_gen_0.tcl \ + artix7_ip/mmcm_0.tcl \ + artix7_ip/mmcm_1.tcl + + +BIT=${BUILD}/out/hp_lcd_driver.bit + +IP_STAMP=${IP:artix7_ip/%.tcl=${BUILD}/ip/%/stamp} +SRCS= ${IP} \ + artix7_config.tcl \ + artix7_hp_lcd_driver.tcl \ + ${BOARD}.tcl \ + ${BOARD}.xdc \ + clkgen_artix7.vhdl \ + debounce.vhdl \ + delay.vhdl \ + edge_det.vhdl \ + hp_lcd_driver.vhdl \ + input_formatter.vhdl \ + input_stage.vhdl \ + output_analog.vhdl \ + output_formatter.vhdl \ + output_stage.vhdl \ + synchronizer.vhdl \ + tmds_encoder.vhdl \ + tmds_encode.vhdl \ + tmds_output_artix7.vhdl \ + tmds_phy_artix7.vhdl \ + vram_artix7.vhdl + + + +OPENOCD=openocd -f openocd/${BOARD}.cfg + +default: ${BUILD}/build.stamp + +${BUILD}/build.stamp:${SRCS} ${IP_STAMP} + mkdir -p ${BUILD} + (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../artix7_hp_lcd_driver.tcl) + touch $@ + +${BUILD}/ip/%/stamp:artix7_ip/%.tcl + mkdir -p ${BUILD}/ip + /bin/rm -rf $(dir $@) + (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@ + + +${BIT}: ${BUILD}/build.stamp diff --git a/fpga/hp_lcd_driver/artix7_config.tcl b/fpga/hp_lcd_driver/artix7_config.tcl new file mode 100644 index 0000000..d76719c --- /dev/null +++ b/fpga/hp_lcd_driver/artix7_config.tcl @@ -0,0 +1,30 @@ +# +set board $::env(BOARD) +set board_tcl $source_dir/$board.tcl +set build_dir . +set ip_dir $build_dir/ip +set bd_dir $build_dir/bd +set ipl_dir $build_dir/ip_library +set output_dir $build_dir/out +source $board_tcl +create_project -in_memory -part $part_num + +file mkdir $build_dir +file mkdir $bd_dir +file mkdir $ip_dir +file mkdir $ipl_dir +file mkdir $output_dir + +#WARNING: [Vivado 12-13651] The IP file '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0/mmcm_0.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +set_msg_config -id 12-13651 -suppress + + +#WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B has an input control pin vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B/ADDRBWRADDR[12] (net: vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[12]) which is driven by a register (output0/output_formatter/addr_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. +set_msg_config -id REQP-1839 -suppress + + + +#WARNING: [Synth 8-3848] Net dma_axi_awid in module/entity pcie_tpm_widget does not have driver. [/root/projects/tpm_interposer/logic_analyzer/source/pcie_tpm_widget.vhdl:88] +#set_msg_config -id 8-3848 -new_severity ERROR + + diff --git a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl new file mode 100644 index 0000000..684e493 --- /dev/null +++ b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl @@ -0,0 +1,85 @@ +# +set source_dir [file dirname [file normalize [info script]]] + +source $source_dir/artix7_config.tcl + +file mkdir $output_dir + +set files [glob -nocomplain "$output_dir/*"] +if {[llength $files] != 0} { + # clear folder contents + puts "deleting contents of $output_dir" + file delete -force {*}[glob -directory $output_dir *]; +} else { + puts "$output_dir is empty" +} + +#Reference HDL and constraint source files + +#read_xdc $early_xdc + +#read_verilog [ glob ../source/*.v ] +#read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ] +read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl } + +set generics {} +append generics { } "video_width=$video_width" +append generics { } "BOARD=\"$board\"" +append generics { } "use_pclk=$use_pclk" + +set_property generic "$generics" [current_fileset] +puts $generics + +read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci +read_ip $ip_dir/mmcm_0/mmcm_0.xci +read_ip $ip_dir/mmcm_1/mmcm_1.xci + +read_xdc $normal_xdc + +#Run Synthesis +synth_design -top hp_lcd_driver -part $part_num +write_checkpoint -force $output_dir/post_synth.dcp +report_timing_summary -file $output_dir/post_synth_timing_summary.rpt +report_utilization -file $output_dir/post_synth_util.rpt + +set crdl [get_param tcl.collectionResultDisplayLimit] +set_param tcl.collectionResultDisplayLimit 10000000 + +set f [open "$output_dir/cells.txt" w] +puts $f [get_cells -hierarchical] +close $f + +set f [open "$output_dir/nets.txt" w] +puts $f [get_nets -hierarchical] +close $f +set_param tcl.collectionResultDisplayLimit $crdl + +set f [open "$output_dir/pins.txt" w] +puts $f [get_pins -hierarchical] +close $f +set_param tcl.collectionResultDisplayLimit $crdl + +#run optimization +opt_design +place_design +report_clock_utilization -file $output_dir/clock_util.rpt + +#get timing violations and run optimizations if needed +if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} { + puts "Found setup timing violations => running physical optimization" + phys_opt_design +} +write_checkpoint -force $output_dir/post_place.dcp +report_utilization -file $output_dir/post_place_util.rpt +report_timing_summary -file $output_dir/post_place_timing_summary.rpt + +#Route design and generate bitstream +route_design -directive Explore +write_checkpoint -force $output_dir/post_route.dcp +report_route_status -file $output_dir/post_route_status.rpt +report_timing_summary -file $output_dir/post_route_timing_summary.rpt +report_power -file $output_dir/post_route_power.rpt +report_drc -file $output_dir/post_imp_drc.rpt +report_io -file $output_dir/post_imp_placed.rpt +write_verilog -force $output_dir/cpu_impl_netlist.v -mode timesim -sdf_anno true +write_bitstream -force $output_dir/hp_lcd_driver.bit diff --git a/fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl new file mode 100644 index 0000000..84626aa --- /dev/null +++ b/fpga/hp_lcd_driver/artix7_ip/blk_mem_gen_0.tcl @@ -0,0 +1,33 @@ + + +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/artix7_config.tcl + +create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_0 -dir $ip_dir + +set_property -dict [list \ + CONFIG.Memory_Type {Simple_Dual_Port_RAM} \ + CONFIG.Enable_32bit_Address {false} \ + CONFIG.Use_Byte_Write_Enable {false} \ + CONFIG.Byte_Size {9} \ + CONFIG.Write_Width_A {6} \ + CONFIG.Write_Depth_A {245760} \ + CONFIG.Read_Width_A {6} \ + CONFIG.Operating_Mode_A {NO_CHANGE} \ + CONFIG.Write_Width_B {6} \ + CONFIG.Read_Width_B {6} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \ + CONFIG.Use_RSTB_Pin {false} \ + CONFIG.Port_B_Clock {22} \ + CONFIG.Port_B_Enable_Rate {22} \ + CONFIG.Disable_Collision_Warnings {false} \ + CONFIG.EN_SAFETY_CKT {false} \ + ] [get_ips blk_mem_gen_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl b/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl new file mode 100644 index 0000000..a49c8f2 --- /dev/null +++ b/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl @@ -0,0 +1,38 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/artix7_config.tcl + +create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_0 -dir $ip_dir + +set_property -dict [list \ + CONFIG.PRIM_IN_FREQ {50} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {240} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {80} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {48} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {24} \ + CONFIG.CLKIN1_JITTER_PS {200.0} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {20.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {15} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {25} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {50} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {120.627} \ + CONFIG.CLKOUT1_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT2_JITTER {146.190} \ + CONFIG.CLKOUT2_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT3_JITTER {165.425} \ + CONFIG.CLKOUT3_PHASE_ERROR {154.678} \ + CONFIG.CLKOUT4_JITTER {202.151} \ + CONFIG.CLKOUT4_PHASE_ERROR {154.678} \ + ] [get_ips mmcm_0] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/artix7_ip/mmcm_1.tcl b/fpga/hp_lcd_driver/artix7_ip/mmcm_1.tcl new file mode 100644 index 0000000..eb2143d --- /dev/null +++ b/fpga/hp_lcd_driver/artix7_ip/mmcm_1.tcl @@ -0,0 +1,35 @@ +set source_dir [file dirname [file dirname [file normalize [info script]]]] + +source $source_dir/artix7_config.tcl + +create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name mmcm_1 -dir $ip_dir + +set_property -dict [list \ + CONFIG.PRIM_IN_FREQ {50} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT5_USED {false} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {78.571} \ + CONFIG.USE_SAFE_CLOCK_STARTUP {false} \ + CONFIG.CLKIN1_JITTER_PS {100.0} \ + CONFIG.CLKOUT1_DRIVES {BUFG} \ + CONFIG.CLKOUT2_DRIVES {BUFG} \ + CONFIG.CLKOUT3_DRIVES {BUFG} \ + CONFIG.CLKOUT4_DRIVES {BUFG} \ + CONFIG.CLKOUT5_DRIVES {BUFG} \ + CONFIG.CLKOUT6_DRIVES {BUFG} \ + CONFIG.CLKOUT7_DRIVES {BUFG} \ + CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {11.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {20.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {20.000} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {7} \ + CONFIG.NUM_OUT_CLKS {1} \ + ] [get_ips mmcm_1] + +generate_target all [get_ips] + +synth_ip [get_ips] + diff --git a/fpga/hp_lcd_driver/clkgen_artix7.vhdl b/fpga/hp_lcd_driver/clkgen_artix7.vhdl new file mode 100644 index 0000000..f7f8971 --- /dev/null +++ b/fpga/hp_lcd_driver/clkgen_artix7.vhdl @@ -0,0 +1,61 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; +use work.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity clkgen is + port ( + sys_rst_n : in std_logic; + clk_in : in std_logic; + i_clk : out std_logic; + o_clk : out std_logic; + o_clk_x2 : out std_logic; + o_clk_phy : out std_logic; + locked : out std_logic + ); +end clkgen; +architecture Behavioural of clkgen is + + signal clk_240m : std_logic; + signal clk_78_571m : std_logic; + signal clk_80m : std_logic; + signal clk_24m : std_logic; + signal clk_48m : std_logic; + signal clk_50m : std_logic; + + signal reset : std_logic; +begin + + reset <= not sys_rst_n; + + o_clk_buf : BUFG port map ( + I => clk_in, + O => clk_50m); + + + mmcm_0_i : mmcm_0 port map ( + clk_in1 => clk_50m, + clk_out1 => clk_240m, + clk_out2 => clk_80m, + clk_out3 => clk_48m, + clk_out4 => clk_24m, + reset => reset, + locked => locked + ); + + mmcm_1_i : mmcm_1 port map ( + clk_in1 => clk_50m, + clk_out1 => clk_78_571m, + reset => reset + ); + + o_clk_phy <= clk_240m; + o_clk <= clk_24m; + o_clk_x2 <= clk_48m; + i_clk <= clk_78_571m; + + +end Behavioural; diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl index 087e475..95a38a1 100644 --- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl @@ -15,12 +15,14 @@ entity hp_lcd_driver is addr_width : natural := 18; phase_slip : natural := 320; i_clk_multiple : natural := 4; - target : string := "spartan6"); + use_pclk : natural := 0; + target : string := "artix7"); port (clk_50m : in std_logic; sys_rst_n : in std_logic; - video : in std_logic_vector(video_width-1 downto 0); + video : in std_logic_vector(video_width -1 downto 0); hsync_in : in std_logic; vsync_in : in std_logic; + pclk_in : in std_logic; r_out : out std_logic; b_out : out std_logic; g_out : out std_logic; @@ -34,7 +36,9 @@ entity hp_lcd_driver is hdmi_g_n : out std_logic; hdmi_b_p : out std_logic; hdmi_b_n : out std_logic; - i_clk_out : out std_logic); + hdmi_vcc : out std_logic; + i_clk_out : out std_logic; + led : out std_logic); end hp_lcd_driver; @@ -70,6 +74,8 @@ architecture Behavioral of hp_lcd_driver is signal v : natural; + signal c : natural; + signal t : std_logic; begin @@ -146,12 +152,14 @@ begin frame_start => 383, h_stride => 384, v_stride => 524287, - phase_slip => phase_slip + phase_slip => phase_slip, + use_pclk => use_pclk ) port map ( sys_rst_n => sys_rst_n, clk => i_clk, video_in => video, + pclk_in => pclk_in, hsync_in => not hsync_in, vsync_in => not vsync_in, @@ -203,14 +211,18 @@ begin rd_data => rd_data ); - - r<=x"00"; - b<=x"00"; - g <= x"ff" when rd_data(1) = '1' else - x"80" when rd_data(0) = '1' else - x"00"; +-- r<=x"00"; +-- b<=x"00"; + + r <= rd_data(1 downto 0) & "000000"; + g <= rd_data(3 downto 2) & "000000"; + b <= rd_data(5 downto 4) & "000000"; + +--"ff" when rd_data(1) = '1' else +-- x"80" when rd_data(0) = '1' else +-- ix"00"; @@ -262,17 +274,20 @@ begin h_stride => 1, v_stride => 384 --- h_active => 800, --- h_sync_start => 832, --- h_sync_end => 912, --- h_total => 1024, --- v_active => 600, --- v_sync_start => 601, --- v_sync_end => 604, --- v_total => 622, --- h_stride => 1, --- v_stride => 384 +-- h_active => 640, +-- h_sync_start=>656, +-- h_sync_end =>752, +-- h_total=>800, +-- +-- v_active =>480, +-- v_sync_start=>490, +-- v_sync_end=>492, +-- v_total=>525, +-- h_stride=>1, +-- v_stride=>384 + ) + port map( clk_locked => clk_locked, clk => o_clk, @@ -299,6 +314,22 @@ begin hdmi_b_n => hdmi_b_n ); + process (clk_50m, c) + begin + if rising_edge(clk_50m) then + + if c < 19999999 then + c <=c+1; + else + c <=0; + t <=not t; + end if; + end if; + end process; + + + led <= t; + end Behavioral; diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl index f3bd434..35916f5 100644 --- a/fpga/hp_lcd_driver/input_formatter.vhdl +++ b/fpga/hp_lcd_driver/input_formatter.vhdl @@ -16,13 +16,16 @@ entity input_formatter is frame_start : natural := 0; h_stride : natural := 384; v_stride : natural := 1; - phase_slip : natural := 320); + phase_slip : natural := 320; + use_pclk : natural := 0 + ); port ( sys_rst_n : in std_logic; clk : in std_logic; hsync : in std_logic; vsync : in std_logic; + pclk : in std_logic; addr_out : out std_logic_vector(addr_width-1 downto 0); wren_out : out std_logic; h_grid : out std_logic; @@ -38,6 +41,9 @@ architecture beh of input_formatter is signal addr : std_logic_vector(addr_width-1 downto 0); signal wren : std_logic; + signal pclk_ne : std_logic; + signal pclk_pe : std_logic; + signal hsync_ne : std_logic; signal hsync_pe : std_logic; @@ -45,8 +51,8 @@ architecture beh of input_formatter is signal v_active_counter : natural; signal h_fp_counter : natural; signal h_active_counter : natural; - signal h_div : natural; + signal h_div : natural; signal phase_accum : natural; @@ -62,6 +68,14 @@ begin pe => hsync_pe); + pclk_ed : entity work.edge_det + port map( + clk => clk, + sig => pclk, + e => pclk_ne, + pe => pclk_pe); + + addr_out <= addr; @@ -77,7 +91,7 @@ begin h_fp_counter <= 0; v_active_counter <= 0; v_fp_counter <= 0; - phase_accum <= 0; + phase_accum <= phase_slip; elsif rising_edge(clk) then if hsync_pe = '1' then --if v_active_counter = 0 and v_fp_counter=0 then @@ -102,22 +116,27 @@ begin h_fp_counter <= h_fp_counter -1; elsif h_active_counter /= 0 then - if h_div = 0 then - wren <= '1'; - if phase_accum = 0 then - phase_accum <= phase_slip; - h_div <= clk_multiple; + if use_pclk = 0 then + if h_div = 0 then + wren <= '1'; + if phase_accum = 0 then + phase_accum <= phase_slip; + h_div <= clk_multiple; + else + phase_accum <= phase_accum-1; + h_div <= clk_multiple-1; + end if; else - phase_accum <= phase_accum-1; - h_div <= clk_multiple-1; + h_div <= h_div -1; + wren <= '0'; end if; else - if wren = '1' then - wren <= '0'; - h_active_counter <= h_active_counter -1; - addr <= std_logic_vector(unsigned(addr)+h_stride); - end if; - h_div <= h_div -1; + wren <= pclk_pe; + end if; + + if wren = '1' then + h_active_counter <= h_active_counter -1; + addr <= std_logic_vector(unsigned(addr)+h_stride); end if; end if; end if; diff --git a/fpga/hp_lcd_driver/input_stage.vhdl b/fpga/hp_lcd_driver/input_stage.vhdl index 9355a93..c124a59 100644 --- a/fpga/hp_lcd_driver/input_stage.vhdl +++ b/fpga/hp_lcd_driver/input_stage.vhdl @@ -16,7 +16,8 @@ entity input_stage is frame_start : natural := 0; h_stride : natural := 384; v_stride : natural := 1; - phase_slip : natural := 320); + phase_slip : natural := 320; + use_pclk : natural := 0); port ( clk : in std_logic; @@ -24,6 +25,7 @@ entity input_stage is video_in : in std_logic_vector(video_width -1 downto 0); + pclk_in : in std_logic; hsync_in : in std_logic; vsync_in : in std_logic; @@ -36,6 +38,9 @@ end input_stage; architecture beh of input_stage is + signal s_pclk : std_logic; + signal d_pclk : std_logic; + signal s_hsync : std_logic; signal d_hsync : std_logic; @@ -65,6 +70,13 @@ begin end generate; + pclk_sync : entity work.synchronizer + generic map(stages => sync_stages) + port map ( + clk => clk, + i => pclk_in, + o => s_pclk + ); hsync_sync : entity work.synchronizer generic map(stages => sync_stages) @@ -82,6 +94,14 @@ begin o => s_vsync ); + + pclk_debounce : entity work.debounce + generic map(stages => debounce_stages) + port map( + clk => clk, + i => s_pclk, + o => d_pclk); + hsync_debounce : entity work.debounce generic map(stages => debounce_stages) port map( @@ -89,8 +109,6 @@ begin i => s_hsync, o => d_hsync); - - vsync_debounce : entity work.debounce generic map(stages => debounce_stages) port map( @@ -112,10 +130,12 @@ begin frame_start => frame_start, h_stride => h_stride, v_stride => v_stride, - phase_slip => phase_slip) + phase_slip => phase_slip, + use_pclk => use_pclk) port map ( sys_rst_n => sys_rst_n, clk => clk, + pclk => d_pclk, hsync => d_hsync, vsync => d_vsync, addr_out => addr, diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl index 3e26515..558c222 100644 --- a/fpga/hp_lcd_driver/output_formatter.vhdl +++ b/fpga/hp_lcd_driver/output_formatter.vhdl @@ -124,11 +124,11 @@ begin h_grid <= '1' when (h mod 32) = 0 -- h_grid <= '1' when (h = 0) or (h = (h_active-1)) - else '0'; +else '0'; v_grid <= '1' when (v mod 32) = 0 -- v_grid <= '1' when (v = 0) or (v = (v_active-1)) - else '0'; +else '0'; addr_out <= addr; diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl index e02d8ce..56f4ae4 100644 --- a/fpga/hp_lcd_driver/output_stage.vhdl +++ b/fpga/hp_lcd_driver/output_stage.vhdl @@ -140,15 +140,17 @@ begin -- o => grid_d -- ); --- r <= r_in; + r <= r_in; g <= g_in; --- b <= b_in; + b <= b_in; - b<=x"00" when v_grid='0' - else x"ff"; - r<=x"00" when h_grid='0' - else x"ff"; + +-- b<=x"00" when v_grid='0' +-- else x"ff"; + +-- r<=x"00" when h_grid='0' +-- else x"ff"; -- b<=x"00" when v_grid='0' and h_grid='0' -- else x"ff"; diff --git a/fpga/hp_lcd_driver/prog_a7 b/fpga/hp_lcd_driver/prog_a7 new file mode 100755 index 0000000..c10ee8f --- /dev/null +++ b/fpga/hp_lcd_driver/prog_a7 @@ -0,0 +1,4 @@ +#!/bin/bash +BIT=./build-rando_a7/out/hp_lcd_driver.bit +../../openocd/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f cpld/xilinx-xc7.cfg -c init -c "pld load xc7.pld $BIT" -c shutdown + diff --git a/fpga/hp_lcd_driver/rando_a7.mk b/fpga/hp_lcd_driver/rando_a7.mk new file mode 100644 index 0000000..87a2ef4 --- /dev/null +++ b/fpga/hp_lcd_driver/rando_a7.mk @@ -0,0 +1,2 @@ +BOARD=rando_a7 +include artix7.mk diff --git a/fpga/hp_lcd_driver/rando_a7.tcl b/fpga/hp_lcd_driver/rando_a7.tcl new file mode 100644 index 0000000..cfaa74d --- /dev/null +++ b/fpga/hp_lcd_driver/rando_a7.tcl @@ -0,0 +1,5 @@ +# +set part_num "xc7a35tfgg484-2" +set normal_xdc "../rando_a7.xdc" +set use_pclk 1 +set video_width 6 diff --git a/fpga/hp_lcd_driver/rando_a7.xdc b/fpga/hp_lcd_driver/rando_a7.xdc new file mode 100644 index 0000000..04b2cac --- /dev/null +++ b/fpga/hp_lcd_driver/rando_a7.xdc @@ -0,0 +1,117 @@ +# "Normal" constraints file- not early not late + + +set_property IOSTANDARD LVCMOS33 [get_ports clk_50m] +set_property PACKAGE_PIN R4 [get_ports clk_50m] + +set_property PACKAGE_PIN U1 [get_ports {led}] +set_property IOSTANDARD LVCMOS33 [get_ports {led}] +#set_property PACKAGE_PIN T1 [get_ports {led_1}] +#set_property IOSTANDARD LVCMOS33 [get_ports {led_1}] + +set_property PACKAGE_PIN R3 [get_ports {hdmi_r_p}] +set_property PACKAGE_PIN R2 [get_ports {hdmi_r_n}] +set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}] +set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}] +set_property PACKAGE_PIN U3 [get_ports {hdmi_b_p}] +set_property PACKAGE_PIN V3 [get_ports {hdmi_b_n}] +set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}] +set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}] + +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}] + +#set_property DRIVE 16 [get_ports {hdmi_c_p}] +#set_property DRIVE 16 [get_ports {hdmi_c_n}] +#set_property DRIVE 16 [get_ports {hdmi_r_p}] +#set_property DRIVE 16 [get_ports {hdmi_r_n}] +#set_property DRIVE 16 [get_ports {hdmi_g_p}] +#set_property DRIVE 16 [get_ports {hdmi_g_n}] +#set_property DRIVE 16 [get_ports {hdmi_b_p}] + +set_property PACKAGE_PIN W1 [get_ports {hdmi_vcc}] +set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}] + + +#set_property PACKAGE_PIN P20 [get_ports rxd] +#set_property PACKAGE_PIN T20 [get_ports txd] +#set_property IOSTANDARD LVCMOS33 [get_ports rxd] +#set_property IOSTANDARD LVCMOS33 [get_ports txd] + +#set_property PACKAGE_PIN T3 [get_ports key] +#set_property IOSTANDARD LVCMOS33 [get_ports key] + +set_property PACKAGE_PIN N22 [get_ports {video[0]}] +set_property PACKAGE_PIN N20 [get_ports {video[1]}] +set_property PACKAGE_PIN N18 [get_ports {video[2]}] +set_property PACKAGE_PIN K18 [get_ports {video[3]}] +set_property PACKAGE_PIN M18 [get_ports {video[4]}] +set_property PACKAGE_PIN M15 [get_ports {video[5]}] +#set_property PACKAGE_PIN U20 [get_ports {video[6]}] +#set_property PACKAGE_PIN T21 [get_ports {video[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}] + +set_property PACKAGE_PIN W19 [get_ports {pclk_in}] +set_property PACKAGE_PIN R18 [get_ports {vsync_in}] +set_property PACKAGE_PIN Y18 [get_ports {hsync_in}] +set_property PACKAGE_PIN P16 [get_ports {r_out}] +set_property PACKAGE_PIN V18 [get_ports {g_out}] +set_property PACKAGE_PIN P15 [get_ports {b_out}] +set_property PACKAGE_PIN P14 [get_ports {i_clk_out}] +set_property PACKAGE_PIN V17 [get_ports {hsync_out}] +set_property PACKAGE_PIN N13 [get_ports {vsync_out}] +set_property PACKAGE_PIN N13 [get_ports {vsync_out}] + + +set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}] +set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}] +set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}] +set_property IOSTANDARD LVCMOS33 [get_ports {r_out}] +set_property IOSTANDARD LVCMOS33 [get_ports {g_out}] +set_property IOSTANDARD LVCMOS33 [get_ports {b_out}] +set_property IOSTANDARD LVCMOS33 [get_ports {i_clk_out}] +set_property IOSTANDARD LVCMOS33 [get_ports {hsync_out}] +set_property IOSTANDARD LVCMOS33 [get_ports {vsync_out}] + +set_property PACKAGE_PIN AA18 [get_ports {sys_rst_n}] +set_property IOSTANDARD LVCMOS33 [get_ports {sys_rst_n}] +set_property PULLTYPE PULLUP [get_ports {sys_rst_n}] + +create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m] +#set_false_path -from [get_ports pci_exp_rst_n] + + +############################################################################### +# Additional design / project settings +############################################################################### + +# Power down on overtemp +set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] + +# High-speed configuration so FPGA is up in time to negotiate with PCIe root complex +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + + + + diff --git a/fpga/hp_lcd_driver/scripts/vivado b/fpga/hp_lcd_driver/scripts/vivado new file mode 100755 index 0000000..0dbf03c --- /dev/null +++ b/fpga/hp_lcd_driver/scripts/vivado @@ -0,0 +1,16 @@ +#!/bin/bash +HS3_BIN=/home/DISTRIB/Xilinx/Digilent-HS3/foo +HS3_LIB=/home/DISTRIB/Xilinx/Digilent-HS3/foo +VIVADO=/software/apps/xilinx/Vivado/2022.1/ +VIVADO_BIN=${VIVADO}/bin +VIVADO_LIB=${VIVADO}/lib64 + +XILINXD_LICENSE_FILE=${PWD}/xilinx_ise_vivado_license.lic +export XILINXD_LICENSE_FILE + +export LD_LIBRARY_PATH + +PATH="${VIVADO_BIN}:${HS3_BIN}:$PATH" +LD_LIBRAY_PATH="${LD_LIBRARY_PATH}:/usr/lib64:/usr/lib:/lib64:/lib:${VIVADO_LIB}:${HS3_LIB}" + +exec ${VIVADO_BIN}/vivado $@ diff --git a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl new file mode 100644 index 0000000..7370bb7 --- /dev/null +++ b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl @@ -0,0 +1,115 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; + +library UNISIM; +use UNISIM.vcomponents.all; + + +entity tmds_output is + port ( + sys_rst_n : in std_logic; + pclk_locked : in std_logic; + pclk : in std_logic; + pclk_x2 : in std_logic; + pclk_phy : in std_logic; + + r_p10 : in std_logic_vector(9 downto 0); + g_p10 : in std_logic_vector(9 downto 0); + b_p10 : in std_logic_vector(9 downto 0); + c_p10 : in std_logic_vector(9 downto 0); + + + tmds_c_out_p : out std_logic; + tmds_c_out_n : out std_logic; + tmds_r_out_p : out std_logic; + tmds_r_out_n : out std_logic; + tmds_g_out_p : out std_logic; + tmds_g_out_n : out std_logic; + tmds_b_out_p : out std_logic; + tmds_b_out_n : out std_logic + ); +end tmds_output; + + +architecture beh of tmds_output is + + signal phy_reset : std_logic; + signal b : natural := 0; + + +begin + phy_reset <= not sys_rst_n; -- or not pll_locked; + + process (pclk_phy, b, sys_rst_n) + begin + if sys_rst_n = '0' then + b <= 0; + elsif rising_edge(pclk_phy) then + if b = 9 then + b <= 0; + else + b <= b+1; + end if; + end if; + end process; + + + phy_c : entity work.tmds_phy_artix7 + port map ( + reset => phy_reset, + pix_clk => pclk, + phy_clk => pclk_phy, + b =>b, + din => c_p10, + tmds_out_p => tmds_c_out_p, + tmds_out_n => tmds_c_out_n + ); + + phy_r : entity work.tmds_phy_artix7 + port map ( + reset => phy_reset, + pix_clk => pclk, + phy_clk => pclk_phy, + b =>b, + din => r_p10, + tmds_out_p => tmds_r_out_p, + tmds_out_n => tmds_r_out_n + ); + + + phy_g : entity work.tmds_phy_artix7 + port map ( + reset => phy_reset, + pix_clk => pclk, + phy_clk => pclk_phy, + b =>b, + din => g_p10, + tmds_out_p => tmds_g_out_p, + tmds_out_n => tmds_g_out_n + ); + + + phy_b : entity work.tmds_phy_artix7 + port map ( + reset => phy_reset, + pix_clk => pclk, + phy_clk => pclk_phy, + b =>b, + din => b_p10, + tmds_out_p => tmds_b_out_p, + tmds_out_n => tmds_b_out_n + ); + + +-- tmds_c_out_p <= '0'; +-- tmds_c_out_n <= '0'; +-- tmds_r_out_p <= '0'; +-- tmds_r_out_n <= '0'; +-- tmds_g_out_p <= '0'; +-- tmds_g_out_n <= '0'; +-- tmds_b_out_p <= '0'; +-- tmds_b_out_n <= '0'; +-- + +end beh; diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl new file mode 100644 index 0000000..8c8106e --- /dev/null +++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl @@ -0,0 +1,85 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; + +library UNISIM; +use UNISIM.vcomponents.all; + + +entity tmds_phy_artix7 is + port ( + reset : in std_logic; + pix_clk : in std_logic; + phy_clk : in std_logic; + din : in std_logic_vector(9 downto 0); + b : in natural; + tmds_out_p : out std_logic; + tmds_out_n : out std_logic + ); +end tmds_phy_artix7; + + +architecture beh of tmds_phy_artix7 is + + signal ld : std_logic_vector(9 downto 0); + signal sr : std_logic_vector(9 downto 0); + + signal s : std_logic; + +begin + + + process(pix_clk) + begin + if rising_edge(pix_clk) then + ld <= din; + end if; + end process; + + +-- Using ODDR +-- process(phy_clk) +-- begin +-- if rising_edge(phy_clk) then +-- if b=0 then +-- sr<= ld; +-- else +-- sr(7 downto 0) <= sr (9 downto 2); +-- end if; +-- end if; +-- end process; +-- +--ODDR_inst : ODDR +--generic map( +-- DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" +-- INIT => '0', -- Initial value for Q port ('1' or '0') +-- SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC") +--port map ( +-- Q => s, -- 1-bit DDR output +-- C => phy_clk, -- 1-bit clock input +-- CE => '1', -- 1-bit clock enable input +-- D1 => sr(0), -- 1-bit data input (positive edge) +-- D2 => sr(1), -- 1-bit data input (negative edge) +-- R => '0', -- 1-bit reset input +-- S => '0' -- 1-bit set input +--); + + +-- Using a shift register + process(phy_clk) + begin + if rising_edge(phy_clk) then + if b = 0 then + sr <= ld; + else + sr(8 downto 0) <= sr (9 downto 1); + s <=sr(0); + end if; + end if; + end process; + + + + od : OBUFDS port map (O => tmds_out_p, OB => tmds_out_n, I => s); + +end beh; diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl new file mode 100644 index 0000000..82186e1 --- /dev/null +++ b/fpga/hp_lcd_driver/vram_artix7.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity vram is + generic ( + addr_width : natural := 18; + video_width : natural := 6 + ); + port ( + wr_clk : in std_logic; + wr_en : in std_logic; + wr_addr : in std_logic_vector(addr_width-1 downto 0); + wr_data : in std_logic_vector(video_width-1 downto 0); + rd_clk : in std_logic; + rd_addr : in std_logic_vector(addr_width-1 downto 0); + rd_data : out std_logic_vector(video_width-1 downto 0) + ); +end vram; + +architecture beh of vram is + signal wr_en_v : std_logic_vector(0 downto 0); +begin + + wr_en_v(0) <= wr_en; + + bmg0 : entity work.blk_mem_gen_0 + port map ( + ena => '1', + enb => '1', + clka => wr_clk, + wea => wr_en_v, + addra => wr_addr, + dina => wr_data, + clkb => rd_clk, + doutb => rd_data, + addrb => rd_addr + ); +end beh; diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/A704 bottom view.pdf b/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/A704 bottom view.pdf new file mode 100644 index 0000000..af5e649 Binary files /dev/null and b/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/A704 bottom view.pdf differ diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/A704 top view.pdf b/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/A704 top view.pdf new file mode 100644 index 0000000..c5002f8 Binary files /dev/null and b/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/A704 top view.pdf differ diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/Xilinx Artix-7 FPGA A704 pcb outline.dxf b/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/Xilinx Artix-7 FPGA A704 pcb outline.dxf new file mode 100644 index 0000000..ea36579 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Dimensional diagram/Xilinx Artix-7 FPGA A704 pcb outline.dxf @@ -0,0 +1,196584 @@ + 0 +SECTION + 2 +HEADER + 9 +$ACADVER + 1 +AC1009 + 9 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tg_wr_data_counts[47:0] + tg_wr_data_counts[47:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + init_calib_complete + init_calib_complete + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + tg_compare_error + tg_compare_error + HEXRADIX + true + STYLE_DIGITAL + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb new file mode 100644 index 0000000..e713159 Binary files /dev/null and b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb differ diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.hw/top.lpr b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.hw/top.lpr new file mode 100644 index 0000000..e6450ba --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.hw/top.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/README.txt new file mode 100644 index 0000000..9015e04 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_sim_netlist.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_sim_netlist.v new file mode 100644 index 0000000..d42af3f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_sim_netlist.v @@ -0,0 +1,210 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Wed Feb 5 18:49:56 2025 +// Host : Win102023HEYRFQ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/ddr_clk_synth_1/ddr_clk_sim_netlist.v +// Design : ddr_clk +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tfgg484-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module ddr_clk + (ddr3_clk, + reset, + locked, + clk_in1); + output ddr3_clk; + input reset; + output locked; + input clk_in1; + + wire clk_in1; + wire ddr3_clk; + wire locked; + wire reset; + + ddr_clk_ddr_clk_clk_wiz inst + (.clk_in1(clk_in1), + .ddr3_clk(ddr3_clk), + .locked(locked), + .reset(reset)); +endmodule + +(* ORIG_REF_NAME = "ddr_clk_clk_wiz" *) +module ddr_clk_ddr_clk_clk_wiz + (ddr3_clk, + reset, + locked, + clk_in1); + output ddr3_clk; + input reset; + output locked; + input clk_in1; + + wire clk_in1; + wire clkfbout_buf_ddr_clk; + wire clkfbout_ddr_clk; + wire ddr3_clk; + wire ddr3_clk_ddr_clk; + wire locked; + wire reset; + wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; + wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_ddr_clk), + .O(clkfbout_buf_ddr_clk)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(ddr3_clk_ddr_clk), + .O(ddr3_clk)); + (* BOX_TYPE = "PRIMITIVE" *) + PLLE2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT(20), + .CLKFBOUT_PHASE(0.000000), + .CLKIN1_PERIOD(20.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE(3), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .STARTUP_WAIT("FALSE")) + plle2_adv_inst + (.CLKFBIN(clkfbout_buf_ddr_clk), + .CLKFBOUT(clkfbout_ddr_clk), + .CLKIN1(clk_in1), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKOUT0(ddr3_clk_ddr_clk), + .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PWRDWN(1'b0), + .RST(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_sim_netlist.vhdl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_sim_netlist.vhdl new file mode 100644 index 0000000..3dac718 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_sim_netlist.vhdl @@ -0,0 +1,136 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +-- Date : Wed Feb 5 18:49:56 2025 +-- Host : Win102023HEYRFQ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/ddr_clk_synth_1/ddr_clk_sim_netlist.vhdl +-- Design : ddr_clk +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7a35tfgg484-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr_clk_ddr_clk_clk_wiz is + port ( + ddr3_clk : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr_clk_ddr_clk_clk_wiz : entity is "ddr_clk_clk_wiz"; +end ddr_clk_ddr_clk_clk_wiz; + +architecture STRUCTURE of ddr_clk_ddr_clk_clk_wiz is + signal clkfbout_buf_ddr_clk : STD_LOGIC; + signal clkfbout_ddr_clk : STD_LOGIC; + signal ddr3_clk_ddr_clk : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_ddr_clk, + O => clkfbout_buf_ddr_clk + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => ddr3_clk_ddr_clk, + O => ddr3_clk + ); +plle2_adv_inst: unisim.vcomponents.PLLE2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT => 20, + CLKFBOUT_PHASE => 0.000000, + CLKIN1_PERIOD => 20.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE => 3, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT1_DIVIDE => 1, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + STARTUP_WAIT => "FALSE" + ) + port map ( + CLKFBIN => clkfbout_buf_ddr_clk, + CLKFBOUT => clkfbout_ddr_clk, + CLKIN1 => clk_in1, + CLKIN2 => '0', + CLKINSEL => '1', + CLKOUT0 => ddr3_clk_ddr_clk, + CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PWRDWN => '0', + RST => reset + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr_clk is + port ( + ddr3_clk : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of ddr_clk : entity is true; +end ddr_clk; + +architecture STRUCTURE of ddr_clk is +begin +inst: entity work.ddr_clk_ddr_clk_clk_wiz + port map ( + clk_in1 => clk_in1, + ddr3_clk => ddr3_clk, + locked => locked, + reset => reset + ); +end STRUCTURE; diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_stub.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_stub.v new file mode 100644 index 0000000..bb827e2 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Wed Feb 5 18:49:56 2025 +// Host : Win102023HEYRFQ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/ddr_clk_synth_1/ddr_clk_stub.v +// Design : ddr_clk +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tfgg484-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module ddr_clk(ddr3_clk, reset, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="ddr3_clk,reset,locked,clk_in1" */; + output ddr3_clk; + input reset; + output locked; + input clk_in1; +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_stub.vhdl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_stub.vhdl new file mode 100644 index 0000000..7ac357f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/ddr_clk/ddr_clk_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +-- Date : Wed Feb 5 18:49:56 2025 +-- Host : Win102023HEYRFQ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/ddr_clk_synth_1/ddr_clk_stub.vhdl +-- Design : ddr_clk +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tfgg484-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ddr_clk is + Port ( + ddr3_clk : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end ddr_clk; + +architecture stub of ddr_clk is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ddr3_clk,reset,locked,clk_in1"; +begin +end; diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_sim_netlist.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_sim_netlist.v new file mode 100644 index 0000000..65100c0 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_sim_netlist.v @@ -0,0 +1,269 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Wed Feb 5 18:49:56 2025 +// Host : Win102023HEYRFQ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/sys_clk_synth_1/sys_clk_sim_netlist.v +// Design : sys_clk +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a35tfgg484-2 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module sys_clk + (clk_200M, + clk_50M, + reset, + locked, + clk_in1); + output clk_200M; + output clk_50M; + input reset; + output locked; + input clk_in1; + + wire clk_200M; + wire clk_50M; + (* IBUF_LOW_PWR *) wire clk_in1; + wire locked; + wire reset; + + sys_clk_sys_clk_clk_wiz inst + (.clk_200M(clk_200M), + .clk_50M(clk_50M), + .clk_in1(clk_in1), + .locked(locked), + .reset(reset)); +endmodule + +(* ORIG_REF_NAME = "sys_clk_clk_wiz" *) +module sys_clk_sys_clk_clk_wiz + (clk_200M, + clk_50M, + reset, + locked, + clk_in1); + output clk_200M; + output clk_50M; + input reset; + output locked; + input clk_in1; + + wire clk_200M; + wire clk_200M_sys_clk; + wire clk_50M; + wire clk_50M_sys_clk; + wire clk_in1; + wire clk_in1_sys_clk; + wire clkfbout_buf_sys_clk; + wire clkfbout_sys_clk; + wire locked; + wire reset; + wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; + wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; + wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; + wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; + wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; + + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkf_buf + (.I(clkfbout_sys_clk), + .O(clkfbout_buf_sys_clk)); + (* BOX_TYPE = "PRIMITIVE" *) + (* CAPACITANCE = "DONT_CARE" *) + (* IBUF_DELAY_VALUE = "0" *) + (* IFD_DELAY_VALUE = "AUTO" *) + IBUF #( + .IOSTANDARD("DEFAULT")) + clkin1_ibufg + (.I(clk_in1), + .O(clk_in1_sys_clk)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout1_buf + (.I(clk_200M_sys_clk), + .O(clk_200M)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout2_buf + (.I(clk_50M_sys_clk), + .O(clk_50M)); + (* BOX_TYPE = "PRIMITIVE" *) + MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(20.000000), + .CLKFBOUT_PHASE(0.000000), + .CLKFBOUT_USE_FINE_PS("FALSE"), + .CLKIN1_PERIOD(20.000000), + .CLKIN2_PERIOD(0.000000), + .CLKOUT0_DIVIDE_F(5.000000), + .CLKOUT0_DUTY_CYCLE(0.500000), + .CLKOUT0_PHASE(0.000000), + .CLKOUT0_USE_FINE_PS("FALSE"), + .CLKOUT1_DIVIDE(20), + .CLKOUT1_DUTY_CYCLE(0.500000), + .CLKOUT1_PHASE(0.000000), + .CLKOUT1_USE_FINE_PS("FALSE"), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.500000), + .CLKOUT2_PHASE(0.000000), + .CLKOUT2_USE_FINE_PS("FALSE"), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.500000), + .CLKOUT3_PHASE(0.000000), + .CLKOUT3_USE_FINE_PS("FALSE"), + .CLKOUT4_CASCADE("FALSE"), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.500000), + .CLKOUT4_PHASE(0.000000), + .CLKOUT4_USE_FINE_PS("FALSE"), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.500000), + .CLKOUT5_PHASE(0.000000), + .CLKOUT5_USE_FINE_PS("FALSE"), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.500000), + .CLKOUT6_PHASE(0.000000), + .CLKOUT6_USE_FINE_PS("FALSE"), + .COMPENSATION("ZHOLD"), + .DIVCLK_DIVIDE(1), + .IS_CLKINSEL_INVERTED(1'b0), + .IS_PSEN_INVERTED(1'b0), + .IS_PSINCDEC_INVERTED(1'b0), + .IS_PWRDWN_INVERTED(1'b0), + .IS_RST_INVERTED(1'b0), + .REF_JITTER1(0.010000), + .REF_JITTER2(0.010000), + .SS_EN("FALSE"), + .SS_MODE("CENTER_HIGH"), + .SS_MOD_PERIOD(10000), + .STARTUP_WAIT("FALSE")) + mmcm_adv_inst + (.CLKFBIN(clkfbout_buf_sys_clk), + .CLKFBOUT(clkfbout_sys_clk), + .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), + .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), + .CLKIN1(clk_in1_sys_clk), + .CLKIN2(1'b0), + .CLKINSEL(1'b1), + .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), + .CLKOUT0(clk_200M_sys_clk), + .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), + .CLKOUT1(clk_50M_sys_clk), + .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), + .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), + .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), + .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), + .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), + .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), + .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), + .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), + .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DCLK(1'b0), + .DEN(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), + .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), + .DWE(1'b0), + .LOCKED(locked), + .PSCLK(1'b0), + .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(1'b0), + .RST(reset)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_sim_netlist.vhdl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_sim_netlist.vhdl new file mode 100644 index 0000000..9eb19e3 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_sim_netlist.vhdl @@ -0,0 +1,199 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +-- Date : Wed Feb 5 18:49:56 2025 +-- Host : Win102023HEYRFQ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/sys_clk_synth_1/sys_clk_sim_netlist.vhdl +-- Design : sys_clk +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7a35tfgg484-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity sys_clk_sys_clk_clk_wiz is + port ( + clk_200M : out STD_LOGIC; + clk_50M : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of sys_clk_sys_clk_clk_wiz : entity is "sys_clk_clk_wiz"; +end sys_clk_sys_clk_clk_wiz; + +architecture STRUCTURE of sys_clk_sys_clk_clk_wiz is + signal clk_200M_sys_clk : STD_LOGIC; + signal clk_50M_sys_clk : STD_LOGIC; + signal clk_in1_sys_clk : STD_LOGIC; + signal clkfbout_buf_sys_clk : STD_LOGIC; + signal clkfbout_sys_clk : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; + signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; + attribute IBUF_DELAY_VALUE : string; + attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; + attribute IFD_DELAY_VALUE : string; + attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; + attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; +begin +clkf_buf: unisim.vcomponents.BUFG + port map ( + I => clkfbout_sys_clk, + O => clkfbout_buf_sys_clk + ); +clkin1_ibufg: unisim.vcomponents.IBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => clk_in1, + O => clk_in1_sys_clk + ); +clkout1_buf: unisim.vcomponents.BUFG + port map ( + I => clk_200M_sys_clk, + O => clk_200M + ); +clkout2_buf: unisim.vcomponents.BUFG + port map ( + I => clk_50M_sys_clk, + O => clk_50M + ); +mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT_F => 20.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 20.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 5.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => false, + CLKOUT1_DIVIDE => 20, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "ZHOLD", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => clkfbout_buf_sys_clk, + CLKFBOUT => clkfbout_sys_clk, + CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, + CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, + CLKIN1 => clk_in1_sys_clk, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, + CLKOUT0 => clk_200M_sys_clk, + CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, + CLKOUT1 => clk_50M_sys_clk, + CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, + CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, + CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, + CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, + CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, + CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, + CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => locked, + PSCLK => '0', + PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => reset + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity sys_clk is + port ( + clk_200M : out STD_LOGIC; + clk_50M : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of sys_clk : entity is true; +end sys_clk; + +architecture STRUCTURE of sys_clk is +begin +inst: entity work.sys_clk_sys_clk_clk_wiz + port map ( + clk_200M => clk_200M, + clk_50M => clk_50M, + clk_in1 => clk_in1, + locked => locked, + reset => reset + ); +end STRUCTURE; diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_stub.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_stub.v new file mode 100644 index 0000000..78ec8cc --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_stub.v @@ -0,0 +1,23 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Wed Feb 5 18:49:56 2025 +// Host : Win102023HEYRFQ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/sys_clk_synth_1/sys_clk_stub.v +// Design : sys_clk +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tfgg484-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module sys_clk(clk_200M, clk_50M, reset, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_200M,clk_50M,reset,locked,clk_in1" */; + output clk_200M; + output clk_50M; + input reset; + output locked; + input clk_in1; +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_stub.vhdl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_stub.vhdl new file mode 100644 index 0000000..e07efdf --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/ip/sys_clk/sys_clk_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +-- Date : Wed Feb 5 18:49:56 2025 +-- Host : Win102023HEYRFQ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub +-- J:/work/HY/Xilinx/A704/V1.0/PRJ/Project/top.runs/sys_clk_synth_1/sys_clk_stub.vhdl +-- Design : sys_clk +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tfgg484-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity sys_clk is + Port ( + clk_200M : out STD_LOGIC; + clk_50M : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end sys_clk; + +architecture stub of sys_clk is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_200M,clk_50M,reset,locked,clk_in1"; +begin +end; diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/mem_init_files/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/mem_init_files/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/mem_init_files/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/README.txt new file mode 100644 index 0000000..3bf1c4a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/README.txt new file mode 100644 index 0000000..49fa92b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/compile.do new file mode 100644 index 0000000..68c6228 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/compile.do @@ -0,0 +1,14 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib + +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xil_defaultlib -v2k5 \ +"../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/ddr3.sh new file mode 100644 index 0000000..3c5cc94 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/ddr3.sh @@ -0,0 +1,154 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr3.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/ddr3.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/ddr3.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/simulate.do new file mode 100644 index 0000000..0484041 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+ddr3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ddr3 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ddr3.udo} + +run -all + +endsim + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/README.txt new file mode 100644 index 0000000..fb24027 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/ddr3.sh new file mode 100644 index 0000000..94173f6 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/ddr3.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr3.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ddr3 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/run.f b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/run.f new file mode 100644 index 0000000..9f8ff19 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/ies/run.f @@ -0,0 +1,7 @@ +-makelib ies_lib/xil_defaultlib \ + "../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/README.txt new file mode 100644 index 0000000..49fa92b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/compile.do new file mode 100644 index 0000000..a170314 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -incr \ +"../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/ddr3.sh new file mode 100644 index 0000000..1d169fc --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/ddr3.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr3.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/ddr3.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/ddr3.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/simulate.do new file mode 100644 index 0000000..411c6cb --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ddr3 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ddr3.udo} + +run -all + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/README.txt new file mode 100644 index 0000000..49fa92b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/compile.do new file mode 100644 index 0000000..2f8e82f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/compile.do @@ -0,0 +1,14 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib \ +"../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/ddr3.sh new file mode 100644 index 0000000..e1ba50f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/ddr3.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr3.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/ddr3.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/ddr3.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/elaborate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/elaborate.do new file mode 100644 index 0000000..8faa648 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/elaborate.do @@ -0,0 +1 @@ +vopt +acc=npr -l elaborate.log -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ddr3 xil_defaultlib.glbl -o ddr3_opt diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/simulate.do new file mode 100644 index 0000000..b76ea9e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib ddr3_opt + +do {wave.do} + +view wave +view structure +view signals + +do {ddr3.udo} + +run -all + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/README.txt new file mode 100644 index 0000000..49fa92b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/compile.do new file mode 100644 index 0000000..8a54d7d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/compile.do @@ -0,0 +1,14 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib + +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xil_defaultlib -v2k5 \ +"../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/ddr3.sh new file mode 100644 index 0000000..d529d48 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/ddr3.sh @@ -0,0 +1,154 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr3.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/ddr3.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/ddr3.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/simulate.do new file mode 100644 index 0000000..0484041 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+ddr3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ddr3 xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ddr3.udo} + +run -all + +endsim + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/README.txt new file mode 100644 index 0000000..49fa92b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/ddr3.sh new file mode 100644 index 0000000..2efd968 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/ddr3.sh @@ -0,0 +1,220 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr3.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.ddr3 xil_defaultlib.glbl -o ddr3_simv +} + +# RUN_STEP: +simulate() +{ + ./ddr3_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key ddr3_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ddr3_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/simulate.do new file mode 100644 index 0000000..a06099a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/README.txt new file mode 100644 index 0000000..fb24027 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/ddr3.sh new file mode 100644 index 0000000..e587e2c --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/ddr3.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr3.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ddr3 \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/run.f b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/run.f new file mode 100644 index 0000000..4626b0a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xcelium/run.f @@ -0,0 +1,7 @@ +-makelib xcelium_lib/xil_defaultlib \ + "../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/README.txt new file mode 100644 index 0000000..49fa92b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:06:09 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr3.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr3.sh' script. + +./ddr3.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr3.sh -noclean_files + +For more information on the script, please type './ddr3.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/cmd.tcl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/cmd.tcl new file mode 100644 index 0000000..05f1b4f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/ddr3.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/ddr3.sh new file mode 100644 index 0000000..1f1fd6b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/ddr3.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr3.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:06:09 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr3.sh [-help] +# usage: ddr3.sh [-lib_map_path] +# usage: ddr3.sh [-noclean_files] +# usage: ddr3.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=E:/Vivado/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ddr3.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ddr3 xil_defaultlib.ddr3 xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ddr3 -key {Behavioral:sim_1:Functional:ddr3} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="E:/Vivado/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr3.sh [-help]\n\ +Usage: ddr3.sh [-lib_map_path]\n\ +Usage: ddr3.sh [-reset_run]\n\ +Usage: ddr3.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/elab.opt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/elab.opt new file mode 100644 index 0000000..c4c011a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ddr3 xil_defaultlib.ddr3 xil_defaultlib.glbl -log elaborate.log diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/file_info.txt new file mode 100644 index 0000000..c566a02 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/file_info.txt @@ -0,0 +1,2 @@ +ddr3_sim_netlist.v,verilog,xil_defaultlib,../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/vlog.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/vlog.prj new file mode 100644 index 0000000..896847a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../../../RTL/ddr_ctrl/ddr3/ddr3_sim_netlist.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/xsim.ini b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/xsim.ini new file mode 100644 index 0000000..4467f0a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr3/xsim/xsim.ini @@ -0,0 +1,497 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +uvm=$RDI_DATADIR/xsim/system_verilog/uvm +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +axi_clock_converter_v2_1_21=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_21 +axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0 +xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4 +lte_fft_v2_0_20=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_20 +axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0 +noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +system_cache_v5_0_3=$RDI_DATADIR/xsim/ip/system_cache_v5_0_3 +rld3_pl_v1_0_4=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_4 +ernic_v3_0_0=$RDI_DATADIR/xsim/ip/ernic_v3_0_0 +xfft_v9_1_5=$RDI_DATADIR/xsim/ip/xfft_v9_1_5 +pr_axi_shutdown_manager_v1_0_2=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_2 +axi_dwidth_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_22 +shell_utils_addr_remap_v1_0_1=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_1 +v_hdmi_rx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_0 +ieee802d3_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_18 +mult_gen_v12_0_16=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_16 +processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6 +noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0 +axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1 +lib_bmg_v1_0_13=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_13 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +cordic_v6_0_16=$RDI_DATADIR/xsim/ip/cordic_v6_0_16 +tmr_sem_v1_0_15=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_15 +axis_dwidth_converter_v1_1_21=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_21 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16 +axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +v_tpg_v8_1_0=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_0 +c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +axis_switch_v1_1_22=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_22 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8 +v_letterbox_v1_1_0=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_0 +high_speed_selectio_wiz_v3_6_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_1 +axi_chip2chip_v5_0_9=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_9 +v_demosaic_v1_1_0=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_0 +v_multi_scaler_v1_2_0=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_0 +ieee802d3_200g_rs_fec_v2_0_0=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_0 +axi_memory_init_v1_0_3=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_3 +high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +axis_interconnect_v1_1_18=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_18 +cmac_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_v2_6_2 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +axi_pcie_v2_9_4=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_4 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0 +v_axi4s_remap_v1_0_14=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_14 +system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 +axi_vfifo_ctrl_v2_0_24=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_24 +ernic_v1_0_2=$RDI_DATADIR/xsim/ip/ernic_v1_0_2 +multi_channel_25g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_11 +oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2 +mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +v_axi4s_vid_out_v4_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_11 +v_letterbox_v1_0_16=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_16 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_traffic_gen_v2_0_23=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_23 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +lte_rach_detector_v3_1_8=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_8 +lte_fft_v2_1_3=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_3 +g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9 +lte_3gpp_channel_estimator_v2_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_17 +g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +axi_perf_mon_v5_0_24=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_24 +axi_timebase_wdt_v3_0_14=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_14 +fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 +g709_fec_v2_4_2=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_2 +v_scenechange_v1_0_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_4 +displayport_v8_1_3=$RDI_DATADIR/xsim/ip/displayport_v8_1_3 +spdif_v2_0_23=$RDI_DATADIR/xsim/ip/spdif_v2_0_23 +dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1 +noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0 +sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +axi_mmu_v2_1_20=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_20 +nvmeha_v1_0_3=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_3 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +v_gamma_lut_v1_0_8=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_8 +axi_traffic_gen_v3_0_8=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_8 +tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4 +axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +rama_v1_1_7_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_7_lib +trace_s2mm_v1_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_0_0 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +v_mix_v5_1_0=$RDI_DATADIR/xsim/ip/v_mix_v5_1_0 +dft_v4_2_1=$RDI_DATADIR/xsim/ip/dft_v4_2_1 +ta_dma_v1_0_6=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_6 +blk_mem_gen_v8_4_4=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_4 +axi_ethernet_buffer_v2_0_23=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_23 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +lte_3gpp_mimo_decoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_16 +ieee802d3_50g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_6 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +axi_sg_v4_1_13=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_13 +v_hdmi_tx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_0 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +v_tc_v6_2_1=$RDI_DATADIR/xsim/ip/v_tc_v6_2_1 +noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +qdriv_pl_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_2 +axi_uart16550_v2_0_24=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_24 +microblaze_v11_0_4=$RDI_DATADIR/xsim/ip/microblaze_v11_0_4 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +mdm_v3_2_19=$RDI_DATADIR/xsim/ip/mdm_v3_2_19 +versal_cips_ps_vip_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_0 +v_hcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_16 +lte_3gpp_mimo_encoder_v4_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_15 +axis_clock_converter_v1_1_23=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_23 +v_scenechange_v1_1_0=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_0 +mpegtsmux_v1_0_2=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_0_2 +axi_sideband_util_v1_0_6=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_6 +dsp_macro_v1_0_1=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_1 +ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0 +sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0 +gtwizard_ultrascale_v1_7_9=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_9 +vid_phy_controller_v2_1_9=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_9 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +canfd_v3_0_1=$RDI_DATADIR/xsim/ip/canfd_v3_0_1 +axis_broadcaster_v1_1_21=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_21 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +pr_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_2 +amm_axi_bridge_v1_0_8=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_8 +canfd_v2_0_4=$RDI_DATADIR/xsim/ip/canfd_v2_0_4 +polar_v1_0_6=$RDI_DATADIR/xsim/ip/polar_v1_0_6 +can_v5_0_25=$RDI_DATADIR/xsim/ip/can_v5_0_25 +axi_timer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_24 +jesd204_v7_2_10=$RDI_DATADIR/xsim/ip/jesd204_v7_2_10 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_firewall_v1_1_1=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_1 +v_axi4s_remap_v1_1_0=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_0 +adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +dfx_controller_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_1 +cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15 +processing_system7_vip_v1_0_10=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_10 +axi_intc_v4_1_15=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_15 +audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2 +axi_protocol_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_22 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +versal_cips_v2_1_0=$RDI_DATADIR/xsim/ip/versal_cips_v2_1_0 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +v_hscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_0 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +pcie_dma_versal_v2_0_1=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_1 +v_tpg_v8_0_4=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_4 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12 +pr_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_9 +axi_bram_ctrl_v4_1_4=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_4 +fc32_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_16 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +axi_register_slice_v2_1_22=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_22 +dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +gig_ethernet_pcs_pma_v16_2_1=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_1 +sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0 +ddr4_pl_v1_0_3=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_3 +axi_vdma_v6_3_10=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_10 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +axi_emc_v3_0_22=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_22 +jesd204c_v4_2_3=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_3 +axi_epc_v2_0_25=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_25 +gig_ethernet_pcs_pma_v16_1_9=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_9 +v_vscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_0 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +usxgmii_v1_2_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_0 +ieee802d3_400g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_11 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +v_frmbuf_rd_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_0 +ieee802d3_25g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_18 +ethernet_1_10_25g_v2_6_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_6_0 +v_frmbuf_wr_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_0 +tmr_manager_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_6 +trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0 +axi_iic_v2_0_25=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_25 +pc_cfr_v6_4_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_0 +v_tpg_v7_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_16 +lmb_bram_if_cntlr_v4_0_19=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_19 +v_vcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_16 +axi_ethernetlite_v3_0_21=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_21 +ldpc_v2_0_6=$RDI_DATADIR/xsim/ip/ldpc_v2_0_6 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +v_mix_v5_0_1=$RDI_DATADIR/xsim/ip/v_mix_v5_0_1 +audio_formatter_v1_0_4=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_4 +flexo_100g_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_16 +uram_rd_back_v1_0_1=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_1 +ptp_1588_timer_syncer_v1_0_1=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_1 +ieee802d3_clause74_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_8 +axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 +etrnic_v1_1_3=$RDI_DATADIR/xsim/ip/etrnic_v1_1_3 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +axi_gpio_v2_0_24=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_24 +dfx_decoupler_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_1 +tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16 +axi_ahblite_bridge_v3_0_19=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_19 +in_system_ibert_v1_0_12=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_12 +axis_register_slice_v1_1_22=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_22 +util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +axi_cdma_v4_1_22=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_22 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +v_hcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_0 +sid_v8_0_15=$RDI_DATADIR/xsim/ip/sid_v8_0_15 +ahblite_axi_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_17 +zynq_ultra_ps_e_v3_3_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_3 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +axi4svideo_bridge_v1_0_11=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_11 +xbip_multadd_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_15 +axis_data_fifo_v1_1_23=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_23 +c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +axis_data_fifo_v2_0_4=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_4 +rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17 +i2s_receiver_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_4 +perf_axi_tg_v1_0_11=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_11 +interlaken_v2_4_7=$RDI_DATADIR/xsim/ip/interlaken_v2_4_7 +xfft_v7_2_11=$RDI_DATADIR/xsim/ip/xfft_v7_2_11 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +g709_fec_v2_3_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_6 +axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0 +tsn_endpoint_ethernet_mac_block_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_7 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +v_uhdsdi_audio_v2_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_3 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +lte_dl_channel_encoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_16 +axi_dma_v7_1_23=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_23 +emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2 +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +axi_mm2s_mapper_v1_1_21=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_21 +tcc_encoder_3gpp_v5_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_16 +av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0 +srio_gen2_v4_1_9=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_9 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +ten_gig_eth_mac_v15_1_9=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_9 +dfx_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_0 +displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0 +v_vcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_0 +axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1 +l_ethernet_v3_2_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_2_0 +xxv_ethernet_v3_3_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_3_0 +xpm=$RDI_DATADIR/xsim/ip/xpm +nvme_tc_v2_0_0=$RDI_DATADIR/xsim/ip/nvme_tc_v2_0_0 +ieee802d3_200g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_11 +ats_switch_v1_0_3=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_3 +axi_data_fifo_v2_1_21=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_21 +zynq_ultra_ps_e_vip_v1_0_8=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_8 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +floating_point_v7_0_18=$RDI_DATADIR/xsim/ip/floating_point_v7_0_18 +v_smpte_uhdsdi_v1_0_8=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_8 +axis_vio_v1_0_2=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_2 +ieee802d3_rs_fec_v2_0_10=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_10 +lte_ul_channel_decoder_v4_0_17=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_17 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +aes_v1_1_2=$RDI_DATADIR/xsim/ip/aes_v1_1_2 +div_gen_v5_1_17=$RDI_DATADIR/xsim/ip/div_gen_v5_1_17 +v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9 +lte_dl_channel_encoder_v4_0_2=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_2 +tcc_decoder_3gppmm_v2_0_20=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_20 +axis_protocol_checker_v2_0_6=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_6 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +advanced_io_wizard_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_3 +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +xpm_cdc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_0 +mailbox_v2_1_14=$RDI_DATADIR/xsim/ip/mailbox_v2_1_14 +uhdsdi_gt_v2_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_3 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +v_vid_gt_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_1 +tri_mode_ethernet_mac_v9_0_17=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_17 +axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0 +dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +pc_cfr_v6_3_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_2 +gmii_to_rgmii_v4_1_0=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_0 +ernic_v2_0_0=$RDI_DATADIR/xsim/ip/ernic_v2_0_0 +accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_pcie3_v3_0_13=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_13 +v_uhdsdi_audio_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_1 +v_dp_axi4s_vid_out_v1_0_1=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_1 +axi_mcdma_v1_1_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_3 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +v_frmbuf_rd_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_5 +v_frmbuf_wr_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_5 +axi_crossbar_v2_1_23=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_23 +qdma_v4_0_2=$RDI_DATADIR/xsim/ip/qdma_v4_0_2 +v_hdmi_phy1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_2 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0 +ten_gig_eth_pcs_pma_v6_0_18=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_18 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_protocol_checker_v2_0_8=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_8 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +ba317=$RDI_DATADIR/xsim/ip/ba317 +xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0 +high_speed_selectio_wiz_v3_5_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_2 +quadsgmii_v3_5_0=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_0 +vby1hs_v1_0_0=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_0 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +vid_phy_controller_v2_2_7=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_7 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +fir_compiler_v7_2_15=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_15 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +hdmi_gt_controller_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_3 +oran_radio_if_v1_1_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v1_1_0 +v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +trace_s2mm_v1_1_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_1_0 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +lte_pucch_receiver_v2_0_18=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_18 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +v_csc_v1_0_16=$RDI_DATADIR/xsim/ip/v_csc_v1_0_16 +ieee802d3_50g_rs_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_14 +emb_mem_gen_v1_0_3=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_3 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +mem_tg_v1_0_3=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_3 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +dds_compiler_v6_0_20=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_20 +icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0 +axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0 +i2s_transmitter_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_4 +axi_hbicap_v1_0_3=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_3 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +picxo=$RDI_DATADIR/xsim/ip/picxo +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14 +axi_uartlite_v2_0_26=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_26 +axi_fifo_mm_s_v4_2_4=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_4 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3 +axi_interconnect_v1_7_18=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_18 +v_hscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_16 +v_vscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_16 +g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7 +tmr_comparator_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_4 +mipi_dphy_v4_3_0=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_0 +prc_v1_3_4=$RDI_DATADIR/xsim/ip/prc_v1_3_4 +fifo_generator_v13_2_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_5 +iomodule_v3_1_6=$RDI_DATADIR/xsim/ip/iomodule_v3_1_6 +axi4stream_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_8 +v_deinterlacer_v5_0_16=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_16 +axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0 +axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +axi_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_8 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +axi_datamover_v5_1_24=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_24 +v_gamma_lut_v1_1_0=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_0 +axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0 +axi_quad_spi_v3_2_21=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_21 +sim_trig_v1_0_4=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_4 +axis_combiner_v1_1_20=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_20 +displayport_v9_0_3=$RDI_DATADIR/xsim/ip/displayport_v9_0_3 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +compact_gt_v1_0_8=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_8 +zynq_ultra_ps_e_v3_2_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_6 +axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0 +xhmc_v1_0_12=$RDI_DATADIR/xsim/ip/xhmc_v1_0_12 +lib_fifo_v1_0_14=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_14 +cpri_v8_11_5=$RDI_DATADIR/xsim/ip/cpri_v8_11_5 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +tsn_temac_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_5 +video_frame_crc_v1_0_3=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_3 +axi_amm_bridge_v1_0_12=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_12 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0 +floating_point_v7_1_11=$RDI_DATADIR/xsim/ip/floating_point_v7_1_11 +axi_tft_v2_0_23=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_23 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +v_demosaic_v1_0_8=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_8 +roe_framer_v3_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_1 +c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +xbip_dsp48_macro_v3_0_18=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_18 +axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0 +axi_usb2_device_v5_0_23=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_23 +axi_hwicap_v3_0_26=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_26 +axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +sd_fec_v1_1_6=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_6 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +xfft_v9_0_19=$RDI_DATADIR/xsim/ip/xfft_v9_0_19 +etrnic_v1_0_4=$RDI_DATADIR/xsim/ip/etrnic_v1_0_4 +mpegtsmux_v1_1_0=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_0 +lmb_v10_v3_0_11=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_11 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +axi_mcdma_v1_0_8=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_8 +ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7 +sem_ultra_v3_1_16=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_16 +pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1 +cmac_usplus_v3_1_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_2 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +ieee802d3_400g_rs_fec_v2_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_2 +switch_core_top_v1_0_8=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_8 +v_multi_scaler_v1_0_4=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_4 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +axis_subset_converter_v1_1_22=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_22 +axi_msg_v1_0_6=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_6 +axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0 +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +axi_fifo_mm_s_v4_1_19=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_19 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +xdma_v4_1_8=$RDI_DATADIR/xsim/ip/xdma_v4_1_8 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +v_csc_v1_1_0=$RDI_DATADIR/xsim/ip/v_csc_v1_1_0 +vfb_v1_0_16=$RDI_DATADIR/xsim/ip/vfb_v1_0_16 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +axi_firewall_v1_0_10=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_10 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +cmpy_v6_0_19=$RDI_DATADIR/xsim/ip/cmpy_v6_0_19 +mrmac_v1_3_0=$RDI_DATADIR/xsim/ip/mrmac_v1_3_0 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +an_lt_v1_0_1=$RDI_DATADIR/xsim/ip/an_lt_v1_0_1 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/README.txt new file mode 100644 index 0000000..3bf1c4a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/README.txt new file mode 100644 index 0000000..8abb4e9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/compile.do new file mode 100644 index 0000000..7f4cb35 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 "+incdir+../../../ip/ddr_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ddr_clk" \ +"../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/ddr_clk.sh new file mode 100644 index 0000000..876dc29 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/ddr_clk.sh @@ -0,0 +1,154 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/ddr_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/ddr_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/file_info.txt new file mode 100644 index 0000000..aa3a217 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ddr_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ddr_clk" +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/simulate.do new file mode 100644 index 0000000..30fdfc4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+ddr_clk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ddr_clk xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ddr_clk.udo} + +run -all + +endsim + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/README.txt new file mode 100644 index 0000000..3185754 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/ddr_clk.sh new file mode 100644 index 0000000..ff94c1c --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/ddr_clk.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ddr_clk \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ddr_clk" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/file_info.txt new file mode 100644 index 0000000..aa3a217 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ddr_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ddr_clk" +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/run.f b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/run.f new file mode 100644 index 0000000..171777a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/ies/run.f @@ -0,0 +1,13 @@ +-makelib ies_lib/xpm -sv \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib ies_lib/xpm \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/README.txt new file mode 100644 index 0000000..8abb4e9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/compile.do new file mode 100644 index 0000000..957d165 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -incr -sv "+incdir+../../../ip/ddr_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -incr "+incdir+../../../ip/ddr_clk" \ +"../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/ddr_clk.sh new file mode 100644 index 0000000..3b95cd5 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/ddr_clk.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/ddr_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/ddr_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/file_info.txt new file mode 100644 index 0000000..aa3a217 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ddr_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ddr_clk" +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/simulate.do new file mode 100644 index 0000000..648f152 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ddr_clk xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ddr_clk.udo} + +run -all + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/README.txt new file mode 100644 index 0000000..8abb4e9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/compile.do new file mode 100644 index 0000000..e58c9c0 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -sv "+incdir+../../../ip/ddr_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib "+incdir+../../../ip/ddr_clk" \ +"../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/ddr_clk.sh new file mode 100644 index 0000000..e7ad1d5 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/ddr_clk.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/ddr_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/ddr_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/elaborate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/elaborate.do new file mode 100644 index 0000000..ea8ae59 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/elaborate.do @@ -0,0 +1 @@ +vopt +acc=npr -l elaborate.log -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ddr_clk xil_defaultlib.glbl -o ddr_clk_opt diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/file_info.txt new file mode 100644 index 0000000..aa3a217 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ddr_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ddr_clk" +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/simulate.do new file mode 100644 index 0000000..88b8965 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib ddr_clk_opt + +do {wave.do} + +view wave +view structure +view signals + +do {ddr_clk.udo} + +run -all + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/README.txt new file mode 100644 index 0000000..8abb4e9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/compile.do new file mode 100644 index 0000000..18dd077 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 "+incdir+../../../ip/ddr_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ddr_clk" \ +"../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/ddr_clk.sh new file mode 100644 index 0000000..1409ea4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/ddr_clk.sh @@ -0,0 +1,154 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/ddr_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/ddr_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/file_info.txt new file mode 100644 index 0000000..aa3a217 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ddr_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ddr_clk" +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/simulate.do new file mode 100644 index 0000000..30fdfc4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+ddr_clk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ddr_clk xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ddr_clk.udo} + +run -all + +endsim + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/README.txt new file mode 100644 index 0000000..8abb4e9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/ddr_clk.sh new file mode 100644 index 0000000..0468f8e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/ddr_clk.sh @@ -0,0 +1,228 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/ddr_clk" \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ddr_clk" \ + "$ref_dir/../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.ddr_clk xil_defaultlib.glbl -o ddr_clk_simv +} + +# RUN_STEP: +simulate() +{ + ./ddr_clk_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key ddr_clk_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ddr_clk_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/file_info.txt new file mode 100644 index 0000000..aa3a217 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ddr_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ddr_clk" +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/simulate.do new file mode 100644 index 0000000..a06099a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/README.txt new file mode 100644 index 0000000..3185754 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/ddr_clk.sh new file mode 100644 index 0000000..522d12a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/ddr_clk.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ddr_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ddr_clk \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ddr_clk" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/file_info.txt new file mode 100644 index 0000000..aa3a217 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ddr_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ddr_clk" +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/run.f b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/run.f new file mode 100644 index 0000000..8ee0100 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xcelium/run.f @@ -0,0 +1,13 @@ +-makelib xcelium_lib/xpm -sv \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/README.txt new file mode 100644 index 0000000..8abb4e9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:42 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ddr_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ddr_clk.sh' script. + +./ddr_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ddr_clk.sh -noclean_files + +For more information on the script, please type './ddr_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/cmd.tcl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/cmd.tcl new file mode 100644 index 0000000..05f1b4f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/ddr_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/ddr_clk.sh new file mode 100644 index 0000000..163eb23 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/ddr_clk.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : ddr_clk.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:42 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: ddr_clk.sh [-help] +# usage: ddr_clk.sh [-lib_map_path] +# usage: ddr_clk.sh [-noclean_files] +# usage: ddr_clk.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=E:/Vivado/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ddr_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ddr_clk xil_defaultlib.ddr_clk xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ddr_clk -key {Behavioral:sim_1:Functional:ddr_clk} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="E:/Vivado/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr_clk.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ddr_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ddr_clk.sh [-help]\n\ +Usage: ddr_clk.sh [-lib_map_path]\n\ +Usage: ddr_clk.sh [-reset_run]\n\ +Usage: ddr_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/elab.opt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/elab.opt new file mode 100644 index 0000000..df61ae3 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ddr_clk xil_defaultlib.ddr_clk xil_defaultlib.glbl -log elaborate.log diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/file_info.txt new file mode 100644 index 0000000..3f88792 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/file_info.txt @@ -0,0 +1,2 @@ +ddr_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/ddr_clk/ddr_clk_sim_netlist.v,incdir="../../../ip/ddr_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/vlog.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/vlog.prj new file mode 100644 index 0000000..7e35736 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/ddr_clk" \ +"../../../ip/ddr_clk/ddr_clk_sim_netlist.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/xsim.ini b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/xsim.ini new file mode 100644 index 0000000..4467f0a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/ddr_clk/xsim/xsim.ini @@ -0,0 +1,497 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +uvm=$RDI_DATADIR/xsim/system_verilog/uvm +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +axi_clock_converter_v2_1_21=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_21 +axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0 +xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4 +lte_fft_v2_0_20=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_20 +axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0 +noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +system_cache_v5_0_3=$RDI_DATADIR/xsim/ip/system_cache_v5_0_3 +rld3_pl_v1_0_4=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_4 +ernic_v3_0_0=$RDI_DATADIR/xsim/ip/ernic_v3_0_0 +xfft_v9_1_5=$RDI_DATADIR/xsim/ip/xfft_v9_1_5 +pr_axi_shutdown_manager_v1_0_2=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_2 +axi_dwidth_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_22 +shell_utils_addr_remap_v1_0_1=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_1 +v_hdmi_rx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_0 +ieee802d3_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_18 +mult_gen_v12_0_16=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_16 +processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6 +noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0 +axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1 +lib_bmg_v1_0_13=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_13 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +cordic_v6_0_16=$RDI_DATADIR/xsim/ip/cordic_v6_0_16 +tmr_sem_v1_0_15=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_15 +axis_dwidth_converter_v1_1_21=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_21 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16 +axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +v_tpg_v8_1_0=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_0 +c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +axis_switch_v1_1_22=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_22 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8 +v_letterbox_v1_1_0=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_0 +high_speed_selectio_wiz_v3_6_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_1 +axi_chip2chip_v5_0_9=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_9 +v_demosaic_v1_1_0=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_0 +v_multi_scaler_v1_2_0=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_0 +ieee802d3_200g_rs_fec_v2_0_0=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_0 +axi_memory_init_v1_0_3=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_3 +high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +axis_interconnect_v1_1_18=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_18 +cmac_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_v2_6_2 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +axi_pcie_v2_9_4=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_4 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0 +v_axi4s_remap_v1_0_14=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_14 +system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 +axi_vfifo_ctrl_v2_0_24=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_24 +ernic_v1_0_2=$RDI_DATADIR/xsim/ip/ernic_v1_0_2 +multi_channel_25g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_11 +oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2 +mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +v_axi4s_vid_out_v4_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_11 +v_letterbox_v1_0_16=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_16 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_traffic_gen_v2_0_23=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_23 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +lte_rach_detector_v3_1_8=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_8 +lte_fft_v2_1_3=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_3 +g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9 +lte_3gpp_channel_estimator_v2_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_17 +g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +axi_perf_mon_v5_0_24=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_24 +axi_timebase_wdt_v3_0_14=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_14 +fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 +g709_fec_v2_4_2=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_2 +v_scenechange_v1_0_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_4 +displayport_v8_1_3=$RDI_DATADIR/xsim/ip/displayport_v8_1_3 +spdif_v2_0_23=$RDI_DATADIR/xsim/ip/spdif_v2_0_23 +dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1 +noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0 +sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +axi_mmu_v2_1_20=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_20 +nvmeha_v1_0_3=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_3 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +v_gamma_lut_v1_0_8=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_8 +axi_traffic_gen_v3_0_8=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_8 +tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4 +axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +rama_v1_1_7_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_7_lib +trace_s2mm_v1_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_0_0 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +v_mix_v5_1_0=$RDI_DATADIR/xsim/ip/v_mix_v5_1_0 +dft_v4_2_1=$RDI_DATADIR/xsim/ip/dft_v4_2_1 +ta_dma_v1_0_6=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_6 +blk_mem_gen_v8_4_4=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_4 +axi_ethernet_buffer_v2_0_23=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_23 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +lte_3gpp_mimo_decoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_16 +ieee802d3_50g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_6 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +axi_sg_v4_1_13=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_13 +v_hdmi_tx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_0 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +v_tc_v6_2_1=$RDI_DATADIR/xsim/ip/v_tc_v6_2_1 +noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +qdriv_pl_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_2 +axi_uart16550_v2_0_24=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_24 +microblaze_v11_0_4=$RDI_DATADIR/xsim/ip/microblaze_v11_0_4 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +mdm_v3_2_19=$RDI_DATADIR/xsim/ip/mdm_v3_2_19 +versal_cips_ps_vip_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_0 +v_hcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_16 +lte_3gpp_mimo_encoder_v4_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_15 +axis_clock_converter_v1_1_23=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_23 +v_scenechange_v1_1_0=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_0 +mpegtsmux_v1_0_2=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_0_2 +axi_sideband_util_v1_0_6=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_6 +dsp_macro_v1_0_1=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_1 +ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0 +sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0 +gtwizard_ultrascale_v1_7_9=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_9 +vid_phy_controller_v2_1_9=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_9 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +canfd_v3_0_1=$RDI_DATADIR/xsim/ip/canfd_v3_0_1 +axis_broadcaster_v1_1_21=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_21 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +pr_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_2 +amm_axi_bridge_v1_0_8=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_8 +canfd_v2_0_4=$RDI_DATADIR/xsim/ip/canfd_v2_0_4 +polar_v1_0_6=$RDI_DATADIR/xsim/ip/polar_v1_0_6 +can_v5_0_25=$RDI_DATADIR/xsim/ip/can_v5_0_25 +axi_timer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_24 +jesd204_v7_2_10=$RDI_DATADIR/xsim/ip/jesd204_v7_2_10 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_firewall_v1_1_1=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_1 +v_axi4s_remap_v1_1_0=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_0 +adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +dfx_controller_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_1 +cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15 +processing_system7_vip_v1_0_10=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_10 +axi_intc_v4_1_15=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_15 +audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2 +axi_protocol_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_22 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +versal_cips_v2_1_0=$RDI_DATADIR/xsim/ip/versal_cips_v2_1_0 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +v_hscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_0 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +pcie_dma_versal_v2_0_1=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_1 +v_tpg_v8_0_4=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_4 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12 +pr_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_9 +axi_bram_ctrl_v4_1_4=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_4 +fc32_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_16 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +axi_register_slice_v2_1_22=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_22 +dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +gig_ethernet_pcs_pma_v16_2_1=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_1 +sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0 +ddr4_pl_v1_0_3=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_3 +axi_vdma_v6_3_10=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_10 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +axi_emc_v3_0_22=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_22 +jesd204c_v4_2_3=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_3 +axi_epc_v2_0_25=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_25 +gig_ethernet_pcs_pma_v16_1_9=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_9 +v_vscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_0 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +usxgmii_v1_2_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_0 +ieee802d3_400g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_11 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +v_frmbuf_rd_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_0 +ieee802d3_25g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_18 +ethernet_1_10_25g_v2_6_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_6_0 +v_frmbuf_wr_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_0 +tmr_manager_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_6 +trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0 +axi_iic_v2_0_25=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_25 +pc_cfr_v6_4_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_0 +v_tpg_v7_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_16 +lmb_bram_if_cntlr_v4_0_19=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_19 +v_vcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_16 +axi_ethernetlite_v3_0_21=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_21 +ldpc_v2_0_6=$RDI_DATADIR/xsim/ip/ldpc_v2_0_6 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +v_mix_v5_0_1=$RDI_DATADIR/xsim/ip/v_mix_v5_0_1 +audio_formatter_v1_0_4=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_4 +flexo_100g_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_16 +uram_rd_back_v1_0_1=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_1 +ptp_1588_timer_syncer_v1_0_1=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_1 +ieee802d3_clause74_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_8 +axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 +etrnic_v1_1_3=$RDI_DATADIR/xsim/ip/etrnic_v1_1_3 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +axi_gpio_v2_0_24=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_24 +dfx_decoupler_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_1 +tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16 +axi_ahblite_bridge_v3_0_19=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_19 +in_system_ibert_v1_0_12=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_12 +axis_register_slice_v1_1_22=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_22 +util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +axi_cdma_v4_1_22=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_22 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +v_hcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_0 +sid_v8_0_15=$RDI_DATADIR/xsim/ip/sid_v8_0_15 +ahblite_axi_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_17 +zynq_ultra_ps_e_v3_3_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_3 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +axi4svideo_bridge_v1_0_11=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_11 +xbip_multadd_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_15 +axis_data_fifo_v1_1_23=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_23 +c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +axis_data_fifo_v2_0_4=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_4 +rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17 +i2s_receiver_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_4 +perf_axi_tg_v1_0_11=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_11 +interlaken_v2_4_7=$RDI_DATADIR/xsim/ip/interlaken_v2_4_7 +xfft_v7_2_11=$RDI_DATADIR/xsim/ip/xfft_v7_2_11 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +g709_fec_v2_3_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_6 +axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0 +tsn_endpoint_ethernet_mac_block_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_7 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +v_uhdsdi_audio_v2_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_3 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +lte_dl_channel_encoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_16 +axi_dma_v7_1_23=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_23 +emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2 +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +axi_mm2s_mapper_v1_1_21=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_21 +tcc_encoder_3gpp_v5_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_16 +av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0 +srio_gen2_v4_1_9=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_9 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +ten_gig_eth_mac_v15_1_9=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_9 +dfx_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_0 +displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0 +v_vcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_0 +axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1 +l_ethernet_v3_2_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_2_0 +xxv_ethernet_v3_3_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_3_0 +xpm=$RDI_DATADIR/xsim/ip/xpm +nvme_tc_v2_0_0=$RDI_DATADIR/xsim/ip/nvme_tc_v2_0_0 +ieee802d3_200g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_11 +ats_switch_v1_0_3=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_3 +axi_data_fifo_v2_1_21=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_21 +zynq_ultra_ps_e_vip_v1_0_8=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_8 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +floating_point_v7_0_18=$RDI_DATADIR/xsim/ip/floating_point_v7_0_18 +v_smpte_uhdsdi_v1_0_8=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_8 +axis_vio_v1_0_2=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_2 +ieee802d3_rs_fec_v2_0_10=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_10 +lte_ul_channel_decoder_v4_0_17=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_17 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +aes_v1_1_2=$RDI_DATADIR/xsim/ip/aes_v1_1_2 +div_gen_v5_1_17=$RDI_DATADIR/xsim/ip/div_gen_v5_1_17 +v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9 +lte_dl_channel_encoder_v4_0_2=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_2 +tcc_decoder_3gppmm_v2_0_20=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_20 +axis_protocol_checker_v2_0_6=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_6 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +advanced_io_wizard_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_3 +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +xpm_cdc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_0 +mailbox_v2_1_14=$RDI_DATADIR/xsim/ip/mailbox_v2_1_14 +uhdsdi_gt_v2_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_3 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +v_vid_gt_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_1 +tri_mode_ethernet_mac_v9_0_17=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_17 +axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0 +dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +pc_cfr_v6_3_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_2 +gmii_to_rgmii_v4_1_0=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_0 +ernic_v2_0_0=$RDI_DATADIR/xsim/ip/ernic_v2_0_0 +accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_pcie3_v3_0_13=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_13 +v_uhdsdi_audio_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_1 +v_dp_axi4s_vid_out_v1_0_1=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_1 +axi_mcdma_v1_1_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_3 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +v_frmbuf_rd_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_5 +v_frmbuf_wr_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_5 +axi_crossbar_v2_1_23=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_23 +qdma_v4_0_2=$RDI_DATADIR/xsim/ip/qdma_v4_0_2 +v_hdmi_phy1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_2 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0 +ten_gig_eth_pcs_pma_v6_0_18=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_18 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_protocol_checker_v2_0_8=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_8 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +ba317=$RDI_DATADIR/xsim/ip/ba317 +xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0 +high_speed_selectio_wiz_v3_5_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_2 +quadsgmii_v3_5_0=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_0 +vby1hs_v1_0_0=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_0 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +vid_phy_controller_v2_2_7=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_7 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +fir_compiler_v7_2_15=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_15 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +hdmi_gt_controller_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_3 +oran_radio_if_v1_1_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v1_1_0 +v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +trace_s2mm_v1_1_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_1_0 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +lte_pucch_receiver_v2_0_18=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_18 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +v_csc_v1_0_16=$RDI_DATADIR/xsim/ip/v_csc_v1_0_16 +ieee802d3_50g_rs_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_14 +emb_mem_gen_v1_0_3=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_3 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +mem_tg_v1_0_3=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_3 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +dds_compiler_v6_0_20=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_20 +icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0 +axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0 +i2s_transmitter_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_4 +axi_hbicap_v1_0_3=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_3 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +picxo=$RDI_DATADIR/xsim/ip/picxo +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14 +axi_uartlite_v2_0_26=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_26 +axi_fifo_mm_s_v4_2_4=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_4 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3 +axi_interconnect_v1_7_18=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_18 +v_hscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_16 +v_vscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_16 +g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7 +tmr_comparator_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_4 +mipi_dphy_v4_3_0=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_0 +prc_v1_3_4=$RDI_DATADIR/xsim/ip/prc_v1_3_4 +fifo_generator_v13_2_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_5 +iomodule_v3_1_6=$RDI_DATADIR/xsim/ip/iomodule_v3_1_6 +axi4stream_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_8 +v_deinterlacer_v5_0_16=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_16 +axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0 +axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +axi_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_8 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +axi_datamover_v5_1_24=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_24 +v_gamma_lut_v1_1_0=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_0 +axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0 +axi_quad_spi_v3_2_21=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_21 +sim_trig_v1_0_4=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_4 +axis_combiner_v1_1_20=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_20 +displayport_v9_0_3=$RDI_DATADIR/xsim/ip/displayport_v9_0_3 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +compact_gt_v1_0_8=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_8 +zynq_ultra_ps_e_v3_2_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_6 +axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0 +xhmc_v1_0_12=$RDI_DATADIR/xsim/ip/xhmc_v1_0_12 +lib_fifo_v1_0_14=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_14 +cpri_v8_11_5=$RDI_DATADIR/xsim/ip/cpri_v8_11_5 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +tsn_temac_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_5 +video_frame_crc_v1_0_3=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_3 +axi_amm_bridge_v1_0_12=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_12 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0 +floating_point_v7_1_11=$RDI_DATADIR/xsim/ip/floating_point_v7_1_11 +axi_tft_v2_0_23=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_23 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +v_demosaic_v1_0_8=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_8 +roe_framer_v3_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_1 +c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +xbip_dsp48_macro_v3_0_18=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_18 +axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0 +axi_usb2_device_v5_0_23=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_23 +axi_hwicap_v3_0_26=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_26 +axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +sd_fec_v1_1_6=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_6 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +xfft_v9_0_19=$RDI_DATADIR/xsim/ip/xfft_v9_0_19 +etrnic_v1_0_4=$RDI_DATADIR/xsim/ip/etrnic_v1_0_4 +mpegtsmux_v1_1_0=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_0 +lmb_v10_v3_0_11=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_11 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +axi_mcdma_v1_0_8=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_8 +ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7 +sem_ultra_v3_1_16=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_16 +pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1 +cmac_usplus_v3_1_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_2 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +ieee802d3_400g_rs_fec_v2_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_2 +switch_core_top_v1_0_8=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_8 +v_multi_scaler_v1_0_4=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_4 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +axis_subset_converter_v1_1_22=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_22 +axi_msg_v1_0_6=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_6 +axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0 +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +axi_fifo_mm_s_v4_1_19=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_19 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +xdma_v4_1_8=$RDI_DATADIR/xsim/ip/xdma_v4_1_8 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +v_csc_v1_1_0=$RDI_DATADIR/xsim/ip/v_csc_v1_1_0 +vfb_v1_0_16=$RDI_DATADIR/xsim/ip/vfb_v1_0_16 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +axi_firewall_v1_0_10=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_10 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +cmpy_v6_0_19=$RDI_DATADIR/xsim/ip/cmpy_v6_0_19 +mrmac_v1_3_0=$RDI_DATADIR/xsim/ip/mrmac_v1_3_0 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +an_lt_v1_0_1=$RDI_DATADIR/xsim/ip/an_lt_v1_0_1 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/README.txt new file mode 100644 index 0000000..3bf1c4a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/README.txt new file mode 100644 index 0000000..83681c8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/compile.do new file mode 100644 index 0000000..5c83102 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xpm +vlib activehdl/xil_defaultlib + +vmap xpm activehdl/xpm +vmap xil_defaultlib activehdl/xil_defaultlib + +vlog -work xpm -sv2k12 "+incdir+../../../ip/sys_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/sys_clk" \ +"../../../ip/sys_clk/sys_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/file_info.txt new file mode 100644 index 0000000..58f776f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/sys_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/sys_clk" +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/simulate.do new file mode 100644 index 0000000..7bf1d93 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+sys_clk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.sys_clk xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {sys_clk.udo} + +run -all + +endsim + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/sys_clk.sh new file mode 100644 index 0000000..2641279 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/sys_clk.sh @@ -0,0 +1,154 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sys_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/sys_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/sys_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/README.txt new file mode 100644 index 0000000..5077a41 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/file_info.txt new file mode 100644 index 0000000..58f776f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/sys_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/sys_clk" +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/run.f b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/run.f new file mode 100644 index 0000000..093c6ba --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/run.f @@ -0,0 +1,13 @@ +-makelib ies_lib/xpm -sv \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib ies_lib/xpm \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/sys_clk/sys_clk_sim_netlist.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/sys_clk.sh new file mode 100644 index 0000000..a8f2e77 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/ies/sys_clk.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sys_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.sys_clk \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/sys_clk" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/README.txt new file mode 100644 index 0000000..83681c8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/compile.do new file mode 100644 index 0000000..29f0d51 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/xil_defaultlib + +vmap xpm modelsim_lib/msim/xpm +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xpm -incr -sv "+incdir+../../../ip/sys_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -incr "+incdir+../../../ip/sys_clk" \ +"../../../ip/sys_clk/sys_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/file_info.txt new file mode 100644 index 0000000..58f776f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/sys_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/sys_clk" +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/simulate.do new file mode 100644 index 0000000..814296a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.sys_clk xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {sys_clk.udo} + +run -all + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/sys_clk.sh new file mode 100644 index 0000000..2053401 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/sys_clk.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sys_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/sys_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/sys_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/README.txt new file mode 100644 index 0000000..83681c8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/compile.do new file mode 100644 index 0000000..acdca3c --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xil_defaultlib + +vmap xpm questa_lib/msim/xpm +vmap xil_defaultlib questa_lib/msim/xil_defaultlib + +vlog -work xpm -sv "+incdir+../../../ip/sys_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib "+incdir+../../../ip/sys_clk" \ +"../../../ip/sys_clk/sys_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/elaborate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/elaborate.do new file mode 100644 index 0000000..6935db7 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/elaborate.do @@ -0,0 +1 @@ +vopt +acc=npr -l elaborate.log -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.sys_clk xil_defaultlib.glbl -o sys_clk_opt diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/file_info.txt new file mode 100644 index 0000000..58f776f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/sys_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/sys_clk" +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/simulate.do new file mode 100644 index 0000000..9935c6f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -lib xil_defaultlib sys_clk_opt + +do {wave.do} + +view wave +view structure +view signals + +do {sys_clk.udo} + +run -all + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/sys_clk.sh new file mode 100644 index 0000000..496fe16 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/sys_clk.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sys_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/sys_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/sys_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/README.txt new file mode 100644 index 0000000..83681c8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/compile.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/compile.do new file mode 100644 index 0000000..563ecec --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xpm +vlib riviera/xil_defaultlib + +vmap xpm riviera/xpm +vmap xil_defaultlib riviera/xil_defaultlib + +vlog -work xpm -sv2k12 "+incdir+../../../ip/sys_clk" \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + +vcom -work xpm -93 \ +"E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/sys_clk" \ +"../../../ip/sys_clk/sys_clk_sim_netlist.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/file_info.txt new file mode 100644 index 0000000..58f776f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/sys_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/sys_clk" +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/simulate.do new file mode 100644 index 0000000..7bf1d93 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim +access +r +m+sys_clk -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.sys_clk xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {sys_clk.udo} + +run -all + +endsim + +quit -force diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/sys_clk.sh new file mode 100644 index 0000000..236f807 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/sys_clk.sh @@ -0,0 +1,154 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sys_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/sys_clk.udo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/sys_clk.udo new file mode 100644 index 0000000..e69de29 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/wave.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/wave.do new file mode 100644 index 0000000..d682cd4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/README.txt new file mode 100644 index 0000000..83681c8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/file_info.txt new file mode 100644 index 0000000..58f776f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/sys_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/sys_clk" +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/simulate.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/simulate.do new file mode 100644 index 0000000..a06099a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/sys_clk.sh new file mode 100644 index 0000000..029058c --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/vcs/sys_clk.sh @@ -0,0 +1,228 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sys_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xpm xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/sys_clk" \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/sys_clk" \ + "$ref_dir/../../../ip/sys_clk/sys_clk_sim_netlist.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.sys_clk xil_defaultlib.glbl -o sys_clk_simv +} + +# RUN_STEP: +simulate() +{ + ./sys_clk_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key sys_clk_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc sys_clk_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/README.txt new file mode 100644 index 0000000..5077a41 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/file_info.txt new file mode 100644 index 0000000..58f776f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/file_info.txt @@ -0,0 +1,4 @@ +xpm_cdc.sv,systemverilog,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/sys_clk" +xpm_VCOMP.vhd,vhdl,xpm,E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/sys_clk" +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/run.f b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/run.f new file mode 100644 index 0000000..546ace9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/run.f @@ -0,0 +1,13 @@ +-makelib xcelium_lib/xpm -sv \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "E:/Vivado/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/sys_clk/sys_clk_sim_netlist.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/sys_clk.sh new file mode 100644 index 0000000..7a39f6a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xcelium/sys_clk.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sys_clk.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xpm xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.sys_clk \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/sys_clk" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/README.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/README.txt new file mode 100644 index 0000000..83681c8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2020.2 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Wed Feb 05 19:07:50 +0800 2025 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sys_clk.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sys_clk.sh' script. + +./sys_clk.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sys_clk.sh -noclean_files + +For more information on the script, please type './sys_clk.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/cmd.tcl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/cmd.tcl new file mode 100644 index 0000000..05f1b4f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/elab.opt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/elab.opt new file mode 100644 index 0000000..2914e6e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/elab.opt @@ -0,0 +1 @@ +--relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sys_clk xil_defaultlib.sys_clk xil_defaultlib.glbl -log elaborate.log diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/file_info.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/file_info.txt new file mode 100644 index 0000000..796bb7e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/file_info.txt @@ -0,0 +1,2 @@ +sys_clk_sim_netlist.v,verilog,xil_defaultlib,../../../ip/sys_clk/sys_clk_sim_netlist.v,incdir="../../../ip/sys_clk" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/glbl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/sys_clk.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/sys_clk.sh new file mode 100644 index 0000000..07d6992 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/sys_clk.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2020.2 (64-bit) +# +# Filename : sys_clk.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Wed Feb 05 19:07:50 +0800 2025 +# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 +# +# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +# +# usage: sys_clk.sh [-help] +# usage: sys_clk.sh [-lib_map_path] +# usage: sys_clk.sh [-noclean_files] +# usage: sys_clk.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=E:/Vivado/Vivado/2020.2/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "sys_clk.sh - Script generated by export_simulation (Vivado v2020.2 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sys_clk xil_defaultlib.sys_clk xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim sys_clk -key {Behavioral:sim_1:Functional:sys_clk} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="E:/Vivado/Vivado/2020.2/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb sys_clk.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sys_clk.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sys_clk.sh [-help]\n\ +Usage: sys_clk.sh [-lib_map_path]\n\ +Usage: sys_clk.sh [-reset_run]\n\ +Usage: sys_clk.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/vlog.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/vlog.prj new file mode 100644 index 0000000..133f5df --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/sys_clk" \ +"../../../ip/sys_clk/sys_clk_sim_netlist.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/xsim.ini b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/xsim.ini new file mode 100644 index 0000000..4467f0a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.ip_user_files/sim_scripts/sys_clk/xsim/xsim.ini @@ -0,0 +1,497 @@ +std=$RDI_DATADIR/xsim/vhdl/std +ieee=$RDI_DATADIR/xsim/vhdl/ieee +ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed +vl=$RDI_DATADIR/xsim/vhdl/vl +synopsys=$RDI_DATADIR/xsim/vhdl/synopsys +uvm=$RDI_DATADIR/xsim/system_verilog/uvm +secureip=$RDI_DATADIR/xsim/verilog/secureip +unisim=$RDI_DATADIR/xsim/vhdl/unisim +unimacro=$RDI_DATADIR/xsim/vhdl/unimacro +unifast=$RDI_DATADIR/xsim/vhdl/unifast +unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver +unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver +unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver +simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver +axi_clock_converter_v2_1_21=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_21 +axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0 +xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4 +lte_fft_v2_0_20=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_20 +axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0 +noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0 +lut_buffer_v1_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v1_0_0 +system_cache_v5_0_3=$RDI_DATADIR/xsim/ip/system_cache_v5_0_3 +rld3_pl_v1_0_4=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_4 +ernic_v3_0_0=$RDI_DATADIR/xsim/ip/ernic_v3_0_0 +xfft_v9_1_5=$RDI_DATADIR/xsim/ip/xfft_v9_1_5 +pr_axi_shutdown_manager_v1_0_2=$RDI_DATADIR/xsim/ip/pr_axi_shutdown_manager_v1_0_2 +axi_dwidth_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_22 +shell_utils_addr_remap_v1_0_1=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_1 +v_hdmi_rx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_0 +ieee802d3_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v1_0_18 +mult_gen_v12_0_16=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_16 +processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6 +noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0 +axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1 +lib_bmg_v1_0_13=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_13 +xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6 +cordic_v6_0_16=$RDI_DATADIR/xsim/ip/cordic_v6_0_16 +tmr_sem_v1_0_15=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_15 +axis_dwidth_converter_v1_1_21=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_21 +xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2 +xtlm=$RDI_DATADIR/xsim/ip/xtlm +rs_encoder_v9_0_16=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_16 +axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0 +v_uhdsdi_audio_v1_1_0=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_1_0 +v_tpg_v8_1_0=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_0 +c_counter_binary_v12_0_14=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_14 +common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1 +axis_switch_v1_1_22=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_22 +rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1 +rs_toolbox_v9_0_8=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_8 +v_letterbox_v1_1_0=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_0 +high_speed_selectio_wiz_v3_6_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_1 +axi_chip2chip_v5_0_9=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_9 +v_demosaic_v1_1_0=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_0 +v_multi_scaler_v1_2_0=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_0 +ieee802d3_200g_rs_fec_v2_0_0=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_0 +axi_memory_init_v1_0_3=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_3 +high_speed_selectio_wiz_v3_4_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_4_1 +duc_ddc_compiler_v3_0_15=$RDI_DATADIR/xsim/ip/duc_ddc_compiler_v3_0_15 +ai_noc=$RDI_DATADIR/xsim/ip/ai_noc +bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0 +ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13 +axis_interconnect_v1_1_18=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_18 +cmac_v2_6_2=$RDI_DATADIR/xsim/ip/cmac_v2_6_2 +high_speed_selectio_wiz_v3_3_1=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_3_1 +axi_pcie_v2_9_4=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_4 +rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0 +sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0 +v_axi4s_remap_v1_0_14=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_14 +system_cache_v4_0_6=$RDI_DATADIR/xsim/ip/system_cache_v4_0_6 +axi_vfifo_ctrl_v2_0_24=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_24 +ernic_v1_0_2=$RDI_DATADIR/xsim/ip/ernic_v1_0_2 +multi_channel_25g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_11 +oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2 +mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0 +fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10 +v_axi4s_vid_out_v4_0_11=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_11 +v_letterbox_v1_0_16=$RDI_DATADIR/xsim/ip/v_letterbox_v1_0_16 +clk_gen_sim_v1_0_0=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_0 +lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0 +axi_traffic_gen_v2_0_23=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v2_0_23 +gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux +lte_rach_detector_v3_1_8=$RDI_DATADIR/xsim/ip/lte_rach_detector_v3_1_8 +lte_fft_v2_1_3=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_3 +g709_rs_decoder_v2_2_9=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_9 +lte_3gpp_channel_estimator_v2_0_17=$RDI_DATADIR/xsim/ip/lte_3gpp_channel_estimator_v2_0_17 +g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18 +stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0 +xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6 +axi_perf_mon_v5_0_24=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_24 +axi_timebase_wdt_v3_0_14=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_14 +fec_5g_common_v1_0_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_0_1 +g709_fec_v2_4_2=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_2 +v_scenechange_v1_0_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_0_4 +displayport_v8_1_3=$RDI_DATADIR/xsim/ip/displayport_v8_1_3 +spdif_v2_0_23=$RDI_DATADIR/xsim/ip/spdif_v2_0_23 +dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1 +noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0 +sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13 +gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4 +axi_mmu_v2_1_20=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_20 +nvmeha_v1_0_3=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_3 +v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9 +v_gamma_lut_v1_0_8=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_0_8 +axi_traffic_gen_v3_0_8=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_8 +tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4 +axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16 +hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1 +rama_v1_1_7_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_7_lib +trace_s2mm_v1_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_0_0 +xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6 +v_mix_v5_1_0=$RDI_DATADIR/xsim/ip/v_mix_v5_1_0 +dft_v4_2_1=$RDI_DATADIR/xsim/ip/dft_v4_2_1 +ta_dma_v1_0_6=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_6 +blk_mem_gen_v8_4_4=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_4 +axi_ethernet_buffer_v2_0_23=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_23 +stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0 +lte_3gpp_mimo_decoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_decoder_v3_0_16 +ieee802d3_50g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_6 +xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6 +axi_sg_v4_1_13=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_13 +v_hdmi_tx1_v1_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_0 +v_hdmi_tx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v2_0_0 +v_tc_v6_2_1=$RDI_DATADIR/xsim/ip/v_tc_v6_2_1 +noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0 +high_speed_selectio_wiz_v3_2_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_2_3 +qdriv_pl_v1_0_2=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_2 +axi_uart16550_v2_0_24=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_24 +microblaze_v11_0_4=$RDI_DATADIR/xsim/ip/microblaze_v11_0_4 +advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0 +mdm_v3_2_19=$RDI_DATADIR/xsim/ip/mdm_v3_2_19 +versal_cips_ps_vip_v1_0_0=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_0 +v_hcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_0_16 +lte_3gpp_mimo_encoder_v4_0_15=$RDI_DATADIR/xsim/ip/lte_3gpp_mimo_encoder_v4_0_15 +axis_clock_converter_v1_1_23=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_23 +v_scenechange_v1_1_0=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_0 +mpegtsmux_v1_0_2=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_0_2 +axi_sideband_util_v1_0_6=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_6 +dsp_macro_v1_0_1=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_1 +ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0 +sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0 +gtwizard_ultrascale_v1_7_9=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_9 +vid_phy_controller_v2_1_9=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_9 +ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig +axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17 +xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0 +rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4 +xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6 +canfd_v3_0_1=$RDI_DATADIR/xsim/ip/canfd_v3_0_1 +axis_broadcaster_v1_1_21=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_21 +mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2 +lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2 +pr_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/pr_bitstream_monitor_v1_0_2 +amm_axi_bridge_v1_0_8=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_8 +canfd_v2_0_4=$RDI_DATADIR/xsim/ip/canfd_v2_0_4 +polar_v1_0_6=$RDI_DATADIR/xsim/ip/polar_v1_0_6 +can_v5_0_25=$RDI_DATADIR/xsim/ip/can_v5_0_25 +axi_timer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_24 +jesd204_v7_2_10=$RDI_DATADIR/xsim/ip/jesd204_v7_2_10 +axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0 +c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6 +axi_firewall_v1_1_1=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_1 +v_axi4s_remap_v1_1_0=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_0 +adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0 +microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6 +axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib +dfx_controller_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_1 +cic_compiler_v4_0_15=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_15 +processing_system7_vip_v1_0_10=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_10 +axi_intc_v4_1_15=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_15 +audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2 +axi_protocol_converter_v2_1_22=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_22 +remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4 +versal_cips_v2_1_0=$RDI_DATADIR/xsim/ip/versal_cips_v2_1_0 +g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18 +v_hscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_0 +axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4 +pcie_dma_versal_v2_0_1=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_1 +v_tpg_v8_0_4=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_4 +c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6 +viterbi_v9_1_12=$RDI_DATADIR/xsim/ip/viterbi_v9_1_12 +pr_decoupler_v1_0_9=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_9 +axi_bram_ctrl_v4_1_4=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_4 +fc32_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_16 +pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0 +axi_register_slice_v2_1_22=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_22 +dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0 +soft_ecc_proxy_v1_0_0=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_0 +hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0 +gig_ethernet_pcs_pma_v16_2_1=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_1 +sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0 +ddr4_pl_v1_0_3=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_3 +axi_vdma_v6_3_10=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_10 +xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0 +xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6 +axi_emc_v3_0_22=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_22 +jesd204c_v4_2_3=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_3 +axi_epc_v2_0_25=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_25 +gig_ethernet_pcs_pma_v16_1_9=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_1_9 +v_vscaler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_0 +generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0 +usxgmii_v1_2_0=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_0 +ieee802d3_400g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v1_0_11 +dft_v4_1_1=$RDI_DATADIR/xsim/ip/dft_v4_1_1 +v_frmbuf_rd_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_0 +ieee802d3_25g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_18 +ethernet_1_10_25g_v2_6_0=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_6_0 +v_frmbuf_wr_v2_2_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_0 +tmr_manager_v1_0_6=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_6 +trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0 +axi_iic_v2_0_25=$RDI_DATADIR/xsim/ip/axi_iic_v2_0_25 +pc_cfr_v6_4_0=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_0 +v_tpg_v7_0_16=$RDI_DATADIR/xsim/ip/v_tpg_v7_0_16 +lmb_bram_if_cntlr_v4_0_19=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_19 +v_vcresampler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_0_16 +axi_ethernetlite_v3_0_21=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_21 +ldpc_v2_0_6=$RDI_DATADIR/xsim/ip/ldpc_v2_0_6 +c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6 +v_mix_v5_0_1=$RDI_DATADIR/xsim/ip/v_mix_v5_0_1 +audio_formatter_v1_0_4=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_4 +flexo_100g_rs_fec_v1_0_16=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_16 +uram_rd_back_v1_0_1=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_1 +ptp_1588_timer_syncer_v1_0_1=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_1 +ieee802d3_clause74_fec_v1_0_8=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_8 +axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0 +common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0 +xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7 +xsdbm_v2_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v2_0_0 +etrnic_v1_1_3=$RDI_DATADIR/xsim/ip/etrnic_v1_1_3 +pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11 +axi_gpio_v2_0_24=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_24 +dfx_decoupler_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_1 +tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16 +axi_ahblite_bridge_v3_0_19=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_19 +in_system_ibert_v1_0_12=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_12 +axis_register_slice_v1_1_22=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_22 +util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2 +xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0 +pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12 +v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0 +axi_cdma_v4_1_22=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_22 +axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7 +hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0 +v_hcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_0 +sid_v8_0_15=$RDI_DATADIR/xsim/ip/sid_v8_0_15 +ahblite_axi_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_17 +zynq_ultra_ps_e_v3_3_3=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_3 +timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4 +axi4svideo_bridge_v1_0_11=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_11 +xbip_multadd_v3_0_15=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_15 +axis_data_fifo_v1_1_23=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_23 +c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14 +xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6 +noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0 +gtwizard_ultrascale_v1_6_10=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_10 +axis_data_fifo_v2_0_4=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_4 +rs_decoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_17 +i2s_receiver_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_4 +perf_axi_tg_v1_0_11=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_11 +interlaken_v2_4_7=$RDI_DATADIR/xsim/ip/interlaken_v2_4_7 +xfft_v7_2_11=$RDI_DATADIR/xsim/ip/xfft_v7_2_11 +smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0 +g709_fec_v2_3_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_3_6 +axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0 +tsn_endpoint_ethernet_mac_block_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_7 +v_hdmi_rx_v2_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v2_0_0 +v_uhdsdi_audio_v2_0_3=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_3 +axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6 +sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1 +vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0 +lte_dl_channel_encoder_v3_0_16=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v3_0_16 +axi_dma_v7_1_23=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_23 +emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2 +c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6 +axi_mm2s_mapper_v1_1_21=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_21 +tcc_encoder_3gpp_v5_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_16 +av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0 +srio_gen2_v4_1_9=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_9 +fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6 +ten_gig_eth_mac_v15_1_9=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_9 +dfx_bitstream_monitor_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_0 +displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0 +v_vcresampler_v1_1_0=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_0 +axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1 +l_ethernet_v3_2_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_2_0 +xxv_ethernet_v3_3_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v3_3_0 +xpm=$RDI_DATADIR/xsim/ip/xpm +nvme_tc_v2_0_0=$RDI_DATADIR/xsim/ip/nvme_tc_v2_0_0 +ieee802d3_200g_rs_fec_v1_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v1_0_11 +ats_switch_v1_0_3=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_3 +axi_data_fifo_v2_1_21=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_21 +zynq_ultra_ps_e_vip_v1_0_8=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_8 +fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4 +mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11 +lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0 +sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2 +xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6 +floating_point_v7_0_18=$RDI_DATADIR/xsim/ip/floating_point_v7_0_18 +v_smpte_uhdsdi_v1_0_8=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_8 +axis_vio_v1_0_2=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_2 +ieee802d3_rs_fec_v2_0_10=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_10 +lte_ul_channel_decoder_v4_0_17=$RDI_DATADIR/xsim/ip/lte_ul_channel_decoder_v4_0_17 +xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10 +aes_v1_1_2=$RDI_DATADIR/xsim/ip/aes_v1_1_2 +div_gen_v5_1_17=$RDI_DATADIR/xsim/ip/div_gen_v5_1_17 +v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9 +lte_dl_channel_encoder_v4_0_2=$RDI_DATADIR/xsim/ip/lte_dl_channel_encoder_v4_0_2 +tcc_decoder_3gppmm_v2_0_20=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_20 +axis_protocol_checker_v2_0_6=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_6 +fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6 +av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1 +xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6 +advanced_io_wizard_v1_0_3=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_3 +v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13 +xpm_cdc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_0 +mailbox_v2_1_14=$RDI_DATADIR/xsim/ip/mailbox_v2_1_14 +uhdsdi_gt_v2_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_3 +lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2 +noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0 +v_vid_gt_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_1 +tri_mode_ethernet_mac_v9_0_17=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_17 +axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0 +axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0 +emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0 +dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf +clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2 +axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0 +mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7 +axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0 +debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1 +pc_cfr_v6_3_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_3_2 +gmii_to_rgmii_v4_1_0=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_0 +ernic_v2_0_0=$RDI_DATADIR/xsim/ip/ernic_v2_0_0 +accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0 +xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4 +axi_pcie3_v3_0_13=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_13 +v_uhdsdi_audio_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v1_0_1 +v_dp_axi4s_vid_out_v1_0_1=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_1 +axi_mcdma_v1_1_3=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_3 +dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13 +sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1 +v_frmbuf_rd_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_1_5 +v_frmbuf_wr_v2_1_5=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_1_5 +axi_crossbar_v2_1_23=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_23 +qdma_v4_0_2=$RDI_DATADIR/xsim/ip/qdma_v4_0_2 +v_hdmi_phy1_v1_0_2=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_2 +hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3 +v_smpte_uhdsdi_tx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_0 +xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0 +ten_gig_eth_pcs_pma_v6_0_18=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_18 +interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4 +axi_protocol_checker_v2_0_8=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_8 +sync_ip=$RDI_DATADIR/xsim/ip/sync_ip +util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4 +util_vector_logic_v2_0_1=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_1 +ba317=$RDI_DATADIR/xsim/ip/ba317 +xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0 +high_speed_selectio_wiz_v3_5_2=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_5_2 +quadsgmii_v3_5_0=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_0 +vby1hs_v1_0_0=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_0 +pc_cfr_v6_1_4=$RDI_DATADIR/xsim/ip/pc_cfr_v6_1_4 +vid_phy_controller_v2_2_7=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_7 +videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5 +fir_compiler_v7_2_15=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_15 +jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi +hdmi_gt_controller_v1_0_3=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_3 +oran_radio_if_v1_1_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v1_1_0 +v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0 +xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip +trace_s2mm_v1_1_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_1_0 +remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4 +lte_pucch_receiver_v2_0_18=$RDI_DATADIR/xsim/ip/lte_pucch_receiver_v2_0_18 +v_smpte_uhdsdi_rx_v1_0_0=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_0 +v_csc_v1_0_16=$RDI_DATADIR/xsim/ip/v_csc_v1_0_16 +ieee802d3_50g_rs_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_14 +emb_mem_gen_v1_0_3=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_3 +lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2 +axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0 +mem_tg_v1_0_3=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_3 +mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4 +emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5 +dds_compiler_v6_0_20=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_20 +icap_arb_v1_0_0=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_0 +axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0 +i2s_transmitter_v1_0_4=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_4 +axi_hbicap_v1_0_3=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_3 +v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0 +picxo=$RDI_DATADIR/xsim/ip/picxo +axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0 +c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14 +axi_uartlite_v2_0_26=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_26 +axi_fifo_mm_s_v4_2_4=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_4 +mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0 +tmr_voter_v1_0_3=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_3 +axi_interconnect_v1_7_18=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_18 +v_hscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_hscaler_v1_0_16 +v_vscaler_v1_0_16=$RDI_DATADIR/xsim/ip/v_vscaler_v1_0_16 +g709_rs_encoder_v2_2_7=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_7 +tmr_comparator_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_4 +mipi_dphy_v4_3_0=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_0 +prc_v1_3_4=$RDI_DATADIR/xsim/ip/prc_v1_3_4 +fifo_generator_v13_2_5=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_5 +iomodule_v3_1_6=$RDI_DATADIR/xsim/ip/iomodule_v3_1_6 +axi4stream_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_8 +v_deinterlacer_v5_0_16=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_0_16 +axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0 +axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0 +pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0 +axi_vip_v1_1_8=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_8 +mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8 +axi_datamover_v5_1_24=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_24 +v_gamma_lut_v1_1_0=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_0 +axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0 +axi_quad_spi_v3_2_21=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_21 +sim_trig_v1_0_4=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_4 +axis_combiner_v1_1_20=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_20 +displayport_v9_0_3=$RDI_DATADIR/xsim/ip/displayport_v9_0_3 +blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6 +sim_clk_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_2 +v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9 +v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0 +compact_gt_v1_0_8=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_8 +zynq_ultra_ps_e_v3_2_6=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_2_6 +axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0 +xhmc_v1_0_12=$RDI_DATADIR/xsim/ip/xhmc_v1_0_12 +lib_fifo_v1_0_14=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_14 +cpri_v8_11_5=$RDI_DATADIR/xsim/ip/cpri_v8_11_5 +proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13 +axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0 +tsn_temac_v1_0_5=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_5 +video_frame_crc_v1_0_3=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_3 +axi_amm_bridge_v1_0_12=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_12 +xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2 +qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0 +floating_point_v7_1_11=$RDI_DATADIR/xsim/ip/floating_point_v7_1_11 +axi_tft_v2_0_23=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_23 +noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0 +lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0 +pc_cfr_v6_0_8=$RDI_DATADIR/xsim/ip/pc_cfr_v6_0_8 +ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0 +v_demosaic_v1_0_8=$RDI_DATADIR/xsim/ip/v_demosaic_v1_0_8 +roe_framer_v3_0_1=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_1 +c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14 +pc_cfr_v6_2_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_2_2 +xbip_dsp48_macro_v3_0_18=$RDI_DATADIR/xsim/ip/xbip_dsp48_macro_v3_0_18 +axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0 +axi_usb2_device_v5_0_23=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_23 +axi_hwicap_v3_0_26=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_26 +axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0 +audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0 +axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0 +microblaze_v10_0_7=$RDI_DATADIR/xsim/ip/microblaze_v10_0_7 +sd_fec_v1_1_6=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_6 +uhdsdi_gt_v1_0_3=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v1_0_3 +bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0 +xfft_v9_0_19=$RDI_DATADIR/xsim/ip/xfft_v9_0_19 +etrnic_v1_0_4=$RDI_DATADIR/xsim/ip/etrnic_v1_0_4 +mpegtsmux_v1_1_0=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_0 +lmb_v10_v3_0_11=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_11 +dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16 +axi_mcdma_v1_0_8=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_0_8 +ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7 +sem_ultra_v3_1_16=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_16 +pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1 +cmac_usplus_v3_1_2=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_2 +axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14 +ieee802d3_400g_rs_fec_v2_0_2=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_2 +switch_core_top_v1_0_8=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_8 +v_multi_scaler_v1_0_4=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_0_4 +v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0 +tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6 +convolution_v9_0_15=$RDI_DATADIR/xsim/ip/convolution_v9_0_15 +iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0 +fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1 +axis_subset_converter_v1_1_22=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_22 +axi_msg_v1_0_6=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_6 +axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0 +aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0 +axi_fifo_mm_s_v4_1_19=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_1_19 +ai_pl=$RDI_DATADIR/xsim/ip/ai_pl +xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6 +c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6 +shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0 +xdma_v4_1_8=$RDI_DATADIR/xsim/ip/xdma_v4_1_8 +hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3 +microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4 +v_csc_v1_1_0=$RDI_DATADIR/xsim/ip/v_csc_v1_1_0 +vfb_v1_0_16=$RDI_DATADIR/xsim/ip/vfb_v1_0_16 +axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub +axi_firewall_v1_0_10=$RDI_DATADIR/xsim/ip/axi_firewall_v1_0_10 +noc_na_v1_0_0=$RDI_DATADIR/xsim/ip/noc_na_v1_0_0 +cmpy_v6_0_19=$RDI_DATADIR/xsim/ip/cmpy_v6_0_19 +mrmac_v1_3_0=$RDI_DATADIR/xsim/ip/mrmac_v1_3_0 +ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0 +bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0 +v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1 +an_lt_v1_0_1=$RDI_DATADIR/xsim/ip/an_lt_v1_0_1 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.xpr b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.xpr new file mode 100644 index 0000000..e15edf8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Project/top.xpr @@ -0,0 +1,491 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/IP/ddr_clk.xcix b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/IP/ddr_clk.xcix new file mode 100644 index 0000000..b26932a Binary files /dev/null and b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/IP/ddr_clk.xcix differ diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/IP/sys_clk.xcix b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/IP/sys_clk.xcix new file mode 100644 index 0000000..5f49d0d Binary files /dev/null and b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/IP/sys_clk.xcix differ diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/clk_ctrl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/clk_ctrl.v new file mode 100644 index 0000000..3725033 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/clk_ctrl/clk_ctrl.v @@ -0,0 +1,52 @@ + + +module clk_ctrl + ( + input clk , + input rst_n , + //*********************************************************** + //Clock OUT + //*********************************************************** + output clk_200M , + output clk_50M , + output ddr3_clk , + //*********************************************************** + //Clock Locked + //*********************************************************** + output [1:0] clk_locked + ); +//*************************************************************** +//50M-->200M +//50M-->125M +//50M-->50M +//50M-->25M +//*************************************************************** + sys_clk U0_sys_clk + (// Clock in ports + .clk_in1 (clk ), // IN + // Clock out ports + .clk_200M (clk_200M ), // OUT + .clk_50M (clk_50M ), // OUT + // Status and control signals + .reset (1'b0 ), + .locked (clka_locked ) + ); + +//*************************************************************** +//50M-->333M +//*************************************************************** +ddr_clk U1_ddr_clk +(// Clock in ports + .clk_in1 (clk_50M ), // IN + // Clock out ports + .ddr3_clk (ddr3_clk ), // OUT + // Status and control signals + .reset (1'b0 ), + .locked (clkb_locked ) + ); +//*************************************************************** +//Clock Locked +//*************************************************************** + assign clk_locked = {clka_locked,clkb_locked}; +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.dcp b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.dcp new file mode 100644 index 0000000..71e3074 Binary files /dev/null and b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.dcp differ diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.veo b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.veo new file mode 100644 index 0000000..4882378 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.veo @@ -0,0 +1,127 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.2 +// \ \ Application : MIG +// / / Filename : ddr3.veo +// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:34:47 $ +// \ \ / \ Date Created : Tue Sept 21 2010 +// \___\/\___\ +// +// Device : 7 Series +// Design Name : DDR3 SDRAM +// Purpose : Template file containing code that can be used as a model +// for instantiating a CORE Generator module in a HDL design. +// Revision History : +//***************************************************************************** + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + ddr3 u_ddr3 ( + + // Memory interface ports + .ddr3_addr (ddr3_addr), // output [14:0] ddr3_addr + .ddr3_ba (ddr3_ba), // output [2:0] ddr3_ba + .ddr3_cas_n (ddr3_cas_n), // output ddr3_cas_n + .ddr3_ck_n (ddr3_ck_n), // output [0:0] ddr3_ck_n + .ddr3_ck_p (ddr3_ck_p), // output [0:0] ddr3_ck_p + .ddr3_cke (ddr3_cke), // output [0:0] ddr3_cke + .ddr3_ras_n (ddr3_ras_n), // output ddr3_ras_n + .ddr3_reset_n (ddr3_reset_n), // output ddr3_reset_n + .ddr3_we_n (ddr3_we_n), // output ddr3_we_n + .ddr3_dq (ddr3_dq), // inout [15:0] ddr3_dq + .ddr3_dqs_n (ddr3_dqs_n), // inout [1:0] ddr3_dqs_n + .ddr3_dqs_p (ddr3_dqs_p), // inout [1:0] ddr3_dqs_p + .init_calib_complete (init_calib_complete), // output init_calib_complete + + .ddr3_dm (ddr3_dm), // output [1:0] ddr3_dm + .ddr3_odt (ddr3_odt), // output [0:0] ddr3_odt + // Application interface ports + .app_addr (app_addr), // input [28:0] app_addr + .app_cmd (app_cmd), // input [2:0] app_cmd + .app_en (app_en), // input app_en + .app_wdf_data (app_wdf_data), // input [127:0] app_wdf_data + .app_wdf_end (app_wdf_end), // input app_wdf_end + .app_wdf_wren (app_wdf_wren), // input app_wdf_wren + .app_rd_data (app_rd_data), // output [127:0] app_rd_data + .app_rd_data_end (app_rd_data_end), // output app_rd_data_end + .app_rd_data_valid (app_rd_data_valid), // output app_rd_data_valid + .app_rdy (app_rdy), // output app_rdy + .app_wdf_rdy (app_wdf_rdy), // output app_wdf_rdy + .app_sr_req (app_sr_req), // input app_sr_req + .app_ref_req (app_ref_req), // input app_ref_req + .app_zq_req (app_zq_req), // input app_zq_req + .app_sr_active (app_sr_active), // output app_sr_active + .app_ref_ack (app_ref_ack), // output app_ref_ack + .app_zq_ack (app_zq_ack), // output app_zq_ack + .ui_clk (ui_clk), // output ui_clk + .ui_clk_sync_rst (ui_clk_sync_rst), // output ui_clk_sync_rst + .app_wdf_mask (app_wdf_mask), // input [15:0] app_wdf_mask + // System Clock Ports + .sys_clk_i (sys_clk_i), + // Reference Clock Ports + .clk_ref_i (clk_ref_i), + .device_temp_i (device_temp_i), // input [11:0] device_temp_i + .sys_rst (sys_rst) // input sys_rst + ); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file ddr3.v when simulating +// the core, ddr3. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.xci b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.xci new file mode 100644 index 0000000..87a6c34 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3.xci @@ -0,0 +1,2964 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ddr3 + + + 0 + 0 + + + 0 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + TDM + 8 + false + 11 + 11 + true + + true + 8 + + COMPONENTS + ROW_COLUMN_BANK + Single + 1250 + 0 + 0 + + + + + 0 + 0 + + + + + 0 + 0 + + + + + 0 + 0 + + + + + 0 + 0 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + false + 100000000 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + + + 0 + 0 + TDM + 8 + false + 11 + 11 + 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DDR3_BANK_WIDTH + bank width + bank width + 3 + + + DDR3_CK_WIDTH + clock width + clock width + 1 + + + DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + DDR3_DM_WIDTH + data mask width + data mask width + 2 + + + DDR3_ODT_WIDTH + odt width + odt width + 1 + + + DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 0 + + + DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + DDR2_ROW_WIDTH + row width + row width + 14 + + + DDR2_BANK_WIDTH + bank width + bank width + 3 + + + DDR2_CK_WIDTH + clock width + clock width + 1 + + + DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + DDR2_ODT_WIDTH + odt width + odt width + 1 + + + DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + LPDDR2_ROW_WIDTH + row width + row width + 14 + + + LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + DDR3_ADDR_WIDTH + addr width + addr width + 29 + + + DDR3_nCK_PER_CLK + nck per clk + nck per clk + 4 + + + DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 16 + + + DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 83333333 + + + PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 666 + + + MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + QDRIIP_DATA_WIDTH + data width + data width + 18 + + + QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + QDRIIP_BURST_LEN + burst len + burst len + 1 + + + RLDII_NUM_DEVICES + num devices + num devices + 1 + + + RLDII_DATA_WIDTH + data width + data width + 18 + + + RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + RLDII_QK_WIDTH + qk width + qk width + 8 + + + RLDII_CK_WIDTH + ck width + ck width + 1 + + + RLDII_DK_WIDTH + dk width + dk width + 1 + + + RLDII_DM_WIDTH + dm width + dm width + 1 + + + RLDII_BANK_WIDTH + bank width + bank width + 2 + + + RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + RLDIII_DATA_WIDTH + data width + data width + 18 + + + RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + RLDIII_QK_WIDTH + qk width + qk width + 8 + + + RLDIII_CK_WIDTH + ck width + ck width + 1 + + + RLDIII_DK_WIDTH + dk width + dk width + 1 + + + RLDIII_DM_WIDTH + dm width + dm width + 1 + + + RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + RLDX_DATA_WIDTH + data width + data width + 18 + + + RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + RLDX_BANK_WIDTH + bank width + bank width + 2 + + + RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + RLDX_DM_WIDTH + dm width + dm width + 1 + + + RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C0_MEM_TYPE + identify interface + identify interface + DDR3 + + + C0_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C0_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C0_USE_AXI + USE AXI + USE AXI + 0 + + + C0_ECC + ecc enable info + ecc enable info + OFF + + + C0_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C0_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C0_DDR3_ROW_WIDTH + row width + row width + 14 + + + C0_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C0_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C0_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C0_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C0_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C0_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C0_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C0_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C0_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C0_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C0_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C0_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C0_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C0_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C0_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C0_DDR2_ROW_WIDTH + row width + row width + 14 + + + C0_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C0_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C0_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C0_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C0_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C0_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C0_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C0_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C0_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C0_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C0_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C0_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C0_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C0_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C0_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C0_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C0_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C0_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C0_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C0_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C0_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C0_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C0_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C0_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C0_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C0_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C0_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C0_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C0_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C0_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C0_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C0_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C0_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C0_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C0_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C0_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C0_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C0_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C0_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C0_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C0_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C0_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C0_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C0_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C0_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C0_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C0_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C0_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C0_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C0_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C0_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C0_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C0_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C0_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C0_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C0_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C0_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C0_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C0_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C0_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C0_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C0_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C0_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C0_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C0_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C0_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C0_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C0_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C0_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C0_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C0_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C0_RLDII_DATA_WIDTH + data width + data width + 18 + + + C0_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C0_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C0_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C0_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C0_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C0_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C0_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C0_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C0_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C0_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C0_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C0_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C0_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C0_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C0_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C0_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C0_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C0_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C0_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C0_RLDX_DATA_WIDTH + data width + data width + 18 + + + C0_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C0_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C0_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C0_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C0_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C0_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C0_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C0_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C0_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C0_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C0_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + C1_MEM_TYPE + identify interface + identify interface + DDR3 + + + C1_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C1_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C1_USE_AXI + USE AXI + USE AXI + 0 + + + C1_ECC + ecc enable info + ecc enable info + OFF + + + C1_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C1_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C1_DDR3_ROW_WIDTH + row width + row width + 14 + + + C1_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C1_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C1_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C1_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C1_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C1_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C1_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C1_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C1_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C1_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C1_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C1_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C1_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C1_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C1_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C1_DDR2_ROW_WIDTH + row width + row width + 14 + + + C1_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C1_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C1_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C1_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C1_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C1_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C1_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C1_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C1_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C1_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C1_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C1_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C1_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C1_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C1_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C1_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C1_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C1_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C1_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C1_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C1_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C1_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C1_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C1_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C1_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C1_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C1_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C1_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C1_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C1_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C1_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C1_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C1_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C1_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C1_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C1_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C1_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C1_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C1_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C1_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C1_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C1_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C1_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C1_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C1_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C1_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C1_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C1_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C1_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C1_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C1_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C1_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C1_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C1_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C1_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C1_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C1_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C1_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C1_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C1_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C1_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C1_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C1_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C1_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C1_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C1_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C1_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C1_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C1_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C1_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C1_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C1_RLDII_DATA_WIDTH + data width + data width + 18 + + + C1_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C1_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C1_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C1_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C1_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C1_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C1_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C1_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C1_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C1_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C1_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C1_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C1_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C1_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C1_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C1_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C1_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C1_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C1_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C1_RLDX_DATA_WIDTH + data width + data width + 18 + + + C1_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C1_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C1_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C1_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C1_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C1_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C1_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C1_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C1_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C1_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C1_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + C2_MEM_TYPE + identify interface + identify interface + DDR3 + + + C2_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C2_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C2_USE_AXI + USE AXI + USE AXI + 0 + + + C2_ECC + ecc enable info + ecc enable info + OFF + + + C2_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C2_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C2_DDR3_ROW_WIDTH + row width + row width + 14 + + + C2_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C2_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C2_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C2_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C2_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C2_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C2_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C2_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C2_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C2_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C2_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C2_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C2_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C2_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C2_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C2_DDR2_ROW_WIDTH + row width + row width + 14 + + + C2_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C2_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C2_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C2_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C2_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C2_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C2_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C2_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C2_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C2_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C2_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C2_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C2_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C2_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C2_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C2_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C2_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C2_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C2_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C2_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C2_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C2_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C2_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C2_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C2_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C2_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C2_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C2_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C2_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C2_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C2_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C2_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C2_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C2_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C2_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C2_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C2_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C2_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C2_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C2_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C2_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C2_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C2_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C2_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C2_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C2_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C2_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C2_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C2_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C2_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C2_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C2_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C2_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C2_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C2_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C2_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C2_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C2_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C2_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C2_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C2_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C2_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C2_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C2_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C2_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C2_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C2_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C2_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C2_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C2_RLDII_DATA_WIDTH + data width + data width + 18 + + + C2_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C2_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C2_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C2_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C2_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C2_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C2_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C2_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C2_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C2_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C2_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C2_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C2_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C2_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C2_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C2_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C2_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C2_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C2_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C2_RLDX_DATA_WIDTH + data width + data width + 18 + + + C2_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C2_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C2_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C2_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C2_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C2_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C2_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C2_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C2_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C2_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C2_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + C3_MEM_TYPE + identify interface + identify interface + DDR3 + + + C3_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C3_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C3_USE_AXI + USE AXI + USE AXI + 0 + + + C3_ECC + ecc enable info + ecc enable info + OFF + + + C3_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C3_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C3_DDR3_ROW_WIDTH + row width + row width + 14 + + + C3_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C3_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C3_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C3_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C3_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C3_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C3_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C3_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C3_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C3_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C3_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C3_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C3_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C3_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C3_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C3_DDR2_ROW_WIDTH + row width + row width + 14 + + + C3_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C3_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C3_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C3_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C3_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C3_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C3_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C3_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C3_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C3_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C3_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C3_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C3_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C3_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C3_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C3_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C3_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C3_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C3_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C3_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C3_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C3_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C3_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C3_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C3_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C3_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C3_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C3_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C3_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C3_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C3_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C3_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C3_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C3_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C3_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C3_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C3_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C3_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C3_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C3_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C3_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C3_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C3_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C3_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C3_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C3_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C3_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C3_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C3_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C3_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C3_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C3_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C3_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C3_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C3_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C3_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C3_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C3_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C3_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C3_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C3_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C3_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C3_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C3_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C3_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C3_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C3_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C3_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C3_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C3_RLDII_DATA_WIDTH + data width + data width + 18 + + + C3_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C3_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C3_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C3_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C3_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C3_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C3_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C3_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C3_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C3_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C3_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C3_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C3_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C3_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C3_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C3_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C3_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C3_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C3_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C3_RLDX_DATA_WIDTH + data width + data width + 18 + + + C3_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C3_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C3_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C3_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C3_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C3_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C3_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C3_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C3_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C3_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C3_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + C4_MEM_TYPE + identify interface + identify interface + DDR3 + + + C4_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C4_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C4_USE_AXI + USE AXI + USE AXI + 0 + + + C4_ECC + ecc enable info + ecc enable info + OFF + + + C4_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C4_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C4_DDR3_ROW_WIDTH + row width + row width + 14 + + + C4_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C4_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C4_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C4_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C4_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C4_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C4_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C4_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C4_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C4_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C4_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C4_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C4_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C4_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C4_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C4_DDR2_ROW_WIDTH + row width + row width + 14 + + + C4_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C4_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C4_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C4_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C4_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C4_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C4_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C4_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C4_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C4_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C4_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C4_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C4_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C4_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C4_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C4_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C4_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C4_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C4_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C4_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C4_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C4_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C4_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C4_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C4_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C4_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C4_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C4_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C4_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C4_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C4_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C4_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C4_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C4_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C4_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C4_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C4_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C4_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C4_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C4_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C4_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C4_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C4_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C4_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C4_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C4_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C4_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C4_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C4_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C4_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C4_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C4_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C4_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C4_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C4_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C4_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C4_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C4_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C4_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C4_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C4_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C4_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C4_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C4_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C4_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C4_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C4_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C4_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C4_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C4_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C4_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C4_RLDII_DATA_WIDTH + data width + data width + 18 + + + C4_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C4_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C4_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C4_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C4_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C4_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C4_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C4_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C4_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C4_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C4_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C4_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C4_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C4_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C4_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C4_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C4_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C4_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C4_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C4_RLDX_DATA_WIDTH + data width + data width + 18 + + + C4_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C4_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C4_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C4_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C4_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C4_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C4_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C4_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C4_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C4_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C4_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + C5_MEM_TYPE + identify interface + identify interface + DDR3 + + + C5_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C5_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C5_USE_AXI + USE AXI + USE AXI + 0 + + + C5_ECC + ecc enable info + ecc enable info + OFF + + + C5_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C5_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C5_DDR3_ROW_WIDTH + row width + row width + 14 + + + C5_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C5_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C5_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C5_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C5_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C5_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C5_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C5_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C5_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C5_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C5_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C5_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C5_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C5_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C5_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C5_DDR2_ROW_WIDTH + row width + row width + 14 + + + C5_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C5_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C5_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C5_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C5_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C5_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C5_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C5_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C5_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C5_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C5_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C5_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C5_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C5_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C5_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C5_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C5_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C5_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C5_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C5_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C5_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C5_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C5_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C5_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C5_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C5_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C5_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C5_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C5_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C5_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C5_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C5_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C5_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C5_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C5_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C5_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C5_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C5_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C5_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C5_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C5_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C5_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C5_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C5_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C5_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C5_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C5_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C5_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C5_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C5_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C5_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C5_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C5_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C5_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C5_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C5_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C5_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C5_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C5_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C5_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C5_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C5_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C5_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C5_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C5_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C5_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C5_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C5_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C5_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C5_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C5_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C5_RLDII_DATA_WIDTH + data width + data width + 18 + + + C5_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C5_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C5_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C5_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C5_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C5_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C5_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C5_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C5_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C5_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C5_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C5_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C5_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C5_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C5_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C5_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C5_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C5_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C5_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C5_RLDX_DATA_WIDTH + data width + data width + 18 + + + C5_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C5_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C5_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C5_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C5_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C5_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C5_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C5_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C5_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C5_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C5_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + C6_MEM_TYPE + identify interface + identify interface + DDR3 + + + C6_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C6_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C6_USE_AXI + USE AXI + USE AXI + 0 + + + C6_ECC + ecc enable info + ecc enable info + OFF + + + C6_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C6_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C6_DDR3_ROW_WIDTH + row width + row width + 14 + + + C6_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C6_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C6_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C6_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C6_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C6_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C6_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C6_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C6_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C6_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C6_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C6_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C6_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C6_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C6_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C6_DDR2_ROW_WIDTH + row width + row width + 14 + + + C6_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C6_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C6_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C6_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C6_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C6_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C6_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C6_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C6_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C6_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C6_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C6_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C6_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C6_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C6_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C6_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C6_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C6_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C6_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C6_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C6_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C6_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C6_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C6_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C6_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C6_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C6_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C6_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C6_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C6_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C6_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C6_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C6_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C6_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C6_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C6_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C6_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C6_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C6_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C6_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C6_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C6_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C6_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C6_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C6_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C6_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C6_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C6_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C6_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C6_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C6_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C6_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C6_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C6_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C6_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C6_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C6_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C6_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C6_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C6_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C6_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C6_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C6_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C6_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C6_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C6_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C6_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C6_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C6_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C6_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C6_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C6_RLDII_DATA_WIDTH + data width + data width + 18 + + + C6_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C6_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C6_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C6_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C6_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C6_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C6_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C6_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C6_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C6_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C6_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C6_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C6_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C6_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C6_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C6_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C6_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C6_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C6_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C6_RLDX_DATA_WIDTH + data width + data width + 18 + + + C6_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C6_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C6_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C6_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C6_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C6_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C6_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C6_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C6_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C6_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C6_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + C7_MEM_TYPE + identify interface + identify interface + DDR3 + + + C7_IS_CLK_SHARED + is clk shared + is clk shared + FALSE + + + C7_SYSCLK_TYPE + Type of sys clk + Type of sys clk + DIFF + + + C7_USE_AXI + USE AXI + USE AXI + 0 + + + C7_ECC + ecc enable info + ecc enable info + OFF + + + C7_DDR3_DQ_WIDTH + data bus width + data bus width + 8 + + + C7_DDR3_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C7_DDR3_ROW_WIDTH + row width + row width + 14 + + + C7_DDR3_BANK_WIDTH + bank width + bank width + 3 + + + C7_DDR3_CK_WIDTH + clock width + clock width + 1 + + + C7_DDR3_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C7_DDR3_CS_WIDTH + chip select width + chip select width + 1 + + + C7_DDR3_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C7_DDR3_DM_WIDTH + data mask width + data mask width + 1 + + + C7_DDR3_ODT_WIDTH + odt width + odt width + 1 + + + C7_DDR3_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C7_DDR3_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C7_DDR3_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C7_DDR3_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C7_DDR3_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C7_DDR3_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C7_DDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C7_DDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C7_DDR2_ROW_WIDTH + row width + row width + 14 + + + C7_DDR2_BANK_WIDTH + bank width + bank width + 3 + + + C7_DDR2_CK_WIDTH + clock width + clock width + 1 + + + C7_DDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C7_DDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C7_DDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C7_DDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C7_DDR2_ODT_WIDTH + odt width + odt width + 1 + + + C7_DDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C7_DDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C7_DDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C7_DDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C7_DDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C7_DDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C7_LPDDR2_DQ_WIDTH + data bus width + data bus width + 8 + + + C7_LPDDR2_DQS_WIDTH + data strobe width + data strobe width + 1 + + + C7_LPDDR2_ROW_WIDTH + row width + row width + 14 + + + C7_LPDDR2_BANK_WIDTH + bank width + bank width + 3 + + + C7_LPDDR2_CK_WIDTH + clock width + clock width + 1 + + + C7_LPDDR2_CKE_WIDTH + clock enable width + clock enable width + 1 + + + C7_LPDDR2_CS_WIDTH + chip select width + chip select width + 1 + + + C7_LPDDR2_nCS_PER_RANK + chip select per rank + chip select per rank + 1 + + + C7_LPDDR2_DM_WIDTH + data mask width + data mask width + 1 + + + C7_LPDDR2_USE_CS_PORT + CS Port is in use + CS Port is in use + 1 + + + C7_LPDDR2_USE_DM_PORT + DM Port is in use + DM Port is in use + 1 + + + C7_LPDDR2_USE_ODT_PORT + ODT Port is in use + ODT Port is in use + 1 + + + C7_LPDDR2_REG_CTRL + Indicates Registered DIMM or not + Indicates Registered DIMM or not + OFF + + + C7_LPDDR2_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C7_LPDDR2_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C7_DQS_CNT_WIDTH + DQS count width + DQS count width + 1 + + + C7_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C7_DDRX_ADDR_WIDTH + addr width + addr width + 8 + + + C7_DDRX_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C7_DDRX_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C7_DDR3_ADDR_WIDTH + addr width + addr width + 8 + + + C7_DDR3_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C7_DDR3_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C7_DDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C7_DDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C7_DDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C7_LPDDR2_ADDR_WIDTH + addr width + addr width + 8 + + + C7_LPDDR2_nCK_PER_CLK + nck per clk + nck per clk + 2 + + + C7_LPDDR2_DATA_WIDTH + datawidth excluding the ECC + datawidth excluding the ECC + 8 + + + C7_FREQ_HZ + defines the UI Clk freq + defines the UI Clk freq + 100.0 + + + C7_PHASE + defines the UI Clk phase + defines the UI Clk phase + 0.000 + + + C7_UI_EXTRA_CLOCKS + Enablement of extra clocks + Enablement of extra clocks + FALSE + + + C7_MMCM_VCO + Max possible VCO of MMCM primitive + Max possible VCO of MMCM primitive + 1200.0 + + + C7_MMCM_CLKOUT0_FREQ + mmcm extra clkout0 + mmcm extra clkout0 + 10.0 + + + C7_MMCM_CLKOUT1_FREQ + mmcm extra clkout1 + mmcm extra clkout1 + 10 + + + C7_MMCM_CLKOUT2_FREQ + mmcm extra clkout2 + mmcm extra clkout2 + 10 + + + C7_MMCM_CLKOUT3_FREQ + mmcm extra clkout3 + mmcm extra clkout3 + 10 + + + C7_MMCM_CLKOUT4_FREQ + mmcm extra clkout4 + mmcm extra clkout4 + 10 + + + C7_MMCM_CLKOUT0_EN + Indicates Enablement of CLKOUT0 + Indicates Enablement of CLKOUT0 + FALSE + + + C7_MMCM_CLKOUT2_EN + Indicates Enablement of CLKOUT2 + Indicates Enablement of CLKOUT2 + FALSE + + + C7_MMCM_CLKOUT1_EN + Indicates Enablement of CLKOUT1 + Indicates Enablement of CLKOUT1 + FALSE + + + C7_MMCM_CLKOUT3_EN + Indicates Enablement of CLKOUT3 + Indicates Enablement of CLKOUT3 + FALSE + + + C7_MMCM_CLKOUT4_EN + Indicates Enablement of CLKOUT4 + Indicates Enablement of CLKOUT4 + FALSE + + + C7_C_S_AXI_CTRL_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C7_C_S_AXI_CTRL_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C7_C_S_AXI_CTRL_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C7_C_S_AXI_CTRL_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C7_C_S_AXI_ID_WIDTH + AXI ID Width + AXI ID Width + 4 + + + C7_C_S_AXI_DATA_WIDTH + AXI Data Width + AXI Data Width + 32 + + + C7_C_S_AXI_ADDR_WIDTH + AXI Addr Width + AXI Addr Width + 32 + + + C7_C_S_AXI_MEM_SIZE + Memory Address Space + Memory Address Space + 1048576 + + + C7_QDRIIP_NUM_DEVICES + num devices + num devices + 1 + + + C7_QDRIIP_DATA_WIDTH + data width + data width + 18 + + + C7_QDRIIP_ADDR_WIDTH + addr width + addr width + 29 + + + C7_QDRIIP_BW_WIDTH + bw width + bw width + 8 + + + C7_QDRIIP_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C7_QDRIIP_BURST_LEN + burst len + burst len + 1 + + + C7_RLDII_NUM_DEVICES + num devices + num devices + 1 + + + C7_RLDII_DATA_WIDTH + data width + data width + 18 + + + C7_RLDII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C7_RLDII_QK_WIDTH + qk width + qk width + 8 + + + C7_RLDII_CK_WIDTH + ck width + ck width + 1 + + + C7_RLDII_DK_WIDTH + dk width + dk width + 1 + + + C7_RLDII_DM_WIDTH + dm width + dm width + 1 + + + C7_RLDII_BANK_WIDTH + bank width + bank width + 2 + + + C7_RLDII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C7_RLDII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C7_RLDIII_NUM_DEVICES + num devices + num devices + 1 + + + C7_RLDIII_DATA_WIDTH + data width + data width + 18 + + + C7_RLDIII_RLD_ADDR_WIDTH + rld addr width + rld addr width + 29 + + + C7_RLDIII_QK_WIDTH + qk width + qk width + 8 + + + C7_RLDIII_CK_WIDTH + ck width + ck width + 1 + + + C7_RLDIII_DK_WIDTH + dk width + dk width + 1 + + + C7_RLDIII_DM_WIDTH + dm width + dm width + 1 + + + C7_RLDIII_BANK_WIDTH + bank width + bank width + 2 + + + C7_RLDIII_QVLD_WIDTH + qvld width + qvld width + 1 + + + C7_RLDIII_DEBUG_PORT + Debug Port enable info + Debug Port enable info + OFF + + + C7_RLDX_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C7_RLDX_DATA_WIDTH + data width + data width + 18 + + + C7_RLDX_ADDR_WIDTH + addr width + addr width + 29 + + + C7_RLDX_BANK_WIDTH + bank width + bank width + 2 + + + C7_RLDX_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C7_RLDX_DM_WIDTH + dm width + dm width + 1 + + + C7_RLDII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C7_RLDII_ADDR_WIDTH + addr width + addr width + 29 + + + C7_RLDII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C7_RLDIII_CMD_PER_CLK + cmd per clock + cmd per clock + 1 + + + C7_RLDIII_ADDR_WIDTH + addr width + addr width + 29 + + + C7_RLDIII_nCK_PER_CLK + nCk per clock + nCk per clock + 1 + + + C7_POLARITY + Polarity of the value + Polarity of the value + ACTIVE_LOW + + + + + + choice_list_1570a756 + DIFF + SINGLE + NOBUF + + + choice_list_350ebf94 + DIFF + SINGLE + NOBUF + NONE + + + choice_list_40181835 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_6eff49bd + ACTIVE_LOW + ACTIVE_HIGH + + + choice_list_ac75ef1e + Custom + + + choice_list_b54243b1 + DDR3 + DDR2 + LPDDR2 + QDRIIP + RLDII + RLDIII + + + choice_list_bdb560e1 + 8 + 16 + 24 + 32 + 40 + 48 + 56 + 64 + 72 + + + choice_list_c7c132f6 + 0.000 + 337.500 + 315.000 + + + choice_list_cf6acb30 + 18 + 36 + 72 + + + choice_list_d10f4555 + FALSE + TRUE + + + choice_list_dc86ec6e + OFF + ON + + + choice_list_dd2843c6 + 1 + 2 + 4 + 8 + + + choice_list_e5b95726 + INTERNAL + EXTERNAL + + + choice_list_e7c484ae + TRUE + FALSE + + + + + xilinx_anylanguagesynthesis_view_fileset + + ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v + verilogSource + + + ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v + verilogSource + + + ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v + verilogSource + + + ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v + verilogSource + + + ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v + verilogSource + + + ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v + verilogSource + + + ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v + verilogSource + + + ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v + verilogSource + + + ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v + verilogSource + + + ddr3/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v + verilogSource + + + ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v + verilogSource + + + ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v + verilogSource + + + ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v + verilogSource + + + ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v + verilogSource + + + ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v + verilogSource + + + ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v + verilogSource + + + ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v + verilogSource + + + ddr3/user_design/constraints/ddr3.xdc + xdc + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + processing_order + early + + + + ddr3/user_design/constraints/ddr3_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + processing_order + early + + + + + xilinx_verilogsynthesiswrapper_view_fileset + + ddr3/user_design/rtl/ddr3.v + verilogSource + + + ddr3/user_design/rtl/ddr3_mig.v + verilogSource + + + + xilinx_implementation_view_fileset + + ddr3/user_design/constraints/ddr3.xdc + xdc + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + processing_order + early + + + + ddr3/user_design/constraints/ddr3_ooc.xdc + xdc + USED_IN_implementation + USED_IN_out_of_context + USED_IN_synthesis + + processing_order + early + + + + + xilinx_externalfiles_view_fileset + + ddr3.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + ddr3_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + ddr3_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + ddr3_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + ddr3_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + This Memory Interface Generator is a simple menu driven tool to generate advanced memory interfaces. This tool generates HDL and pin placement constraints that will help you design your application. Kintex-7 supports DDR3 SDRAM, DDR2 SDRAM, LPDDR2 SDRAM, QDR II+ SRAM, RLDRAMII and RLDRAMIII. Virtex-7 supports DDR3 SDRAM, DDR2 SDRAM, LPDDR2 SDRAM, QDR II+ SRAM, RLDRAMII and RLDRAMIII. Artix-7, Spartan-7, and Zynq support DDR3 SDRAM, DDR2 SDRAM and LPDDR2 SDRAM + + + XML_INPUT_FILE + XML_INPUT_FILE + mig_b.prj + + + RESET_BOARD_INTERFACE + RESET_BOARD_INTERFACE + Custom + + + MIG_DONT_TOUCH_PARAM + MIG_DONT_TOUCH_PARAM + Custom + + + BOARD_MIG_PARAM + BOARD_MIG_PARAM + Custom + + + Component_Name + ddr3 + + + + + Memory Interface Generator (MIG 7 Series) + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2020.2 + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/datasheet.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/datasheet.txt new file mode 100644 index 0000000..20507ea --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/datasheet.txt @@ -0,0 +1,120 @@ + + +Vivado Project Options: + Target Device : xc7a35t-fgg484 + Speed Grade : -2 + HDL : verilog + Synthesis Tool : VIVADO + +MIG Output Options: + Module Name : ddr3 + No of Controllers : 1 + Selected Compatible Device(s) : xc7a50t-fgg484, xc7a75t-fgg484, xc7a100t-fgg484, xc7a15t-fgg484 + +FPGA Options: + System Clock Type : No Buffer + Reference Clock Type : No Buffer + Debug Port : OFF + Internal Vref : enabled + IO Power Reduction : ON + XADC instantiation in MIG : Disabled + +Extended FPGA Options: + DCI for DQ,DQS/DQS#,DM : enabled + Internal Termination (HR Banks) : 50 Ohms + + +/*******************************************************/ + +/* Controller 0 */ + +/*******************************************************/ + +Controller Options : + + Memory : DDR3_SDRAM + + Interface : NATIVE + + Design Clock Frequency : 3000 ps ( 0.00 MHz) + + Phy to Controller Clock Ratio : 4:1 + + Input Clock Period : 3000 ps + + CLKFBOUT_MULT (PLL) : 4 + + DIVCLK_DIVIDE (PLL) : 1 + + VCC_AUX IO : 1.8V + + Memory Type : Components + + Memory Part : MT41K256M16XX-125 + + Equivalent Part(s) : MT41K256M16RE-125 + + Data Width : 16 + + ECC : Disabled + + Data Mask : enabled + + ORDERING : Normal + + + +AXI Parameters : + + Data Width : 128 + + Arbitration Scheme : RD_PRI_REG + + Narrow Burst Support : 0 + + ID Width : 4 + + + +Memory Options: + + Burst Length (MR0[1:0]) : 8 - Fixed + + Read Burst Type (MR0[3]) : Sequential + + CAS Latency (MR0[6:4]) : 5 + + Output Drive Strength (MR1[5,1]) : RZQ/7 + + Controller CS option : Disable + + Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/4 + + Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off + + Memory Address Mapping : BANK_ROW_COLUMN + + + + +Bank Selections: + Bank: 35 + Byte Group T0: DQ[8-15] + Byte Group T1: DQ[0-7] + Byte Group T2: Address/Ctrl-0 + Byte Group T3: Address/Ctrl-1 + + +System_Control: + SignalName: sys_rst + PadLocation: No connect Bank: Select Bank + SignalName: init_calib_complete + PadLocation: No connect Bank: Select Bank + SignalName: tg_compare_error + PadLocation: No connect Bank: Select Bank + + + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/docs/phy_only_support_readme.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/docs/phy_only_support_readme.txt new file mode 100644 index 0000000..d3f5840 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/docs/phy_only_support_readme.txt @@ -0,0 +1,12 @@ +This file includes the information about the PHY layer support: + + - Folder "/user_design/rtl/phy" includes the PHY layer + RTL modules. + - The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v) + - PHY modules can be used in any environment by taking the RTL modules + listed in "phy" folder and PHY layer needs to be connected to + the memory controller. + - Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory + Controller Design)" for more details on PHY interface signaling, + parameter(s) and timing information. + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a100tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a100tfgg484_pkg.xdc new file mode 100644 index 0000000..d62df0f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a100tfgg484_pkg.xdc @@ -0,0 +1,38 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : example_top.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A100TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a15tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a15tfgg484_pkg.xdc new file mode 100644 index 0000000..b9b87a8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a15tfgg484_pkg.xdc @@ -0,0 +1,38 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : example_top.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A15TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a50tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a50tfgg484_pkg.xdc new file mode 100644 index 0000000..e7a6aca --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a50tfgg484_pkg.xdc @@ -0,0 +1,38 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : example_top.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A50TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a75tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a75tfgg484_pkg.xdc new file mode 100644 index 0000000..8c78c0b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/compatible_ucf/xc7a75tfgg484_pkg.xdc @@ -0,0 +1,38 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : example_top.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A75TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/example_top.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/example_top.xdc new file mode 100644 index 0000000..cec6511 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/example_top.xdc @@ -0,0 +1,30 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : example_top.xdc +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A35T-FGG484 +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## +############## NET - IOSTANDARD ################## + + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/readme.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/readme.txt new file mode 100644 index 0000000..5b90a47 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/par/readme.txt @@ -0,0 +1,18 @@ +Files in PAR folder : + +* "example_top.xdc" file is the constraint file for the design. This is used + by Vivado. It has clock constraints, location constraints, IO standards + and false path/SLICE constraints if any. + +* LTX/probe file is required when programming BIT file to FPGA as it contains + the information of debug signals like signal name and position with respect + to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by + vivado tool and is found in .runs/impl_1/debug_nets.ltx + +compatible_ucf folder: + +* MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI + (Pin Compatible FPGAs page in GUI). It generates the XDC files for all + the Compatible FPGAs selected in GUI. If you want to switch to any of the + Compatible FPGAs follow the steps mentioned below. + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/example_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/example_top.v new file mode 100644 index 0000000..6fcc382 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/example_top.v @@ -0,0 +1,662 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.2 +// \ \ Application : MIG +// / / Filename : example_top.v +// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ +// \ \ / \ Date Created : Tue Sept 21 2010 +// \___\/\___\ +// +// Device : 7 Series +// Design Name : DDR3 SDRAM +// Purpose : +// Top-level module. This module serves as an example, +// and allows the user to synthesize a self-contained design, +// which they can be used to test their hardware. +// In addition to the memory controller, the module instantiates: +// 1. Synthesizable testbench - used to model user's backend logic +// and generate different traffic patterns +// Reference : +// Revision History : +//***************************************************************************** + +//`define SKIP_CALIB +`timescale 1ps/1ps + +module example_top # + ( + + //*************************************************************************** + // Traffic Gen related parameters + //*************************************************************************** + parameter PORT_MODE = "BI_MODE", + parameter DATA_MODE = 4'b0010, + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", + parameter EYE_TEST = "FALSE", + // set EYE_TEST = "TRUE" to probe memory + // signals. Traffic Generator will only + // write to one single location and no + // read transactions will be generated. + parameter DATA_PATTERN = "DGEN_ALL", + // For small devices, choose one only. + // For large device, choose "DGEN_ALL" + // "DGEN_HAMMER", "DGEN_WALKING1", + // "DGEN_WALKING0","DGEN_ADDR"," + // "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter CMD_PATTERN = "CGEN_ALL", + // "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM", + // "CGEN_SEQUENTIAL", "CGEN_ALL" + parameter CMD_WDT = 'h3FF, + parameter WR_WDT = 'h1FFF, + parameter RD_WDT = 'h3FF, + parameter SEL_VICTIM_LINE = 0, + parameter BEGIN_ADDRESS = 32'h00000000, + parameter END_ADDRESS = 32'h00ffffff, + parameter PRBS_EADDR_MASK_POS = 32'hff000000, + + //*************************************************************************** + // The following parameters refer to width of various ports + //*************************************************************************** + parameter CK_WIDTH = 1, + // # of CK/CK# outputs to memory. + parameter nCS_PER_RANK = 1, + // # of unique CS outputs per rank for phy + parameter CKE_WIDTH = 1, + // # of CKE outputs to memory. + parameter DM_WIDTH = 2, + // # of DM (data mask) + parameter ODT_WIDTH = 1, + // # of ODT outputs to memory. + parameter BANK_WIDTH = 3, + // # of memory Bank Address bits. + parameter COL_WIDTH = 10, + // # of memory Column Address bits. + parameter CS_WIDTH = 1, + // # of unique CS outputs to memory. + parameter DQ_WIDTH = 16, + // # of DQ (data) + parameter DQS_WIDTH = 2, + parameter DQS_CNT_WIDTH = 1, + // = ceil(log2(DQS_WIDTH)) + parameter DRAM_WIDTH = 8, + // # of DQ per DQS + parameter ECC = "OFF", + parameter ECC_TEST = "OFF", + //parameter nBANK_MACHS = 4, + parameter nBANK_MACHS = 4, + parameter RANKS = 1, + // # of Ranks. + parameter ROW_WIDTH = 15, + // # of memory Row Address bits. + parameter ADDR_WIDTH = 29, + // # = RANK_WIDTH + BANK_WIDTH + // + ROW_WIDTH + COL_WIDTH; + // Chip Select is always tied to low for + // single rank devices + + //*************************************************************************** + // The following parameters are mode register settings + //*************************************************************************** + parameter BURST_MODE = "8", + // DDR3 SDRAM: + // Burst Length (Mode Register 0). + // # = "8", "4", "OTF". + // DDR2 SDRAM: + // Burst Length (Mode Register). + // # = "8", "4". + + + //*************************************************************************** + // The following parameters are multiplier and divisor factors for PLLE2. + // Based on the selected design frequency these parameters vary. + //*************************************************************************** + parameter CLKIN_PERIOD = 3000, + // Input Clock Period + parameter CLKFBOUT_MULT = 4, + // write PLL VCO multiplier + parameter DIVCLK_DIVIDE = 1, + // write PLL VCO divisor + parameter CLKOUT0_PHASE = 0.0, + // Phase for PLL output clock (CLKOUT0) + parameter CLKOUT0_DIVIDE = 2, + // VCO output divisor for PLL output clock (CLKOUT0) + parameter CLKOUT1_DIVIDE = 4, + // VCO output divisor for PLL output clock (CLKOUT1) + parameter CLKOUT2_DIVIDE = 64, + // VCO output divisor for PLL output clock (CLKOUT2) + parameter CLKOUT3_DIVIDE = 16, + // VCO output divisor for PLL output clock (CLKOUT3) + parameter MMCM_VCO = 666, + // Max Freq (MHz) of MMCM VCO + parameter MMCM_MULT_F = 8, + // write MMCM VCO multiplier + parameter MMCM_DIVCLK_DIVIDE = 1, + // write MMCM VCO divisor + + //*************************************************************************** + // Simulation parameters + //*************************************************************************** + parameter SIMULATION = "FALSE", + // Should be TRUE during design simulations and + // FALSE during implementations + + //*************************************************************************** + // IODELAY and PHY related parameters + //*************************************************************************** + parameter TCQ = 100, + + parameter DRAM_TYPE = "DDR3", + + + //*************************************************************************** + // System clock frequency parameters + //*************************************************************************** + parameter nCK_PER_CLK = 4, + // # of memory CKs per fabric CLK + + + + //*************************************************************************** + // Debug parameters + //*************************************************************************** + parameter DEBUG_PORT = "OFF", + // # = "ON" Enable debug signals/controls. + // = "OFF" Disable debug signals/controls. + + parameter RST_ACT_LOW = 1 + // =1 for active low reset, + // =0 for active high. + ) + ( + + // Inouts + inout [15:0] ddr3_dq, + inout [1:0] ddr3_dqs_n, + inout [1:0] ddr3_dqs_p, + + // Outputs + output [14:0] ddr3_addr, + output [2:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + output [0:0] ddr3_ck_p, + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, + + + output [1:0] ddr3_dm, + + output [0:0] ddr3_odt, + + + // Inputs + + // Single-ended system clock + input sys_clk_i, + + // Single-ended iodelayctrl clk (reference clock) + input clk_ref_i, + + output tg_compare_error, + output init_calib_complete, + input [11:0] device_temp_i, + // The 12 MSB bits of the temperature sensor transfer + // function need to be connected to this port. This port + // will be synchronized w.r.t. to fabric clock internally. + + + // System reset - Default polarity of sys_rst pin is Active Low. + // System reset polarity will change based on the option + // selected in GUI. + input sys_rst + ); + +function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + function integer STR_TO_INT; + input [7:0] in; + begin + if(in == "8") + STR_TO_INT = 8; + else if(in == "4") + STR_TO_INT = 4; + else + STR_TO_INT = 0; + end + endfunction + + + localparam DATA_WIDTH = 16; + localparam RANK_WIDTH = clogb2(RANKS); + localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH; + localparam BURST_LENGTH = STR_TO_INT(BURST_MODE); + localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH; + localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8; + + //*************************************************************************** + // Traffic Gen related parameters (derived) + //*************************************************************************** + localparam TG_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH) + + BANK_WIDTH + ROW_WIDTH + COL_WIDTH; + localparam MASK_SIZE = DATA_WIDTH/8; + + + // Wire declarations + + wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err; + wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err; + wire [ADDR_WIDTH-1:0] app_addr; + wire [2:0] app_cmd; + wire app_en; + wire app_rdy; + wire [APP_DATA_WIDTH-1:0] app_rd_data; + wire app_rd_data_end; + wire app_rd_data_valid; + wire [APP_DATA_WIDTH-1:0] app_wdf_data; + wire app_wdf_end; + wire [APP_MASK_WIDTH-1:0] app_wdf_mask; + wire app_wdf_rdy; + wire app_sr_active; + wire app_ref_ack; + wire app_zq_ack; + wire app_wdf_wren; + wire [(64+(2*APP_DATA_WIDTH))-1:0] error_status; + wire [(PAYLOAD_WIDTH/8)-1:0] cumlative_dq_lane_error; + wire mem_pattern_init_done; + wire [47:0] tg_wr_data_counts; + wire [47:0] tg_rd_data_counts; + wire modify_enable_sel; + wire [2:0] data_mode_manual_sel; + wire [2:0] addr_mode_manual_sel; + wire [APP_DATA_WIDTH-1:0] cmp_data; + reg [63:0] cmp_data_r; + wire cmp_data_valid; + reg cmp_data_valid_r; + wire cmp_error; + wire [(PAYLOAD_WIDTH/8)-1:0] dq_error_bytelane_cmp; + + wire clk; + wire rst; + + wire dbg_sel_pi_incdec; + wire dbg_pi_f_inc; + wire dbg_pi_f_dec; + wire dbg_sel_po_incdec; + wire dbg_po_f_inc; + wire dbg_po_f_stg23_sel; + wire dbg_po_f_dec; + + + wire vio_modify_enable; + wire [3:0] vio_data_mode_value; + wire vio_pause_traffic; + wire [2:0] vio_addr_mode_value; + wire [3:0] vio_instr_mode_value; + wire [1:0] vio_bl_mode_value; + wire [9:0] vio_fixed_bl_value; + wire [2:0] vio_fixed_instr_value; + wire vio_data_mask_gen; + wire vio_tg_rst; + wire vio_dbg_sel_pi_incdec; + wire vio_dbg_pi_f_inc; + wire vio_dbg_pi_f_dec; + wire vio_dbg_sel_po_incdec; + wire vio_dbg_po_f_inc; + wire vio_dbg_po_f_stg23_sel; + wire vio_dbg_po_f_dec; + + wire [11:0] device_temp; + +`ifdef SKIP_CALIB + // skip calibration wires + wire calib_tap_req; + reg calib_tap_load; + reg [6:0] calib_tap_addr; + reg [7:0] calib_tap_val; + reg calib_tap_load_done; +`endif + + + +//*************************************************************************** + + + + + + + +// Start of User Design top instance +//*************************************************************************** +// The User design is instantiated below. The memory interface ports are +// connected to the top-level and the application interface ports are +// connected to the traffic generator module. This provides a reference +// for connecting the memory controller to system. +//*************************************************************************** + + ddr3 u_ddr3 + ( + + +// Memory interface ports + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_we_n (ddr3_we_n), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_reset_n (ddr3_reset_n), + .init_calib_complete (init_calib_complete), + + + .ddr3_dm (ddr3_dm), + .ddr3_odt (ddr3_odt), +// Application interface ports + .app_addr (app_addr), + .app_cmd (app_cmd), + .app_en (app_en), + .app_wdf_data (app_wdf_data), + .app_wdf_end (app_wdf_end), + .app_wdf_wren (app_wdf_wren), + .app_rd_data (app_rd_data), + .app_rd_data_end (app_rd_data_end), + .app_rd_data_valid (app_rd_data_valid), + .app_rdy (app_rdy), + .app_wdf_rdy (app_wdf_rdy), + .app_sr_req (1'b0), + .app_ref_req (1'b0), + .app_zq_req (1'b0), + .app_sr_active (app_sr_active), + .app_ref_ack (app_ref_ack), + .app_zq_ack (app_zq_ack), + .ui_clk (clk), + .ui_clk_sync_rst (rst), + + .app_wdf_mask (app_wdf_mask), + + +// System Clock Ports + .sys_clk_i (sys_clk_i), +// Reference Clock Ports + .clk_ref_i (clk_ref_i), + .device_temp_i (device_temp_i), + .device_temp (device_temp), + `ifdef SKIP_CALIB + .calib_tap_req (calib_tap_req), + .calib_tap_load (calib_tap_load), + .calib_tap_addr (calib_tap_addr), + .calib_tap_val (calib_tap_val), + .calib_tap_load_done (calib_tap_load_done), + `endif + + .sys_rst (sys_rst) + ); +// End of User Design top instance + + +//*************************************************************************** +// The traffic generation module instantiated below drives traffic (patterns) +// on the application interface of the memory controller +//*************************************************************************** + + mig_7series_v4_2_traffic_gen_top # + ( + .TCQ (TCQ), + .SIMULATION (SIMULATION), + .FAMILY ("VIRTEX7"), + .MEM_TYPE (DRAM_TYPE), + .TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE), + //.BL_WIDTH (BL_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + .NUM_DQ_PINS (PAYLOAD_WIDTH), + .MEM_BURST_LEN (BURST_LENGTH), + .MEM_COL_WIDTH (COL_WIDTH), + .PORT_MODE (PORT_MODE), + .DATA_PATTERN (DATA_PATTERN), + .CMD_PATTERN (CMD_PATTERN), + .DATA_WIDTH (APP_DATA_WIDTH), + .ADDR_WIDTH (TG_ADDR_WIDTH), + .MASK_SIZE (MASK_SIZE), + .BEGIN_ADDRESS (BEGIN_ADDRESS), + .DATA_MODE (DATA_MODE), + .END_ADDRESS (END_ADDRESS), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .CMD_WDT (CMD_WDT), + .RD_WDT (RD_WDT), + .WR_WDT (WR_WDT), + .EYE_TEST (EYE_TEST) + ) + u_traffic_gen_top + ( + .clk (clk), + .rst (rst), + .tg_only_rst (po_win_tg_rst | vio_tg_rst), + .manual_clear_error (manual_clear_error), + .memc_init_done (init_calib_complete), + .memc_cmd_full (~app_rdy), + .memc_cmd_en (app_en), + .memc_cmd_instr (app_cmd), + .memc_cmd_bl (), + .memc_cmd_addr (app_addr), + .memc_wr_en (app_wdf_wren), + .memc_wr_end (app_wdf_end), + .memc_wr_mask (app_wdf_mask), + .memc_wr_data (app_wdf_data), + .memc_wr_full (~app_wdf_rdy), + .memc_rd_en (), + .memc_rd_data (app_rd_data), + .memc_rd_empty (~app_rd_data_valid), + .qdr_wr_cmd_o (), + .qdr_rd_cmd_o (), + .vio_pause_traffic (vio_pause_traffic), + .vio_modify_enable (vio_modify_enable), + .vio_data_mode_value (vio_data_mode_value), + .vio_addr_mode_value (vio_addr_mode_value), + .vio_instr_mode_value (vio_instr_mode_value), + .vio_bl_mode_value (vio_bl_mode_value), + .vio_fixed_bl_value (vio_fixed_bl_value), + .vio_fixed_instr_value(vio_fixed_instr_value), + .vio_data_mask_gen (vio_data_mask_gen), + .fixed_addr_i (32'b0), + .fixed_data_i (32'b0), + .simple_data0 (32'b0), + .simple_data1 (32'b0), + .simple_data2 (32'b0), + .simple_data3 (32'b0), + .simple_data4 (32'b0), + .simple_data5 (32'b0), + .simple_data6 (32'b0), + .simple_data7 (32'b0), + .wdt_en_i (wdt_en_w), + .bram_cmd_i (39'b0), + .bram_valid_i (1'b0), + .bram_rdy_o (), + .cmp_data (cmp_data), + .cmp_data_valid (cmp_data_valid), + .cmp_error (cmp_error), + .wr_data_counts (tg_wr_data_counts), + .rd_data_counts (tg_rd_data_counts), + .dq_error_bytelane_cmp (dq_error_bytelane_cmp), + .error (tg_compare_error), + .error_status (error_status), + .cumlative_dq_lane_error (cumlative_dq_lane_error), + .cmd_wdt_err_o (cmd_wdt_err_w), + .wr_wdt_err_o (wr_wdt_err_w), + .rd_wdt_err_o (rd_wdt_err_w), + .mem_pattern_init_done (mem_pattern_init_done) + ); + + + //***************************************************************** + // Default values are assigned to the debug inputs of the traffic + // generator + //***************************************************************** + assign vio_modify_enable = 1'b0; + assign vio_data_mode_value = 4'b0010; + assign vio_addr_mode_value = 3'b011; + assign vio_instr_mode_value = 4'b0010; + assign vio_bl_mode_value = 2'b10; + assign vio_fixed_bl_value = 8'd16; + assign vio_data_mask_gen = 1'b0; + assign vio_pause_traffic = 1'b0; + assign vio_fixed_instr_value = 3'b001; + assign dbg_clear_error = 1'b0; + assign po_win_tg_rst = 1'b0; + assign vio_tg_rst = 1'b0; + assign wdt_en_w = 1'b1; + + assign dbg_sel_pi_incdec = 'b0; + assign dbg_sel_po_incdec = 'b0; + assign dbg_pi_f_inc = 'b0; + assign dbg_pi_f_dec = 'b0; + assign dbg_po_f_inc = 'b0; + assign dbg_po_f_dec = 'b0; + assign dbg_po_f_stg23_sel = 'b0; + + +`ifdef SKIP_CALIB + //*************************************************************************** + // Skip calib test logic + //*************************************************************************** + + reg[3*DQS_WIDTH-1:0] po_coarse_tap; + reg[6*DQS_WIDTH-1:0] po_stg3_taps; + reg[6*DQS_WIDTH-1:0] po_stg2_taps; + reg[6*DQS_WIDTH-1:0] pi_stg2_taps; + reg[5*DQS_WIDTH-1:0] idelay_taps; + reg[11:0] cal_device_temp; + + + always @(posedge clk) begin + // tap values from golden run (factory) + po_coarse_tap <= #TCQ 'h2; + po_stg3_taps <= #TCQ 'h0D; + po_stg2_taps <= #TCQ 'h1D; + pi_stg2_taps <= #TCQ 'h1E; + idelay_taps <= #TCQ 'h08; + cal_device_temp <= #TCQ 'h000; + end + + always @(posedge clk) begin + if (rst) + calib_tap_load <= #TCQ 1'b0; + else if (calib_tap_req) + calib_tap_load <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) begin + calib_tap_addr <= #TCQ 'd0; + calib_tap_val <= #TCQ po_coarse_tap[3*calib_tap_addr[6:3]+:3]; //'d1; + calib_tap_load_done <= #TCQ 1'b0; + end else if (calib_tap_load) begin + case (calib_tap_addr[2:0]) + 3'b000: begin + calib_tap_addr[2:0] <= #TCQ 3'b001; + calib_tap_val <= #TCQ po_stg3_taps[6*calib_tap_addr[6:3]+:6]; //'d19; + end + 3'b001: begin + calib_tap_addr[2:0] <= #TCQ 3'b010; + calib_tap_val <= #TCQ po_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d45; + end + 3'b010: begin + calib_tap_addr[2:0] <= #TCQ 3'b011; + calib_tap_val <= #TCQ pi_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d20; + end + 3'b011: begin + calib_tap_addr[2:0] <= #TCQ 3'b100; + calib_tap_val <= #TCQ idelay_taps[5*calib_tap_addr[6:3]+:5]; //'d1; + end + 3'b100: begin + if (calib_tap_addr[6:3] < DQS_WIDTH-1) begin + calib_tap_addr[2:0] <= #TCQ 3'b000; + calib_tap_val <= #TCQ po_coarse_tap[3*(calib_tap_addr[6:3]+1)+:3]; //'d1; + calib_tap_addr[6:3] <= #TCQ calib_tap_addr[6:3] + 1; + end else begin + calib_tap_addr[2:0] <= #TCQ 3'b110; + calib_tap_val <= #TCQ cal_device_temp[7:0]; + calib_tap_addr[6:3] <= #TCQ 4'b1111; + end + end + 3'b110: begin + calib_tap_addr[2:0] <= #TCQ 3'b111; + calib_tap_val <= #TCQ {4'h0,cal_device_temp[11:8]}; + calib_tap_addr[6:3] <= #TCQ 4'b1111; + end + 3'b111: begin + calib_tap_load_done <= #TCQ 1'b1; + end + endcase + end + end + + +//****************skip calib test logic end********************************** +`endif + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_afifo.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_afifo.v new file mode 100644 index 0000000..86ce619 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_afifo.v @@ -0,0 +1,231 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: afifo.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $ +// \ \ / \ Date Created: Oct 21 2008 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: A generic synchronous fifo. +//Reference: +//Revision History: 1.2 11/8/2010 Removed unused signals. + +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_afifo # +( + parameter TCQ = 100, + parameter DSIZE = 32, + parameter FIFO_DEPTH = 16, + parameter ASIZE = 4, + parameter SYNC = 1 // only has always '1' logic. +) +( +input wr_clk, +input rst, +input wr_en, +input [DSIZE-1:0] wr_data, +input rd_en, +input rd_clk, +output [DSIZE-1:0] rd_data, +output reg full, +output reg empty, +output reg almost_full +); + +// memory array +reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1]; + +//Read Capture Logic +// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk +reg [ASIZE:0] rd_capture_ptr; +reg [ASIZE:0] pre_rd_capture_gray_ptr; +reg [ASIZE:0] rd_capture_gray_ptr; + +reg [ASIZE:0] wr_capture_ptr; +reg [ASIZE:0] pre_wr_capture_gray_ptr; +reg [ASIZE:0] wr_capture_gray_ptr; +wire [ASIZE:0] buf_avail; +wire [ASIZE:0] buf_filled; +wire [ASIZE-1:0] wr_addr, rd_addr; +wire COutb,COutd; +reg COuta,COutc; +reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp; +integer i,j,k; + + + always @ (rd_ptr) + rd_capture_ptr = rd_ptr; + + + +//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers +// before do comparison. + + + +always @ (wr_ptr) + wr_capture_ptr = wr_ptr; + +// dualport ram +// Memory (RAM) that holds the contents of the FIFO + + +assign wr_addr = wr_ptr[ASIZE-1:0]; +assign rd_data = mem[rd_addr]; +always @(posedge wr_clk) +begin +if (wr_en && !full) + mem[wr_addr] <= #TCQ wr_data; + +end + + +// Read Side Logic + + +assign rd_addr = rd_ptr_cp[ASIZE-1:0]; +assign rd_strobe = rd_en && !empty; + +integer n; + // change the binary pointer to gray pointer + + +always @(posedge rd_clk) +begin +if (rst) + begin + rd_ptr <= #TCQ 'b0; + rd_ptr_cp <= #TCQ 'b0; + + end +else begin + if (rd_strobe) begin + {COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1; + rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1; + + end + + // change the binary pointer to gray pointer +end + +end + +//generate empty signal +assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr; + +always @ (posedge rd_clk ) +begin + if (rst) + empty <= #TCQ 1'b1; + else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe)) + empty <= #TCQ 1'b1; + else + empty <= #TCQ 1'b0; +end + + +// write side logic; + +reg [ASIZE:0] wbin; +wire [ASIZE:0] wgraynext, wbinnext; + + + +always @(posedge rd_clk) +begin +if (rst) + begin + wr_ptr <= #TCQ 'b0; + end +else begin + if (wr_en) + {COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1; + + // change the binary pointer to gray pointer +end + +end + + +// calculate how many buf still available +//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr; +assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16; + + +always @ (posedge wr_clk ) +begin + if (rst) + full <= #TCQ 1'b0; + else if ((buf_avail == 0) || (buf_avail == 1 && wr_en)) + full <= #TCQ 1'b1; + else + full <= #TCQ 1'b0; +end + + +always @ (posedge wr_clk ) +begin + if (rst) + almost_full <= #TCQ 1'b0; + else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en)) + almost_full <= #TCQ 1'b1; + else + almost_full <= #TCQ 1'b0; +end + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_gen.v new file mode 100644 index 0000000..95798fd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_gen.v @@ -0,0 +1,1788 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: cmd_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ +// \ \ / \ Date Created: Oct 21 2008 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module genreates different type of commands, address, +// burst_length to mcb_flow_control module. +//Reference: +//Revision History: +// Nov14 2008. Added constraints for generating PRBS_BL when +// generated address is too close to end of address space. +// The BL will be force to 1 to avoid across other port's space. +// April 2 2009 Fixed Sequential Address Circuit to avoide generate any address +// beyond the allowed address range. +// Oct 22 2009 Fixed BRAM interface. +// Fixed run_traffic stop and go problem. +// Merged V6 and SP6 specific requirements. +// Modified syntax for VHDL Formality comparison. +// Dec 1 2011 Fixed Simple Data mode address generation problem. +// Jan 4 2012 Added percent write instruction mode ( mode == 4) to +// let user specify percentage of write commands out of mix +// write/read commands. + +//***************************************************************************** + + + +`timescale 1ps/1ps + + + +`define RD 3'b001; + +`define RDP 3'b011; + +`define WR 3'b000; + +`define WRP 3'b010; + +`define REFRESH 3'b100; + + + +(* use_dsp48 = "no" *) + +module mig_7series_v4_2_cmd_gen # + + ( + + parameter TCQ = 100, + + + + parameter FAMILY = "SPARTAN6", + + parameter MEM_TYPE = "DDR3", + + + + parameter BL_WIDTH = 6, // User Commands Burst length that send over User Interface. + + parameter MEM_BURST_LEN = 8, + + parameter nCK_PER_CLK = 4, + + parameter PORT_MODE = "BI_MODE", + + parameter NUM_DQ_PINS = 8, + + parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL", + + parameter ADDR_WIDTH = 30, + + parameter BANK_WIDTH = 3, + + parameter DWIDTH = 32, + + parameter PIPE_STAGES = 0, + + parameter MEM_COL_WIDTH = 10, // memory column width + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + + parameter PRBS_EADDR = 32'h00002000, + + parameter PRBS_SADDR = 32'h00002000 + + ) + + ( + + input clk_i, + + input [9:0] rst_i, + + input run_traffic_i, + + input [3:0] vio_instr_mode_value, + input [3:0] vio_percent_write, + input single_operation, + + // runtime parameter + + input mem_pattern_init_done_i, + + input [31:0] start_addr_i, // define the start of address + + input [31:0] end_addr_i, + + input [31:0] cmd_seed_i, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen + + input load_seed_i, // + + // upper layer inputs to determine the command bus and data pattern + + // internal traffic generator initialize the memory with + + input [2:0] addr_mode_i, // "00" = bram; takes the address from bram output + + // "01" = fixed address from the fixed_addr input + + // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR + + // "11" = sequential + + + + input [3:0] data_mode_i, // 4'b0010:address as data + + // 4'b0011:DGEN_HAMMER + + // 4'b0100:DGEN_NEIGHBOUR + + // 4'b0101:DGEN_WALKING1 + + // 4'b0110:DGEN_WALKING0 + + // 4'b0111:PRBS_DATA + + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + + input [3:0] instr_mode_i, // "0000" = bram; takes instruction from bram output + + // "0001" = fixed instr from fixed instr input + + // "0010" = R/W + + // "0011" = RP/WP + + // "0100" = R/RP/W/WP + + // "0101" = R/RP/W/WP/REF + + // "0110" = PRBS + + + + + + input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output + + // "01" = fixed , takes the burst length from the fixed_bl input + + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + + + input mode_load_i, + + + + // fixed pattern inputs interface + + input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64 + + input [2:0] fixed_instr_i, //RD 3'b001 + + //RDP 3'b011 + + //WR 3'b000 + + //WRP 3'b010 + + //REFRESH 3'b100 + + input [31:0] fixed_addr_i, // only upper 30 bits will be used + + // BRAM FIFO input + + input [31:0] bram_addr_i, // + + input [2:0] bram_instr_i, + + input [5:0] bram_bl_i, + + input bram_valid_i, + + output bram_rdy_o, + + + + input reading_rd_data_i, + + // mcb_flow_control interface + + input rdy_i, + + + + output [31:0] addr_o, // generated address + + output [2:0] instr_o, // generated instruction + + output [BL_WIDTH - 1:0] bl_o, // generated instruction + +// output reg [31:0] m_addr_o, + + output cmd_o_vld , // valid commands when asserted + + output reg mem_init_done_o + + ); + + + + localparam PRBS_ADDR_WIDTH = 32; + + localparam INSTR_PRBS_WIDTH = 16; + + localparam BL_PRBS_WIDTH = 16; + + + +localparam BRAM_DATAL_MODE = 4'b0000; + +localparam FIXED_DATA_MODE = 4'b0001; + +localparam ADDR_DATA_MODE = 4'b0010; + +localparam HAMMER_DATA_MODE = 4'b0011; + +localparam NEIGHBOR_DATA_MODE = 4'b0100; + +localparam WALKING1_DATA_MODE = 4'b0101; + +localparam WALKING0_DATA_MODE = 4'b0110; + +localparam PRBS_DATA_MODE = 4'b0111; + +localparam DWIDTH_BY_8 = (DWIDTH >> 3); + +localparam LOGB2_MEM_BURST_INT = (MEM_BURST_LEN == 8)? 3:2; + + + +reg [BL_WIDTH+DWIDTH_BY_8-1:0] bl_x_DWIDTH_BY_8; + +reg [BL_WIDTH+2:0] INC_COUNTS /* synthesis syn_dspstyle = logic */ ; + +reg [2:0] addr_mode_reg; + +reg [1:0] bl_mode_reg; + +reg [31:0] addr_counts /* synthesis syn_dspstyle = logic */ ; + +reg [31:0] addr_counts_next_r; + +reg [BANK_WIDTH-1:0] bank_counts; + +wire [14:0] prbs_bl; + +reg [2:0] instr_out; + +wire [14:0] prbs_instr_a; + +wire [14:0] prbs_instr_b; + +reg [BL_WIDTH - 1:0] prbs_brlen; + +wire [31:0] prbs_addr; + +wire [31:0] seq_addr; + +wire [31:0] fixed_addr; + +reg [31:0] addr_out ; + +reg [BL_WIDTH - 1:0] bl_out; + +reg [BL_WIDTH + DWIDTH/8 - 1:0]cal_blout; + +reg [BL_WIDTH - 1:0] bl_out_reg; + +reg mode_load_d1; + +reg mode_load_d2; + +reg mode_load_pulse; + +wire [BL_WIDTH+35:0] pipe_data_o; + +wire cmd_clk_en; + +wire pipe_out_vld; + +reg force_bl1; + +reg bl_out_clk_en; + +reg [BL_WIDTH+35:0] pipe_data_in; + +reg instr_vld; + +reg bl_out_vld; + +reg gen_addr_larger ; + +reg gen_bl_larger; + +reg [7:0] buf_avail_r; + +reg [6:0] rd_data_received_counts; + +reg [6:0] rd_data_counts_asked; + +reg instr_vld_dly1; + +reg first_load_pulse; + +reg mem_init_done; + +reg refresh_cmd_en ; + +reg [9:0] refresh_timer; + +reg refresh_prbs; + +reg cmd_vld; + +reg run_traffic_r; + +reg cmd_clk_en_r; + +reg finish_init; + +reg mem_init_done_r; + +reg first_mode_load_pulse_r1; + +reg first_mode_load_pulse_set; + +reg mode_load_pulse_r1; + +reg n_gen_write_only; + +reg [9:0]force_rd_counts; + +reg force_rd; + +reg bl_64; + +reg force_wrcmd_gen; +reg toggle_rw; +reg [3:0] write_percent_cnt; + + + +always @ (posedge clk_i) + + if (rst_i[0]) + + mem_init_done_o <= #TCQ 1'b0; + + else if (cmd_clk_en_r) + + mem_init_done_o <= #TCQ mem_init_done_r; + + +always @ (posedge clk_i) +begin + + run_traffic_r <= #TCQ run_traffic_i; + +end + + +// commands go through pipeline inserters + +assign addr_o = pipe_data_o[31:0]; + +assign instr_o = pipe_data_o[34:32]; + + + +assign bl_o = pipe_data_o[(BL_WIDTH - 1 + 35):35]; + + + + + + + + // most significant bit + +assign cmd_o_vld = pipe_data_o[BL_WIDTH + 35] & run_traffic_r; + +assign pipe_out_vld = pipe_data_o[BL_WIDTH + 35] & run_traffic_r; + + + + + +assign pipe_data_o = pipe_data_in; + + + +always @(posedge clk_i) begin + + + + instr_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse)); + + bl_out_clk_en <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse)); + + bl_out_vld <= #TCQ bl_out_clk_en; + + end + + + +always @ (posedge clk_i) begin + + if (rst_i[0] || single_operation) + + first_load_pulse <= #TCQ 1'b1; + + else if (mode_load_pulse) + + first_load_pulse <= #TCQ 1'b0; + + else + + first_load_pulse <= #TCQ first_load_pulse; + + end + + + + + +always @(posedge clk_i) begin + +if (CMD_PATTERN == "CGEN_BRAM") + + cmd_vld <= #TCQ (cmd_clk_en ); + +else //if (CMD_PATTERN != "CGEN_BRAM") + + cmd_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse )); + + + +end + + + + + +assign cmd_clk_en = ( rdy_i & pipe_out_vld & run_traffic_i || mode_load_pulse && (CMD_PATTERN == "CGEN_BRAM")); + + + + + + + +integer i; + +always @ (posedge clk_i) + +if (rst_i[1]) + + bl_64 <= 1'b0; + +else if (data_mode_i == 7 || data_mode_i == 8 || data_mode_i == 9) + + bl_64 <= 1'b1; + +else + + bl_64 <= 1'b0; + + + + + + always @ (posedge clk_i) begin + + if (rst_i[1]) + + if (vio_instr_mode_value == 4'h7) + + pipe_data_in[31:0] <= #TCQ fixed_addr_i; + + else + + pipe_data_in[31:0] <= #TCQ start_addr_i; + + else if (instr_vld) + + // In order to simplify all different test pattern, the V6 generated + + // seed address from cmd_gen are aligned to burst length. The PRBS + + // burst length for write always 64 else it will break. + + // if (MEM_BURST_LEN == 8) + + if (data_mode_i == 5 || data_mode_i == 6) + + // for walking 1's / walking 0's pattern, the least 8 bits starting address + + // has to be all zero. This is to force the DQ pattern of each starting burst + + // starts from DQ0. + + if (FAMILY == "VIRTEX6") + + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'h00}; + + + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'h00}; // DWIDTH = 64 + + + + + + else if (data_mode_i == 4) + + // pipe_data_in[31:0] <= #TCQ {addr_out[31:3], 3'b000}; + + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'b000}; + + + + else if (bl_64) + + // nCK_PER_CLK = 4 && PRBS Length = 8 + + //force the least 11 bits starting address is always zero to align + + // PRBS sequence. + + if (nCK_PER_CLK == 4) + + if (FAMILY == "VIRTEX6") + + pipe_data_in[31:0] <= #TCQ {addr_out[31:11], 11'h000}; + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:9], 9'h000}; + + + + else + + if (FAMILY == "VIRTEX6") + + pipe_data_in[31:0] <= #TCQ {addr_out[31:10], 10'h000}; + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:9], 9'h000}; + + else if (gen_addr_larger && mem_init_done)// && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) + + pipe_data_in[31:0] <= #TCQ {end_addr_i[31:8],8'h0}; + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:2], 2'b00}; + + // else + + // pipe_data_in[31:0] <= #TCQ {addr_out[31:2],2'b00000}; + + + +end + + + +//end endgenerate + + + + + + always @ (posedge clk_i) begin + + if (rst_i[0]) + + force_wrcmd_gen <= #TCQ 1'b0; + + else if (buf_avail_r == 63) + + force_wrcmd_gen <= #TCQ 1'b0; + + else if (instr_vld_dly1 && pipe_data_in[32]== 1 && pipe_data_in[41:35] > 16) + + force_wrcmd_gen <= #TCQ 1'b1; + + end + +reg [3:0]instr_mode_reg; + + always @ (posedge clk_i) + + begin + + instr_mode_reg <= #TCQ instr_mode_i; + + end + + always @ (posedge clk_i) + + begin + + if (rst_i[2]) begin + + pipe_data_in[40:32] <= #TCQ 'b0; + + end + + else if (instr_vld) begin + + if (instr_mode_reg == 0) begin + + pipe_data_in[34:32] <= #TCQ instr_out; + + end + + else if (instr_out[2]) begin + + pipe_data_in[34:32] <= #TCQ 3'b100; + + end + + // + + else if ( FAMILY == "SPARTAN6" && PORT_MODE == "RD_MODE") + + begin + + pipe_data_in[34:32] <= #TCQ {instr_out[2:1],1'b1}; + + end + + + + else if ((force_wrcmd_gen || buf_avail_r <= 15) && FAMILY == "SPARTAN6" && PORT_MODE != "RD_MODE") + + begin + + pipe_data_in[34:32] <= #TCQ {instr_out[2],2'b00}; + + end + + else begin + + pipe_data_in[34:32] <= #TCQ instr_out; + + end + + + + //********* condition the generated bl value except if TG is programmed for BRAM interface' + + // if the generated address is close to end address range, the bl_out will be altered to 1. + + if (data_mode_i == 7 ) + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ bl_out; + + + + else if (data_mode_i == 4 ) + + + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd32; + + + + + + else + + if (gen_bl_larger && mem_pattern_init_done_i) // this condition is needed + + + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd8; + + else if (force_bl1 && mem_pattern_init_done_i) + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd2; // for V6 + + + + else + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ bl_out; // 8:2' 4:4 + + + + end //else instr_vld + + end // always + + + +reg COut; + + + +always @ (posedge clk_i) + +begin + + if (rst_i[2]) + + pipe_data_in[BL_WIDTH + 35] <= #TCQ 'b0; + + else if (cmd_vld) + + pipe_data_in[BL_WIDTH + 35] <= #TCQ instr_vld;//instr_vld; + + else if (rdy_i && pipe_out_vld) + + pipe_data_in[BL_WIDTH + 35] <= #TCQ 1'b0; + + end + + + + always @ (posedge clk_i) + + instr_vld_dly1 <= #TCQ instr_vld; + + + + + +reg COutA; + +always @ (posedge clk_i) begin + + if (rst_i[0]) begin + + rd_data_counts_asked <= #TCQ 'b0; + + end else if (instr_vld_dly1 && pipe_data_in[32]== 1) begin + + if (pipe_data_in[(BL_WIDTH +35):35] == 0) + + {COutA,rd_data_counts_asked} <= #TCQ rd_data_counts_asked + (10'd64) ; + + else + + {COutA,rd_data_counts_asked} <= #TCQ rd_data_counts_asked + (pipe_data_in[41:35]) ; + + + + end + + end + + + +always @ (posedge clk_i) begin + + if (rst_i[0]) begin + + rd_data_received_counts <= #TCQ 'b0; + + end else if(reading_rd_data_i) begin + + rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1; + + end + + end + + + + + +reg COut_d; + + always @ (posedge clk_i) + + if (FAMILY == "SPARTAN6") + + {COut_d, buf_avail_r} <= #TCQ ( rd_data_received_counts[6:0] - rd_data_counts_asked[6:0] + 7'd64); + + else // Virtex 6 MC has no need to generate such constraints . + + buf_avail_r <= #TCQ 8'd64; + + + +localparam BRAM_ADDR = 2'b00; + +localparam FIXED_ADDR = 2'b01; + +localparam PRBS_ADDR = 2'b10; + +localparam SEQUENTIAL_ADDR = 2'b11; + + + +// registered the mode settings + +always @ (posedge clk_i) begin + + if (rst_i[3]) + + if (CMD_PATTERN == "CGEN_BRAM") + + addr_mode_reg <= #TCQ 3'b000; + + else + + addr_mode_reg <= #TCQ 3'b011; + + else if (mode_load_pulse) + + addr_mode_reg <= #TCQ addr_mode_i; + +end + + + +always @ (posedge clk_i) begin + + if (mode_load_pulse) begin + + bl_mode_reg <= #TCQ bl_mode_i ; + + end + +// mode_load_d1 <= #TCQ mode_load_i; +// +// mode_load_d2 <= #TCQ mode_load_d1; + +end + +always @ (posedge clk_i) +begin + if (rst_i[0]) + begin + mode_load_d1 <= #TCQ 'b0; + mode_load_d2 <= #TCQ 'b0; + end + else + begin + mode_load_d1 <= #TCQ mode_load_i ; + mode_load_d2 <= #TCQ mode_load_d1 ; + end +end + + + +always @ (posedge clk_i) + + mode_load_pulse <= #TCQ mode_load_d1 & ~mode_load_d2; + + + +// MUX the addr pattern out depending on the addr_mode setting + + + +// "000" = bram; takes the address from bram output + +// "001" = fixed address from the fixed_addr input + +// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR + +// "011" = sequential + +// "100" = mode that used for prbs addr , prbs bl and prbs data + +//always @(addr_mode_reg,prbs_addr,seq_addr,fixed_addr,bram_addr_i,data_mode_i) + +always @ (posedge clk_i) begin + +if (rst_i[3]) + + + + addr_out <= #TCQ start_addr_i; + +else if (vio_instr_mode_value == 4'h7) + + addr_out <= #TCQ fixed_addr_i; + + + +else + + case({addr_mode_reg}) + + 3'b000: addr_out <= #TCQ bram_addr_i; + + 3'b001: addr_out <= #TCQ fixed_addr; + +// 3'b010: addr_out <= #TCQ {prbs_addr[31:10], 10'h00}; // this is specific to + + // data mode = PRBS + + + + 3'b010: if (FAMILY == "VIRTEX6") + + if (data_mode_i == 5) // ??? optimize this + + addr_out <= #TCQ {prbs_addr[31:BL_WIDTH+1], {BL_WIDTH+1{1'b0}}}; // this is specific to + + else + + addr_out <= #TCQ {prbs_addr[31:BL_WIDTH], {BL_WIDTH{1'b0}}}; // this is specific to + + else + + addr_out <= #TCQ {prbs_addr}; + + + + + + 3'b011: addr_out <= #TCQ {2'b0,seq_addr[29:0]}; + + 3'b100: addr_out <= #TCQ {3'b000,seq_addr[6:2],seq_addr[23:0]};//{prbs_addr[31:6],6'b000000} ; + + 3'b101: addr_out <= #TCQ {prbs_addr[31:20],seq_addr[19:0]} ; + + + + default : addr_out <= #TCQ 'b0; + + endcase + +end + + + +// ADDR PRBS GENERATION + +generate + +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) + + begin: gen_prbs_addr + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .TCQ (TCQ), + .FAMILY (FAMILY), + .ADDR_WIDTH (32), + .DWIDTH (DWIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .PRBS_WIDTH (32), + .SEED_WIDTH (32), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), + .PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS), + .PRBS_EADDR (PRBS_EADDR), + .PRBS_SADDR (PRBS_SADDR) + ) + + addr_prbs_gen + + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (mode_load_pulse), + + .prbs_seed_i (cmd_seed_i[31:0]), + + .prbs_o (prbs_addr) + + ); + + end + + else + + begin: no_prbs + + assign prbs_addr = 'b0; + + + + end + +endgenerate + + + +always @ (posedge clk_i) begin + +if (addr_out[31:8] >= end_addr_i[31:8]) + + gen_addr_larger <= 1'b1; + +else + + gen_addr_larger <= 1'b0; + +end + +wire [23:0] calc_end_addr /* synthesis syn_dspstyle = logic */ ; +assign calc_end_addr = (bl_out*(DWIDTH/8) + addr_out[31:8]) ; + +always @ (posedge clk_i) begin +if (instr_mode_i == 4 && mem_init_done) + gen_bl_larger <= 1'b0; + +else if ( calc_end_addr >= end_addr_i[31:8] ) + gen_bl_larger <= 1'b1; +else + gen_bl_larger <= 1'b0; +end + + + +//converting string to integer + +//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4; + +localparam MEM_BURST_INT = MEM_BURST_LEN ; + + +generate + +if (FAMILY == "SPARTAN6") begin : INC_COUNTS_S + + always @ (posedge clk_i) + + if (mem_init_done) + INC_COUNTS <= #TCQ (DWIDTH/8)*(bl_out_reg); + else begin + if (fixed_bl_i == 0) + INC_COUNTS <= #TCQ (DWIDTH/8)*(64); + else + INC_COUNTS <= #TCQ (DWIDTH/8)*(fixed_bl_i); + end + + end + +else begin : INC_COUNTS_V + + always @ (posedge clk_i) begin + if (rst_i[3]) begin + INC_COUNTS[BL_WIDTH-1:0] <= fixed_bl_i * (DWIDTH)/16; + INC_COUNTS[BL_WIDTH+2:BL_WIDTH] <= 'b0; + end + else + if (nCK_PER_CLK == 4 && MEM_BURST_LEN != 2) + INC_COUNTS <= #TCQ (bl_out << LOGB2_MEM_BURST_INT); + else begin + if (MEM_TYPE != "QDR2PLUS") begin //nCK_PER_CK == 2 + if (MEM_BURST_LEN == 8 || MEM_BURST_LEN == 2) // 13:11 + INC_COUNTS <= #TCQ (bl_out << (LOGB2_MEM_BURST_INT - 1)); + else + INC_COUNTS <= #TCQ (bl_out << LOGB2_MEM_BURST_INT); + end + else begin + INC_COUNTS[BL_WIDTH-1:0] <= #TCQ bl_out; + INC_COUNTS[BL_WIDTH+2:BL_WIDTH] <= 'b0; + end + end + end + +end + +endgenerate + + +generate + +// Sequential Address pattern +// It is generated when rdy_i is valid and write command is valid and bl_cmd is valid. +if (CMD_PATTERN == "CGEN_SEQUENTIAL" || CMD_PATTERN == "CGEN_ALL" ) + + begin : seq_addr_gen + + assign seq_addr = addr_counts; + + always @ (posedge clk_i) + begin + + if (rst_i[2]) + + first_mode_load_pulse_set <= 1'b0; + + else if (mode_load_pulse_r1) + + first_mode_load_pulse_set <= #TCQ 1'b1; + end + + always @ (posedge clk_i) + begin + + mode_load_pulse_r1 <= #TCQ mode_load_pulse; + first_mode_load_pulse_r1 <= #TCQ mode_load_pulse & ~first_mode_load_pulse_set; + end + + always @ (posedge clk_i) + begin + + if (rst_i[4]) + + mem_init_done_r <= #TCQ 1'b0 ; + + else if (cmd_clk_en_r) + + mem_init_done_r <= #TCQ mem_init_done ; + end + + + reg COut_b,COut_c; + wire [32:0] addr_counts_added; + assign addr_counts_added = addr_counts + INC_COUNTS /* synthesis syn_dspstyle = logic */ ; + + always @ (posedge clk_i) + + addr_counts_next_r <= #TCQ addr_counts_added ; + + + always @ (posedge clk_i) + + cmd_clk_en_r <= #TCQ cmd_clk_en; + + + always @ (posedge clk_i) + begin + + if (rst_i[4]) begin + + addr_counts <= #TCQ start_addr_i; + mem_init_done <= #TCQ 1'b0; + + end + + else if (cmd_clk_en_r || first_mode_load_pulse_r1) + + if(addr_counts_next_r >= end_addr_i ) begin + + addr_counts <= #TCQ start_addr_i; + mem_init_done <= #TCQ 1'b1; + + end + + else // address counts get incremented by burst_length and port size each wr command generated + + {COut_c,addr_counts} <= #TCQ addr_counts_added ; + end + + end + + else + + begin: no_gen_seq_addr + + assign seq_addr = 'b0; + + end + +endgenerate + +always @ (posedge clk_i) begin + + if (rst_i[4]) + + n_gen_write_only <= 1'b0; + + else if (~n_gen_write_only && addr_counts_next_r>= end_addr_i) + + n_gen_write_only <= 1'b1; + + + + else if(addr_counts_next_r>= end_addr_i && instr_out[0] == 1'b0) + + n_gen_write_only <= 1'b0; +end + +generate + +// Fixed Address pattern +if (CMD_PATTERN == "CGEN_FIXED" || CMD_PATTERN == "CGEN_ALL" ) + + begin : fixed_addr_gen + + assign fixed_addr = (DWIDTH == 32)? {fixed_addr_i[31:2],2'b0} : + + (DWIDTH == 64)? {fixed_addr_i[31:3],3'b0}: + + (DWIDTH <= 128)? {fixed_addr_i[31:4],4'b0}: + + (DWIDTH <= 256)? {fixed_addr_i[31:5],5'b0}: + + {fixed_addr_i[31:6],6'b0}; + + end + +else + + begin : no_fixed_addr_gen + + assign fixed_addr = 'b0; + + end + +endgenerate + + +generate + +// BRAM Address pattern +if (CMD_PATTERN == "CGEN_BRAM" || CMD_PATTERN == "CGEN_ALL" ) + + begin : bram_addr_gen + + assign bram_rdy_o = run_traffic_i & cmd_clk_en & bram_valid_i | mode_load_pulse; + + end + +else + + begin: no_bram_addr_gen + + assign bram_rdy_o = 1'b0; + + end + +endgenerate + + + +/////////////////////////////////////////////////////////////////////////// + +// INSTR COMMAND GENERATION + + + +// tap points are 3,2 + +//`define RD 3'b001 + +//`define RDP 3'b011 + +//`define WR 3'b000 + +//`define WRP 3'b010 + +//`define REFRESH 3'b100 + +// use 14 stages 1 sr16; tap position 1,3,5,14 + + + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + force_rd_counts <= #TCQ 'b0; + +else if (instr_vld) begin + + force_rd_counts <= #TCQ force_rd_counts + 1'b1; + + end + +end + + + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + force_rd <= #TCQ 1'b0; + +else if (force_rd_counts[3]) + + force_rd <= #TCQ 1'b1; + +else + + force_rd <= #TCQ 1'b0; + +end + +// adding refresh timer to limit the amount of issuing refresh command. + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + refresh_timer <= #TCQ 'b0; + +else + + refresh_timer <= #TCQ refresh_timer + 1'b1; + +end + + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + refresh_cmd_en <= #TCQ 'b0; + +//else if (refresh_timer >= 12'hff0 && refresh_timer <= 12'hfff) + +else if (refresh_timer == 10'h3ff) + + refresh_cmd_en <= #TCQ 'b1; + +else if (cmd_clk_en && refresh_cmd_en) + + refresh_cmd_en <= #TCQ 'b0; +end + +always @ (posedge clk_i) begin + +if (FAMILY == "SPARTAN6") + + refresh_prbs <= #TCQ prbs_instr_b[3] & refresh_cmd_en; + +else + + refresh_prbs <= #TCQ 1'b0; + +end + +always @ (posedge clk_i) +begin +if (rst_i[4]) + write_percent_cnt <= 'b0; +else if (cmd_clk_en_r) + if ( write_percent_cnt == 9) + write_percent_cnt <= 'b0; + else + write_percent_cnt <= write_percent_cnt + 1'b1; +end +always @ (posedge clk_i) +begin +if (rst_i[4]) + toggle_rw <= 1'b0; +else if (cmd_clk_en_r && mem_init_done) + if (write_percent_cnt >= vio_percent_write) + toggle_rw <= 1'b1; + else + toggle_rw <= 1'b0; +end + +always @ (posedge clk_i) begin + + case(instr_mode_i) + + 0: instr_out <= #TCQ bram_instr_i; + + 1: instr_out <= #TCQ fixed_instr_i; + + 2: instr_out <= #TCQ {2'b00,(prbs_instr_a[0] | force_rd)}; + 3: instr_out <= #TCQ {2'b00,prbs_instr_a[0]}; //: WP/RP + 4: instr_out <= #TCQ {2'b00,toggle_rw}; // percent write + + + // may be add another PRBS for generating REFRESH + +// 5: instr_out <= #TCQ {prbs_instr_b[3],prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH + + 5: instr_out <= #TCQ {refresh_prbs ,prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH + + + + + + default : instr_out <= #TCQ {2'b00,1'b1}; + + endcase + +end + + + +generate // PRBS INSTRUCTION generation + +// use two PRBS generators and tap off 1 bit from each to create more randomness for + +// generating actual read/write commands + +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) + + begin: gen_prbs_instr + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .TCQ (TCQ), + + .PRBS_CMD ("INSTR"), + + .DWIDTH (DWIDTH), + + + + .ADDR_WIDTH (32), + + .SEED_WIDTH (15), + + .PRBS_WIDTH (20) + + ) + + instr_prbs_gen_a + + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (load_seed_i), + + .prbs_seed_i (cmd_seed_i[14:0]), + + .prbs_o (prbs_instr_a) + + ); + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .PRBS_CMD ("INSTR"), + + .DWIDTH (DWIDTH), + + + + .SEED_WIDTH (15), + + .PRBS_WIDTH (20) + + ) + instr_prbs_gen_b + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (load_seed_i), + + .prbs_seed_i (cmd_seed_i[16:2]), + + .prbs_o (prbs_instr_b) + + ); + + end + + else + + begin: no_prbs_instr_gen + + assign prbs_instr_a = 'b0; + + assign prbs_instr_b = 'b0; + + end + +endgenerate + + + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// BURST LENGTH GENERATION + +// burst length code = user burst length input - 1 + +// mcb_flow_control does the minus before sending out to mcb\ + +// when filling up the memory, need to make sure bl doesn't go beyound its upper limit boundary + +//assign force_bl1 = (addr_out[31:0] >= (end_addr_i[31:0] - 4*64)) ? 1'b1: 1'b0; + +// for neighbour pattern, need to limit the bl to make sure it is within column size boundary. + + + +// This is required in S6 . + + + +always @ (posedge clk_i) + +begin + +if (rst_i[4] ) + + cal_blout <= 'b0; + +else + + cal_blout <= bl_out* (DWIDTH/8); + +end + +wire [31:0] dummy; +wire [32:0] dummy_sub; + +assign dummy = (addr_out + cal_blout); +assign dummy_sub = (dummy - end_addr_i); + +always @(*) begin + + force_bl1 = 1'b0; + if (rst_i[6] || (mem_init_done && instr_mode_i == 4)) + force_bl1 = 1'b0; + else if ((dummy_sub[32] == 0) || (buf_avail_r <= 50 && PORT_MODE == "RD_MODE")) + force_bl1 = 1'b1; + +end + +//always @(addr_out,mem_init_done, instr_mode_i,bl_out,cal_blout,end_addr_i,rst_i,buf_avail_r,bl_x_DWIDTH_BY_8) begin + +// if (rst_i[6]) +// force_bl1 = 1'b0; +// else if (mem_init_done && instr_mode_i == 4) +// force_bl1 = 1'b0; + +// else if (((addr_out + cal_blout) >= end_addr_i) || (buf_avail_r <= 50 && PORT_MODE == "RD_MODE")) + +// force_bl1 = 1'b1; + +// else + +// force_bl1 = 1'b0; +//end + +always @(posedge clk_i) begin + + if (rst_i[6]) + + bl_out_reg <= #TCQ fixed_bl_i; + + else if (bl_out_vld) + + bl_out_reg <= #TCQ bl_out; + +end + +// BurstLength defination in Traffic Gen is the consecutive write/read commands + +// that sent to Memory Controller User Interface. In V6, cmd_gen module sends + +// the number of burst length to rd_data_gen, wr_data_gen and mcb_flow_control_v6. + +// The mcb_flow_control takes the base address of the first burst and the bl value, + +// it automatically increment the next consecutive address of the back-to-back commands + +// until the burst counts decrement to 0. + +//verilint STARC-2.2.3.3 off +always @ (posedge clk_i) begin + + if (mode_load_pulse || rst_i[3]) + + if (data_mode_i == 4) + + bl_out <= #TCQ 10'd32 ; + + else + + bl_out <= #TCQ fixed_bl_i ; + + else if (cmd_clk_en) begin + + case({bl_mode_reg}) + + 0: begin + + bl_out[5:0] <= #TCQ bram_bl_i ; + + bl_out[BL_WIDTH-1:6] <= #TCQ 'b0 ; + + + + end + + 1: if (data_mode_i == 4) + + bl_out <= #TCQ 10'd32 ; + + else + + bl_out <= #TCQ fixed_bl_i ; + + 2: bl_out <= #TCQ prbs_brlen; + + default : begin + + bl_out[5:0] <= #TCQ 6'h1; + + bl_out[BL_WIDTH - 1:6] <= #TCQ 'b0; + + + + end + + endcase + + end + +end +//verilint STARC-2.2.3.3 off + + + //synthesis translate_off + +//always @ (bl_out) + +// if(bl_out >2 && FAMILY == "VIRTEX6") begin + +// $display("Error ! Not valid burst length"); + +// $stop; + +// end + + //synthesis translate_on + + + +generate + +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) + + begin: gen_prbs_bl + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .TCQ (TCQ), + + .FAMILY (FAMILY), + + .PRBS_CMD ("BLEN"), + + .ADDR_WIDTH (32), + + .SEED_WIDTH (15), + + .PRBS_WIDTH (20) + + ) + + bl_prbs_gen + + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (load_seed_i), + + .prbs_seed_i (cmd_seed_i[16:2]), + + .prbs_o (prbs_bl) + + ); + + + + always @ (prbs_bl) + + if (FAMILY == "SPARTAN6" || FAMILY == "MCB") // supports 1 throug 64 + + prbs_brlen[5:0] = (prbs_bl[5:1] == 5'b00000) ? 6'b000010: {prbs_bl[5:1],1'b0}; + + else // VIRTEX6 only supports 1 or 2 burst on user ports + + prbs_brlen = (prbs_bl[BL_WIDTH-1:1] == 5'b00000) ? {{BL_WIDTH-2{1'b0}},2'b10}: {prbs_bl[BL_WIDTH-1:1],1'b0}; + + end + + else + + begin: no_gen_prbs_bl + + assign prbs_bl = 'b0; + + end + +endgenerate + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v new file mode 100644 index 0000000..d018c52 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v @@ -0,0 +1,268 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: cmd_prbs_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This moduel use LFSR to generate random address, isntructions +// or burst_length. +//Reference: +//Revision History: 1.1 7/9/2009 Added condition to zero out the LSB address bits according to +// DWIDTH and FAMILY. 7/9/2009 +// 1.2 11/8/2010 Fixed the PRBS Address generation. +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_cmd_prbs_gen # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter MEM_BURST_LEN = 8, + parameter ADDR_WIDTH = 29, + parameter DWIDTH = 32, + parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS" + parameter PRBS_WIDTH = 64, // 64,15,20 + parameter SEED_WIDTH = 32, // 32,15,4 + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + parameter PRBS_EADDR = 32'h00002000, + parameter PRBS_SADDR = 32'h00002000 + ) + ( + input clk_i, + input prbs_seed_init, // when high the prbs_x_seed will be loaded + input clk_en, + input [SEED_WIDTH-1:0] prbs_seed_i, + + output[SEED_WIDTH-1:0] prbs_o // generated address + ); + +wire[ADDR_WIDTH - 1:0] ZEROS; +reg [SEED_WIDTH - 1:0] prbs; +reg [PRBS_WIDTH :1] lfsr_q; + +assign ZEROS = 'b0; + + +function integer logb2; + input integer number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end +endfunction + + +// +//************************************************************** +//#################################################################################################################### +// # +// # +// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} # +// upper 32 bits are loadable # +// # +// +// +// ........................................................................................ +// ^ ^ ^ ^ | +// | ____ | ___ ___ | ___ | ___ ___ ___ | +// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable. +// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<-- +// |___| --- |___| |___| --- |___| --- |___|...|___| |___| +// +// +// <<-- shifting -- +//##################################################################################################################### + +// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages. +// we need to provide 30 bits addres. SRLC32 has only one bit output. +// address seed will be loaded to upper 32 bits. +// +// parallel load and serial shift out to LFSR during INIT time + +generate + if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) + begin :gen64_taps + always @ (posedge clk_i) begin + if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {31'b0,prbs_seed_i}; + end else if(clk_en) begin + lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63]; + lfsr_q[63] <= #TCQ lfsr_q[62]; + lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61]; + lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60]; + lfsr_q[60:2] <= #TCQ lfsr_q[59:1]; + lfsr_q[1] <= #TCQ lfsr_q[64]; + end + end + + always @(lfsr_q[32:1]) begin + prbs = lfsr_q[32:1]; + end + end +//endgenerate +//generate +else if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) + begin :gen32_taps + always @ (posedge clk_i) begin + if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {prbs_seed_i}; + end else if(clk_en) begin + lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + end + end + + integer i; + always @(lfsr_q[32:1]) begin + + if (FAMILY == "SPARTAN6" ) begin // for 32 bits + + for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1) + + if(PRBS_SADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; + else if(PRBS_EADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; + else + prbs[i] = lfsr_q[i+1]; + + prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}}; + + end + else begin + for(i = logb2(MEM_BURST_LEN) - 2; i <= SEED_WIDTH - 1; i = i + 1) + // for(i = 3; i <= SEED_WIDTH - 1; i = i + 1) + +// BL8: 0,8 +//BL4: incremnt by 4 +// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1) + + if(PRBS_SADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; + else if(PRBS_EADDR_MASK_POS[i] == 0) + prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; + else + prbs[i] = 1'b0;// lfsr_q[i+1]; + // 3 1 + prbs[logb2(MEM_BURST_LEN)-3:0] = 'b0;//{logb2(MEM_BURST_LEN) -3{1'b0}}; + // prbs[2:0] = {3{1'b0}}; + + + end + + end +end +//endgenerate + +////////////////////////////////////////////////////////////////////////// +//#################################################################################################################### +// # +// # +// 15 taps: [15,14]: # +// # +// # +// +// +// ............................................................. +// ^ ^ . ^ +// | ____ | ___ ___ ___ ___ ___ | +// | | | |---|<- | | | | | |...| | | | | +// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<-- +// |___| --- |___| |___| |___|...|___| |___| +// +// +// <<-- shifting -- +//##################################################################################################################### + +//generate +// if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") +else + begin :gen20_taps + always @(posedge clk_i) begin + if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]}; + end else if(clk_en) begin + lfsr_q[20] <= #TCQ lfsr_q[19]; + lfsr_q[19] <= #TCQ lfsr_q[18]; + + lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17]; + + lfsr_q[17:2] <= #TCQ lfsr_q[16:1]; + lfsr_q[1] <= #TCQ lfsr_q[20]; + end + end + + always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin + prbs = {ZEROS[SEED_WIDTH - 1:6],lfsr_q[6:1]}; + end + end +endgenerate + +assign prbs_o = prbs; + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v new file mode 100644 index 0000000..70f5039 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v @@ -0,0 +1,128 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: data_prbs_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module is used LFSR to generate random data for memory +// data write or memory data read comparison.The first data is +// seeded by the input prbs_seed_i which is connected to memory address. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_data_prbs_gen # + ( + parameter TCQ = 100, + + parameter EYE_TEST = "FALSE", + parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" + parameter SEED_WIDTH = 32 + ) + ( + input clk_i, + input clk_en, + input rst_i, + input prbs_seed_init, // when high the prbs_x_seed will be loaded + input [PRBS_WIDTH - 1:0] prbs_seed_i, + + output [PRBS_WIDTH - 1:0] prbs_o // generated address + ); + +reg [PRBS_WIDTH - 1 :0] prbs; +reg [PRBS_WIDTH :1] lfsr_q; +integer i; + + + +always @ (posedge clk_i) +begin + if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up +// if (rst_i ) //reset it to a known good state to prevent it locks up + + begin + lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; + // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; + + lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; + end + else if (clk_en) begin + + lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + + + end +end + +always @ (lfsr_q[PRBS_WIDTH:1]) begin + prbs = lfsr_q[PRBS_WIDTH:1]; +end + +assign prbs_o = prbs; + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_init_mem_pattern_ctr.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_init_mem_pattern_ctr.v new file mode 100644 index 0000000..4fd543b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_init_mem_pattern_ctr.v @@ -0,0 +1,2117 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: init_mem_pattern_ctr.v +// /___/ /\ Date Last Modified: $Date: 2011/02/24 00:08:32 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This moduel has a small FSM to control the operation of +// memc_traffic_gen module.It first fill up the memory with a selected +// DATA pattern and then starts the memory testing state. +//Reference: +//Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE +// and the fixed_bl_o is fixed at 64 if data_mode_o == PRBA and FAMILY == "SPARTAN6" +// The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH. +// 1.2 10-1-2009 Added parameter TST_MEM_INSTR_MODE to select instruction pattern during +// memory testing phase. +// 1.3 1-4-2012 Fixed end address logic if defined END_ADDRESS == 0x0FFFFFFF. +//***************************************************************************** + + + +`timescale 1ps/1ps + + + + + + + + + + + +module mig_7series_v4_2_init_mem_pattern_ctr # + + ( + + parameter SIMULATION = "FALSE", + + parameter TCQ = 100, + + parameter FAMILY = "SPARTAN6", // VIRTEX6, SPARTAN6 + + parameter MEM_TYPE = "DDR3",//DDR3,DDR2, QDR2PLUS, + + + + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands: + + // "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE" + + // "R_W_INSTR_MODE", "RP_WP_INSTR_MODE + + // "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE" + + // ******************************* + + // Virtex 6 Available commands: + + // "FIXED_INSTR_R_MODE" - Only Read commands will be generated. + + // "FIXED_INSTR_W_MODE" -- Only Write commands will be generated. + + // "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated + + // with lower 10 bits address in sequential increment. + + // This mode is for Read Eye measurement. + + + + // "R_W_INSTR_MODE" - Random Read/Write commands will be generated. + + parameter MEM_BURST_LEN = 8, // VIRTEX 6 Option. + + parameter nCK_PER_CLK = 4, + + parameter BL_WIDTH = 10, + + parameter NUM_DQ_PINS = 4, // Total number of memory dq pins in the design. + + + + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_ALL" option generates all available + + // commands pattern. + + parameter BEGIN_ADDRESS = 32'h00000000, + + parameter END_ADDRESS = 32'h00000fff, + + parameter ADDR_WIDTH = 30, + + parameter DWIDTH = 32, + + parameter CMD_SEED_VALUE = 32'h12345678, + + parameter DATA_SEED_VALUE = 32'hca345675, + + parameter DATA_MODE = 4'b0010, + + parameter PORT_MODE = "BI_MODE", // V6 Option: "BI_MODE"; SP6 Option: "WR_MODE", "RD_MODE", "BI_MODE" + + parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory + + // signals. It overwrites the TST_MEM_INSTR_MODE setting. + + // Traffic Generator will onlywrite to one single location and no + + // read transactions will be generated. + + + + + + ) + + ( + + input clk_i, + + input rst_i, + + + + input single_write_button, + + input single_read_button, + + input slow_write_read_button, + + input single_operation, // tie this signal to '1' if want to do single operation + + + + input memc_cmd_en_i, + + input memc_wr_en_i, + + input vio_modify_enable, // 0: default to ADDR as DATA PATTERN. No runtime change in data mode. + + // 1: enable exteral VIO to control the data_mode pattern + + input [3:0] vio_instr_mode_value, // "0000" = Fixed + + // "0001" = bram; takes instruction from bram output + + // "0010" = R/W + + // "0011" = RP/WP + + // "0100" = R/RP/W/WP + + // "0101" = R/RP/W/WP/REF + + // "0111" = Single Step + + + + // and address mode pattern during runtime. + + input [3:0] vio_data_mode_value, + + input [2:0] vio_addr_mode_value, + + + + + + + + + + + + + + input [1:0] vio_bl_mode_value, + + input vio_data_mask_gen, + + input [2:0] vio_fixed_instr_value, + + input [BL_WIDTH - 1:0] vio_fixed_bl_value, // valid range is: from 1 to 64. + + + + input memc_init_done_i, + + input cmp_error, + + output reg run_traffic_o, + + // runtime parameter + + output [31:0] start_addr_o, // define the start of address + + output [31:0] end_addr_o, + + output [31:0] cmd_seed_o, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen + + output [31:0] data_seed_o, + + output reg load_seed_o, // + + // upper layer inputs to determine the command bus and data pattern + + // internal traffic generator initialize the memory with + + output reg [2:0] addr_mode_o, // "00" = bram; takes the address from bram output + + // "001" = fixed address from the fixed_addr input + + // "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR + + // "011" = sequential + + + + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + + output reg [3:0] instr_mode_o, // "0000" = Fixed + + // "0001" = bram; takes instruction from bram output + + // "0010" = R/W + + // "0011" = RP/WP + + // "0100" = R/RP/W/WP + + // "0101" = R/RP/W/WP/REF + + // "0111" = Single Step + + // "1111" = Debug Read Only, bypass memory initialization + + + + output reg [1:0] bl_mode_o, // "00" = bram; takes the burst length from bram output + + // "01" = fixed , takes the burst length from the fixed_bl input + + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + + + output reg [3:0] data_mode_o, // "00" = bram; + + // "01" = fixed data from the fixed_data input + + // "10" = psuedo ramdom pattern; generated from internal 32 bit LFSR + + // "11" = sequential using the addrs as the starting data pattern + + output reg mode_load_o, + + + + // fixed pattern inputs interface + + output reg [BL_WIDTH-1:0] fixed_bl_o, // range from 1 to 64 + + output reg [2:0] fixed_instr_o, //RD 3'b001 + + //RDP 3'b011 + + //WR 3'b000 + + //WRP 3'b010 + + //REFRESH 3'b100 + + output reg mem_pattern_init_done_o + + + + ); + + + + //FSM State Defination + +parameter IDLE = 8'b00000001, + + + + INIT_MEM_WRITE = 8'b00000010, + + INIT_MEM_READ = 8'b00000100, + + TEST_MEM = 8'b00001000, + + SINGLE_STEP_WRITE = 8'b00010000, //0x10 + + SINGLE_STEP_READ = 8'b00100000, //0x20 + + CMP_ERROR = 8'b01000000, + + SINGLE_CMD_WAIT = 8'b10000000; + + + + + +localparam BRAM_ADDR = 3'b000; + +localparam FIXED_ADDR = 3'b001; + +localparam PRBS_ADDR = 3'b010; + +localparam SEQUENTIAL_ADDR = 3'b011; + + + +localparam BRAM_INSTR_MODE = 4'b0000; + +localparam FIXED_INSTR_MODE = 4'b0001; + +localparam R_W_INSTR_MODE = 4'b0010; + +localparam RP_WP_INSTR_MODE = 4'b0011; + +localparam R_RP_W_WP_INSTR_MODE = 4'b0100; + +localparam R_RP_W_WP_REF_INSTR_MODE = 4'b0101; + + + +localparam BRAM_BL_MODE = 2'b00; + +localparam FIXED_BL_MODE = 2'b01; + +localparam PRBS_BL_MODE = 2'b10; + + + +localparam BRAM_DATAL_MODE = 4'b0000; + +localparam FIXED_DATA_MODE = 4'b0001; + +localparam ADDR_DATA_MODE = 4'b0010; + +localparam HAMMER_DATA_MODE = 4'b0011; + +localparam NEIGHBOR_DATA_MODE = 4'b0100; + +localparam WALKING1_DATA_MODE = 4'b0101; + +localparam WALKING0_DATA_MODE = 4'b0110; + +localparam PRBS_DATA_MODE = 4'b0111; + + + +// type fixed instruction + +localparam RD_INSTR = 3'b001; + +localparam RDP_INSTR = 3'b011; + +localparam WR_INSTR = 3'b000; + + + +localparam WRP_INSTR = 3'b010; + +localparam REFRESH_INSTR = 3'b100; + +localparam NOP_WR_INSTR = 3'b101; + +//(* FSM_ENCODING="USER" *) reg [6:0] STATE = current_state; + +reg [7:0] current_state; + +reg [7:0] next_state; + +reg memc_init_done_reg; + +reg AC2_G_E2,AC1_G_E1,AC3_G_E3; + +reg upper_end_matched; + +reg [31:0] end_boundary_addr; + + + +reg memc_cmd_en_r; + +reg lower_end_matched; + +reg end_addr_reached; + +reg run_traffic; + +reg bram_mode_enable; + +reg [31:0] current_address; + +reg [BL_WIDTH-1:0] fix_bl_value; + +reg [3:0] data_mode_sel; + +reg [1:0] bl_mode_sel; + +reg [2:0] addr_mode; + +reg [10:0] INC_COUNTS; + +wire [3:0] test_mem_instr_mode; + +reg pre_instr_switch; + +reg switch_instr; + +reg memc_wr_en_r; + +reg mode_load_d1,mode_load_d2,mode_load_pulse; + +reg mode_load_d3,mode_load_d4,mode_load_d5; + + + +always @ (posedge clk_i) begin + + mode_load_d1 <= #TCQ mode_load_o; + + mode_load_d2 <= #TCQ mode_load_d1; + + mode_load_d3 <= #TCQ mode_load_d2; + + mode_load_d4 <= #TCQ mode_load_d3; + + mode_load_d5 <= #TCQ mode_load_d4; + + + +end + + + +always @ (posedge clk_i) + + mode_load_pulse <= #TCQ mode_load_d4 & ~mode_load_d5; + + + + + +always @ (TST_MEM_INSTR_MODE, EYE_TEST) + +if ((TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || TST_MEM_INSTR_MODE == "R_W_INSTR_MODE" || + + TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" || TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" || + + TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" || TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE" ) + + && (EYE_TEST == "TRUE")) + +begin: Warning_Message1 + +$display("Invalid Parameter setting! When EYE_TEST is set to TRUE, only WRITE commands can be generated."); + + + +$stop; + +end + +else + +begin: NoWarning_Message1 + + + +end + +always @ (TST_MEM_INSTR_MODE) + +if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "SPARTAN6") + +begin + +$display("Error ! Not supported test instruction mode in Spartan 6"); + + + +$stop; + +end + +else + +begin + + // dummy + +end + + + + + + + +always @ (vio_fixed_bl_value,vio_data_mode_value) + +if (vio_fixed_bl_value[6:0] > 7'd64 && FAMILY == "SPARTAN6") + +begin + +$display("Error ! Maximum User Burst Length is 64"); + +$display("Change a smaller burst size"); + + + +$stop; + +end + +else if ((vio_data_mode_value == 4'h6 || vio_data_mode_value == 4'h5) && FAMILY == "VIRTEX6") + +begin + + $display("Data DQ bus Walking 1's test."); + + $display("A single DQ bit is set to 1 and walk through entire DQ bus to test "); + + $display("if each DQ bit can be set to 0 or 1 "); + + + + if (NUM_DQ_PINS == 8)begin + + $display("Warning ! Fixed Burst Length in this mode is forced to 64"); + + $display("to ensure '1' always appear on DQ0 of each beginning User Burst"); + + end + + else begin + + $display("Warning ! Fixed Burst Length in this mode is forced to equal to NUM_DQ_PINS"); + + $display("to ensure '1' always appear on DQ0 of each beginning User Burst"); + + end + + + +end + +else + +begin// dummy + + + +end + + + +always @ (data_mode_o) + +if (data_mode_o == 4'h7 && FAMILY == "SPARTAN6") + +begin + + $display("Error ! Hammer PRBS is not support in MCB-like interface"); + + $display("Set value to 4'h8 for Psuedo PRBS"); + + $stop; + +end + + + +else + +begin + + // dummy + +end + + + +//always @ (vio_data_mode_value,TST_MEM_INSTR_MODE) + +//if (TST_MEM_INSTR_MODE != "FIXED_INSTR_R_MODE" && + +// vio_data_mode_value == 4'b1000) + +//begin + +//$display("Error ! The selected PRBS data pattern has to run together with FIXED_INSTR_R_MODE"); + +//$display("Set the TST_MEM_INSTR_MODE = FIXED_INSTR_R_MODE and addr_mode to sequential mode"); + +//$stop; + +//end + + + +assign test_mem_instr_mode = (vio_instr_mode_value[3:2] == 2'b11) ? 4'b1111: + + (vio_instr_mode_value[3:2] == 2'b10) ? 4'b1011: + + (TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE") ? 4'b0000: + + (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || + + TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") ? 4'b0001: + + (TST_MEM_INSTR_MODE == "R_W_INSTR_MODE") ? 4'b0010: + + (TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0011: + + (TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0100: + + (TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0101: + + 4'b0010; + + + + + + + + always @ (posedge clk_i) + + begin + + if (data_mode_o == 4) + + begin + + fix_bl_value[4:0] <= 5'd8;//Simple_Data_MODE; + + fix_bl_value[BL_WIDTH-1:5] <= 'b0; + + end + + else if (data_mode_o == 5 || data_mode_o == 6 ) + if (MEM_TYPE == "RLD3" && vio_modify_enable) + fix_bl_value <= vio_fixed_bl_value; + else + + if (NUM_DQ_PINS == 8) + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + end + + else + + fix_bl_value <= NUM_DQ_PINS;//Waling 1's or 0's; + + else if (data_mode_o == 8) + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + + + end + + + + else if (vio_modify_enable == 1'b1) + + if (vio_fixed_bl_value == 0) // not valid value; + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + + + end + + else begin + + fix_bl_value <= vio_fixed_bl_value; + + + + end + + else + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + + + end + + + + end + + + + + +generate + +if (FAMILY == "SPARTAN6" ) + +begin : INC_COUNTS_S + + + +always @ (posedge clk_i) + + INC_COUNTS <= (DWIDTH/8); + +end + +else // VIRTEX 6 + +begin : INC_COUNTS_V + +always @ (posedge clk_i) + if (MEM_TYPE == "QDR2PLUS") + INC_COUNTS <= 1;// Each address is associated with 4 words in QDR2. + else + INC_COUNTS <= MEM_BURST_LEN; +end + +endgenerate + + + + + +// In V6, each write command in MEM_BLEN = 8, TG writes 8 words of DQ width data to the accessed location. + +// For MEM_BLEN = 4, TG writes 4 words of DQ width data to the accessed location. + +reg Cout_b; + +always @ (posedge clk_i) + +begin + +if (rst_i) + + current_address <= BEGIN_ADDRESS; + +else if (memc_wr_en_r && (current_state == INIT_MEM_WRITE && (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")) + + || (memc_wr_en_r && (current_state == IDLE && PORT_MODE == "RD_MODE")) ) + +// ** current_address stops incrementing when reaching the beginning of last END_ADDRESS write burst. + {Cout_b,current_address} <= current_address + INC_COUNTS; + +else + + current_address <= current_address; + + + +end + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + AC3_G_E3 <= 1'b0; + + else if (current_address[29:24] >= end_boundary_addr[29:24]) + + AC3_G_E3 <= 1'b1; + + else + + AC3_G_E3 <= AC3_G_E3; + + + + if (rst_i) + + AC2_G_E2 <= 1'b0; + + else if (current_address[23:16] >= end_boundary_addr[23:16]) + AC2_G_E2 <= AC3_G_E3; + + else + + AC2_G_E2 <= AC2_G_E2; + + + + + + if (rst_i) + + AC1_G_E1 <= 1'b0; + + else if (current_address[15:8] >= end_boundary_addr[15:8] ) + AC1_G_E1 <= AC2_G_E2 & AC3_G_E3; + +else + + AC1_G_E1 <= AC1_G_E1; + + + + + +end + +always @(posedge clk_i) + +begin + +if (rst_i) + + upper_end_matched <= 1'b0; + + + +else if (memc_cmd_en_i) + + upper_end_matched <= AC3_G_E3 & AC2_G_E2 & AC1_G_E1; + +else + + upper_end_matched <= upper_end_matched; + + + +end + + + + + + //synthesis translate_off + +always @ (fix_bl_value) + + if(fix_bl_value * MEM_BURST_LEN > END_ADDRESS) + + begin + + $display("Error ! User Burst Size goes beyond END Address"); + + $display("decrease vio_fixed_bl_value or increase END Address range"); + + $stop; + + end + + else + + begin + + // dummy + + + + end + + + + + +always @ (vio_data_mode_value, vio_data_mask_gen) + + if(vio_data_mode_value != 4'b0010 && vio_data_mask_gen) + + begin + + $display("Error ! Data Mask Generation only supported in Data Mode = Address as Data"); + + $stop; + + end + + else + + begin + + // dummy + + + + end + + + + //synthesis translate_on + + + +reg COuta; + +always @(posedge clk_i) + +begin + // **end_boundary_addr defination is the beginning address of the last write burst of END_ADDRESS + {COuta,end_boundary_addr} <= (END_ADDRESS[31:0] - {{32-BL_WIDTH{1'b0}} ,fix_bl_value } +1) ; + +end + + + + + + + +always @(posedge clk_i) + +begin + + if ((current_address[7:4] >= END_ADDRESS[7:4]) && MEM_TYPE == "QDR2PLUS") + + + + lower_end_matched <= 1'b1; + + + + else if ((current_address[7:0] >= end_boundary_addr[7:0]) && MEM_TYPE != "QDR2PLUS") + + + + lower_end_matched <= 1'b1; + + else + + lower_end_matched <= 1'b0; + + + +end + + + + + + + +always @(posedge clk_i) + +begin + + if (rst_i) + + pre_instr_switch <= 1'b0; + + + +else if (current_address[7:0] >= end_boundary_addr[7:0] ) // V6 send a seed address to memc_flow_ctr + + pre_instr_switch <= 1'b1; + + + +end + + + + + +always @(posedge clk_i) + +begin + + + + //if (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6" && MEM_TYPE == "QDR2PLUS") + + // end_addr_reached <= 1'b1; + + + + if ((upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 32) || + + (upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 64) || + + (upper_end_matched && DWIDTH == 128 && FAMILY == "SPARTAN6") || + + (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6")) + + end_addr_reached <= 1'b1; + + else + + end_addr_reached <= 1'b0; + + + +end + + + +always @(posedge clk_i) + +begin + + if ((upper_end_matched && pre_instr_switch && FAMILY == "VIRTEX6")) + + switch_instr <= 1'b1; + + else + + switch_instr <= 1'b0; + + + +end + + + + + + always @ (posedge clk_i) + + begin + + memc_wr_en_r <= memc_wr_en_i; + + memc_init_done_reg <= memc_init_done_i; + +end + + + + always @ (posedge clk_i) + + run_traffic_o <= run_traffic; + + + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i) + + current_state <= 5'b00001; + + else + + current_state <= next_state; + + end + + + + assign start_addr_o = BEGIN_ADDRESS;//BEGIN_ADDRESS; + + assign end_addr_o = END_ADDRESS; + + assign cmd_seed_o = CMD_SEED_VALUE; + + assign data_seed_o = DATA_SEED_VALUE; + + + + + +// + +always @ (posedge clk_i) + +begin + + if (rst_i) + + mem_pattern_init_done_o <= 1'b0; + else if (current_address >= end_boundary_addr ) + + mem_pattern_init_done_o <= 1'b1; + +end + + + +reg [3:0] syn1_vio_data_mode_value; + +reg [2:0] syn1_vio_addr_mode_value; + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i) begin + + syn1_vio_data_mode_value <= 4'b0011; + + syn1_vio_addr_mode_value <= 3'b011; + + end + + else if (vio_modify_enable == 1'b1) begin + + syn1_vio_data_mode_value <= vio_data_mode_value; + + syn1_vio_addr_mode_value <= vio_addr_mode_value; + + end + + end + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i) begin + + data_mode_sel <= DATA_MODE;//ADDR_DATA_MODE; + + end + + else if (vio_modify_enable == 1'b1) begin + + data_mode_sel <= syn1_vio_data_mode_value; + + end + + end + + + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i ) + + bl_mode_sel <= FIXED_BL_MODE; + + else if (test_mem_instr_mode[3]) + + bl_mode_sel <= 2'b11; + + else if (vio_modify_enable == 1'b1) begin + + bl_mode_sel <= vio_bl_mode_value; + + end + + end + + + + + + always @ (posedge clk_i) + + begin + + // whenever vio_instr_mode_value[3] == 1'b1, TG expects reading back phy calibration data pattern + + // which is: 0xFF, 0x00, 0xAA,0x55, 0x55, 0xAA, 0x99 and 0x66. + + if (vio_modify_enable) + + if (vio_instr_mode_value == 4'h7) + + data_mode_o <= 4'h1; // fixed data input + + else + + data_mode_o <= (test_mem_instr_mode[3]) ? 4'b1000: data_mode_sel; + + else + + data_mode_o <= DATA_MODE; + + + + + + addr_mode_o <= (test_mem_instr_mode[3]) ? 3'b000: addr_mode ; + + + + // assuming if vio_modify_enable is enabled and vio_addr_mode_value is set to zero + + // user wants to have bram interface. + + if (syn1_vio_addr_mode_value == 0 && vio_modify_enable == 1'b1) + + bram_mode_enable <= 1'b1; + + else + + bram_mode_enable <= 1'b0; + + + + end + +reg single_write_r1,single_write_r2,single_read_r1,single_read_r2; + +reg single_instr_run_trarric; + +reg slow_write_read_button_r1,slow_write_read_button_r2; + +reg toggle_start_stop_write_read; + +wire int_single_wr,int_single_rd; + +reg [8:0] write_read_counter; + +always @ (posedge clk_i) + +begin + + if (rst_i) begin + + write_read_counter <= 'b0; + + slow_write_read_button_r1 <= 1'b0; + + slow_write_read_button_r2 <= 1'b0; + + + + toggle_start_stop_write_read <= 1'b0; + + end + + else begin + + write_read_counter <= write_read_counter + 1; + + slow_write_read_button_r1 <= slow_write_read_button; + + slow_write_read_button_r2 <= slow_write_read_button_r1; + + + + if (~slow_write_read_button_r2 && slow_write_read_button_r1) + + toggle_start_stop_write_read <= ~toggle_start_stop_write_read; + + + + end + +end + + + +assign int_single_wr = write_read_counter[8]; + +assign int_single_rd = ~write_read_counter[8]; + + + + + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + begin + + single_write_r1 <= 1'b0; + + single_write_r2 <= 1'b0; + + single_read_r1 <= 1'b0; + + single_read_r2 <= 1'b0; + + + + end + + else begin + + single_write_r1 <= single_write_button | (int_single_wr & toggle_start_stop_write_read); + + single_write_r2 <= single_write_r1 ; + + single_read_r1 <= single_read_button | (int_single_rd & toggle_start_stop_write_read); + + single_read_r2 <= single_read_r1 ; + + end + +end + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + single_instr_run_trarric <= 1'b0; + + else if ((single_write_r1 && ~single_write_r2) || (single_read_r1 && ~single_read_r2)) + + single_instr_run_trarric <= 1'b1; + + else if (mode_load_o) + + single_instr_run_trarric <= 1'b0; + +end + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + run_traffic <= 1'b0; + + else if ((current_state == SINGLE_CMD_WAIT ) || (current_state == SINGLE_STEP_WRITE ) || (current_state == SINGLE_STEP_READ )) + + run_traffic <= single_instr_run_trarric; + + else if ((current_state == SINGLE_CMD_WAIT ) ) + + run_traffic <= 1'b0; + + + + else if ( (current_state != IDLE)) + + run_traffic <= 1'b1; + + else + + run_traffic <= 1'b0; + + + +end + + + + + +always @ (*) + +begin + + load_seed_o = 1'b0; + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + addr_mode = 'b0; + + else + + addr_mode = SEQUENTIAL_ADDR; + + + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + instr_mode_o = 'b0; + + else + + instr_mode_o = FIXED_INSTR_MODE; + + + + + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + bl_mode_o = 'b0; + + else + + bl_mode_o = FIXED_BL_MODE; + + + + + + if (vio_modify_enable) + + if (vio_instr_mode_value == 7) + + fixed_bl_o = 10'd1; + + else if (data_mode_o[2:0] == 3'b111) + + if (FAMILY == "VIRTEX6") + + fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256. + + else + + fixed_bl_o = 10'd64; + + else + + if (FAMILY == "VIRTEX6") + + fixed_bl_o = vio_fixed_bl_value; + + // PRBS mode + + else if (data_mode_o[3:0] == 4'b1000 && FAMILY == "SPARTAN6") + + fixed_bl_o = 10'd64; // + + + + else + + fixed_bl_o = fix_bl_value; + + else + + fixed_bl_o = fix_bl_value; + + + + // fixed_bl_o = 10'd64; + + // fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256. + + + + mode_load_o = 1'b0; + + // run_traffic = 1'b0; + + next_state = IDLE; + + + + if (PORT_MODE == "RD_MODE") + + fixed_instr_o = RD_INSTR; + + + + else //if( PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") + + fixed_instr_o = WR_INSTR; + + + + + +case(current_state) + + IDLE: + + begin + + if(memc_init_done_reg ) //rdp_rdy_i comes from read_data path + + begin + + + + if (vio_instr_mode_value == 4'h7 && single_write_r1 && ~single_write_r2) + + begin + + next_state = SINGLE_STEP_WRITE; + + mode_load_o = 1'b1; + + // run_traffic = 1'b1; + + load_seed_o = 1'b1; + + end + + + + else if (vio_instr_mode_value == 4'h7 && single_read_r1 && ~single_read_r2) + + begin + + next_state = SINGLE_STEP_READ; + + mode_load_o = 1'b1; + + // run_traffic = 1'b1; + + load_seed_o = 1'b1; + + end + + + + + + + + else if ((PORT_MODE == "WR_MODE" || (PORT_MODE == "BI_MODE" && test_mem_instr_mode[3:2] != 2'b11)) && + + vio_instr_mode_value != 4'h7 ) // normal test mode + + begin + + next_state = INIT_MEM_WRITE; + + mode_load_o = 1'b1; + + // run_traffic = 1'b0; + + load_seed_o = 1'b1; + + end + + else if ((PORT_MODE == "RD_MODE" && end_addr_reached || (test_mem_instr_mode == 4'b1111)) && + + vio_instr_mode_value != 4'h7 ) + + begin + + next_state = TEST_MEM; + + mode_load_o = 1'b1; + + // run_traffic = 1'b1; + + load_seed_o = 1'b1; + + end + + else + + begin + + next_state = IDLE; + + // run_traffic = 1'b0; + + load_seed_o = 1'b0; + + + + end + + + + end + + else + + begin + + next_state = IDLE; + + // run_traffic = 1'b0; + + load_seed_o = 1'b0; + + + + end + + + + end + + SINGLE_CMD_WAIT: begin + + if (single_operation&& single_read_r1 && ~single_read_r2) + + next_state = SINGLE_STEP_READ; + + else + + next_state = SINGLE_CMD_WAIT; + + + + fixed_instr_o = RD_INSTR; + + addr_mode = FIXED_ADDR; + + bl_mode_o = FIXED_BL_MODE; + + + + mode_load_o = 1'b0; + + load_seed_o = 1'b0; + + end + + SINGLE_STEP_WRITE: begin + + + + // run_traffic = single_instr_run_trarric; + + + + + + if (memc_cmd_en_i) + + next_state = IDLE; + + + + else + + next_state = SINGLE_STEP_WRITE; + + + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + addr_mode = FIXED_ADDR; + + bl_mode_o = FIXED_BL_MODE; + + + + fixed_instr_o = WR_INSTR; + + + + end + + + + SINGLE_STEP_READ: begin //0x20 + + + + // run_traffic = single_instr_run_trarric; + + if (single_operation) + + next_state = SINGLE_CMD_WAIT; + + + + else if (memc_cmd_en_i) + + next_state = IDLE; + + else + + next_state = SINGLE_STEP_READ; + + + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + // run_traffic = 1'b1; + + addr_mode = FIXED_ADDR; + + bl_mode_o = FIXED_BL_MODE; + + + + fixed_instr_o = RD_INSTR; + + + + end + + + + INIT_MEM_WRITE: begin + + + + + + + + if (end_addr_reached && EYE_TEST == "FALSE" ) + + begin + + next_state = TEST_MEM; + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + // run_traffic = 1'b1; + + + + end + + else + + begin + + next_state = INIT_MEM_WRITE; + + // run_traffic = 1'b1; + + mode_load_o = 1'b0; + + load_seed_o = 1'b0; + + if (EYE_TEST == "TRUE") + + addr_mode = FIXED_ADDR; + + else if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + addr_mode = 'b0; + + else + + addr_mode = SEQUENTIAL_ADDR; + + + + + + if (switch_instr && TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE") + + fixed_instr_o = RD_INSTR; + + else + + + + fixed_instr_o = WR_INSTR; + + + + end + + + + end + + + + INIT_MEM_READ: begin + + + + if (end_addr_reached ) + + begin + + next_state = TEST_MEM; + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + + + end + + else + + begin + + next_state = INIT_MEM_READ; + + // run_traffic = 1'b0; + + mode_load_o = 1'b0; + + load_seed_o = 1'b0; + + + + end + + + + end + + TEST_MEM: begin + + if (single_operation) + + next_state = SINGLE_CMD_WAIT; + + else if (cmp_error) + + next_state = TEST_MEM;//CMP_ERROR; + + + + else + + next_state = TEST_MEM; + + // run_traffic = 1'b1; + + + + if (vio_modify_enable) + + fixed_instr_o = vio_fixed_instr_value; + + else if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") + + fixed_instr_o = WR_INSTR; + + else if (PORT_MODE == "BI_MODE" && ( TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || + + TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE")) + + fixed_instr_o = RD_INSTR; + + else if (PORT_MODE == "RD_MODE") + + fixed_instr_o = RD_INSTR; + + + + else //if( PORT_MODE == "WR_MODE") + + fixed_instr_o = WR_INSTR; + + + + + + + + if ((data_mode_o == 3'b111) && FAMILY == "VIRTEX6") + + fixed_bl_o = 10'd256; + + else if ((FAMILY == "SPARTAN6")) + + fixed_bl_o = 10'd64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64. + + else + + fixed_bl_o = fix_bl_value; + + + + + + if (data_mode_o == 3'b111) + + bl_mode_o = FIXED_BL_MODE; + + + + else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") + + bl_mode_o = FIXED_BL_MODE; + + else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110) + + // simplify the downstream logic, data_mode is forced to FIXED_BL_MODE + + // if data_mode is set to Walking 1's or Walking 0's. + + bl_mode_o = FIXED_BL_MODE; + + else + + bl_mode_o = bl_mode_sel ; + + + + /* if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") + + addr_mode = SEQUENTIAL_ADDR; + + else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110) + + // simplify the downstream logic, addr_mode is forced to SEQUENTIAL + + // if data_mode is set to Walking 1's or Walking 0's. + + // This ensure the starting burst address always in in the beginning + + // of burst_length address for the number of DQ pins.And to ensure the + + // DQ0 always asserts at the beginning of each user burst. + + addr_mode = SEQUENTIAL_ADDR; + + else if (bl_mode_o == PRBS_BL_MODE) + + addr_mode = PRBS_ADDR; + + else + + addr_mode = 3'b010;*/ + + + + addr_mode = vio_addr_mode_value; + + + + if (vio_modify_enable ) + + instr_mode_o = vio_instr_mode_value; + + + + else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "VIRTEX6") + + instr_mode_o = FIXED_INSTR_MODE; + + else if(PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE != "FIXED_INSTR_R_EYE_MODE") + + if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + instr_mode_o = BRAM_INSTR_MODE; + + else + + instr_mode_o = test_mem_instr_mode;//R_RP_W_WP_REF_INSTR_MODE;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;// + + else //if (PORT_MODE == "RD_MODE" || PORT_MODE == "WR_MODE") begin + + instr_mode_o = FIXED_INSTR_MODE; + + + + end + + + + + + CMP_ERROR: + + begin + + next_state = CMP_ERROR; + + bl_mode_o = bl_mode_sel;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE; + + fixed_instr_o = RD_INSTR; + + addr_mode = SEQUENTIAL_ADDR;//PRBS_ADDR;//PRBS_ADDR;//PRBS_ADDR;//SEQUENTIAL_ADDR; + + if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + instr_mode_o = BRAM_INSTR_MODE;// + + else + + instr_mode_o = test_mem_instr_mode;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;// + + + + // run_traffic = 1'b1; // ?? keep it running or stop if error happened + + + + end + + default: + + begin + + next_state = IDLE; + + //run_traffic = 1'b0; + + + + end + + + + endcase + + end + + + + + + + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_memc_flow_vcontrol.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_memc_flow_vcontrol.v new file mode 100644 index 0000000..63f4dcd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_memc_flow_vcontrol.v @@ -0,0 +1,503 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: mcb_flow_control.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:21 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Virtex 6 +//Design Name: DDR2/DDR3 +//Purpose: This module is the main flow control between cmd_gen.v, +// write_data_path and read_data_path modules. +//Reference: +//Revision History: 7/29/10 Support V6 Back-to-back commands over user interface. +// +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_memc_flow_vcontrol # + ( + parameter TCQ = 100, + parameter nCK_PER_CLK = 4, + parameter NUM_DQ_PINS = 32, + parameter BL_WIDTH = 6, + parameter MEM_BURST_LEN = 4, + parameter FAMILY = "SPARTAN6", + parameter MEM_TYPE = "DDR3" + + ) + ( + input clk_i, + input [9:0] rst_i, + input [3:0] data_mode_i, + input [5:0] cmds_gap_delay_value, + input mem_pattern_init_done_i, + // interface to cmd_gen, pipeline inserter + output reg cmd_rdy_o, + input cmd_valid_i, + input [2:0] cmd_i, + input [31:0] addr_i, + input [BL_WIDTH - 1:0] bl_i, + + // interface to mcb_cmd port + input mcb_cmd_full, + input mcb_wr_full_i, + output reg [2:0] cmd_o, + output [31:0] addr_o, + output reg [BL_WIDTH-1:0] bl_o, + output cmd_en_o, // interface to write data path module + // *** interface to qdr **** + output reg qdr_rd_cmd_o, + // ************************* + input mcb_wr_en_i, + input last_word_wr_i, + input wdp_rdy_i, + output reg wdp_valid_o, + output reg wdp_validB_o, + output reg wdp_validC_o, + output [31:0] wr_addr_o, + output [BL_WIDTH-1:0] wr_bl_o, + // interface to read data path module + input rdp_rdy_i, + output reg rdp_valid_o, + output [31:0] rd_addr_o, + output [BL_WIDTH-1:0] rd_bl_o + ); + + //FSM State Defination + localparam READY = 4'b0001, + READ = 4'b0010, + WRITE = 4'b0100, + CMD_WAIT = 4'b1000; + + localparam RD = 3'b001; + localparam RDP = 3'b011; + localparam WR = 3'b000; + localparam WRP = 3'b010; + localparam REFRESH = 3'b100; + localparam NOP = 3'b101; + + + reg cmd_fifo_rdy; + reg push_cmd; + reg cmd_rdy; + reg [31:0] addr_r; + reg [2:0] cmd_reg; + reg [31:0] addr_reg; + reg [BL_WIDTH-1:0] bl_reg; + reg [BL_WIDTH:0] cmd_counts; + reg rdp_valid; +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC; + reg [3:0] current_state; + reg [3:0] next_state; + reg push_cmd_r; + reg cmd_en_r1; + reg wr_in_progress; + reg wrcmd_in_progress; + reg rdcmd_in_progress; + reg [5:0] commands_delay_counters; + reg goahead; + reg cmd_en_r2; + reg cmd_wr_pending_r1; + reg [3:0] addr_INC; + reg COuta; + wire cmd_rd; + wire cmd_wr; + + always @ (posedge clk_i) begin + if (data_mode_i == 4'b1000 || FAMILY == "SPARTAN6") + addr_INC <= #TCQ 0; + else + addr_INC <= #TCQ MEM_BURST_LEN[3:0]; + end + +// mcb_command bus outputs + always @(posedge clk_i) begin + if (rst_i[0]) begin + commands_delay_counters <= 6'b00000; + goahead <= 1'b1; + end + else if (cmds_gap_delay_value == 5'd0) + goahead <= 1'b1; + else if (wr_in_progress || wrcmd_in_progress || + rdcmd_in_progress || cmd_rdy_o) begin + commands_delay_counters <= 6'b00000; + goahead <= 1'b0; + end + else if (commands_delay_counters == cmds_gap_delay_value) begin + commands_delay_counters <= commands_delay_counters; + goahead <= 1'b1; + end + else + commands_delay_counters <= commands_delay_counters + 1'b1; + end + + assign cmd_en_o = (FAMILY == "VIRTEX6") ? cmd_en_r1 : (~cmd_en_r1 & cmd_en_r2) ; + + always @ (posedge clk_i) + cmd_rdy_o <= #TCQ cmd_rdy; + + always @ (posedge clk_i) begin + if (rst_i[8]) + cmd_en_r1 <= #TCQ 1'b0; +// else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 || mcb_wr_full_i)) + else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 )) + + cmd_en_r1 <= #TCQ 1'b0; + else if ((rdcmd_in_progress || wrcmd_in_progress && MEM_TYPE != "QDR2PLUS") || + (mcb_wr_en_i && MEM_TYPE == "QDR2PLUS")) + cmd_en_r1 <= #TCQ 1'b1; + else if (!mcb_cmd_full) + cmd_en_r1 <= #TCQ 1'b0; + end + + always @ (posedge clk_i) + if (rst_i[8]) + cmd_en_r2 <= #TCQ 1'b0; + else + cmd_en_r2 <= cmd_en_r1; + +// QDR read command generation + always @ (posedge clk_i) begin + if (rst_i[8]) + qdr_rd_cmd_o <= #TCQ 1'b0; + else if (cmd_counts == 1 && !mcb_cmd_full && rdcmd_in_progress && cmd_en_r1) + qdr_rd_cmd_o <= #TCQ 1'b0; + else if (rdcmd_in_progress) + qdr_rd_cmd_o <= #TCQ 1'b1; + else if (!mcb_cmd_full) + qdr_rd_cmd_o <= #TCQ 1'b0; + end + + always @ (posedge clk_i) begin + if (rst_i[9]) + cmd_fifo_rdy <= #TCQ 1'b1; + else if (cmd_en_r1 || mcb_cmd_full) + cmd_fifo_rdy <= #TCQ 1'b0; + else if (!mcb_cmd_full) + cmd_fifo_rdy <= #TCQ 1'b1; + end + + always @ (posedge clk_i) begin + if (rst_i[9]) begin + cmd_o <= #TCQ 'b0; + bl_o <= #TCQ 'b0; + end + else if (push_cmd_r && current_state == READ) begin + cmd_o <= #TCQ cmd_i; + bl_o <= #TCQ bl_i - 'b1; + end + else if (push_cmd_r && current_state == WRITE) begin + if (FAMILY == "SPARTAN6") + cmd_o <= #TCQ cmd_reg; + else + cmd_o <= #TCQ {2'b00,cmd_reg[0]}; + bl_o <= #TCQ bl_reg; + end + end + + always @ (posedge clk_i) + if ((push_cmd && mem_pattern_init_done_i) | rst_i) + addr_reg <= #TCQ addr_i; + else if (push_cmd && !mem_pattern_init_done_i) + addr_reg <= #TCQ addr_r; + + always @ (posedge clk_i) begin + if (push_cmd && cmd_rd || rst_i[0]) + addr_r <= #TCQ addr_i; + else if (push_cmd_r && current_state != READ) + addr_r <= #TCQ addr_reg; + else if ((wrcmd_in_progress || rdcmd_in_progress) && + cmd_en_r1 && ~mcb_cmd_full) begin + if (MEM_TYPE == "QDR2PLUS") + {COuta,addr_r[31:0]} <= addr_o + 1; + else + {COuta,addr_r[31:0]} <= addr_o + addr_INC; + + end + end + + assign addr_o = addr_r; + assign wr_addr_o = addr_i; + assign rd_addr_o = addr_i; + assign rd_bl_o = bl_i; + assign wr_bl_o = bl_i; + + always @ (posedge clk_i) begin + wdp_valid_o <= wdp_valid; + wdp_validB_o <= wdp_validB; + wdp_validC_o <= wdp_validC; + end + + always @ (posedge clk_i) + rdp_valid_o <= rdp_valid; + + always @(posedge clk_i) + push_cmd_r <= #TCQ push_cmd; + + always @(posedge clk_i) + if (push_cmd) begin + cmd_reg <= #TCQ cmd_i; + bl_reg <= #TCQ bl_i - 1'b1; + end + + always @ (posedge clk_i) + begin + if (rst_i[8]) + cmd_counts <= #TCQ 'b0; + else if (push_cmd_r) begin + if (bl_i == 0) begin + if (MEM_BURST_LEN == 8) begin + if (nCK_PER_CLK == 4) + cmd_counts <= #TCQ {2'b01, {BL_WIDTH-1{1'b0}}}; + else + cmd_counts <= #TCQ {3'b001, {BL_WIDTH-2{1'b0}}}; + end + else + cmd_counts <= {1'b0,{BL_WIDTH{1'b1}}} ;//- 2;//63; + end + else begin + if (MEM_BURST_LEN == 8) begin + if (nCK_PER_CLK == 4) + cmd_counts <= {1'b0,bl_i}; + else + cmd_counts <= {3'b000,bl_i[BL_WIDTH-2:1]}; + end + else + cmd_counts <= {1'b0,bl_i};//- 1 ;// {1'b0,bl_i[5:1]} -2; + end + end + else if ((wrcmd_in_progress || rdcmd_in_progress) && cmd_en_r1 && ~mcb_cmd_full) begin + if (cmd_counts > 0) begin + if (FAMILY == "VIRTEX6") + cmd_counts <= cmd_counts - 1'b1; + else if (wrcmd_in_progress) + cmd_counts <= cmd_counts - 1'b1; + else + cmd_counts <= 0; + end + end + end + + //--Command Decodes-- + assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i) ? 1'b1 : 1'b0; + assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0; + + always @ (posedge clk_i) begin + if (rst_i[0]) + cmd_wr_pending_r1 <= #TCQ 1'b0; + else if (last_word_wr_i) + cmd_wr_pending_r1 <= #TCQ 1'b1; + else if (push_cmd & cmd_wr) + cmd_wr_pending_r1 <= #TCQ 1'b0; + end + + always @ (posedge clk_i) begin + if (rst_i[0]) + wr_in_progress <= #TCQ 1'b0; + else if (last_word_wr_i) + wr_in_progress <= #TCQ 1'b0; + else if (push_cmd && cmd_wr) + wr_in_progress <= #TCQ 1'b1; + end + + always @ (posedge clk_i) begin + if (rst_i[0]) + wrcmd_in_progress <= #TCQ 1'b0; + else if (cmd_wr && push_cmd_r) + wrcmd_in_progress <= #TCQ 1'b1; + else if (cmd_counts == 0 || (cmd_counts == 1 && ~mcb_cmd_full)) + wrcmd_in_progress <= #TCQ 1'b0; + end + + always @ (posedge clk_i) begin + if (rst_i[0]) + rdcmd_in_progress <= #TCQ 1'b0; + else if (cmd_rd && push_cmd_r) + rdcmd_in_progress <= #TCQ 1'b1; + else if (cmd_counts <= 1) + rdcmd_in_progress <= #TCQ 1'b0; + end + +// mcb_flow_control statemachine + always @ (posedge clk_i) + if (rst_i[0]) + current_state <= #TCQ 5'b00001; + else + current_state <= #TCQ next_state; + + always @ (*) begin + push_cmd = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + rdp_valid = 1'b0; + cmd_rdy = 1'b0; + next_state = current_state; + + case(current_state) // next state logic + + READY: begin // 5'h01 + + if (rdp_rdy_i && cmd_rd && ~mcb_cmd_full) begin + next_state = READ; + push_cmd = 1'b1; + rdp_valid = 1'b1; + cmd_rdy = 1'b1; + end + else if (wdp_rdy_i && cmd_wr && ~mcb_cmd_full) begin + next_state = WRITE; + push_cmd = 1'b1; + wdp_valid = 1'b1; + wdp_validB = 1'b1; + wdp_validC = 1'b1; + cmd_rdy = 1'b1; + end + else begin + next_state = READY; + push_cmd = 1'b0; + cmd_rdy = 1'b0; + end + end // READY + + READ: begin // 5'h02 + + if (rdcmd_in_progress) begin + next_state = READ; + push_cmd = 1'b0; + rdp_valid = 1'b0; + wdp_valid = 1'b0; + end + else if (!rdp_rdy_i) begin + next_state = READ; + push_cmd = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + rdp_valid = 1'b0; + end + else if (~cmd_fifo_rdy && ~rdcmd_in_progress && goahead) begin + next_state = CMD_WAIT; + end + else if (goahead && ~push_cmd_r) begin + next_state = READY; + cmd_rdy = 1'b0; + end + else + next_state = READ; + end // READ + + WRITE: begin // 5'h04 + + if (wr_in_progress || wrcmd_in_progress || push_cmd_r) begin + next_state = WRITE; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + push_cmd = 1'b0; + end + else if (!cmd_fifo_rdy && last_word_wr_i && goahead) begin + next_state = CMD_WAIT; + push_cmd = 1'b0; + end + else if (goahead) begin + next_state = READY; + end + else + next_state = WRITE; + + cmd_rdy = 1'b0; + + end // WRITE + + CMD_WAIT: begin // 5'h08 + + if (!cmd_fifo_rdy || wr_in_progress) begin + next_state = CMD_WAIT; + cmd_rdy = 1'b0; + end + else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd) begin + next_state = READY; + push_cmd = 1'b0; + cmd_rdy = 1'b0; + rdp_valid = 1'b0; + end + else if (cmd_fifo_rdy && cmd_wr && goahead && + cmd_wr_pending_r1) begin + next_state = READY; + push_cmd = 1'b0; + cmd_rdy = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + end + else begin + next_state = CMD_WAIT; + cmd_rdy = 1'b0; + end + end // CMD_WAIT + + default: begin + push_cmd = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + next_state = READY; + end + + endcase + end + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_memc_traffic_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_memc_traffic_gen.v new file mode 100644 index 0000000..5d06399 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_memc_traffic_gen.v @@ -0,0 +1,909 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MEMC +// / / Filename: memc_traffic_gen.v +// /___/ /\ Date Last Modified: $Date: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6/Virtex6 +//Design Name: memc_traffic_gen +//Purpose: This is top level module of memory traffic generator which can +// generate different CMD_PATTERN and DATA_PATTERN to Spartan 6 +// hard memory controller core. +//Reference: +//Revision History: 1.1 Brought out internal signals cmp_data and cmp_error as outputs. +// 1.2 7/1/2009 Added EYE_TEST parameter for signal SI probing. +// 1.3 10/1/2009 Added dq_error_bytelane_cmp,cumlative_dq_lane_error signals for V6. +// Any comparison error on user read data bus are mapped back to +// dq bus. The cumulative_dq_lane_error accumulate any errors on +// DQ bus. And the dq_error_bytelane_cmp shows error during current +// command cycle. The error can be cleared by input signal "manual_clear_error". +// 1.4 7/29/10 Support virtex Back-to-back commands over user interface. +// +// 1/4/2012 Added vio_percent_write (instr_mode == 4) to +// let user specify percentage of write commands out of mix +// write/read commands. + +//***************************************************************************** +`timescale 1ps/1ps + +module mig_7series_v4_2_memc_traffic_gen # + ( + parameter TCQ = 100, // SIMULATION tCQ delay. + parameter FAMILY = "SPARTAN6", // "VIRTEX6", "SPARTAN6" + parameter MEM_TYPE = "DDR3", + parameter SIMULATION = "FALSE", + parameter tCK = 2500, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + + parameter BL_WIDTH = 6, + parameter MEM_BURST_LEN = 8, // For VIRTEX6 Only in this traffic gen. + // This traffic gen doesn't support DDR3 OTF Burst mode. + + parameter PORT_MODE = "BI_MODE", // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE" + // VIRTEX6: "BI_MODE" + parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL", + + parameter ADDR_WIDTH = 30, // Spartan 6 Addr width is 30 + + parameter BANK_WIDTH = 3, + + parameter CMP_DATA_PIPE_STAGES = 0, // parameter for MPMC, it should always set to 0 + + // memory type specific + parameter MEM_COL_WIDTH = 10, // memory column width + parameter NUM_DQ_PINS = 16, // Spartan 6 Options: 4,8,16; + // Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144 + + parameter SEL_VICTIM_LINE = 3, // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern + // SEL_VICTIM_LINE is only for V6. + // Virtex 6 option: 8,9,16,17,32,36,64,72 + parameter DWIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, //NUM_DQ_PINS*4, // Spartan 6 Options: 32,64,128; + // Virtex 6 Always: 4* NUM_DQ_PINS + + + // the following parameter is to limit the range of generated PRBS Address + // + // e.g PRBS_SADDR_MASK_POS = 32'h0000_7000 the bit 14:12 of PRBS_SADDR will be ORed with + // PRBS_SADDR = 32'h0000_5000 the LFSR[14:12] to add the starting address offset. + + // PRBS_EADDR = 32'h0000_7fff + // PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to + // zero out the LFSR[31:15] + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + parameter PRBS_EADDR = 32'h00002000, + parameter PRBS_SADDR = 32'h00005000, + parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals. + // Traffic Generator will only write to one single location and no + // read transactions will be generated. + + + ) + + ( + + input clk_i, + input rst_i, + input run_traffic_i, + input single_operation, + input manual_clear_error, + input [5:0] cmds_gap_delay_value, // control delay gap between each sucessive + input [3:0] vio_instr_mode_value, + input [3:0] vio_percent_write, + // burst commands. + + // *** runtime parameter *** + input mem_pattern_init_done_i, + input [31:0] start_addr_i, // define the start of address + input [31:0] end_addr_i, // define upper limit addressboundary + input [31:0] cmd_seed_i, // seed for cmd PRBS generators + input [31:0] data_seed_i, // data seed will be added to generated address + // for PRBS data generation + // seed for cmd PRBS generators + input load_seed_i, // when asserted the cmd_seed and data_seed inputs will be registered. + + // upper layer inputs to determine the command bus and data pattern + // internal traffic generator initialize the memory with + input [2:0] addr_mode_i, // "00" = bram; takes the address from bram interface + // "01" = fixed address from the fixed_addr input + // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR + // "11" = sequential + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + input [3:0] instr_mode_i, // "0000" = BRAM + // "0001" = Fixed; takes instruction from bram output + // "0010" = R/W + // "0011" = RP/WP + // "0100" = R/RP/W/WP + // "0101" = R/RP/W/WP/REF + // "0110" = PRBS + // "1111" = Read Only from Address 0 . Expecting phy calibration data pattern. + + + input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output + // "01" = fixed , takes the burst length from the fixed_bl input + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + input [3:0] data_mode_i, // "000" = address as data + // "001" = hammer + // "010" = neighbour + // "011" = prbs + // "100" = walking 0's + // "101" = walking 1's + // "110" = + // "111" = + + input wr_data_mask_gen_i, // "1": turn on wr_data_mask generation + // random follow by walking 1's + input mode_load_i, + + // fixed pattern inputs interface + input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64 + input [2:0] fixed_instr_i, //RD 3'b001 + //RDP 3'b011 + //WR 3'b000 + //WRP 3'b010 + //REFRESH 3'b100 + + + input [31:0] fixed_addr_i, // only upper 30 bits will be used + input [31:0] fixed_data_i, // + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + + // BRAM interface. + // bram bus formats: + // Only SP6 has been tested. + input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}} + input bram_valid_i, + output bram_rdy_o, // + + ///////////////////////////////////////////////////////////////////////////// + // MCB INTERFACE + // interface to mcb command port + output memc_cmd_en_o, + output [2:0] memc_cmd_instr_o, + output [31:0] memc_cmd_addr_o, + output [5:0] memc_cmd_bl_o, // this output is for Spartan 6 + + input memc_cmd_full_i, + // interface to qdr interface + output qdr_wr_cmd_o, + output qdr_rd_cmd_o, + + // interface to mcb wr data port + output memc_wr_en_o, + output [DWIDTH-1:0] memc_wr_data_o, + output memc_wr_data_end_o, + output [(DWIDTH/8) - 1:0] memc_wr_mask_o, + + input memc_wr_full_i, + + // interface to mcb rd data port + output memc_rd_en_o, + input [DWIDTH-1:0] memc_rd_data_i, + input memc_rd_empty_i, + ///////////////////////////////////////////////////////////////////////////// + // status feedback + input counts_rst, + output reg [47:0] wr_data_counts, + output reg [47:0] rd_data_counts, + output cmp_error, + output cmp_data_valid, + output error, // asserted whenever the read back data is not correct. + output [64 + (2*DWIDTH - 1):0] error_status ,// TBD how signals mapped + output [DWIDTH-1:0] cmp_data, + output [DWIDTH-1:0] mem_rd_data, + + + // **** V6 Signals + output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane + output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error, // V6: latched error byte lane that occure on + // first error + + //************************************************ + // DQ bit error debug signals. + + output [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error , + output [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error , + output [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error , + output [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error , + + output [NUM_DQ_PINS-1:0] dq_r0_bit_error_r, + output [NUM_DQ_PINS-1:0] dq_f0_bit_error_r, + output [NUM_DQ_PINS-1:0] dq_r1_bit_error_r, + output [NUM_DQ_PINS-1:0] dq_f1_bit_error_r, + + + + // + output [NUM_DQ_PINS - 1:0] dq_r0_read_bit, // rising 0 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_f0_read_bit, // falling 0 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_r1_read_bit, // rising 1 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_f1_read_bit, // falling 1 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_r0_expect_bit, // rising 0 read bits from internal expect data generator + output [NUM_DQ_PINS - 1:0] dq_f0_expect_bit, // falling 0 read bits from internal expect data generator + output [NUM_DQ_PINS - 1:0] dq_r1_expect_bit, // rising 1 read bits from internal expect data generator + output [NUM_DQ_PINS - 1:0] dq_f1_expect_bit, // falling 1 read bits from internal expect data generator + output [31:0] error_addr // the command address of the returned data. + // Can use dq_rx_bit_error as write enable to latch the address. + + + + ); + + + wire [DWIDTH-1:0] rdpath_rd_data_i; + wire rdpath_data_valid_i; + wire memc_wr_en; + wire cmd2flow_valid; + wire [2:0] cmd2flow_cmd; + wire [31:0] cmd2flow_addr; + wire [BL_WIDTH-1:0] cmd2flow_bl; + wire last_word_wr; + wire flow2cmd_rdy; + wire [31:0] wr_addr; + wire [31:0] rd_addr; + wire [BL_WIDTH-1:0] wr_bl; + wire [BL_WIDTH-1:0] rd_bl; + reg run_traffic_reg; +wire wr_validB, wr_valid,wr_validC; +wire [31:0] bram_addr_i; +wire [2:0] bram_instr_i; +wire [5:0] bram_bl_i; +reg AC2_G_E2,AC1_G_E1,AC3_G_E3; +reg upper_end_matched; +reg [7:0] end_boundary_addr; +reg lower_end_matched; +wire [31:0] addr_o; +wire [31:0] m_addr; +wire dcount_rst; +wire [31:0] rd_addr_error; +wire rd_rdy; +//wire cmp_error; +wire cmd_full; +wire rd_mdata_fifo_rd_en; +wire rd_mdata_fifo_afull; +reg memc_wr_en_r; +wire memc_wr_data_end; +reg [DWIDTH-1:0] memc_rd_data_r; + +wire [DWIDTH-1:0] memc_wr_data; +reg [DWIDTH-1:0] memc_wr_data_r; + + +wire wr_path_data_rdy_i; +// +wire [31:0] cmp_addr; +wire [5:0] cmp_bl; + + +reg [9:0] rst_ra,rst_rb /* synthesis syn_maxfan = 10 */; +wire mem_init_done; +reg [3:0] data_mode_r_a; +reg [3:0] data_mode_r_b; +reg [3:0] data_mode_r_c; +reg error_access_range = 1'b0; + +wire [BL_WIDTH-1:0] memc_bl_o; + +// generic parameters and need to be tested in both MCB mode and V7 Virtext Mode. + + + initial begin + if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8) && (MEM_BURST_LEN !== 2)) + begin: NO_OTF_Warning_Error + $display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!"); + $stop; + end + else + begin: Dummy1 + + end + end + +always @ (memc_cmd_en_o,memc_cmd_addr_o,memc_cmd_bl_o,start_addr_i,end_addr_i) +if (memc_cmd_en_o && + ((FAMILY == "SPARTAN6" && memc_cmd_addr_o + 20) > end_addr_i[ADDR_WIDTH-1:0]) || + ((FAMILY == "VIRTEX6" && memc_cmd_addr_o ) > end_addr_i[ADDR_WIDTH-1:0]) + ) + begin + $display("Error ! Command access beyond address range"); + $display("Assigned Address Space: Start_Address = 0x%h ; End_Addr = 0x%h",start_addr_i,end_addr_i); + $display("Attempted area = 0x%h",memc_cmd_addr_o + (memc_cmd_bl_o - 1) * (DWIDTH/8)); + + $stop; + end +else +begin: No_Error_Display + +end + +assign memc_cmd_bl_o = memc_bl_o[5:0]; + + + + + +always @ (posedge clk_i) +begin + data_mode_r_a <= #TCQ data_mode_i; + data_mode_r_b <= #TCQ data_mode_i; + data_mode_r_c <= #TCQ data_mode_i; +end + + + + +//reg GSR = 1'b0; + always @(rst_i) + begin + rst_ra = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i}; + rst_rb = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i}; + + end + // register it . Just in case the calling modules didn't syn with clk_i + always @(posedge clk_i) + begin + run_traffic_reg <= #TCQ run_traffic_i; + end + + assign bram_addr_i = {bram_cmd_i[29:0],2'b00}; + assign bram_instr_i = bram_cmd_i[32:30]; + assign bram_bl_i[5:0] = bram_cmd_i[38:33]; //41 + +// +// +reg COutc,COutd; + +assign dcount_rst = counts_rst | rst_ra[0]; +always @ (posedge clk_i) +begin + if (dcount_rst) + wr_data_counts <= #TCQ 'b0; + else if (memc_wr_en) + {COutc,wr_data_counts} <= #TCQ wr_data_counts + DWIDTH/8; + +end + +always @ (posedge clk_i) +begin + if (dcount_rst) + rd_data_counts <= #TCQ 'b0; + else if (memc_rd_en_o) + {COutd,rd_data_counts} <= #TCQ rd_data_counts + DWIDTH/8; + +end + + + +// **** for debug +// this part of logic is to check there are no commands been duplicated or dropped +// in the cmd_flow_control logic +generate +if (SIMULATION == "TRUE") +begin: cmd_check +wire fifo_error; +wire [31:0] xfer_addr; +wire [BL_WIDTH-1:0] xfer_cmd_bl; +wire cmd_fifo_rd; + +assign cmd_fifo_wr = flow2cmd_rdy & cmd2flow_valid; + +assign fifo_error = ( xfer_addr != memc_cmd_addr_o) ? 1'b1: 1'b0; + + +wire cmd_fifo_empty; +//assign cmd_fifo_rd = memc_cmd_en_o & ~memc_cmd_full_i & ~cmd_fifo_empty; +assign cmd_fifo_rd = memc_cmd_en_o & ~cmd_fifo_empty; + + + mig_7series_v4_2_afifo # + (.TCQ (TCQ), + .DSIZE (32+BL_WIDTH), + .FIFO_DEPTH (16), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + cmd_fifo + ( + .wr_clk (clk_i), + .rst (rst_ra[0]), + .wr_en (cmd_fifo_wr), + .wr_data ({cmd2flow_bl,cmd2flow_addr}), + .rd_en (cmd_fifo_rd), + .rd_clk (clk_i), + .rd_data ({xfer_cmd_bl,xfer_addr}), + .full (cmd_fifo_full), + .almost_full (), + .empty (cmd_fifo_empty) + + ); + + +end +else +begin + assign fifo_error = 1'b0; +end + +endgenerate + +reg [31:0] end_addr_r; + always @ (posedge clk_i) + end_addr_r <= end_addr_i; + + + mig_7series_v4_2_cmd_gen + #( + .TCQ (TCQ), + .FAMILY (FAMILY) , + .MEM_TYPE (MEM_TYPE), + + .BL_WIDTH (BL_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + + .MEM_BURST_LEN (MEM_BURST_LEN), + .PORT_MODE (PORT_MODE), + .BANK_WIDTH (BANK_WIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .DATA_PATTERN (DATA_PATTERN), + .CMD_PATTERN (CMD_PATTERN), + .ADDR_WIDTH (ADDR_WIDTH), + .DWIDTH (DWIDTH), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ), + .PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ), + .PRBS_EADDR (PRBS_EADDR), + .PRBS_SADDR (PRBS_SADDR ) + + ) + u_c_gen + ( + .clk_i (clk_i), + .rst_i (rst_ra), + .reading_rd_data_i (memc_rd_en_o), + .vio_instr_mode_value (vio_instr_mode_value), + .vio_percent_write (vio_percent_write), + .single_operation (single_operation), + .run_traffic_i (run_traffic_reg), + .mem_pattern_init_done_i (mem_pattern_init_done_i), + .start_addr_i (start_addr_i), + .end_addr_i (end_addr_r), + .cmd_seed_i (cmd_seed_i), + .load_seed_i (load_seed_i), + .addr_mode_i (addr_mode_i), + .data_mode_i (data_mode_r_a), + + .instr_mode_i (instr_mode_i), + .bl_mode_i (bl_mode_i), + .mode_load_i (mode_load_i), + // fixed pattern inputs interface + .fixed_bl_i (fixed_bl_i), + .fixed_addr_i (fixed_addr_i), + .fixed_instr_i (fixed_instr_i), + // BRAM FIFO input : Holist vector inputs + + .bram_addr_i (bram_addr_i), + .bram_instr_i (bram_instr_i ), + .bram_bl_i (bram_bl_i ), + .bram_valid_i (bram_valid_i ), + .bram_rdy_o (bram_rdy_o ), + + .rdy_i (flow2cmd_rdy), + .instr_o (cmd2flow_cmd), + .addr_o (cmd2flow_addr), + .bl_o (cmd2flow_bl), +// .m_addr_o (m_addr), + .cmd_o_vld (cmd2flow_valid), + .mem_init_done_o (mem_init_done) + + ); + +assign memc_cmd_addr_o = addr_o; + + +assign qdr_wr_cmd_o = memc_wr_en_r; + +assign cmd_full = memc_cmd_full_i; + mig_7series_v4_2_memc_flow_vcontrol # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + + .BL_WIDTH (BL_WIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE) + + ) + memc_control + ( + .clk_i (clk_i), + .rst_i (rst_ra), + .data_mode_i (data_mode_r_b), + .cmds_gap_delay_value (cmds_gap_delay_value), + .mcb_wr_full_i (memc_wr_full_i), + .cmd_rdy_o (flow2cmd_rdy), + .cmd_valid_i (cmd2flow_valid), + .cmd_i (cmd2flow_cmd), + + + .mem_pattern_init_done_i (mem_pattern_init_done_i), + + .addr_i (cmd2flow_addr), + .bl_i (cmd2flow_bl), + // interface to memc_cmd port + .mcb_cmd_full (cmd_full), + .cmd_o (memc_cmd_instr_o), + .addr_o (addr_o), + .bl_o (memc_bl_o), + .cmd_en_o (memc_cmd_en_o), + .qdr_rd_cmd_o (qdr_rd_cmd_o), + // interface to write data path module + + .mcb_wr_en_i (memc_wr_en), + .last_word_wr_i (last_word_wr), + .wdp_rdy_i (wr_rdy),//(wr_rdy), + .wdp_valid_o (wr_valid), + .wdp_validB_o (wr_validB), + .wdp_validC_o (wr_validC), + + .wr_addr_o (wr_addr), + .wr_bl_o (wr_bl), + // interface to read data path module + + .rdp_rdy_i (rd_rdy),// (rd_rdy), + .rdp_valid_o (rd_valid), + .rd_addr_o (rd_addr), + .rd_bl_o (rd_bl) + + ); + + + /* afifo # + ( + + .TCQ (TCQ), + .DSIZE (DWIDTH), + .FIFO_DEPTH (32), + .ASIZE (5), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_mdata_fifo + ( + .wr_clk (clk_i), + .rst (rst_rb[0]), + .wr_en (!memc_rd_empty_i), + .wr_data (memc_rd_data_i), + .rd_en (memc_rd_en_o), + .rd_clk (clk_i), + .rd_data (rd_v6_mdata), + .full (), + .almost_full (rd_mdata_fifo_afull), + .empty (rd_mdata_fifo_empty) + + ); +*/ + +wire cmd_rd_en; + +assign cmd_rd_en = memc_cmd_en_o; + + + + +assign rdpath_data_valid_i =!memc_rd_empty_i ; +assign rdpath_rd_data_i = memc_rd_data_i ; + + +generate +if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE") +begin : RD_PATH + mig_7series_v4_2_read_data_path + #( + .TCQ (TCQ), + .FAMILY (FAMILY) , + .MEM_TYPE (MEM_TYPE), + .BL_WIDTH (BL_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + + .MEM_BURST_LEN (MEM_BURST_LEN), + .START_ADDR (PRBS_SADDR), + .CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES), + .ADDR_WIDTH (ADDR_WIDTH), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .SIMULATION (SIMULATION) + + ) + read_data_path + ( + .clk_i (clk_i), + .rst_i (rst_rb), + .manual_clear_error (manual_clear_error), + .cmd_rdy_o (rd_rdy), + .cmd_valid_i (rd_valid), + .memc_cmd_full_i (memc_cmd_full_i), + .prbs_fseed_i (data_seed_i), + .cmd_sent (memc_cmd_instr_o), + .bl_sent (memc_bl_o[5:0]), + .cmd_en_i (cmd_rd_en), + .vio_instr_mode_value (vio_instr_mode_value), + + .data_mode_i (data_mode_r_b), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + .mode_load_i (mode_load_i), + + .addr_i (rd_addr), + .bl_i (rd_bl), + .data_rdy_o (memc_rd_en_o), + + .data_valid_i (rdpath_data_valid_i), + .data_i (rdpath_rd_data_i), + + + .data_error_o (cmp_error), + .cmp_data_valid (cmp_data_valid), + .cmp_data_o (cmp_data), + .rd_mdata_o (mem_rd_data ), + .cmp_addr_o (cmp_addr), + .cmp_bl_o (cmp_bl), + .dq_error_bytelane_cmp (dq_error_bytelane_cmp), + + //**************************************************** + .cumlative_dq_lane_error_r (cumlative_dq_lane_error), + .cumlative_dq_r0_bit_error_r (cumlative_dq_r0_bit_error), + .cumlative_dq_f0_bit_error_r (cumlative_dq_f0_bit_error), + .cumlative_dq_r1_bit_error_r (cumlative_dq_r1_bit_error), + .cumlative_dq_f1_bit_error_r (cumlative_dq_f1_bit_error), + .dq_r0_bit_error_r (dq_r0_bit_error_r), + .dq_f0_bit_error_r (dq_f0_bit_error_r), + .dq_r1_bit_error_r (dq_r1_bit_error_r), + .dq_f1_bit_error_r (dq_f1_bit_error_r), + + .dq_r0_read_bit_r (dq_r0_read_bit), + .dq_f0_read_bit_r (dq_f0_read_bit), + .dq_r1_read_bit_r (dq_r1_read_bit), + .dq_f1_read_bit_r (dq_f1_read_bit), + .dq_r0_expect_bit_r (dq_r0_expect_bit), + .dq_f0_expect_bit_r (dq_f0_expect_bit ), + .dq_r1_expect_bit_r (dq_r1_expect_bit), + .dq_f1_expect_bit_r (dq_f1_expect_bit ), + .error_addr_o (error_addr) + + + + + + ); + +end +else +begin + assign cmp_error = 1'b0; + assign cmp_data_valid = 1'b0; + assign cmp_data ='b0; + +end + +endgenerate + + + +assign wr_path_data_rdy_i = !(memc_wr_full_i ) ;//& (~memc_cmd_full_i); + +generate +if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") +begin : WR_PATH + + mig_7series_v4_2_write_data_path + #( + + .TCQ (TCQ), + .FAMILY (FAMILY), + .nCK_PER_CLK (nCK_PER_CLK), + .MEM_TYPE (MEM_TYPE), + + .START_ADDR (PRBS_SADDR), + .BL_WIDTH (BL_WIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .EYE_TEST (EYE_TEST) + + ) + write_data_path + ( + .clk_i(clk_i), + .rst_i (rst_rb), + .cmd_rdy_o (wr_rdy), + .cmd_valid_i (wr_valid), + .cmd_validB_i (wr_validB), + .cmd_validC_i (wr_validC), + .prbs_fseed_i (data_seed_i), + .mode_load_i (mode_load_i), + .wr_data_mask_gen_i (wr_data_mask_gen_i), + .mem_init_done_i (mem_init_done), + + + .data_mode_i (data_mode_r_c), + .last_word_wr_o (last_word_wr), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + + .addr_i (wr_addr), + .bl_i (wr_bl), + .memc_cmd_full_i (memc_cmd_full_i), + .data_rdy_i (wr_path_data_rdy_i), + .data_valid_o (memc_wr_en), + .data_o (memc_wr_data), + .data_mask_o (memc_wr_mask_o), + .data_wr_end_o (memc_wr_data_end) + ); + +end +else +begin + assign memc_wr_en = 1'b0; + assign memc_wr_data = 'b0; + assign memc_wr_mask_o = 'b0; + +end + +endgenerate + +generate +if (MEM_TYPE != "QDR2PLUS" && (FAMILY == "VIRTEX6" || FAMILY == "SPARTAN6" )) + begin: nonQDR_WR + assign memc_wr_en_o = memc_wr_en; + assign memc_wr_data_o = memc_wr_data ; + assign memc_wr_data_end_o = (nCK_PER_CLK == 4) ? memc_wr_data_end: memc_wr_data_end; + end +// QDR +else + begin: QDR_WR + + always @ (posedge clk_i) + memc_wr_data_r <= memc_wr_data; + + assign memc_wr_en_o = memc_wr_en; + assign memc_wr_data_o = memc_wr_data_r ; + + assign memc_wr_data_end_o = memc_wr_data_end; + end +endgenerate + +//QDR +always @ (posedge clk_i) +begin + +if (memc_wr_full_i) + begin + memc_wr_en_r <= 1'b0; + end +else + begin + memc_wr_en_r <= memc_wr_en; + end + +end + + mig_7series_v4_2_tg_status + #( + + .TCQ (TCQ), + .DWIDTH (DWIDTH) + ) + tg_status + ( + .clk_i (clk_i), + .rst_i (rst_ra[2]), + .manual_clear_error (manual_clear_error), + .data_error_i (cmp_error), + .cmp_data_i (cmp_data), + .rd_data_i (mem_rd_data ), + .cmp_addr_i (cmp_addr), + .cmp_bl_i (cmp_bl), + .mcb_cmd_full_i (memc_cmd_full_i), + .mcb_wr_full_i (memc_wr_full_i), + .mcb_rd_empty_i (memc_rd_empty_i), + .error_status (error_status), + .error (error) + ); + + +endmodule // memc_traffic_gen diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_rd_data_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_rd_data_gen.v new file mode 100644 index 0000000..44a86a2 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_rd_data_gen.v @@ -0,0 +1,382 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: rd_data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module has all the timing control for generating "compare data" +// to compare the read data from memory. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_rd_data_gen # + ( + parameter TCQ = 100, + parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6" + parameter MEM_TYPE = "DDR3", + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + + parameter MEM_BURST_LEN = 8, + parameter START_ADDR = 32'h00000000, + + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter COLUMN_WIDTH = 10 + + ) + ( + input clk_i, // + input [4:0] rst_i, + input [31:0] prbs_fseed_i, + input [3:0] data_mode_i, // "00" = bram; + input mode_load_i, + input [3:0] vio_instr_mode_value, + + output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. + // And then it should reasserted when + // it is generating the last_word. + input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. + output reg cmd_start_o, +// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern. + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + + input [31:0] fixed_data_i, + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data + output user_bl_cnt_is_1_o, + input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6 + // connect from mcb_rd_empty when used as rd_data_gen in sp6 + // connect from rd_data_valid in v6 + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the + // pattern is available. +// output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1 + output [31:0] tg_st_addr_o, + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1 + +); +// + + + +wire [31:0] prbs_data; +reg cmd_start; +reg [31:0] adata; +reg [31:0] hdata; +reg [31:0] ndata; +reg [31:0] w1data; +reg [NUM_DQ_PINS*4-1:0] v6_w1data; + +reg [31:0] w0data; +reg [DWIDTH-1:0] data; +reg cmd_rdy; +reg [BL_WIDTH:0]user_burst_cnt; +reg [31:0] w3data; +reg prefetch; +assign data_port_fifo_rdy = data_rdy_i; + + + + +reg user_bl_cnt_is_1; +assign user_bl_cnt_is_1_o = user_bl_cnt_is_1; +always @ (posedge clk_i) +begin +if (data_port_fifo_rdy) + if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6") + || (user_burst_cnt == 2 && FAMILY == "VIRTEX6") + ) + + user_bl_cnt_is_1 <= #TCQ 1'b1; + else + user_bl_cnt_is_1 <= #TCQ 1'b0; +end + + +//reg cmd_start_b; +always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch) +begin + + cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ; + cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ; + +end + + + + +// counter to count user burst length +// verilint STARC-2.2.3.3 off +always @( posedge clk_i) +begin + if ( rst_i[0] ) + user_burst_cnt <= #TCQ 'd0; + else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin + + // SPATAN6 has maximum of burst length of 64. + if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000) + begin + user_burst_cnt[6:0] <= #TCQ 7'd64; + user_burst_cnt[BL_WIDTH:7] <= 'b0; + end + else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}}) + user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}}; + else + user_burst_cnt <= #TCQ {1'b0,bl_i }; + end + else if(data_port_fifo_rdy) + if (user_burst_cnt != 6'd0) + user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; + else + user_burst_cnt <= #TCQ 'd0; + +end +// verilint STARC-2.2.3.3 on + +// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i +// is assert and reassert during the last data + +//data_valid_o logic + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + prefetch <= #TCQ 1'b1; + else if (data_port_fifo_rdy || cmd_start) + prefetch <= #TCQ 1'b0; + + else if (user_burst_cnt == 0 && ~data_port_fifo_rdy) + prefetch <= #TCQ 1'b1; + +end +assign cmd_rdy_o = cmd_rdy ; + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdy <= #TCQ 1'b1; + + else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch )) + cmd_rdy <= #TCQ 1'b0; + else if ((data_port_fifo_rdy && user_burst_cnt == 2 && vio_instr_mode_value != 7 ) || + (data_port_fifo_rdy && user_burst_cnt == 1 && vio_instr_mode_value == 7 )) + + cmd_rdy <= #TCQ 1'b1; + + +end + + + + +always @ (data_port_fifo_rdy) +if (FAMILY == "SPARTAN6") + data_valid_o = data_port_fifo_rdy; +else + data_valid_o = data_port_fifo_rdy; + + +/* +generate +if (FAMILY == "SPARTAN6") +begin : SP6_DGEN +s7ven_data_gen # + +( + .TCQ (TCQ), + .DMODE ("READ"), + .nCK_PER_CLK (nCK_PER_CLK), + .FAMILY (FAMILY), + + .ADDR_WIDTH (32 ), + .BL_WIDTH (BL_WIDTH ), + .MEM_BURST_LEN (MEM_BURST_LEN), + .DWIDTH (DWIDTH ), + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .START_ADDR (START_ADDR), + + .COLUMN_WIDTH (COLUMN_WIDTH) + + ) + s7ven_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .mem_init_done_i (1'b1), + .wr_data_mask_gen_i (1'b0), + + .prbs_fseed_i (prbs_fseed_i), + .mode_load_i (mode_load_i), + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_start ), + .cmd_startC (cmd_start ), + .cmd_startD (cmd_start ), + .cmd_startE (cmd_start ), + .m_addr_i (addr_i),//(m_addr_i ), + + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (data_port_fifo_rdy ), + .data_o (data_o ), + .data_mask_o (), + + .bram_rd_valid_o () + ); + +end + +endgenerate*/ +//generate +//if (FAMILY == "VIRTEX6") +//begin : V_DGEN +mig_7series_v4_2_s7ven_data_gen # +( + .TCQ (TCQ), + .DMODE ("READ"), + .nCK_PER_CLK (nCK_PER_CLK), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + + .ADDR_WIDTH (32 ), + .BL_WIDTH (BL_WIDTH ), + .MEM_BURST_LEN (MEM_BURST_LEN), + .DWIDTH (DWIDTH ), + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .START_ADDR (START_ADDR), + + .COLUMN_WIDTH (COLUMN_WIDTH) + + ) + s7ven_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .mem_init_done_i (1'b1), + .wr_data_mask_gen_i (1'b0), + + .prbs_fseed_i (prbs_fseed_i), + .mode_load_i (mode_load_i), + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_start ), + .cmd_startC (cmd_start ), + .cmd_startD (cmd_start ), + .cmd_startE (cmd_start ), + .m_addr_i (addr_i),//(m_addr_i ), + + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (data_port_fifo_rdy ), + .data_o (data_o ), + .tg_st_addr_o (tg_st_addr_o), + .data_mask_o (), + + .bram_rd_valid_o () + ); + +//end +//endgenerate + + + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_read_data_path.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_read_data_path.v new file mode 100644 index 0000000..fff048e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_read_data_path.v @@ -0,0 +1,751 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: read_data_path.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This is top level of read path and also consist of comparison logic +// for read data. +//Reference: +//Revision History: 11/18 /2011 Fixed a localparam ER_WIDTH bug for QDR2+ case. +// 03/15/2012 Registered error_byte, error_bit to avoid false +// comparison when data_valid_i is deasserted. +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_read_data_path #( + parameter TCQ = 100, + parameter START_ADDR = 32'h00000000, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + + parameter MEM_TYPE = "DDR3", + parameter FAMILY = "VIRTEX6", + parameter BL_WIDTH = 6, + parameter MEM_BURST_LEN = 8, + parameter ADDR_WIDTH = 32, + parameter CMP_DATA_PIPE_STAGES = 3, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter DWIDTH = nCK_PER_CLK * 2 * NUM_DQ_PINS, + + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter MEM_COL_WIDTH = 10, + parameter SIMULATION = "FALSE" + + ) + ( + + + input clk_i, + input [9:0] rst_i, + input manual_clear_error, + output cmd_rdy_o, + input cmd_valid_i, + input memc_cmd_full_i, + input [31:0] prbs_fseed_i, + input mode_load_i, + input [3:0] vio_instr_mode_value, + + input [3:0] data_mode_i, + input [2:0] cmd_sent, + input [5:0] bl_sent , + input cmd_en_i , +// input [31:0] m_addr_i, + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [31:0] fixed_data_i, + input [31:0] addr_i, + input [BL_WIDTH-1:0] bl_i, + + + output data_rdy_o, + input data_valid_i, + input [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_i, + output data_error_o, //data_error on user data bus side + output [DWIDTH-1:0] cmp_data_o, + output [DWIDTH-1:0] rd_mdata_o , + output cmp_data_valid, + output [31:0] cmp_addr_o, + output [5 :0] cmp_bl_o, + output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane + output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error_r, // V6: latched error byte lane that occure on + // first error + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error_r , + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error_r , + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error_r , + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error_r , + + output reg [NUM_DQ_PINS-1:0] dq_r0_bit_error_r, + output reg [NUM_DQ_PINS-1:0] dq_f0_bit_error_r, + output reg [NUM_DQ_PINS-1:0] dq_r1_bit_error_r, + output reg [NUM_DQ_PINS-1:0] dq_f1_bit_error_r, + + + output reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_r, + output [31:0] error_addr_o + + + ); + + wire gen_rdy; + wire gen_valid; + wire [31:0] gen_addr; + wire [BL_WIDTH-1:0] gen_bl; + + wire cmp_rdy; + wire cmp_valid; + wire [31:0] cmp_addr; + wire [5:0] cmp_bl; + + reg data_error; + wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data; + wire [31:0] tg_st_addr_o; + reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data_r1,cmp_data_r2; + reg last_word_rd; + reg [5:0] bl_counter; + wire cmd_rdy; + wire user_bl_cnt_is_1; + wire data_rdy; + reg [DWIDTH:0] delayed_data; + wire rd_mdata_en; + reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r1; + reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r2; + reg force_wrcmd_gen; + reg wait_bl_end; + reg wait_bl_end_r1; +reg l_data_error ; +reg u_data_error; +reg v6_data_cmp_valid; +wire [DWIDTH -1 :0] rd_v6_mdata; +reg [DWIDTH -1 :0] cmpdata_r; +wire [DWIDTH -1 :0] rd_mdata; + reg cmp_data_en; + +localparam ER_WIDTH = ( MEM_TYPE == "QDR2PLUS" && nCK_PER_CLK == 2) ? (NUM_DQ_PINS*MEM_BURST_LEN)/9 : + ( MEM_TYPE != "QDR2PLUS" && nCK_PER_CLK == 2) ? NUM_DQ_PINS/2 : NUM_DQ_PINS; + +reg [ER_WIDTH - 1:0] error_byte; +reg [ER_WIDTH - 1:0] error_byte_r1; + +reg [NUM_DQ_PINS*nCK_PER_CLK*2 - 1:0] error_bit; +reg [NUM_DQ_PINS*nCK_PER_CLK*2 -1:0] error_bit_r1; + +wire [NUM_DQ_PINS-1:0] dq_bit_error; +wire [NUM_DQ_PINS-1:0] cumlative_dq_bit_error_c; + +wire [ NUM_DQ_PINS/8-1:0] dq_lane_error; +reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r1; +reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r2; +reg [NUM_DQ_PINS-1:0] dq_bit_error_r1; +wire [NUM_DQ_PINS-1:0] cumlative_dq_r0_bit_error_c; +wire [NUM_DQ_PINS-1:0] cumlative_dq_f0_bit_error_c; +wire [NUM_DQ_PINS-1:0] cumlative_dq_r1_bit_error_c; +wire [NUM_DQ_PINS-1:0] cumlative_dq_f1_bit_error_c; + + +wire [ NUM_DQ_PINS/8-1:0] cum_dq_lane_error_mask; +wire [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_c; +reg [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_reg; + + + reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_rdlay1; + wire [NUM_DQ_PINS-1:0] dq_r0_bit_error ; + wire [NUM_DQ_PINS-1:0] dq_f0_bit_error ; + wire [NUM_DQ_PINS-1:0] dq_r1_bit_error ; + wire [NUM_DQ_PINS-1:0] dq_f1_bit_error ; + reg [31:0] error_addr_r1; + reg [31:0] error_addr_r2; + reg [31:0] error_addr_r3; + reg data_valid_r1; + reg data_valid_r2; + wire cmd_start_i; + + + + always @ (posedge clk_i) begin + wait_bl_end_r1 <= #TCQ wait_bl_end; + rd_data_r1 <= #TCQ data_i; + rd_data_r2 <= #TCQ rd_data_r1; + end + + reg [7:0] force_wrcmd_timeout_cnts ; + + always @ (posedge clk_i) begin + if (rst_i[0]) + force_wrcmd_gen <= #TCQ 1'b0; + else if ((wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111) + force_wrcmd_gen <= #TCQ 1'b0; + + else if ((cmd_valid_i && bl_i > 16) || wait_bl_end ) + force_wrcmd_gen <= #TCQ 1'b1; + end + + + always @ (posedge clk_i) begin + if (rst_i[0]) + force_wrcmd_timeout_cnts <= #TCQ 'b0; + else if (wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) + force_wrcmd_timeout_cnts <= #TCQ 'b0; + + else if (force_wrcmd_gen) + force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1'b1; + end + + always @ (posedge clk_i) + if (rst_i[0]) + wait_bl_end <= #TCQ 1'b0; + else if (force_wrcmd_timeout_cnts == 8'b11111111) + wait_bl_end <= #TCQ 1'b0; + + else if (gen_rdy && gen_valid && gen_bl > 16) + wait_bl_end <= #TCQ 1'b1; + else if (wait_bl_end && user_bl_cnt_is_1) + wait_bl_end <= #TCQ 1'b0; + + + assign cmd_rdy_o = cmd_rdy; + mig_7series_v4_2_read_posted_fifo # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .nCK_PER_CLK (nCK_PER_CLK), + .MEM_BURST_LEN (MEM_BURST_LEN), + .ADDR_WIDTH (32), + .BL_WIDTH (BL_WIDTH) + ) + read_postedfifo( + .clk_i (clk_i), + .rst_i (rst_i[0]), + .cmd_rdy_o (cmd_rdy ), + .cmd_valid_i (cmd_valid_i ), + .data_valid_i (data_rdy ), // input to + .addr_i (addr_i ), + .bl_i (bl_i ), + .cmd_start_i (cmd_start), + .cmd_sent (cmd_sent), + .bl_sent (bl_sent ), + .cmd_en_i (cmd_en_i), + .memc_cmd_full_i (memc_cmd_full_i), + .gen_valid_o (gen_valid ), + .gen_addr_o (gen_addr ), + .gen_bl_o (gen_bl ), + .rd_mdata_en (rd_mdata_en) + ); + + + + + mig_7series_v4_2_rd_data_gen # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + + .BL_WIDTH (BL_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + + .MEM_BURST_LEN (MEM_BURST_LEN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .START_ADDR (START_ADDR), + + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH(DWIDTH), + .COLUMN_WIDTH (MEM_COL_WIDTH) + + ) + rd_datagen( + .clk_i (clk_i ), + .rst_i (rst_i[4:0]), + .prbs_fseed_i (prbs_fseed_i), + .data_mode_i (data_mode_i ), + .vio_instr_mode_value (vio_instr_mode_value), + + .cmd_rdy_o (gen_rdy ), + .cmd_valid_i (gen_valid ), + .mode_load_i (mode_load_i), + .cmd_start_o (cmd_start), + // .m_addr_i (m_addr_i ), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + + .fixed_data_i (fixed_data_i), + + .addr_i (gen_addr ), + .bl_i (gen_bl ), + .user_bl_cnt_is_1_o (user_bl_cnt_is_1), + .data_rdy_i (data_valid_i ), // input to + .data_valid_o (cmp_valid ), + .tg_st_addr_o (tg_st_addr_o), + .data_o (cmp_data ) + ); + + mig_7series_v4_2_afifo # + ( + .TCQ (TCQ), + .DSIZE (DWIDTH), + .FIFO_DEPTH (32), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_mdata_fifo + ( + .wr_clk (clk_i), + .rst (rst_i[0]), + .wr_en (data_valid_i), + .wr_data (data_i), + .rd_en (rd_mdata_en), + .rd_clk (clk_i), + .rd_data (rd_v6_mdata), + .full (), + .empty (), + .almost_full () + ); + +always @ (posedge clk_i) +begin +// delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data}; + cmp_data_r1 <= #TCQ cmp_data; + cmp_data_r2 <= #TCQ cmp_data_r1; +end +assign rd_mdata_o = rd_mdata; + +assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r1: + (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata: + rd_data_r2; + +assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en : + (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i; + + + + +assign cmp_data_o = cmp_data_r2; +assign cmp_addr_o = tg_st_addr_o;//gen_addr; +assign cmp_bl_o = gen_bl[5:0]; + + + +assign data_rdy_o = data_rdy; +assign data_rdy = cmp_valid & data_valid_i; + + always @ (posedge clk_i) + v6_data_cmp_valid <= #TCQ rd_mdata_en; + + + always @ (posedge clk_i) + cmp_data_en <= #TCQ data_rdy; + + +genvar i; + + generate + if (FAMILY == "SPARTAN6") + begin: gen_error_sp6 + always @ (posedge clk_i) + begin + if (cmp_data_en) + l_data_error <= #TCQ (rd_data_r1[DWIDTH/2-1:0] != cmp_data_r1[DWIDTH/2-1:0]); + else + l_data_error <= #TCQ 1'b0; + + if (cmp_data_en) + u_data_error <= #TCQ (rd_data_r1[DWIDTH-1:DWIDTH/2] != cmp_data_r1[DWIDTH-1:DWIDTH/2]); + else + u_data_error <= #TCQ 1'b0; + + data_error <= #TCQ l_data_error | u_data_error; + //synthesis translate_off + if (data_error) + $display ("ERROR at time %t" , $time); + //synthesis translate_on + + end + +end +else +// if (FAMILY == "VIRTEX6" ) + begin: gen_error_v7 + if (nCK_PER_CLK == 2) + begin + if (MEM_TYPE == "QDR2PLUS") + begin: qdr_design + for (i = 0; i < (NUM_DQ_PINS*MEM_BURST_LEN)/9; i = i + 1) + begin: gen_cmp_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_byte[i] <= (data_i[9*(i+1)-1:9*i] !== cmp_data[9*(i+1)-1:9*i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_byte[i] <= (data_i[9*(i+1)-1:9*i] != cmp_data[9*(i+1)-1:9*i]) ; + else + error_byte[i] <= 1'b0; + end + for (i = 0; i < NUM_DQ_PINS*MEM_BURST_LEN; i = i + 1) + begin: gen_cmp_bit_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_bit[i] <= (data_i[i] !== cmp_data[i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_bit[i] <= (data_i[i] != cmp_data[i]) ; + else + error_bit[i] <= 1'b0; + end + end + else + begin: ddr_design + for (i = 0; i < NUM_DQ_PINS/2; i = i + 1) + begin: gen_cmp_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ; + else + error_byte[i] <= 1'b0; + end + for (i = 0; i < NUM_DQ_PINS*4; i = i + 1) + begin: gen_cmp_bit_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_bit[i] <= ( (data_i[i] !== cmp_data[i]) ) ; + else + //synthesis translate_on + if (data_valid_i) + error_bit[i] <= ( (data_i[i] != cmp_data[i]) ) ; + else + error_bit[i] <= 1'b0; + end + end + end + else //nCK_PER_CLK == 4 + begin + for (i = 0; i < NUM_DQ_PINS; i = i + 1) + begin: gen_cmp_4 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ; + else + error_byte[i] <= 1'b0; + end + + for (i = 0; i < NUM_DQ_PINS*8; i = i + 1) + begin: gen_cmp_bit_4 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_bit[i] <= (data_i[i] !== cmp_data[i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_bit[i] <= (data_i[i] != cmp_data[i]) ; + else + error_bit[i] <= 1'b0; + end + end + +always @ (posedge clk_i) +begin + dq_r0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*1 - 1:0]; + dq_f0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1]; + dq_r1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2]; + dq_f1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3]; + + dq_r0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*1 - 1:0]; + dq_f0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1]; + dq_r1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2]; + dq_f1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3]; + + dq_r0_read_bit_r <= #TCQ dq_r0_read_bit_rdlay1 ; + dq_f0_read_bit_r <= #TCQ dq_f0_read_bit_rdlay1 ; + dq_r1_read_bit_r <= #TCQ dq_r1_read_bit_rdlay1 ; + dq_f1_read_bit_r <= #TCQ dq_f1_read_bit_rdlay1 ; + + dq_r0_expect_bit_r <= #TCQ dq_r0_expect_bit_rdlay1; + dq_f0_expect_bit_r <= #TCQ dq_f0_expect_bit_rdlay1; + dq_r1_expect_bit_r <= #TCQ dq_r1_expect_bit_rdlay1; + dq_f1_expect_bit_r <= #TCQ dq_f1_expect_bit_rdlay1; + + + + + +end +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + + error_byte_r1 <= #TCQ 'b0; + error_bit_r1 <= #TCQ 'b0; + + end + else if (data_valid_r1) begin + + error_byte_r1 <= #TCQ error_byte; + error_bit_r1 <= #TCQ error_bit; + end + else + begin + error_byte_r1 <= #TCQ 'b0; + error_bit_r1 <= #TCQ 'b0; + end +end +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) + data_error <= #TCQ 1'b0; + else if (data_valid_r2) + data_error <= #TCQ | error_byte_r1; + else + data_error <= #TCQ 1'b0; + + //synthesis translate_off + if (data_error) + $display ("ERROR: Expected data=%h, Received data=%h @ %t" ,cmp_data_r2, rd_data_r2, $time); + //synthesis translate_on + + end + +localparam NUM_OF_DQS = (MEM_TYPE == "QDR2PLUS") ? 9 : 8 ; + + if (MEM_TYPE == "QDR2PLUS") begin: qdr_design_error_calc + + if (MEM_BURST_LEN == 4) begin: bl4_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end else begin: bl2_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end + + end else begin: ddr_design_error_calc + + if (nCK_PER_CLK == 4) begin: ck_4to1_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*4/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*5/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*6/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*7/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end else if (nCK_PER_CLK == 2) begin: ck_2to1_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end + end + + // mapped the user bits error to dq bits error + + // mapper the error to rising 0 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_r0_error_mapbit + assign dq_r0_bit_error[i] = (error_bit_r1[i]); + assign cumlative_dq_r0_bit_error_c[i] = cumlative_dq_r0_bit_error_r[i] | dq_r0_bit_error[i]; + + end + // mapper the error to falling 0 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_f0_error_mapbit + assign dq_f0_bit_error[i] = (error_bit_r1[i+NUM_DQ_PINS*1] ); + assign cumlative_dq_f0_bit_error_c[i] = cumlative_dq_f0_bit_error_r[i] | dq_f0_bit_error[i]; + + end + + // mapper the error to rising 1 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_r1_error_mapbit + assign dq_r1_bit_error[i] = (error_bit_r1[i+ (NUM_DQ_PINS*2)]); + assign cumlative_dq_r1_bit_error_c[i] = cumlative_dq_r1_bit_error_r[i] | dq_r1_bit_error[i]; + + end + + // mapper the error to falling 1 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_f1_error_mapbit + assign dq_f1_bit_error[i] = ( error_bit_r1[i+ (NUM_DQ_PINS*3)]); + assign cumlative_dq_f1_bit_error_c[i] = cumlative_dq_f1_bit_error_r[i] | dq_f1_bit_error[i]; + end +reg COuta; +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + dq_bit_error_r1 <= #TCQ 'b0; + dq_lane_error_r1 <= #TCQ 'b0; + dq_lane_error_r2 <= #TCQ 'b0; + data_valid_r1 <= #TCQ 1'b0; + data_valid_r2 <= #TCQ 1'b0; + dq_r0_bit_error_r <= #TCQ 'b0; + dq_f0_bit_error_r <= #TCQ 'b0; + dq_r1_bit_error_r <= #TCQ 'b0; + dq_f1_bit_error_r <= #TCQ 'b0; + + cumlative_dq_lane_error_reg <= #TCQ 'b0; + cumlative_dq_r0_bit_error_r <= #TCQ 'b0; + cumlative_dq_f0_bit_error_r <= #TCQ 'b0; + cumlative_dq_r1_bit_error_r <= #TCQ 'b0; + cumlative_dq_f1_bit_error_r <= #TCQ 'b0; + error_addr_r1 <= #TCQ 'b0; + error_addr_r2 <= #TCQ 'b0; + error_addr_r3 <= #TCQ 'b0; + + end + else begin + data_valid_r1 <= #TCQ data_valid_i; + data_valid_r2 <= #TCQ data_valid_r1; + dq_lane_error_r1 <= #TCQ dq_lane_error; + dq_bit_error_r1 <= #TCQ dq_bit_error; + + cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c; + cumlative_dq_r0_bit_error_r <= #TCQ cumlative_dq_r0_bit_error_c; + + cumlative_dq_f0_bit_error_r <= #TCQ cumlative_dq_f0_bit_error_c; + cumlative_dq_r1_bit_error_r <= #TCQ cumlative_dq_r1_bit_error_c; + cumlative_dq_f1_bit_error_r <= #TCQ cumlative_dq_f1_bit_error_c; + dq_r0_bit_error_r <= #TCQ dq_r0_bit_error; + dq_f0_bit_error_r <= #TCQ dq_f0_bit_error; + dq_r1_bit_error_r <= #TCQ dq_r1_bit_error; + dq_f1_bit_error_r <= #TCQ dq_f1_bit_error; + error_addr_r2 <= #TCQ error_addr_r1; + error_addr_r3 <= #TCQ error_addr_r2; + + if (rd_mdata_en) + error_addr_r1 <= #TCQ gen_addr; + else if (data_valid_i) + {COuta,error_addr_r1} <= #TCQ error_addr_r1 + 4; + + end +end + +end +endgenerate + +assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg; +assign dq_error_bytelane_cmp = dq_lane_error_r1; +assign data_error_o = data_error; +assign error_addr_o = error_addr_r3; + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v new file mode 100644 index 0000000..5c5aec5 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v @@ -0,0 +1,251 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: read_posted_fifo.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module instantiated by read_data_path module and sits between +// mcb_flow_control module and read_data_gen module to buffer up the +// commands that has sent to memory controller. +//Reference: +//Revision History: 3/14/2012 Adding support for "nCK_PER_CLK == 2" abd MEM_BURST_LEN == 2 " +//***************************************************************************** +`timescale 1ps/1ps + + module mig_7series_v4_2_read_posted_fifo # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter nCK_PER_CLK = 4, + parameter MEM_BURST_LEN = 4, + + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6 + ) + ( + input clk_i, + input rst_i, + output reg cmd_rdy_o, + input memc_cmd_full_i, + input cmd_valid_i, + input data_valid_i, + input cmd_start_i, + input [ADDR_WIDTH-1:0] addr_i, + input [BL_WIDTH-1:0] bl_i, + input [2:0] cmd_sent, + input [5:0] bl_sent , + input cmd_en_i , + + + output gen_valid_o, + output [ADDR_WIDTH-1:0] gen_addr_o, + output [BL_WIDTH-1:0] gen_bl_o, + output rd_mdata_en + + ); + +//reg empty_r; + reg rd_en_r; + wire full; + wire empty; + wire wr_en; + reg mcb_rd_fifo_port_almost_full; + reg [6:0] buf_avail_r; + reg [6:0] rd_data_received_counts; + reg [6:0] rd_data_counts_asked; + + reg dfifo_has_enough_room; + reg [1:0] wait_cnt; + reg wait_done; + + assign rd_mdata_en = rd_en_r; + + generate + if (FAMILY == "SPARTAN6") + begin: gen_sp6_cmd_rdy + + always @ (posedge clk_i) + cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done; + end + +// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") || +// (FAMILY == "VIRTEX6") ) + else + begin: gen_v6_cmd_rdy + + always @ (posedge clk_i) + cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room; + end + endgenerate + + always @ (posedge clk_i) + begin + if (rst_i) + wait_cnt <= #TCQ 'b0; + else if (cmd_rdy_o && cmd_valid_i) + wait_cnt <= #TCQ 2'b10; + else if (wait_cnt > 0) + wait_cnt <= #TCQ wait_cnt - 1'b1; + + end + + always @(posedge clk_i) + begin + if (rst_i) + wait_done <= #TCQ 1'b1; + else if (cmd_rdy_o && cmd_valid_i) + wait_done <= #TCQ 1'b0; + else if (wait_cnt == 0) + wait_done <= #TCQ 1'b1; + else + wait_done <= #TCQ 1'b0; + + end + + reg dfifo_has_enough_room_d1; + always @ (posedge clk_i) + begin + dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0; + dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ; + end + + // remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop + // sending more read commands but still accepting it if there is one coming. + assign wr_en = cmd_valid_i & !full & wait_done; + + + + always @ (posedge clk_i) + begin + if (rst_i) begin + rd_data_counts_asked <= #TCQ 'b0; + end + else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin + if (FAMILY == "SPARTAN6") + rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ; + else + // if (nCK_PER_CLK == 2 ) + // rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ; + // else + // rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ; + + if (nCK_PER_CLK == 4 || (nCK_PER_CLK == 2 && (MEM_BURST_LEN == 4 || MEM_BURST_LEN == 2 ) )) + rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ; + else if (nCK_PER_CLK == 2 && MEM_BURST_LEN == 8) + rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ; + + + + end + end + + always @ (posedge clk_i) + begin + if (rst_i) begin + rd_data_received_counts <= #TCQ 'b0; + end + else if (data_valid_i) begin + rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1; + end + end + + // calculate how many buf still available + always @ (posedge clk_i) + if (rd_data_received_counts[6] == rd_data_counts_asked[6]) + buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 ); + + else + buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] ); + + + always @ (posedge clk_i) begin + rd_en_r <= #TCQ cmd_start_i; + end + + + + assign gen_valid_o = !empty; + mig_7series_v4_2_afifo # + ( + .TCQ (TCQ), + .DSIZE (BL_WIDTH+ADDR_WIDTH), + .FIFO_DEPTH (16), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_fifo + ( + .wr_clk (clk_i), + .rst (rst_i), + .wr_en (wr_en), + .wr_data ({bl_i,addr_i}), + .rd_en (rd_en_r), + .rd_clk (clk_i), + .rd_data ({gen_bl_o,gen_addr_o}), + .full (full), + .empty (empty), + .almost_full () + + ); + + + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_s7ven_data_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_s7ven_data_gen.v new file mode 100644 index 0000000..39cf9ab --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_s7ven_data_gen.v @@ -0,0 +1,1047 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MEMC +// / / Filename: mcb_traffic_gen.v +// /___/ /\ Date Last Modified: $Date: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Virtex7 +//Design Name: s7ven_data_gen +//Purpose: This is top level module of memory traffic generator which can +// generate different CMD_PATTERN and DATA_PATTERN to Virtex 7 +// hard memory controller core. +// Supported Data pattern: 0 : Reserved. +// 1 : FIXED_DATA_MODE. +// 2 : ADDR_DATA_MODE +// 3 : HAMMER_DATA_MODE +// 4 : NEIGHBOR_DATA_MODE +// 5 : WALKING1_DATA_MODE +// 6 : WALKING0_DATA_MODE +// 7 : TRUE_PRBS_MODE +// +// +//Reference: +//Revision History: 1.1 +// 06/2011 Rewrite PRBS code. + +//***************************************************************************** + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + +module mig_7series_v4_2_s7ven_data_gen # + +( parameter DMODE = "WRITE", + parameter nCK_PER_CLK = 2, // 2: Memc core speed 1/2 of memory clock speed. + // User data bus width = 4 x DQs data width. + // 4: memc core speed 1/4 of memory clock speed. + // User data bus width = 8 x DQs data width. + parameter MEM_TYPE = "DDR3", + + parameter TCQ = 100, + parameter BL_WIDTH = 6, // USER_Interface Command Burst Length + parameter FAMILY = "SPARTAN6", + + parameter EYE_TEST = "FALSE", + parameter ADDR_WIDTH = 32, + parameter MEM_BURST_LEN = 8, + parameter START_ADDR = 32'h00000000, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 72, + parameter COLUMN_WIDTH = 10, + parameter SEL_VICTIM_LINE = 3 // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern +// parameter [287:0] ALL_1 = {288{1'b1}}, +// parameter [287:0] ALL_0 = {288{1'b0}} + + + ) + ( + input clk_i, // + input rst_i, + input [31:0] prbs_fseed_i, + input mode_load_i, + input mem_init_done_i, + input wr_data_mask_gen_i, + input [3:0] data_mode_i, // "00" = bram; + input data_rdy_i, + input cmd_startA, + input cmd_startB, + input cmd_startC, + input cmd_startD, + input cmd_startE, + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern. + input [31:0] fixed_data_i, + + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH:0] user_burst_cnt, // generated burst length for control the burst data + + input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen + // connect from mcb_rd_empty when used as rd_data_gen + // When both data_rdy and data_valid is asserted, the ouput data is valid. + // input [(DWIDTH/8)-1:0] wr_mask_count; + output [(NUM_DQ_PINS*nCK_PER_CLK*2/8)-1:0] data_mask_o, + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o , // generated data pattern + output reg [31:0] tg_st_addr_o, + output bram_rd_valid_o +); +// + +localparam PRBS_WIDTH = 8;//BL_WIDTH; +localparam TAPS_VALUE = (BL_WIDTH == 8) ? 8'b10001110 : + // (BL_WIDTH == 10) ? 10'b1000000100: + 8'b10001110 ; + + +wire [31:0] prbs_data; +reg [35:0] acounts; + +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] fdata; +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] bdata; +wire [31:0] bram_data; + +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata_tmp; +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata; + +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] hammer_data; + +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data; +reg [NUM_DQ_PINS*2-1:0] hdata; + +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w0data; +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data; + +reg burst_count_reached2; + +reg data_valid; +reg [2:0] walk_cnt; +reg [ADDR_WIDTH-1:0] user_address; +reg [ADDR_WIDTH-1:0] m_addr_r; // generated address used to determine data pattern. +reg sel_w1gen_logic; +//reg [7:0] BLANK; +reg [4*NUM_DQ_PINS -1 :0] sel_victimline_r; +reg data_clk_en,data_clk_en2 /* synthesis syn_maxfan = 10 */; +wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] full_prbs_data2; +wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] psuedo_prbs_data; + +wire [127:0] prbs_shift_value; +reg next_calib_data; +reg [2*nCK_PER_CLK*NUM_DQ_PINS-1:0 ] calib_data; +wire [2*nCK_PER_CLK*NUM_DQ_PINS/8 -1:0] w1data_group; +wire [31:0] mcb_prbs_data; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_0; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_0; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_1; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_1; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_2; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_2; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_3; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_3 ; + +wire [BL_WIDTH-1:0] prbs_o0,prbs_o1,prbs_o2,prbs_o3,prbs_o4,prbs_o5,prbs_o6,prbs_o7; +wire [BL_WIDTH-1:0] prbs_o8,prbs_o9,prbs_o10,prbs_o11,prbs_o12,prbs_o13,prbs_o14,prbs_o15; + + +//wire [nCK_PER_CLK * 32 -1 :0] prbs_shift_value; + +wire [32*NUM_DQ_PINS-1:0] ReSeedcounter; + + +reg [3:0] htstpoint ; +reg data_clk_en2_r; +reg [NUM_DQ_PINS-1:0] wdatamask_ripplecnt; +//wire [4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] ALL_1 = +reg mode_load_r; +reg user_burst_cnt_larger_1_r; +reg user_burst_cnt_larger_bram; + + +integer i,j,k; + +localparam NUM_WIDTH = 2*nCK_PER_CLK*NUM_DQ_PINS; +localparam USER_BUS_DWIDTH = (nCK_PER_CLK == 2) ? NUM_DQ_PINS*4 : NUM_DQ_PINS*8; + +// MODIFIED richc 061711 +//wire [PRBS_WIDTH-1:0] prbs_seed; + wire [2*nCK_PER_CLK-1:0] prbs_out [NUM_DQ_PINS-1:0]; + wire [PRBS_WIDTH-1:0] prbs_seed [NUM_DQ_PINS-1:0]; +//********************************************************************************************* +localparam BRAM_DATAL_MODE = 4'b0000; +localparam FIXED_DATA_MODE = 4'b0001; +localparam ADDR_DATA_MODE = 4'b0010; +localparam HAMMER_DATA_MODE = 4'b0011; +localparam NEIGHBOR_DATA_MODE = 4'b0100; +localparam WALKING1_DATA_MODE = 4'b0101; +localparam WALKING0_DATA_MODE = 4'b0110; +localparam PRBS_DATA_MODE = 4'b0111; + +assign data_o = data; +generate +if (nCK_PER_CLK == 4) +begin: full_prbs_data64 +//always @ (prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0) + assign full_prbs_data2 = {prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0}; +end +else +begin: full_prbs_data32 + assign full_prbs_data2 = {prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0}; +end +endgenerate +generate + +genvar p; + +for (p = 0; p < NUM_DQ_PINS*nCK_PER_CLK*2/32; p = p+1) +begin + assign psuedo_prbs_data[p*32+31:p*32] = mcb_prbs_data; + +end +endgenerate + + + +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data_o; +reg [3:0] data_mode_rr_a; +reg [3:0] data_mode_rr_c; + +// write data mask generation. +// Only support data pattern = address data mode. +// When wdatamask_ripple_cnt is asserted, the corresponding wr_data word will be jammed with 8'hff. + +assign data_mask_o = (wr_data_mask_gen_i == 1'b1 && mem_init_done_i) ? wdatamask_ripplecnt :{ NUM_DQ_PINS*nCK_PER_CLK*2/8{1'b0}}; + +always @ (posedge clk_i) +begin +if (rst_i || ~wr_data_mask_gen_i || ~mem_init_done_i) + wdatamask_ripplecnt <= 'b0; +else if (cmd_startA) + //wdatamask_ripplecnt <= {15'd0,1'b1}; + wdatamask_ripplecnt <= {{NUM_DQ_PINS-1{1'b0}},1'b1}; + +else if (user_burst_cnt_larger_1_r && data_rdy_i) + wdatamask_ripplecnt <= {wdatamask_ripplecnt[NUM_DQ_PINS-2:0],wdatamask_ripplecnt[NUM_DQ_PINS-1]}; + + +end + + +generate +genvar n; +for (n = 0; n < NUM_DQ_PINS*nCK_PER_CLK*2/8; n = n+1) +begin + + if (MEM_TYPE == "QDR2PLUS") + assign adata = adata_tmp;// QDR not supporting masking + else + assign adata[n*8+7:n*8] = adata_tmp[n*8+7:n*8]| {8{wdatamask_ripplecnt[NUM_DQ_PINS-1]}}; + +end +endgenerate + + +always @ (posedge clk_i) +begin + data_mode_rr_a <= #TCQ data_mode_i; + data_mode_rr_c <= #TCQ data_mode_i; + +end + + + +assign bdata = {USER_BUS_DWIDTH/32{bram_data[31:0]}}; + +// selected data pattern go through "data" mux to user data bus. +// 72 pin 1: failed +always @ (bdata,calib_data,hammer_data,adata,data_mode_rr_a,w1data,full_prbs_data2,psuedo_prbs_data) +begin + case(data_mode_rr_a) // + // Simple Data Pattern for bring up + // 0: Reserved + // 1: 32 bits fixed_data from user defined inputs. + // The data from this static pattern is concatenated together multiple times + // to make up the required number of bits as needed. + // 2: 32 bits address as data + // The data from this pattern is concatenated together multiple times + // to make up the required number of bits as needed. + // 4: simple 8data pattern and repeats every 8 words. The pattern is embedded in RAM. + // 5,6: Walkign 1,0 data. + // a Calibration data pattern + + // 0,1,2,3,4,9: use bram to implemnt. + 4'b0000,4'b0001,4'b0100,4'b1001: data = bdata; + 4'b0010: data = adata; // address as data + + 4'b0011: data = hammer_data; + + + 4'b0101, 4'b110: data = w1data; // walking 1 or walking 0 data + // when vio_instr_mode_value set to 4'hf,the init_mem_pattern_ctr module + // will automatically set the data_mode_o to 0x8 + 4'b1010: data =calib_data; + + + // Characterization Mode + // 2: Address as data + // 3: hammer data with option to select VICTIM line which output is always high. + // 7: Hammer PRBS. Only valid in V6,V7 family + // 9: Slow 2 MHz hammer pattern. + 4'b0111: data = full_prbs_data2;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs + 4'b1000: data = psuedo_prbs_data;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs + + default : begin + // for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) begin: neighbor_data + // data = begin + // for ( + data = adata; + end + endcase +end + +// phy calibration data pattern +// +generate +if (nCK_PER_CLK == 2) +begin: calib_data32 +always @ (posedge clk_i) +if (rst_i) begin + next_calib_data <= 1'b0; + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}}; + end +else if (cmd_startA) + begin + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}}; + next_calib_data <=#TCQ 1'b1; +// calib_data <= 'b0; + end + else if (fifo_rdy_i) + begin + next_calib_data <= #TCQ ~next_calib_data; + if (next_calib_data ) + + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h66}},{(NUM_DQ_PINS/8){8'h99}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h55}}}; + else + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}}; + end +end +else +begin: calib_data64 // when nCK_PER_LK =4 has not verified +always @ (posedge clk_i) + +if (rst_i) begin + next_calib_data <= 1'b0; + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}}; + end +else if (cmd_startA) + begin + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}}; + next_calib_data <=#TCQ 1'b1; +// calib_data <= 'b0; + end + else if (fifo_rdy_i) + begin + next_calib_data <= #TCQ ~next_calib_data; + if (next_calib_data ) + + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h6666}},{(NUM_DQ_PINS/8){16'h9999}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h5555}}}; + else + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}}; + end + + +end +endgenerate +/* + +always @ (posedge clk_i) +begin calib_data <= 'b0; + +end +*/ +//************************************************************************** +// Pattern bram generates fixed input, hammer, simple 8 repeat data pattern. +//************************************************************************** + +function integer logb2; + input [31:0] number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end +endfunction + + + +mig_7series_v4_2_vio_init_pattern_bram # +( .MEM_BURST_LEN (MEM_BURST_LEN), + .START_ADDR (START_ADDR), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE) + +) +vio_init_pattern_bram +( + .clk_i (clk_i ), + .rst_i (rst_i ), + // BL8 : least 3 address bits are always zero. + // BL4 " least 2 address bits are always zero. + // for walking 1's or 0's, the least 8 address bits are always zero. + .cmd_addr (addr_i), + .cmd_start (cmd_startB), + .mode_load_i (mode_load_i), + .data_mode_i (data_mode_rr_a), + //.w1data (w1data), + .data0 (simple_data0 ), + .data1 (simple_data1 ), + .data2 (simple_data2 ), + .data3 (simple_data3 ), + .data4 (simple_data4 ), + .data5 (simple_data5 ), + .data6 (simple_data6 ), + .data7 (simple_data7 ), + .data8 (fixed_data_i ), + + .bram_rd_valid_o (bram_rd_valid_o), + .bram_rd_rdy_i (user_burst_cnt_larger_bram & (data_rdy_i | cmd_startB)), + .dout_o (bram_data) + + ); + + + +//************************************************************** +// Functions to be used byg Walking 1 and Walking 0 circuits. +//************************************************************** + + +function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_Gen (input integer i ); + integer j; + begin + j = i/2; + Data_Gen = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b0}}; + if(i %2 == 1) begin + if (nCK_PER_CLK == 2) begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + end + else begin + + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + + end + end else begin + if (nCK_PER_CLK == 2) begin + if (MEM_TYPE == "QDR2PLUS") begin + //QDR sends the high order data bit out first to memory. + + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + end else begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + end + end + else begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + + end + + + + + + end + + + end +endfunction + + + +function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_GenW0 (input integer i); + integer j; + begin + j = i/2; + Data_GenW0 = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b1}}; + + if(i %2 == 1) begin + if (nCK_PER_CLK == 2) begin + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + + end + else begin + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + + Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + + end + end else begin + if (nCK_PER_CLK == 2) begin + + + if (MEM_TYPE == "QDR2PLUS") begin + //QDR sends the high order data bit out first to memory. + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + end else begin + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + end + + end + else begin + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + + end + end + + + end +endfunction + +always @ (posedge clk_i) begin + if (data_mode_rr_c[2:0] == 3'b101 || data_mode_rr_c[2:0] == 3'b100 || data_mode_rr_c[2:0] == 3'b110) // WALKING ONES + sel_w1gen_logic <= #TCQ 1'b1; + else + sel_w1gen_logic <= #TCQ 1'b0; +end + + + +generate +genvar m; + for (m=0; m < (2*nCK_PER_CLK*NUM_DQ_PINS/8) - 1; m= m+1) + begin: w1_gp + assign w1data_group[m] = ( (w1data[(m*8+7):m*8]) != 8'h00); + end +endgenerate + + + + generate + if ((NUM_DQ_PINS == 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) + begin : WALKING_ONE_8_PATTERN + if (nCK_PER_CLK == 2) begin : WALKING_ONE_8_PATTERN_NCK_2 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end // end of always + end // end of nCK_PER_CLK == 2 + else + begin: WALKING_ONE_8_PATTERN_NCK_4 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i ) begin + w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS ]; + w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS ]; + w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS ]; + w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS ]; + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS ]; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS ]; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS ]; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS ]; + end + end // end of always + end // end of nCK_PER_CLK == 4 + end + + else if ((NUM_DQ_PINS != 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) + begin : WALKING_ONE_64_PATTERN + if (nCK_PER_CLK == 2) begin : WALKING_ONE_64_PATTERN_NCK_2 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end // end of always + end //end of nCK_PER_CLK == 2 + else + begin: WALKING_ONE_64_PATTERN_NCK_4 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i) begin + w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ {w1data[8*NUM_DQ_PINS - 9:7*NUM_DQ_PINS ],w1data[8*NUM_DQ_PINS - 1:8*NUM_DQ_PINS - 8]}; + w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ {w1data[7*NUM_DQ_PINS - 9:6*NUM_DQ_PINS ],w1data[7*NUM_DQ_PINS - 1:7*NUM_DQ_PINS - 8]}; + w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ {w1data[6*NUM_DQ_PINS - 9:5*NUM_DQ_PINS ],w1data[6*NUM_DQ_PINS - 1:6*NUM_DQ_PINS - 8]}; + w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ {w1data[5*NUM_DQ_PINS - 9:4*NUM_DQ_PINS ],w1data[5*NUM_DQ_PINS - 1:5*NUM_DQ_PINS - 8]}; + + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 9:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 8]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 9:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 8]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 9:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 8]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 9:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 8]}; + end + end // end of always + end //end of nCK_PER_CLK == 4 + end + + else + begin: NO_WALKING_PATTERN + always @ (posedge clk_i) + w1data <= 'b0; + end + endgenerate + + +// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine +// the position of the pin driving oppsite polarity +// addr_i[6:2] = 5'h0f ; 32 bit data port +// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111 +// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 + +// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level. +always @ (posedge clk_i) +begin + for (i= 0; i <= 2*NUM_DQ_PINS - 1; i= i+1) //begin: hammer_data + + if ( i >= NUM_DQ_PINS ) + if (SEL_VICTIM_LINE == NUM_DQ_PINS) + hdata[i] <= 1'b0; + else if ( + ((i == SEL_VICTIM_LINE-1) || + (i-NUM_DQ_PINS) == SEL_VICTIM_LINE ))//|| + + hdata[i] <= 1'b1; + else + hdata[i] <= 1'b0; + + else + + hdata[i] <= 1'b1; + + +end +generate +if (nCK_PER_CLK == 2) +begin : HAMMER_2 + assign hammer_data = {2{hdata[2*NUM_DQ_PINS - 1:0]}}; +end +else +begin : HAMMER_4 + assign hammer_data = {4{hdata[2*NUM_DQ_PINS - 1:0]}}; +end +endgenerate + + +// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 32'h12345678, burst length 8 +// => the 1st data pattern : 32'h12345680 +// => the 2nd data pattern : 32'h12345688 +// => the 3rd data pattern : 32'h12345690 +// => the 4th data pattern : 32'h12345698 +generate + +reg COut_a; +if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL") +begin : ADDRESS_PATTERN + always @ (posedge clk_i) + begin + if (cmd_startD) + /// 35:0 + acounts <= #TCQ {4'b0000,addr_i} ; + else if (user_burst_cnt_larger_1_r && data_rdy_i ) begin + if (nCK_PER_CLK == 2) + if (FAMILY == "VIRTEX6") + if (MEM_TYPE == "QDR2PLUS") + {COut_a,acounts} <= #TCQ acounts + 1; + else + {COut_a,acounts} <= #TCQ acounts + 4; + + else begin // "SPARTAN6" + if (DWIDTH == 32) + {COut_a,acounts} <= #TCQ acounts + 4; + else if (DWIDTH == 64) + {COut_a,acounts} <= #TCQ acounts + 8; + else if (DWIDTH == 64) + {COut_a,acounts} <= #TCQ acounts + 16; + end + else + {COut_a,acounts} <= #TCQ acounts + 8; + end + else + acounts <= #TCQ acounts; + + end + + assign adata_tmp = {USER_BUS_DWIDTH/32{acounts[31:0]}}; + + end +else +begin: NO_ADDRESS_PATTERN + assign adata_tmp = 'b0; +end +endgenerate + + always @ (posedge clk_i) + begin + if (cmd_startD) + tg_st_addr_o <= addr_i; + end + +// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4 +// + +// this user_burst_cnt_larger_bram is used by vio_init_pattern_bram module +// only +always @ (posedge clk_i) + if (user_burst_cnt > 6'd1 || cmd_startE) + user_burst_cnt_larger_bram <= 1'b1; + else + user_burst_cnt_larger_bram <= 1'b0; + + +generate +if (DMODE == "WRITE") +begin: wr_ubr + always @ (posedge clk_i) + if (user_burst_cnt > 6'd1 || cmd_startE) + user_burst_cnt_larger_1_r <= 1'b1; + else + user_burst_cnt_larger_1_r <= 1'b0; +end +else +begin: rd_ubr + + always @ (posedge clk_i) + if (user_burst_cnt >= 6'd1 || cmd_startE) + user_burst_cnt_larger_1_r <= 1'b1; + else if (ReSeedcounter[31:0] == 255) + user_burst_cnt_larger_1_r <= 1'b0; +end +endgenerate + + +generate +// When doing eye_test, traffic gen only does write and want to +// keep the prbs random and address is fixed at a location. +if (EYE_TEST == "TRUE") +begin : d_clk_en1 +always @(data_clk_en) + data_clk_en = 1'b1;//fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1; +end +else if (DMODE == "WRITE") + begin: wr_dataclken + always @ (data_rdy_i , user_burst_cnt_larger_1_r,ReSeedcounter[31:0]) + +begin + + if ( data_rdy_i && (user_burst_cnt_larger_1_r || ReSeedcounter[31:0] == 255 )) + data_clk_en = 1'b1; +else + data_clk_en = 1'b0; +end + +always @ (data_rdy_i , user_burst_cnt_larger_1_r,ReSeedcounter) +begin + + if ( data_rdy_i && (user_burst_cnt_larger_1_r || ReSeedcounter[31:0] == 255 )) + data_clk_en2 = 1'b1; + else + data_clk_en2 = 1'b0; + end + end else // (DMODE == "READ") + begin: rd_dataclken + always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r) + begin + if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r ) + data_clk_en <= 1'b1; + else + data_clk_en <= 1'b0; + end + always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r) + begin + if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r ) + data_clk_en2 <= 1'b1; +else + data_clk_en2 <= 1'b0; +end + +end +endgenerate + +generate +if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL") +begin : PSUEDO_PRBS_PATTERN + +// PRBS DATA GENERATION +// xor all the tap positions before feedback to 1st stage. + always @ (posedge clk_i) + m_addr_r <= m_addr_i; + + + mig_7series_v4_2_data_prbs_gen # + ( + .PRBS_WIDTH (32), + .SEED_WIDTH (32), + .EYE_TEST (EYE_TEST) + ) + data_prbs_gen + ( + .clk_i (clk_i), + .rst_i (rst_i), + .clk_en (data_clk_en), + + .prbs_seed_init (cmd_startE), + .prbs_seed_i (m_addr_i[31:0]), + .prbs_o (mcb_prbs_data) + + ); +end +else +begin:NO_PSUEDO_PRBS_PATTERN + assign mcb_prbs_data = 'b0; +end +endgenerate + + //*************************************************************************** + // "Full pseudo-PRBS" data generation + //*************************************************************************** + + genvar r; + + // Assign initial seed (used for 1st data bit); use alternating 1/0 pat + assign prbs_seed[0] = {(PRBS_WIDTH/2){2'b10}}; + + // Generate seeds for all other data bits, each one is staggered in time + // by one LFSR shift from the preceeding bit + + + + + + + + + + + generate + if (PRBS_WIDTH == 8) begin: gen_seed_prbs8 + for (r = 1; r < NUM_DQ_PINS; r = r + 1) begin: gen_loop_seed_prbs + // PRBS 8 - feedback uses taps [7,5,4,3] + assign prbs_seed[r] = {prbs_seed[r-1][PRBS_WIDTH-2:0], + ~(prbs_seed[r-1][7] ^ prbs_seed[r-1][5] ^ + prbs_seed[r-1][4] ^ prbs_seed[r-1][3])}; + end + end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10 + // PRBS 10 - feedback uses taps [9,6] + for (r = 1; r < NUM_DQ_PINS; r = r + 1) begin: gen_loop_seed_prbs + assign prbs_seed[r] = {prbs_seed[r-1][PRBS_WIDTH-2:0], + ~(prbs_seed[r-1][9] ^ prbs_seed[r-1][6])}; + end + end + endgenerate + + // Instantiate one PRBS per data bit. Note this is only temporary - + // eventually it will be far more efficient to use a large shift register + // that is initialized with 2*CK_PER_CLK*NUM_DQ_PINS worth of LFSR cycles + // rather than individual PRBS generators. For now this is done because + // not sure if current logic allows for the initial delay required to fill + // this large shift register + generate + for (r = 0; r < NUM_DQ_PINS; r = r + 1) begin: gen_prbs_modules + mig_7series_v4_2_tg_prbs_gen # + (.nCK_PER_CLK (nCK_PER_CLK), + .TCQ (TCQ), + .PRBS_WIDTH (PRBS_WIDTH) + ) + u_data_prbs_gen + ( + .clk_i (clk_i), + .rst_i (rst_i), + .clk_en_i (data_clk_en), + .prbs_seed_i (prbs_seed[r]), + .prbs_o (prbs_out[r]), + .ReSeedcounter_o (ReSeedcounter[32*r+:32]) + ); + end + endgenerate + + generate + for (r = 0; r < NUM_DQ_PINS; r = r + 1) begin: gen_prbs_rise_fall_data + if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 + assign prbsdata_rising_0[r] = prbs_out[r][0]; + assign prbsdata_falling_0[r] = prbs_out[r][1]; + assign prbsdata_rising_1[r] = prbs_out[r][2]; + assign prbsdata_falling_1[r] = prbs_out[r][3]; + end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign prbsdata_rising_0[r] = prbs_out[r][0]; + assign prbsdata_falling_0[r] = prbs_out[r][1]; + assign prbsdata_rising_1[r] = prbs_out[r][2]; + assign prbsdata_falling_1[r] = prbs_out[r][3]; + assign prbsdata_rising_2[r] = prbs_out[r][4]; + assign prbsdata_falling_2[r] = prbs_out[r][5]; + assign prbsdata_rising_3[r] = prbs_out[r][6]; + assign prbsdata_falling_3[r] = prbs_out[r][7]; + end + end + endgenerate + + //*************************************************************************** + +//***debug PRBS in ddr3 hware +//assign dbg_prbs_tpts[15:0] = {prbs_shift_value3 ,prbs_shift_value2,prbs_shift_value1,prbs_shift_value0}; +//assign dbg_prbs_tpts[21:16] = prbs_mux_counter[5:0]; +//assign dbg_prbs_tpts[22] = data_clk_en2; +//assign dbg_prbs_tpts[23] = mode_load_r1 ; +//assign dbg_prbs_tpts[24] = mode_has_loaded; +//fifo_rdy_i && data_rdy_i +//assign dbg_prbs_tpts[25] = data_rdy_i; +//assign dbg_prbs_tpts[26] = fifo_rdy_i; + +//assign dbg_prbs_tpts[31:27] = 'b0; + +//assign dbg_prbs_tpts[63:32] = ReSeedcounter[31:0]; +//assign dbg_prbs_tpts[64+:10] = user_burst_cnt[9:0]; +//assign dbg_prbs_tpts[74] = user_burst_cnt_larger_1_r; + +//assign dbg_prbs_tpts[127:75] = 'b0; + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v new file mode 100644 index 0000000..a4cf47e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v @@ -0,0 +1,246 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: tb_cmd_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: PRBS_Generator +//Purpose: +// Overview: +// Implements a "pseudo-PRBS" generator. Basically this is a standard +// PRBS generator (using an linear feedback shift register) along with +// logic to force the repetition of the sequence after 2^PRBS_WIDTH +// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design +// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains +// are supported in this code +// Parameter Requirements: +// 1. PRBS_WIDTH = 8 or 10 +// 2. PRBS_WIDTH >= 2*nCK_PER_CLK +// Output notes: +// The output of this module consists of 2*nCK_PER_CLK bits, these contain +// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note +// that prbs_o[0] contains the bit value for the "earliest" bit time. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_tg_prbs_gen # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter PRBS_WIDTH = 10, // LFSR shift register length + parameter nCK_PER_CLK = 4 // output:internal clock freq ratio + ) + ( + input clk_i, // input clock + input clk_en_i, // clock enable + input rst_i, // synchronous reset + input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed + output [2*nCK_PER_CLK-1:0] prbs_o, // generated address + // ReSeedcounter used to indicate when pseudo-PRBS sequence has reached + // the end of it's cycle. May not be needed, but for now included to + // maintain compatibility with current TG code + output [31:0] ReSeedcounter_o + ); + + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + + // Number of internal clock cycles before the PRBS sequence will repeat + localparam PRBS_SEQ_LEN_CYCLES = (2**PRBS_WIDTH) / (2*nCK_PER_CLK); + localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES); + + reg [PRBS_WIDTH-1:0] lfsr_reg_r; + wire [PRBS_WIDTH-1:0] next_lfsr_reg; + reg [PRBS_WIDTH-1:0] reseed_cnt_r; + reg reseed_prbs_r; + reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r; + + genvar i; + + //*************************************************************************** + + assign ReSeedcounter_o = {{(32-PRBS_WIDTH){1'b0}}, reseed_cnt_r}; + always @ (posedge clk_i) + if (rst_i) + reseed_cnt_r <= 'b0; + else if (clk_en_i) + if (reseed_cnt_r == {PRBS_WIDTH {1'b1}}) + reseed_cnt_r <= 'b0; + else + reseed_cnt_r <= reseed_cnt_r + 1; + + //*************************************************************************** + + // Generate PRBS reset signal to ensure that PRBS sequence repeats after + // every 2**PRBS_WIDTH samples. Basically what happens is that we let the + // LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1 + // samples have past. Once that extra cycle is finished, we reseed the LFSR + always @(posedge clk_i) + if (rst_i) begin + sample_cnt_r <= #TCQ 'b0; + reseed_prbs_r <= #TCQ 1'b0; + end else if (clk_en_i) begin + // The rollver count should always be [(power of 2) - 1] + sample_cnt_r <= #TCQ sample_cnt_r + 1; + // Assert PRBS reset signal so that it is simultaneously with the + // last sample of the sequence + if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2) + reseed_prbs_r <= #TCQ 1'b1; + else + reseed_prbs_r <= #TCQ 1'b0; + end + + // Load initial seed or update LFSR contents + always @(posedge clk_i) + if (rst_i) + lfsr_reg_r <= #TCQ prbs_seed_i; + else if (clk_en_i) + if (reseed_prbs_r) + lfsr_reg_r <= #TCQ prbs_seed_i; + else begin + lfsr_reg_r <= #TCQ next_lfsr_reg; + end + + // Calculate next set of nCK_PER_CLK samplse for LFSR + // Basically we calculate all PRBS_WIDTH samples in parallel, rather + // than serially shifting the LFSR to determine future sample values. + // Shifting is possible, but requires multiple shift registers to be + // instantiated because the fabric clock frequency is running at a + // fraction of the output clock frequency + generate + if (PRBS_WIDTH == 8) begin: gen_next_lfsr_prbs8 + if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 + assign next_lfsr_reg[7] = lfsr_reg_r[3]; + assign next_lfsr_reg[6] = lfsr_reg_r[2]; + assign next_lfsr_reg[5] = lfsr_reg_r[1]; + assign next_lfsr_reg[4] = lfsr_reg_r[0]; + assign next_lfsr_reg[3] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^ + lfsr_reg_r[4] ^ lfsr_reg_r[3]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^ + lfsr_reg_r[3] ^ lfsr_reg_r[2]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^ + lfsr_reg_r[2] ^ lfsr_reg_r[1]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^ + lfsr_reg_r[1] ^ lfsr_reg_r[0]); + end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign next_lfsr_reg[7] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^ + lfsr_reg_r[4] ^ lfsr_reg_r[3]); + assign next_lfsr_reg[6] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^ + lfsr_reg_r[3] ^ lfsr_reg_r[2]) ; + assign next_lfsr_reg[5] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^ + lfsr_reg_r[2] ^ lfsr_reg_r[1]); + assign next_lfsr_reg[4] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^ + lfsr_reg_r[1] ^ lfsr_reg_r[0]); + assign next_lfsr_reg[3] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[1] ^ + lfsr_reg_r[0] ^ next_lfsr_reg[7]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[2] ^ lfsr_reg_r[0] ^ + next_lfsr_reg[7] ^ next_lfsr_reg[6]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[1] ^ next_lfsr_reg[7] ^ + next_lfsr_reg[6] ^ next_lfsr_reg[5]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[0] ^ next_lfsr_reg[6] ^ + next_lfsr_reg[5] ^ next_lfsr_reg[4]); + end + end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10 + if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 + assign next_lfsr_reg[9] = lfsr_reg_r[5]; + assign next_lfsr_reg[8] = lfsr_reg_r[4]; + assign next_lfsr_reg[7] = lfsr_reg_r[3]; + assign next_lfsr_reg[6] = lfsr_reg_r[2]; + assign next_lfsr_reg[5] = lfsr_reg_r[1]; + assign next_lfsr_reg[4] = lfsr_reg_r[0]; + assign next_lfsr_reg[3] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]); + end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign next_lfsr_reg[9] = lfsr_reg_r[1]; + assign next_lfsr_reg[8] = lfsr_reg_r[0]; + assign next_lfsr_reg[7] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]); + assign next_lfsr_reg[6] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]); + assign next_lfsr_reg[5] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]); + assign next_lfsr_reg[4] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]); + assign next_lfsr_reg[3] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[2]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[1]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[0]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[2] ^ next_lfsr_reg[7]); + end + end + endgenerate + + // Output highest (2*nCK_PER_CLK) taps of LFSR - note that the "earliest" + // tap is highest tap (e.g. for an 8-bit LFSR, tap[7] contains the first + // data sent out the shift register), therefore tap[PRBS_WIDTH-1] must be + // routed to bit[0] of the output, tap[PRBS_WIDTH-2] to bit[1] of the + // output, etc. + generate + for (i = 0; i < 2*nCK_PER_CLK; i = i + 1) begin: gen_prbs_transpose + assign prbs_o[i] = lfsr_reg_r[PRBS_WIDTH-1-i]; + end + endgenerate + + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_status.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_status.v new file mode 100644 index 0000000..8ef66fd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_tg_status.v @@ -0,0 +1,127 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: tg_status.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. +// Error signal will be asserted if the comparsion is not equal. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + + +module mig_7series_v4_2_tg_status #( + parameter TCQ = 100, + + parameter DWIDTH = 32 + ) + ( + + + input clk_i , + input rst_i , + input manual_clear_error, + input data_error_i , + input [DWIDTH-1:0] cmp_data_i, + input [DWIDTH-1:0] rd_data_i , + input [31:0] cmp_addr_i , + input [5:0] cmp_bl_i , + input mcb_cmd_full_i , + input mcb_wr_full_i, + input mcb_rd_empty_i, + output reg [64 + (2*DWIDTH - 1):0] error_status, + output error + ); + +reg data_error_r; +reg error_set; +assign error = error_set; + +always @ (posedge clk_i) + data_error_r <= #TCQ data_error_i; + +always @ (posedge clk_i) +begin + +if (rst_i || manual_clear_error) begin + error_status <= #TCQ 'b0; + error_set <= #TCQ 1'b0; +end +else begin + // latch the first error only + if (data_error_i && ~data_error_r && ~error_set ) begin + error_status[31:0] <= #TCQ cmp_addr_i; + error_status[37:32] <= #TCQ cmp_bl_i; + error_status[40] <= #TCQ mcb_cmd_full_i; + error_status[41] <= #TCQ mcb_wr_full_i; + error_status[42] <= #TCQ mcb_rd_empty_i; + error_set <= #TCQ 1'b1; + error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; + error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; + + end + + error_status[39:38] <= #TCQ 'b0; // reserved + error_status[63:43] <= #TCQ 'b0; // reserved + + +end end + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v new file mode 100644 index 0000000..8ee36e9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v @@ -0,0 +1,627 @@ +//***************************************************************************** +// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Application : MIG +// \ \ Filename : traffic_gen_top.v +// / / Date Last Modified : $Date: 2011/06/02 08:37:25 $ +// /___/ /\ Date Created : Fri Mar 26 2010 +// \ \ / \ +// \___\/\___\ +// +//Device : Virtex-7 +//Design Name : DDR/DDR2/DDR3/LPDDR +//Purpose : This Traffic Gen supports both nCK_PER_CLK x4 mode and nCK_PER_CLK x2 mode for +// 7series MC UI Interface. The user bus datawidth has a equation: 2*nCK_PER_CLK*DQ_WIDTH. +// +//Reference : +//Revision History : 11/17/2011 Adding CMD_GAP_DELAY to allow control of next command generation after current +// completion of burst command in user interface port. +// 1/4/2012 Added vio_percent_write in memc_traffic_gen module to let user specify percentage +// of write commands out of mix write/read commands. User can +// modify this file and bring the signals to top level to use it. +// The value is between 1(10 percent) through 10 (100 percent). +// The signal value is only used if vio_instr_mode_value == 4. +// 5/21/2012 Removed BL_WIDTH parameter and forced internally to 10. +// +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_traffic_gen_top #( + parameter TCQ = 100, // SIMULATION tCQ delay. + + parameter SIMULATION = "FALSE", + parameter FAMILY = "VIRTEX7", // "VIRTEX6", "VIRTEX7" + parameter MEM_TYPE = "DDR3", + + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands: + // "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE" + // "R_W_INSTR_MODE", "RP_WP_INSTR_MODE + // "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE" + // ******************************* + // Virtex 6 Available commands: + // "R_W_INSTR_MODE" + // "FIXED_INSTR_R_MODE" - Only Read commands will be generated. + // "FIXED_INSTR_W_MODE" -- Only Write commands will be generated. + // "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated + // with lower 10 bits address in sequential increment. + // This mode is for Read Eye measurement. + + // parameter BL_WIDTH = 10, // Define User Interface Burst length width. + // // For a maximum 128 continuous back_to_back command, set this to 8. + parameter nCK_PER_CLK = 4, // Memory Clock ratio to fabric clock. + parameter NUM_DQ_PINS = 8, // Total number of memory dq pins in the design. + parameter MEM_BURST_LEN = 8, // MEMROY Burst Length + parameter MEM_COL_WIDTH = 10, // Memory component column width. + parameter DATA_WIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, // User Interface Data Width + parameter ADDR_WIDTH = 29, // Command Address Bus width + parameter MASK_SIZE = DATA_WIDTH/8, // + parameter DATA_MODE = 4'b0010, // Default Data mode is set to Address as Data pattern. + + // parameters define the address range + parameter BEGIN_ADDRESS = 32'h00000100, + parameter END_ADDRESS = 32'h000002ff, + parameter PRBS_EADDR_MASK_POS = 32'hfffffc00, + // debug parameters + parameter CMDS_GAP_DELAY = 6'd0, // CMDS_GAP_DELAY is used in memc_flow_vcontrol module to insert delay between + // each sucessive burst commands. The maximum delay is 32 clock cycles + // after the last command. + parameter SEL_VICTIM_LINE = NUM_DQ_PINS, // VICTIM LINE is one of the DQ pins is selected to be always asserted when + // DATA MODE is hammer pattern. No VICTIM_LINE will be selected if + // SEL_VICTIM_LINE = NUM_DQ_PINS. + parameter CMD_WDT = 'h3FF, + parameter WR_WDT = 'h1FFF, + parameter RD_WDT = 'hFF, + + parameter EYE_TEST = "FALSE", + // S6 Only parameters + parameter PORT_MODE = "BI_MODE", + parameter DATA_PATTERN = "DGEN_ALL", // Default is to generate all data pattern circuits. + parameter CMD_PATTERN = "CGEN_ALL" // Default is to generate all commands pattern circuits. + + ) + ( + input clk, + input rst, + input tg_only_rst, + input manual_clear_error, + input memc_init_done, + + input memc_cmd_full, + output memc_cmd_en, + output [2:0] memc_cmd_instr, + output [5:0] memc_cmd_bl, + output [31:0] memc_cmd_addr, + + output memc_wr_en, + output memc_wr_end, + + output [DATA_WIDTH/8 - 1:0] memc_wr_mask, + output [DATA_WIDTH - 1:0] memc_wr_data, + input memc_wr_full, + + output memc_rd_en, + input [DATA_WIDTH - 1:0] memc_rd_data, + input memc_rd_empty, + + // interface to qdr interface + output qdr_wr_cmd_o, + output qdr_rd_cmd_o, + + + // Signal declarations that can be connected to vio module + input vio_pause_traffic, // Pause traffic on the fly. + input vio_modify_enable, + input [3:0] vio_data_mode_value, + input [2:0] vio_addr_mode_value, + input [3:0] vio_instr_mode_value, + input [1:0] vio_bl_mode_value, + input [9:0] vio_fixed_bl_value, + input [2:0] vio_fixed_instr_value, // Allows upper level control write only or read only + // on the fly. + // Set the vio_instr_mode_value to "0001" . + // User has control of the type of commands to be generated + // after memory has been filled with selected data pattern. + // vio_fixed_instr_value = 3'b000: Write command + // vio_fixed_instr_value = 3'b001: Read command + input vio_data_mask_gen, // data_mask generation is only supported + // when data mode = address as data . + // + input [31:0] fixed_addr_i, + + // User Specific data pattern interface that used when vio_data_mode vale = 1.4.9. + input [31:0] fixed_data_i, + input [31:0] simple_data0, + input [31:0] simple_data1, + input [31:0] simple_data2, + input [31:0] simple_data3, + input [31:0] simple_data4, + input [31:0] simple_data5, + input [31:0] simple_data6, + input [31:0] simple_data7, + input wdt_en_i, + + // BRAM interface. + // bram bus formats: + // Only SP6 has been tested. + input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}} + input bram_valid_i, + output bram_rdy_o, // + + + // status feedback + output [DATA_WIDTH-1:0] cmp_data, + output cmp_data_valid, + output cmp_error, + output [47:0] wr_data_counts, + output [47:0] rd_data_counts, + output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, + output error, // asserted whenever the read back data is not correct. + output [64 + (2*DATA_WIDTH - 1):0] error_status, + output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error, + output reg cmd_wdt_err_o, + output reg wr_wdt_err_o, + output reg rd_wdt_err_o, + + output mem_pattern_init_done + + ); + + + + +//p0 wire declarations + wire tg_run_traffic; + wire tg_data_mask_gen; + wire run_traffic; + wire [31:0] tg_start_addr; + wire [31:0] tg_end_addr; + wire [31:0] tg_cmd_seed; + wire [31:0] tg_data_seed; + wire tg_load_seed; + wire [2:0] tg_addr_mode; + wire [3:0] tg_instr_mode; + wire [1:0] tg_bl_mode; + wire [3:0] tg_data_mode; + wire tg_mode_load; + wire [9:0] tg_fixed_bl; + wire [2:0] tg_fixed_instr; + wire tg_addr_order; + wire [5:0] cmds_gap_delay_value; + wire tg_memc_wr_en; + wire [63:0] mem_tg_tstpoints; + wire [9:0] lcl_v_fixed_bl_value; + + wire single_operation; + wire [3:0] tg_instr_mode_value; + wire [3:0] instr_mode_value; + reg tg_rst; + localparam ADDR_WIDTH_MASK = {{31-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH-1{1'b1}}}; + localparam ADDR_WIDTH_MASK_1 = {{30-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH{1'b1}}}; + localparam BEGIN_ADDRESS_MASK = ADDR_WIDTH_MASK & BEGIN_ADDRESS; + localparam END_ADDRESS_MASK = ADDR_WIDTH_MASK_1 & END_ADDRESS; + + localparam SHIFT_COUNT = (31-ADDR_WIDTH) ; + localparam BEGIN_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (BEGIN_ADDRESS >> SHIFT_COUNT) : BEGIN_ADDRESS_MASK ; + localparam END_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (END_ADDRESS >> SHIFT_COUNT) : END_ADDRESS_MASK ; + localparam TG_INIT_DATA_MODE = (DATA_PATTERN == "DGEN_ADDR") ? 4'b0010 : + (DATA_PATTERN == "DGEN_HAMMER") ? 4'b0011 : + (DATA_PATTERN == "DGEN_WALKING1") ? 4'b0101 : + (DATA_PATTERN == "DGEN_WALKING0") ? 4'b0110 : + (DATA_PATTERN == "DGEN_PRBS") ? 4'b0111 : + DATA_MODE ; + +assign single_operation = 1'b0; // Disable this for 13.3 release + + +// cmds_gap_delay_value is used in memc_flow_vcontrol module to insert delay between +// each sucessive burst commands. The maximum delay is 32 clock cycles after the last command. + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + + localparam CMD_WDT_WIDTH = clogb2(CMD_WDT); + localparam RD_WDT_WIDTH = clogb2(RD_WDT); + localparam WR_WDT_WIDTH = clogb2(WR_WDT); + +assign cmds_gap_delay_value = CMDS_GAP_DELAY; + +localparam TG_FAMILY = ((FAMILY == "VIRTEX6") || (FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") + || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ) ? "VIRTEX6" : "SPARTAN6"; + +assign tg_memc_wr_en = (TG_FAMILY == "VIRTEX6") ?memc_cmd_en & ~memc_cmd_full : memc_wr_en ; +assign lcl_v_fixed_bl_value = (vio_data_mode_value == 4) ? 32:vio_fixed_bl_value; +assign tg_run_traffic = (run_traffic & ((vio_modify_enable == 1'b1) ? ~vio_pause_traffic : 1'b1)) ; +assign tg_data_mask_gen = (vio_modify_enable == 1'b1) ? vio_data_mask_gen : 1'b0 ; +assign instr_mode_value = (vio_modify_enable == 1'b1) ? vio_instr_mode_value : 4'b0010; +assign tg_instr_mode_value = (single_operation == 1'b1) ? 4'b0111: instr_mode_value; + +reg [CMD_WDT_WIDTH-1 : 0] cmd_wdt; +reg [RD_WDT_WIDTH-1 : 0] rd_wdt; +reg [WR_WDT_WIDTH-1 : 0] wr_wdt; + +// The following 'generate' statement activates the traffic generator for + // init_mem_pattern_ctr module instantiation for Port-0 + mig_7series_v4_2_init_mem_pattern_ctr # + ( + .TCQ (TCQ), + .DWIDTH (DATA_WIDTH), + + .TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE), + .nCK_PER_CLK (nCK_PER_CLK), + .MEM_BURST_LEN (MEM_BURST_LEN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .MEM_TYPE (MEM_TYPE), + + .FAMILY (TG_FAMILY), + .BL_WIDTH (10), + .ADDR_WIDTH (ADDR_WIDTH), + .BEGIN_ADDRESS (BEGIN_ADDRESS_INT), + .END_ADDRESS (END_ADDRESS_INT), + .CMD_SEED_VALUE (32'h56456783), + .DATA_SEED_VALUE (32'h12345678), + .DATA_MODE (TG_INIT_DATA_MODE), + .PORT_MODE (PORT_MODE) + ) + u_init_mem_pattern_ctr + ( + .clk_i (clk), + .rst_i (tg_rst), + .memc_cmd_en_i (memc_cmd_en), + .memc_wr_en_i (tg_memc_wr_en), + .single_write_button (1'b0), // tie off these group of signals for 13.3 + .single_read_button (1'b0), + .slow_write_read_button (1'b0), + .single_operation (1'b0), + .vio_modify_enable (vio_modify_enable), + .vio_instr_mode_value (tg_instr_mode_value), + .vio_data_mode_value (vio_data_mode_value), + .vio_addr_mode_value (vio_addr_mode_value), + .vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode + .vio_fixed_bl_value (lcl_v_fixed_bl_value), // always set to 64 in order to run PRBS data pattern + .vio_data_mask_gen (vio_data_mask_gen), + .vio_fixed_instr_value (vio_fixed_instr_value), + .memc_init_done_i (memc_init_done), + .cmp_error (error), + .run_traffic_o (run_traffic), + .start_addr_o (tg_start_addr), + .end_addr_o (tg_end_addr), + .cmd_seed_o (tg_cmd_seed), + .data_seed_o (tg_data_seed), + .load_seed_o (tg_load_seed), + .addr_mode_o (tg_addr_mode), + .instr_mode_o (tg_instr_mode), + .bl_mode_o (tg_bl_mode), + .data_mode_o (tg_data_mode), + .mode_load_o (tg_mode_load), + .fixed_bl_o (tg_fixed_bl), + .fixed_instr_o (tg_fixed_instr), + .mem_pattern_init_done_o (mem_pattern_init_done) + ); + + // traffic generator instantiation for Port-0 + mig_7series_v4_2_memc_traffic_gen # + ( + .TCQ (TCQ), + .MEM_BURST_LEN (MEM_BURST_LEN), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .nCK_PER_CLK (nCK_PER_CLK), + + .PORT_MODE (PORT_MODE), + .DWIDTH (DATA_WIDTH), + .FAMILY (TG_FAMILY), + .MEM_TYPE (MEM_TYPE), + .SIMULATION (SIMULATION), + .DATA_PATTERN (DATA_PATTERN), + .CMD_PATTERN (CMD_PATTERN ), + .ADDR_WIDTH (ADDR_WIDTH), + .BL_WIDTH (10), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .PRBS_SADDR_MASK_POS (BEGIN_ADDRESS_INT), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), + .PRBS_SADDR (BEGIN_ADDRESS_INT), + .PRBS_EADDR (END_ADDRESS_INT), + .EYE_TEST (EYE_TEST) + ) + u_memc_traffic_gen + ( + .clk_i (clk), + .rst_i (tg_rst), + .run_traffic_i (tg_run_traffic), + .manual_clear_error (manual_clear_error), + .cmds_gap_delay_value (cmds_gap_delay_value), + .vio_instr_mode_value (tg_instr_mode_value), + .vio_percent_write ('b0), // bring this to top if want to specify percentage of write commands + // instr_mode_i has to be == 4 if want to use this command pattern + // runtime parameter + .mem_pattern_init_done_i (mem_pattern_init_done), + .single_operation (1'b0), + + .start_addr_i (tg_start_addr), + .end_addr_i (tg_end_addr), + .cmd_seed_i (tg_cmd_seed), + .data_seed_i (tg_data_seed), + .load_seed_i (tg_load_seed), + .addr_mode_i (tg_addr_mode), + .instr_mode_i (tg_instr_mode), + .bl_mode_i (tg_bl_mode), + .data_mode_i (tg_data_mode), + .mode_load_i (tg_mode_load), + .wr_data_mask_gen_i (tg_data_mask_gen), + // fixed pattern inputs interface + .fixed_bl_i (tg_fixed_bl), + .fixed_instr_i (tg_fixed_instr), + .fixed_addr_i (fixed_addr_i), + .fixed_data_i (fixed_data_i), + // BRAM interface. + .bram_cmd_i (bram_cmd_i), + // .bram_addr_i (bram_addr_i ), + // .bram_instr_i ( bram_instr_i), + .bram_valid_i (bram_valid_i), + .bram_rdy_o (bram_rdy_o), + + // MCB INTERFACE + .memc_cmd_en_o (memc_cmd_en), + .memc_cmd_instr_o (memc_cmd_instr), + .memc_cmd_bl_o (memc_cmd_bl), + .memc_cmd_addr_o (memc_cmd_addr), + .memc_cmd_full_i (memc_cmd_full), + + .memc_wr_en_o (memc_wr_en), + .memc_wr_data_end_o (memc_wr_end), + .memc_wr_mask_o (memc_wr_mask), + .memc_wr_data_o (memc_wr_data), + .memc_wr_full_i (memc_wr_full), + + .memc_rd_en_o (memc_rd_en), + .memc_rd_data_i (memc_rd_data), + .memc_rd_empty_i (memc_rd_empty), + + .qdr_wr_cmd_o (qdr_wr_cmd_o), + .qdr_rd_cmd_o (qdr_rd_cmd_o), + // status feedback + .counts_rst (tg_rst), + .wr_data_counts (wr_data_counts), + .rd_data_counts (rd_data_counts), + .error (error), // asserted whenever the read back data is not correct. + .error_status (error_status), // TBD how signals mapped + .cmp_data (cmp_data), + .cmp_data_valid (cmp_data_valid), + .cmp_error (cmp_error), + .mem_rd_data (), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .dq_error_bytelane_cmp (dq_error_bytelane_cmp), + .cumlative_dq_lane_error (cumlative_dq_lane_error), + .cumlative_dq_r0_bit_error (), + .cumlative_dq_f0_bit_error (), + .cumlative_dq_r1_bit_error (), + .cumlative_dq_f1_bit_error (), + .dq_r0_bit_error_r (), + .dq_f0_bit_error_r (), + .dq_r1_bit_error_r (), + .dq_f1_bit_error_r (), + .dq_r0_read_bit (), + .dq_f0_read_bit (), + .dq_r1_read_bit (), + .dq_f1_read_bit (), + .dq_r0_expect_bit (), + .dq_f0_expect_bit (), + .dq_r1_expect_bit (), + .dq_f1_expect_bit (), + .error_addr () + ); + + reg [8:0] wr_cmd_cnt; + reg [8:0] dat_cmd_cnt; + reg rst_remem; + reg [2:0] app_cmd1; + reg [2:0] app_cmd2; + reg [2:0] app_cmd3; + reg [2:0] app_cmd4; + + reg [8:0] rst_cntr; + + always @(posedge clk) begin + if (rst) begin + rst_remem <= 1'b0; + end else if (tg_only_rst) begin + rst_remem <= 1'b1; + end else if (rst_cntr == 9'h0) begin + rst_remem <= 1'b0; + end + end + + + always @(posedge clk) begin + if (rst) begin + tg_rst <= 1'b1; + end else begin + tg_rst <= (rst_cntr != 9'h1ff); + end + end + + always @ (posedge clk) + begin + if (rst) + rst_cntr <= 9'h1ff; + else if (rst_remem & (wr_cmd_cnt==dat_cmd_cnt) & (app_cmd3==3'h1) & (app_cmd4==3'h0)) + rst_cntr <= 9'h0; + else if (rst_cntr != 9'h1ff) + rst_cntr <= rst_cntr + 1'b1; + end + + always @(posedge clk) begin + if (rst | tg_rst) begin + wr_cmd_cnt <= 1'b0; + end else if (memc_cmd_en & (!memc_cmd_full)& (memc_cmd_instr == 3'h0)) begin + wr_cmd_cnt <= wr_cmd_cnt + 1'b1; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + dat_cmd_cnt <= 1'b0; + end else if (memc_wr_en & (!memc_wr_full)) begin + dat_cmd_cnt <= dat_cmd_cnt + 1'b1; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + app_cmd1 <= 'b0; + app_cmd2 <= 'b0; + app_cmd3 <= 'b0; + app_cmd4 <= 'b0; + end else if (memc_cmd_en & (!memc_cmd_full)) begin + app_cmd1 <= memc_cmd_instr; + app_cmd2 <= app_cmd1; + app_cmd3 <= app_cmd2; + app_cmd4 <= app_cmd3; + end + end + always @(posedge clk) begin + if (rst| tg_rst) begin + cmd_wdt <= 1'b0; + end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (memc_cmd_full | (!memc_cmd_en)) & wdt_en_i) begin + // init_calib_done !app_rdy app_en + cmd_wdt <= cmd_wdt + 1'b1; +// end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (!memc_cmd_full) & memc_cmd_en & wdt_en_w) begin + end else if ((!memc_cmd_full) & memc_cmd_en) begin + // init_calib_done !app_rdy app_en + cmd_wdt <= 'b0; + end + end + + + always @(posedge clk) begin + if (rst| tg_rst) begin + rd_wdt <= 1'b0; + end else if (mem_pattern_init_done & (rd_wdt != RD_WDT) & (memc_rd_empty) & wdt_en_i) begin + // !app_rd_data_valid + rd_wdt <= rd_wdt + 1'b1; + end else if (!memc_rd_empty) begin + // !app_rd_data_valid + rd_wdt <= 'b0; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + wr_wdt <= 1'b0; + end else if (mem_pattern_init_done & (wr_wdt != WR_WDT) & (!memc_wr_en) & wdt_en_i) begin + // app_wdf_wren + wr_wdt <= wr_wdt + 1'b1; + end else if (memc_wr_en) begin + // app_wdf_wren + wr_wdt <= 'b0; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + cmd_wdt_err_o <= 'b0; + rd_wdt_err_o <= 'b0; + wr_wdt_err_o <= 'b0; + end else begin + cmd_wdt_err_o <= cmd_wdt == CMD_WDT; + rd_wdt_err_o <= rd_wdt == RD_WDT; + wr_wdt_err_o <= wr_wdt == WR_WDT; + end + end + + +//synthesis translate_off +initial +begin +@ (posedge cmd_wdt_err_o); +$display ("ERROR: COMMAND Watch Dog Timer Expired"); +repeat (20) @ (posedge clk); +$finish; +end + +initial +begin +@ (posedge rd_wdt_err_o); +$display ("ERROR: READ Watch Dog Timer Expired"); +repeat (20) @ (posedge clk); +$finish; +end + +initial +begin +@ (posedge wr_wdt_err_o) +$display ("ERROR: WRITE Watch Dog Timer Expired"); +repeat (20) @ (posedge clk); +$finish; +end + +initial +begin +@ (posedge error) +repeat (20) @ (posedge clk); +$finish; +end +//synthesis translate_on + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v new file mode 100644 index 0000000..12cd0cb --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v @@ -0,0 +1,397 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: tb_cmd_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:25 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Fuji +//Design Name: vio_init_pattern_bram +//Purpose: This moduel takes external defined data inputs as its bram init pattern. +// It allows users to change simple test data pattern withoug recompilation. +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif +module mig_7series_v4_2_vio_init_pattern_bram # + ( + parameter TCQ = 100, + parameter START_ADDR = 32'h00000000, + parameter MEM_BURST_LEN = 8, + parameter ADDR_WIDTH = 4, + parameter DEPTH = 16, + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = NUM_DQ_PINS // possible value : 0 to NUM_DQ_PINS + + ) + ( + input clk_i, + input rst_i, + input cmd_start, + input [31:0] cmd_addr, // + input mode_load_i, // signal to initialze internal bram + // with input data1 through data9. + input [3:0] data_mode_i, // selection of data pattern. + input [31:0] data0, // data1 through data8 are + input [31:0] data1, // used as simple traffic data + input [31:0] data2, // pattern that repeats continuously + input [31:0] data3, + input [31:0] data4, + input [31:0] data5, + input [31:0] data6, + input [31:0] data7, + input [31:0] data8, // used a fixed input data + + output reg bram_rd_valid_o, + input bram_rd_rdy_i, + output [31:0] dout_o + ); + + function integer logb2; + input [31:0] number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end + endfunction + + reg [ADDR_WIDTH - 1:0] wr_addr /* synthesis syn_maxfan = 8 */; + reg [ADDR_WIDTH - 1:0] rd_addr /* synthesis syn_maxfan = 8 */; + reg init_write; + reg mode_load_r1; + reg mode_load_r2; + reg [31:0] data_in0; + reg [31:0] data_in1; + reg [31:0] data_in2; + reg [31:0] data_in3; + reg [31:0] data_in4; + reg [31:0] data_in5; + reg [31:0] data_in6; + reg [31:0] data_in7; + reg [31:0] data_in8; + reg [31:0] data_in9; + reg [31:0] data_in10; + reg [31:0] data_in11; + reg [31:0] data_in12; + reg [31:0] data_in13; + reg [31:0] data_in14; + reg [31:0] data_in15; + reg [31:0] hdata; + reg [7:0] mem_0 [0:DEPTH - 1]; + reg [7:0] mem_1 [0:DEPTH - 1]; + reg [7:0] mem_2 [0:DEPTH - 1]; + reg [7:0] mem_3 [0:DEPTH - 1]; + reg [31:0] data_in; + reg wr_en; + reg cmd_addr_r9; + integer i,j,k; + + always @ (posedge clk_i) + begin + mode_load_r1 <= mode_load_i; + mode_load_r2 <= mode_load_r1; + end + + always @ (posedge clk_i) + begin + if (rst_i) + init_write <= 'b0; + else if (wr_addr == {4'b0111}) + init_write <= 'b1; + else if (mode_load_r1 && ~mode_load_r2 && data_mode_i != 4'b0010) + init_write <= 'b1; + end + +// generate a mutil_cycle control siganl to improve timing. + always @ (posedge clk_i) + begin + if (rst_i) + wr_en <= 1'b1; + else if (init_write && data_mode_i != 4'b0010) + wr_en <= 1'b1; + end + + always @ (posedge clk_i) + begin + if (rst_i) + wr_addr <= 'b0; + else if (data_mode_i == 4'h1) + wr_addr <= 4'b1000; + else if (data_mode_i == 4'b0011) + wr_addr <= 4'b1001; + else if (~init_write && data_mode_i == 4'b0100) + wr_addr <= 4'b0000; + else if (init_write && wr_en && data_mode_i != 4'b0010 && wr_addr != 15) + wr_addr <= wr_addr + 1'b1; + end + +// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. +// The incoming addr_i[5:2] determine the position of the pin driving oppsite polarity +// addr_i[6:2] = 5'h0f ; 32 bit data port +// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111 +// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 + +// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level. + always @ (posedge clk_i) + begin + for (i= 0; i <= 31; i= i+1) //begin: hammer_data + if (i >= NUM_DQ_PINS) begin + if (SEL_VICTIM_LINE == NUM_DQ_PINS) + hdata[i] <= 1'b0; + else if ( + ((i == SEL_VICTIM_LINE-1) || (i-NUM_DQ_PINS) == SEL_VICTIM_LINE || + (i-(NUM_DQ_PINS*2)) == SEL_VICTIM_LINE || + (i-(NUM_DQ_PINS*3)) == SEL_VICTIM_LINE)) + hdata[i] <= 1'b1; + else + hdata[i] <= 1'b0; + end + else + hdata[i] <= 1'b1; + end + +// content formats +// {burst length, instruction, address} + initial begin + mem_0[0] = {2'b00,6'h00}; + mem_1[0] = 8'h0; + mem_2[0] = 8'h0; + mem_3[0] = 8'h0; + mem_0[1] = {2'b00,6'h04}; + mem_1[1] = 8'h0; + mem_2[1] = 8'h0; + mem_3[1] = 8'h0; + mem_0[2] = {2'b00,6'h08}; + mem_1[2] = 8'h0; + mem_2[2] = 8'h0; + mem_3[2] = 8'h0; + mem_0[3] = {2'b00,6'h0c}; + mem_1[3] = 8'h0; + mem_2[3] = 8'h0; + mem_3[3] = 8'h0; + mem_0[4] = {2'b00,6'h10}; + mem_1[4] = 8'h0; + mem_2[4] = 8'h0; + mem_3[4] = 8'h0; + mem_0[5] = {2'b00,6'h14}; + mem_1[5] = 8'h0; + mem_2[5] = 8'h0; + mem_3[5] = 8'h0; + mem_0[6] = {2'b00,6'h18}; + mem_1[6] = 8'h0; + mem_2[6] = 8'h0; + mem_3[6] = 8'h0; + mem_0[7] = {2'b00,6'h1c}; + mem_1[7] = 8'h0; + mem_2[7] = 8'h0; + mem_3[7] = 8'h0; + mem_0[8] = {2'b00,6'h20}; + mem_1[8] = 8'h0; + mem_2[8] = 8'h0; + mem_3[8] = 8'h0; + mem_0[9] = {2'b00,6'h24}; + mem_1[9] = 8'h0; + mem_2[9] = 8'h0; + mem_3[9] = 8'h0; + mem_0[10] = 8'hff; + mem_1[10] = 8'hff; + mem_2[10] = 8'hff; + mem_3[10] = 8'hff; + mem_0[11] = 8'h0; + mem_1[11] = 8'h0; + mem_2[11] = 8'h0; + mem_3[11] = 8'h0; + mem_0[12] = {2'b00,6'h30}; + mem_1[12] = 8'h0; + mem_2[12] = 8'h0; + mem_3[12] = 8'h0; + mem_0[13] = {2'b00,6'h34}; + mem_1[13] = 8'h0; + mem_2[13] = 8'h0; + mem_3[13] = 8'h0; + mem_0[14] = {2'b00,6'h38}; + mem_1[14] = 8'h0; + mem_2[14] = 8'h0; + mem_3[14] = 8'h0; + mem_0[15] = {2'b00,6'h3c}; + mem_1[15] = 8'h0; + mem_2[15] = 8'h0; + mem_3[15] = 8'h0; + end + +// address is one cycle earlier. + always @ (posedge clk_i) + begin + if (rst_i) + data_in <= #TCQ data0; + else begin + case(wr_addr) + 0: if (init_write) + data_in <= #TCQ data_in1; + else + data_in <= #TCQ data_in0; + 1: data_in <= #TCQ data_in2; + 2: data_in <= #TCQ data_in3; + 3: data_in <= #TCQ data_in4; + 4: data_in <= #TCQ data_in5; + 5: data_in <= #TCQ data_in6; + 6: data_in <= #TCQ data_in7; + 7: data_in <= #TCQ data_in7; + 8: data_in <= #TCQ data_in8; + 9: data_in <= #TCQ data_in9; + 10: data_in <= #TCQ data_in10; + 11: data_in <= #TCQ data_in11; + 12: data_in <= #TCQ data_in12; + 13: data_in <= #TCQ data_in13; + 14: data_in <= #TCQ data_in14; + 15: data_in <= #TCQ data_in15; + default: data_in <= data8; + endcase + end + end + + always @(posedge clk_i) begin + mem_0[wr_addr] <= data_in[7:0]; + mem_1[wr_addr] <= data_in[15:8]; + mem_2[wr_addr] <= data_in[23:16]; + mem_3[wr_addr] <= data_in[31:24]; + end + + always @ (data_mode_i, data0,data1,data2,data3,data4,data5,data6,data7,data8,hdata) + begin + data_in0[31:0] = #TCQ data0; + data_in1[31:0] = #TCQ data1; + data_in2[31:0] = #TCQ data2; + data_in3[31:0] = #TCQ data3; + data_in4[31:0] = #TCQ data4; + data_in5[31:0] = #TCQ data5; + data_in6[31:0] = #TCQ data6; + data_in7[31:0] = #TCQ data7; + data_in8[31:0] = #TCQ data8; + data_in9[31:0] = #TCQ hdata; + data_in10[31:0] = #TCQ 32'hffffffff; + data_in11[31:0] = #TCQ 32'h00000000; + data_in12[31:0] = #TCQ 'b0; + data_in13[31:0] = #TCQ 'b0; + data_in14[31:0] = #TCQ 'b0; + data_in15[31:0] = #TCQ 'b0; + end + + always @ (posedge clk_i) + begin + if (cmd_start) + cmd_addr_r9 <= cmd_addr[9]; + end + + always @ (posedge clk_i) + if (rst_i) + bram_rd_valid_o <= 1'b0; + else if (wr_addr[3:0] == {ADDR_WIDTH - 1{1'b1}} || data_mode_i == 2 || data_mode_i == 3) + bram_rd_valid_o <= 1'b1; + +// rd_address generation depending on data pattern mode. + always @ (posedge clk_i) + begin + if (rst_i) begin + if (data_mode_i == 9) begin + rd_addr[3:1] <= #TCQ 3'b101; + rd_addr[0] <= #TCQ cmd_addr[9]; + end + else if (data_mode_i == 1) + rd_addr[3:0] <= #TCQ 8; + else if (data_mode_i == 3) // address as data pattern + rd_addr <= #TCQ 9; + else + rd_addr <= #TCQ 0; + end + else if (cmd_start) begin + if (data_mode_i == 3) + rd_addr[3:0] <= #TCQ 9; + else if (data_mode_i == 1) + rd_addr[3:0] <= #TCQ 8; + else if (data_mode_i == 9) begin + rd_addr[3:1] <= #TCQ 3'b101; + rd_addr[0] <= #TCQ cmd_addr[9]; + end + else + rd_addr[3:0] <= #TCQ 0; + end + else if (bram_rd_rdy_i) begin + case (data_mode_i) + 4'h2: rd_addr <= #TCQ 0; + 4'h4: if (rd_addr == 7) + rd_addr <= #TCQ 0; + else + rd_addr <= #TCQ rd_addr+ 1'b1; + 4'h1: rd_addr <= #TCQ 8; + 4'h3: rd_addr <= #TCQ 9; + 4'h9: begin + rd_addr[3:1] <= #TCQ 3'b101; + rd_addr[0] <= #TCQ cmd_addr_r9; + end + default: rd_addr <= #TCQ 0; + endcase + end + end + +// need to infer distributed RAM to meet output timing +// in upper level +assign dout_o = {mem_3[rd_addr],mem_2[rd_addr],mem_1[rd_addr],mem_0[rd_addr]}; // + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_wr_data_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_wr_data_gen.v new file mode 100644 index 0000000..dd5e408 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_wr_data_gen.v @@ -0,0 +1,433 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: wr_data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: +//Reference: +//Revision History: 5/2/2012 Fixed data_wr_end_r logic which didn't hold its state when data_rdy_i was deasserted and +// data_valid was asserted. +// +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_wr_data_gen # + +( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6" + parameter MEM_BURST_LEN = 8, + parameter START_ADDR = 32'h00000000, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + parameter MEM_TYPE = "DDR3", + + parameter MODE = "WR", //"WR", "RD" + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter COLUMN_WIDTH = 10, + parameter EYE_TEST = "FALSE" + + ) + ( + input clk_i, // + input [4:0] rst_i, + input [31:0] prbs_fseed_i, + input mode_load_i, + + input [3:0] data_mode_i, // "00" = bram; + input mem_init_done_i, + input wr_data_mask_gen_i, + + output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. + // And then it should reasserted when + // it is generating the last_word. + input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. + input cmd_validB_i, + input cmd_validC_i, + + output last_word_o, + + // input [5:0] port_data_counts_i,// connect to data port fifo counts + // input [ADDR_WIDTH-1:0] m_addr_i, + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [31:0] fixed_data_i, + + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data + input memc_cmd_full_i, + + input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen + // connect from mcb_rd_empty when used as rd_data_gen + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output data_valid_o, // connect to wr_en or rd_en and is asserted whenever the + // pattern is available. + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, // generated data pattern + output data_wr_end_o, + output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o + + + +); +// + + +reg [DWIDTH-1:0] data; + + + +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF; +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF; + + + + +reg burst_count_reached2; + +reg data_valid; +reg [BL_WIDTH:0]user_burst_cnt; +reg [2:0] walk_cnt; +wire fifo_not_full; +integer i,j; +reg [31:0] w3data; +reg data_wr_end_r; +wire data_wr_end; +wire bram_rd_valid_o; + +function integer logb2; + input [31:0] number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end +endfunction + + +assign fifo_not_full = data_rdy_i; + + +// data_wr_end_r is used in nCK_PER_CLK == 2; when nCK_PER_CLK = 4, data_wr_end_o == data_valid_o; + +always @(posedge clk_i) +begin + if (~user_burst_cnt[0] && data_valid && data_rdy_i && MEM_BURST_LEN == 8) + data_wr_end_r <= #TCQ 1'b1; + else if (data_rdy_i) // keep the data_wr_end_r asserted if data_rdy_i is deasserted because of mc's write + // data fifo full. + data_wr_end_r <= #TCQ 1'b0; +end + +//assign data_wr_end_o = data_wr_end_r && fifo_not_full; */ +assign data_wr_end_o = (nCK_PER_CLK == 4 || nCK_PER_CLK == 2 && MEM_BURST_LEN == 4) ? data_valid_o :data_wr_end_r ;//(MEM_BURST_LEN == 8) ? user_burst_cnt[0] & data_valid_o : + +assign data_valid_o = data_valid ;//& ~memc_cmd_full_i;// (nCK_PER_CLK == 4)?data_valid_r: data_valid ;//& fifo_not_full; + +//assign data_wr_end_o = data_wr_end_r; + + +always @ (posedge clk_i) +begin +cmd_start <= #TCQ cmd_validC_i & cmd_rdyC ; +cmd_startB <= #TCQ cmd_valid_i & cmd_rdyB; +cmd_startC <= #TCQ cmd_validB_i & cmd_rdyC; +cmd_startD <= #TCQ cmd_validB_i & cmd_rdyD; +cmd_startE <= #TCQ cmd_validB_i & cmd_rdyE; +cmd_startF <= #TCQ cmd_validB_i & cmd_rdyF; +end + + +// counter to count user burst length +// verilint STARC-2.2.3.3 off +always @( posedge clk_i) +begin + if ( rst_i[0] ) + user_burst_cnt <= #TCQ 'd0; + else if(cmd_start) + // if (FAMILY == "SPARTAN6") begin + // SPATAN6 has maximum of burst length of 64. + if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000) + // user_burst_cnt <= #TCQ 7'b1000000; + begin + user_burst_cnt[6:0] <= #TCQ 7'd64; + user_burst_cnt[BL_WIDTH:7] <= 'b0; + end + else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}}) + user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}}; + + else + user_burst_cnt <= #TCQ {1'b0,bl_i}; + + // else + // user_burst_cnt <= #TCQ bl_i; +// else if(fifo_not_full && data_valid && ~memc_cmd_full_i) +// verilint STARC-2.2.3.3 on + else if(fifo_not_full && data_valid ) + + if (user_burst_cnt != 6'd0) + user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; + else + user_burst_cnt <=#TCQ 'd0; + +end + +reg u_bcount_2; +wire last_word_t; +always @ (posedge clk_i) +begin +if ((user_burst_cnt == 2 && fifo_not_full )|| (cmd_startC && bl_i == 1)) + u_bcount_2 <= #TCQ 1'b1; +else if (last_word_o) + u_bcount_2 <= #TCQ 1'b0; +end + + +assign last_word_o = u_bcount_2 & fifo_not_full; + +// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i +// is assert and reassert during the last data + +assign cmd_rdy_o = cmd_rdy & fifo_not_full; + + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdy <= #TCQ 1'b1; // the state should be '0' for bram_interface during reset. + else if (bram_rd_valid_o) // need work here. + cmd_rdy <= #TCQ 1'b1; + + else if (cmd_start) + if (bl_i == 1) + cmd_rdy <= #TCQ 1'b1; + else + cmd_rdy <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + cmd_rdy <= #TCQ bram_rd_valid_o;//1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i [0]) + cmd_rdyB <= #TCQ 1'b1; + else if (cmd_startB) + if (bl_i == 1) + cmd_rdyB <= #TCQ 1'b1; + else + cmd_rdyB <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyB <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyC <= #TCQ 1'b1; + else if (cmd_startC) + if (bl_i == 1) + cmd_rdyC <= #TCQ 1'b1; + else + cmd_rdyC <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyC <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyD <= #TCQ 1'b1; + else if (cmd_startD) + if (bl_i == 1) + cmd_rdyD <= #TCQ 1'b1; + else + cmd_rdyD <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyD <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyE <= #TCQ 1'b1; + else if (cmd_startE) + if (bl_i == 1) + cmd_rdyE <= #TCQ 1'b1; + else + cmd_rdyE <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyE <= #TCQ 1'b1; + + +end + + + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyF <= #TCQ 1'b1; + else if (cmd_startF) + if (bl_i == 1) + cmd_rdyF <= #TCQ 1'b1; + else + cmd_rdyF <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + cmd_rdyF <= #TCQ 1'b1; + + +end + + +reg dvalid; + +always @ (posedge clk_i) +begin + if (rst_i[1]) + data_valid <= #TCQ 'd0; + else if(cmd_start) + data_valid <= #TCQ 1'b1; + else if (fifo_not_full && user_burst_cnt <= 6'd1) + data_valid <= #TCQ 1'b0; + + // data_valid <= dvalid ; +end + +mig_7series_v4_2_s7ven_data_gen # + ( + .TCQ (TCQ), + .ADDR_WIDTH (32 ), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + .BL_WIDTH (BL_WIDTH), + .DWIDTH (DWIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .nCK_PER_CLK (nCK_PER_CLK), + .START_ADDR (START_ADDR), + .DATA_PATTERN (DATA_PATTERN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .COLUMN_WIDTH (COLUMN_WIDTH), + .EYE_TEST (EYE_TEST) + ) + s7ven_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .prbs_fseed_i (prbs_fseed_i), + .mem_init_done_i (mem_init_done_i), + .mode_load_i (mode_load_i), + .wr_data_mask_gen_i (wr_data_mask_gen_i), + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_startB ), + .cmd_startC (cmd_startC ), + .cmd_startD (cmd_startD ), + .cmd_startE (cmd_startE ), + .m_addr_i (addr_i ), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (fifo_not_full ), + .data_o (data_o ), + .data_mask_o (data_mask_o), + .bram_rd_valid_o (bram_rd_valid_o), + .tg_st_addr_o () + ); + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_write_data_path.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_write_data_path.v new file mode 100644 index 0000000..97a1d28 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_2_write_data_path.v @@ -0,0 +1,193 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: write_data_path.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This is top level of write path . + +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + + +module mig_7series_v4_2_write_data_path #( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter MEM_TYPE = "DDR3", + + parameter ADDR_WIDTH = 32, + parameter START_ADDR = 32'h00000000, + parameter BL_WIDTH = 6, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + parameter MEM_BURST_LEN = 8, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter MEM_COL_WIDTH = 10, + parameter EYE_TEST = "FALSE" + + ) + ( + + input clk_i, + input [9:0] rst_i, + output cmd_rdy_o, + input cmd_valid_i, + input cmd_validB_i, + input cmd_validC_i, + input [31:0] prbs_fseed_i, + input [3:0] data_mode_i, + input mem_init_done_i, + input wr_data_mask_gen_i, + // input [31:0] m_addr_i, + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [31:0] fixed_data_i, + input mode_load_i, + + input [31:0] addr_i, + input [BL_WIDTH-1:0] bl_i, + +// input [5:0] port_data_counts_i,// connect to data port fifo counts + input memc_cmd_full_i, + input data_rdy_i, + output data_valid_o, + output last_word_wr_o, + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, + output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o, + output data_wr_end_o + + ); + +wire data_valid; +reg cmd_rdy; + + assign data_valid_o = data_valid;// & data_rdy_i; + + + mig_7series_v4_2_wr_data_gen # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + .NUM_DQ_PINS (NUM_DQ_PINS), + .MEM_BURST_LEN (MEM_BURST_LEN), + .BL_WIDTH (BL_WIDTH), + .START_ADDR (START_ADDR), + .nCK_PER_CLK (nCK_PER_CLK), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .COLUMN_WIDTH (MEM_COL_WIDTH), + .EYE_TEST (EYE_TEST) + + ) + wr_data_gen( + .clk_i (clk_i ), + .rst_i (rst_i[9:5]), + .prbs_fseed_i (prbs_fseed_i), + .wr_data_mask_gen_i (wr_data_mask_gen_i), + .mem_init_done_i (mem_init_done_i), + .data_mode_i (data_mode_i ), + .cmd_rdy_o (cmd_rdy_o ), + .cmd_valid_i (cmd_valid_i ), + .cmd_validB_i (cmd_validB_i ), + .cmd_validC_i (cmd_validC_i ), + + .last_word_o (last_word_wr_o ), + // .port_data_counts_i (port_data_counts_i), + // .m_addr_i (m_addr_i ), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + + .mode_load_i (mode_load_i), + + .addr_i (addr_i ), + .bl_i (bl_i ), + .memc_cmd_full_i (memc_cmd_full_i), + + .data_rdy_i (data_rdy_i ), + .data_valid_o ( data_valid ), + .data_o (data_o ), + .data_wr_end_o (data_wr_end_o), + .data_mask_o (data_mask_o) + ); + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model.sv b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model.sv new file mode 100644 index 0000000..29418ff --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model.sv @@ -0,0 +1,2938 @@ +//`define MAX_MEM + +/**************************************************************************************** +* +* File Name: ddr3.v +* Version: 1.72 +* Model: BUS Functional +* +* Dependencies: ddr3_model_parameters.vh +* +* Description: Micron SDRAM DDR3 (Double Data Rate 3) +* +* Limitation: - doesn't check for average refresh timings +* - positive ck and ck_n edges are used to form internal clock +* - positive dqs and dqs_n edges are used to latch data +* - test mode is not modeled +* - Duty Cycle Corrector is not modeled +* - Temperature Compensated Self Refresh is not modeled +* - DLL off mode is not modeled. +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set DEBUG = 0 to disable $display messages +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +* Rev Author Date Changes +* --------------------------------------------------------------------------------------- +* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check. +* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n. +* TDQS can only be enabled in EMR for x8 configurations. +* CAS latency is checked vs frequency when DLL locks. +* Improved checking of DQS during writes. +* Added true BL4 operation. +* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers. +* Added ODTS Readout. +* Replaced tZQCL with tZQinit and tZQoper +* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS. +* Added tRFC checking for Refresh to Power-Down Re-Entry. +* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry +* Added Clock Frequency Change during Precharge Power-Down. +* Added -125x speed grades. +* Fixed tRCD checking during Write. +* 1.00 JMK 05/11/07 Initial release +* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF +* Removed temp sensor readout from MPR +* Updated initialization sequence +* Updated timing parameters +* 1.20 JMK 09/05/07 Updated clock frequency change +* Added ddr3_dimm module +* 1.30 JMK 01/23/08 Updated timing parameters +* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133 +* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support. +* Added multi-chip package model support in ddr3_mcp.v +* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades. +* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes +* 1.61 SPH 12/10/09 Only check tIH for cmd_addr if CS# LOW +* 1.62 SPH 10/26/10 Added 4Gb DDR3 SDRAM support +* 1.63 MYY 11/09/10 Added Dll Disable mode +* 1.64 MYY 07/28/11 Check dqs_in for dqs timing check +* 1.65 MYY 09/19/11 Widen internal bus width +* 1.66 MYY 01/20/12 Support ODT tied high feature +* 1.67 MYY 02/03/12 Added TJIT_PER margin for timing checks +* 1.68 SPH 04/02/12 Added memory preload +* 1.69 SPH 03/19/13 Update tZQCS, tZQinit, tZQoper timing parameters +* 1.70 SPH 04/08/14 Update tRFC to PRECHARGE check +* 1.71 SPH 04/21/14 Added 8Gb mono die parameters +* Remove strict CL check +* 1.72 DLH 06/18/15 calculate TZQCS from current tCK +*****************************************************************************************/ + +// DO NOT CHANGE THE TIMESCALE +// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION +`timescale 1ps / 1ps + +// model flags +// `define MODEL_PASR +//Memory Details +`define x4Gb +`define sg125 +`define x16 +module ddr3_model ( + rst_n, + ck, + ck_n, + cke, + cs_n, + ras_n, + cas_n, + we_n, + dm_tdqs, + ba, + addr, + dq, + dqs, + dqs_n, + tdqs_n, + odt +); + + `include "ddr3_model_parameters.vh" + + parameter check_strict_mrbits = 1; + parameter check_strict_timing = 1; + parameter feature_pasr = 1; + parameter feature_truebl4 = 0; + parameter feature_odt_hi = 0; + parameter PERTCKAVG=TDLLK; + + // text macros + `define DQ_PER_DQS DQ_BITS/DQS_BITS + `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); + if ((1< BL_MAX) + $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); + + $timeformat (-12, 1, " ps", 1); + seed = RANDOM_SEED; + + ck_cntr = 0; + end + + function integer get_rtt_wr; + input [1:0] rtt; + begin + get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0}; + end + endfunction + + function integer get_rtt_nom; + input [2:0] rtt; + begin + case (rtt) + 1: get_rtt_nom = RZQ/4; + 2: get_rtt_nom = RZQ/2; + 3: get_rtt_nom = RZQ/6; + 4: get_rtt_nom = RZQ/12; + 5: get_rtt_nom = RZQ/8; + default : get_rtt_nom = 0; + endcase + end + endfunction + + // calculate the absolute value of a real number + function real abs_value; + input arg; + real arg; + begin + if (arg < 0.0) + abs_value = -1.0 * arg; + else + abs_value = arg; + end + endfunction + + function integer ceil; + input number; + real number; + + // LMR 4.1.7 + // When either operand of a relational expression is a real operand then the other operand shall be converted + // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. + if (number > $rtoi(number)) + ceil = $rtoi(number) + 1; + else + ceil = number; + endfunction + + function integer floor; + input number; + real number; + + // LMR 4.1.7 + // When either operand of a relational expression is a real operand then the other operand shall be converted + // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. + if (number < $rtoi(number)) + floor = $rtoi(number) - 1; + else + floor = number; + endfunction + + function int max( input int a, b ); + max = (a < b) ? b : a; + endfunction + + function int min( input int a, b ); + min = (a > b) ? b : a; + endfunction + +`ifdef MAX_MEM + + function integer open_bank_file( input integer bank ); + integer fd; + reg [2048:1] filename; + begin + $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank ); + + fd = $fopen(filename, "wb+"); + if (fd == 0) + begin + $display("%m: at time %0t ERROR: failed to open %0s.", $time, filename); + $finish; + end + else + begin + if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename); + open_bank_file = fd; + end + + end + endfunction + + function [RFF_BITS:1] read_from_file( + input integer fd, + input integer index + ); + integer code; + integer offset; + reg [1024:1] msg; + reg [RFF_BITS:1] read_value; + + begin + offset = index * RFF_CHUNK; + code = $fseek( fd, offset, 0 ); + // $fseek returns 0 on success, -1 on failure + if (code != 0) + begin + $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); + $finish; + end + + code = $fscanf(fd, "%z", read_value); + // $fscanf returns number of items read + if (code != 1) + begin + if ($ferror(fd,msg) != 0) + begin + $display("%m: at time %t ERROR: fscanf failed at %d", $time, index); + $display(msg); + $finish; + end + else + read_value = 'hx; + end + + /* when reading from unwritten portions of the file, 0 will be returned. + * Use 0 in bit 1 as indicator that invalid data has been read. + * A true 0 is encoded as Z. + */ + if (read_value[1] === 1'bz) + // true 0 encoded as Z, data is valid + read_value[1] = 1'b0; + else if (read_value[1] === 1'b0) + // read from file section that has not been written + read_value = 'hx; + + read_from_file = read_value; + end + endfunction + + task write_to_file( + input integer fd, + input integer index, + input [RFF_BITS:1] data + ); + integer code; + integer offset; + + begin + offset = index * RFF_CHUNK; + code = $fseek( fd, offset, 0 ); + if (code != 0) + begin + $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); + $finish; + end + + // encode a valid data + if (data[1] === 1'bz) + data[1] = 1'bx; + else if (data[1] === 1'b0) + data[1] = 1'bz; + + $fwrite( fd, "%z", data ); + end + endtask +`else + function get_index; + input [`MAX_BITS-1:0] addr; + begin : index + get_index = 0; + for (memory_index=0; memory_index>(ROW_BITS+COL_BITS-BL_BITS)); + if (!banks[ba]) begin //bank is selected to keep + address[i] = address[memory_index]; + memory[i] = memory[memory_index]; + i = i + 1; + end + end + // clean up the unused banks + for (memory_index=i; memory_index TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); + if ($time - tm_bank_activate[bank] < TRAS_MIN-TJIT_PER) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end + {1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC-TJIT_PER) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, SAME_BANK , ACTIVATE , WRITE } , + {1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task + {1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC-TJIT_PER) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end + + // write + {1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR-TJIT_PER) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR-TJIT_PER) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end + + // read + {1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP-TJIT_PER) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task + {1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task + {1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task + {1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end + + // zq + {1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK + {1'bx, DIFF_BANK , ZQ , REFRESH } , + {1'bx, DIFF_BANK , ZQ , PRECHARGE} , + {1'bx, DIFF_BANK , ZQ , ACTIVATE } , + {1'bx, DIFF_BANK , ZQ , ZQ } , + {1'bx, DIFF_BANK , ZQ , PWR_DOWN } , + {1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]); + if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]); + if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end + + // power down + {1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} , + {1'bx, DIFF_BANK , PWR_DOWN , REFRESH } , + {1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} , + {1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } , + {1'bx, DIFF_BANK , PWR_DOWN , WRITE } , + {1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); + else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } , + {1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); + if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); + if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); + if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end + + // self refresh + {1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} , + {1'bx, DIFF_BANK , SELF_REF , REFRESH } , + {1'bx, DIFF_BANK , SELF_REF , PRECHARGE} , + {1'bx, DIFF_BANK , SELF_REF , ACTIVATE } , + {1'bx, DIFF_BANK , SELF_REF , WRITE } , + {1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } , + {1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); + if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end + endcase + end + endtask + + task cmd_task; + inout prev_cke; + input cke; + input [2:0] cmd; + input [BA_BITS-1:0] bank; + input [ADDR_BITS-1:0] addr; + reg [`BANKS:0] i; + integer j; + reg [`BANKS:0] tfaw_cntr; + reg [COL_BITS-1:0] col; + reg group; + begin + // tRFC max check + if (!er_trfc_max && !in_self_refresh) begin + if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin + $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); + er_trfc_max = 1; + end + end + if (cke) begin + if ((cmd < NOP) && (cmd != PRECHARGE)) begin + if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(SAME_BANK , bank, j, cmd); + chk_err(DIFF_BANK , bank, j, cmd); + chk_err(DIFF_GROUP, bank, j, cmd); + end + end + case (cmd) + LOAD_MODE : begin + if (|odt_pipeline) + $display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]); + if (odt_state && !feature_odt_hi) + $display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]); + + if (|active_bank) begin + $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank); + if (bank>>2) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + case (bank) + 0 : begin + // Burst Length + if (addr[1:0] == 2'b00) begin + burst_length = 8; + blotf = 0; + truebl4 = 0; + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); + end else if (addr[1:0] == 2'b01) begin + burst_length = 8; + blotf = 1; + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank); + end else if (addr[1:0] == 2'b10) begin + burst_length = 4; + blotf = 0; + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]); + end + // Burst Order + burst_order = addr[3]; + if (!burst_order) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); + end else if (burst_order) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); + end + // CAS Latency + cas_latency = {addr[2],addr[6:4]} + 4; + set_latency; + if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); + end + // Reserved + if (addr[7] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // DLL Reset + dll_reset = addr[8]; + if (!dll_reset) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); + end else if (dll_reset) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); + dll_locked = 0; + init_dll_reset = 1; + ck_dll_reset <= ck_cntr; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); + end + + // Write Recovery + if (addr[11:9] == 0) begin + write_recovery = 16; + end else if (addr[11:9] < 4) begin + write_recovery = addr[11:9] + 4; + end else begin + write_recovery = 2*addr[11:9]; + end + + if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); + end + // Power Down Mode + low_power = !addr[12]; + if (!low_power) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank); + end else if (low_power) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); + end + // Reserved + if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + 1 : begin + // DLL Enable + dll_en = !addr[0]; + if (!dll_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); + if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not fully modeled", $time, cmd_string[cmd], bank); + end else if (dll_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); + end + // Output Drive Strength + if ({addr[5], addr[1]} == 2'b00) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6); + end else if ({addr[5], addr[1]} == 2'b01) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7); + end else if ({addr[5], addr[1]} == 2'b11) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]}); + end + // ODT Rtt (Rtt_NOM) + odt_rtt_nom = {addr[9], addr[6], addr[2]}; + if (odt_rtt_nom == 3'b000) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); + odt_en = 0; + end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom)); + odt_en = 1; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom); + odt_en = 0; + end + // Report the additive latency value + al = addr[4:3]; + set_latency; + if (al == 0) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al); + end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al); + end + // Write Levelization + write_levelization = addr[7]; + if (!write_levelization) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank); + end else if (write_levelization) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization); + end + // Reserved + if (addr[8] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // Reserved + if (addr[10] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // TDQS Enable + tdqs_en = addr[11]; + if (!tdqs_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (tdqs_en) begin + if (8 == DQ_BITS) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank); + end + else begin + $display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank); + tdqs_en = 0; + end + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en); + end + // Output Enable + out_en = !addr[12]; + if (!out_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank); + end else if (out_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en); + end + // Reserved + if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + 2 : begin + if (feature_pasr) begin + // Partial Array Self Refresh + pasr = addr[2:0]; + case (pasr) + 3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank); + 3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank); + 3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank); + 3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank); + 3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank); + 3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank); + 3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank); + 3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank); + default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr); + endcase + end + else + if (addr[2:0] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // CAS Write Latency + cas_write_latency = addr[5:3]+5; + set_latency; + if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); + end + // Auto Self Refresh Method + asr = addr[6]; + if (!asr) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank); + end else if (asr) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank); + if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr); + end + // Self Refresh Temperature + srt = addr[7]; + if (!srt) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank); + end else if (srt) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank); + if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt); + end + if (asr && srt) + $display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank); + // Reserved + if (addr[8] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // Dynamic ODT (Rtt_WR) + odt_rtt_wr = addr[10:9]; + if (odt_rtt_wr == 2'b00) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank); + dyn_odt_en = 0; + end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr)); + dyn_odt_en = 1; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr); + dyn_odt_en = 0; + end + // Reserved + if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + 3 : begin + mpr_select = addr[1:0]; + // MultiPurpose Register Select + if (mpr_select == 2'b00) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank); + end else begin + if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select); + end + // MultiPurpose Register Enable + mpr_en = addr[2]; + if (!mpr_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (mpr_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en); + end + + if (feature_truebl4 && (addr[11] == 1'b1)) begin + if (addr[11] == 1'b1) begin + truebl4 = 1; + $display(" EMRS3 Set True Bl4 mode only "); + end + end + + // Reserved + if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + endcase + if (dyn_odt_en && write_levelization) + $display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time); + init_mode_reg[bank] = 1; + mode_reg[bank] = addr; + // dll_reset bit self clear + if(bank==0 && addr[8]==1'b1) + mode_reg[0][8] <= #($rtoi(tck_avg)) 1'b0; + tm_load_mode <= $time; + ck_load_mode <= ck_cntr; + end + end + REFRESH : begin + if (mpr_en) begin + $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else if (|active_bank) begin + $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); + er_trfc_max = 0; + ref_cntr = ref_cntr + 1; + tm_refresh <= $time; + ck_refresh <= ck_cntr; + end + end + PRECHARGE : begin + if (addr[AP]) begin + if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]); + end + // PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), + // or if the previously open row is already in the process of precharging + if (|active_bank) begin + if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); + if (mpr_en) begin + $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else begin + for (i=0; i<`BANKS; i=i+1) begin + if (active_bank[i]) begin + if (addr[AP] || (i == bank)) begin + + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(SAME_BANK, i, j, cmd); + chk_err(DIFF_BANK, i, j, cmd); + end + + if (auto_precharge_bank[i]) begin + $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i); + active_bank[i] = 1'b0; + tm_bank_precharge[i] <= $time; + tm_precharge <= $time; + ck_precharge <= ck_cntr; + end + end + end + end + end + end // if (|active_bank) + else begin + chk_err(DIFF_BANK, 0, REFRESH, PRECHARGE); + end + end + ACTIVATE : begin + tfaw_cntr = 0; + for (i=0; i<`BANKS; i=i+1) begin + if ($time - tm_bank_activate[i] < TFAW) begin + tfaw_cntr = tfaw_cntr + 1; + end + end + if (tfaw_cntr > 3) begin + $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); + end + + if (mpr_en) begin + $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else if (!init_done) begin + $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else if (active_bank[bank]) begin + $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (addr >= 1< AP +`else + col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP +`endif + if (col >= 1< AP +`else + col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP +`endif + if (col >= 1< TPD_MAX) + $display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time); + if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time); + in_power_down = 0; + if ((active_bank == 0) && low_power) begin // precharge power down with dll off + if (ck_cntr - ck_odt < write_latency - 1) + $display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time); + tm_slow_exit_pd <= $time; + ck_slow_exit_pd <= ck_cntr; + end + tm_power_down <= $time; + ck_power_down <= ck_cntr; + end + if (in_self_refresh) begin + if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK)) + $display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time); + if (ck_cntr - ck_cke_cmd < TCKESR_TCK) + $display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time); + if ($time - tm_cke < TISXR) + $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time); + if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time); + in_self_refresh = 0; + ck_dll_reset <= ck_cntr; + ck_self_refresh <= ck_cntr; + tm_self_refresh <= $time; + tm_refresh <= $time; + end + end + endcase + if ((prev_cke !== 1) && (cmd !== NOP)) begin + $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time); + end + + if (!init_done) begin + case (init_step) + 0 : begin + if ($time - tm_rst_n < 500000000 && check_strict_timing) + $display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time); + tm_txpr <= $time; + ck_txpr <= ck_cntr; + init_step = init_step + 1; + end + 1 : begin + if (dll_en) init_step = init_step + 1; + end + 2 : begin + if (&init_mode_reg && init_dll_reset && zq_set) begin + if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); + init_done = 1; + end + end + endcase + end + end else if (prev_cke) begin + if ((!init_done) && (init_step > 1)) begin + $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); + if (STOP_ON_ERROR) $stop(0); + end + case (cmd) + REFRESH : begin + if ($time - tm_txpr < TXPR) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]); + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(DIFF_BANK, bank, j, SELF_REF); + end + + if (mpr_en) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (|active_bank) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (odt_state) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (!init_done) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time); + if (feature_pasr) + // Partial Array Self Refresh + case (pasr) + 3'b000 : ;//keep Bank 0-7 + 3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end + 3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end + 3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end + 3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end + 3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end + 3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end + 3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end + endcase + in_self_refresh = 1; + dll_locked = 0; + end + end + NOP : begin + // entering precharge power down with dll off and tANPD has not been satisfied + if (low_power && (active_bank == 0) && |odt_pipeline) + $display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]); + if ($time - tm_txpr < TXPR) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]); + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(DIFF_BANK, bank, j, PWR_DOWN); + end + + if (mpr_en) begin + $display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (!init_done) begin + $display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) begin + if (|active_bank) begin + $display ("%m: at time %t INFO: Active Power Down Enter", $time); + end else begin + $display ("%m: at time %t INFO: Precharge Power Down Enter", $time); + end + end + in_power_down = 1; + end + end + default : begin + $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time); + end + endcase + end else if (in_self_refresh || in_power_down) begin + if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP)) + $display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time); + end + prev_cke = cke; + + end + endtask + + task data_task; + reg [BA_BITS-1:0] bank; + reg [ROW_BITS-1:0] row; + reg [COL_BITS-1:0] col; + integer i; + integer j; + begin + + if (diff_ck) begin + for (i=0; i<64; i=i+1) begin + if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg))) + $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/32], i%32); + if (check_write_dqs_high[i]) + $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/32], i%32); + end + check_write_dqs_high <= 0; + end else begin + for (i=0; i<64; i=i+1) begin + if (dll_locked && dq_in_valid) begin + tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]); + if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg)) + $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/32], i%32); + end + if (check_write_dqs_low[i]) + $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/32], i%32); + end + check_write_preamble <= 0; + check_write_postamble <= 0; + check_write_dqs_low <= 0; + end + + if (wr_pipeline[0] || rd_pipeline[0]) begin + bank = ba_pipeline[0]; + row = row_pipeline[0]; + col = col_pipeline[0]; + burst_cntr = 0; + memory_read(bank, row, col, memory_data); + end + + // burst counter + if (burst_cntr < burst_length) begin + burst_position = col ^ burst_cntr; + if (!burst_order) begin + burst_position[BO_BITS-1:0] = col + burst_cntr; + end + burst_cntr = burst_cntr + 1; + end + + // write dqs counter + if (wr_pipeline[WDQS_PRE + 1]) begin + wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1; + end + // write dqs + if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble + check_write_preamble <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; + end + if (wdqs_cntr > 1) begin // write data + if ((wdqs_cntr - WDQS_PST)%2) begin + check_write_dqs_high <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; + end else begin + check_write_dqs_low <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; + end + end + if (wdqs_cntr == WDQS_PST) begin // write postamble + check_write_postamble <= ({DQS_BITS{1'b1}}<<32) | {DQS_BITS{1'b1}}; + end + if (wdqs_cntr > 0) begin + wdqs_cntr = wdqs_cntr - 1; + end + + // write dq + if (dq_in_valid) begin // write data + bit_mask = 0; + if (diff_ck) begin + for (i=0; i>(burst_position*DQ_BITS); + if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); + if (burst_cntr%BL_MIN == 0) begin + memory_write(bank, row, col, memory_data); + end + end + if (wr_pipeline[1]) begin + wdq_cntr = bl_pipeline[1]; + end + if (wdq_cntr > 0) begin + wdq_cntr = wdq_cntr - 1; + dq_in_valid = 1'b1; + end else begin + dq_in_valid = 1'b0; + dqs_in_valid <= 1'b0; + for (i=0; i<63; i=i+1) begin + wdqs_pos_cntr[i] <= 0; + end + end + if (wr_pipeline[0]) begin + b2b_write <= 1'b0; + end + if (wr_pipeline[2]) begin + if (dqs_in_valid) begin + b2b_write <= 1'b1; + end + dqs_in_valid <= 1'b1; + wr_burst_length = bl_pipeline[2]; + end + + // read dqs enable counter + if (rd_pipeline[RDQSEN_PRE]) begin + rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; + end + if (rdqsen_cntr > 0) begin + rdqsen_cntr = rdqsen_cntr - 1; + dqs_out_en = 1'b1; + end else begin + dqs_out_en = 1'b0; + end + + // read dqs counter + if (rd_pipeline[RDQS_PRE]) begin + rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1; + end + // read dqs + if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble + dqs_out = 1'b0; + end else if (rdqs_cntr > RDQS_PST) begin // read data + dqs_out = rdqs_cntr - RDQS_PST; + end else if (rdqs_cntr > 0) begin // read postamble + dqs_out = 1'b0; + end else begin + dqs_out = 1'b1; + end + if (rdqs_cntr > 0) begin + rdqs_cntr = rdqs_cntr - 1; + end + + // read dq enable counter + if (rd_pipeline[RDQEN_PRE]) begin + rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST; + end + if (rdqen_cntr > 0) begin + rdqen_cntr = rdqen_cntr - 1; + dq_out_en = 1'b1; + end else begin + dq_out_en = 1'b0; + end + // read dq + if (rd_pipeline[0]) begin + rdq_cntr = bl_pipeline[0]; + end + if (rdq_cntr > 0) begin // read data + if (mpr_en) begin +`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low + if (mpr_select == 2'b00) begin // Calibration Pattern + dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}}; + end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) + dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}}; + end else begin // Reserved + dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}}; + end +`else // all DQ output MPR data + if (mpr_select == 2'b00) begin // Calibration Pattern + dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}}; + end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) + dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}}; + end else begin // Reserved + dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}}; + end +`endif + if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]); + end else begin + dq_temp = memory_data>>(burst_position*DQ_BITS); + if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); + end + dq_out = dq_temp; + rdq_cntr = rdq_cntr - 1; + end else begin + dq_out = {DQ_BITS{1'b1}}; + end + + // delay signals prior to output + if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin + for (i=0; i dqsck[i] + TQH*tck_avg + TDQSQ) begin + dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ; + end + dqsck_min = -1*TDQSCK; + if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin + dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ; + end + + // DQSQ requirements + // 1.) less than tDQSQ + // 2.) greater than 0 + // 3.) greater than tQH from the previous DQS edge + dqsq_min = 0; + if (dqsq_min < dqsck[i] - TQH*tck_avg) begin + dqsq_min = dqsck[i] - TQH*tck_avg; + end + if (dqsck_min == dqsck_max) begin + dqsck[i] = dqsck_min; + end else begin + dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); + end + dqsq_max = TDQSQ + dqsck[i]; + + dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en; + dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out; + if (!write_levelization) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en; + if (dqsq_min == dqsq_max) begin + dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; + end else begin + dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; + end + end + end + end + end else begin + if (dll_en) + if(diff_ck) + out_delay = ($rtoi(tch_avg) > 50000) ? 0 : $rtoi(tch_avg); + else + out_delay = ($rtoi(tcl_avg) > 50000) ? 0 : $rtoi(tcl_avg); + else + if(diff_ck) + out_delay = ($rtoi(tch_avg) > 50000) ? 0 : $rtoi(tch_avg) + TDQSCK_DLLDIS; + else + out_delay = ($rtoi(tcl_avg) > 50000) ? 0 : $rtoi(tcl_avg) + TDQSCK_DLLDIS; + dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; + dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; + if (write_levelization !== 1'b1) begin + dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; + dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; + end + end + end + endtask + + always @ (posedge rst_n_in) begin : reset + integer i; + if (rst_n_in) begin + if ($time < 200000000 && check_strict_timing) + $display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time); + if (cke_in !== 1'b0) + $display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time); + if ($time - tm_cke < 10000) + $display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time); + + // clear memory +`ifdef MAX_MEM + // verification group does not erase memory + // for (banki = 0; banki < `BANKS; banki = banki + 1) begin + // $fclose(memfd[banki]); + // memfd[banki] = open_bank_file(banki); + // end +`else + memory_used <= 0; //erase memory +`endif + + end + end + + always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main + integer i; + if (!rst_n_in) begin + reset_task; + end else begin + if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) + $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); + data_task; + + // Clock Frequency Change is legal: + // 1.) During Self Refresh + // 2.) During Precharge Power Down (DLL on or off) + if (in_self_refresh || (in_power_down && (active_bank == 0))) begin + if (diff_ck) begin + tjit_per_rtime = $time - tm_ck_pos - tck_avg; + end else begin + tjit_per_rtime = $time - tm_ck_neg - tck_avg; + end + if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin + if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK)) + $display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time); + if (odt_state) begin + $display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time); + tm_freq_change <= $time; + ck_freq_change <= ck_cntr; + dll_locked = 0; + end + end + end + + if (diff_ck) begin + // check setup of command signals + if ($time > TIS) begin + if ($time - tm_cke < TIS) + $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); + if (cke_in) begin + for (i=0; i<23; i=i+1) begin + if ($time - tm_cmd_addr[i] < TIS) + $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); + end + end + end + + // update current state + if (dll_locked) begin + if (mr_chk == 0) begin + mr_chk = 1; + end else if (init_mode_reg[0] && (mr_chk == 1)) begin + // check CL value against the clock frequency + // check WR value against the clock frequency + if (ceil(write_recovery*tck_avg) < TWR) + $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); + // check the CWL value against the clock frequency + if (check_strict_timing) begin + case (cas_write_latency) + 5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + endcase + // check the CL value against the clock frequency + if (!valid_cl(cas_latency, cas_write_latency)) + $display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency); + end + mr_chk = 2; + end + end else if (!in_self_refresh) begin + mr_chk = 0; + if (ck_cntr - ck_dll_reset == TDLLK) begin + dll_locked = 1; + end + end + + if (|auto_precharge_bank) begin + for (i=0; i<`BANKS; i=i+1) begin + // Write with Auto Precharge Calculation + // 1. Meet minimum tRAS requirement + // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command + if (write_precharge_bank[i]) begin + if ($time - tm_bank_activate[i] >= TRAS_MIN) begin + if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); + write_precharge_bank[i] = 0; + active_bank[i] = 0; + auto_precharge_bank[i] = 0; + tm_bank_precharge[i] = $time; + tm_precharge = $time; + ck_precharge = ck_cntr; + end + end + end + // Read with Auto Precharge Calculation + // 1. Meet minimum tRAS requirement + // 2. Additive Latency plus 4 cycles after Read command + // 3. tRTP after the last 8-bit prefetch + if (read_precharge_bank[i]) begin + if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin + read_precharge_bank[i] = 0; + // In case the internal precharge is pushed out by tRTP, tRP starts at the point where + // the internal precharge happens (not at the next rising clock edge after this event). + if ($time - tm_bank_read_end[i] < TRTP) begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); + active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; + auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; + tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; + tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; + ck_precharge = ck_cntr; + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); + active_bank[i] = 0; + auto_precharge_bank[i] = 0; + tm_bank_precharge[i] = $time; + tm_precharge = $time; + ck_precharge = ck_cntr; + end + end + end + end + end + + + // respond to incoming command + if (cke_in ^ prev_cke) begin + tm_cke_cmd <= $time; + ck_cke_cmd <= ck_cntr; + end + + + cmd_task(prev_cke, cke_in, cmd_n_in, ba_in, addr_in); + if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin + al_pipeline[2*additive_latency] = 1'b1; + end + if (al_pipeline[0]) begin + // check tRCD after additive latency + if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD)) + $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); + if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD)) + $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); + // check tWTR after additive latency + if (rd_pipeline[2*cas_latency - 1]) begin //{ + if (truebl4) begin //{ + i = ba_pipeline[2*cas_latency - 1]; + if ($time - tm_group_write_end[i[1]] < TWTR) + $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); + if ($time - tm_write_end < TWTR_DG) + $display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]); + end else begin + if ($time - tm_write_end < TWTR) + $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); + end + end + end + if (rd_pipeline) begin + if (rd_pipeline[2*cas_latency - 1]) begin + tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time; + end + end + for (i=0; i<`BANKS; i=i+1) begin + if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin + tm_bank_write_end[i] <= $time; + tm_group_write_end[i[1]] <= $time; + tm_write_end <= $time; + end + end + + // clk pin is disabled during self refresh + if (!in_self_refresh && tm_ck_pos ) begin + tjit_cc_time = $time - tm_ck_pos - tck_i; + tck_i = $time - tm_ck_pos; + tck_avg = tck_avg - tck_sample[ck_cntr%PERTCKAVG]/$itor(PERTCKAVG); + tck_avg = tck_avg + tck_i/$itor(PERTCKAVG); + tck_sample[ck_cntr%PERTCKAVG] = tck_i; + tjit_per_rtime = tck_i - tck_avg; + + if (dll_locked && check_strict_timing) begin + // check accumulated error + terr_nper_rtime = 0; + for (i=0; i<12; i=i+1) begin + terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; + terr_nper_rtime = abs_value(terr_nper_rtime); + case (i) + 0 :; + 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); + 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); + 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); + 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); + 5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER); + 6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER); + 7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER); + 8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER); + 9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER); + 10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER); + 11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER); + endcase + end + + // check tCK min/max/jitter + if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) + $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); + if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) + $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); + if (TCK_MIN - tck_avg >= 1.0) + $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); + if (tck_avg - TCK_MAX >= 1.0) + $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); + + // check tCL + if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time); + if (tcl_avg < TCL_AVG_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg); + if (tcl_avg > TCL_AVG_MAX*tck_avg) + $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg); + end + + // calculate the tch avg jitter + tch_avg = tch_avg - tch_sample[ck_cntr%PERTCKAVG]/$itor(PERTCKAVG); + tch_avg = tch_avg + tch_i/$itor(PERTCKAVG); + tch_sample[ck_cntr%PERTCKAVG] = tch_i; + tjit_ch_rtime = tch_i - tch_avg; + duty_cycle = $rtoi(tch_avg*100/tck_avg); + + // update timers/counters + tcl_i <= $time - tm_ck_neg; + end + + prev_odt <= odt_in; + // update timers/counters + ck_cntr <= ck_cntr + 1; + tm_ck_pos = $time; + end else begin + // clk pin is disabled during self refresh + if (!in_self_refresh) begin + if (dll_locked && check_strict_timing) begin + if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos); + if (tch_avg < TCH_AVG_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg); + if (tch_avg > TCH_AVG_MAX*tck_avg) + $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg); + end + + // calculate the tcl avg jitter + tcl_avg = tcl_avg - tcl_sample[ck_cntr%PERTCKAVG]/$itor(PERTCKAVG); + tcl_avg = tcl_avg + tcl_i/$itor(PERTCKAVG); + tcl_sample[ck_cntr%PERTCKAVG] = tcl_i; + + // update timers/counters + tch_i <= $time - tm_ck_pos; + end + tm_ck_neg = $time; + end + + // on die termination + if (odt_en || dyn_odt_en) begin + // odt pin is disabled during self refresh + if (!in_self_refresh && diff_ck) begin + if ($time - tm_odt < TIS) + $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); + if (prev_odt ^ odt_in) begin + if (!dll_locked) + $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); + if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) + $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); + if (ck_cntr - ck_zqinit < TZQINIT) + $display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time); + if (ck_cntr - ck_zqoper < TZQOPER) + $display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time); + if (ck_cntr - ck_zqcs < TZQCS) + $display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time); + // if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) + // $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time); + if (ck_cntr - ck_self_refresh < TXSDLL) + $display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time); + if (in_self_refresh) + $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); + if (!odt_in && (ck_cntr - ck_odt < ODTH4)) + $display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time); + if (!odt_in && (ck_cntr - ck_odth8 < ODTH8)) + $display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time); + if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) + $display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); + + // async ODT mode applies: + // 1.) during precharge power down with DLL off + // 2.) if tANPD has not been satisfied + // 3.) until tXPDLL has been satisfied + if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin + odt_state = odt_in; + if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); + if (odt_state) begin + odt_state_dly <= #(TAONPD) odt_state; + end else begin + odt_state_dly <= #(TAOFPD) odt_state; + end + // sync ODT mode applies: + // 1.) during normal operation + // 2.) during active power down + // 3.) during precharge power down with DLL on + end else begin + odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff + end + ck_odt <= ck_cntr; + end + end + if (odt_pipeline[0]) begin + odt_state = ~odt_state; + if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); + if (odt_state) begin + odt_state_dly <= #(TAON) odt_state; + end else begin + odt_state_dly <= #(TAOF*tck_avg) odt_state; + end + end + if (rd_pipeline[RDQSEN_PRE]) begin + odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; + end + if (odt_cntr > 0) begin + if ((get_rtt_nom(odt_rtt_nom) > 0) && odt_state) begin + $display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time); + end + odt_cntr = odt_cntr - 1; + end + if (dyn_odt_en && ( odt_state || feature_odt_hi) ) begin + if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0])) + $display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr)); + dyn_odt_state = dyn_odt_pipeline[0]; + end + dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state; + end + + if (cke_in && write_levelization) begin + for (i=0; i>1; + wr_pipeline = wr_pipeline>>1; + rd_pipeline = rd_pipeline>>1; + for (i=0; i<`MAX_PIPE; i=i+1) begin + bl_pipeline[i] = bl_pipeline[i+1]; + ba_pipeline[i] = ba_pipeline[i+1]; + row_pipeline[i] = row_pipeline[i+1]; + col_pipeline[i] = col_pipeline[i+1]; + end + end + if (|odt_pipeline || |dyn_odt_pipeline) begin + odt_pipeline = odt_pipeline>>1; + dyn_odt_pipeline = dyn_odt_pipeline>>1; + end + end + end + + // receiver(s) + task dqs_even_receiver; + input [4:0] i; + reg [127:0] bit_mask; + begin + bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); + if (dqs_even[i]) begin + if (tdqs_en) begin // tdqs disables dm + dm_in_pos[i] = 1'b0; + end else begin + dm_in_pos[i] = dm_in[i]; + end + dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); + end + end + endtask + + always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); + always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); + always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); + always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); + always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); + always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); + always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); + always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); + always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); + always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); + always @(posedge dqs_even[10]) dqs_even_receiver(10); + always @(posedge dqs_even[11]) dqs_even_receiver(11); + always @(posedge dqs_even[12]) dqs_even_receiver(12); + always @(posedge dqs_even[13]) dqs_even_receiver(13); + always @(posedge dqs_even[14]) dqs_even_receiver(14); + always @(posedge dqs_even[15]) dqs_even_receiver(15); + + task dqs_odd_receiver; + input [4:0] i; + reg [127:0] bit_mask; + begin + bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); + if (dqs_odd[i]) begin + if (tdqs_en) begin // tdqs disables dm + dm_in_neg[i] = 1'b0; + end else begin + dm_in_neg[i] = dm_in[i]; + end + dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); + end + end + endtask + + always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); + always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); + always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); + always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); + always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); + always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); + always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); + always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); + always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); + always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); + always @(posedge dqs_odd[10]) dqs_odd_receiver(10); + always @(posedge dqs_odd[11]) dqs_odd_receiver(11); + always @(posedge dqs_odd[12]) dqs_odd_receiver(12); + always @(posedge dqs_odd[13]) dqs_odd_receiver(13); + always @(posedge dqs_odd[14]) dqs_odd_receiver(14); + always @(posedge dqs_odd[15]) dqs_odd_receiver(15); + + // Processes to check hold and pulse width of control signals + always @(posedge rst_n_in) begin + if ($time > 100000) begin + if (tm_rst_n + 100000 > $time) + $display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time); + end + tm_rst_n = $time; + end + always @(cke_in) begin + if (rst_n_in) begin + if ($time > TIH) begin + if ($time - tm_ck_pos < TIH) + $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); + end + if ($time - tm_cke < TIPW) + $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time); + end + tm_cke = $time; + end + always @(odt_in) begin + if (rst_n_in && odt_en && !in_self_refresh) begin + if ($time - tm_ck_pos < TIH) + $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); + if ($time - tm_odt < TIPW) + $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time); + end + tm_odt = $time; + end + + task cmd_addr_timing_check; + input i; + reg [4:0] i; + begin + if (rst_n_in && prev_cke) begin + if ((i == 0) && ($time - tm_ck_pos < TIH)) // always check tIH for CS# + $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); + if ((i > 0) && (cs_n_in == 0) &&($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# is low + $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); + if ((i == 0) && ($time - tm_cmd_addr[i] < TIPW)) // always check tIPW for CS# + $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time); + if ((i > 0) && (cs_n_in == 0) && ($time - tm_cmd_addr[i] < TIPW)) + $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time); + end + tm_cmd_addr[i] = $time; + end + endtask + + always @(cs_n_in ) cmd_addr_timing_check( 0); + always @(ras_n_in ) cmd_addr_timing_check( 1); + always @(cas_n_in ) cmd_addr_timing_check( 2); + always @(we_n_in ) cmd_addr_timing_check( 3); + always @(ba_in [ 0]) cmd_addr_timing_check( 4); + always @(ba_in [ 1]) cmd_addr_timing_check( 5); + always @(ba_in [ 2]) cmd_addr_timing_check( 6); + always @(addr_in[ 0]) cmd_addr_timing_check( 7); + always @(addr_in[ 1]) cmd_addr_timing_check( 8); + always @(addr_in[ 2]) cmd_addr_timing_check( 9); + always @(addr_in[ 3]) cmd_addr_timing_check(10); + always @(addr_in[ 4]) cmd_addr_timing_check(11); + always @(addr_in[ 5]) cmd_addr_timing_check(12); + always @(addr_in[ 6]) cmd_addr_timing_check(13); + always @(addr_in[ 7]) cmd_addr_timing_check(14); + always @(addr_in[ 8]) cmd_addr_timing_check(15); + always @(addr_in[ 9]) cmd_addr_timing_check(16); + always @(addr_in[10]) cmd_addr_timing_check(17); + always @(addr_in[11]) cmd_addr_timing_check(18); + always @(addr_in[12]) cmd_addr_timing_check(19); + always @(addr_in[13]) cmd_addr_timing_check(20); + always @(addr_in[14]) cmd_addr_timing_check(21); + always @(addr_in[15]) cmd_addr_timing_check(22); + always @(addr_in[16]) cmd_addr_timing_check(23); + + // Processes to check setup and hold of data signals + task dm_timing_check; + input i; + reg [4:0] i; + begin + if (dqs_in_valid) begin + if ($time - tm_dqs[i] < TDH) + $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); + if (check_dm_tdipw[i]) begin + if ($time - tm_dm[i] < TDIPW) + $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time); + end + end + check_dm_tdipw[i] <= 1'b0; + tm_dm[i] = $time; + end + endtask + + always @(dm_in[ 0]) dm_timing_check( 0); + always @(dm_in[ 1]) dm_timing_check( 1); + always @(dm_in[ 2]) dm_timing_check( 2); + always @(dm_in[ 3]) dm_timing_check( 3); + always @(dm_in[ 4]) dm_timing_check( 4); + always @(dm_in[ 5]) dm_timing_check( 5); + always @(dm_in[ 6]) dm_timing_check( 6); + always @(dm_in[ 7]) dm_timing_check( 7); + always @(dm_in[ 8]) dm_timing_check( 8); + always @(dm_in[ 9]) dm_timing_check( 9); + always @(dm_in[10]) dm_timing_check(10); + always @(dm_in[11]) dm_timing_check(11); + always @(dm_in[12]) dm_timing_check(12); + always @(dm_in[13]) dm_timing_check(13); + always @(dm_in[14]) dm_timing_check(14); + always @(dm_in[15]) dm_timing_check(15); + + always @(dm_in[16]) dm_timing_check(16); + always @(dm_in[17]) dm_timing_check(17); + always @(dm_in[18]) dm_timing_check(18); + always @(dm_in[19]) dm_timing_check(19); + always @(dm_in[20]) dm_timing_check(20); + always @(dm_in[21]) dm_timing_check(21); + always @(dm_in[22]) dm_timing_check(22); + always @(dm_in[23]) dm_timing_check(23); + always @(dm_in[24]) dm_timing_check(24); + always @(dm_in[25]) dm_timing_check(25); + always @(dm_in[26]) dm_timing_check(26); + always @(dm_in[27]) dm_timing_check(27); + always @(dm_in[28]) dm_timing_check(28); + always @(dm_in[29]) dm_timing_check(29); + always @(dm_in[30]) dm_timing_check(30); + always @(dm_in[31]) dm_timing_check(31); + + task dq_timing_check; + input i; + reg [6:0] i; + begin + if (dqs_in_valid) begin + if ($time - tm_dqs[i/(`DQ_PER_DQS)] < TDH) + $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); + if (check_dq_tdipw[i]) begin + if ($time - tm_dq[i] < TDIPW) + $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time); + end + end + check_dq_tdipw[i] <= 1'b0; + tm_dq[i] = $time; + end + endtask + + always @(dq_in[ 0]) dq_timing_check( 0); + always @(dq_in[ 1]) dq_timing_check( 1); + always @(dq_in[ 2]) dq_timing_check( 2); + always @(dq_in[ 3]) dq_timing_check( 3); + always @(dq_in[ 4]) dq_timing_check( 4); + always @(dq_in[ 5]) dq_timing_check( 5); + always @(dq_in[ 6]) dq_timing_check( 6); + always @(dq_in[ 7]) dq_timing_check( 7); + always @(dq_in[ 8]) dq_timing_check( 8); + always @(dq_in[ 9]) dq_timing_check( 9); + always @(dq_in[10]) dq_timing_check(10); + always @(dq_in[11]) dq_timing_check(11); + always @(dq_in[12]) dq_timing_check(12); + always @(dq_in[13]) dq_timing_check(13); + always @(dq_in[14]) dq_timing_check(14); + always @(dq_in[15]) dq_timing_check(15); + always @(dq_in[16]) dq_timing_check(16); + always @(dq_in[17]) dq_timing_check(17); + always @(dq_in[18]) dq_timing_check(18); + always @(dq_in[19]) dq_timing_check(19); + always @(dq_in[20]) dq_timing_check(20); + always @(dq_in[21]) dq_timing_check(21); + always @(dq_in[22]) dq_timing_check(22); + always @(dq_in[23]) dq_timing_check(23); + always @(dq_in[24]) dq_timing_check(24); + always @(dq_in[25]) dq_timing_check(25); + always @(dq_in[26]) dq_timing_check(26); + always @(dq_in[27]) dq_timing_check(27); + always @(dq_in[28]) dq_timing_check(28); + always @(dq_in[29]) dq_timing_check(29); + always @(dq_in[30]) dq_timing_check(30); + always @(dq_in[31]) dq_timing_check(31); + always @(dq_in[32]) dq_timing_check(32); + always @(dq_in[33]) dq_timing_check(33); + always @(dq_in[34]) dq_timing_check(34); + always @(dq_in[35]) dq_timing_check(35); + always @(dq_in[36]) dq_timing_check(36); + always @(dq_in[37]) dq_timing_check(37); + always @(dq_in[38]) dq_timing_check(38); + always @(dq_in[39]) dq_timing_check(39); + always @(dq_in[40]) dq_timing_check(40); + always @(dq_in[41]) dq_timing_check(41); + always @(dq_in[42]) dq_timing_check(42); + always @(dq_in[43]) dq_timing_check(43); + always @(dq_in[44]) dq_timing_check(44); + always @(dq_in[45]) dq_timing_check(45); + always @(dq_in[46]) dq_timing_check(46); + always @(dq_in[47]) dq_timing_check(47); + always @(dq_in[48]) dq_timing_check(48); + always @(dq_in[49]) dq_timing_check(49); + always @(dq_in[50]) dq_timing_check(50); + always @(dq_in[51]) dq_timing_check(51); + always @(dq_in[52]) dq_timing_check(52); + always @(dq_in[53]) dq_timing_check(53); + always @(dq_in[54]) dq_timing_check(54); + always @(dq_in[55]) dq_timing_check(55); + always @(dq_in[56]) dq_timing_check(56); + always @(dq_in[57]) dq_timing_check(57); + always @(dq_in[58]) dq_timing_check(58); + always @(dq_in[59]) dq_timing_check(59); + always @(dq_in[60]) dq_timing_check(60); + always @(dq_in[61]) dq_timing_check(61); + always @(dq_in[62]) dq_timing_check(62); + always @(dq_in[63]) dq_timing_check(63); + + always @(dq_in[64]) dq_timing_check(64); + always @(dq_in[65]) dq_timing_check(65); + always @(dq_in[66]) dq_timing_check(66); + always @(dq_in[67]) dq_timing_check(67); + always @(dq_in[68]) dq_timing_check(68); + always @(dq_in[69]) dq_timing_check(69); + always @(dq_in[70]) dq_timing_check(70); + always @(dq_in[71]) dq_timing_check(71); + always @(dq_in[72]) dq_timing_check(72); + always @(dq_in[73]) dq_timing_check(73); + always @(dq_in[74]) dq_timing_check(74); + always @(dq_in[75]) dq_timing_check(75); + always @(dq_in[76]) dq_timing_check(76); + always @(dq_in[77]) dq_timing_check(77); + always @(dq_in[78]) dq_timing_check(78); + always @(dq_in[79]) dq_timing_check(79); + always @(dq_in[80]) dq_timing_check(80); + always @(dq_in[81]) dq_timing_check(81); + always @(dq_in[82]) dq_timing_check(82); + always @(dq_in[83]) dq_timing_check(83); + always @(dq_in[84]) dq_timing_check(84); + always @(dq_in[85]) dq_timing_check(85); + always @(dq_in[86]) dq_timing_check(86); + always @(dq_in[87]) dq_timing_check(87); + always @(dq_in[88]) dq_timing_check(88); + always @(dq_in[89]) dq_timing_check(89); + always @(dq_in[90]) dq_timing_check(90); + always @(dq_in[91]) dq_timing_check(91); + always @(dq_in[92]) dq_timing_check(92); + always @(dq_in[93]) dq_timing_check(93); + always @(dq_in[94]) dq_timing_check(94); + always @(dq_in[95]) dq_timing_check(95); + always @(dq_in[96]) dq_timing_check(96); + always @(dq_in[97]) dq_timing_check(97); + always @(dq_in[98]) dq_timing_check(98); + always @(dq_in[99]) dq_timing_check(99); + always @(dq_in[100]) dq_timing_check(100); + always @(dq_in[101]) dq_timing_check(101); + always @(dq_in[102]) dq_timing_check(102); + always @(dq_in[103]) dq_timing_check(103); + always @(dq_in[104]) dq_timing_check(104); + always @(dq_in[105]) dq_timing_check(105); + always @(dq_in[106]) dq_timing_check(106); + always @(dq_in[107]) dq_timing_check(107); + always @(dq_in[108]) dq_timing_check(108); + always @(dq_in[109]) dq_timing_check(109); + always @(dq_in[110]) dq_timing_check(110); + always @(dq_in[111]) dq_timing_check(111); + always @(dq_in[112]) dq_timing_check(112); + always @(dq_in[113]) dq_timing_check(113); + always @(dq_in[114]) dq_timing_check(114); + always @(dq_in[115]) dq_timing_check(115); + always @(dq_in[116]) dq_timing_check(116); + always @(dq_in[117]) dq_timing_check(117); + always @(dq_in[118]) dq_timing_check(118); + always @(dq_in[119]) dq_timing_check(119); + always @(dq_in[120]) dq_timing_check(120); + always @(dq_in[121]) dq_timing_check(121); + always @(dq_in[122]) dq_timing_check(122); + always @(dq_in[123]) dq_timing_check(123); + always @(dq_in[124]) dq_timing_check(124); + always @(dq_in[125]) dq_timing_check(125); + always @(dq_in[126]) dq_timing_check(126); + always @(dq_in[127]) dq_timing_check(127); + + task dqs_pos_timing_check; + input i; + reg [5:0] i; + reg [4:0] j; + begin + if (write_levelization && i<32) begin + if (ck_cntr - ck_load_mode < TWLMRD) + $display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i); + if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS)) + $display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i); + if (DEBUG) + $display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck); + dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1; + dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck; +`ifdef WL_ALLDQ + for (j=1; j<`DQ_PER_DQS; j=j+1) begin + dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO) 1'b1; + dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO) diff_ck; + end +`else + for (j=1; j<`DQ_PER_DQS; j=j+1) begin + dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1; + dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0; + end +`endif + end + if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin + if (dqs_in[i] ^ prev_dqs_in[i]) begin + if (dll_locked) begin + if (check_write_preamble[i]) begin + if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg)) + $display ("%m: at time %t ERROR: tWPRE violation on %s bit %d", $time, dqs_string[i/32], i%32); + end else if (check_write_postamble[i]) begin + if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) + $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/32], i%32); + end else begin + if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) + $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/32], i%32); + end + end + if ($time - tm_dm[i%32] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%32] + TDS - $time); + if (!dq_out_en) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + if ($time - tm_dq[(i%32)*`DQ_PER_DQS+j] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%32)*`DQ_PER_DQS+j] + TDS - $time); + check_dq_tdipw[(i%32)*`DQ_PER_DQS+j] <= 1'b1; + end + end + if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin + wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; + end else begin + wdqs_pos_cntr[i] <= 1; + end + check_dm_tdipw[i%32] <= 1'b1; + check_write_preamble[i] <= 1'b0; + check_write_postamble[i] <= 1'b0; + check_write_dqs_low[i] <= 1'b0; + tm_dqs[i%32] <= $time; + end else begin + $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/32], i%32); + end + end + tm_dqss_pos[i] <= $time; + tm_dqs_pos[i] = $time; + prev_dqs_in[i] <= dqs_in[i]; + end + endtask + + always @(posedge dqs_in[ 0]) if ( dqs_in[ 0]) dqs_pos_timing_check( 0); + always @(posedge dqs_in[ 1]) if ( dqs_in[ 1]) dqs_pos_timing_check( 1); + always @(posedge dqs_in[ 2]) if ( dqs_in[ 2]) dqs_pos_timing_check( 2); + always @(posedge dqs_in[ 3]) if ( dqs_in[ 3]) dqs_pos_timing_check( 3); + always @(posedge dqs_in[ 4]) if ( dqs_in[ 4]) dqs_pos_timing_check( 4); + always @(posedge dqs_in[ 5]) if ( dqs_in[ 5]) dqs_pos_timing_check( 5); + always @(posedge dqs_in[ 6]) if ( dqs_in[ 6]) dqs_pos_timing_check( 6); + always @(posedge dqs_in[ 7]) if ( dqs_in[ 7]) dqs_pos_timing_check( 7); + always @(posedge dqs_in[ 8]) if ( dqs_in[ 8]) dqs_pos_timing_check( 8); + always @(posedge dqs_in[ 9]) if ( dqs_in[ 9]) dqs_pos_timing_check( 9); + always @(posedge dqs_in[10]) if ( dqs_in[10]) dqs_pos_timing_check(10); + always @(posedge dqs_in[11]) if ( dqs_in[11]) dqs_pos_timing_check(11); + always @(posedge dqs_in[12]) if ( dqs_in[12]) dqs_pos_timing_check(12); + always @(posedge dqs_in[13]) if ( dqs_in[13]) dqs_pos_timing_check(13); + always @(posedge dqs_in[14]) if ( dqs_in[14]) dqs_pos_timing_check(14); + always @(posedge dqs_in[15]) if ( dqs_in[15]) dqs_pos_timing_check(15); + always @(posedge dqs_in[16]) if ( dqs_in[16]) dqs_pos_timing_check(16); + always @(posedge dqs_in[17]) if ( dqs_in[17]) dqs_pos_timing_check(17); + always @(posedge dqs_in[18]) if ( dqs_in[18]) dqs_pos_timing_check(18); + always @(posedge dqs_in[19]) if ( dqs_in[19]) dqs_pos_timing_check(19); + always @(posedge dqs_in[20]) if ( dqs_in[20]) dqs_pos_timing_check(20); + always @(posedge dqs_in[21]) if ( dqs_in[21]) dqs_pos_timing_check(21); + always @(posedge dqs_in[22]) if ( dqs_in[22]) dqs_pos_timing_check(22); + always @(posedge dqs_in[23]) if ( dqs_in[23]) dqs_pos_timing_check(23); + always @(posedge dqs_in[24]) if ( dqs_in[24]) dqs_pos_timing_check(24); + always @(posedge dqs_in[25]) if ( dqs_in[25]) dqs_pos_timing_check(25); + always @(posedge dqs_in[26]) if ( dqs_in[26]) dqs_pos_timing_check(26); + always @(posedge dqs_in[27]) if ( dqs_in[27]) dqs_pos_timing_check(27); + always @(posedge dqs_in[28]) if ( dqs_in[28]) dqs_pos_timing_check(28); + always @(posedge dqs_in[29]) if ( dqs_in[29]) dqs_pos_timing_check(29); + always @(posedge dqs_in[30]) if ( dqs_in[30]) dqs_pos_timing_check(30); + always @(posedge dqs_in[31]) if ( dqs_in[31]) dqs_pos_timing_check(31); + + always @(negedge dqs_in[32]) if (!dqs_in[32]) dqs_pos_timing_check(32); + always @(negedge dqs_in[33]) if (!dqs_in[33]) dqs_pos_timing_check(33); + always @(negedge dqs_in[34]) if (!dqs_in[34]) dqs_pos_timing_check(34); + always @(negedge dqs_in[35]) if (!dqs_in[35]) dqs_pos_timing_check(35); + always @(negedge dqs_in[36]) if (!dqs_in[36]) dqs_pos_timing_check(36); + always @(negedge dqs_in[37]) if (!dqs_in[37]) dqs_pos_timing_check(37); + always @(negedge dqs_in[38]) if (!dqs_in[38]) dqs_pos_timing_check(38); + always @(negedge dqs_in[39]) if (!dqs_in[39]) dqs_pos_timing_check(39); + always @(negedge dqs_in[40]) if (!dqs_in[40]) dqs_pos_timing_check(40); + always @(negedge dqs_in[41]) if (!dqs_in[41]) dqs_pos_timing_check(41); + always @(negedge dqs_in[42]) if (!dqs_in[42]) dqs_pos_timing_check(42); + always @(negedge dqs_in[43]) if (!dqs_in[43]) dqs_pos_timing_check(43); + always @(negedge dqs_in[44]) if (!dqs_in[44]) dqs_pos_timing_check(44); + always @(negedge dqs_in[45]) if (!dqs_in[45]) dqs_pos_timing_check(45); + always @(negedge dqs_in[46]) if (!dqs_in[46]) dqs_pos_timing_check(46); + always @(negedge dqs_in[47]) if (!dqs_in[47]) dqs_pos_timing_check(47); + always @(negedge dqs_in[48]) if (!dqs_in[48]) dqs_pos_timing_check(48); + always @(negedge dqs_in[49]) if (!dqs_in[49]) dqs_pos_timing_check(49); + always @(negedge dqs_in[50]) if (!dqs_in[50]) dqs_pos_timing_check(50); + always @(negedge dqs_in[51]) if (!dqs_in[51]) dqs_pos_timing_check(51); + always @(negedge dqs_in[52]) if (!dqs_in[52]) dqs_pos_timing_check(52); + always @(negedge dqs_in[53]) if (!dqs_in[53]) dqs_pos_timing_check(53); + always @(negedge dqs_in[54]) if (!dqs_in[54]) dqs_pos_timing_check(54); + always @(negedge dqs_in[55]) if (!dqs_in[55]) dqs_pos_timing_check(55); + always @(negedge dqs_in[56]) if (!dqs_in[56]) dqs_pos_timing_check(56); + always @(negedge dqs_in[57]) if (!dqs_in[57]) dqs_pos_timing_check(57); + always @(negedge dqs_in[58]) if (!dqs_in[58]) dqs_pos_timing_check(58); + always @(negedge dqs_in[59]) if (!dqs_in[59]) dqs_pos_timing_check(59); + always @(negedge dqs_in[60]) if (!dqs_in[60]) dqs_pos_timing_check(60); + always @(negedge dqs_in[61]) if (!dqs_in[61]) dqs_pos_timing_check(61); + always @(negedge dqs_in[62]) if (!dqs_in[62]) dqs_pos_timing_check(62); + always @(negedge dqs_in[63]) if (!dqs_in[63]) dqs_pos_timing_check(63); + + task dqs_neg_timing_check; + input i; + reg [5:0] i; + reg [4:0] j; + begin + if (write_levelization && i<32) begin + if (ck_cntr - ck_load_mode < TWLDQSEN) + $display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i); + if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) + $display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time); + end + if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin + if (dqs_in[i] ^ prev_dqs_in[i]) begin + if (dll_locked) begin + if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) + $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/32], i%32); + if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) + $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/32], i%32); + end + if ($time - tm_dm[i%32] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%32] + TDS - $time); + if (!dq_out_en) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + if ($time - tm_dq[(i%32)*`DQ_PER_DQS+j] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%32)*`DQ_PER_DQS+j] + TDS - $time); + check_dq_tdipw[(i%32)*`DQ_PER_DQS+j] <= 1'b1; + end + end + check_dm_tdipw[i%32] <= 1'b1; + tm_dqs[i%32] <= $time; + end else begin + $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/32], i%32); + end + end + check_write_dqs_high[i] <= 1'b0; + tm_dqs_neg[i] = $time; + prev_dqs_in[i] <= dqs_in[i]; + end + endtask + + always @(negedge dqs_in[ 0]) if (!dqs_in[ 0]) dqs_neg_timing_check( 0); + always @(negedge dqs_in[ 1]) if (!dqs_in[ 1]) dqs_neg_timing_check( 1); + always @(negedge dqs_in[ 2]) if (!dqs_in[ 2]) dqs_neg_timing_check( 2); + always @(negedge dqs_in[ 3]) if (!dqs_in[ 3]) dqs_neg_timing_check( 3); + always @(negedge dqs_in[ 4]) if (!dqs_in[ 4]) dqs_neg_timing_check( 4); + always @(negedge dqs_in[ 5]) if (!dqs_in[ 5]) dqs_neg_timing_check( 5); + always @(negedge dqs_in[ 6]) if (!dqs_in[ 6]) dqs_neg_timing_check( 6); + always @(negedge dqs_in[ 7]) if (!dqs_in[ 7]) dqs_neg_timing_check( 7); + always @(negedge dqs_in[ 8]) if (!dqs_in[ 8]) dqs_neg_timing_check( 8); + always @(negedge dqs_in[ 9]) if (!dqs_in[ 9]) dqs_neg_timing_check( 9); + always @(negedge dqs_in[10]) if (!dqs_in[10]) dqs_neg_timing_check(10); + always @(negedge dqs_in[11]) if (!dqs_in[11]) dqs_neg_timing_check(11); + always @(negedge dqs_in[12]) if (!dqs_in[12]) dqs_neg_timing_check(12); + always @(negedge dqs_in[13]) if (!dqs_in[13]) dqs_neg_timing_check(13); + always @(negedge dqs_in[14]) if (!dqs_in[14]) dqs_neg_timing_check(14); + always @(negedge dqs_in[15]) if (!dqs_in[15]) dqs_neg_timing_check(15); + always @(negedge dqs_in[16]) if (!dqs_in[16]) dqs_neg_timing_check(16); + always @(negedge dqs_in[17]) if (!dqs_in[17]) dqs_neg_timing_check(17); + always @(negedge dqs_in[18]) if (!dqs_in[18]) dqs_neg_timing_check(18); + always @(negedge dqs_in[19]) if (!dqs_in[19]) dqs_neg_timing_check(19); + always @(negedge dqs_in[20]) if (!dqs_in[20]) dqs_neg_timing_check(20); + always @(negedge dqs_in[21]) if (!dqs_in[21]) dqs_neg_timing_check(21); + always @(negedge dqs_in[22]) if (!dqs_in[22]) dqs_neg_timing_check(22); + always @(negedge dqs_in[23]) if (!dqs_in[23]) dqs_neg_timing_check(23); + always @(negedge dqs_in[24]) if (!dqs_in[24]) dqs_neg_timing_check(24); + always @(negedge dqs_in[25]) if (!dqs_in[25]) dqs_neg_timing_check(25); + always @(negedge dqs_in[26]) if (!dqs_in[26]) dqs_neg_timing_check(26); + always @(negedge dqs_in[27]) if (!dqs_in[27]) dqs_neg_timing_check(27); + always @(negedge dqs_in[28]) if (!dqs_in[28]) dqs_neg_timing_check(28); + always @(negedge dqs_in[29]) if (!dqs_in[29]) dqs_neg_timing_check(29); + always @(negedge dqs_in[30]) if (!dqs_in[30]) dqs_neg_timing_check(30); + always @(negedge dqs_in[31]) if (!dqs_in[31]) dqs_neg_timing_check(31); + + always @(posedge dqs_in[32]) if ( dqs_in[32]) dqs_neg_timing_check(32); + always @(posedge dqs_in[33]) if ( dqs_in[33]) dqs_neg_timing_check(33); + always @(posedge dqs_in[34]) if ( dqs_in[34]) dqs_neg_timing_check(34); + always @(posedge dqs_in[35]) if ( dqs_in[35]) dqs_neg_timing_check(35); + always @(posedge dqs_in[36]) if ( dqs_in[36]) dqs_neg_timing_check(36); + always @(posedge dqs_in[37]) if ( dqs_in[37]) dqs_neg_timing_check(37); + always @(posedge dqs_in[38]) if ( dqs_in[38]) dqs_neg_timing_check(38); + always @(posedge dqs_in[39]) if ( dqs_in[39]) dqs_neg_timing_check(39); + always @(posedge dqs_in[40]) if ( dqs_in[40]) dqs_neg_timing_check(40); + always @(posedge dqs_in[41]) if ( dqs_in[41]) dqs_neg_timing_check(41); + always @(posedge dqs_in[42]) if ( dqs_in[42]) dqs_neg_timing_check(42); + always @(posedge dqs_in[43]) if ( dqs_in[43]) dqs_neg_timing_check(43); + always @(posedge dqs_in[44]) if ( dqs_in[44]) dqs_neg_timing_check(44); + always @(posedge dqs_in[45]) if ( dqs_in[45]) dqs_neg_timing_check(45); + always @(posedge dqs_in[46]) if ( dqs_in[46]) dqs_neg_timing_check(46); + always @(posedge dqs_in[47]) if ( dqs_in[47]) dqs_neg_timing_check(47); + always @(posedge dqs_in[48]) if ( dqs_in[48]) dqs_neg_timing_check(48); + always @(posedge dqs_in[49]) if ( dqs_in[49]) dqs_neg_timing_check(49); + always @(posedge dqs_in[50]) if ( dqs_in[50]) dqs_neg_timing_check(50); + always @(posedge dqs_in[51]) if ( dqs_in[51]) dqs_neg_timing_check(51); + always @(posedge dqs_in[52]) if ( dqs_in[52]) dqs_neg_timing_check(52); + always @(posedge dqs_in[53]) if ( dqs_in[53]) dqs_neg_timing_check(53); + always @(posedge dqs_in[54]) if ( dqs_in[54]) dqs_neg_timing_check(54); + always @(posedge dqs_in[55]) if ( dqs_in[55]) dqs_neg_timing_check(55); + always @(posedge dqs_in[56]) if ( dqs_in[56]) dqs_neg_timing_check(56); + always @(posedge dqs_in[57]) if ( dqs_in[57]) dqs_neg_timing_check(57); + always @(posedge dqs_in[58]) if ( dqs_in[58]) dqs_neg_timing_check(58); + always @(posedge dqs_in[59]) if ( dqs_in[59]) dqs_neg_timing_check(59); + always @(posedge dqs_in[60]) if ( dqs_in[60]) dqs_neg_timing_check(60); + always @(posedge dqs_in[61]) if ( dqs_in[61]) dqs_neg_timing_check(61); + always @(posedge dqs_in[62]) if ( dqs_in[62]) dqs_neg_timing_check(62); + always @(posedge dqs_in[63]) if ( dqs_in[63]) dqs_neg_timing_check(63); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model_parameters.vh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model_parameters.vh new file mode 100644 index 0000000..48f5132 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ddr3_model_parameters.vh @@ -0,0 +1,3413 @@ +/**************************************************************************************** +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +****************************************************************************************/ + + // Parameters current with 1Gb, 2Gb, 4Gb and 8Gb datasheet + + // Timing parameters based on Speed Grade + +`ifdef x8Gb // 8Gb parameters + // SYMBOL UNITS DESCRIPTION + // ------ ----- ----------- + `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin + parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46090; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13090; // tRCD ps Active to Read/Write command time + parameter TRP = 13090; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data + parameter CL_TIME = 13090; // CL ps Minimum CAS Latency + `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin + parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47910; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13910; // tRCD ps Active to Read/Write command time + parameter TRP = 13910; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data + parameter CL_TIME = 13910; // CL ps Minimum CAS Latency + `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13750; // tRCD ps Active to Read/Write command time + parameter TRP = 13750; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data + parameter CL_TIME = 13750; // CL ps Minimum CAS Latency + `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333 (9-9-9) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13500; // tRCD ps Active to Read/Write command time + parameter TRP = 13500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data + parameter CL_TIME = 13500; // CL ps Minimum CAS Latency + `else + `define sg187E // sg187E is equivalent to the JEDEC DDR3-1066 (7-7-7) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `endif + + parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed + + `ifdef x16 + `ifdef sg093 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `else // sg187E, sg187, sg25, sg25E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `endif + `else // x4, x8 + `ifdef sg093 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `else // sg25, sg25E + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `endif + `endif + + // Timing Parameters + + // Mode Register + parameter CL_MIN = 5; // CL tCK Minimum CAS Latency + parameter CL_MAX = 14; // CL tCK Maximum CAS Latency + parameter AL_MIN = 0; // AL tCK Minimum Additive Latency + parameter AL_MAX = 2; // AL tCK Maximum Additive Latency + parameter WR_MIN = 5; // WR tCK Minimum Write Recovery + parameter WR_MAX = 16; // WR tCK Maximum Write Recovery + parameter BL_MIN = 4; // BL tCK Minimum Burst Length + parameter BL_MAX = 8; // BL tCK Minimum Burst Length + parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency + parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency + + // Clock + parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time + parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width + parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width + parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width + parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data + + // Data OUT + parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# + // Data Strobe OUT + parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble + parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble + // Data Strobe IN + parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width + parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width + parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble + parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble + // Command and Address + integer TZQCS; // tZQCS tCK ZQ Cal (Short) time + integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time + integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time + parameter TCCD = 4; // tCCD tCK Cas to Cas command delay + parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group + parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time + parameter TWR = 15000; // tWR ps Write recovery time + parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time + parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time + parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time + parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time + parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group + parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group + parameter TRTP = 7500; // tRTP ps Read to Precharge command delay + parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay + parameter TWTR = 7500; // tWTR ps Write to Read command delay + parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group + parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay + parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group + parameter TDLLK = 512; // tDLLK tCK DLL locking time + // Refresh - 4Gb + parameter TRFC_MIN = 260000; // tRFC ps Refresh to Refresh Command interval minimum value + parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value + // Power Down + parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command + parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry + parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry + parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry + parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay + parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing + parameter TXPR = 270000; // tXPR ps Exit Reset from CKE assertion to a valid command + parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command + // Self Refresh + parameter TXS = 270000; // tXS ps Exit self refesh to a non-read or write command + parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command + parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command + parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. + parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing + // ODT + parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference + parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) + parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) + parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) + parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) + parameter TADC = 0.7; // tADC tCK RTT dynamic change skew + // Write Levelization + parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed + parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed + parameter TWLOE = 2000; // tWLOE ps Write levelization output error + + // Size Parameters based on Part Width + + `ifdef x4 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 16; // MAX Address Bits + parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 14; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `define CA14PLUS + `elsif x8 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 16; // MAX Address Bits + parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `else + `define x16 + parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 16; // MAX Address Bits + parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used + `endif + + // Size Parameters + parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used + parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. + parameter AP = 10; // the address bit that controls auto-precharge and precharge-all + parameter BC = 12; // the address bit that controls burst chop + parameter BL_BITS = 3; // the number of bits required to count to BL_MAX + parameter BO_BITS = 2; // the number of Burst Order Bits + + `ifdef QUAD_RANK + parameter CS_BITS = 4; // Number of Chip Select Bits + parameter RANKS = 4; // Number of Chip Selects + `elsif DUAL_RANK + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 2; // Number of Chip Selects + `else + parameter CS_BITS = 1; // Number of Chip Select Bits + parameter RANKS = 1; // Number of Chip Selects + `endif + + // Simulation parameters + parameter RZQ = 240; // termination resistance + parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout + parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors + parameter DEBUG = 1; // Turn on Debug messages + parameter BUS_DELAY = 0; // delay in nanoseconds + parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads + parameter RANDOM_SEED = 31913; //seed value for random generator. + + parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe + parameter RDQSEN_PST = 1; // DQS driving time after last read strobe + parameter RDQS_PRE = 2; // DQS low time prior to first read strobe + parameter RDQS_PST = 1; // DQS low time after last read strobe + parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data + parameter RDQEN_PST = 0; // DQ/DM driving time after last read data + parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe + parameter WDQS_PST = 1; // DQS half clock periods after last write strobe + + // check for legal cas latency based on the cas write latency + function valid_cl; + input [3:0] cl; + input [3:0] cwl; + + case ({cwl, cl}) + `ifdef sg093 + {4'd5 , 4'd5 }, + {4'd5 , 4'd6 }, + {4'd6 , 4'd7 }, + {4'd6 , 4'd8 }, + {4'd7 , 4'd9 }, + {4'd7 , 4'd10}, + {4'd8 , 4'd11}, + {4'd9 , 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg107 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg125 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg15E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg15 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg187E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg187 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }: valid_cl = 1; + `endif + default : valid_cl = 0; + endcase + endfunction + + // find the minimum valid cas write latency + function [3:0] min_cwl; + input period; + real period; + min_cwl = (period >= 2500.0) ? 5: + (period >= 1875.0) ? 6: + (period >= 1500.0) ? 7: + (period >= 1250.0) ? 8: + (period >= 1071.0) ? 9: + 10; // (period >= 938) + endfunction + + // find the minimum valid cas latency + function [3:0] min_cl; + input period; + real period; + reg [3:0] cwl; + reg [3:0] cl; + begin + cwl = min_cwl(period); + for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin + if (valid_cl(cl, cwl)) begin + min_cl = cl; + end + end + end + endfunction + +`elsif x4Gb // 4Gb parameters + // SYMBOL UNITS DESCRIPTION + // ------ ----- ----------- + `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin + parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13090; // tRCD ps Active to Read/Write command time + parameter TRP = 13090; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data + parameter CL_TIME = 13090; // CL ps Minimum CAS Latency + `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12155; // tRCD ps Active to Read/Write command time + parameter TRP = 12155; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data + parameter CL_TIME = 12155; // CL ps Minimum CAS Latency + `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11220; // tRCD ps Active to Read/Write command time + parameter TRP = 11220; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data + parameter CL_TIME = 11220; // CL ps Minimum CAS Latency + `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin + parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47910; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13910; // tRCD ps Active to Read/Write command time + parameter TRP = 13910; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data + parameter CL_TIME = 13910; // CL ps Minimum CAS Latency + `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12840; // tRCD ps Active to Read/Write command time + parameter TRP = 12840; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data + parameter CL_TIME = 12840; // CL ps Minimum CAS Latency + `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11770; // tRCD ps Active to Read/Write command time + parameter TRP = 11770; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data + parameter CL_TIME = 11770; // CL ps Minimum CAS Latency + `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13750; // tRCD ps Active to Read/Write command time + parameter TRP = 13750; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data + parameter CL_TIME = 13750; // CL ps Minimum CAS Latency + `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13500; // tRCD ps Active to Read/Write command time + parameter TRP = 13500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data + parameter CL_TIME = 13500; // CL ps Minimum CAS Latency + `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `else //`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `endif + + parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed + + `ifdef x16 + `ifdef sg093 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `else // sg187E, sg187, sg25, sg25E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `endif + `else // x4, x8 + `ifdef sg093 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `else // sg25, sg25E + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `endif + `endif + + // Timing Parameters + + // Mode Register + parameter CL_MIN = 5; // CL tCK Minimum CAS Latency + parameter CL_MAX = 14; // CL tCK Maximum CAS Latency + parameter AL_MIN = 0; // AL tCK Minimum Additive Latency + parameter AL_MAX = 2; // AL tCK Maximum Additive Latency + parameter WR_MIN = 5; // WR tCK Minimum Write Recovery + parameter WR_MAX = 16; // WR tCK Maximum Write Recovery + parameter BL_MIN = 4; // BL tCK Minimum Burst Length + parameter BL_MAX = 8; // BL tCK Minimum Burst Length + parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency + parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency + + // Clock + parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time + parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width + parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width + parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width + parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data + + // Data OUT + parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# + // Data Strobe OUT + parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble + parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble + // Data Strobe IN + parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width + parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width + parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble + parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble + // Command and Address + integer TZQCS; // tZQCS tCK ZQ Cal (Short) time + integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time + integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time + parameter TCCD = 4; // tCCD tCK Cas to Cas command delay + parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group + parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time + parameter TWR = 15000; // tWR ps Write recovery time + parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time + parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time + parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time + parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time + parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group + parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group + parameter TRTP = 7500; // tRTP ps Read to Precharge command delay + parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay + parameter TWTR = 7500; // tWTR ps Write to Read command delay + parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group + parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay + parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group + parameter TDLLK = 512; // tDLLK tCK DLL locking time + // Refresh - 4Gb + parameter TRFC_MIN = 260000; // tRFC ps Refresh to Refresh Command interval minimum value + parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value + // Power Down + parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command + parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry + parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry + parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry + parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay + parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing + parameter TXPR = 270000; // tXPR ps Exit Reset from CKE assertion to a valid command + parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command + // Self Refresh + parameter TXS = 270000; // tXS ps Exit self refesh to a non-read or write command + parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command + parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command + parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. + parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing + // ODT + parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference + parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) + parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) + parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) + parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) + parameter TADC = 0.7; // tADC tCK RTT dynamic change skew + // Write Levelization + parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed + parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed + parameter TWLOE = 2000; // tWLOE ps Write levelization output error + + // Size Parameters based on Part Width + + `ifdef x4 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 16; // MAX Address Bits + parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `elsif x8 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 16; // MAX Address Bits + parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `else //`define x16 + parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 15; // MAX Address Bits + parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used + `endif + + // Size Parameters + parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used + parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. + parameter AP = 10; // the address bit that controls auto-precharge and precharge-all + parameter BC = 12; // the address bit that controls burst chop + parameter BL_BITS = 3; // the number of bits required to count to BL_MAX + parameter BO_BITS = 2; // the number of Burst Order Bits + + `ifdef QUAD_RANK + parameter CS_BITS = 4; // Number of Chip Select Bits + parameter RANKS = 4; // Number of Chip Selects + `elsif DUAL_RANK + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 2; // Number of Chip Selects + `else + parameter CS_BITS = 1; // Number of Chip Select Bits + parameter RANKS = 1; // Number of Chip Selects + `endif + + // Simulation parameters + parameter RZQ = 240; // termination resistance + parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout + parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors + parameter DEBUG = 1; // Turn on Debug messages + parameter BUS_DELAY = 0; // delay in nanoseconds + parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads + parameter RANDOM_SEED = 31913; //seed value for random generator. + + parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe + parameter RDQSEN_PST = 1; // DQS driving time after last read strobe + parameter RDQS_PRE = 2; // DQS low time prior to first read strobe + parameter RDQS_PST = 1; // DQS low time after last read strobe + parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data + parameter RDQEN_PST = 0; // DQ/DM driving time after last read data + parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe + parameter WDQS_PST = 1; // DQS half clock periods after last write strobe + + // check for legal cas latency based on the cas write latency + function valid_cl; + input [3:0] cl; + input [3:0] cwl; + + case ({cwl, cl}) + `ifdef sg093 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd9 }, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd12}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg107 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107E + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg125E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg125 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg15E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg15 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg187E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg187 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg25E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `elsif sg25 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `endif + default : valid_cl = 0; + endcase + endfunction + + // find the minimum valid cas write latency + function [3:0] min_cwl; + input period; + real period; + min_cwl = (period >= 2500.0) ? 5: + (period >= 1875.0) ? 6: + (period >= 1500.0) ? 7: + (period >= 1250.0) ? 8: + (period >= 1071.0) ? 9: + 10; // (period >= 938) + endfunction + + // find the minimum valid cas latency + function [3:0] min_cl; + input period; + real period; + reg [3:0] cwl; + reg [3:0] cl; + begin + cwl = min_cwl(period); + for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin + if (valid_cl(cl, cwl)) begin + min_cl = cl; + end + end + end + endfunction + +`elsif x2Gb // 2Gb parameters + + // SYMBOL UNITS DESCRIPTION + // ------ ----- ----------- + `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin + parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13090; // tRCD ps Active to Read/Write command time + parameter TRP = 13090; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data + parameter CL_TIME = 13090; // CL ps Minimum CAS Latency + `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12155; // tRCD ps Active to Read/Write command time + parameter TRP = 12155; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data + parameter CL_TIME = 12155; // CL ps Minimum CAS Latency + `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11220; // tRCD ps Active to Read/Write command time + parameter TRP = 11220; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data + parameter CL_TIME = 11220; // CL ps Minimum CAS Latency + `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin + parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13910; // tRCD ps Active to Read/Write command time + parameter TRP = 13910; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data + parameter CL_TIME = 13910; // CL ps Minimum CAS Latency + `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12840; // tRCD ps Active to Read/Write command time + parameter TRP = 12840; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data + parameter CL_TIME = 12840; // CL ps Minimum CAS Latency + `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11770; // tRCD ps Active to Read/Write command time + parameter TRP = 11770; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data + parameter CL_TIME = 11770; // CL ps Minimum CAS Latency + `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13750; // tRCD ps Active to Read/Write command time + parameter TRP = 13750; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data + parameter CL_TIME = 13750; // CL ps Minimum CAS Latency + `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13500; // tRCD ps Active to Read/Write command time + parameter TRP = 13500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data + parameter CL_TIME = 13500; // CL ps Minimum CAS Latency + `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `else //`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `endif + + parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed + + `ifdef x16 + `ifdef sg093 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `else // sg187E, sg187, sg25, sg25E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `endif + `else // x4, x8 + `ifdef sg093 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `else // sg25, sg25E + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `endif + `endif + + // Timing Parameters + + // Mode Register + parameter CL_MIN = 5; // CL tCK Minimum CAS Latency + parameter CL_MAX = 14; // CL tCK Maximum CAS Latency + parameter AL_MIN = 0; // AL tCK Minimum Additive Latency + parameter AL_MAX = 2; // AL tCK Maximum Additive Latency + parameter WR_MIN = 5; // WR tCK Minimum Write Recovery + parameter WR_MAX = 16; // WR tCK Maximum Write Recovery + parameter BL_MIN = 4; // BL tCK Minimum Burst Length + parameter BL_MAX = 8; // BL tCK Minimum Burst Length + parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency + parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency + + // Clock + parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time + parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width + parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width + parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width + parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data + + // Data OUT + parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# + // Data Strobe OUT + parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble + parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble + // Data Strobe IN + parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width + parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width + parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble + parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble + // Command and Address + integer TZQCS; // tZQCS tCK ZQ Cal (Short) time + integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time + integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time + parameter TCCD = 4; // tCCD tCK Cas to Cas command delay + parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group + parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time + parameter TWR = 15000; // tWR ps Write recovery time + parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time + parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time + parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time + parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time + parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group + parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group + parameter TRTP = 7500; // tRTP ps Read to Precharge command delay + parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay + parameter TWTR = 7500; // tWTR ps Write to Read command delay + parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group + parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay + parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group + parameter TDLLK = 512; // tDLLK tCK DLL locking time + // Refresh - 2Gb + parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value + parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value + // Power Down + parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command + parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry + parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry + parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry + parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay + parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing + parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command + parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command + // Self Refresh + parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command + parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command + parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command + parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. + parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing + // ODT + parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference + parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) + parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) + parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) + parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) + parameter TADC = 0.7; // tADC tCK RTT dynamic change skew + // Write Levelization + parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed + parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed + parameter TWLOE = 2000; // tWLOE ps Write levelization output error + + // Size Parameters based on Part Width + + `ifdef x4 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 15; // MAX Address Bits + parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `elsif x8 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 15; // MAX Address Bits + parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `else //`define x16 + parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 14; // MAX Address Bits + parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used + `endif + + // Size Parameters + parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used + parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. + parameter AP = 10; // the address bit that controls auto-precharge and precharge-all + parameter BC = 12; // the address bit that controls burst chop + parameter BL_BITS = 3; // the number of bits required to count to BL_MAX + parameter BO_BITS = 2; // the number of Burst Order Bits + + `ifdef QUAD_RANK + `define DUAL_RANK // also define DUAL_RANK + parameter CS_BITS = 4; // Number of Chip Select Bits + parameter RANKS = 4; // Number of Chip Selects + `elsif DUAL_RANK + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 2; // Number of Chip Selects + `else + parameter CS_BITS = 1; // Number of Chip Select Bits + parameter RANKS = 1; // Number of Chip Selects + `endif + + // Simulation parameters + parameter RZQ = 240; // termination resistance + parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout + parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors + parameter DEBUG = 1; // Turn on Debug messages + parameter BUS_DELAY = 0; // delay in nanoseconds + parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads + parameter RANDOM_SEED = 31913; //seed value for random generator. + + parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe + parameter RDQSEN_PST = 1; // DQS driving time after last read strobe + parameter RDQS_PRE = 2; // DQS low time prior to first read strobe + parameter RDQS_PST = 1; // DQS low time after last read strobe + parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data + parameter RDQEN_PST = 0; // DQ/DM driving time after last read data + parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe + parameter WDQS_PST = 1; // DQS half clock periods after last write strobe + + // check for legal cas latency based on the cas write latency + function valid_cl; + input [3:0] cl; + input [3:0] cwl; + + case ({cwl, cl}) + `ifdef sg093 + {4'd5 , 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd9 }, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd12}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg107 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg125E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg125 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg15E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg15 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg187E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg187 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg25E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `elsif sg25 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `endif + default : valid_cl = 0; + endcase + endfunction + + // find the minimum valid cas write latency + function [3:0] min_cwl; + input period; + real period; + min_cwl = (period >= 2500.0) ? 5: + (period >= 1875.0) ? 6: + (period >= 1500.0) ? 7: + (period >= 1250.0) ? 8: + (period >= 1071.0) ? 9: + 10; // (period >= 938) + endfunction + + // find the minimum valid cas latency + function [3:0] min_cl; + input period; + real period; + reg [3:0] cwl; + reg [3:0] cl; + begin + cwl = min_cwl(period); + for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin + if (valid_cl(cl, cwl)) begin + min_cl = cl; + end + end + end + endfunction + + +`else //`define x1Gb // 1Gb parts + + // SYMBOL UNITS DESCRIPTION + // ------ ----- ----------- + `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin + parameter TCK_MIN = 938; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46130; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13090; // tRCD ps Active to Read/Write command time + parameter TRP = 13090; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data + parameter CL_TIME = 13090; // CL ps Minimum CAS Latency + `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12155; // tRCD ps Active to Read/Write command time + parameter TRP = 12155; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data + parameter CL_TIME = 12155; // CL ps Minimum CAS Latency + `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11220; // tRCD ps Active to Read/Write command time + parameter TRP = 11220; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data + parameter CL_TIME = 11220; // CL ps Minimum CAS Latency + `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin + parameter TCK_MIN = 1071; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13910; // tRCD ps Active to Read/Write command time + parameter TRP = 13910; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data + parameter CL_TIME = 13910; // CL ps Minimum CAS Latency + `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12840; // tRCD ps Active to Read/Write command time + parameter TRP = 12840; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data + parameter CL_TIME = 12840; // CL ps Minimum CAS Latency + `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11770; // tRCD ps Active to Read/Write command time + parameter TRP = 11770; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data + parameter CL_TIME = 11770; // CL ps Minimum CAS Latency + `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13750; // tRCD ps Active to Read/Write command time + parameter TRP = 13750; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data + parameter CL_TIME = 13750; // CL ps Minimum CAS Latency + `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13500; // tRCD ps Active to Read/Write command time + parameter TRP = 13500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data + parameter CL_TIME = 13500; // CL ps Minimum CAS Latency + `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800E (5-5-5) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `else //`define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `endif + + parameter TDQSCK_DLLDIS = TDQSCK; // tDQSCK ps for DLLDIS mode, timing not guaranteed + + `ifdef x16 + `ifdef sg093 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg25E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `else // sg25 + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `endif + `else // x4, x8 + `ifdef sg093 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg25E + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `else // sg25 + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `endif + `endif + + // Timing Parameters + + // Mode Register + parameter CL_MIN = 5; // CL tCK Minimum CAS Latency + parameter CL_MAX = 14; // CL tCK Maximum CAS Latency + parameter AL_MIN = 0; // AL tCK Minimum Additive Latency + parameter AL_MAX = 2; // AL tCK Maximum Additive Latency + parameter WR_MIN = 5; // WR tCK Minimum Write Recovery + parameter WR_MAX = 16; // WR tCK Maximum Write Recovery + parameter BL_MIN = 4; // BL tCK Minimum Burst Length + parameter BL_MAX = 8; // BL tCK Minimum Burst Length + parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency + parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency + + // Clock + parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time + parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width + parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width + parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width + parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data + + // Data OUT + parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# + // Data Strobe OUT + parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble + parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble + // Data Strobe IN + parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width + parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width + parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble + parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble + // Command and Address + integer TZQCS; // tZQCS tCK ZQ Cal (Short) time + integer TZQINIT = max(512, ceil(640000/TCK_MIN)); // tZQinit tCK ZQ Cal (Long) time + integer TZQOPER = max(256, ceil(320000/TCK_MIN)); // tZQoper tCK ZQ Cal (Long) time + parameter TCCD = 4; // tCCD tCK Cas to Cas command delay + parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group + parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time + parameter TWR = 15000; // tWR ps Write recovery time + parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time + parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time + parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time + parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time + parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group + parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group + parameter TRTP = 7500; // tRTP ps Read to Precharge command delay + parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay + parameter TWTR = 7500; // tWTR ps Write to Read command delay + parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group + parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay + parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group + parameter TDLLK = 512; // tDLLK tCK DLL locking time + // Refresh - 1Gb + parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value + parameter TRFC_MAX =70200000; // tRFC ps Refresh to Refresh Command Interval maximum value + // Power Down + parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command + parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry + parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry + parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry + parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay + parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing + parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command + parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command + // Self Refresh + parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command + parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command + parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command + parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. + parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing + // ODT + parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference + parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) + parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) + parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) + parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) + parameter TADC = 0.7; // tADC tCK RTT dynamic change skew + // Write Levelization + parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed + parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed + parameter TWLOE = 2000; // tWLOE ps Write levelization output error + + // Size Parameters based on Part Width + + `ifdef x4 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 14; // MAX Address Bits + parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `elsif x8 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 14; // MAX Address Bits + parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `else //`define x16 + parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 13; // MAX Address Bits + parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used + `endif + + // Size Parameters + parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used + parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. + parameter AP = 10; // the address bit that controls auto-precharge and precharge-all + parameter BC = 12; // the address bit that controls burst chop + parameter BL_BITS = 3; // the number of bits required to count to BL_MAX + parameter BO_BITS = 2; // the number of Burst Order Bits + + `ifdef QUAD_RANK + `define DUAL_RANK // also define DUAL_RANK + parameter CS_BITS = 4; // Number of Chip Select Bits + parameter RANKS = 4; // Number of Chip Selects + `elsif DUAL_RANK + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 2; // Number of Chip Selects + `else + parameter CS_BITS = 1; // Number of Chip Select Bits + parameter RANKS = 1; // Number of Chip Selects + `endif + + // Simulation parameters + parameter RZQ = 240; // termination resistance + parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout + parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors + parameter DEBUG = 1; // Turn on Debug messages + parameter BUS_DELAY = 0; // delay in nanoseconds + parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads + parameter RANDOM_SEED = 31913; //seed value for random generator. + + parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe + parameter RDQSEN_PST = 1; // DQS driving time after last read strobe + parameter RDQS_PRE = 2; // DQS low time prior to first read strobe + parameter RDQS_PST = 1; // DQS low time after last read strobe + parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data + parameter RDQEN_PST = 0; // DQ/DM driving time after last read data + parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe + parameter WDQS_PST = 1; // DQS half clock periods after last write strobe + + // check for legal cas latency based on the cas write latency + function valid_cl; + input [3:0] cl; + input [3:0] cwl; + + case ({cwl, cl}) + `ifdef sg093 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd9 }, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd12}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg107 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg125E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg125 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg15E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg15 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg187E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg187 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg25E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `elsif sg25 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `endif + default : valid_cl = 0; + endcase + endfunction + + // find the minimum valid cas write latency + function [3:0] min_cwl; + input period; + real period; + min_cwl = (period >= 2500.0) ? 5: + (period >= 1875.0) ? 6: + (period >= 1500.0) ? 7: + (period >= 1250.0) ? 8: + (period >= 1071.0) ? 9: + 10; // (period >= 938) + endfunction + + // find the minimum valid cas latency + function [3:0] min_cl; + input period; + real period; + reg [3:0] cwl; + reg [3:0] cl; + begin + cwl = min_cwl(period); + for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin + if (valid_cl(cl, cwl)) begin + min_cl = cl; + end + end + end + endfunction + +`endif + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ies_run.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ies_run.sh new file mode 100644 index 0000000..58eae90 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/ies_run.sh @@ -0,0 +1,103 @@ +############################################################################### +## (c) Copyright 2008 – 2009 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +############################################################################### +## ____ ____ +## / /\/ / +## /___/ \ / Vendor : Xilinx +## \ \ \/ Version : 4.2 +## \ \ Application : MIG +## / / Filename : ies_run.sh +## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ +## \ \ / \ Date Created : Tue Oct 29 2013 +## \___\/\___\ +## +## Device : 7 Series +## Purpose : +## Sample ies_run.sh file to compile and simulate memory interface +## design and run the simulation for specified period of time. +## Display the waveforms that are listed with "add wave" command. +## Assumptions : +## Simulation takes place in \sim folder of MIG output directory. +## Reference : +## Revision History : +############################################################################### + +#echo Simulation Tool: IES + +#Compile the required libraries here# +#libraries path# + +#Compile all modules# +ncvlog -work worklib -sv -messages mig_7series*.v > ies_sim.log +ncvlog -sv -work worklib -messages ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3.v >> ies_sim.log +ncvlog -sv -work worklib -messages ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v >> ies_sim.log +ncvlog -work worklib -messages -sv ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/*.v >> ies_sim.log +ncvlog -work worklib -messages -sv ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/*.v >> ies_sim.log +ncvlog -work worklib -messages -sv ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/*.v >> ies_sim.log +ncvlog -work worklib -messages -sv ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ip_top/*.v >> ies_sim.log +ncvlog -work worklib -messages -sv ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/*.v >> ies_sim.log +ncvlog -work worklib -messages -sv ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/*.v >> ies_sim.log + + + +ncvlog -sv -work worklib -messages example_top.v >> ies_sim.log + +#Compile files in sim folder (excluding model parameter file)# +#$XILINX variable must be set +ncvlog -work worklib -messages $XILINX_VIVADO/data/verilog/src/glbl.v >> ies_sim.log +ncvlog -work worklib -messages wiredly.v >> ies_sim.log +ncvlog -work worklib -messages sim_tb_top.v >> ies_sim.log + +#Pass the parameters for memory model parameter file# +ncvlog -work worklib -messages -sv +define+x4Gb +define+sg125 +define+x16 ddr3_model.sv >> ies_sim.log + +#Simulate the design with sim_tb_top as the top module +ncelab -namemap_mixgen -timescale '1ps/1ps' -vhdlsync -v93 -messages -nettype_port_relax -access +rwc sim_tb_top glbl >> ies_sim.log +ncsim sim_tb_top >> ies_sim.log +#echo done + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/readme.txt b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/readme.txt new file mode 100644 index 0000000..143b146 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/readme.txt @@ -0,0 +1,230 @@ +############################################################################### +## (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +############################################################################### +## ____ ____ +## / /\/ / +## /___/ \ / Vendor : Xilinx +## \ \ \/ Version : 4.2 +## \ \ Application : MIG +## / / Filename : readme.txt +## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ +## \ \ / \ Date Created : Tue Sept 21 2010 +## \___\/\___\ +## +## Device : 7 Series +## Design Name : DDR3 SDRAM +## Purpose : Steps to run simulations using Modelsim/QuestaSim, +## Cadence IES, and Synopsys VCS +## Assumptions : Simulations are run in \sim folder of MIG output "Open IP +## Example Design" directory +## Reference : +## Revision History: +############################################################################### + +MIG outputs script files required to run the simulations for Modelsim/QuestaSim, +Vivado Simulator, IES and VCS. These scripts are valid only for running +simulations for "Open IP Example Design" + +1. How to run simulations in Modelsim/QuestaSim simulator + + A) sim.do File : + + a) The 'sim.do' file has commands to compile and simulate memory + interface design and run the simulation for specified period of time. + + b) It has the syntax to Map the required libraries (unisims_ver, + unisim and secureip). The libraries should be mapped using + the following command + vmap unisims_ver + vmap unisim + vmap secureip + + Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file + + c) Displays the waveforms that are listed with "add wave" command. + + B) Steps to run the Modelsim/QuestaSim simulation: + + a) The user should invoke the Modelsim/QuestaSim simulator GUI. + + b) Change the present working directory path to the sim folder. + In Transcript window, at Modelsim/QuestaSim prompt, type the following + command to change directory path. + cd + + c) Run the simulation using sim.do file. + At Modelsim/QuestaSim prompt, type the following command: + do sim.do + + d) To exit simulation, type the following command at Modelsim/QuestaSim + prompt: + quit -f + + e) Verify the transcript file for the memory transactions. + +2. How to run simulations in Vivado simulator + + A) Following files are provided : + + a) The 'xsim_run.bat' is the executable file for Vivado simulator under + MicroSoft Windows environment. + + b) The 'xsim_run.sh' is the executable file for Vivado simulator under + Linux environment. + + c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and + simulate memory interface design and run the simulation for specified + period of time. + + d) xsim_options.tcl file has commands to add waveforms and simulation + period. + + e) xsim_files.prj file has list of rtl files for simulating the design. + + f) $XILINX_VIVADO environment variable must be set in order to compile + glbl.v file + + B) Steps to run the Vivado Simulator simulation: + + a) Change the present working directory path to the sim folder of "Open + IP Example Design" path in the OS terminal. + + b) Run the simulation using xsim_run.sh file under Linux environment and + xsim_run.bat under MicroSoft Windows environment. + + c) Verify the transcript file for the memory transactions. + +3. How to run Cadence IES Simulations + + A) ies_run.sh File : + + a) The "ies_run.sh" file contains the commands for simulation of the + hdl files. + + b) Libraries must be mapped before running simulations. Following + procedure must be followed to before running simulations + + 1. Create two files named cds.lib and hdl.var in this directory + 2. Create a directory 'worklib' in same directory. + mkdir worklib + 3. Add following lines in the cds.lib file to map Xilinx libraries + + DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim + DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver + DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip + DEFINE worklib ./worklib + + 4. ATTENTION: In above lines replace the path for libraries as per your + compiled Xilinx libraries directory + 5. ATTENTION: Add the lines in the same order given above + 6. Please make sure you need to map all Xilinx libraries mentioned above + 7. Save and close the cds.lib file + + Also, $XILINX_VIVADO environment variable must be set in order to + compile glbl.v file and the above mentioned library files + + B) Steps to run the IES simulation: + + a) Change the present working directory path to the sim folder of "Open + IP Example Design" path in the OS terminal. + + b) Run the simulation using ies_run.sh file. Type the following command: + ./ies_run.sh + + c) Verify the ies_sim.log file for the memory transactions. + +4. How to run Synopsys VCS Simulations + + A) vcs_run.sh File : + + a) The "vcs_run.sh" file contains the commands for simulation of hdl files. + + b) Libraries must be mapped before running simulations. Following + procedure must be followed to before running simulations + + 1. Create a file named synopsys_sim.setup in this directory + 2. Add following lines in the synopsys_sim.setup file to map Xilinx + libraries + + unisim : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/unisim + secureip : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/secureip + unisims_ver : /proj/xbuilds/2014.4_daily_latest/clibs/vcs/I-2014.03/lin64/lib/unisims_ver + + 3. ATTENTION: In above lines replace the path for libraries as per your + Compiled Xilinx libraries directory + 4. Please make sure you need to map all Xilinx libraries mentioned above + + Also, $XILINX_VIVADO environment variable must be set in order to + compile glbl.v file and the above mentioned library files + + B) Steps to run the VCS simulation: + + a) Change the present working directory path to the sim folder of "Open + IP Example Design" path in the OS terminal. + + b) Run the simulation using vcs_run.sh file. Type the following command: + ./vcs_run.sh + + c) Verify the vcs_sim.log file for the memory transactions. + +5. SIM_BYPASS_INIT_CAL parameter value of SKIP, skips memory initialization sequence + and calibration sequence. This could lead to simulation errors since design is not + calibrated at all. Preferred values for parameter SIM_BYPASS_INIT_CAL to run + simulations are FAST and OFF. + +6. Simulations running with parameter MAX_MEM defined uses a temporary directory for model data. + The default temporary directory specified in model file is /tmp which doesn't exist for Windows OS. + Therfore users running on Windows OS should change the ddr3_model.v file as below + + tmp_model_dir = "/tmp"; + to + tmp_model_dir = "."; + + This change works for All OS. + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim.do b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim.do new file mode 100644 index 0000000..86b38dc --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim.do @@ -0,0 +1,155 @@ +############################################################################### +## (c) Copyright 2008 – 2009 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +############################################################################### +## ____ ____ +## / /\/ / +## /___/ \ / Vendor : Xilinx +## \ \ \/ Version : 4.2 +## \ \ Application : MIG +## / / Filename : sim.do +## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ +## \ \ / \ Date Created : Tue Sept 21 2010 +## \___\/\___\ +## +## Device : 7 Series +## Purpose : +## Sample sim .do file to compile and simulate memory interface +## design and run the simulation for specified period of time. +## Display the waveforms that are listed with "add wave" command. +## Assumptions : +## Simulation takes place in \sim folder of MIG output directory. +## Reference : +## Revision History : +############################################################################### + +vlib work + +#Map the required libraries here# +#vmap unisims_ver +#vmap unisim +#vmap secureip + +#Compile all modules# +vlog -incr mig_7series*.v +vlog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3.v +vlog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v +vlog -incr ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/*.v +vlog -incr ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/*.v +vlog -incr ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/*.v +vlog -incr ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ip_top/*.v +vlog -incr ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/*.v +vlog -incr ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/*.v + + + +vlog example_top.v + +#Compile files in sim folder (excluding model parameter file)# +#$XILINX variable must be set +vlog -incr $env(XILINX_VIVADO)/data/verilog/src/glbl.v +vlog wiredly.v +vlog sim_tb_top.v + +#Pass the parameters for memory model parameter file# +vlog -sv +define+x4Gb +define+sg125 +define+x16 ddr3_model.sv + +#Load the design. Use required libraries.# +vsim -t fs -novopt +notimingchecks -L unisims_ver -L secureip work.sim_tb_top glbl + +onerror {resume} +#Log all the objects in design. These will appear in .wlf file# +#This helps in viewing all signals of the design instead of +#re-running the simulation for viewing the signals. +#Uncomment below line to log all objects in the design. +#log -r /* + +#View sim_tb_top signals in waveform# +add wave sim:/sim_tb_top/* +#Change radix to Hexadecimal# +radix hex +#Supress Numeric Std package and Arith package warnings.# +#For VHDL designs we get some warnings due to unknown values on some signals at startup# +# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0# +#We may also get some Arithmetic packeage warnings because of unknown values on# +#some of the signals that are used in an Arithmetic operation.# +#In order to suppress these warnings, we use following two commands# +set NumericStdNoWarnings 1 +set StdArithNoWarnings 1 + +# Choose simulation run time by inserting a breakpoint and then run for specified # +# period. For more details, refer to user guide (UG586).# +# Status reporting logic exists both in simulation test bench (sim_tb_top) +# and sim.do file for ModelSim. Any update in simulation run time or time out +# in this file need to be updated in sim_tb_top file as well. +when {/sim_tb_top/init_calib_complete = 1} { +if {[when -label a_100] == ""} { +when -label a_100 { $now = 50 us } { +nowhen a_100 +report simulator control +report simulator state +if {[examine /sim_tb_top/tg_compare_error] == 0} { +echo "TEST PASSED" +stop +} +if {[examine /sim_tb_top/tg_compare_error] != 0} { +echo "TEST FAILED: DATA ERROR" +stop +} +} +} +} + +#In case calibration fails to complete, choose the run time and then stop# +when {$now = @1000 us and /sim_tb_top/init_calib_complete != 1} { +echo "TEST FAILED: CALIBRATION DID NOT COMPLETE" +stop +} + +run -all +stop + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim_tb_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim_tb_top.v new file mode 100644 index 0000000..a3e5ff5 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/sim_tb_top.v @@ -0,0 +1,601 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.2 +// \ \ Application : MIG +// / / Filename : sim_tb_top.v +// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $ +// \ \ / \ Date Created : Tue Sept 21 2010 +// \___\/\___\ +// +// Device : 7 Series +// Design Name : DDR3 SDRAM +// Purpose : +// Top-level testbench for testing DDR3. +// Instantiates: +// 1. IP_TOP (top-level representing FPGA, contains core, +// clocking, built-in testbench/memory checker and other +// support structures) +// 2. DDR3 Memory +// 3. Miscellaneous clock generation and reset logic +// 4. For ECC ON case inserts error on LSB bit +// of data from DRAM to FPGA. +// Reference : +// Revision History : +//***************************************************************************** + +`timescale 1ps/100fs + +module sim_tb_top; + + + //*************************************************************************** + // Traffic Gen related parameters + //*************************************************************************** + parameter SIMULATION = "TRUE"; + parameter PORT_MODE = "BI_MODE"; + parameter DATA_MODE = 4'b0010; + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE"; + parameter EYE_TEST = "FALSE"; + // set EYE_TEST = "TRUE" to probe memory + // signals. Traffic Generator will only + // write to one single location and no + // read transactions will be generated. + parameter DATA_PATTERN = "DGEN_ALL"; + // For small devices, choose one only. + // For large device, choose "DGEN_ALL" + // "DGEN_HAMMER", "DGEN_WALKING1", + // "DGEN_WALKING0","DGEN_ADDR"," + // "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter CMD_PATTERN = "CGEN_ALL"; + // "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM", + // "CGEN_SEQUENTIAL", "CGEN_ALL" + parameter BEGIN_ADDRESS = 32'h00000000; + parameter END_ADDRESS = 32'h00000fff; + parameter PRBS_EADDR_MASK_POS = 32'hff000000; + + //*************************************************************************** + // The following parameters refer to width of various ports + //*************************************************************************** + parameter COL_WIDTH = 10; + // # of memory Column Address bits. + parameter CS_WIDTH = 1; + // # of unique CS outputs to memory. + parameter DM_WIDTH = 2; + // # of DM (data mask) + parameter DQ_WIDTH = 16; + // # of DQ (data) + parameter DQS_WIDTH = 2; + parameter DQS_CNT_WIDTH = 1; + // = ceil(log2(DQS_WIDTH)) + parameter DRAM_WIDTH = 8; + // # of DQ per DQS + parameter ECC = "OFF"; + parameter RANKS = 1; + // # of Ranks. + parameter ODT_WIDTH = 1; + // # of ODT outputs to memory. + parameter ROW_WIDTH = 15; + // # of memory Row Address bits. + parameter ADDR_WIDTH = 29; + // # = RANK_WIDTH + BANK_WIDTH + // + ROW_WIDTH + COL_WIDTH; + // Chip Select is always tied to low for + // single rank devices + //*************************************************************************** + // The following parameters are mode register settings + //*************************************************************************** + parameter BURST_MODE = "8"; + // DDR3 SDRAM: + // Burst Length (Mode Register 0). + // # = "8", "4", "OTF". + // DDR2 SDRAM: + // Burst Length (Mode Register). + // # = "8", "4". + parameter CA_MIRROR = "OFF"; + // C/A mirror opt for DDR3 dual rank + + //*************************************************************************** + // The following parameters are multiplier and divisor factors for PLLE2. + // Based on the selected design frequency these parameters vary. + //*************************************************************************** + parameter CLKIN_PERIOD = 3000; + // Input Clock Period + + + //*************************************************************************** + // Simulation parameters + //*************************************************************************** + parameter SIM_BYPASS_INIT_CAL = "FAST"; + // # = "SIM_INIT_CAL_FULL" - Complete + // memory init & + // calibration sequence + // # = "SKIP" - Not supported + // # = "FAST" - Complete memory init & use + // abbreviated calib sequence + + //*************************************************************************** + // IODELAY and PHY related parameters + //*************************************************************************** + parameter TCQ = 100; + //*************************************************************************** + // IODELAY and PHY related parameters + //*************************************************************************** + parameter RST_ACT_LOW = 1; + // =1 for active low reset, + // =0 for active high. + + //*************************************************************************** + // Referece clock frequency parameters + //*************************************************************************** + parameter REFCLK_FREQ = 200.0; + // IODELAYCTRL reference clock frequency + //*************************************************************************** + // System clock frequency parameters + //*************************************************************************** + parameter tCK = 3000; + // memory tCK paramter. + // # = Clock Period in pS. + parameter nCK_PER_CLK = 4; + // # of memory CKs per fabric CLK + + + + //*************************************************************************** + // Debug and Internal parameters + //*************************************************************************** + parameter DEBUG_PORT = "OFF"; + // # = "ON" Enable debug signals/controls. + // = "OFF" Disable debug signals/controls. + //*************************************************************************** + // Debug and Internal parameters + //*************************************************************************** + parameter DRAM_TYPE = "DDR3"; + + + + //**************************************************************************// + // Local parameters Declarations + //**************************************************************************// + + localparam real TPROP_DQS = 0.00; + // Delay for DQS signal during Write Operation + localparam real TPROP_DQS_RD = 0.00; + // Delay for DQS signal during Read Operation + localparam real TPROP_PCB_CTRL = 0.00; + // Delay for Address and Ctrl signals + localparam real TPROP_PCB_DATA = 0.00; + // Delay for data signal during Write operation + localparam real TPROP_PCB_DATA_RD = 0.00; + // Delay for data signal during Read operation + + localparam MEMORY_WIDTH = 16; + localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH; + localparam ECC_TEST = "OFF" ; + localparam ERR_INSERT = (ECC_TEST == "ON") ? "OFF" : ECC ; + + + localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ)); + localparam RESET_PERIOD = 200000; //in pSec + localparam real SYSCLK_PERIOD = tCK; + + + + //**************************************************************************// + // Wire Declarations + //**************************************************************************// + reg sys_rst_n; + wire sys_rst; + + + reg sys_clk_i; + + reg clk_ref_i; + + + wire ddr3_reset_n; + wire [DQ_WIDTH-1:0] ddr3_dq_fpga; + wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga; + wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga; + wire [ROW_WIDTH-1:0] ddr3_addr_fpga; + wire [3-1:0] ddr3_ba_fpga; + wire ddr3_ras_n_fpga; + wire ddr3_cas_n_fpga; + wire ddr3_we_n_fpga; + wire [1-1:0] ddr3_cke_fpga; + wire [1-1:0] ddr3_ck_p_fpga; + wire [1-1:0] ddr3_ck_n_fpga; + + + wire init_calib_complete; + wire tg_compare_error; + + wire [DM_WIDTH-1:0] ddr3_dm_fpga; + + wire [ODT_WIDTH-1:0] ddr3_odt_fpga; + + + + reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp; + + reg [ODT_WIDTH-1:0] ddr3_odt_sdram_tmp; + + + + wire [DQ_WIDTH-1:0] ddr3_dq_sdram; + reg [ROW_WIDTH-1:0] ddr3_addr_sdram [0:1]; + reg [3-1:0] ddr3_ba_sdram [0:1]; + reg ddr3_ras_n_sdram; + reg ddr3_cas_n_sdram; + reg ddr3_we_n_sdram; + wire [(CS_WIDTH*1)-1:0] ddr3_cs_n_sdram; + wire [ODT_WIDTH-1:0] ddr3_odt_sdram; + reg [1-1:0] ddr3_cke_sdram; + wire [DM_WIDTH-1:0] ddr3_dm_sdram; + wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram; + wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram; + reg [1-1:0] ddr3_ck_p_sdram; + reg [1-1:0] ddr3_ck_n_sdram; + + + +//**************************************************************************// + + //**************************************************************************// + // Reset Generation + //**************************************************************************// + initial begin + sys_rst_n = 1'b0; + #RESET_PERIOD + sys_rst_n = 1'b1; + end + + assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n; + + //**************************************************************************// + // Clock Generation + //**************************************************************************// + + initial + sys_clk_i = 1'b0; + always + sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i; + + + initial + clk_ref_i = 1'b0; + always + clk_ref_i = #REFCLK_PERIOD ~clk_ref_i; + + + + + always @( * ) begin + ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga; + ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga; + ddr3_addr_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_addr_fpga; + ddr3_addr_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ? + {ddr3_addr_fpga[ROW_WIDTH-1:9], + ddr3_addr_fpga[7], ddr3_addr_fpga[8], + ddr3_addr_fpga[5], ddr3_addr_fpga[6], + ddr3_addr_fpga[3], ddr3_addr_fpga[4], + ddr3_addr_fpga[2:0]} : + ddr3_addr_fpga; + ddr3_ba_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_ba_fpga; + ddr3_ba_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ? + {ddr3_ba_fpga[3-1:2], + ddr3_ba_fpga[0], + ddr3_ba_fpga[1]} : + ddr3_ba_fpga; + ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga; + ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga; + ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga; + ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga; + end + + + assign ddr3_cs_n_sdram = {(CS_WIDTH*1){1'b0}}; + + + always @( * ) + ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation + assign ddr3_dm_sdram = ddr3_dm_sdram_tmp; + + + always @( * ) + ddr3_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_odt_fpga; + assign ddr3_odt_sdram = ddr3_odt_sdram_tmp; + + +// Controlling the bi-directional BUS + + genvar dqwd; + generate + for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay + WireDelay # + ( + .Delay_g (TPROP_PCB_DATA), + .Delay_rd (TPROP_PCB_DATA_RD), + .ERR_INSERT ("OFF") + ) + u_delay_dq + ( + .A (ddr3_dq_fpga[dqwd]), + .B (ddr3_dq_sdram[dqwd]), + .reset (sys_rst_n), + .phy_init_done (init_calib_complete) + ); + end + WireDelay # + ( + .Delay_g (TPROP_PCB_DATA), + .Delay_rd (TPROP_PCB_DATA_RD), + .ERR_INSERT ("OFF") + ) + u_delay_dq_0 + ( + .A (ddr3_dq_fpga[0]), + .B (ddr3_dq_sdram[0]), + .reset (sys_rst_n), + .phy_init_done (init_calib_complete) + ); + endgenerate + + genvar dqswd; + generate + for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay + WireDelay # + ( + .Delay_g (TPROP_DQS), + .Delay_rd (TPROP_DQS_RD), + .ERR_INSERT ("OFF") + ) + u_delay_dqs_p + ( + .A (ddr3_dqs_p_fpga[dqswd]), + .B (ddr3_dqs_p_sdram[dqswd]), + .reset (sys_rst_n), + .phy_init_done (init_calib_complete) + ); + + WireDelay # + ( + .Delay_g (TPROP_DQS), + .Delay_rd (TPROP_DQS_RD), + .ERR_INSERT ("OFF") + ) + u_delay_dqs_n + ( + .A (ddr3_dqs_n_fpga[dqswd]), + .B (ddr3_dqs_n_sdram[dqswd]), + .reset (sys_rst_n), + .phy_init_done (init_calib_complete) + ); + end + endgenerate + + + + + //=========================================================================== + // FPGA Memory Controller + //=========================================================================== + + example_top # + ( + + .SIMULATION (SIMULATION), + .PORT_MODE (PORT_MODE), + .DATA_MODE (DATA_MODE), + .TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE), + .EYE_TEST (EYE_TEST), + .DATA_PATTERN (DATA_PATTERN), + .CMD_PATTERN (CMD_PATTERN), + .BEGIN_ADDRESS (BEGIN_ADDRESS), + .END_ADDRESS (END_ADDRESS), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), + + .COL_WIDTH (COL_WIDTH), + .CS_WIDTH (CS_WIDTH), + .DM_WIDTH (DM_WIDTH), + + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .ECC_TEST (ECC_TEST), + .RANKS (RANKS), + .ROW_WIDTH (ROW_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .BURST_MODE (BURST_MODE), + .TCQ (TCQ), + + + .DRAM_TYPE (DRAM_TYPE), + + + .nCK_PER_CLK (nCK_PER_CLK), + + + .DEBUG_PORT (DEBUG_PORT), + + .RST_ACT_LOW (RST_ACT_LOW) + ) + u_ip_top + ( + + .ddr3_dq (ddr3_dq_fpga), + .ddr3_dqs_n (ddr3_dqs_n_fpga), + .ddr3_dqs_p (ddr3_dqs_p_fpga), + + .ddr3_addr (ddr3_addr_fpga), + .ddr3_ba (ddr3_ba_fpga), + .ddr3_ras_n (ddr3_ras_n_fpga), + .ddr3_cas_n (ddr3_cas_n_fpga), + .ddr3_we_n (ddr3_we_n_fpga), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_ck_p (ddr3_ck_p_fpga), + .ddr3_ck_n (ddr3_ck_n_fpga), + .ddr3_cke (ddr3_cke_fpga), + .ddr3_dm (ddr3_dm_fpga), + + .ddr3_odt (ddr3_odt_fpga), + + + .sys_clk_i (sys_clk_i), + + .clk_ref_i (clk_ref_i), + + .device_temp_i (12'b0), + + .init_calib_complete (init_calib_complete), + .tg_compare_error (tg_compare_error), + .sys_rst (sys_rst) + ); + + //**************************************************************************// + // Memory Models instantiations + //**************************************************************************// + + genvar r,i; + generate + for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk + if(DQ_WIDTH/16) begin: mem + for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem + ddr3_model u_comp_ddr3 + ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p_sdram), + .ck_n (ddr3_ck_n_sdram), + .cke (ddr3_cke_sdram[r]), + .cs_n (ddr3_cs_n_sdram[r]), + .ras_n (ddr3_ras_n_sdram), + .cas_n (ddr3_cas_n_sdram), + .we_n (ddr3_we_n_sdram), + .dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]), + .ba (ddr3_ba_sdram[r]), + .addr (ddr3_addr_sdram[r]), + .dq (ddr3_dq_sdram[16*(i+1)-1:16*(i)]), + .dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]), + .dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]), + .tdqs_n (), + .odt (ddr3_odt_sdram[r]) + ); + end + end + if (DQ_WIDTH%16) begin: gen_mem_extrabits + ddr3_model u_comp_ddr3 + ( + .rst_n (ddr3_reset_n), + .ck (ddr3_ck_p_sdram), + .ck_n (ddr3_ck_n_sdram), + .cke (ddr3_cke_sdram[r]), + .cs_n (ddr3_cs_n_sdram[r]), + .ras_n (ddr3_ras_n_sdram), + .cas_n (ddr3_cas_n_sdram), + .we_n (ddr3_we_n_sdram), + .dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}), + .ba (ddr3_ba_sdram[r]), + .addr (ddr3_addr_sdram[r]), + .dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)], + ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}), + .dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1], + ddr3_dqs_p_sdram[DQS_WIDTH-1]}), + .dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1], + ddr3_dqs_n_sdram[DQS_WIDTH-1]}), + .tdqs_n (), + .odt (ddr3_odt_sdram[r]) + ); + end + end + endgenerate + + + + + //*************************************************************************** + // Reporting the test case status + // Status reporting logic exists both in simulation test bench (sim_tb_top) + // and sim.do file for ModelSim. Any update in simulation run time or time out + // in this file need to be updated in sim.do file as well. + //*************************************************************************** + initial + begin : Logging + fork + begin : calibration_done + wait (init_calib_complete); + $display("Calibration Done"); + #50000000.0; + if (!tg_compare_error) begin + $display("TEST PASSED"); + end + else begin + $display("TEST FAILED: DATA ERROR"); + end + disable calib_not_done; + $finish; + end + + begin : calib_not_done + if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL") + #2500000000.0; + else + #1000000000.0; + if (!init_calib_complete) begin + $display("TEST FAILED: INITIALIZATION DID NOT COMPLETE"); + end + disable calibration_done; + $finish; + end + join + end + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/vcs_run.sh b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/vcs_run.sh new file mode 100644 index 0000000..bd1931e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/vcs_run.sh @@ -0,0 +1,103 @@ +############################################################################### +## (c) Copyright 2008 – 2009 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +############################################################################### +## ____ ____ +## / /\/ / +## /___/ \ / Vendor : Xilinx +## \ \ \/ Version : 4.2 +## \ \ Application : MIG +## / / Filename : vcs_run.sh +## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ +## \ \ / \ Date Created : Tue Oct 29 2013 +## \___\/\___\ +## +## Device : 7 Series +## Purpose : +## Sample vcs_run.sh file to compile and simulate memory interface +## design and run the simulation for specified period of time. +## Display the waveforms that are listed with "add wave" command. +## Assumptions : +## Simulation takes place in \sim folder of MIG output directory. +## Reference : +## Revision History : +############################################################################### + +#echo Simulation Tool: VCS + +#Compile the required libraries here# +#libraries path# + +#Compile all modules# +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3.v > vcs_sim.log +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v >> vcs_sim.log +vlogan -sverilog mig_7series*.v >> vcs_sim.log +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/*.v >> vcs_sim.log +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/*.v >> vcs_sim.log +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/*.v >> vcs_sim.log +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ip_top/*.v >> vcs_sim.log +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/*.v >> vcs_sim.log +vlogan -sverilog ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/*.v >> vcs_sim.log + + + + +vlogan -sverilog example_top.v >> vcs_sim.log + +#Compile files in sim folder (excluding model parameter file)# +#$XILINX variable must be set +vlogan $XILINX_VIVADO/data/verilog/src/glbl.v >> vcs_sim.log +vlogan -sverilog wiredly.v >> vcs_sim.log +vlogan -sverilog sim_tb_top.v >> vcs_sim.log + +#Pass the parameters for memory model parameter file# +vlogan -Xcheck_p1800_2009=char -sverilog +define+x4Gb +define+sg125 +define+x16 ddr3_model.sv >> vcs_sim.log + +#Simulate the design with sim_tb_top as the top module +vcs -R -debug_pp -lca sim_tb_top glbl >> vcs_sim.log +#echo done + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/wiredly.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/wiredly.v new file mode 100644 index 0000000..38164bd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/wiredly.v @@ -0,0 +1,160 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.2 +// \ \ Application : MIG +// / / Filename : wiredly.v +// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ +// \ \ / \ Date Created : Tue Sept 21 2010 +// \___\/\___\ +// +// Device : 7Series +// Design Name : DDR3 SDRAM +// Purpose : +// This module provide the definition of a zero ohm component (A, B). +// +// The applications of this component include: +// . Normal operation of a jumper wire (data flowing in both directions) +// This can corrupt data from DRAM to FPGA useful for verifying ECC function. +// +// The component consists of 2 ports: +// . Port A: One side of the pass-through switch +// . Port B: The other side of the pass-through switch + +// The model is sensitive to transactions on all ports. Once a transaction +// is detected, all other transactions are ignored for that simulation time +// (i.e. further transactions in that delta time are ignored). + +// Model Limitations and Restrictions: +// Signals asserted on the ports of the error injector should not have +// transactions occuring in multiple delta times because the model +// is sensitive to transactions on port A, B ONLY ONCE during +// a simulation time. Thus, once fired, a process will +// not refire if there are multiple transactions occuring in delta times. +// This condition may occur in gate level simulations with +// ZERO delays because transactions may occur in multiple delta times. +// +// Reference : +// Revision History : +//***************************************************************************** + +`timescale 1ns / 1ps + +module WireDelay # ( + parameter Delay_g = 0, + parameter Delay_rd = 0, + parameter ERR_INSERT = "OFF" +) +( + inout A, + inout B, + input reset, + input phy_init_done +); + + reg A_r; + reg B_r; + reg B_inv ; + reg line_en; + + reg B_nonX; + + assign A = A_r; + assign B = B_r; + + always @ (*) + begin + if (B === 1'bx) + B_nonX <= $random; + else + B_nonX <= B; + end + + always@(*) + begin + if((B_nonX == 'b1) || (B_nonX == 'b0)) + B_inv <= #0 ~B_nonX ; + else + B_inv <= #0 'bz ; + end + + always @(*) begin + if (!reset) begin + A_r <= 1'bz; + B_r <= 1'bz; + line_en <= 1'b0; + end else begin + if (line_en) begin + B_r <= 1'bz; + if ((ERR_INSERT == "ON") & (phy_init_done)) + A_r <= #Delay_rd B_inv; + else + A_r <= #Delay_rd B_nonX; + end else begin + B_r <= #Delay_g A; + A_r <= 1'bz; + end + end + end + + always @(A or B) begin + if (!reset) begin + line_en <= 1'b0; + end else if (A !== A_r) begin + line_en <= 1'b0; + end else if (B_r !== B) begin + line_en <= 1'b1; + end else begin + line_en <= line_en; + end + end +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_files.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_files.prj new file mode 100644 index 0000000..4274a11 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_files.prj @@ -0,0 +1,159 @@ +------------------------------------------------------------------------------- +-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor : Xilinx +-- \ \ \/ Version : 4.2 +-- \ \ Application : MIG +-- / / Filename : xsim_files.prj +-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ +-- \ \ / \ Date Created : Tue Jun 05 2012 +-- \___\/\___\ +-- +-- Device : 7 Series +-- Design Name : DDR3 SDRAM +-- Purpose : Contains a list of all the files associated with a design +-- Assumptions: +-- - Simulation takes place in \sim folder of MIG output directory +-- Reference : +-- Revision History: +------------------------------------------------------------------------------- + +verilog work mig_7series_v4_2_afifo.v +verilog work mig_7series_v4_2_cmd_gen.v +verilog work mig_7series_v4_2_cmd_prbs_gen.v +verilog work mig_7series_v4_2_data_prbs_gen.v +verilog work mig_7series_v4_2_init_mem_pattern_ctr.v +verilog work mig_7series_v4_2_memc_flow_vcontrol.v +verilog work mig_7series_v4_2_memc_traffic_gen.v +verilog work mig_7series_v4_2_rd_data_gen.v +verilog work mig_7series_v4_2_read_data_path.v +verilog work mig_7series_v4_2_read_posted_fifo.v +verilog work mig_7series_v4_2_s7ven_data_gen.v +verilog work mig_7series_v4_2_tg_prbs_gen.v +verilog work mig_7series_v4_2_tg_status.v +verilog work mig_7series_v4_2_traffic_gen_top.v +verilog work mig_7series_v4_2_vio_init_pattern_bram.v +verilog work mig_7series_v4_2_write_data_path.v +verilog work mig_7series_v4_2_wr_data_gen.v +verilog work example_top.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3.v +verilog work ../ddr3_ex.srcs/sources_1/ip/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v +verilog work $XILINX_VIVADO/data/verilog/src/glbl.v +sv work ddr3_model.sv -d x4Gb -d sg125 -d x16 +verilog work wiredly.v +verilog work sim_tb_top.v + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_options.tcl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_options.tcl new file mode 100644 index 0000000..b43651c --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_options.tcl @@ -0,0 +1,71 @@ +############################################################################### +## (c) Copyright 2012 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +############################################################################### +## ____ ____ +## / /\/ / +## /___/ \ / Vendor : Xilinx +## \ \ \/ Version : 4.2 +## \ \ Application : MIG +## / / Filename : xsim_options.tcl +## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ +## \ \ / \ Date Created : Tue Jun 05 2012 +## \___\/\___\ +## +## Device : 7 Series +## Design Name : DDR3 SDRAM +## Purpose : To give commands to XSIM Simulator through batch mode +## Assumptions: +## - Simulation takes place in \sim folder of MIG output directory +## Reference : +## Revision History: +############################################################################### + + +add_wave -radix hex /sim_tb_top +run 1000 us + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_run.bat b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_run.bat new file mode 100644 index 0000000..f0c3550 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/example_design/sim/xsim_run.bat @@ -0,0 +1,72 @@ +::!/bin/csh -f +::***************************************************************************** +:: (c) Copyright 2012 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +:: +:: **************************************************************************** +:: ____ ____ +:: / /\/ / +:: /___/ \ / Vendor : Xilinx +:: \ \ \/ Version : 4.2 +:: \ \ Application : MIG +:: / / Filename : xsim_run.bat +:: /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ +:: \ \ / \ Date Created : Tue Jun 05 2012 +:: \___\/\___\ +:: +:: Device : 7 Series +:: Design Name : DDR3 SDRAM +:: Purpose : Batch file to run Simulation through Vivado Simulator +:: Reference : +:: Revision History : +:: **************************************************************************** + + +echo Simulation Tool: Viavdo Simulator +call xelab work.sim_tb_top work.glbl -prj xsim_files.prj -L unisims_ver -L secureip -s xsim_test -debug typical +xsim -g -t xsim_options.tcl -wdb xsim_database.wdb xsim_test +echo done + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/mig.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/mig.prj new file mode 100644 index 0000000..b1e7eb0 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/mig.prj @@ -0,0 +1,152 @@ + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a100tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a100tfgg484_pkg.xdc new file mode 100644 index 0000000..e4e7729 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a100tfgg484_pkg.xdc @@ -0,0 +1,360 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : ddr3.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A100TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + +# PadFunction: IO_L11N_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L12P_T1_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L8N_T1_AD14N_35 +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN G2 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L7N_T1_AD6N_35 +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L11P_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L7P_T1_AD6P_35 +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L8P_T1_AD14P_35 +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L10P_T1_AD15P_35 +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L6N_T0_VREF_35 +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN E3 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L2P_T0_AD12P_35 +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN C2 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L5N_T0_AD13N_35 +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L4N_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L2N_T0_AD12N_35 +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L1N_T0_AD4N_35 +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN A1 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L4P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L1P_T0_AD4P_35 +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_25_35 +set_property SLEW FAST [get_ports {ddr3_addr[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN L6 [get_ports {ddr3_addr[14]}] + +# PadFunction: IO_L19P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L23N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN M5 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L24N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN N5 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L18P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN L5 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L22P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN P2 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L20P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN R1 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L22N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN N2 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L23P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L16N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN M2 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L20N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN P1 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L18N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN L4 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L19N_T3_VREF_35 +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN N3 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L24P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L16P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN M3 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L17P_T2_35 +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN K6 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L15P_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN M1 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L14P_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN L3 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L17N_T2_35 +set_property SLEW FAST [get_ports {ddr3_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] +set_property PACKAGE_PIN J6 [get_ports {ddr3_ras_n}] + +# PadFunction: IO_L14N_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] +set_property PACKAGE_PIN K3 [get_ports {ddr3_cas_n}] + +# PadFunction: IO_L13P_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] +set_property PACKAGE_PIN K4 [get_ports {ddr3_we_n}] + +# PadFunction: IO_L5P_T0_AD13P_35 +set_property SLEW FAST [get_ports {ddr3_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] +set_property PACKAGE_PIN G1 [get_ports {ddr3_reset_n}] + +# PadFunction: IO_L15N_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN L1 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_L13N_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN J4 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L10N_T1_AD15N_35 +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN H5 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L6P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN F3 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L9P_T1_DQS_AD7P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L9N_T1_DQS_AD7N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN J2 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L3P_T0_DQS_AD5P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN E1 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L3N_T0_DQS_AD5N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN D1 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L21P_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN P5 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L21N_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN P4 [get_ports {ddr3_ck_n[0]}] + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] + + +set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] + + +## set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] + + + + + +set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] + + +set_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] + + +set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + + +set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + + +set_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] + + + +set_property LOC PLLE2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + + + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -setup 6 + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -hold 5 + +set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start + +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20 +set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 +#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] +set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}] + \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a15tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a15tfgg484_pkg.xdc new file mode 100644 index 0000000..4e3128b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a15tfgg484_pkg.xdc @@ -0,0 +1,360 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : ddr3.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A15TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + +# PadFunction: IO_L11N_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L12P_T1_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L8N_T1_AD14N_35 +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN G2 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L7N_T1_AD6N_35 +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L11P_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L7P_T1_AD6P_35 +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L8P_T1_AD14P_35 +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L10P_T1_AD15P_35 +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L6N_T0_VREF_35 +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN E3 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L2P_T0_AD12P_35 +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN C2 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L5N_T0_AD13N_35 +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L4N_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L2N_T0_AD12N_35 +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L1N_T0_AD4N_35 +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN A1 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L4P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L1P_T0_AD4P_35 +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_25_35 +set_property SLEW FAST [get_ports {ddr3_addr[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN L6 [get_ports {ddr3_addr[14]}] + +# PadFunction: IO_L19P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L23N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN M5 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L24N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN N5 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L18P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN L5 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L22P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN P2 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L20P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN R1 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L22N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN N2 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L23P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L16N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN M2 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L20N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN P1 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L18N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN L4 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L19N_T3_VREF_35 +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN N3 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L24P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L16P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN M3 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L17P_T2_35 +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN K6 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L15P_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN M1 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L14P_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN L3 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L17N_T2_35 +set_property SLEW FAST [get_ports {ddr3_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] +set_property PACKAGE_PIN J6 [get_ports {ddr3_ras_n}] + +# PadFunction: IO_L14N_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] +set_property PACKAGE_PIN K3 [get_ports {ddr3_cas_n}] + +# PadFunction: IO_L13P_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] +set_property PACKAGE_PIN K4 [get_ports {ddr3_we_n}] + +# PadFunction: IO_L5P_T0_AD13P_35 +set_property SLEW FAST [get_ports {ddr3_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] +set_property PACKAGE_PIN G1 [get_ports {ddr3_reset_n}] + +# PadFunction: IO_L15N_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN L1 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_L13N_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN J4 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L10N_T1_AD15N_35 +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN H5 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L6P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN F3 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L9P_T1_DQS_AD7P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L9N_T1_DQS_AD7N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN J2 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L3P_T0_DQS_AD5P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN E1 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L3N_T0_DQS_AD5N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN D1 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L21P_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN P5 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L21N_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN P4 [get_ports {ddr3_ck_n[0]}] + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] + + +set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] + + +## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] + + + + + +set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] + + +set_property LOC IN_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] + + +set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + + +set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + + +set_property LOC OLOGIC_X1Y93 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y81 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] + + + +set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + + + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -setup 6 + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -hold 5 + +set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start + +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20 +set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 +#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] +set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}] + \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a50tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a50tfgg484_pkg.xdc new file mode 100644 index 0000000..74f36dd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a50tfgg484_pkg.xdc @@ -0,0 +1,360 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : ddr3.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A50TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + +# PadFunction: IO_L11N_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L12P_T1_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L8N_T1_AD14N_35 +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN G2 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L7N_T1_AD6N_35 +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L11P_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L7P_T1_AD6P_35 +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L8P_T1_AD14P_35 +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L10P_T1_AD15P_35 +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L6N_T0_VREF_35 +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN E3 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L2P_T0_AD12P_35 +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN C2 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L5N_T0_AD13N_35 +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L4N_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L2N_T0_AD12N_35 +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L1N_T0_AD4N_35 +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN A1 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L4P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L1P_T0_AD4P_35 +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_25_35 +set_property SLEW FAST [get_ports {ddr3_addr[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN L6 [get_ports {ddr3_addr[14]}] + +# PadFunction: IO_L19P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L23N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN M5 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L24N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN N5 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L18P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN L5 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L22P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN P2 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L20P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN R1 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L22N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN N2 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L23P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L16N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN M2 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L20N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN P1 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L18N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN L4 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L19N_T3_VREF_35 +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN N3 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L24P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L16P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN M3 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L17P_T2_35 +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN K6 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L15P_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN M1 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L14P_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN L3 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L17N_T2_35 +set_property SLEW FAST [get_ports {ddr3_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] +set_property PACKAGE_PIN J6 [get_ports {ddr3_ras_n}] + +# PadFunction: IO_L14N_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] +set_property PACKAGE_PIN K3 [get_ports {ddr3_cas_n}] + +# PadFunction: IO_L13P_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] +set_property PACKAGE_PIN K4 [get_ports {ddr3_we_n}] + +# PadFunction: IO_L5P_T0_AD13P_35 +set_property SLEW FAST [get_ports {ddr3_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] +set_property PACKAGE_PIN G1 [get_ports {ddr3_reset_n}] + +# PadFunction: IO_L15N_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN L1 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_L13N_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN J4 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L10N_T1_AD15N_35 +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN H5 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L6P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN F3 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L9P_T1_DQS_AD7P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L9N_T1_DQS_AD7N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN J2 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L3P_T0_DQS_AD5P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN E1 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L3N_T0_DQS_AD5N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN D1 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L21P_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN P5 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L21N_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN P4 [get_ports {ddr3_ck_n[0]}] + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] + + +set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] + + +## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] + + + + + +set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] + + +set_property LOC IN_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] + + +set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + + +set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + + +set_property LOC OLOGIC_X1Y93 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y81 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] + + + +set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + + + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -setup 6 + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -hold 5 + +set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start + +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20 +set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 +#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] +set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}] + \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a75tfgg484_pkg.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a75tfgg484_pkg.xdc new file mode 100644 index 0000000..8d3008d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/compatible_ucf/xc7a75tfgg484_pkg.xdc @@ -0,0 +1,360 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : ddr3.sd +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A75TFGG484_PKG +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + +# PadFunction: IO_L11N_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L12P_T1_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L8N_T1_AD14N_35 +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN G2 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L7N_T1_AD6N_35 +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L11P_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L7P_T1_AD6P_35 +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L8P_T1_AD14P_35 +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L10P_T1_AD15P_35 +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L6N_T0_VREF_35 +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN E3 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L2P_T0_AD12P_35 +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN C2 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L5N_T0_AD13N_35 +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L4N_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L2N_T0_AD12N_35 +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L1N_T0_AD4N_35 +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN A1 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L4P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L1P_T0_AD4P_35 +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_25_35 +set_property SLEW FAST [get_ports {ddr3_addr[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN L6 [get_ports {ddr3_addr[14]}] + +# PadFunction: IO_L19P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L23N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN M5 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L24N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN N5 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L18P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN L5 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L22P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN P2 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L20P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN R1 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L22N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN N2 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L23P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L16N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN M2 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L20N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN P1 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L18N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN L4 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L19N_T3_VREF_35 +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN N3 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L24P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L16P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN M3 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L17P_T2_35 +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN K6 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L15P_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN M1 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L14P_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN L3 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L17N_T2_35 +set_property SLEW FAST [get_ports {ddr3_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] +set_property PACKAGE_PIN J6 [get_ports {ddr3_ras_n}] + +# PadFunction: IO_L14N_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] +set_property PACKAGE_PIN K3 [get_ports {ddr3_cas_n}] + +# PadFunction: IO_L13P_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] +set_property PACKAGE_PIN K4 [get_ports {ddr3_we_n}] + +# PadFunction: IO_L5P_T0_AD13P_35 +set_property SLEW FAST [get_ports {ddr3_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] +set_property PACKAGE_PIN G1 [get_ports {ddr3_reset_n}] + +# PadFunction: IO_L15N_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN L1 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_L13N_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN J4 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L10N_T1_AD15N_35 +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN H5 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L6P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN F3 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L9P_T1_DQS_AD7P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L9N_T1_DQS_AD7N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN J2 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L3P_T0_DQS_AD5P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN E1 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L3N_T0_DQS_AD5N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN D1 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L21P_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN P5 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L21N_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN P4 [get_ports {ddr3_ck_n[0]}] + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] + + +set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] + + +## set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] + + + + + +set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] + + +set_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] + + +set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + + +set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + + +set_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] + + + +set_property LOC PLLE2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + + + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -setup 6 + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -hold 5 + +set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start + +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20 +set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 +#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] +set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}] + \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3.xdc new file mode 100644 index 0000000..a87cd3d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3.xdc @@ -0,0 +1,360 @@ +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : ddr3.xdc +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A35T-FGG484 +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_n[*]} ] +set_property IO_BUFFER_TYPE NONE [get_ports {ddr3_ck_p[*]} ] + +#create_clock -period 3 [get_ports sys_clk_i] + +#create_clock -period 5 [get_ports clk_ref_i] + +############## NET - IOSTANDARD ################## + + +# PadFunction: IO_L11N_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] +set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[0]}] + +# PadFunction: IO_L12P_T1_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] +set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[1]}] + +# PadFunction: IO_L8N_T1_AD14N_35 +set_property SLEW FAST [get_ports {ddr3_dq[2]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] +set_property PACKAGE_PIN G2 [get_ports {ddr3_dq[2]}] + +# PadFunction: IO_L7N_T1_AD6N_35 +set_property SLEW FAST [get_ports {ddr3_dq[3]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] +set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[3]}] + +# PadFunction: IO_L11P_T1_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_dq[4]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] +set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[4]}] + +# PadFunction: IO_L7P_T1_AD6P_35 +set_property SLEW FAST [get_ports {ddr3_dq[5]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] +set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[5]}] + +# PadFunction: IO_L8P_T1_AD14P_35 +set_property SLEW FAST [get_ports {ddr3_dq[6]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] +set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[6]}] + +# PadFunction: IO_L10P_T1_AD15P_35 +set_property SLEW FAST [get_ports {ddr3_dq[7]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] +set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[7]}] + +# PadFunction: IO_L6N_T0_VREF_35 +set_property SLEW FAST [get_ports {ddr3_dq[8]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] +set_property PACKAGE_PIN E3 [get_ports {ddr3_dq[8]}] + +# PadFunction: IO_L2P_T0_AD12P_35 +set_property SLEW FAST [get_ports {ddr3_dq[9]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] +set_property PACKAGE_PIN C2 [get_ports {ddr3_dq[9]}] + +# PadFunction: IO_L5N_T0_AD13N_35 +set_property SLEW FAST [get_ports {ddr3_dq[10]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] +set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[10]}] + +# PadFunction: IO_L4N_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[11]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] +set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[11]}] + +# PadFunction: IO_L2N_T0_AD12N_35 +set_property SLEW FAST [get_ports {ddr3_dq[12]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] +set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[12]}] + +# PadFunction: IO_L1N_T0_AD4N_35 +set_property SLEW FAST [get_ports {ddr3_dq[13]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] +set_property PACKAGE_PIN A1 [get_ports {ddr3_dq[13]}] + +# PadFunction: IO_L4P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dq[14]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] +set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[14]}] + +# PadFunction: IO_L1P_T0_AD4P_35 +set_property SLEW FAST [get_ports {ddr3_dq[15]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] +set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[15]}] + +# PadFunction: IO_25_35 +set_property SLEW FAST [get_ports {ddr3_addr[14]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] +set_property PACKAGE_PIN L6 [get_ports {ddr3_addr[14]}] + +# PadFunction: IO_L19P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] +set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[13]}] + +# PadFunction: IO_L23N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] +set_property PACKAGE_PIN M5 [get_ports {ddr3_addr[12]}] + +# PadFunction: IO_L24N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] +set_property PACKAGE_PIN N5 [get_ports {ddr3_addr[11]}] + +# PadFunction: IO_L18P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] +set_property PACKAGE_PIN L5 [get_ports {ddr3_addr[10]}] + +# PadFunction: IO_L22P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] +set_property PACKAGE_PIN P2 [get_ports {ddr3_addr[9]}] + +# PadFunction: IO_L20P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] +set_property PACKAGE_PIN R1 [get_ports {ddr3_addr[8]}] + +# PadFunction: IO_L22N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] +set_property PACKAGE_PIN N2 [get_ports {ddr3_addr[7]}] + +# PadFunction: IO_L23P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] +set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[6]}] + +# PadFunction: IO_L16N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] +set_property PACKAGE_PIN M2 [get_ports {ddr3_addr[5]}] + +# PadFunction: IO_L20N_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] +set_property PACKAGE_PIN P1 [get_ports {ddr3_addr[4]}] + +# PadFunction: IO_L18N_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] +set_property PACKAGE_PIN L4 [get_ports {ddr3_addr[3]}] + +# PadFunction: IO_L19N_T3_VREF_35 +set_property SLEW FAST [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] +set_property PACKAGE_PIN N3 [get_ports {ddr3_addr[2]}] + +# PadFunction: IO_L24P_T3_35 +set_property SLEW FAST [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] +set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[1]}] + +# PadFunction: IO_L16P_T2_35 +set_property SLEW FAST [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] +set_property PACKAGE_PIN M3 [get_ports {ddr3_addr[0]}] + +# PadFunction: IO_L17P_T2_35 +set_property SLEW FAST [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] +set_property PACKAGE_PIN K6 [get_ports {ddr3_ba[2]}] + +# PadFunction: IO_L15P_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] +set_property PACKAGE_PIN M1 [get_ports {ddr3_ba[1]}] + +# PadFunction: IO_L14P_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_ba[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] +set_property PACKAGE_PIN L3 [get_ports {ddr3_ba[0]}] + +# PadFunction: IO_L17N_T2_35 +set_property SLEW FAST [get_ports {ddr3_ras_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}] +set_property PACKAGE_PIN J6 [get_ports {ddr3_ras_n}] + +# PadFunction: IO_L14N_T2_SRCC_35 +set_property SLEW FAST [get_ports {ddr3_cas_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}] +set_property PACKAGE_PIN K3 [get_ports {ddr3_cas_n}] + +# PadFunction: IO_L13P_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_we_n}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}] +set_property PACKAGE_PIN K4 [get_ports {ddr3_we_n}] + +# PadFunction: IO_L5P_T0_AD13P_35 +set_property SLEW FAST [get_ports {ddr3_reset_n}] +set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}] +set_property PACKAGE_PIN G1 [get_ports {ddr3_reset_n}] + +# PadFunction: IO_L15N_T2_DQS_35 +set_property SLEW FAST [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}] +set_property PACKAGE_PIN L1 [get_ports {ddr3_cke[0]}] + +# PadFunction: IO_L13N_T2_MRCC_35 +set_property SLEW FAST [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}] +set_property PACKAGE_PIN J4 [get_ports {ddr3_odt[0]}] + +# PadFunction: IO_L10N_T1_AD15N_35 +set_property SLEW FAST [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] +set_property PACKAGE_PIN H5 [get_ports {ddr3_dm[0]}] + +# PadFunction: IO_L6P_T0_35 +set_property SLEW FAST [get_ports {ddr3_dm[1]}] +set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] +set_property PACKAGE_PIN F3 [get_ports {ddr3_dm[1]}] + +# PadFunction: IO_L9P_T1_DQS_AD7P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] +set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_p[0]}] + +# PadFunction: IO_L9N_T1_DQS_AD7N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] +set_property PACKAGE_PIN J2 [get_ports {ddr3_dqs_n[0]}] + +# PadFunction: IO_L3P_T0_DQS_AD5P_35 +set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] +set_property PACKAGE_PIN E1 [get_ports {ddr3_dqs_p[1]}] + +# PadFunction: IO_L3N_T0_DQS_AD5N_35 +set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] +set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] +set_property PACKAGE_PIN D1 [get_ports {ddr3_dqs_n[1]}] + +# PadFunction: IO_L21P_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_p[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}] +set_property PACKAGE_PIN P5 [get_ports {ddr3_ck_p[0]}] + +# PadFunction: IO_L21N_T3_DQS_35 +set_property SLEW FAST [get_ports {ddr3_ck_n[0]}] +set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}] +set_property PACKAGE_PIN P4 [get_ports {ddr3_ck_n[0]}] + + +set_property INTERNAL_VREF 0.750 [get_iobanks 35] + + +set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}] +set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}] + + +## set_property LOC PHASER_IN_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}] +## set_property LOC PHASER_IN_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}] +set_property LOC PHASER_IN_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}] + + + + + +set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}] +set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}] +set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}] +set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}] + + +set_property LOC IN_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}] +set_property LOC IN_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}] + + +set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}] + + +set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}] + + +set_property LOC OLOGIC_X1Y93 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}] +set_property LOC OLOGIC_X1Y81 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}] + + + +set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}] +set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}] + + + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -setup 6 + +set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \ + -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \ + -hold 5 + +set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]] + +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start +set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start + +#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20 +set_max_delay -to [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}] 20 +set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5 +#set_false_path -through [get_pins -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst}] +set_false_path -through [get_nets -hier -filter {NAME =~ */u_iodelay_ctrl/sys_rst_i}] + \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3_ooc.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3_ooc.xdc new file mode 100644 index 0000000..d9dda1b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/constraints/ddr3_ooc.xdc @@ -0,0 +1,38 @@ +################################################################################################### +## This constraints file contains default clock frequencies to be used during creation of a +## Synthesis Design Checkpoint (DCP). For best results the frequencies should be modified +## to match the target frequencies. +## This constraints file is not used in top-down/global synthesis (not the default flow of Vivado). +################################################################################################### + + +################################################################################################## +## +## Xilinx, Inc. 2010 www.xilinx.com +## Wed Feb 5 18:48:19 2025 + +## Generated by MIG Version 4.2 +## +################################################################################################## +## File name : ddr3.xdc +## Details : Constraints file +## FPGA Family: ARTIX7 +## FPGA Part: XC7A35T-FGG484 +## Speedgrade: -2 +## Design Entry: VERILOG +## Frequency: 333.32999999999998 MHz +## Time Period: 3000 ps +################################################################################################## + +################################################################################################## +## Controller 0 +## Memory Device: DDR3_SDRAM->Components->MT41K256M16XX-125 +## Data Width: 16 +## Time Period: 3000 +## Data Mask: 1 +################################################################################################## + +create_clock -period 3 [get_ports sys_clk_i] + +create_clock -period 5 [get_ports clk_ref_i] + \ No newline at end of file diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v new file mode 100644 index 0000000..d7fe92d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v @@ -0,0 +1,131 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: clk_ibuf.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ +// \ \ / \ Date Created:Mon Aug 3 2009 +// \___\/\___\ +// +//Device: Virtex-6 +//Design Name: DDR3 SDRAM +//Purpose: +// Clock generation/distribution and reset synchronization +//Reference: +//Revision History: +//***************************************************************************** +`timescale 1ns/1ps + +module mig_7series_v4_2_clk_ibuf # + ( + parameter SYSCLK_TYPE = "DIFFERENTIAL", + // input clock type + parameter DIFF_TERM_SYSCLK = "TRUE" + // Differential Termination + ) + ( + // Clock inputs + input sys_clk_p, // System clock diff input + input sys_clk_n, + input sys_clk_i, + output mmcm_clk + ); + + (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */; + + generate + if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk + + //*********************************************************************** + // Differential input clock input buffers + //*********************************************************************** + + IBUFGDS # + ( + .DIFF_TERM (DIFF_TERM_SYSCLK), + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_sys_clk + ( + .I (sys_clk_p), + .IB (sys_clk_n), + .O (sys_clk_ibufg) + ); + + end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk + + //*********************************************************************** + // SINGLE_ENDED input clock input buffers + //*********************************************************************** + + IBUFG # + ( + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_sys_clk + ( + .I (sys_clk_i), + .O (sys_clk_ibufg) + ); + end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk + + //*********************************************************************** + // System clock is driven from FPGA internal clock (clock from fabric) + //*********************************************************************** + assign sys_clk_ibufg = sys_clk_i; + end + endgenerate + + assign mmcm_clk = sys_clk_ibufg; + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v new file mode 100644 index 0000000..a6661a8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v @@ -0,0 +1,768 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: infrastructure.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ +// \ \ / \ Date Created:Tue Jun 30 2009 +// \___\/\___\ +// +//Device: Virtex-6 +//Design Name: DDR3 SDRAM +//Purpose: +// Clock generation/distribution and reset synchronization +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ +**$Date: 2011/06/02 08:34:56 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + + +module mig_7series_v4_2_infrastructure # + ( + parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and + // FALSE during implementations + parameter TCQ = 100, // clk->out delay (sim only) + parameter CLKIN_PERIOD = 3000, // Memory clock period + parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period + parameter SYSCLK_TYPE = "DIFFERENTIAL", + // input clock type + // "DIFFERENTIAL","SINGLE_ENDED" + parameter UI_EXTRA_CLOCKS = "FALSE", + // Generates extra clocks as + // 1/2, 1/4 and 1/8 of fabrick clock. + // Valid for DDR2/DDR3 AXI interfaces + // based on GUI selection + parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier + parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor + parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 + parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 + parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 + parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 + parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 + parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO + parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier + parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor + parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 + parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 + parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 + parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 + parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 + parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 + parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 + parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 + parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 + parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 + parameter RST_ACT_LOW = 1, + parameter tCK = 1250, + // memory tCK paramter. + // # = Clock Period in pS. + parameter MEM_TYPE = "DDR3" + ) + ( + // Clock inputs + input mmcm_clk, // System clock diff input + // System reset input + input sys_rst, // core reset from user application + // PLLE2/IDELAYCTRL Lock status + input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status + // Clock outputs + + output clk, // fabric clock freq ; either half rate or quarter rate and is + // determined by PLL parameters settings. + output clk_div2, // mem_refclk divided by 2 for PI incdec + output rst_div2, // reset in clk_div2 domain + output mem_refclk, // equal to memory clock + output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk + // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; + // to hard PHY for phaser + output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide +// output auxout_clk, // IO clk used to clock out Aux_Out ports + output mmcm_ps_clk, // Phase shift clock + output poc_sample_pd, // Tell POC when to sample phase detector output. + output ui_addn_clk_0, // MMCM out0 clk + output ui_addn_clk_1, // MMCM out1 clk + output ui_addn_clk_2, // MMCM out2 clk + output ui_addn_clk_3, // MMCM out3 clk + output ui_addn_clk_4, // MMCM out4 clk + output pll_locked, // locked output from PLLE2_ADV + output mmcm_locked, // locked output from MMCME2_ADV + // Reset outputs + output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), + output iddr_rst + + ,output rst_phaser_ref + ,input ref_dll_lock + ,input psen + ,input psincdec + ,output psdone + ); + + // # of clock cycles to delay deassertion of reset. Needs to be a fairly + // high number not so much for metastability protection, but to give time + // for reset (i.e. stable clock cycles) to propagate through all state + // machines and to all control signals (i.e. not all control signals have + // resets, instead they rely on base state logic being reset, and the effect + // of that reset propagating through the logic). Need this because we may not + // be getting stable clock cycles while reset asserted (i.e. since reset + // depends on DCM lock status) + localparam RST_SYNC_NUM = 25; + + // Round up for clk reset delay to ensure that CLKDIV reset deassertion + // occurs at same time or after CLK reset deassertion (still need to + // consider route delay - add one or two extra cycles to be sure!) + localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; + + // Input clock is assumed to be equal to the memory clock frequency + // User should change the parameter as necessary if a different input + // clock frequency is used + localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; + localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; + + localparam integer VCO_PERIOD + = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; + + localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; + localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; + localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; + localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; + localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; + + localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; + + localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; + localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; + + //synthesis translate_off + initial begin + $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); + $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); + $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); + $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); + $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); + $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); + $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); + $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); + $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); + $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); + $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); + $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); + $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); + $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); + $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); + $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); + $display("############################################################\n"); + end + //synthesis translate_on + + wire clk_bufg; + wire clk_pll_i; + wire clkfbout_pll; + wire pll_clkfbout; + wire pll_locked_i + /* synthesis syn_maxfan = 10 */; + (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; + wire rst_tmp; + (* max_fanout = 50 *) reg rstdiv0_sync_r1 + /* synthesis syn_maxfan = 50 */; + reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; + (* max_fanout = 10 *) reg rst_sync_r1 + /* synthesis syn_maxfan = 10 */; + reg [RST_DIV_SYNC_NUM-2:0] rstdiv2_sync_r; + (* max_fanout = 10 *) reg rstdiv2_sync_r1 + /* synthesis syn_maxfan = 10 */; + wire sys_rst_act_hi; + + wire rst_tmp_phaser_ref; + (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r + /* synthesis syn_maxfan = 10 */; + + // Instantiation of the MMCM primitive + wire clkfbout; + wire MMCM_Locked_i; + + wire mmcm_clkout0; + wire mmcm_clkout1; + wire mmcm_clkout2; + wire mmcm_clkout3; + wire mmcm_clkout4; + wire mmcm_ps_clk_bufg_in; + wire clk_div2_bufg_in; + + wire pll_clk3_out; + wire pll_clk3; + + assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; + + //*************************************************************************** + // Assign global clocks: + // 2. clk : Half rate / Quarter rate(used for majority of internal logic) + //*************************************************************************** + + assign clk = clk_bufg; + assign pll_locked = pll_locked_i & MMCM_Locked_i; + assign mmcm_locked = MMCM_Locked_i; + + + //*************************************************************************** + // Global base clock generation and distribution + //*************************************************************************** + + //***************************************************************** + // NOTES ON CALCULTING PROPER VCO FREQUENCY + // 1. VCO frequency = + // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) + // 2. VCO frequency must be in the range [TBD, TBD] + //***************************************************************** + + PLLE2_ADV # + ( + .BANDWIDTH ("OPTIMIZED"), + .COMPENSATION ("INTERNAL"), + .STARTUP_WAIT ("FALSE"), + .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref + .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref + .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync + .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk + .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), + .CLKOUT5_DIVIDE (), + .DIVCLK_DIVIDE (DIVCLK_DIVIDE), + .CLKFBOUT_MULT (CLKFBOUT_MULT), + .CLKFBOUT_PHASE (0.000), + .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), + .CLKIN2_PERIOD (), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_PHASE (CLKOUT0_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (1.0/16.0), + .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_PHASE (0.000), + .CLKOUT4_DUTY_CYCLE (0.500), + .CLKOUT4_PHASE (CLKOUT4_PHASE), + .CLKOUT5_DUTY_CYCLE (0.500), + .CLKOUT5_PHASE (0.000), + .REF_JITTER1 (0.010), + .REF_JITTER2 (0.010) + ) + plle2_i + ( + .CLKFBOUT (pll_clkfbout), + .CLKOUT0 (freq_refclk), + .CLKOUT1 (mem_refclk), + .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk + .CLKOUT3 (pll_clk3_out), +// .CLKOUT4 (auxout_clk_i), + .CLKOUT4 (), + .CLKOUT5 (), + .DO (), + .DRDY (), + .LOCKED (pll_locked_i), + .CLKFBIN (pll_clkfbout), + .CLKIN1 (mmcm_clk), + .CLKIN2 (), + .CLKINSEL (1'b1), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DWE (1'b0), + .PWRDWN (1'b0), + .RST ( sys_rst_act_hi) + ); + + +// BUFH u_bufh_auxout_clk +// ( +// .O (auxout_clk), +// .I (auxout_clk_i) +// ); + + BUFG u_bufg_clkdiv0 + ( + .O (clk_bufg), + .I (clk_pll_i) + ); + + BUFH u_bufh_pll_clk3 + ( + .O (pll_clk3), + .I (pll_clk3_out) + ); + + localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; + + //synthesis translate_off + initial begin + $display("############# MMCME2_ADV Parameters #############\n"); + $display("MMCM_MULT_F = %d", MMCM_MULT_F); +// $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); + $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1.000); + $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); + $display("#################################################\n"); + end + //synthesis translate_on + + generate + if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks + + localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; + localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; + + MMCME2_ADV + #(.BANDWIDTH ("HIGH"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("BUF_IN"), + .STARTUP_WAIT ("FALSE"), +// .DIVCLK_DIVIDE (1), + .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), + .CLKFBOUT_MULT_F (MMCM_MULT_F), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), + .CLKOUT2_PHASE (0.000), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), + .CLKOUT3_PHASE (0.000), + .CLKOUT3_DUTY_CYCLE (0.500), + .CLKOUT3_USE_FINE_PS ("FALSE"), + .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), + .CLKOUT4_PHASE (0.000), + .CLKOUT4_DUTY_CYCLE (0.500), + .CLKOUT4_USE_FINE_PS ("FALSE"), + .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), + .CLKOUT5_PHASE (0.000), + .CLKOUT5_DUTY_CYCLE (0.500), + .CLKOUT5_USE_FINE_PS ("TRUE"), + .CLKOUT6_DIVIDE (MMCM_MULT_F/2), + .CLKOUT6_PHASE (0.000), + .CLKOUT6_DUTY_CYCLE (0.500), + .CLKOUT6_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), + .REF_JITTER1 (0.000)) + mmcm_i + // Output clocks + (.CLKFBOUT (clk_pll_i), + .CLKFBOUTB (), + .CLKOUT0 (mmcm_clkout0), + .CLKOUT0B (), + .CLKOUT1 (mmcm_clkout1), + .CLKOUT1B (), + .CLKOUT2 (mmcm_clkout2), + .CLKOUT2B (), + .CLKOUT3 (mmcm_clkout3), + .CLKOUT3B (), + .CLKOUT4 (mmcm_clkout4), + .CLKOUT5 (mmcm_ps_clk_bufg_in), + .CLKOUT6 (clk_div2_bufg_in), + // Input clock control + .CLKFBIN (clk_bufg), // From BUFH network + .CLKIN1 (pll_clk3), // From PLL + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (clk), + .PSEN (psen), + .PSINCDEC (psincdec), + .PSDONE (psdone), + // Other control and status signals + .LOCKED (MMCM_Locked_i), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (~pll_locked_i)); + + BUFG u_bufg_ui_addn_clk_0 + ( + .O (ui_addn_clk_0), + .I (mmcm_clkout0) + ); + + BUFG u_bufg_ui_addn_clk_1 + ( + .O (ui_addn_clk_1), + .I (mmcm_clkout1) + ); + + BUFG u_bufg_ui_addn_clk_2 + ( + .O (ui_addn_clk_2), + .I (mmcm_clkout2) + ); + + BUFG u_bufg_ui_addn_clk_3 + ( + .O (ui_addn_clk_3), + .I (mmcm_clkout3) + ); + + BUFG u_bufg_ui_addn_clk_4 + ( + .O (ui_addn_clk_4), + .I (mmcm_clkout4) + ); + + BUFG u_bufg_mmcm_ps_clk + ( + .O (mmcm_ps_clk), + .I (mmcm_ps_clk_bufg_in) + ); + + BUFG u_bufg_clk_div2 + ( + .O (clk_div2), + .I (clk_div2_bufg_in) + ); + end else begin: gen_mmcm + + MMCME2_ADV + #(.BANDWIDTH ("HIGH"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("BUF_IN"), + .STARTUP_WAIT ("FALSE"), +// .DIVCLK_DIVIDE (1), + .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), + .CLKFBOUT_MULT_F (MMCM_MULT_F), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("TRUE"), + .CLKOUT1_DIVIDE (MMCM_MULT_F/2), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), + .REF_JITTER1 (0.000)) + mmcm_i + // Output clocks + (.CLKFBOUT (clk_pll_i), + .CLKFBOUTB (), + .CLKOUT0 (mmcm_ps_clk_bufg_in), + .CLKOUT0B (), + .CLKOUT1 (clk_div2_bufg_in), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (clk_bufg), // From BUFH network + .CLKIN1 (pll_clk3), // From PLL + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (clk), + .PSEN (psen), + .PSINCDEC (psincdec), + .PSDONE (psdone), + // Other control and status signals + .LOCKED (MMCM_Locked_i), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (~pll_locked_i)); + + BUFG u_bufg_mmcm_ps_clk + ( + .O (mmcm_ps_clk), + .I (mmcm_ps_clk_bufg_in) + ); + + BUFG u_bufg_clk_div2 + ( + .O (clk_div2), + .I (clk_div2_bufg_in) + ); + + end // block: gen_mmcm + endgenerate + + //*************************************************************************** + // Generate poc_sample_pd. + // + // As the phase shift clocks precesses around kclk, it also precesses + // around the fabric clock. Noise may be generated as output of the + // IDDR is registered into the fabric clock domain. + // + // The mmcm_ps_clk signal runs at half the rate of the fabric clock. + // This means that there are two rising edges of fabric clock per mmcm_ps_clk. + // If we can guarantee that the POC uses the data sampled on the second + // fabric clock, then we are certain that the setup time to the second + // fabric clock is greater than 1 fabric clock cycle. + // + // To predict when the phase detctor output is from this second edge, we + // need to know two things. The initial phase of fabric clock and mmcm_ps_clk + // and the number of phase offsets set into the mmcm. The later is a + // trivial count of the PSEN signal. + // + // The former is a bit tricky because latching a clock with a clock is + // not well defined. This problem is solved by generating a signal + // the goes high on the first rising edge of mmcm_ps_clk. Logic in + // the fabric domain can look at this signal and then develop an analog + // the mmcm_ps_clk with zero offset. + // + // This all depends on the timing tools making the timing work when + // when the mmcm phase offset is zero. + // + // poc_sample_pd tells the POC when to sample the phase detector output. + // Setup from the IDDR to the fabric clock is always one plus some + // fraction of the fabric clock. + //*************************************************************************** + + localparam ONE = 1; + localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; + localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; + localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; + always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; + + reg inv_poc_sample_ns, inv_poc_sample_r; + always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; + + always @(*) begin + qcntr_ns = qcntr_r; + inv_poc_sample_ns = inv_poc_sample_r; + if (rstdiv0) begin + qcntr_ns = 'b0; + inv_poc_sample_ns = 'b0; + end else if (psen) begin + if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) + qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); + else begin + qcntr_ns = {QCNTR_WIDTH{1'b0}}; + inv_poc_sample_ns = ~inv_poc_sample_r; + end + end + end + + // Be vewy vewy careful to make sure this path is aligned with the + // phase detector out pipeline. + reg first_rising_ps_clk_ns, first_rising_ps_clk_r; + always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; + always @(*) first_rising_ps_clk_ns = ~rstdiv0; + + reg mmcm_hi0_ns, mmcm_hi0_r; + always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; + always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; + + reg poc_sample_pd_ns, poc_sample_pd_r; + always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; + always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; + assign poc_sample_pd = poc_sample_pd_r; + + //*************************************************************************** + // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk + // to the appropriate edge of fabric clock + //*************************************************************************** + + //synthesis translate_off + generate + if ( tCK <= 2500 ) begin : check_ocal_timing + localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; + localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; + + time rising_mmcm_ps_clk; + always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); + + time pdiff; // Not used, except in waveform plots. + always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; + end + endgenerate + + //synthesis translate_on + + //*************************************************************************** + // RESET SYNCHRONIZATION DESCRIPTION: + // Various resets are generated to ensure that: + // 1. All resets are synchronously deasserted with respect to the clock + // domain they are interfacing to. There are several different clock + // domains - each one will receive a synchronized reset. + // 2. The reset deassertion order starts with deassertion of SYS_RST, + // followed by deassertion of resets for various parts of the design + // (see "RESET ORDER" below) based on the lock status of PLLE2s. + // RESET ORDER: + // 1. User deasserts SYS_RST + // 2. Reset PLLE2 and IDELAYCTRL + // 3. Wait for PLLE2 and IDELAYCTRL to lock + // 4. Release reset for all I/O primitives and internal logic + // OTHER NOTES: + // 1. Asynchronously assert reset. This way we can assert reset even if + // there is no clock (needed for things like 3-stating output buffers + // to prevent initial bus contention). Reset deassertion is synchronous. + //*************************************************************************** + + //***************************************************************** + // CLKDIV logic reset + //***************************************************************** + + // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset + + // current O,25.0 unisim phaser_ref never locks. Need to find out why . + generate + if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 + assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | + ~ref_dll_lock | ~MMCM_Locked_i; + end else begin: rst_tmp_200 + assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | + ~ref_dll_lock | ~MMCM_Locked_i; + end + endgenerate + + always @(posedge clk_bufg or posedge rst_tmp) begin + if (rst_tmp) begin + rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; + rstdiv0_sync_r1 <= #TCQ 1'b1 ; + end else begin + rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; + rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; + end + end + + assign rstdiv0 = rstdiv0_sync_r1 ; + +//IDDR rest + always @(posedge mmcm_ps_clk or posedge rst_tmp) begin + if (rst_tmp) begin + rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; + rst_sync_r1 <= #TCQ 1'b1 ; + end else begin + rst_sync_r <= #TCQ rst_sync_r << 1; + rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; + end + end + + assign iddr_rst = rst_sync_r1 ; + +// Sync reset in the clk_div2 domain + always @(posedge clk_div2 or posedge rst_tmp) begin + if (rst_tmp) begin + rstdiv2_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; + rstdiv2_sync_r1 <= #TCQ 1'b1 ; + end else begin + rstdiv2_sync_r <= #TCQ rstdiv2_sync_r << 1; + rstdiv2_sync_r1 <= #TCQ rstdiv2_sync_r[RST_DIV_SYNC_NUM-2]; + end + end + + assign rst_div2 = rstdiv2_sync_r1 ; + + generate + if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 + assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; + end else begin: rst_tmp_phaser_ref_200 + assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; + end + endgenerate + + always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) + if (rst_tmp_phaser_ref) + rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; + else + rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; + + assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v new file mode 100644 index 0000000..e5c1bdf --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v @@ -0,0 +1,359 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: iodelay_ctrl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ +// \ \ / \ Date Created: Wed Aug 16 2006 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// This module instantiates the IDELAYCTRL primitive, which continously +// calibrates the IODELAY elements in the region to account for varying +// environmental conditions. A 200MHz or 300MHz reference clock (depending +// on the desired IODELAY tap resolution) must be supplied +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ +**$Date: 2011/06/02 08:34:56 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_iodelay_ctrl # + ( + parameter TCQ = 100, + // clk->out delay (sim only) + parameter IODELAY_GRP0 = "IODELAY_MIG0", + // May be assigned unique name when + // multiple IP cores used in design + parameter IODELAY_GRP1 = "IODELAY_MIG1", + // May be assigned unique name when + // multiple IP cores used in design + parameter REFCLK_TYPE = "DIFFERENTIAL", + // Reference clock type + // "DIFFERENTIAL","SINGLE_ENDED" + // NO_BUFFER, USE_SYSTEM_CLOCK + parameter SYSCLK_TYPE = "DIFFERENTIAL", + // input clock type + // DIFFERENTIAL, SINGLE_ENDED, + // NO_BUFFER + parameter SYS_RST_PORT = "FALSE", + // "TRUE" - if pin is selected for sys_rst + // and IBUF will be instantiated. + // "FALSE" - if pin is not selected for sys_rst + parameter RST_ACT_LOW = 1, + // Reset input polarity + // (0 = active high, 1 = active low) + parameter DIFF_TERM_REFCLK = "TRUE", + // Differential Termination + parameter FPGA_SPEED_GRADE = 1, + // FPGA speed grade + parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE" + ) + ( + input clk_ref_p, + input clk_ref_n, + input clk_ref_i, + input sys_rst, + output [1:0] clk_ref, + output sys_rst_o, + output [1:0] iodelay_ctrl_rdy + ); + + // # of clock cycles to delay deassertion of reset. Needs to be a fairly + // high number not so much for metastability protection, but to give time + // for reset (i.e. stable clock cycles) to propagate through all state + // machines and to all control signals (i.e. not all control signals have + // resets, instead they rely on base state logic being reset, and the effect + // of that reset propagating through the logic). Need this because we may not + // be getting stable clock cycles while reset asserted (i.e. since reset + // depends on DCM lock status) + // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger # + localparam RST_SYNC_NUM = 15; + // localparam RST_SYNC_NUM = 25; + + wire clk_ref_ibufg; + wire clk_ref_mmcm_300; + wire clk_ref_mmcm_400; + wire mmcm_clkfbout; + wire mmcm_Locked; + wire [1:0] rst_ref; + reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */; + wire rst_tmp_idelay; + wire sys_rst_act_hi; + (* keep = "TRUE" *) wire sys_rst_i; + + //*************************************************************************** + + assign sys_rst_o = sys_rst_i; + + // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. + // If the pin is not selected in GUI, sys_rst signal is expected to be + // driven internally. + generate + if (SYS_RST_PORT == "TRUE") + IBUF u_sys_rst_ibuf + ( + .I (sys_rst), + .O (sys_rst_i) + ); + else + assign sys_rst_i = sys_rst; + endgenerate + + // Possible inversion of system reset as appropriate + assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_i: sys_rst_i; + + //*************************************************************************** + // 1) Input buffer for IDELAYCTRL reference clock - handle either a + // differential or single-ended input. Global clock buffer is used to + // drive the rest of FPGA logic. + // 2) For NO_BUFFER option, Reference clock will be driven from internal + // clock i.e., clock is driven from fabric. Input buffers and Global + // clock buffers will not be instaitaed. + // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used + // as the input reference clock. Global clock buffer is used to drive + // the rest of FPGA logic. + //*************************************************************************** + + generate + if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref + IBUFGDS # + ( + .DIFF_TERM (DIFF_TERM_REFCLK), + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_clk_ref + ( + .I (clk_ref_p), + .IB (clk_ref_n), + .O (clk_ref_ibufg) + ); + + end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref + IBUFG # + ( + .IBUF_LOW_PWR ("FALSE") + ) + u_ibufg_clk_ref + ( + .I (clk_ref_i), + .O (clk_ref_ibufg) + ); + + end else if ((REFCLK_TYPE == "NO_BUFFER") || + (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf + assign clk_ref_ibufg = clk_ref_i; + end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf + assign clk_ref_ibufg = clk_ref_i; + end + endgenerate + + // reference clock 300MHz and 400MHz generation with MMCM + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen + + MMCME2_ADV + #(.BANDWIDTH ("HIGH"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("INTERNAL"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (6), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (4), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (3), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (5), + .REF_JITTER1 (0.000)) + mmcm_i + // Output clocks + (.CLKFBOUT (mmcm_clkfbout), + .CLKFBOUTB (), + .CLKOUT0 (clk_ref_mmcm_300), + .CLKOUT0B (), + .CLKOUT1 (clk_ref_mmcm_400), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + // Input clock control + .CLKFBIN (mmcm_clkfbout), + .CLKIN1 (clk_ref_ibufg), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (), + .DRDY (), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + // Other control and status signals + .LOCKED (mmcm_Locked), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (sys_rst_act_hi)); + end + endgenerate + + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en + if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300 + BUFG u_bufg_clk_ref_300 + ( + .O (clk_ref[1]), + .I (clk_ref_mmcm_300) + ); + end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400 + BUFG u_bufg_clk_ref_400 + ( + .O (clk_ref[1]), + .I (clk_ref_mmcm_400) + ); + end + end + endgenerate + + generate + if ((REFCLK_TYPE == "DIFFERENTIAL") || + (REFCLK_TYPE == "SINGLE_ENDED") || + (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200 + BUFG u_bufg_clk_ref + ( + .O (clk_ref[0]), + .I (clk_ref_ibufg) + ); + end else begin: clk_ref_200_no_buffer + assign clk_ref[0] = clk_ref_i; + end + endgenerate + + //***************************************************************** + // IDELAYCTRL reset + // This assumes an external clock signal driving the IDELAYCTRL + // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL + // lock signal will need to be incorporated in this. + //***************************************************************** + + // Add PLL lock if PLL drives IDELAYCTRL in user design + assign rst_tmp_idelay = sys_rst_act_hi; + + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1 + always @(posedge clk_ref[1] or posedge rst_tmp_idelay) + if (rst_tmp_idelay) + rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}}; + else + rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1; + + assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1]; + end + endgenerate + + always @(posedge clk_ref[0] or posedge rst_tmp_idelay) + if (rst_tmp_idelay) + rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}}; + else + rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1; + + assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1]; + + //***************************************************************** + + generate + if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1 + (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400 + ( + .RDY (iodelay_ctrl_rdy[1]), + .REFCLK (clk_ref[1]), + .RST (rst_ref[1]) + ); + end + endgenerate + + (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200 + ( + .RDY (iodelay_ctrl_rdy[0]), + .REFCLK (clk_ref[0]), + .RST (rst_ref[0]) + ); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v new file mode 100644 index 0000000..7424987 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v @@ -0,0 +1,382 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : mig_7series_v4_2_tempmon.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Jul 25 2012 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Monitors chip temperature via the XADC and adjusts the +// stage 2 tap values as appropriate. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_tempmon # +( + parameter TCQ = 100, // Register delay (sim only) + parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source + parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) + parameter tTEMPSAMPLE = 10000000 // ps (10 us) +) +( + input clk, // Fabric clock + input xadc_clk, + input rst, // System reset + input [11:0] device_temp_i, // User device temperature + output [11:0] device_temp // Sampled temperature +); + + //*************************************************************************** + // Function cdiv + // Description: + // This function performs ceiling division (divide and round-up) + // Inputs: + // num: integer to be divided + // div: divisor + // Outputs: + // cdiv: result of ceiling division (num/div, rounded up) + //*************************************************************************** + + function integer cdiv (input integer num, input integer div); + begin + // perform division, then add 1 if and only if remainder is non-zero + cdiv = (num/div) + (((num%div)>0) ? 1 : 0); + end + endfunction // cdiv + + //*************************************************************************** + // Function clogb2 + // Description: + // This function performs binary logarithm and rounds up + // Inputs: + // size: integer to perform binary log upon + // Outputs: + // clogb2: result of binary logarithm, rounded up + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + + size = size - 1; + + // increment clogb2 from 1 for each bit in size + for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) + size = size >> 1; + + end + + endfunction // clogb2 + + // Synchronization registers + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; + + // Output register + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; + + wire [11:0] device_temp_lcl; + reg [3:0] sync_cntr = 4'b0000; + reg device_temp_sync_r4_neq_r3; + + // (* ASYNC_REG = "TRUE" *) reg rst_r1; + // (* ASYNC_REG = "TRUE" *) reg rst_r2; + + // // Synchronization rst to XADC clock domain + // always @(posedge xadc_clk) begin + // rst_r1 <= rst; + // rst_r2 <= rst_r1; + // end + + // Synchronization counter + always @(posedge clk) begin + + device_temp_sync_r1 <= #TCQ device_temp_lcl; + device_temp_sync_r2 <= #TCQ device_temp_sync_r1; + device_temp_sync_r3 <= #TCQ device_temp_sync_r2; + device_temp_sync_r4 <= #TCQ device_temp_sync_r3; + device_temp_sync_r5 <= #TCQ device_temp_sync_r4; + + device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; + + end + + always @(posedge clk) + if(rst || (device_temp_sync_r4_neq_r3)) + sync_cntr <= #TCQ 4'b0000; + else if(~&sync_cntr) + sync_cntr <= #TCQ sync_cntr + 4'b0001; + + always @(posedge clk) + if(&sync_cntr) + device_temp_r <= #TCQ device_temp_sync_r5; + + assign device_temp = device_temp_r; + + generate + + if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature + + assign device_temp_lcl = device_temp_i; + + end else begin : xadc_supplied_temperature + + // calculate polling timer width and limit + localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); + localparam nTEMPSAMP_CLKS = nTEMPSAMP; + localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; + localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); + + // Temperature sampler FSM encoding + localparam INIT_IDLE = 2'b00; + localparam REQUEST_READ_TEMP = 2'b01; + localparam WAIT_FOR_READ = 2'b10; + localparam READ = 2'b11; + + // polling timer and tick + reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; + reg sample_timer_en = 1'b0; + reg sample_timer_clr = 1'b0; + reg sample_en = 1'b0; + + // Temperature sampler state + reg [2:0] tempmon_state = INIT_IDLE; + reg [2:0] tempmon_next_state = INIT_IDLE; + + // XADC interfacing + reg xadc_den = 1'b0; + wire xadc_drdy; + wire [15:0] xadc_do; + reg xadc_drdy_r = 1'b0; + reg [15:0] xadc_do_r = 1'b0; + + // Temperature storage + reg [11:0] temperature = 12'b0; + + // Reset sync + (* ASYNC_REG = "TRUE" *) reg rst_r1; + (* ASYNC_REG = "TRUE" *) reg rst_r2; + + // Synchronization rst to XADC clock domain + always @(posedge xadc_clk) begin + rst_r1 <= rst; + rst_r2 <= rst_r1; + end + + // XADC polling interval timer + always @ (posedge xadc_clk) + if(rst_r2 || sample_timer_clr) + sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; + else if(sample_timer_en) + sample_timer <= #TCQ sample_timer + 1'b1; + + // XADC sampler state transition + always @(posedge xadc_clk) + if(rst_r2) + tempmon_state <= #TCQ INIT_IDLE; + else + tempmon_state <= #TCQ tempmon_next_state; + + // Sample enable + always @(posedge xadc_clk) + sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; + + // XADC sampler next state transition + always @(tempmon_state or sample_en or xadc_drdy_r) begin + + tempmon_next_state = tempmon_state; + + case(tempmon_state) + + INIT_IDLE: + if(sample_en) + tempmon_next_state = REQUEST_READ_TEMP; + + REQUEST_READ_TEMP: + tempmon_next_state = WAIT_FOR_READ; + + WAIT_FOR_READ: + if(xadc_drdy_r) + tempmon_next_state = READ; + + READ: + tempmon_next_state = INIT_IDLE; + + default: + tempmon_next_state = INIT_IDLE; + + endcase + + end + + // Sample timer clear + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) + sample_timer_clr <= #TCQ 1'b0; + else if(tempmon_state == REQUEST_READ_TEMP) + sample_timer_clr <= #TCQ 1'b1; + + // Sample timer enable + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) + sample_timer_en <= #TCQ 1'b0; + else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) + sample_timer_en <= #TCQ 1'b1; + + // XADC enable + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) + xadc_den <= #TCQ 1'b0; + else if(tempmon_state == REQUEST_READ_TEMP) + xadc_den <= #TCQ 1'b1; + + // Register XADC outputs + always @(posedge xadc_clk) + if(rst_r2) begin + xadc_drdy_r <= #TCQ 1'b0; + xadc_do_r <= #TCQ 16'b0; + end + else begin + xadc_drdy_r <= #TCQ xadc_drdy; + xadc_do_r <= #TCQ xadc_do; + end + + // Store current read value + always @(posedge xadc_clk) + if(rst_r2) + temperature <= #TCQ 12'b0; + else if(tempmon_state == READ) + temperature <= #TCQ xadc_do_r[15:4]; + + assign device_temp_lcl = temperature; + + // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter + // 7 Series + // Xilinx HDL Libraries Guide, version 14.1 + XADC #( + // INIT_40 - INIT_42: XADC configuration registers + .INIT_40(16'h1000), // config reg 0 + .INIT_41(16'h2fff), // config reg 1 + .INIT_42(16'h0800), // config reg 2 + // INIT_48 - INIT_4F: Sequence Registers + .INIT_48(16'h0101), // Sequencer channel selection + .INIT_49(16'h0000), // Sequencer channel selection + .INIT_4A(16'h0100), // Sequencer Average selection + .INIT_4B(16'h0000), // Sequencer Average selection + .INIT_4C(16'h0000), // Sequencer Bipolar selection + .INIT_4D(16'h0000), // Sequencer Bipolar selection + .INIT_4E(16'h0000), // Sequencer Acq time selection + .INIT_4F(16'h0000), // Sequencer Acq time selection + // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers + .INIT_50(16'hb5ed), // Temp alarm trigger + .INIT_51(16'h57e4), // Vccint upper alarm limit + .INIT_52(16'ha147), // Vccaux upper alarm limit + .INIT_53(16'hca33), // Temp alarm OT upper + .INIT_54(16'ha93a), // Temp alarm reset + .INIT_55(16'h52c6), // Vccint lower alarm limit + .INIT_56(16'h9555), // Vccaux lower alarm limit + .INIT_57(16'hae4e), // Temp alarm OT reset + .INIT_58(16'h5999), // VBRAM upper alarm limit + .INIT_5C(16'h5111), // VBRAM lower alarm limit + // Simulation attributes: Set for proepr simulation behavior + .SIM_DEVICE("7SERIES") // Select target device (values) + ) + XADC_inst ( + // ALARMS: 8-bit (each) output: ALM, OT + .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram + .OT(), // 1-bit output: Over-Temperature alarm + // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports + .DO(xadc_do), // 16-bit output: DRP output data bus + .DRDY(xadc_drdy), // 1-bit output: DRP data ready + // STATUS: 1-bit (each) output: XADC status ports + .BUSY(), // 1-bit output: ADC busy output + .CHANNEL(), // 5-bit output: Channel selection outputs + .EOC(), // 1-bit output: End of Conversion + .EOS(), // 1-bit output: End of Sequence + .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output + .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock + .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred + .MUXADDR(), // 5-bit output: External MUX channel decode + // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] + .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input + .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input + // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs + .CONVST(1'b0), // 1-bit input: Convert start input + .CONVSTCLK(1'b0), // 1-bit input: Convert start input + .RESET(1'b0), // 1-bit input: Active-high reset + // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN + .VN(1'b0), // 1-bit input: N-side analog input + .VP(1'b0), // 1-bit input: P-side analog input + // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports + .DADDR(7'b0), // 7-bit input: DRP address bus + .DCLK(xadc_clk), // 1-bit input: DRP clock + .DEN(xadc_den), // 1-bit input: DRP enable signal + .DI(16'b0), // 16-bit input: DRP input data bus + .DWE(1'b0) // 1-bit input: DRP write enable + ); + + // End of XADC_inst instantiation + + end + + endgenerate + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v new file mode 100644 index 0000000..892a657 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v @@ -0,0 +1,373 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : arb_mux.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + + +`timescale 1ps/1ps + +module mig_7series_v4_2_arb_mux # + ( + parameter TCQ = 100, + parameter EVEN_CWL_2T_MODE = "OFF", + parameter ADDR_CMD_MODE = "1T", + parameter BANK_VECT_INDX = 11, + parameter BANK_WIDTH = 3, + parameter BURST_MODE = "8", + parameter CS_WIDTH = 4, + parameter CL = 5, + parameter CWL = 5, + parameter DATA_BUF_ADDR_VECT_INDX = 31, + parameter DATA_BUF_ADDR_WIDTH = 8, + parameter DRAM_TYPE = "DDR3", + parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal + parameter EARLY_WR_DATA_ADDR = "OFF", + parameter ECC = "OFF", + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs + parameter nCS_PER_RANK = 1, + parameter nRAS = 37500, // ACT->PRE cmd period (CKs) + parameter nRCD = 12500, // ACT->R/W delay (CKs) + parameter nSLOTS = 2, + parameter nWR = 6, // Write recovery (CKs) + parameter RANKS = 1, + parameter RANK_VECT_INDX = 15, + parameter RANK_WIDTH = 2, + parameter ROW_VECT_INDX = 63, + parameter ROW_WIDTH = 16, + parameter RTT_NOM = "40", + parameter RTT_WR = "120", + parameter SLOT_0_CONFIG = 8'b0000_0101, + parameter SLOT_1_CONFIG = 8'b0000_1010 + ) + (/*AUTOARG*/ + // Outputs + output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v + output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v + output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v + output col_periodic_rd, // From arb_select0 of arb_select.v + output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v + output col_rmw, // From arb_select0 of arb_select.v + output col_rd_wr, + output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v + output col_size, // From arb_select0 of arb_select.v + output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v + output wire [nCK_PER_CLK-1:0] mc_ras_n, + output wire [nCK_PER_CLK-1:0] mc_cas_n, + output wire [nCK_PER_CLK-1:0] mc_we_n, + output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, + output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, + output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, + output wire [1:0] mc_odt, + output wire [nCK_PER_CLK-1:0] mc_cke, + output wire [3:0] mc_aux_out0, + output wire [3:0] mc_aux_out1, + output [2:0] mc_cmd, + output [5:0] mc_data_offset, + output [5:0] mc_data_offset_1, + output [5:0] mc_data_offset_2, + output [1:0] mc_cas_slot, + output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v + output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v + output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v + output [nBANK_MACHS-1:0] sending_pre, + output sent_col, // From arb_row_col0 of arb_row_col.v + output sent_col_r, // From arb_row_col0 of arb_row_col.v + output sent_row, // From arb_row_col0 of arb_row_col.v + output [nBANK_MACHS-1:0] sending_col, + output rnk_config_strobe, + output insert_maint_r1, + output rnk_config_kill_rts_col, + + // Inputs + input clk, + input rst, + input init_calib_complete, + input [6*RANKS-1:0] calib_rddata_offset, + input [6*RANKS-1:0] calib_rddata_offset_1, + input [6*RANKS-1:0] calib_rddata_offset_2, + input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v + input insert_maint_r, // To arb_row_col0 of arb_row_col.v + input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v + input maint_zq_r, // To arb_select0 of arb_select.v + input maint_sre_r, // To arb_select0 of arb_select.v + input maint_srx_r, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v + input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v + input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v + input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v + input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v + input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v + input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v + input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v + input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v + input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v + input [7:0] slot_0_present, // To arb_select0 of arb_select.v + input [7:0] slot_1_present // To arb_select0 of arb_select.v + + ); + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + // End of automatics + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + + // End of automatics + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire cs_en0; // From arb_row_col0 of arb_row_col.v + wire cs_en1; // From arb_row_col0 of arb_row_col.v + wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v + wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v + wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v + wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v + wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v + wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v + wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v + wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v + wire send_cmd1_col; + wire send_cmd2_row; + wire send_cmd2_col; + wire send_cmd2_pre; + wire send_cmd3_col; + wire [5:0] col_channel_offset; + // End of automatics + + wire sent_col_i; + wire cs_en2; + wire cs_en3; + assign sent_col = sent_col_i; + + mig_7series_v4_2_arb_row_col # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .CWL (CWL), + .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), + .nBANK_MACHS (nBANK_MACHS), + .nCK_PER_CLK (nCK_PER_CLK), + .nRAS (nRAS), + .nRCD (nRCD), + .nWR (nWR)) + arb_row_col0 + (/*AUTOINST*/ + // Outputs + .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), + .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), + .sent_row (sent_row), + .sending_row (sending_row[nBANK_MACHS-1:0]), + .sending_pre (sending_pre[nBANK_MACHS-1:0]), + .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), + .rnk_config_strobe (rnk_config_strobe), + .rnk_config_kill_rts_col (rnk_config_kill_rts_col), + .rnk_config_valid_r (rnk_config_valid_r), + .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), + .sending_col (sending_col[nBANK_MACHS-1:0]), + .sent_col (sent_col_i), + .sent_col_r (sent_col_r), + .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), + .send_cmd0_row (send_cmd0_row), + .send_cmd0_col (send_cmd0_col), + .send_cmd1_row (send_cmd1_row), + .send_cmd1_col (send_cmd1_col), + .send_cmd2_row (send_cmd2_row), + .send_cmd2_col (send_cmd2_col), + .send_cmd2_pre (send_cmd2_pre), + .send_cmd3_col (send_cmd3_col), + .col_channel_offset (col_channel_offset), + .cs_en0 (cs_en0), + .cs_en1 (cs_en1), + .cs_en2 (cs_en2), + .cs_en3 (cs_en3), + .insert_maint_r1 (insert_maint_r1), + // Inputs + .clk (clk), + .rst (rst), + .rts_row (rts_row[nBANK_MACHS-1:0]), + .rts_pre (rts_pre[nBANK_MACHS-1:0]), + .insert_maint_r (insert_maint_r), + .rts_col (rts_col[nBANK_MACHS-1:0]), + .rtc (rtc[nBANK_MACHS-1:0]), + .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0])); + + mig_7series_v4_2_arb_select # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ), + .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .BANK_VECT_INDX (BANK_VECT_INDX), + .BANK_WIDTH (BANK_WIDTH), + .BURST_MODE (BURST_MODE), + .CS_WIDTH (CS_WIDTH), + .CL (CL), + .CWL (CWL), + .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), + .ECC (ECC), + .CKE_ODT_AUX (CKE_ODT_AUX), + .nBANK_MACHS (nBANK_MACHS), + .nCK_PER_CLK (nCK_PER_CLK), + .nCS_PER_RANK (nCS_PER_RANK), + .nSLOTS (nSLOTS), + .RANKS (RANKS), + .RANK_VECT_INDX (RANK_VECT_INDX), + .RANK_WIDTH (RANK_WIDTH), + .ROW_VECT_INDX (ROW_VECT_INDX), + .ROW_WIDTH (ROW_WIDTH), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .SLOT_0_CONFIG (SLOT_0_CONFIG), + .SLOT_1_CONFIG (SLOT_1_CONFIG)) + arb_select0 + (/*AUTOINST*/ + // Outputs + .col_periodic_rd (col_periodic_rd), + .col_ra (col_ra[RANK_WIDTH-1:0]), + .col_ba (col_ba[BANK_WIDTH-1:0]), + .col_a (col_a[ROW_WIDTH-1:0]), + .col_rmw (col_rmw), + .col_rd_wr (col_rd_wr), + .col_size (col_size), + .col_row (col_row[ROW_WIDTH-1:0]), + .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .mc_bank (mc_bank), + .mc_address (mc_address), + .mc_ras_n (mc_ras_n), + .mc_cas_n (mc_cas_n), + .mc_we_n (mc_we_n), + .mc_cs_n (mc_cs_n), + .mc_odt (mc_odt), + .mc_cke (mc_cke), + .mc_aux_out0 (mc_aux_out0), + .mc_aux_out1 (mc_aux_out1), + .mc_cmd (mc_cmd), + .mc_data_offset (mc_data_offset), + .mc_data_offset_1 (mc_data_offset_1), + .mc_data_offset_2 (mc_data_offset_2), + .mc_cas_slot (mc_cas_slot), + .col_channel_offset (col_channel_offset), + .rnk_config (rnk_config), + // Inputs + .clk (clk), + .rst (rst), + .init_calib_complete (init_calib_complete), + .calib_rddata_offset (calib_rddata_offset), + .calib_rddata_offset_1 (calib_rddata_offset_1), + .calib_rddata_offset_2 (calib_rddata_offset_2), + .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), + .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), + .req_ras (req_ras[nBANK_MACHS-1:0]), + .req_cas (req_cas[nBANK_MACHS-1:0]), + .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), + .grant_row_r (grant_row_r[nBANK_MACHS-1:0]), + .grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]), + .row_addr (row_addr[ROW_VECT_INDX:0]), + .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), + .insert_maint_r1 (insert_maint_r1), + .maint_zq_r (maint_zq_r), + .maint_sre_r (maint_sre_r), + .maint_srx_r (maint_srx_r), + .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), + .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), + .req_size_r (req_size_r[nBANK_MACHS-1:0]), + .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), + .req_row_r (req_row_r[ROW_VECT_INDX:0]), + .col_addr (col_addr[ROW_VECT_INDX:0]), + .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), + .grant_col_r (grant_col_r[nBANK_MACHS-1:0]), + .grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]), + .send_cmd0_row (send_cmd0_row), + .send_cmd0_col (send_cmd0_col), + .send_cmd1_row (send_cmd1_row), + .send_cmd1_col (send_cmd1_col), + .send_cmd2_row (send_cmd2_row), + .send_cmd2_col (send_cmd2_col), + .send_cmd2_pre (send_cmd2_pre), + .send_cmd3_col (send_cmd3_col), + .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col), + .cs_en0 (cs_en0), + .cs_en1 (cs_en1), + .cs_en2 (cs_en2), + .cs_en3 (cs_en3), + .grant_config_r (grant_config_r[nBANK_MACHS-1:0]), + .rnk_config_strobe (rnk_config_strobe), + .slot_0_present (slot_0_present[7:0]), + .slot_1_present (slot_1_present[7:0])); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v new file mode 100644 index 0000000..f0cf428 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v @@ -0,0 +1,525 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : arb_row_col.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + + +// This block receives request to send row and column commands. These requests +// come the individual bank machines. The arbitration winner is selected +// and driven back to the bank machines. +// +// The CS enables are generated. For 2:1 mode, row commands are sent +// in the "0" phase, and column commands are sent in the "1" phase. +// +// In 2T mode, a further arbitration is performed between the row +// and column commands. The winner of this arbitration inhibits +// arbitration by the loser. The winner is allowed to arbitrate, the loser is +// blocked until the next state. The winning address command +// is repeated on both the "0" and the "1" phases and the CS +// is asserted for just the "1" phase. + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_arb_row_col # + ( + parameter TCQ = 100, + parameter ADDR_CMD_MODE = "1T", + parameter CWL = 5, + parameter EARLY_WR_DATA_ADDR = "OFF", + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, + parameter nRAS = 37500, // ACT->PRE cmd period (CKs) + parameter nRCD = 12500, // ACT->R/W delay (CKs) + parameter nWR = 6 // Write recovery (CKs) + ) + (/*AUTOARG*/ + // Outputs + grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r, + rnk_config_strobe, rnk_config_valid_r, grant_col_r, + sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col, + send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre, + send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3, + insert_maint_r1, rnk_config_kill_rts_col, + // Inputs + clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr + ); + + // Create a delay when switching ranks + localparam RNK2RNK_DLY = 12; + localparam RNK2RNK_DLY_CLKS = + (RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0); + + input clk; + input rst; + + input [nBANK_MACHS-1:0] rts_row; + input insert_maint_r; + input [nBANK_MACHS-1:0] rts_col; + reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r; + wire block_grant_row; + wire block_grant_col; + wire rnk_config_kill_rts_col_lcl = + RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0; + + output rnk_config_kill_rts_col; + assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl; + + wire [nBANK_MACHS-1:0] col_request; + wire granted_col_ns = |col_request; + wire [nBANK_MACHS-1:0] row_request = + rts_row & {nBANK_MACHS{~insert_maint_r}}; + wire granted_row_ns = |row_request; + generate + if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb + assign col_request = + rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}}; +// Give column command priority whenever previous state has no row request. + wire [1:0] row_col_grant; + wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant; + wire upd_last_master = ~granted_row_ns || |row_col_grant; + mig_7series_v4_2_round_robin_arb # + (.WIDTH (2)) + row_col_arb0 + (.grant_ns (), + .grant_r (row_col_grant), + .upd_last_master (upd_last_master), + .current_master (current_master), + .clk (clk), + .rst (rst), + .req ({granted_row_ns, granted_col_ns}), + .disable_grant (1'b0)); + assign {block_grant_col, block_grant_row} = row_col_grant; + end + else begin : row_col_1T_arb + assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}}; + assign block_grant_row = 1'b0; + assign block_grant_col = 1'b0; + end + endgenerate + +// Row address/command arbitration. + wire[nBANK_MACHS-1:0] grant_row_r_lcl; + output wire[nBANK_MACHS-1:0] grant_row_r; + assign grant_row_r = grant_row_r_lcl; + reg granted_row_r; + always @(posedge clk) granted_row_r <= #TCQ granted_row_ns; + wire sent_row_lcl = granted_row_r && ~block_grant_row; + output wire sent_row; + assign sent_row = sent_row_lcl; + mig_7series_v4_2_round_robin_arb # + (.WIDTH (nBANK_MACHS)) + row_arb0 + (.grant_ns (), + .grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]), + .upd_last_master (sent_row_lcl), + .current_master (grant_row_r_lcl[nBANK_MACHS-1:0]), + .clk (clk), + .rst (rst), + .req (row_request), + .disable_grant (1'b0)); + + output wire [nBANK_MACHS-1:0] sending_row; + assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}}; + + // Precharge arbitration for 4:1 mode + input [nBANK_MACHS-1:0] rts_pre; + output wire[nBANK_MACHS-1:0] grant_pre_r; + output wire [nBANK_MACHS-1:0] sending_pre; + wire sent_pre_lcl; + + generate + + if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb + + reg granted_pre_r; + wire[nBANK_MACHS-1:0] grant_pre_r_lcl; + + wire granted_pre_ns = |rts_pre; + assign grant_pre_r = grant_pre_r_lcl; + always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns; + assign sent_pre_lcl = granted_pre_r; + assign sending_pre = grant_pre_r_lcl; + + mig_7series_v4_2_round_robin_arb # + (.WIDTH (nBANK_MACHS)) + pre_arb0 + (.grant_ns (), + .grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]), + .upd_last_master (sent_pre_lcl), + .current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]), + .clk (clk), + .rst (rst), + .req (rts_pre), + .disable_grant (1'b0)); + + end + + endgenerate + +`ifdef MC_SVA + all_bank_machines_row_arb: + cover property (@(posedge clk) (~rst && &rts_row)); +`endif + +// Rank config arbitration. + input [nBANK_MACHS-1:0] rtc; + wire [nBANK_MACHS-1:0] grant_config_r_lcl; + output wire [nBANK_MACHS-1:0] grant_config_r; + assign grant_config_r = grant_config_r_lcl; + wire upd_rnk_config_last_master; + mig_7series_v4_2_round_robin_arb # + (.WIDTH (nBANK_MACHS)) + config_arb0 + (.grant_ns (), + .grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]), + .upd_last_master (upd_rnk_config_last_master), + .current_master (grant_config_r_lcl[nBANK_MACHS-1:0]), + .clk (clk), + .rst (rst), + .req (rtc[nBANK_MACHS-1:0]), + .disable_grant (1'b0)); + +`ifdef MC_SVA + all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc)); +`endif + + wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns; + always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns; + + genvar i; + generate + for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1) + always @(posedge clk) + rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1]; + endgenerate + + output wire rnk_config_strobe; + assign rnk_config_strobe = rnk_config_strobe_r[0]; + + assign upd_rnk_config_last_master = rnk_config_strobe_r[0]; + +// Generate rnk_config_valid. + reg rnk_config_valid_r_lcl; + wire rnk_config_valid_ns; + assign rnk_config_valid_ns = + ~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns); + always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns; + output wire rnk_config_valid_r; + assign rnk_config_valid_r = rnk_config_valid_r_lcl; + +// Column address/command arbitration. + wire [nBANK_MACHS-1:0] grant_col_r_lcl; + output wire [nBANK_MACHS-1:0] grant_col_r; + assign grant_col_r = grant_col_r_lcl; + reg granted_col_r; + always @(posedge clk) granted_col_r <= #TCQ granted_col_ns; + wire sent_col_lcl; + mig_7series_v4_2_round_robin_arb # + (.WIDTH (nBANK_MACHS)) + col_arb0 + (.grant_ns (), + .grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]), + .upd_last_master (sent_col_lcl), + .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), + .clk (clk), + .rst (rst), + .req (col_request), + .disable_grant (1'b0)); + +`ifdef MC_SVA + all_bank_machines_col_arb: + cover property (@(posedge clk) (~rst && &rts_col)); +`endif + + output wire [nBANK_MACHS-1:0] sending_col; + assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}}; + assign sent_col_lcl = granted_col_r && ~block_grant_col; + reg sent_col_lcl_r = 1'b0; + always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl; + output wire sent_col; + assign sent_col = sent_col_lcl; + output wire sent_col_r; + assign sent_col_r = sent_col_lcl_r; + + // If we need early wr_data_addr because ECC is on, arbitrate + // to see which bank machine might sent the next wr_data_addr; + input [nBANK_MACHS-1:0] col_rdy_wr; + output wire [nBANK_MACHS-1:0] grant_col_wr; + generate + if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off + assign grant_col_wr = {nBANK_MACHS{1'b0}}; + end + else begin : early_wr_addr_arb_on + wire [nBANK_MACHS-1:0] grant_col_wr_raw; + mig_7series_v4_2_round_robin_arb # + (.WIDTH (nBANK_MACHS)) + col_arb0 + (.grant_ns (grant_col_wr_raw), + .grant_r (), + .upd_last_master (sent_col_lcl), + .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), + .clk (clk), + .rst (rst), + .req (col_rdy_wr), + .disable_grant (1'b0)); + reg [nBANK_MACHS-1:0] grant_col_wr_r; + wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns + ? grant_col_wr_raw + : grant_col_wr_r; + always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns; + assign grant_col_wr = grant_col_wr_ns; + end // block: early_wr_addr_arb_on + endgenerate + + output reg send_cmd0_row = 1'b0; + output reg send_cmd0_col = 1'b0; + output reg send_cmd1_row = 1'b0; + output reg send_cmd1_col = 1'b0; + output reg send_cmd2_row = 1'b0; + output reg send_cmd2_col = 1'b0; + output reg send_cmd2_pre = 1'b0; + output reg send_cmd3_col = 1'b0; + + output reg cs_en0 = 1'b0; + output reg cs_en1 = 1'b0; + output reg cs_en2 = 1'b0; + output reg cs_en3 = 1'b0; + + output wire [5:0] col_channel_offset; + + reg insert_maint_r1_lcl; + always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r; + output wire insert_maint_r1; + assign insert_maint_r1 = insert_maint_r1_lcl; + + wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl; + reg sent_row_or_maint_r = 1'b0; + always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint; + generate + case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")}) + 3'b000 : begin : one_one_not2T + end + 3'b001 : begin : one_one_2T + end + 3'b010 : begin : two_one_not2T + + if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL + + always @(sent_col_lcl) begin + cs_en0 = sent_col_lcl; + send_cmd0_col = sent_col_lcl; + end + + always @(sent_row_or_maint) begin + cs_en1 = sent_row_or_maint; + send_cmd1_row = sent_row_or_maint; + end + + assign col_channel_offset = 0; + + end + + else begin // Place column commands on slot 1 for odd CWL + + always @(sent_row_or_maint) begin + cs_en0 = sent_row_or_maint; + send_cmd0_row = sent_row_or_maint; + end + + always @(sent_col_lcl) begin + cs_en1 = sent_col_lcl; + send_cmd1_col = sent_col_lcl; + end + + assign col_channel_offset = 1; + + end + + end + 3'b011 : begin : two_one_2T + + if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL + + always @(sent_row_or_maint_r or sent_col_lcl_r) + cs_en0 = sent_row_or_maint_r || sent_col_lcl_r; + + always @(sent_row_or_maint or sent_row_or_maint_r) begin + send_cmd0_row = sent_row_or_maint_r; + send_cmd1_row = sent_row_or_maint; + end + + always @(sent_col_lcl or sent_col_lcl_r) begin + send_cmd0_col = sent_col_lcl_r; + send_cmd1_col = sent_col_lcl; + end + + assign col_channel_offset = 0; + + end + + else begin // Place column commands on slot 0->1 for odd CWL + + always @(sent_col_lcl or sent_row_or_maint) + cs_en1 = sent_row_or_maint || sent_col_lcl; + + always @(sent_row_or_maint) begin + send_cmd0_row = sent_row_or_maint; + send_cmd1_row = sent_row_or_maint; + end + + always @(sent_col_lcl) begin + send_cmd0_col = sent_col_lcl; + send_cmd1_col = sent_col_lcl; + end + + assign col_channel_offset = 1; + + end + + end + 3'b100 : begin : four_one_not2T + + if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL + + always @(sent_col_lcl) begin + cs_en0 = sent_col_lcl; + send_cmd0_col = sent_col_lcl; + end + + always @(sent_row_or_maint) begin + cs_en1 = sent_row_or_maint; + send_cmd1_row = sent_row_or_maint; + end + + assign col_channel_offset = 0; + + end + + else begin // Place column commands on slot 1 for odd CWL + + always @(sent_row_or_maint) begin + cs_en0 = sent_row_or_maint; + send_cmd0_row = sent_row_or_maint; + end + + always @(sent_col_lcl) begin + cs_en1 = sent_col_lcl; + send_cmd1_col = sent_col_lcl; + end + + assign col_channel_offset = 1; + + end + + always @(sent_pre_lcl) begin + cs_en2 = sent_pre_lcl; + send_cmd2_pre = sent_pre_lcl; + end + + end + 3'b101 : begin : four_one_2T + + if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL + + always @(sent_col_lcl or sent_col_lcl_r) begin + cs_en0 = sent_col_lcl_r; + send_cmd0_col = sent_col_lcl_r; + send_cmd3_col = sent_col_lcl; + end + + always @(sent_row_or_maint) begin + cs_en2 = sent_row_or_maint; + send_cmd1_row = sent_row_or_maint; + send_cmd2_row = sent_row_or_maint; + end + + assign col_channel_offset = 0; + + end + + else begin // Place column commands on slot 2->3 for odd CWL + + always @(sent_row_or_maint) begin + cs_en1 = sent_row_or_maint; + send_cmd0_row = sent_row_or_maint; + send_cmd1_row = sent_row_or_maint; + end + + always @(sent_col_lcl) begin + cs_en3 = sent_col_lcl; + send_cmd2_col = sent_col_lcl; + send_cmd3_col = sent_col_lcl; + end + + assign col_channel_offset = 3; + + end + + end + endcase + endgenerate + + + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v new file mode 100644 index 0000000..00933be --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v @@ -0,0 +1,699 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : arb_select.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// Based on granta_r and grantc_r, this module selects a +// row and column command from the request information +// provided by the bank machines. +// +// Depending on address mode configuration, nCL and nCWL, a column +// command pipeline of up to three states will be created. + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_arb_select # + ( + parameter TCQ = 100, + parameter EVEN_CWL_2T_MODE = "OFF", + parameter ADDR_CMD_MODE = "1T", + parameter BANK_VECT_INDX = 11, + parameter BANK_WIDTH = 3, + parameter BURST_MODE = "8", + parameter CS_WIDTH = 4, + parameter CL = 5, + parameter CWL = 5, + parameter DATA_BUF_ADDR_VECT_INDX = 31, + parameter DATA_BUF_ADDR_WIDTH = 8, + parameter DRAM_TYPE = "DDR3", + parameter EARLY_WR_DATA_ADDR = "OFF", + parameter ECC = "OFF", + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, + parameter nCS_PER_RANK = 1, + parameter CKE_ODT_AUX = "FALSE", + parameter nSLOTS = 2, + parameter RANKS = 1, + parameter RANK_VECT_INDX = 15, + parameter RANK_WIDTH = 2, + parameter ROW_VECT_INDX = 63, + parameter ROW_WIDTH = 16, + parameter RTT_NOM = "40", + parameter RTT_WR = "120", + parameter SLOT_0_CONFIG = 8'b0000_0101, + parameter SLOT_1_CONFIG = 8'b0000_1010 + ) + ( + + // Outputs + + output wire col_periodic_rd, + output wire [RANK_WIDTH-1:0] col_ra, + output wire [BANK_WIDTH-1:0] col_ba, + output wire [ROW_WIDTH-1:0] col_a, + output wire col_rmw, + output wire col_rd_wr, + output wire col_size, + output wire [ROW_WIDTH-1:0] col_row, + output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr, + output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr, + + output wire [nCK_PER_CLK-1:0] mc_ras_n, + output wire [nCK_PER_CLK-1:0] mc_cas_n, + output wire [nCK_PER_CLK-1:0] mc_we_n, + output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, + output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, + output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, + output wire [1:0] mc_odt, + output wire [nCK_PER_CLK-1:0] mc_cke, + output wire [3:0] mc_aux_out0, + output wire [3:0] mc_aux_out1, + output [2:0] mc_cmd, + output wire [5:0] mc_data_offset, + output wire [5:0] mc_data_offset_1, + output wire [5:0] mc_data_offset_2, + output wire [1:0] mc_cas_slot, + + output wire [RANK_WIDTH-1:0] rnk_config, + + // Inputs + + input clk, + input rst, + input init_calib_complete, + + input [RANK_VECT_INDX:0] req_rank_r, + input [BANK_VECT_INDX:0] req_bank_r, + input [nBANK_MACHS-1:0] req_ras, + input [nBANK_MACHS-1:0] req_cas, + input [nBANK_MACHS-1:0] req_wr_r, + input [nBANK_MACHS-1:0] grant_row_r, + input [nBANK_MACHS-1:0] grant_pre_r, + input [ROW_VECT_INDX:0] row_addr, + input [nBANK_MACHS-1:0] row_cmd_wr, + input insert_maint_r1, + input maint_zq_r, + input maint_sre_r, + input maint_srx_r, + input [RANK_WIDTH-1:0] maint_rank_r, + + input [nBANK_MACHS-1:0] req_periodic_rd_r, + input [nBANK_MACHS-1:0] req_size_r, + input [nBANK_MACHS-1:0] rd_wr_r, + input [ROW_VECT_INDX:0] req_row_r, + input [ROW_VECT_INDX:0] col_addr, + input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r, + input [nBANK_MACHS-1:0] grant_col_r, + input [nBANK_MACHS-1:0] grant_col_wr, + + input [6*RANKS-1:0] calib_rddata_offset, + input [6*RANKS-1:0] calib_rddata_offset_1, + input [6*RANKS-1:0] calib_rddata_offset_2, + input [5:0] col_channel_offset, + + input [nBANK_MACHS-1:0] grant_config_r, + input rnk_config_strobe, + + input [7:0] slot_0_present, + input [7:0] slot_1_present, + + input send_cmd0_row, + input send_cmd0_col, + input send_cmd1_row, + input send_cmd1_col, + input send_cmd2_row, + input send_cmd2_col, + input send_cmd2_pre, + input send_cmd3_col, + + input sent_col, + + input cs_en0, + input cs_en1, + input cs_en2, + input cs_en3 + + ); + + localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1; + + reg col_rd_wr_ns; + reg col_rd_wr_r = 1'b0; + reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}}; + reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}}; + + // calib_rd_data_offset for currently targeted rank + reg [5:0] rank_rddata_offset_0; + reg [5:0] rank_rddata_offset_1; + reg [5:0] rank_rddata_offset_2; + + // Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1] + assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1; + assign mc_aux_out0[2] = 1'b0; + + reg cke_r; + reg cke_ns; + generate + if(CKE_ODT_AUX == "FALSE")begin + always @(posedge clk) + begin + if (rst) + cke_r = 1'b1; + else + cke_r = cke_ns; + end + + always @(*) + begin + cke_ns = 1'b1; + if (maint_sre_r & insert_maint_r1) + cke_ns = 1'b0; + else if (cke_r==1'b0) + begin + if (maint_srx_r & insert_maint_r1) + cke_ns = 1'b1; + else + cke_ns = 1'b0; + end + end + end + endgenerate + + // Disable ODT & CKE toggle enable high bits + assign mc_aux_out1 = 4'b0; + + // implement PHY command word + assign mc_cmd[0] = sent_col; + assign mc_cmd[1] = EVEN_CWL_2T_MODE == "ON" ? + sent_col && col_rd_wr_r : + sent_col && col_rd_wr_ns; + assign mc_cmd[2] = ~sent_col; + + // generate calib_rd_data_offset for current rank - only use rank 0 values for now + always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin + rank_rddata_offset_0 = calib_rddata_offset[5:0]; + rank_rddata_offset_1 = calib_rddata_offset_1[5:0]; + rank_rddata_offset_2 = calib_rddata_offset_2[5:0]; + end + + // generate data offset + generate + if(EVEN_CWL_2T_MODE == "ON") begin : gen_mc_data_offset_even_cwl_2t + assign mc_data_offset = ~sent_col ? + 6'b0 : + col_rd_wr_r ? + rank_rddata_offset_0 + col_channel_offset : + nCK_PER_CLK == 2 ? + CWL - 2 + col_channel_offset : + // nCK_PER_CLK == 4 + CWL + 2 + col_channel_offset; + assign mc_data_offset_1 = ~sent_col ? + 6'b0 : + col_rd_wr_r ? + rank_rddata_offset_1 + col_channel_offset : + nCK_PER_CLK == 2 ? + CWL - 2 + col_channel_offset : + // nCK_PER_CLK == 4 + CWL + 2 + col_channel_offset; + assign mc_data_offset_2 = ~sent_col ? + 6'b0 : + col_rd_wr_r ? + rank_rddata_offset_2 + col_channel_offset : + nCK_PER_CLK == 2 ? + CWL - 2 + col_channel_offset : + // nCK_PER_CLK == 4 + CWL + 2 + col_channel_offset; + end + else begin : gen_mc_data_offset_not_even_cwl_2t + assign mc_data_offset = ~sent_col ? + 6'b0 : + col_rd_wr_ns ? + rank_rddata_offset_0 + col_channel_offset : + nCK_PER_CLK == 2 ? + CWL - 2 + col_channel_offset : + // nCK_PER_CLK == 4 + CWL + 2 + col_channel_offset; + assign mc_data_offset_1 = ~sent_col ? + 6'b0 : + col_rd_wr_ns ? + rank_rddata_offset_1 + col_channel_offset : + nCK_PER_CLK == 2 ? + CWL - 2 + col_channel_offset : + // nCK_PER_CLK == 4 + CWL + 2 + col_channel_offset; + assign mc_data_offset_2 = ~sent_col ? + 6'b0 : + col_rd_wr_ns ? + rank_rddata_offset_2 + col_channel_offset : + nCK_PER_CLK == 2 ? + CWL - 2 + col_channel_offset : + // nCK_PER_CLK == 4 + CWL + 2 + col_channel_offset; + end + endgenerate + + assign mc_cas_slot = col_channel_offset[1:0]; + +// Based on arbitration results, select the row and column commands. + + integer i; + reg [OUT_CMD_WIDTH-1:0] row_cmd_ns; + generate + begin : row_mux + wire [OUT_CMD_WIDTH-1:0] maint_cmd = + {maint_rank_r, // maintenance rank + row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)], + // bank plus upper address bits + 1'b0, // A10 = 0 for ZQCS + row_cmd_r[3+:10], // address bits [9:0] + // ZQ, SRX or SRE/REFRESH + (maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001) + }; + always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd + or req_bank_r or req_cas or req_rank_r or req_ras + or row_addr or row_cmd_r or row_cmd_wr or rst) + begin + row_cmd_ns = rst + ? {RANK_WIDTH{1'b0}} + : insert_maint_r1 + ? maint_cmd + : row_cmd_r; + for (i=0; i 1) begin : slot_1_configured + wire slot_1_select = (slot_1_present[3] & slot_1_present[1])? + |({col_ra_one_hot[slot_0_population+1], + col_ra_one_hot[slot_0_population]}) : + (slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0; + wire slot_1_read = EVEN_CWL_2T_MODE == "ON" ? + slot_1_select && col_rd_wr_r : + slot_1_select && col_rd_wr_ns; + wire slot_1_write = EVEN_CWL_2T_MODE == "ON" ? + slot_1_select && ~col_rd_wr_r : + slot_1_select && ~col_rd_wr_ns; + + // ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3) + wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write; + assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds + + end // if (nSLOTS > 1) + else begin + + // Disable slot 1 ODT when not present + assign mc_aux_out0[3] = 1'b0; + + end // else: !if(nSLOTS > 1) + endgenerate + + + generate + if(CKE_ODT_AUX == "FALSE")begin + reg[1:0] mc_aux_out_r ; + reg[1:0] mc_aux_out_r_1 ; + reg[1:0] mc_aux_out_r_2 ; + + always@(posedge clk) begin + mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ; + mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ; + mc_aux_out_r_1 <= #TCQ mc_aux_out_r ; + mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ; + end + + if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot + assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0]; + assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1]; + end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1 + assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ; + assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ; + end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1 + assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ; + assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ; + end + end + endgenerate + + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v new file mode 100644 index 0000000..7fd2a3d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v @@ -0,0 +1,462 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : bank_cntrl.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// Structural block instantiating the three sub blocks that make up +// a bank machine. +`timescale 1ps/1ps + +module mig_7series_v4_2_bank_cntrl # + ( + parameter TCQ = 100, + parameter ADDR_CMD_MODE = "1T", + parameter BANK_WIDTH = 3, + parameter BM_CNT_WIDTH = 2, + parameter BURST_MODE = "8", + parameter COL_WIDTH = 12, + parameter CWL = 5, + parameter DATA_BUF_ADDR_WIDTH = 8, + parameter DRAM_TYPE = "DDR3", + parameter ECC = "OFF", + parameter ID = 4, + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, + parameter nOP_WAIT = 0, + parameter nRAS_CLKS = 10, + parameter nRCD = 5, + parameter nRTP = 4, + parameter nRP = 10, + parameter nWTP_CLKS = 5, + parameter ORDERING = "NORM", + parameter RANK_WIDTH = 2, + parameter RANKS = 4, + parameter RAS_TIMER_WIDTH = 5, + parameter ROW_WIDTH = 16, + parameter STARVE_LIMIT = 2 + ) + (/*AUTOARG*/ + // Outputs + wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc, + row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras, + req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r, + rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r, + ordered_issued, op_exit_req, end_rtp, demand_priority, + demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns, + req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r, + rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r, + // Inputs + was_wr, was_priority, use_addr, start_rcd_in, + size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row, + req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in, + rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r, + periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in, + order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r, + maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr, + rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority, + dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in, + data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q, + accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full, + phy_mc_cmd_full, phy_mc_data_full + ); + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input accept_internal_r; // To bank_queue0 of bank_queue.v + input accept_req; // To bank_queue0 of bank_queue.v + input adv_order_q; // To bank_queue0 of bank_queue.v + input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v + input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v + input clk; // To bank_compare0 of bank_compare.v, ... + input [2:0] cmd; // To bank_compare0 of bank_compare.v + input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v + input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v + input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v + input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v + input phy_rddata_valid; // To bank_state0 of bank_state.v + input dq_busy_data; // To bank_state0 of bank_state.v + input hi_priority; // To bank_compare0 of bank_compare.v + input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v + input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v + input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v + input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v + input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v + input rnk_config_strobe; // To bank_state0 of bank_state.v + input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v + input rnk_config_valid_r; // To bank_state0 of bank_state.v + input low_idle_cnt_r; // To bank_state0 of bank_state.v + input maint_idle; // To bank_queue0 of bank_queue.v + input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v + input maint_req_r; // To bank_queue0 of bank_queue.v + input maint_zq_r; // To bank_compare0 of bank_compare.v + input maint_sre_r; // To bank_compare0 of bank_compare.v + input op_exit_grant; // To bank_state0 of bank_state.v + input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v + input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v + input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v + input periodic_rd_insert; // To bank_compare0 of bank_compare.v + input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v + input phy_mc_ctl_full; + input phy_mc_cmd_full; + input phy_mc_data_full; + input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v + input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v + input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v + input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v + input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v + input rd_rmw; // To bank_state0 of bank_state.v + input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v + input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v + input rst; // To bank_state0 of bank_state.v, ... + input sending_col; // To bank_compare0 of bank_compare.v, ... + input sending_row; // To bank_state0 of bank_state.v + input sending_pre; + input sent_col; // To bank_state0 of bank_state.v + input sent_row; // To bank_state0 of bank_state.v + input size; // To bank_compare0 of bank_compare.v + input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v + input use_addr; // To bank_queue0 of bank_queue.v + input was_priority; // To bank_queue0 of bank_queue.v + input was_wr; // To bank_queue0 of bank_queue.v + // End of automatics + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v + output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v + output col_rdy_wr; // From bank_state0 of bank_state.v + output demand_act_priority; // From bank_state0 of bank_state.v + output demand_priority; // From bank_state0 of bank_state.v + output end_rtp; // From bank_state0 of bank_state.v + output op_exit_req; // From bank_state0 of bank_state.v + output ordered_issued; // From bank_queue0 of bank_queue.v + output ordered_r; // From bank_queue0 of bank_queue.v + output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v + output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v + output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v + output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v + output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v + output req_cas; // From bank_compare0 of bank_compare.v + output req_periodic_rd_r; // From bank_compare0 of bank_compare.v + output req_ras; // From bank_compare0 of bank_compare.v + output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v + output req_size_r; // From bank_compare0 of bank_compare.v + output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v + output row_cmd_wr; // From bank_compare0 of bank_compare.v + output rtc; // From bank_state0 of bank_state.v + output rts_col; // From bank_state0 of bank_state.v + output rts_row; // From bank_state0 of bank_state.v + output rts_pre; + output start_pre_wait; // From bank_state0 of bank_state.v + output start_rcd; // From bank_state0 of bank_state.v + output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v + // End of automatics + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire act_wait_r; // From bank_state0 of bank_state.v + wire allow_auto_pre; // From bank_state0 of bank_state.v + wire auto_pre_r; // From bank_queue0 of bank_queue.v + wire bank_wait_in_progress; // From bank_state0 of bank_state.v + wire order_q_zero; // From bank_queue0 of bank_queue.v + wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v + wire pass_open_bank_r; // From bank_queue0 of bank_queue.v + wire pre_wait_r; // From bank_state0 of bank_state.v + wire precharge_bm_end; // From bank_state0 of bank_state.v + wire q_has_priority; // From bank_queue0 of bank_queue.v + wire q_has_rd; // From bank_queue0 of bank_queue.v + wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v + wire rcv_open_bank; // From bank_queue0 of bank_queue.v + wire rd_half_rmw; // From bank_state0 of bank_state.v + wire req_priority_r; // From bank_compare0 of bank_compare.v + wire row_hit_r; // From bank_compare0 of bank_compare.v + wire tail_r; // From bank_queue0 of bank_queue.v + wire wait_for_maint_r; // From bank_queue0 of bank_queue.v + // End of automatics + + output idle_ns; + output req_wr_r; + output rd_wr_r; + output bm_end; + output idle_r; + output head_r; + output [RANK_WIDTH-1:0] req_rank_r; + output rb_hit_busy_r; + output passing_open_bank; + output maint_hit; + output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r; + + mig_7series_v4_2_bank_compare # + (/*AUTOINSTPARAM*/ + // Parameters + .BANK_WIDTH (BANK_WIDTH), + .TCQ (TCQ), + .BURST_MODE (BURST_MODE), + .COL_WIDTH (COL_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .ECC (ECC), + .RANK_WIDTH (RANK_WIDTH), + .RANKS (RANKS), + .ROW_WIDTH (ROW_WIDTH)) + bank_compare0 + (/*AUTOINST*/ + // Outputs + .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]), + .req_periodic_rd_r (req_periodic_rd_r), + .req_size_r (req_size_r), + .rd_wr_r (rd_wr_r), + .req_rank_r (req_rank_r[RANK_WIDTH-1:0]), + .req_bank_r (req_bank_r[BANK_WIDTH-1:0]), + .req_row_r (req_row_r[ROW_WIDTH-1:0]), + .req_wr_r (req_wr_r), + .req_priority_r (req_priority_r), + .rb_hit_busy_r (rb_hit_busy_r), + .rb_hit_busy_ns (rb_hit_busy_ns), + .row_hit_r (row_hit_r), + .maint_hit (maint_hit), + .col_addr (col_addr[ROW_WIDTH-1:0]), + .req_ras (req_ras), + .req_cas (req_cas), + .row_cmd_wr (row_cmd_wr), + .row_addr (row_addr[ROW_WIDTH-1:0]), + .rank_busy_r (rank_busy_r[RANKS-1:0]), + // Inputs + .clk (clk), + .idle_ns (idle_ns), + .idle_r (idle_r), + .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .periodic_rd_insert (periodic_rd_insert), + .size (size), + .cmd (cmd[2:0]), + .sending_col (sending_col), + .rank (rank[RANK_WIDTH-1:0]), + .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), + .bank (bank[BANK_WIDTH-1:0]), + .row (row[ROW_WIDTH-1:0]), + .col (col[COL_WIDTH-1:0]), + .hi_priority (hi_priority), + .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), + .maint_zq_r (maint_zq_r), + .maint_sre_r (maint_sre_r), + .auto_pre_r (auto_pre_r), + .rd_half_rmw (rd_half_rmw), + .act_wait_r (act_wait_r)); + + mig_7series_v4_2_bank_state # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .BM_CNT_WIDTH (BM_CNT_WIDTH), + .BURST_MODE (BURST_MODE), + .CWL (CWL), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .ECC (ECC), + .ID (ID), + .nBANK_MACHS (nBANK_MACHS), + .nCK_PER_CLK (nCK_PER_CLK), + .nOP_WAIT (nOP_WAIT), + .nRAS_CLKS (nRAS_CLKS), + .nRP (nRP), + .nRTP (nRTP), + .nRCD (nRCD), + .nWTP_CLKS (nWTP_CLKS), + .ORDERING (ORDERING), + .RANKS (RANKS), + .RANK_WIDTH (RANK_WIDTH), + .RAS_TIMER_WIDTH (RAS_TIMER_WIDTH), + .STARVE_LIMIT (STARVE_LIMIT)) + bank_state0 + (/*AUTOINST*/ + // Outputs + .start_rcd (start_rcd), + .act_wait_r (act_wait_r), + .rd_half_rmw (rd_half_rmw), + .ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]), + .end_rtp (end_rtp), + .bank_wait_in_progress (bank_wait_in_progress), + .start_pre_wait (start_pre_wait), + .op_exit_req (op_exit_req), + .pre_wait_r (pre_wait_r), + .allow_auto_pre (allow_auto_pre), + .precharge_bm_end (precharge_bm_end), + .demand_act_priority (demand_act_priority), + .rts_row (rts_row), + .rts_pre (rts_pre), + .act_this_rank_r (act_this_rank_r[RANKS-1:0]), + .demand_priority (demand_priority), + .col_rdy_wr (col_rdy_wr), + .rts_col (rts_col), + .wr_this_rank_r (wr_this_rank_r[RANKS-1:0]), + .rd_this_rank_r (rd_this_rank_r[RANKS-1:0]), + // Inputs + .clk (clk), + .rst (rst), + .bm_end (bm_end), + .pass_open_bank_r (pass_open_bank_r), + .sending_row (sending_row), + .sending_pre (sending_pre), + .rcv_open_bank (rcv_open_bank), + .sending_col (sending_col), + .rd_wr_r (rd_wr_r), + .req_wr_r (req_wr_r), + .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]), + .phy_rddata_valid (phy_rddata_valid), + .rd_rmw (rd_rmw), + .ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]), + .rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]), + .idle_r (idle_r), + .passing_open_bank (passing_open_bank), + .low_idle_cnt_r (low_idle_cnt_r), + .op_exit_grant (op_exit_grant), + .tail_r (tail_r), + .auto_pre_r (auto_pre_r), + .pass_open_bank_ns (pass_open_bank_ns), + .phy_mc_cmd_full (phy_mc_cmd_full), + .phy_mc_ctl_full (phy_mc_ctl_full), + .phy_mc_data_full (phy_mc_data_full), + .rnk_config (rnk_config[RANK_WIDTH-1:0]), + .rnk_config_strobe (rnk_config_strobe), + .rnk_config_kill_rts_col (rnk_config_kill_rts_col), + .rnk_config_valid_r (rnk_config_valid_r), + .rtc (rtc), + .req_rank_r (req_rank_r[RANK_WIDTH-1:0]), + .req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]), + .start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]), + .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), + .wait_for_maint_r (wait_for_maint_r), + .head_r (head_r), + .sent_row (sent_row), + .demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]), + .order_q_zero (order_q_zero), + .sent_col (sent_col), + .q_has_rd (q_has_rd), + .q_has_priority (q_has_priority), + .req_priority_r (req_priority_r), + .idle_ns (idle_ns), + .demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]), + .inhbt_rd (inhbt_rd[RANKS-1:0]), + .inhbt_wr (inhbt_wr[RANKS-1:0]), + .dq_busy_data (dq_busy_data)); + + mig_7series_v4_2_bank_queue # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ), + .BM_CNT_WIDTH (BM_CNT_WIDTH), + .nBANK_MACHS (nBANK_MACHS), + .ORDERING (ORDERING), + .ID (ID)) + bank_queue0 + (/*AUTOINST*/ + // Outputs + .head_r (head_r), + .tail_r (tail_r), + .idle_ns (idle_ns), + .idle_r (idle_r), + .pass_open_bank_ns (pass_open_bank_ns), + .pass_open_bank_r (pass_open_bank_r), + .auto_pre_r (auto_pre_r), + .bm_end (bm_end), + .passing_open_bank (passing_open_bank), + .ordered_issued (ordered_issued), + .ordered_r (ordered_r), + .order_q_zero (order_q_zero), + .rcv_open_bank (rcv_open_bank), + .rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]), + .q_has_rd (q_has_rd), + .q_has_priority (q_has_priority), + .wait_for_maint_r (wait_for_maint_r), + // Inputs + .clk (clk), + .rst (rst), + .accept_internal_r (accept_internal_r), + .use_addr (use_addr), + .periodic_rd_ack_r (periodic_rd_ack_r), + .bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]), + .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), + .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), + .accept_req (accept_req), + .rb_hit_busy_r (rb_hit_busy_r), + .maint_idle (maint_idle), + .maint_hit (maint_hit), + .row_hit_r (row_hit_r), + .pre_wait_r (pre_wait_r), + .allow_auto_pre (allow_auto_pre), + .sending_col (sending_col), + .req_wr_r (req_wr_r), + .rd_wr_r (rd_wr_r), + .bank_wait_in_progress (bank_wait_in_progress), + .precharge_bm_end (precharge_bm_end), + .adv_order_q (adv_order_q), + .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), + .rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]), + .passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]), + .was_wr (was_wr), + .maint_req_r (maint_req_r), + .was_priority (was_priority)); + +endmodule // bank_cntrl + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v new file mode 100644 index 0000000..61c6e61 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v @@ -0,0 +1,461 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : bank_common.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// Common block for the bank machines. Bank_common computes various +// items that cross all of the bank machines. These values are then +// fed back to all of the bank machines. Most of these values have +// to do with a row machine figuring out where it belongs in a queue. + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_bank_common # + ( + parameter TCQ = 100, + parameter BM_CNT_WIDTH = 2, + parameter LOW_IDLE_CNT = 1, + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, + parameter nOP_WAIT = 0, + parameter nRFC = 44, + parameter nXSDLL = 512, + parameter RANK_WIDTH = 2, + parameter RANKS = 4, + parameter CWL = 5, + parameter tZQCS = 64 + ) + (/*AUTOARG*/ + // Outputs + accept_internal_r, accept_ns, accept, periodic_rd_insert, + periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt, + adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr, + was_priority, maint_wip_r, maint_idle, insert_maint_r, + // Inputs + clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr, + rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp, + passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r, + maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end, + slot_0_present, slot_1_present + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + localparam ZERO = 0; + localparam ONE = 1; + localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH]; + localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH]; + + input clk; + input rst; + + input [nBANK_MACHS-1:0] idle_ns; + input init_calib_complete; + wire accept_internal_ns = init_calib_complete && |idle_ns; + output reg accept_internal_r; + always @(posedge clk) accept_internal_r <= accept_internal_ns; + wire periodic_rd_ack_ns; + wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns; + output wire accept_ns; + assign accept_ns = accept_ns_lcl; + reg accept_r; + always @(posedge clk) accept_r <= #TCQ accept_ns_lcl; + +// Wire to user interface informing user that the request has been accepted. + output wire accept; + assign accept = accept_r; + +`ifdef MC_SVA + property none_idle; + @(posedge clk) (init_calib_complete && ~|idle_r); + endproperty + + all_bank_machines_busy: cover property (none_idle); +`endif + +// periodic_rd_insert tells everyone to mux in the periodic read. + input periodic_rd_r; + reg periodic_rd_ack_r_lcl; + reg periodic_rd_cntr_r ; + always @(posedge clk) begin + if (rst) periodic_rd_cntr_r <= #TCQ 1'b0; + else if (periodic_rd_r && periodic_rd_ack_r_lcl) + periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r; + end + + wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl); + + // wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl; + wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl; + output wire periodic_rd_insert; + assign periodic_rd_insert = periodic_rd_insert_lcl; + +// periodic_rd_ack_r acknowledges that the read has been accepted +// into the queue. + assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns; + always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns; + output wire periodic_rd_ack_r; + assign periodic_rd_ack_r = periodic_rd_ack_r_lcl; + +// accept_req tells all q entries that a request has been accepted. + input use_addr; + wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr); + output wire accept_req; + assign accept_req = accept_req_lcl; + +// Count how many non idle bank machines hit on the rank and bank. + input [nBANK_MACHS-1:0] rb_hit_busy_r; + output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; + integer i; + always @(/*AS*/rb_hit_busy_r) begin + rb_hit_busy_cnt = BM_CNT_ZERO; + for (i = 0; i < nBANK_MACHS; i = i + 1) + if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE; + end + +// Count the number of idle bank machines. + input [nBANK_MACHS-1:0] idle_r; + output reg [BM_CNT_WIDTH-1:0] idle_cnt; + always @(/*AS*/idle_r) begin + idle_cnt = BM_CNT_ZERO; + for (i = 0; i < nBANK_MACHS; i = i + 1) + if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE; + end + +// Report an overall idle status + output idle; + assign idle = init_calib_complete && &idle_r; + +// Count the number of bank machines in the ordering queue. + input [nBANK_MACHS-1:0] ordered_r; + output reg [BM_CNT_WIDTH-1:0] order_cnt; + always @(/*AS*/ordered_r) begin + order_cnt = BM_CNT_ZERO; + for (i = 0; i < nBANK_MACHS; i = i + 1) + if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE; + end + + input [nBANK_MACHS-1:0] ordered_issued; + output wire adv_order_q; + assign adv_order_q = |ordered_issued; + +// Figure out which bank machine is going to accept the next request. + input [nBANK_MACHS-1:0] head_r; + wire [nBANK_MACHS-1:0] next = idle_r & head_r; + output reg[BM_CNT_WIDTH-1:0] bank_mach_next; + always @(/*AS*/next) begin + bank_mach_next = BM_CNT_ZERO; + for (i = 0; i <= nBANK_MACHS-1; i = i + 1) + if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0]; + end + + input [nBANK_MACHS-1:0] end_rtp; + input [nBANK_MACHS-1:0] passing_open_bank; + input [nBANK_MACHS-1:0] op_exit_req; + output wire [nBANK_MACHS-1:0] op_exit_grant; + output reg low_idle_cnt_r = 1'b0; + input [nBANK_MACHS-1:0] start_pre_wait; + + generate +// In support of open page mode, the following logic +// keeps track of how many "idle" bank machines there +// are. In this case, idle means a bank machine is on +// the idle list, or is in the process of precharging and +// will soon be idle. + if (nOP_WAIT == 0) begin : op_mode_disabled + assign op_exit_grant = {nBANK_MACHS{1'b0}}; + end + + else begin : op_mode_enabled + reg [BM_CNT_WIDTH:0] idle_cnt_r; + reg [BM_CNT_WIDTH:0] idle_cnt_ns; + always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank + or rst or start_pre_wait) + if (rst) idle_cnt_ns = nBANK_MACHS; + else begin + idle_cnt_ns = idle_cnt_r - accept_req_lcl; + for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin + idle_cnt_ns = idle_cnt_ns + passing_open_bank[i]; + end + idle_cnt_ns = idle_cnt_ns + |start_pre_wait; + end + always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns; + wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]); + always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns; + +// This arbiter determines which bank machine should transition +// from open page wait to precharge. Ideally, this process +// would take the oldest waiter, but don't have any reasonable +// way to implement that. Instead, just use simple round robin +// arb with the small enhancement that the most recent bank machine +// to enter open page wait is given lowest priority in the arbiter. + + wire upd_last_master = |end_rtp; // should be one bit set at most + mig_7series_v4_2_round_robin_arb # + (.WIDTH (nBANK_MACHS)) + op_arb0 + (.grant_ns (op_exit_grant[nBANK_MACHS-1:0]), + .grant_r (), + .upd_last_master (upd_last_master), + .current_master (end_rtp[nBANK_MACHS-1:0]), + .clk (clk), + .rst (rst), + .req (op_exit_req[nBANK_MACHS-1:0]), + .disable_grant (1'b0)); + + end + endgenerate + +// Register some command information. This information will be used +// by the bank machines to figure out if there is something behind it +// in the queue that require hi priority. + + input [2:0] cmd; + output reg was_wr; + always @(posedge clk) was_wr <= #TCQ + cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl); + + input hi_priority; + output reg was_priority; + always @(posedge clk) begin + if (hi_priority) + was_priority <= #TCQ 1'b1; + else + was_priority <= #TCQ 1'b0; + end + + +// DRAM maintenance (refresh and ZQ) and self-refresh controller + + input maint_req_r; + reg maint_wip_r_lcl; + output wire maint_wip_r; + assign maint_wip_r = maint_wip_r_lcl; + wire maint_idle_lcl; + output wire maint_idle; + assign maint_idle = maint_idle_lcl; + input maint_zq_r; + input maint_sre_r; + input maint_srx_r; + input [nBANK_MACHS-1:0] maint_hit; + input [nBANK_MACHS-1:0] bm_end; + wire start_maint; + wire maint_end; + + generate begin : maint_controller + +// Idle when not (maintenance work in progress (wip), OR maintenance +// starting tick). + assign maint_idle_lcl = ~(maint_req_r && ~periodic_rd_cntr_r) && ~maint_wip_r_lcl; + +// Maintenance work in progress starts with maint_reg_r tick, terminated +// with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer +// below. + wire maint_wip_ns = + ~rst && ~maint_end && (maint_wip_r_lcl || (maint_req_r && ~periodic_rd_cntr_r)); + always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns; + +// Keep track of which bank machines hit on the maintenance request +// when the request is made. As bank machines complete, an assertion +// of the bm_end signal clears the correspoding bit in the +// maint_hit_busies_r vector. Eventually, all bits should clear and +// the maintenance operation will proceed. ZQ and self-refresh hit on all +// non idle banks. Refresh hits only on non idle banks with the same rank as +// the refresh request. + wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end; + wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} & + (maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns; + wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} & + (maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns; + reg [nBANK_MACHS-1:0] maint_hit_busies_r; + wire [nBANK_MACHS-1:0] maint_hit_busies_ns = + ~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits); + always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns; + +// Queue is clear of requests conflicting with maintenance. + wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns; + +// Ready to start sending maintenance commands. + wire maint_rdy = maint_clear; + reg maint_rdy_r1; + reg maint_srx_r1; + always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy; + always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r; + assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1; + + end // block: maint_controller + endgenerate + + +// Figure out how many maintenance commands to send, and send them. + input [7:0] slot_0_present; + input [7:0] slot_1_present; + reg insert_maint_r_lcl; + output wire insert_maint_r; + assign insert_maint_r = insert_maint_r_lcl; + + generate begin : generate_maint_cmds + +// Count up how many slots are occupied. This tells +// us how many ZQ, SRE or SRX commands to send out. + reg [RANK_WIDTH:0] present_count; + wire [7:0] present = slot_0_present | slot_1_present; + always @(/*AS*/present) begin + present_count = {RANK_WIDTH{1'b0}}; + for (i=0; i<8; i=i+1) + present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]}; + end + +// For refresh, there is only a single command sent. For +// ZQ, SRE and SRX, each rank present will receive a command. The counter +// below counts down the number of ranks present. + reg [RANK_WIDTH:0] send_cnt_ns; + reg [RANK_WIDTH:0] send_cnt_r; + always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count + or rst or send_cnt_r or start_maint) + if (rst) send_cnt_ns = 4'b0; + else begin + send_cnt_ns = send_cnt_r; + if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count; + if (|send_cnt_ns) + send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0]; + end + always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns; + +// Insert a maintenance command for start_maint, or when the sent count +// is not zero. + wire insert_maint_ns = start_maint || |send_cnt_r; + + always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns; + end // block: generate_maint_cmds + endgenerate + + +// RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ +// command until the end of the maintenance operation. + +// Compute values for RFC, ZQ and XSDLL periods. + localparam nRFC_CLKS = (nCK_PER_CLK == 1) ? + nRFC : + (nCK_PER_CLK == 2) ? + ((nRFC/2) + (nRFC%2)) : + // (nCK_PER_CLK == 4) + ((nRFC/4) + ((nRFC%4) ? 1 : 0)); + + localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ? + tZQCS : + (nCK_PER_CLK == 2) ? + ((tZQCS/2) + (tZQCS%2)) : + // (nCK_PER_CLK == 4) + ((tZQCS/4) + ((tZQCS%4) ? 1 : 0)); + + localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ? + nXSDLL : + (nCK_PER_CLK == 2) ? + ((nXSDLL/2) + (nXSDLL%2)) : + // (nCK_PER_CLK == 4) + ((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0)); + + localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1); + + localparam THREE = 3; + + generate begin : rfc_zq_xsdll_timer + + reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns; + reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r; + + always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r + or rfc_zq_xsdll_timer_r or rst) begin + rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r; + if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}}; + else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ? + nZQCS_CLKS : + maint_sre_r ? + {RFC_ZQ_TIMER_WIDTH{1'b0}} : + maint_srx_r ? + nXSDLL_CLKS : + nRFC_CLKS; + else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns = + rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0]; + end + always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns; + +// Based on rfc_zq_xsdll_timer_r, figure out when to release any bank +// machines waiting to send an activate. Need to add two to the end count. +// One because the counter starts a state after the insert_refresh_r, and +// one more because bm_end to insert_refresh_r is one state shorter +// than bm_end to rts_row. + assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]); + end // block: rfc_zq_xsdll_timer + endgenerate + + +endmodule // bank_common + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v new file mode 100644 index 0000000..74d4028 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v @@ -0,0 +1,285 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : bank_compare.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// This block stores the request for this bank machine. +// +// All possible new requests are compared against the request stored +// here. The compare results are shared with the bank machines and +// is used to determine where to enqueue a new request. + +`timescale 1ps/1ps + +module mig_7series_v4_2_bank_compare # + (parameter BANK_WIDTH = 3, + parameter TCQ = 100, + parameter BURST_MODE = "8", + parameter COL_WIDTH = 12, + parameter DATA_BUF_ADDR_WIDTH = 8, + parameter ECC = "OFF", + parameter RANK_WIDTH = 2, + parameter RANKS = 4, + parameter ROW_WIDTH = 16) + (/*AUTOARG*/ + // Outputs + req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r, + req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r, + rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr, + req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r, + // Inputs + clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd, + sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority, + maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r + ); + + input clk; + + input idle_ns; + input idle_r; + + input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr; + output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r; + wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns = + idle_r + ? data_buf_addr + : req_data_buf_addr_r; + always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns; + + input periodic_rd_insert; + + reg req_periodic_rd_r_lcl; + wire req_periodic_rd_ns = idle_ns + ? periodic_rd_insert + : req_periodic_rd_r_lcl; + always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns; + output wire req_periodic_rd_r; + assign req_periodic_rd_r = req_periodic_rd_r_lcl; + + input size; + wire req_size_r_lcl; + generate + if (BURST_MODE == "4") begin : burst_mode_4 + assign req_size_r_lcl = 1'b0; + end + else + if (BURST_MODE == "8") begin : burst_mode_8 + assign req_size_r_lcl = 1'b1; + end + else + if (BURST_MODE == "OTF") begin : burst_mode_otf + reg req_size; + wire req_size_ns = idle_ns + ? (periodic_rd_insert || size) + : req_size; + always @(posedge clk) req_size <= #TCQ req_size_ns; + assign req_size_r_lcl = req_size; + end + endgenerate + output wire req_size_r; + assign req_size_r = req_size_r_lcl; + + + + input [2:0] cmd; + reg [2:0] req_cmd_r; + wire [2:0] req_cmd_ns = idle_ns + ? (periodic_rd_insert ? 3'b001 : cmd) + : req_cmd_r; + + always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns; + +`ifdef MC_SVA + rd_wr_only_wo_ecc: assert property + (@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1])); +`endif + + input sending_col; + reg rd_wr_r_lcl; + wire rd_wr_ns = idle_ns + ? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0]) + : ~sending_col && rd_wr_r_lcl; + always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns; + output wire rd_wr_r; + assign rd_wr_r = rd_wr_r_lcl; + + input [RANK_WIDTH-1:0] rank; + input [RANK_WIDTH-1:0] periodic_rd_rank_r; + reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}}; + reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}}; + generate + if (RANKS != 1) begin + always @(/*AS*/idle_ns or periodic_rd_insert + or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns + ? periodic_rd_insert + ? periodic_rd_rank_r + : rank + : req_rank_r_lcl; + always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns; + end + endgenerate + output wire [RANK_WIDTH-1:0] req_rank_r; + assign req_rank_r = req_rank_r_lcl; + + input [BANK_WIDTH-1:0] bank; + reg [BANK_WIDTH-1:0] req_bank_r_lcl; + wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl; + always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns; + output wire[BANK_WIDTH-1:0] req_bank_r; + assign req_bank_r = req_bank_r_lcl; + + input [ROW_WIDTH-1:0] row; + reg [ROW_WIDTH-1:0] req_row_r_lcl; + wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl; + always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns; + output wire [ROW_WIDTH-1:0] req_row_r; + assign req_row_r = req_row_r_lcl; + + // Make req_col_r as wide as the max row address. This + // makes it easier to deal with indexing different column widths. + input [COL_WIDTH-1:0] col; + reg [15:0] req_col_r = 16'b0; + wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0]; + always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns; + + reg req_wr_r_lcl; + wire req_wr_ns = idle_ns + ? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0]) + : req_wr_r_lcl; + always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns; + output wire req_wr_r; + assign req_wr_r = req_wr_r_lcl; + + input hi_priority; + output reg req_priority_r; + wire req_priority_ns = idle_ns ? hi_priority : req_priority_r; + always @(posedge clk) req_priority_r <= #TCQ req_priority_ns; + + wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert + ? periodic_rd_rank_r + : rank)); + wire bank_hit = (req_bank_r_lcl == bank); + wire rank_bank_hit = rank_hit && bank_hit; + + output reg rb_hit_busy_r; // rank-bank hit on non idle row machine + wire rb_hit_busy_ns_lcl; + assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns; + output wire rb_hit_busy_ns; + assign rb_hit_busy_ns = rb_hit_busy_ns_lcl; + + wire row_hit_ns = (req_row_r_lcl == row); + output reg row_hit_r; + + always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl; + always @(posedge clk) row_hit_r <= #TCQ row_hit_ns; + + input [RANK_WIDTH-1:0] maint_rank_r; + input maint_zq_r; + input maint_sre_r; + output wire maint_hit; + assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r; + +// Assemble column address. Structure to be the same +// width as the row address. This makes it easier +// for the downstream muxing. Depending on the sizes +// of the row and column addresses, fill in as appropriate. + input auto_pre_r; + input rd_half_rmw; + reg [15:0] col_addr_template = 16'b0; + always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r + or req_size_r_lcl) begin + col_addr_template = req_col_r; + col_addr_template[10] = auto_pre_r && ~rd_half_rmw; + col_addr_template[11] = req_col_r[10]; + col_addr_template[12] = req_size_r_lcl; + col_addr_template[13] = req_col_r[11]; + end + output wire [ROW_WIDTH-1:0] col_addr; + assign col_addr = col_addr_template[ROW_WIDTH-1:0]; + + output wire req_ras; + output wire req_cas; + output wire row_cmd_wr; + input act_wait_r; + assign req_ras = 1'b0; + assign req_cas = 1'b1; + assign row_cmd_wr = act_wait_r; + + output reg [ROW_WIDTH-1:0] row_addr; + always @(/*AS*/act_wait_r or req_row_r_lcl) begin + row_addr = req_row_r_lcl; +// This causes all precharges to be precharge single bank command. + if (~act_wait_r) row_addr[10] = 1'b0; + end + +// Indicate which, if any, rank this bank machine is busy with. +// Not registering the result would probably be more accurate, but +// would create timing issues. This is used for refresh banking, perfect +// accuracy is not required. + localparam ONE = 1; + output reg [RANKS-1:0] rank_busy_r; + wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns); + always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns; + +endmodule // bank_compare + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v new file mode 100644 index 0000000..1bce010 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v @@ -0,0 +1,597 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : bank_mach.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// Top level bank machine block. A structural block instantiating the configured +// individual bank machines, and a common block that computes various items shared +// by all bank machines. + +`timescale 1ps/1ps + +module mig_7series_v4_2_bank_mach # + ( + parameter TCQ = 100, + parameter EVEN_CWL_2T_MODE = "OFF", + parameter ADDR_CMD_MODE = "1T", + parameter BANK_WIDTH = 3, + parameter BM_CNT_WIDTH = 2, + parameter BURST_MODE = "8", + parameter COL_WIDTH = 12, + parameter CS_WIDTH = 4, + parameter CL = 5, + parameter CWL = 5, + parameter DATA_BUF_ADDR_WIDTH = 8, + parameter DRAM_TYPE = "DDR3", + parameter EARLY_WR_DATA_ADDR = "OFF", + parameter ECC = "OFF", + parameter LOW_IDLE_CNT = 1, + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, + parameter nCS_PER_RANK = 1, + parameter nOP_WAIT = 0, + parameter nRAS = 20, + parameter nRCD = 5, + parameter nRFC = 44, + parameter nRTP = 4, + parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal + parameter nRP = 10, + parameter nSLOTS = 2, + parameter nWR = 6, + parameter nXSDLL = 512, + parameter ORDERING = "NORM", + parameter RANK_BM_BV_WIDTH = 16, + parameter RANK_WIDTH = 2, + parameter RANKS = 4, + parameter ROW_WIDTH = 16, + parameter RTT_NOM = "40", + parameter RTT_WR = "120", + parameter STARVE_LIMIT = 2, + parameter SLOT_0_CONFIG = 8'b0000_0101, + parameter SLOT_1_CONFIG = 8'b0000_1010, + parameter tZQCS = 64 + ) + (/*AUTOARG*/ + // Outputs + output accept, // From bank_common0 of bank_common.v + output accept_ns, // From bank_common0 of bank_common.v + output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v + output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v + output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v + output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v + output col_periodic_rd, // From arb_mux0 of arb_mux.v + output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v + output col_rmw, // From arb_mux0 of arb_mux.v + output col_rd_wr, + output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v + output col_size, // From arb_mux0 of arb_mux.v + output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v + output wire [nCK_PER_CLK-1:0] mc_ras_n, + output wire [nCK_PER_CLK-1:0] mc_cas_n, + output wire [nCK_PER_CLK-1:0] mc_we_n, + output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, + output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, + output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, + output wire [1:0] mc_odt, + output wire [nCK_PER_CLK-1:0] mc_cke, + output wire [3:0] mc_aux_out0, + output wire [3:0] mc_aux_out1, + output [2:0] mc_cmd, + output [5:0] mc_data_offset, + output [5:0] mc_data_offset_1, + output [5:0] mc_data_offset_2, + output [1:0] mc_cas_slot, + output insert_maint_r1, // From arb_mux0 of arb_mux.v + output maint_wip_r, // From bank_common0 of bank_common.v + output wire [nBANK_MACHS-1:0] sending_row, + output wire [nBANK_MACHS-1:0] sending_col, + output wire sent_col, + output wire sent_col_r, + output periodic_rd_ack_r, + output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, + output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r, + output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, + output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, + output idle, + + // Inputs + input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v + input [6*RANKS-1:0] calib_rddata_offset, + input [6*RANKS-1:0] calib_rddata_offset_1, + input [6*RANKS-1:0] calib_rddata_offset_2, + input clk, // To bank0 of bank_cntrl.v, ... + input [2:0] cmd, // To bank0 of bank_cntrl.v, ... + input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v + input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v + input init_calib_complete, // To bank_common0 of bank_common.v + input phy_rddata_valid, // To bank0 of bank_cntrl.v + input dq_busy_data, // To bank0 of bank_cntrl.v + input hi_priority, // To bank0 of bank_cntrl.v, ... + input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v + input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v + input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v + input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ... + input maint_req_r, // To bank0 of bank_cntrl.v, ... + input maint_zq_r, // To bank0 of bank_cntrl.v, ... + input maint_sre_r, // To bank0 of bank_cntrl.v, ... + input maint_srx_r, // To bank0 of bank_cntrl.v, ... + input periodic_rd_r, // To bank_common0 of bank_common.v + input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v + input phy_mc_ctl_full, + input phy_mc_cmd_full, + input phy_mc_data_full, + input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v + input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v + input rd_rmw, // To bank0 of bank_cntrl.v + input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v + input rst, // To bank0 of bank_cntrl.v, ... + input size, // To bank0 of bank_cntrl.v + input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ... + input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ... + input use_addr + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1; + localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1; + localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1; + localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1; + localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0)); + localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR; +// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of +// one DRAM CK due to column command to row command fixed offset. In 2T mode, +// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T +// mode, in which case we add 1 if the remainder exceeds the fixed offset. + localparam nWTP_CLKS = (nCK_PER_CLK == 1) + ? nWTP : + (nCK_PER_CLK == 2) + ? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) : + (nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2); + localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS) + ? nRAS_CLKS + : nWTP_CLKS) - 1); + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + + // End of automatics + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + + // End of automatics + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire accept_internal_r; // From bank_common0 of bank_common.v + wire accept_req; // From bank_common0 of bank_common.v + wire adv_order_q; // From bank_common0 of bank_common.v + wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v + wire insert_maint_r; // From bank_common0 of bank_common.v + wire low_idle_cnt_r; // From bank_common0 of bank_common.v + wire maint_idle; // From bank_common0 of bank_common.v + wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v + wire periodic_rd_insert; // From bank_common0 of bank_common.v + wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v + wire sent_row; // From arb_mux0 of arb_mux.v + wire was_priority; // From bank_common0 of bank_common.v + wire was_wr; // From bank_common0 of bank_common.v + // End of automatics + + wire [RANK_WIDTH-1:0] rnk_config; + wire rnk_config_strobe; + wire rnk_config_kill_rts_col; + wire rnk_config_valid_r; + + wire [nBANK_MACHS-1:0] rts_row; + wire [nBANK_MACHS-1:0] rts_col; + wire [nBANK_MACHS-1:0] rts_pre; + wire [nBANK_MACHS-1:0] col_rdy_wr; + wire [nBANK_MACHS-1:0] rtc; + wire [nBANK_MACHS-1:0] sending_pre; + + wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r; + wire [nBANK_MACHS-1:0] req_size_r; + wire [RANK_VECT_INDX:0] req_rank_r; + wire [BANK_VECT_INDX:0] req_bank_r; + wire [ROW_VECT_INDX:0] req_row_r; + wire [ROW_VECT_INDX:0] col_addr; + wire [nBANK_MACHS-1:0] req_periodic_rd_r; + wire [nBANK_MACHS-1:0] req_wr_r; + wire [nBANK_MACHS-1:0] rd_wr_r; + wire [nBANK_MACHS-1:0] req_ras; + wire [nBANK_MACHS-1:0] req_cas; + wire [ROW_VECT_INDX:0] row_addr; + wire [nBANK_MACHS-1:0] row_cmd_wr; + wire [nBANK_MACHS-1:0] demand_priority; + wire [nBANK_MACHS-1:0] demand_act_priority; + + wire [nBANK_MACHS-1:0] idle_ns; + wire [nBANK_MACHS-1:0] rb_hit_busy_r; + wire [nBANK_MACHS-1:0] bm_end; + wire [nBANK_MACHS-1:0] passing_open_bank; + wire [nBANK_MACHS-1:0] ordered_r; + wire [nBANK_MACHS-1:0] ordered_issued; + wire [nBANK_MACHS-1:0] rb_hit_busy_ns; + wire [nBANK_MACHS-1:0] maint_hit; + wire [nBANK_MACHS-1:0] idle_r; + wire [nBANK_MACHS-1:0] head_r; + wire [nBANK_MACHS-1:0] start_rcd; + + wire [nBANK_MACHS-1:0] end_rtp; + wire [nBANK_MACHS-1:0] op_exit_req; + wire [nBANK_MACHS-1:0] op_exit_grant; + wire [nBANK_MACHS-1:0] start_pre_wait; + + wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns; + + genvar ID; + generate for (ID=0; ID 1) begin : compute_tail + reg tail_ns; + always @(accept_req or accept_this_bm + or bm_end_in or bm_end_lcl or idle_r_lcl + or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin + if (rst) tail_ns = (ID == nBANK_MACHS); +// The order of the statements below is important in the case where +// another bank machine is retiring and this bank machine is accepting. + else begin + tail_ns = tail_r_lcl; + if ((accept_req && rb_hit_busy_r) || + (|bm_end_in[`BM_SHARED_BV] && idle_r_lcl)) + tail_ns = 1'b0; + if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1; + end + end + always @(posedge clk) tail_r_lcl <= #TCQ tail_ns; + end // if (nBANK_MACHS > 1) + endgenerate + output wire tail_r; + assign tail_r = tail_r_lcl; + + wire clear_req = bm_end_lcl || rst; + +// Is this entry in the idle queue? + reg idle_ns_lcl; + always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin + idle_ns_lcl = idle_r_lcl; + if (accept_this_bm) idle_ns_lcl = 1'b0; + if (clear_req) idle_ns_lcl = 1'b1; + end + always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl; + output wire idle_ns; + assign idle_ns = idle_ns_lcl; + output wire idle_r; + assign idle_r = idle_r_lcl; + +// Maintenance hitting on this active bank machine is in progress. + input maint_idle; + input maint_hit; + wire maint_hit_this_bm = ~maint_idle && maint_hit; + +// Does new request hit on this bank machine while it is able to pass the +// open bank? + input row_hit_r; + input pre_wait_r; + wire pass_open_bank_eligible = + tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r; + +// Set pass open bank bit, but not if request preceded active maintenance. + reg wait_for_maint_r_lcl; + reg pass_open_bank_r_lcl; + wire pass_open_bank_ns_lcl = ~clear_req && + (pass_open_bank_r_lcl || + (accept_req && pass_open_bank_eligible && + (~maint_hit_this_bm || wait_for_maint_r_lcl))); + always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl; + output wire pass_open_bank_ns; + assign pass_open_bank_ns = pass_open_bank_ns_lcl; + output wire pass_open_bank_r; + assign pass_open_bank_r = pass_open_bank_r_lcl; + +`ifdef MC_SVA + pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns)); + pass_open_bank_killed_by_maint: cover property (@(posedge clk) + (~rst && accept_req && pass_open_bank_eligible && + maint_hit_this_bm && ~wait_for_maint_r_lcl)); + pass_open_bank_following_maint: cover property (@(posedge clk) + (~rst && accept_req && pass_open_bank_eligible && + maint_hit_this_bm && wait_for_maint_r_lcl)); +`endif + +// Should the column command be sent with the auto precharge bit set? This +// will happen when it is detected that next request is to a different row, +// or the next reqest is the next request is refresh to this rank. + reg auto_pre_r_lcl; + reg auto_pre_ns; + input allow_auto_pre; + always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl + or clear_req or maint_hit_this_bm or rb_hit_busy_r + or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin + auto_pre_ns = auto_pre_r_lcl; + if (clear_req) auto_pre_ns = 1'b0; + else + if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r && + (~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl))) + auto_pre_ns = 1'b1; + end + always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns; + output wire auto_pre_r; + assign auto_pre_r = auto_pre_r_lcl; + +`ifdef MC_SVA + auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns)); + maint_triggers_auto_precharge: cover property (@(posedge clk) + (~rst && auto_pre_ns && ~auto_pre_r && row_hit_r)); +`endif + +// Determine when the current request is finished. + input sending_col; + input req_wr_r; + input rd_wr_r; + wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r); + input bank_wait_in_progress; + input precharge_bm_end; + reg pre_bm_end_r; + wire pre_bm_end_ns = precharge_bm_end || + (bank_wait_in_progress && pass_open_bank_ns_lcl); + always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns; + assign bm_end_lcl = + pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); + output wire bm_end; + assign bm_end = bm_end_lcl; + +// Determine that the open bank should be passed to the successor bank machine. + reg pre_passing_open_bank_r; + wire pre_passing_open_bank_ns = + bank_wait_in_progress && pass_open_bank_ns_lcl; + always @(posedge clk) pre_passing_open_bank_r <= #TCQ + pre_passing_open_bank_ns; + output wire passing_open_bank; + assign passing_open_bank = + pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl); + + reg ordered_ns; + wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") && + req_wr_r)) && accept_this_bm; + + wire ordered_issued_lcl = + sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) && + ((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r)); + output wire ordered_issued; + assign ordered_issued = ordered_issued_lcl; + + reg ordered_r_lcl; + always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst + or set_order_q) begin + if (rst) ordered_ns = 1'b0; + else begin + ordered_ns = ordered_r_lcl; +// Should never see accept_this_bm and adv_order_q at the same time. + if (set_order_q) ordered_ns = 1'b1; + if (ordered_issued_lcl) ordered_ns = 1'b0; + end + end + always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns; + output wire ordered_r; + assign ordered_r = ordered_r_lcl; + +// Figure out when to advance the ordering queue. + input adv_order_q; + input [BM_CNT_WIDTH-1:0] order_cnt; + reg [BM_CNT_WIDTH-1:0] order_q_r; + reg [BM_CNT_WIDTH-1:0] order_q_ns; + always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst + or set_order_q) begin + order_q_ns = order_q_r; + if (rst) order_q_ns = BM_CNT_ZERO; + if (set_order_q) + if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE; + else order_q_ns = order_cnt; + if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE; + end + always @(posedge clk) order_q_r <= #TCQ order_q_ns; + + output wire order_q_zero; + assign order_q_zero = ~|order_q_r || + (adv_order_q && (order_q_r == BM_CNT_ONE)) || + ((ORDERING == "NORM") && rd_wr_r); + +// Keep track of which other bank machine are ahead of this one in a +// rank-bank queue. This is necessary to know when to advance this bank +// machine in the queue, and when to update bank state machine counter upon +// passing a bank. + input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in; + reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}}; + input [(nBANK_MACHS*2)-1:0] passing_open_bank_in; + output reg rcv_open_bank = 1'b0; + + generate + if (nBANK_MACHS > 1) begin : rb_hit_busies + +// The clear_vector resets bits in the rb_hit_busies vector as bank machines +// completes requests. rst also resets all the bits. + wire [nBANK_MACHS-2:0] clear_vector = + ({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]); + +// As this bank machine takes on a new request, capture the vector of +// which other bank machines are in the same queue. + wire [`BM_SHARED_BV] rb_hit_busies_ns = + ~clear_vector & + (idle_ns_lcl + ? rb_hit_busy_ns_in[`BM_SHARED_BV] + : rb_hit_busies_r_lcl[`BM_SHARED_BV]); + always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <= + #TCQ rb_hit_busies_ns; + +// Compute when to advance this queue entry based on seeing other bank machines +// in the same queue finish. + always @(bm_end_in or rb_hit_busies_r_lcl) + adv_queue = + |(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]); + +// Decide when to receive an open bank based on knowing this bank machine is +// one entry from the head, and a passing_open_bank hits on the +// rb_hit_busies vector. + always @(idle_r_lcl + or passing_open_bank_in or q_entry_r + or rb_hit_busies_r_lcl) rcv_open_bank = + |(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV]) + && (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl; + end + endgenerate + output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; + assign rb_hit_busies_r = rb_hit_busies_r_lcl; + + +// Keep track if the queue this entry is in has priority content. + input was_wr; + input maint_req_r; + reg q_has_rd_r; + wire q_has_rd_ns = ~clear_req && + (q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) || + (maint_req_r && maint_hit && ~idle_r_lcl)); + always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns; + output wire q_has_rd; + assign q_has_rd = q_has_rd_r; + + input was_priority; + reg q_has_priority_r; + wire q_has_priority_ns = ~clear_req && + (q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority)); + always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns; + output wire q_has_priority; + assign q_has_priority = q_has_priority_r; + +// Figure out if this entry should wait for maintenance to end. + wire wait_for_maint_ns = ~rst && ~maint_idle && + (wait_for_maint_r_lcl || (maint_hit && accept_this_bm)); + always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns; + output wire wait_for_maint_r; + assign wait_for_maint_r = wait_for_maint_r_lcl; + +endmodule // bank_queue + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v new file mode 100644 index 0000000..725dc33 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v @@ -0,0 +1,899 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. 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Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : bank_state.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + + +// Primary bank state machine. All bank specific timing is generated here. +// +// Conceptually, when a bank machine is assigned a request, conflicts are +// checked. If there is a conflict, then the new request is added +// to the queue for that rank-bank. +// +// Eventually, that request will find itself at the head of the queue for +// its rank-bank. Forthwith, the bank machine will begin arbitration to send an +// activate command to the DRAM. Once arbitration is successful and the +// activate is sent, the row state machine waits the RCD delay. The RAS +// counter is also started when the activate is sent. +// +// Upon completion of the RCD delay, the bank state machine will begin +// arbitration for sending out the column command. Once the column +// command has been sent, the bank state machine waits the RTP latency, and +// if the command is a write, the RAS counter is loaded with the WR latency. +// +// When the RTP counter reaches zero, the pre charge wait state is entered. +// Once the RAS timer reaches zero, arbitration to send a precharge command +// begins. +// +// Upon successful transmission of the precharge command, the bank state +// machine waits the precharge period and then rejoins the idle list. +// +// For an open rank-bank hit, a bank machine passes management of the rank-bank to +// a bank machine that is managing the subsequent request to the same page. A bank +// machine can either be a "passer" or a "passee" in this handoff. There +// are two conditions that have to occur before an open bank can be passed. +// A spatial condition, ie same rank-bank and row address. And a temporal condition, +// ie the passee has completed it work with the bank, but has not issued a precharge. +// +// The spatial condition is signalled by pass_open_bank_ns. The temporal condition +// is when the column command is issued, or when the bank_wait_in_progress +// signal is true. Bank_wait_in_progress is true when the RTP timer is not +// zero, or when the RAS/WR timer is not zero and the state machine is waiting +// to send out a precharge command. +// +// On an open bank pass, the passer transitions from the temporal condition +// noted above and performs the end of request processing and eventually lands +// in the act_wait_r state. +// +// On an open bank pass, the passee lands in the col_wait_r state and waits +// for its chance to send out a column command. +// +// Since there is a single data bus shared by all columns in all ranks, there +// is a single column machine. The column machine is primarily in charge of +// managing the timing on the DQ data bus. It reserves states for data transfer, +// driver turnaround states, and preambles. It also has the ability to add +// additional programmable delay for read to write changeovers. This read to write +// delay is generated in the column machine which inhibits writes via the +// inhbt_wr signal. +// +// There is a rank machine for every rank. The rank machines are responsible +// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed +// in the bank machine since it is closely coupled to the operation of the +// bank machine and is timing critical. +// +// Since a bank machine can be working on a request for any rank, all rank machines +// inhibits are input to all bank machines. Based on the rank of the current +// request, each bank machine selects the rank information corresponding +// to the rank of its current request. +// +// Since driver turnaround states and WTR delays are so severe with DDRIII, the +// memory interface has the ability to promote requests that use the same +// driver as the most recent request. There is logic in this block that +// detects when the driver for its request is the same as the driver for +// the most recent request. In such a case, this block will send out special +// "same" request early enough to eliminate dead states when there is no +// driver changeover. + + +`timescale 1ps/1ps +`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1) + +module mig_7series_v4_2_bank_state # + ( + parameter TCQ = 100, + parameter ADDR_CMD_MODE = "1T", + parameter BM_CNT_WIDTH = 2, + parameter BURST_MODE = "8", + parameter CWL = 5, + parameter DATA_BUF_ADDR_WIDTH = 8, + parameter DRAM_TYPE = "DDR3", + parameter ECC = "OFF", + parameter ID = 0, + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, + parameter nOP_WAIT = 0, + parameter nRAS_CLKS = 10, + parameter nRP = 10, + parameter nRTP = 4, + parameter nRCD = 5, + parameter nWTP_CLKS = 5, + parameter ORDERING = "NORM", + parameter RANKS = 4, + parameter RANK_WIDTH = 4, + parameter RAS_TIMER_WIDTH = 5, + parameter STARVE_LIMIT = 2 + ) + (/*AUTOARG*/ + // Outputs + start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp, + bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r, + allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row, + act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r, + rd_this_rank_r, rts_pre, rtc, + // Inputs + clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank, + sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r, + phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r, + passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r, + auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in, + start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row, + demand_act_priority_in, order_q_zero, sent_col, q_has_rd, + q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd, + inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config, + rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + input clk; + input rst; + +// Activate wait state machine. + input bm_end; + reg bm_end_r1; + always @(posedge clk) bm_end_r1 <= #TCQ bm_end; + + reg col_wait_r; + + input pass_open_bank_r; + input sending_row; + reg act_wait_r_lcl; + input rcv_open_bank; + wire start_rcd_lcl = act_wait_r_lcl && sending_row; + output wire start_rcd; + assign start_rcd = start_rcd_lcl; + wire act_wait_ns = rst || + ((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) || + bm_end_r1 || (pass_open_bank_r && bm_end)); + always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns; + output wire act_wait_r; + assign act_wait_r = act_wait_r_lcl; + +// RCD timer +// +// When CWL is even, CAS commands are issued on slot 0 and RAS commands are +// issued on slot 1. This implies that the RCD can never expire in the same +// cycle as the RAS (otherwise the CAS for a given transaction would precede +// the RAS). Similarly, this can also cause premature expiration for longer +// RCD. An offset must be added to RCD before translating it to the FPGA clock +// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to +// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to +// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode. +// +// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are +// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS +// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the +// RAS command. In 2:1 mode, there are only 2 slots so direct translation +// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode, +// there are two slots after CAS, so 2 is added to shift the timer into the +// next FPGA cycle for cases that can't expire in the current cycle. +// +// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode, +// It is sufficient to translate to the half-rate domain and add the remainder. +// In 4:1 mode, we must translate to the quarter-rate domain and add an +// additional fabric cycle only if the remainder exceeds the fixed offset of 2 + + localparam nRCD_CLKS = + nCK_PER_CLK == 1 ? + nRCD : + nCK_PER_CLK == 2 ? + ADDR_CMD_MODE == "2T" ? + (nRCD/2) + (nRCD%2) : + CWL % 2 ? + (nRCD/2) : + (nRCD+2) / 2 : +// (nCK_PER_CLK == 4) + ADDR_CMD_MODE == "2T" ? + (nRCD/4) + (nRCD%4 > 2 ? 1 : 0) : + CWL % 2 ? + (nRCD-2 ? (nRCD-2) / 4 + 1 : 1) : + nRCD/4 + 1; + + localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2; + localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1); + localparam ZERO = 0; + localparam ONE = 1; + reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}}; + reg end_rcd; + reg rcd_active_r = 1'b0; + + generate + if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2 + always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl; + end + else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2 + reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns; + always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin + if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0]; + else begin + rcd_timer_ns = rcd_timer_r; + if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0]; + else if (|rcd_timer_r) rcd_timer_ns = + rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0]; + end + end + always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns; + wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]); + always @(posedge clk) end_rcd = end_rcd_ns; + wire rcd_active_ns = |rcd_timer_ns; + always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns; + end + endgenerate + +// Figure out if the read that's completing is for an RMW for +// this bank machine. Delay by a state if CWL != 8 since the +// data is not ready in the RMW buffer for the early write +// data fetch that happens with ECC and CWL != 8. +// Create a state bit indicating we're waiting for the read +// half of the rmw to complete. + input sending_col; + input rd_wr_r; + input req_wr_r; + input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; + input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r; + input phy_rddata_valid; + input rd_rmw; + reg rmw_rd_done = 1'b0; + reg rd_half_rmw_lcl = 1'b0; + output wire rd_half_rmw; + assign rd_half_rmw = rd_half_rmw_lcl; + reg rmw_wait_r = 1'b0; + generate + if (ECC != "OFF") begin : rmw_on +// Delay phy_rddata_valid and rd_rmw by one cycle to align them +// to req_data_buf_addr_r so that rmw_wait_r clears properly + reg phy_rddata_valid_r; + reg rd_rmw_r; + always @(posedge clk) begin + phy_rddata_valid_r <= #TCQ phy_rddata_valid; + rd_rmw_r <= #TCQ rd_rmw; + end + wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r && + (rd_data_addr == req_data_buf_addr_r); + if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns; + else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns; + always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r; + wire rmw_wait_ns = ~rst && + ((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col)); + always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns; + end + endgenerate + +// column wait state machine. + wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd + || rcv_open_bank || (rmw_rd_done && rmw_wait_r)); + always @(posedge clk) col_wait_r <= #TCQ col_wait_ns; + +// Set up various RAS timer parameters, wires, etc. + + localparam TWO = 2; + output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns; + reg [RAS_TIMER_WIDTH-1:0] ras_timer_r; + input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in; + input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r; + +// On a bank pass, select the RAS timer from the passing bank machine. + reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer; + integer i; + always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin + passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}}; + for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1) + if (rb_hit_busies_r[i]) + passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH]; + end + +// RAS and (reused for) WTP timer. When an open bank is passed, this +// timer is passed to the new owner. The existing RAS prevents +// an activate from occuring too early. + + + wire start_wtp_timer = sending_col && ~rd_wr_r; + input idle_r; + + always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl + or start_wtp_timer) begin + if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0]; + else begin + ras_timer_ns = ras_timer_r; + if (start_rcd_lcl) ras_timer_ns = + nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]; + if (start_wtp_timer) ras_timer_ns = + // As the timer is being reused, it is essential to compare + // before new value is loaded. + (ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0] + : ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0]; + if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns = + ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0]; + end + end // always @ (... + + wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank + ? passed_ras_timer + : ras_timer_ns; + always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns; + + wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]); + reg ras_timer_zero_r; + always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns; + +// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of +// one DRAM CK due to column command to row command fixed offset. In 2T mode, +// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T +// mode, in which case we add 1 if the remainder exceeds the fixed offset. + localparam nRTP_CLKS = (nCK_PER_CLK == 1) + ? nRTP : + (nCK_PER_CLK == 2) + ? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) : + (nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2); + localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1; + localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1); + reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns; + reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r; + wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl; + always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r + or sending_col_not_rmw_rd) begin + rtp_timer_ns = rtp_timer_r; + if (rst || pass_open_bank_r) + rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0]; + else begin + if (sending_col_not_rmw_rd) + rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0]; + if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0]; + end + end + always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns; + + wire end_rtp_lcl = ~pass_open_bank_r && + ((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) || + ((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd)); + output wire end_rtp; + assign end_rtp = end_rtp_lcl; + +// Optionally implement open page mode timer. + localparam OP_WIDTH = clogb2(nOP_WAIT + 1); + output wire bank_wait_in_progress; + output wire start_pre_wait; + input passing_open_bank; + input low_idle_cnt_r; + output wire op_exit_req; + input op_exit_grant; + input tail_r; + output reg pre_wait_r; + + generate + if (nOP_WAIT == 0) begin : op_mode_disabled + assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r || + (pre_wait_r && ~ras_timer_zero_r); + assign start_pre_wait = end_rtp_lcl; + assign op_exit_req = 1'b0; + end + else begin : op_mode_enabled + reg op_wait_r; + assign bank_wait_in_progress = sending_col || |rtp_timer_r || + (pre_wait_r && ~ras_timer_zero_r) || + op_wait_r; + wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r) + || op_wait_r); + wire op_wait_ns = ~op_exit_grant && op_active; + always @(posedge clk) op_wait_r <= #TCQ op_wait_ns; + assign start_pre_wait = op_exit_grant || + (end_rtp_lcl && ~tail_r && ~passing_open_bank); + if (nOP_WAIT == -1) + assign op_exit_req = (low_idle_cnt_r && op_active); + else begin : op_cnt + reg [OP_WIDTH-1:0] op_cnt_r; + wire [OP_WIDTH-1:0] op_cnt_ns = + (passing_open_bank || op_exit_grant || rst) + ? ZERO[OP_WIDTH-1:0] + : end_rtp_lcl + ? nOP_WAIT[OP_WIDTH-1:0] + : |op_cnt_r + ? op_cnt_r - ONE[OP_WIDTH-1:0] + : op_cnt_r; + always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns; + assign op_exit_req = (low_idle_cnt_r && op_active) || + (op_wait_r && ~|op_cnt_r); + end + end + endgenerate + + output allow_auto_pre; + wire allow_auto_pre = act_wait_r_lcl || rcd_active_r || + (col_wait_r && ~sending_col); + +// precharge wait state machine. + input auto_pre_r; + wire start_pre; + input pass_open_bank_ns; + wire pre_wait_ns = ~rst && (~pass_open_bank_ns && + (start_pre_wait || (pre_wait_r && ~start_pre))); + always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns; + wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r; + +// precharge timer. + localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP : + (nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) : + /*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0)); + +// Subtract two because there are a minimum of two fabric states from +// end of RP timer until earliest possible arb to send act. + localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2; + localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1); + + input sending_pre; + output rts_pre; + + generate + + if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin + + assign start_pre = pre_wait_r && ras_timer_zero_r && + (sending_pre || auto_pre_r); + + assign rts_pre = ~sending_pre && pre_request; + + end + + else begin + + assign start_pre = pre_wait_r && ras_timer_zero_r && + (sending_row || auto_pre_r); + + assign rts_pre = 1'b0; + + end + + endgenerate + + reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0]; + + generate + if (nRP_CLKS_M2 > ZERO) begin : rp_timer + reg [RP_TIMER_WIDTH-1:0] rp_timer_ns; + always @(/*AS*/rp_timer_r or rst or start_pre) + if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0]; + else begin + rp_timer_ns = rp_timer_r; + if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0]; + else if (|rp_timer_r) rp_timer_ns = + rp_timer_r - ONE[RP_TIMER_WIDTH-1:0]; + end + always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns; + end // block: rp_timer + endgenerate + + output wire precharge_bm_end; + assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) || + (start_pre && (nRP_CLKS_M2 == ZERO)); + +// Compute RRD related activate inhibit. +// Compare this bank machine's rank with others, then +// select result based on grant. An alternative is to +// select the just issued rank with the grant and simply +// compare against this bank machine's rank. However, this +// serializes the selection of the rank and the compare processes. +// As implemented below, the compare occurs first, then the +// selection based on grant. This is faster. + + input [RANK_WIDTH-1:0] req_rank_r; + input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in; + + reg inhbt_act_rrd; + input [(nBANK_MACHS*2)-1:0] start_rcd_in; + + generate + integer j; + if (RANKS == 1) + always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin + inhbt_act_rrd = 1'b0; + for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1) + inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j]; + end + else begin + always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin + inhbt_act_rrd = 1'b0; + for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1) + inhbt_act_rrd = inhbt_act_rrd || + (start_rcd_in[j] && + (req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r)); + end + end + + endgenerate + +// Extract the activate command inhibit for the rank associated +// with this request. FAW and RRD are computed separately so that +// gate level timing can be carefully managed. + input [RANKS-1:0] inhbt_act_faw_r; + wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r]; + + input wait_for_maint_r; + input head_r; + wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r && + ~wait_for_maint_r; + +// Implement simple starvation avoidance for act requests. Precharge +// requests don't need this because they are never gated off by +// timing events such as inhbt_act_rrd. Priority request timeout +// is fixed at a single trip around the round robin arbiter. + + input sent_row; + wire rts_act_denied = act_req && sent_row && ~sending_row; + + reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns; + reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r; + + generate + if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2 + begin :BM_MORE_THAN_2 + always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied) + begin + act_starve_limit_cntr_ns = act_starve_limit_cntr_r; + if (~act_req) + act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}}; + else + if (rts_act_denied && &act_starve_limit_cntr_r) + act_starve_limit_cntr_ns = act_starve_limit_cntr_r + + {{BM_CNT_WIDTH-1{1'b0}}, 1'b1}; + end + end + else // Number of Bank Machs == 2 + begin :BM_EQUAL_2 + always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied) + begin + act_starve_limit_cntr_ns = act_starve_limit_cntr_r; + if (~act_req) + act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}}; + else + if (rts_act_denied && &act_starve_limit_cntr_r) + act_starve_limit_cntr_ns = act_starve_limit_cntr_r + + {1'b1}; + end + end + endgenerate + + always @(posedge clk) act_starve_limit_cntr_r <= + #TCQ act_starve_limit_cntr_ns; + + reg demand_act_priority_r; + wire demand_act_priority_ns = act_req && + (demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r)); + always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns; + +`ifdef MC_SVA + cover_demand_act_priority: + cover property (@(posedge clk) (~rst && demand_act_priority_r)); +`endif + + output wire demand_act_priority; + assign demand_act_priority = demand_act_priority_r && ~sending_row; + +// compute act_demanded from other demand_act_priorities + input [(nBANK_MACHS*2)-1:0] demand_act_priority_in; + reg act_demanded = 1'b0; + generate + if (nBANK_MACHS > 1) begin : compute_act_demanded + always @(demand_act_priority_in[`BM_SHARED_BV]) + act_demanded = |demand_act_priority_in[`BM_SHARED_BV]; + end + endgenerate + + wire row_demand_ok = demand_act_priority_r || ~act_demanded; + +// Generate the Request To Send row arbitation signal. + output wire rts_row; + + generate + + if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) + assign rts_row = ~sending_row && row_demand_ok && + (act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd); + else + assign rts_row = ~sending_row && row_demand_ok && + ((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) || + pre_request); + endgenerate + +`ifdef MC_SVA + four_activate_window_wait: + cover property (@(posedge clk) + (~rst && ~sending_row && act_req && my_inhbt_act_faw)); + ras_ras_delay_wait: + cover property (@(posedge clk) + (~rst && ~sending_row && act_req && inhbt_act_rrd)); +`endif + +// Provide rank machines early knowledge that this bank machine is +// going to send an activate to the rank. In this way, the rank +// machines just need to use the sending_row wire to figure out if +// they need to keep track of the activate. + output reg [RANKS-1:0] act_this_rank_r; + reg [RANKS-1:0] act_this_rank_ns; + always @(/*AS*/act_wait_r or req_rank_r) begin + act_this_rank_ns = {RANKS{1'b0}}; + for (i = 0; i < RANKS; i = i + 1) + act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r); + end + always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns; + + +// Generate request to send column command signal. + + input order_q_zero; + wire req_bank_rdy_ns = order_q_zero && col_wait_r; + reg req_bank_rdy_r; + always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns; + +// Determine is we have been denied a column command request. + input sent_col; + wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col; + +// Implement a starvation limit counter. Count the number of times a +// request to send a column command has been denied. + localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS; + localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT); + reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r; + reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns; + always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r) + if (~col_wait_r) + starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}}; + else + if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1)) + starve_limit_cntr_ns = starve_limit_cntr_r + + {{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1}; + else starve_limit_cntr_ns = starve_limit_cntr_r; + always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns; + + input q_has_rd; + input q_has_priority; + +// Decide if this bank machine should demand priority. Priority is demanded +// when starvation limit counter is reached, or a bit in the request. + wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) && + rts_col_denied); + input req_priority_r; + input idle_ns; + reg demand_priority_r; + wire demand_priority_ns = ~idle_ns && col_wait_ns && + (demand_priority_r || + (order_q_zero && + (req_priority_r || q_has_priority)) || + (starved && (q_has_rd || ~req_wr_r))); + + always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns; + +`ifdef MC_SVA + wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns && + col_wait_ns; + req_triggers_demand_priority: + cover property (@(posedge clk) + (rdy_for_priority && req_priority_r && ~q_has_priority && ~starved)); + q_priority_triggers_demand_priority: + cover property (@(posedge clk) + (rdy_for_priority && ~req_priority_r && q_has_priority && ~starved)); + wire not_req_or_q_rdy_for_priority = + rdy_for_priority && ~req_priority_r && ~q_has_priority; + starved_req_triggers_demand_priority: + cover property (@(posedge clk) + (not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r)); + starved_q_triggers_demand_priority: + cover property (@(posedge clk) + (not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r)); +`endif + +// compute demanded from other demand_priorities + input [(nBANK_MACHS*2)-1:0] demand_priority_in; + reg demanded = 1'b0; + generate + if (nBANK_MACHS > 1) begin : compute_demanded + always @(demand_priority_in[`BM_SHARED_BV]) demanded = + |demand_priority_in[`BM_SHARED_BV]; + end + endgenerate + + +// In order to make sure that there is no starvation amongst a possibly +// unlimited stream of priority requests, add a second stage to the demand +// priority signal. If there are no other requests demanding priority, then +// go ahead and assert demand_priority. If any other requests are asserting +// demand_priority, hold off asserting demand_priority until these clear, then +// assert demand priority. Its possible to get multiple requests asserting +// demand priority simultaneously, but that's OK. Those requests will be +// serviced, demanded will fall, and another group of requests will be +// allowed to assert demand_priority. + + reg demanded_prior_r; + wire demanded_prior_ns = demanded && + (demanded_prior_r || ~demand_priority_r); + always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns; + + output wire demand_priority; + assign demand_priority = demand_priority_r && ~demanded_prior_r && + ~sending_col; + +`ifdef MC_SVA + demand_priority_gated: + cover property (@(posedge clk) (demand_priority_r && ~demand_priority)); + generate + if (nBANK_MACHS >1) multiple_demand_priority: + cover property (@(posedge clk) + ($countones(demand_priority_in[`BM_SHARED_BV]) > 1)); + endgenerate +`endif + + wire demand_ok = demand_priority_r || ~demanded; + + // Figure out if the request in this bank machine matches the current rank + // configuration. + input rnk_config_strobe; + input rnk_config_kill_rts_col; + input rnk_config_valid_r; + input [RANK_WIDTH-1:0] rnk_config; + output wire rtc; + + wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r); + assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok; + +// Using rank state provided by the rank machines, figure out if +// a read requests should wait for WTR or RTW. + input [RANKS-1:0] inhbt_rd; + wire my_inhbt_rd = inhbt_rd[req_rank_r]; + input [RANKS-1:0] inhbt_wr; + wire my_inhbt_wr = inhbt_wr[req_rank_r]; + wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd; + +// DQ bus timing constraints. + input dq_busy_data; + +// Column command is ready to arbitrate, except for databus restrictions. + wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) || + (rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") || + (rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) && + order_q_zero; + +// Column command is ready to arbitrate for sending a write. Used +// to generate early wr_data_addr for ECC mode. + output wire col_rdy_wr; + assign col_rdy_wr = col_rdy && ~rd_wr_r; + +// Figure out if we're ready to send a column command based on all timing +// constraints. +// if timing is an issue. + wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match; + +`ifdef MC_SVA + col_wait_for_order_q: cover property + (@(posedge clk) + (~rst && col_wait_r && ~order_q_zero && ~dq_busy_data && + allow_rw)); + col_wait_for_dq_busy: cover property + (@(posedge clk) + (~rst && col_wait_r && order_q_zero && dq_busy_data && + allow_rw)); + col_wait_for_allow_rw: cover property + (@(posedge clk) + (~rst && col_wait_r && order_q_zero && ~dq_busy_data && + ~allow_rw)); +`endif + +// Implement flow control for the command and control FIFOs and for the data +// FIFO during writes + input phy_mc_ctl_full; + input phy_mc_cmd_full; + input phy_mc_data_full; + + // Register ctl_full and cmd_full + reg phy_mc_ctl_full_r = 1'b0; + reg phy_mc_cmd_full_r = 1'b0; + always @(posedge clk) + if(rst) begin + phy_mc_ctl_full_r <= #TCQ 1'b0; + phy_mc_cmd_full_r <= #TCQ 1'b0; + end else begin + phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full; + phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full; + end + + // register output data pre-fifo almost full condition and fold in WR status + reg ofs_rdy_r = 1'b0; + always @(posedge clk) + if(rst) + ofs_rdy_r <= #TCQ 1'b0; + else + ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r); + +// Disable priority feature for one state after a config to insure +// forward progress on the just installed io config. + reg override_demand_r; + wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col; + always @(posedge clk) override_demand_r <= override_demand_ns; + output wire rts_col; + assign rts_col = ~sending_col && (demand_ok || override_demand_r) && + col_cmd_rts && ofs_rdy_r; + +// As in act_this_rank, wr/rd_this_rank informs rank machines +// that this bank machine is doing a write/rd. Removes logic +// after the grant. + reg [RANKS-1:0] wr_this_rank_ns; + reg [RANKS-1:0] rd_this_rank_ns; + always @(/*AS*/rd_wr_r or req_rank_r) begin + wr_this_rank_ns = {RANKS{1'b0}}; + rd_this_rank_ns = {RANKS{1'b0}}; + for (i=0; i= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0 + always @(posedge clk) offset_r1 <= + #TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0]; + always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr; + end + if(nPHY_WRLAT == 2) begin : offset_pipe_1 + always @(posedge clk) offset_r2 <= + #TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]; + always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1; + end + endgenerate + + output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; + assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1) + ? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0] + : (EARLY_WR_DATA_ADDR == "OFF") + ? offset_r[DATA_BUF_OFFSET_WIDTH-1:0] + : offset_ns[DATA_BUF_OFFSET_WIDTH-1:0]; + + reg sent_col_r1; + reg sent_col_r2; + always @(posedge clk) sent_col_r1 <= #TCQ sent_col; + always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1; + + wire wrdata_en = (nPHY_WRLAT == 0) ? + (sent_col || |offset_r) & ~col_rd_wr : + (nPHY_WRLAT == 1) ? + (sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 : + //(nPHY_WRLAT >= 2) ? + (sent_col_r2 || |offset_r2) & ~col_rd_wr_r2; + + output wire mc_wrdata_en; + assign mc_wrdata_en = wrdata_en; + + output wire wr_data_en; + assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1) + ? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1) + : ((sent_col || |offset_r) && ~col_rd_wr); + + + input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; + output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; + generate + if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1 + reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r; + always @(posedge clk) col_wr_data_buf_addr_r <= + #TCQ col_wr_data_buf_addr; + assign wr_data_addr = col_wr_data_buf_addr_r; + end + else begin : delay_wr_data_cntrl_ne_1 + assign wr_data_addr = col_wr_data_buf_addr; + end + endgenerate + +// CAS-RD to mc_rddata_en + + wire read_data_valid = (sent_col || |offset_r) && col_rd_wr; + +function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end +endfunction // clogb2 + +// Implement FIFO that records reads as they are sent to the DRAM. +// When phy_rddata_valid is returned some unknown time later, the +// FIFO output is used to control how the data is interpreted. + + input phy_rddata_valid; + output wire rd_rmw; + output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; + output reg ecc_status_valid; + output reg wr_ecc_buf; + output reg rd_data_end; + output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; + output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; + output reg rd_data_en /* synthesis syn_maxfan = 10 */; + output col_read_fifo_empty; + + input col_periodic_rd; + input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; + input col_rmw; + input [RANK_WIDTH-1:0] col_ra; + input [BANK_WIDTH-1:0] col_ba; + input [ROW_WIDTH-1:0] col_row; + input [ROW_WIDTH-1:0] col_a; + + // Real column address (skip A10/AP and A12/BC#). The maximum width is 12; + // the width will be tailored for the target DRAM downstream. + wire [11:0] col_a_full; + + // Minimum row width is 12; take remaining 11 bits after omitting A10/AP + assign col_a_full[10:0] = {col_a[11], col_a[9:0]}; + + // Get the 12th bit when row address width accommodates it; omit A12/BC# + generate + if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1 + assign col_a_full[11] = col_a[13]; + end else begin : COL_A_FULL_11_0 + assign col_a_full[11] = 0; + end + endgenerate + + // Extract only the width of the target DRAM + wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0]; + + localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH; + localparam FIFO_WIDTH = 1 /*data_end*/ + + 1 /*periodic_rd*/ + + DATA_BUF_ADDR_WIDTH + + DATA_BUF_OFFSET_WIDTH + + ((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH); + localparam FULL_RAM_CNT = (FIFO_WIDTH/6); + localparam REMAINDER = FIFO_WIDTH % 6; + localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); + localparam RAM_WIDTH = (RAM_CNT*6); + + generate + begin : read_fifo + + wire [MC_ERR_LINE_WIDTH:0] ecc_line; + if (CS_WIDTH == 1) + assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted}; + else + assign ecc_line = {col_rmw, + col_ra, + col_ba, + col_row, + col_a_extracted}; + + wire [FIFO_WIDTH-1:0] real_fifo_data; + if (ECC == "OFF") + assign real_fifo_data = {data_end, + col_periodic_rd, + col_data_buf_addr, + offset_r[DATA_BUF_OFFSET_WIDTH-1:0]}; + else + assign real_fifo_data = {data_end, + col_periodic_rd, + col_data_buf_addr, + offset_r[DATA_BUF_OFFSET_WIDTH-1:0], + ecc_line}; + + wire [RAM_WIDTH-1:0] fifo_in_data; + if (REMAINDER == 0) + assign fifo_in_data = real_fifo_data; + else + assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data}; + + wire [RAM_WIDTH-1:0] fifo_out_data_ns; + + reg [4:0] head_r; + wire [4:0] head_ns = rst ? 5'b0 : read_data_valid + ? (head_r + 5'b1) + : head_r; + always @(posedge clk) head_r <= #TCQ head_ns; + + + reg [4:0] tail_r; + wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid + ? (tail_r + 5'b1) + : tail_r; + always @(posedge clk) tail_r <= #TCQ tail_ns; + + assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0; + + genvar i; + for (i=0; iout delay(sim only) + parameter ADDR_CMD_MODE = "1T", // registered or + // 1Tfered mem? + parameter BANK_WIDTH = 3, // bank address width + parameter BM_CNT_WIDTH = 2, // # BM counter width + // i.e., log2(nBANK_MACHS) + parameter BURST_MODE = "8", // Burst length + parameter CL = 5, // Read CAS latency + // (in clk cyc) + parameter CMD_PIPE_PLUS1 = "ON", // add register stage + // between MC and PHY + parameter COL_WIDTH = 12, // column address width + parameter CS_WIDTH = 4, // # of unique CS outputs + parameter CWL = 5, // Write CAS latency + // (in clk cyc) + parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g. + // user src/dest buf addr) + parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width + parameter DATA_WIDTH = 64, // Data bus width + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_TYPE = "DDR3", // Memory I/F type: + // "DDR3", "DDR2" + parameter ECC = "OFF", // ECC ON/OFF? + parameter ECC_WIDTH = 8, // # of ECC bits + parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps) + parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits + parameter nBANK_MACHS = 4, // # of bank machines (BM) + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + // frequency ratio + parameter nCS_PER_RANK = 1, // # of unique CS outputs + // per rank + parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in + parameter nSLOTS = 1, // # DIMM slots in system + parameter ORDERING = "NORM", // request ordering mode + parameter PAYLOAD_WIDTH = 64, // Width of data payload + // from PHY + parameter RANK_WIDTH = 2, // # of bits to count ranks + parameter RANKS = 4, // # of ranks of DRAM + parameter REG_CTRL = "ON", // "ON" for registered DIMM + parameter ROW_WIDTH = 16, // row address width + parameter RTT_NOM = "40", // Nominal ODT value + parameter RTT_WR = "120", // Write ODT value + parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0 + parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1 + parameter STARVE_LIMIT = 2, // max # of times a user + // request is allowed to + // lose arbitration when + // reordering is enabled + parameter tCK = 2500, // memory clk period(ps) + parameter tCKE = 10000, // CKE minimum pulse (ps) + parameter tFAW = 40000, // four activate window(ps) + parameter tRAS = 37500, // ACT->PRE cmd period (ps) + parameter tRCD = 12500, // ACT->R/W delay (ps) + parameter tREFI = 7800000, // average periodic + // refresh interval(ps) + parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal + parameter tRFC = 110000, // REF->ACT/REF delay (ps) + parameter tRP = 12500, // PRE cmd period (ps) + parameter tRRD = 10000, // ACT->ACT period (ps) + parameter tRTP = 7500, // Read->PRE cmd delay (ps) + parameter tWTR = 7500, // Internal write->read + // delay (ps) + // requiring DLL lock (CKs) + parameter tZQCS = 64, // ZQCS cmd period (CKs) + parameter tZQI = 128_000_000, // ZQCS interval (ps) + parameter tPRDI = 1_000_000, // pS + parameter USER_REFRESH = "OFF" // Whether user manages REF + ) + ( + + // System inputs + + input clk, + input rst, + + // Physical memory slot presence + + input [7:0] slot_0_present, + input [7:0] slot_1_present, + + // Native Interface + + input [2:0] cmd, + input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, + input hi_priority, + input size, + + input [BANK_WIDTH-1:0] bank, + input [COL_WIDTH-1:0] col, + input [RANK_WIDTH-1:0] rank, + input [ROW_WIDTH-1:0] row, + input use_addr, + + input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data, + input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask, + + output accept, + output accept_ns, + + output [BM_CNT_WIDTH-1:0] bank_mach_next, + + output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data, + output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, + output rd_data_en, + output rd_data_end, + output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, + + output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */, + output reg wr_data_en, +output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */, + + output mc_read_idle, + output mc_ref_zq_wip, + + // ECC interface + + input correct_en, + input [2*nCK_PER_CLK-1:0] raw_not_ecc, + + input [DQS_WIDTH - 1:0] fi_xor_we, + input [DQ_WIDTH -1 :0 ] fi_xor_wrdata, + + output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr, + output [2*nCK_PER_CLK-1:0] ecc_single, + output [2*nCK_PER_CLK-1:0] ecc_multiple, + + // User maintenance requests + + input app_periodic_rd_req, + input app_ref_req, + input app_zq_req, + input app_sr_req, + output app_sr_active, + output app_ref_ack, + output app_zq_ack, + + // MC <==> PHY Interface + + output reg [nCK_PER_CLK-1:0] mc_ras_n, + output reg [nCK_PER_CLK-1:0] mc_cas_n, + output reg [nCK_PER_CLK-1:0] mc_we_n, + output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, + output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, + output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, + output reg [1:0] mc_odt, + output reg [nCK_PER_CLK-1:0] mc_cke, + output wire mc_reset_n, + output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, + output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask, + output reg mc_wrdata_en, + + output wire mc_cmd_wren, + output wire mc_ctl_wren, + output reg [2:0] mc_cmd, + output reg [5:0] mc_data_offset, + output reg [5:0] mc_data_offset_1, + output reg [5:0] mc_data_offset_2, + output reg [1:0] mc_cas_slot, + output reg [3:0] mc_aux_out0, + output reg [3:0] mc_aux_out1, + output reg [1:0] mc_rank_cnt, + + input phy_mc_ctl_full, + input phy_mc_cmd_full, + input phy_mc_data_full, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, + input phy_rddata_valid, + + input init_calib_complete, + input [6*RANKS-1:0] calib_rd_data_offset, + input [6*RANKS-1:0] calib_rd_data_offset_1, + input [6*RANKS-1:0] calib_rd_data_offset_2 + + ); + + assign mc_reset_n = 1'b1; // never reset memory + assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle) + assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle) + + // Ensure there is always at least one rank present during operation + `ifdef MC_SVA + ranks_present: assert property + (@(posedge clk) (rst || (|(slot_0_present | slot_1_present)))); + `endif + + // Reserved. Do not change. + localparam nPHY_WRLAT = 2; + + // always delay write data control unless ECC mode is enabled + localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1; + + // Ensure that write control is delayed for appropriate CWL + /*`ifdef MC_SVA + delay_wr_data_zero_CWL_le_6: assert property + (@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0))); + `endif*/ + + // Never retrieve WR_DATA_ADDR early + localparam EARLY_WR_DATA_ADDR = "OFF"; + + //*************************************************************************** + // Convert timing parameters from time to clock cycles + //*************************************************************************** + + localparam nCKE = cdiv(tCKE, tCK); + localparam nRP = cdiv(tRP, tCK); + localparam nRCD = cdiv(tRCD, tCK); + localparam nRAS = cdiv(tRAS, tCK); + localparam nFAW = cdiv(tFAW, tCK); + localparam nRFC = cdiv(tRFC, tCK); + + // Convert tWR. As per specification, write recover for autoprecharge + // cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12 + localparam nWR_CK = cdiv(15000, tCK) ; + localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK; + + // tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2 + localparam nRRD_CK = cdiv(tRRD, tCK); + localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK + : (nRRD_CK < 2) ? 2 : nRRD_CK; + localparam nWTR_CK = cdiv(tWTR, tCK); + localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK + : (nWTR_CK < 2) ? 2 : nWTR_CK; + localparam nRTP_CK = cdiv(tRTP, tCK); + localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK + : (nRTP_CK < 2) ? 2 : nRTP_CK; + + // Add a cycle to CL/CWL for the register in RDIMM devices + localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; + localparam CL_M = (REG_CTRL == "ON") ? CL + 1 : CL; + + // Tuneable delay between read and write data on the DQ bus + localparam DQRD2DQWR_DLY = 4; + + // CKE minimum pulse width for self-refresh (SRE->SRX minimum time) + localparam nCKESR = nCKE + 1; + + // Delay from SRE to command requiring locked DLL. Currently fixed at 512 for + // all devices per JEDEC spec. + localparam tXSDLL = 512; + + //*************************************************************************** + // Set up maintenance counter dividers + //*************************************************************************** + + // CK clock divisor to generate maintenance prescaler period (round down) + localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK); + + // Maintenance prescaler divisor for refresh timer. Essentially, this is + // just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst + // case delay from the time we get a tick from the refresh counter to the + // time that we can actually issue the REF command. Thus, subtract tRCD, CL, + // data burst time and tRP for each implemented bank machine to ensure that + // all transactions can complete before tREFI expires + localparam REFRESH_TIMER_DIV = + USER_REFRESH == "ON" ? 0 : + (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD; + + // Periodic read (RESERVED - not currently required or supported in 7 series) + // tPRDI should only be set to 0 + // localparam tPRDI = 0; // Do NOT change. + localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD; + + // Convert maintenance prescaler from ps to ns + localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000; + + // Maintenance prescaler divisor for ZQ calibration (ZQCS) timer + localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS; + + // Bus width required to broadcast a single bit rank signal among all the + // bank machines - 1 bit per rank, per bank + localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS; + + //*************************************************************************** + // Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands + //*************************************************************************** + localparam EVEN_CWL_2T_MODE = + ((ADDR_CMD_MODE == "2T") && (!(CWL % 2))) ? "ON" : "OFF"; + + //*************************************************************************** + // Reserved feature control. + //*************************************************************************** + + // Open page wait mode is reserved. + // nOP_WAIT is the number of states a bank machine will park itself + // on an otherwise inactive open page before closing the page. If + // nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1, + // the bank machine will remain parked until the pool of idle bank machines + // are less than LOW_IDLE_CNT. At which point parked bank machines + // are selected to exit until the number of idle bank machines exceeds the + // LOW_IDLE_CNT. + localparam nOP_WAIT = 0; // Open page mode + localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold + + //*************************************************************************** + // Internal wires + //*************************************************************************** + + wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; + wire [ROW_WIDTH-1:0] col_a; + wire [BANK_WIDTH-1:0] col_ba; + wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; + wire col_periodic_rd; + wire [RANK_WIDTH-1:0] col_ra; + wire col_rmw; + wire col_rd_wr; + wire [ROW_WIDTH-1:0] col_row; + wire col_size; + wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; + wire dq_busy_data; + wire ecc_status_valid; + wire [RANKS-1:0] inhbt_act_faw_r; + wire [RANKS-1:0] inhbt_rd; + wire [RANKS-1:0] inhbt_wr; + wire insert_maint_r1; + wire [RANK_WIDTH-1:0] maint_rank_r; + wire maint_req_r; + wire maint_wip_r; + wire maint_zq_r; + wire maint_sre_r; + wire maint_srx_r; + wire periodic_rd_ack_r; + wire periodic_rd_r; + wire [RANK_WIDTH-1:0] periodic_rd_rank_r; + wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; + wire rd_rmw; + wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; + wire [nBANK_MACHS-1:0] sending_col; + wire [nBANK_MACHS-1:0] sending_row; + wire sent_col; + wire sent_col_r; + wire wr_ecc_buf; + wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; + + // MC/PHY optional pipeline stage support + wire [nCK_PER_CLK-1:0] mc_ras_n_ns; + wire [nCK_PER_CLK-1:0] mc_cas_n_ns; + wire [nCK_PER_CLK-1:0] mc_we_n_ns; + wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns; + wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns; + wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns; + wire [1:0] mc_odt_ns; + wire [nCK_PER_CLK-1:0] mc_cke_ns; + wire [3:0] mc_aux_out0_ns; + wire [3:0] mc_aux_out1_ns; + wire [1:0] mc_rank_cnt_ns = col_ra; + wire [2:0] mc_cmd_ns; + wire [5:0] mc_data_offset_ns; + wire [5:0] mc_data_offset_1_ns; + wire [5:0] mc_data_offset_2_ns; + wire [1:0] mc_cas_slot_ns; + wire mc_wrdata_en_ns; + + wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns; + wire wr_data_en_ns; + wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns; + + integer i; + + // MC Read idle support + wire col_read_fifo_empty; + wire mc_read_idle_ns; + reg mc_read_idle_r; + + // MC Maintenance in progress with bus idle indication + wire maint_ref_zq_wip; + wire mc_ref_zq_wip_ns; + reg mc_ref_zq_wip_r; + + //*************************************************************************** + // Function cdiv + // Description: + // This function performs ceiling division (divide and round-up) + // Inputs: + // num: integer to be divided + // div: divisor + // Outputs: + // cdiv: result of ceiling division (num/div, rounded up) + //*************************************************************************** + + function integer cdiv (input integer num, input integer div); + begin + // perform division, then add 1 if and only if remainder is non-zero + cdiv = (num/div) + (((num%div)>0) ? 1 : 0); + end + endfunction // cdiv + + //*************************************************************************** + // Optional pipeline register stage on MC/PHY interface + //*************************************************************************** + + generate + + if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface + + always @(posedge clk) begin + + mc_address <= #TCQ mc_address_ns; + mc_bank <= #TCQ mc_bank_ns; + mc_cas_n <= #TCQ mc_cas_n_ns; + mc_cs_n <= #TCQ mc_cs_n_ns; + mc_odt <= #TCQ mc_odt_ns; + mc_cke <= #TCQ mc_cke_ns; + mc_aux_out0 <= #TCQ mc_aux_out0_ns; + mc_aux_out1 <= #TCQ mc_aux_out1_ns; + mc_cmd <= #TCQ mc_cmd_ns; + mc_ras_n <= #TCQ mc_ras_n_ns; + mc_we_n <= #TCQ mc_we_n_ns; + mc_data_offset <= #TCQ mc_data_offset_ns; + mc_data_offset_1 <= #TCQ mc_data_offset_1_ns; + mc_data_offset_2 <= #TCQ mc_data_offset_2_ns; + mc_cas_slot <= #TCQ mc_cas_slot_ns; + mc_wrdata_en <= #TCQ mc_wrdata_en_ns; + mc_rank_cnt <= #TCQ mc_rank_cnt_ns; + + wr_data_addr <= #TCQ wr_data_addr_ns; + wr_data_en <= #TCQ wr_data_en_ns; + wr_data_offset <= #TCQ wr_data_offset_ns; + + end // always @ (posedge clk) + + end // block: cmd_pipe_plus + + else begin : cmd_pipe_plus0 // don't register interface + + always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or + mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or + mc_odt_ns or mc_cke_ns or mc_data_offset_ns or + mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or + mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or + wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or + mc_cas_slot_ns) + begin + + mc_address = #TCQ mc_address_ns; + mc_bank = #TCQ mc_bank_ns; + mc_cas_n = #TCQ mc_cas_n_ns; + mc_cs_n = #TCQ mc_cs_n_ns; + mc_odt = #TCQ mc_odt_ns; + mc_cke = #TCQ mc_cke_ns; + mc_aux_out0 = #TCQ mc_aux_out0_ns; + mc_aux_out1 = #TCQ mc_aux_out1_ns; + mc_cmd = #TCQ mc_cmd_ns; + mc_ras_n = #TCQ mc_ras_n_ns; + mc_we_n = #TCQ mc_we_n_ns; + mc_data_offset = #TCQ mc_data_offset_ns; + mc_data_offset_1 = #TCQ mc_data_offset_1_ns; + mc_data_offset_2 = #TCQ mc_data_offset_2_ns; + mc_cas_slot = #TCQ mc_cas_slot_ns; + mc_wrdata_en = #TCQ mc_wrdata_en_ns; + mc_rank_cnt = #TCQ mc_rank_cnt_ns; + + wr_data_addr = #TCQ wr_data_addr_ns; + wr_data_en = #TCQ wr_data_en_ns; + wr_data_offset = #TCQ wr_data_offset_ns; + + end // always @ (... + + end // block: cmd_pipe_plus0 + + endgenerate + + //*************************************************************************** + // Indicate when there are no pending reads so that input features can be + // powered down + //*************************************************************************** + + assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete; + always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns; + assign mc_read_idle = mc_read_idle_r; + + //*************************************************************************** + // Indicate when there is a refresh in progress and the bus is idle so that + // tap adjustments can be made + //*************************************************************************** + + assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty; + always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns; + assign mc_ref_zq_wip = mc_ref_zq_wip_r; + + //*************************************************************************** + // Manage rank-level timing and maintanence + //*************************************************************************** + + mig_7series_v4_2_rank_mach # + ( + // Parameters + .BURST_MODE (BURST_MODE), + .CL (CL), + .CWL (CWL), + .CS_WIDTH (CS_WIDTH), + .DQRD2DQWR_DLY (DQRD2DQWR_DLY), + .DRAM_TYPE (DRAM_TYPE), + .MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV), + .nBANK_MACHS (nBANK_MACHS), + .nCKESR (nCKESR), + .nCK_PER_CLK (nCK_PER_CLK), + .nFAW (nFAW), + .nREFRESH_BANK (nREFRESH_BANK), + .nRRD (nRRD), + .nWTR (nWTR), + .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV), + .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), + .RANK_WIDTH (RANK_WIDTH), + .RANKS (RANKS), + .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV), + .ZQ_TIMER_DIV (ZQ_TIMER_DIV) + ) + rank_mach0 + ( + // Outputs + .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), + .inhbt_rd (inhbt_rd[RANKS-1:0]), + .inhbt_wr (inhbt_wr[RANKS-1:0]), + .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), + .maint_req_r (maint_req_r), + .maint_zq_r (maint_zq_r), + .maint_sre_r (maint_sre_r), + .maint_srx_r (maint_srx_r), + .maint_ref_zq_wip (maint_ref_zq_wip), + .periodic_rd_r (periodic_rd_r), + .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), + // Inputs + .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), + .app_periodic_rd_req (app_periodic_rd_req), + .app_ref_req (app_ref_req), + .app_ref_ack (app_ref_ack), + .app_zq_req (app_zq_req), + .app_zq_ack (app_zq_ack), + .app_sr_req (app_sr_req), + .app_sr_active (app_sr_active), + .col_rd_wr (col_rd_wr), + .clk (clk), + .init_calib_complete (init_calib_complete), + .insert_maint_r1 (insert_maint_r1), + .maint_wip_r (maint_wip_r), + .periodic_rd_ack_r (periodic_rd_ack_r), + .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), + .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), + .rst (rst), + .sending_col (sending_col[nBANK_MACHS-1:0]), + .sending_row (sending_row[nBANK_MACHS-1:0]), + .slot_0_present (slot_0_present[7:0]), + .slot_1_present (slot_1_present[7:0]), + .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]) + ); + + //*************************************************************************** + // Manage requests, reordering and bank timing + //*************************************************************************** + + mig_7series_v4_2_bank_mach # + ( + // Parameters + .TCQ (TCQ), + .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .BANK_WIDTH (BANK_WIDTH), + .BM_CNT_WIDTH (BM_CNT_WIDTH), + .BURST_MODE (BURST_MODE), + .COL_WIDTH (COL_WIDTH), + .CS_WIDTH (CS_WIDTH), + .CL (CL_M), + .CWL (CWL_M), + .CKE_ODT_AUX (CKE_ODT_AUX), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), + .ECC (ECC), + .LOW_IDLE_CNT (LOW_IDLE_CNT), + .nBANK_MACHS (nBANK_MACHS), + .nCK_PER_CLK (nCK_PER_CLK), + .nCS_PER_RANK (nCS_PER_RANK), + .nOP_WAIT (nOP_WAIT), + .nRAS (nRAS), + .nRCD (nRCD), + .nRFC (nRFC), + .nRP (nRP), + .nRTP (nRTP), + .nSLOTS (nSLOTS), + .nWR (nWR), + .nXSDLL (tXSDLL), + .ORDERING (ORDERING), + .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), + .RANK_WIDTH (RANK_WIDTH), + .RANKS (RANKS), + .ROW_WIDTH (ROW_WIDTH), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .SLOT_0_CONFIG (SLOT_0_CONFIG), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .STARVE_LIMIT (STARVE_LIMIT), + .tZQCS (tZQCS) + ) + bank_mach0 + ( + // Outputs + .accept (accept), + .accept_ns (accept_ns), + .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), + .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), + .col_a (col_a[ROW_WIDTH-1:0]), + .col_ba (col_ba[BANK_WIDTH-1:0]), + .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .col_periodic_rd (col_periodic_rd), + .col_ra (col_ra[RANK_WIDTH-1:0]), + .col_rmw (col_rmw), + .col_rd_wr (col_rd_wr), + .col_row (col_row[ROW_WIDTH-1:0]), + .col_size (col_size), + .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .mc_bank (mc_bank_ns), + .mc_address (mc_address_ns), + .mc_ras_n (mc_ras_n_ns), + .mc_cas_n (mc_cas_n_ns), + .mc_we_n (mc_we_n_ns), + .mc_cs_n (mc_cs_n_ns), + .mc_odt (mc_odt_ns), + .mc_cke (mc_cke_ns), + .mc_aux_out0 (mc_aux_out0_ns), + .mc_aux_out1 (mc_aux_out1_ns), + .mc_cmd (mc_cmd_ns), + .mc_data_offset (mc_data_offset_ns), + .mc_data_offset_1 (mc_data_offset_1_ns), + .mc_data_offset_2 (mc_data_offset_2_ns), + .mc_cas_slot (mc_cas_slot_ns), + .insert_maint_r1 (insert_maint_r1), + .maint_wip_r (maint_wip_r), + .periodic_rd_ack_r (periodic_rd_ack_r), + .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), + .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), + .sending_row (sending_row[nBANK_MACHS-1:0]), + .sending_col (sending_col[nBANK_MACHS-1:0]), + .sent_col (sent_col), + .sent_col_r (sent_col_r), + .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]), + // Inputs + .bank (bank[BANK_WIDTH-1:0]), + .calib_rddata_offset (calib_rd_data_offset), + .calib_rddata_offset_1 (calib_rd_data_offset_1), + .calib_rddata_offset_2 (calib_rd_data_offset_2), + .clk (clk), + .cmd (cmd[2:0]), + .col (col[COL_WIDTH-1:0]), + .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .init_calib_complete (init_calib_complete), + .phy_rddata_valid (phy_rddata_valid), + .dq_busy_data (dq_busy_data), + .hi_priority (hi_priority), + .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), + .inhbt_rd (inhbt_rd[RANKS-1:0]), + .inhbt_wr (inhbt_wr[RANKS-1:0]), + .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), + .maint_req_r (maint_req_r), + .maint_zq_r (maint_zq_r), + .maint_sre_r (maint_sre_r), + .maint_srx_r (maint_srx_r), + .periodic_rd_r (periodic_rd_r), + .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), + .phy_mc_cmd_full (phy_mc_cmd_full), + .phy_mc_ctl_full (phy_mc_ctl_full), + .phy_mc_data_full (phy_mc_data_full), + .rank (rank[RANK_WIDTH-1:0]), + .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .rd_rmw (rd_rmw), + .row (row[ROW_WIDTH-1:0]), + .rst (rst), + .size (size), + .slot_0_present (slot_0_present[7:0]), + .slot_1_present (slot_1_present[7:0]), + .use_addr (use_addr) + ); + + //*************************************************************************** + // Manage DQ bus + //*************************************************************************** + + mig_7series_v4_2_col_mach # + ( + // Parameters + .TCQ (TCQ), + .BANK_WIDTH (BANK_WIDTH), + .BURST_MODE (BURST_MODE), + .COL_WIDTH (COL_WIDTH), + .CS_WIDTH (CS_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), + .DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), + .ECC (ECC), + .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + .nPHY_WRLAT (nPHY_WRLAT), + .RANK_WIDTH (RANK_WIDTH), + .ROW_WIDTH (ROW_WIDTH) + ) + col_mach0 + ( + // Outputs + .mc_wrdata_en (mc_wrdata_en_ns), + .dq_busy_data (dq_busy_data), + .ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]), + .ecc_status_valid (ecc_status_valid), + .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .rd_data_en (rd_data_en), + .rd_data_end (rd_data_end), + .rd_data_offset (rd_data_offset), + .rd_rmw (rd_rmw), + .wr_data_addr (wr_data_addr_ns), + .wr_data_en (wr_data_en_ns), + .wr_data_offset (wr_data_offset_ns), + .wr_ecc_buf (wr_ecc_buf), + .col_read_fifo_empty (col_read_fifo_empty), + // Inputs + .clk (clk), + .rst (rst), + .col_a (col_a[ROW_WIDTH-1:0]), + .col_ba (col_ba[BANK_WIDTH-1:0]), + .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .col_periodic_rd (col_periodic_rd), + .col_ra (col_ra[RANK_WIDTH-1:0]), + .col_rmw (col_rmw), + .col_rd_wr (col_rd_wr), + .col_row (col_row[ROW_WIDTH-1:0]), + .col_size (col_size), + .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), + .phy_rddata_valid (phy_rddata_valid), + .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col) + ); + + //*************************************************************************** + // Implement ECC + //*************************************************************************** + + // Total ECC word length = ECC code width + Data width + localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH; + + generate + + if (ECC == "OFF") begin : ecc_off + + assign rd_data = phy_rd_data; + assign mc_wrdata = wr_data; + assign mc_wrdata_mask = wr_data_mask; + assign ecc_single = 4'b0; + assign ecc_multiple = 4'b0; + + end + + else begin : ecc_on + + wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; + wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i; + + + // Merge and encode + mig_7series_v4_2_ecc_merge_enc # + ( + // Parameters + .TCQ (TCQ), + .CODE_WIDTH (CODE_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .ECC_WIDTH (ECC_WIDTH), + .PAYLOAD_WIDTH (PAYLOAD_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK) + ) + ecc_merge_enc0 + ( + // Outputs + .mc_wrdata (mc_wrdata_i), + .mc_wrdata_mask (mc_wrdata_mask), + // Inputs + .clk (clk), + .rst (rst), + .h_rows (h_rows), + .rd_merge_data (rd_merge_data), + .raw_not_ecc (raw_not_ecc), + .wr_data (wr_data), + .wr_data_mask (wr_data_mask) + ); + + // Decode and fix + mig_7series_v4_2_ecc_dec_fix # + ( + // Parameters + .TCQ (TCQ), + .CODE_WIDTH (CODE_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .ECC_WIDTH (ECC_WIDTH), + .PAYLOAD_WIDTH (PAYLOAD_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK) + ) + ecc_dec_fix0 + ( + // Outputs + .ecc_multiple (ecc_multiple), + .ecc_single (ecc_single), + .rd_data (rd_data), + // Inputs + .clk (clk), + .rst (rst), + .correct_en (correct_en), + .phy_rddata (phy_rd_data), + .ecc_status_valid (ecc_status_valid), + .h_rows (h_rows) + ); + + // ECC Buffer + mig_7series_v4_2_ecc_buf # + ( + // Parameters + .TCQ (TCQ), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .PAYLOAD_WIDTH (PAYLOAD_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK) + ) + ecc_buf0 + ( + // Outputs + .rd_merge_data (rd_merge_data), + // Inputs + .clk (clk), + .rst (rst), + .rd_data (rd_data), + .rd_data_addr (rd_data_addr), + .rd_data_offset (rd_data_offset), + .wr_data_addr (wr_data_addr), + .wr_data_offset (wr_data_offset), + .wr_ecc_buf (wr_ecc_buf) + ); + + // Generate ECC table + mig_7series_v4_2_ecc_gen # + ( + // Parameters + .CODE_WIDTH (CODE_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .ECC_WIDTH (ECC_WIDTH) + ) + ecc_gen0 + ( + // Outputs + .h_rows (h_rows) + ); + + + + if (ECC == "ON") begin : gen_fi_xor_inst + reg mc_wrdata_en_r; + wire mc_wrdata_en_i; + + always @(posedge clk) begin + mc_wrdata_en_r <= mc_wrdata_en; + end + + assign mc_wrdata_en_i = mc_wrdata_en_r; + + mig_7series_v4_2_fi_xor #( + .DQ_WIDTH (DQ_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK) + ) + fi_xor0 + ( + .clk (clk), + .wrdata_in (mc_wrdata_i), + .wrdata_out (mc_wrdata), + .wrdata_en (mc_wrdata_en_i), + .fi_xor_we (fi_xor_we), + .fi_xor_wrdata (fi_xor_wrdata) + ); + end + else begin : gen_wrdata_passthru + assign mc_wrdata = mc_wrdata_i; + end + + + `ifdef DISPLAY_H_MATRIX + + integer i; + + always @(negedge rst) begin + + $display ("**********************************************"); + $display ("H Matrix:"); + + for (i=0; iout delay (sim only) + parameter BURST_MODE = "8", // Burst length + parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay + parameter CL = 5, // Read CAS latency + parameter CWL = 5, // Write CAS latency + parameter ID = 0, // Unique ID for each instance + parameter nBANK_MACHS = 4, // # bank machines in MC + parameter nCK_PER_CLK = 2, // DRAM clock : MC clock + parameter nFAW = 30, // four activate window (CKs) + parameter nREFRESH_BANK = 8, // # REF commands to pull-in + parameter nRRD = 4, // ACT->ACT period (CKs) + parameter nWTR = 4, // Internal write->read + // delay (CKs) + parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor + // for periodic read timer + parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a + // single bit rank signal among + // all the bank machines + parameter RANK_WIDTH = 2, // # of bits to count ranks + parameter RANKS = 4, // # of ranks of DRAM + parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor + // for refresh timer + ) + ( + + // Maintenance requests + + output periodic_rd_request, + output wire refresh_request, + + // Inhibit signals + + output reg inhbt_act_faw_r, + output reg inhbt_rd, + output reg inhbt_wr, + + // System Inputs + + input clk, + input rst, + + // User maintenance requests + + input app_periodic_rd_req, + input app_ref_req, + + // Inputs + + input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, + input clear_periodic_rd_request, + input col_rd_wr, + input init_calib_complete, + input insert_maint_r1, + input maint_prescaler_tick_r, + input [RANK_WIDTH-1:0] maint_rank_r, + input maint_zq_r, + input maint_sre_r, + input maint_srx_r, + input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, + input refresh_tick, + input [nBANK_MACHS-1:0] sending_col, + input [nBANK_MACHS-1:0] sending_row, + input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, + input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r + + ); + + //*************************************************************************** + // RRD configuration. The bank machines have a mechanism to prevent RAS to + // RAS on adjacent fabric CLK states to the same rank. When + // nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD + // when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the + // higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit + // is worked into the inhbt_faw signal. + //*************************************************************************** + + localparam nADD_RRD = nRRD - + ( + (nCK_PER_CLK == 1) ? 2 : + (nCK_PER_CLK == 2) ? 4 : + /*(nCK_PER_CLK == 4)*/ 8 + ); + + // divide by nCK_PER_CLK and add a cycle if there's a remainder + localparam nRRD_CLKS = + (nCK_PER_CLK == 1) ? nADD_RRD : + (nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) : + /*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0)); + + // take binary log to obtain counter width and add a tick for the idle cycle + localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1); + + //*************************************************************************** + // Internal signals + //*************************************************************************** + reg act_this_rank; + integer i; // loop invariant + + //*************************************************************************** + // Function clogb2 + // Description: + // This function performs binary logarithm and rounds up + // Inputs: + // size: integer to perform binary log upon + // Outputs: + // clogb2: result of binary logarithm, rounded up + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + + size = size - 1; + + // increment clogb2 from 1 for each bit in size + for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) + size = size >> 1; + + end + endfunction // clogb2 + + //*************************************************************************** + // Determine if this rank has been activated. act_this_rank_r is a + // registered bit vector from individual bank machines indicating the + // corresponding bank machine is sending + // an activate. Timing is improved with this method. + //*************************************************************************** + + always @(/*AS*/act_this_rank_r or sending_row) begin + + act_this_rank = 1'b0; + + for (i = 0; i < nBANK_MACHS; i = i + 1) + act_this_rank = + act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]); + + end + + + + reg add_rrd_inhbt = 1'b0; + generate + if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1 + reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; + reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; + always @(/*AS*/act_this_rank or add_rrd_r or rst) begin + add_rrd_ns = add_rrd_r; + if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; + else + if (act_this_rank) + add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; + else if (|add_rrd_r) add_rrd_ns = + add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1}; + end + always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; + always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; + end // add_rdd1 + else if (nADD_RRD > 0) begin :add_rdd0 + reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns; + reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r; + always @(/*AS*/act_this_rank or add_rrd_r or rst) begin + add_rrd_ns = add_rrd_r; + if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}}; + else + if (act_this_rank) + add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH]; + else if (|add_rrd_r) add_rrd_ns = + add_rrd_r - {1'b1}; + end + always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns; + always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns; + end // add_rdd0 + endgenerate + + +// Compute inhbt_act_faw_r. Only allow a limited number of activates +// in a window. Both the number of activates and the window are +// configurable. This depends on the RRD mechanism to prevent +// two consecutive activates to the same rank. +// +// Subtract three from the specified nFAW. Subtract three because: +// -Zero for the delay into the SRL is really one state. +// -Sending_row is used to trigger the delay. Sending_row is one +// state delayed from the arb. +// -inhbt_act_faw_r is registered to make timing work, hence the +// generation needs to be one state early. + + localparam nFAW_CLKS = (nCK_PER_CLK == 1) + ? nFAW + : (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) : + ((nFAW/4) + ((nFAW%4) ? 1 : 0)); + + generate + begin : inhbt_act_faw + wire act_delayed; + wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3; + + SRLC32E #(.INIT(32'h00000000) ) SRLC32E0 + (.Q(act_delayed), // SRL data output + .Q31(), // SRL cascade output pin + .A(shift_depth), // 5-bit shift depth select input + .CE(1'b1), // Clock enable input + .CLK(clk), // Clock input + .D(act_this_rank) // SRL data input + ); + + reg [2:0] faw_cnt_ns; + reg [2:0] faw_cnt_r; + reg inhbt_act_faw_ns; + always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt + or faw_cnt_r or rst) begin + if (rst) faw_cnt_ns = 3'b0; + else begin + faw_cnt_ns = faw_cnt_r; + if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1; + if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1; + end + inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt; + end + always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns; + always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns; + end // block: inhbt_act_faw + endgenerate + + +// In the DRAM spec, tWTR starts from CK following the end of the data +// burst. Since we don't directly have that spec, the wtr timer is +// based on when the CAS write command is sent to the DRAM. +// +// To compute the wtr timer value, first compute the time from the write command +// to the read command. This is CWL + data_time + nWTR. +// +// Two is subtracted from the required wtr time since the timer +// starts two states after the arbitration cycle. + + localparam ONE = 1; + localparam TWO = 2; + + localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR; + localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1) + ? CASWR2CASRD : + (nCK_PER_CLK == 2) + ? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) : + ((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0)); + localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS); + + generate + begin : wtr_timer + + reg write_this_rank; + always @(/*AS*/sending_col or wr_this_rank_r) begin + write_this_rank = 1'b0; + for (i = 0; i < nBANK_MACHS; i = i + 1) + write_this_rank = + write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]); + end + + reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r; + reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns; + + always @(/*AS*/rst or write_this_rank or wtr_cnt_r) + if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}}; + else begin + wtr_cnt_ns = wtr_cnt_r; + if (write_this_rank) wtr_cnt_ns = + CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0]; + else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0]; + end + + wire inhbt_rd_ns = |wtr_cnt_ns; + + always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns; + always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns; + + end + endgenerate + +// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to +// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the +// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap +// between them. Here, we allow the user to tune this fixed term via the +// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating +// this to the rank_common module, since this is a DQ/DQS bus-level requirement, +// not a per-rank requirement. + + localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL; + localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1) + ? CASRD2CASWR : + (nCK_PER_CLK == 2) + ? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) : + ((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0)); + localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS); + + generate + begin : rtw_timer + + reg read_this_rank; + always @(/*AS*/sending_col or rd_this_rank_r) begin + read_this_rank = 1'b0; + for (i = 0; i < nBANK_MACHS; i = i + 1) + read_this_rank = + read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); + end + + reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r; + reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns; + + always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r) + if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}}; + else begin + rtw_cnt_ns = rtw_cnt_r; + if (col_rd_wr && |sending_col) rtw_cnt_ns = + CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0]; + else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0]; + end + + wire inhbt_wr_ns = |rtw_cnt_ns; + + always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns; + always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns; + + end + endgenerate + +// Refresh request generation. Implement a "refresh bank". Referred +// to as pullin-in refresh in the JEDEC spec. +// The refresh_rank_r counter increments when a refresh to this +// rank has been decoded. In the up direction, the count saturates +// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK +// is normally eight. The counter decrements with each refresh_tick, +// saturating at zero. A refresh will be requests when the rank is +// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r +// equals zero. + + localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1); + + + generate begin : refresh_generation + reg my_rank_busy; + always @(/*AS*/rank_busy_r) begin + my_rank_busy = 1'b0; + for (i=0; i < nBANK_MACHS; i=i+1) + my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID]; + end + + wire my_refresh = + insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r && + (maint_rank_r == ID[RANK_WIDTH-1:0]); + + reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r; + reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns; + always @(/*AS*/app_ref_req or init_calib_complete or my_refresh + or refresh_bank_r or refresh_tick) + if (~init_calib_complete) + if (REFRESH_TIMER_DIV == 0) + refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]; + else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}}; + else + case ({my_refresh, refresh_tick, app_ref_req}) + 3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r; + 3'b010, 3'b001, 3'b011 : refresh_bank_ns = + (|refresh_bank_r)? + refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]: + refresh_bank_r; + 3'b100 : refresh_bank_ns = + refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH]; + endcase // case ({my_refresh, refresh_tick}) + always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns; + + `ifdef MC_SVA + refresh_bank_overflow: assert property (@(posedge clk) + (rst || (refresh_bank_r <= nREFRESH_BANK))); + refresh_bank_underflow: assert property (@(posedge clk) + (rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick))); + refresh_hi_priority: cover property (@(posedge clk) + (rst && ~|refresh_bank_ns && (refresh_bank_r == + ONE[0+:REFRESH_BANK_WIDTH]))); + refresh_bank_full: cover property (@(posedge clk) + (rst && (refresh_bank_r == + nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]))); + `endif + + assign refresh_request = init_calib_complete && + (~|refresh_bank_r || + ((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy)); + + end + endgenerate + +// Periodic read request generation. + + localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1); + + + generate begin : periodic_rd_generation + if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads + reg read_this_rank; + always @(/*AS*/rd_this_rank_r or sending_col) begin + read_this_rank = 1'b0; + for (i = 0; i < nBANK_MACHS; i = i + 1) + read_this_rank = + read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]); + end + + reg read_this_rank_r; + reg read_this_rank_r1; + always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank; + always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r; + wire int_read_this_rank = read_this_rank && + (((nCK_PER_CLK == 4) && read_this_rank_r) || + ((nCK_PER_CLK != 4) && read_this_rank_r1)); + + reg periodic_rd_cntr1_ns; + reg periodic_rd_cntr1_r; + always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin + periodic_rd_cntr1_ns = periodic_rd_cntr1_r; + if (clear_periodic_rd_request) + periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1; + end + always @(posedge clk) begin + if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0; + else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns; + end + + reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r; + reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns; + wire periodic_rd_timer_one = maint_prescaler_tick_r && + (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]); + + always @(/*AS*/init_calib_complete or maint_prescaler_tick_r + or periodic_rd_timer_r or int_read_this_rank) begin + periodic_rd_timer_ns = periodic_rd_timer_r; + if (~init_calib_complete) + periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; + //periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}}; + else if (int_read_this_rank || periodic_rd_timer_one) + periodic_rd_timer_ns = + PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH]; + else if (|periodic_rd_timer_r && maint_prescaler_tick_r) + periodic_rd_timer_ns = + periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH]; + end + always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns; + + reg periodic_rd_request_r; + wire periodic_rd_request_ns = ~rst && + ((app_periodic_rd_req && init_calib_complete) || + ((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) || + // (~(read_this_rank || clear_periodic_rd_request) && + (~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) && + (periodic_rd_request_r || periodic_rd_timer_one))); + always @(posedge clk) periodic_rd_request_r <= + #TCQ periodic_rd_request_ns; + + `ifdef MC_SVA + read_clears_periodic_rd_request: cover property (@(posedge clk) + (rst && (periodic_rd_request_r && read_this_rank))); + `endif + + assign periodic_rd_request = init_calib_complete && periodic_rd_request_r; + end else + assign periodic_rd_request = 1'b0; //to disable periodic reads + + end + endgenerate + + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v new file mode 100644 index 0000000..097adad --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v @@ -0,0 +1,515 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : rank_common.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// Block for logic common to all rank machines. Contains +// a clock prescaler, and arbiters for refresh and periodic +// read functions. + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_rank_common # + ( + parameter TCQ = 100, + parameter DRAM_TYPE = "DDR3", + parameter MAINT_PRESCALER_DIV = 40, + parameter nBANK_MACHS = 4, + parameter nCKESR = 4, + parameter nCK_PER_CLK = 2, + parameter PERIODIC_RD_TIMER_DIV = 20, + parameter RANK_WIDTH = 2, + parameter RANKS = 4, + parameter REFRESH_TIMER_DIV = 39, + parameter ZQ_TIMER_DIV = 640000 + ) + (/*AUTOARG*/ + // Outputs + maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r, + maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r, + periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip, + // Inputs + clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req, + insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present, + periodic_rd_request, periodic_rd_ack_r + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + input clk; + input rst; + +// Maintenance and periodic read prescaler. Nominally 200 nS. + localparam ONE = 1; + localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1); + input init_calib_complete; + reg maint_prescaler_tick_r_lcl; + generate + begin : maint_prescaler + reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r; + reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns; + wire maint_prescaler_tick_ns = + (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]); + always @(/*AS*/init_calib_complete or maint_prescaler_r + or maint_prescaler_tick_ns) begin + maint_prescaler_ns = maint_prescaler_r; + if (~init_calib_complete || maint_prescaler_tick_ns) + maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0]; + else if (|maint_prescaler_r) + maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0]; + end + always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns; + + always @(posedge clk) maint_prescaler_tick_r_lcl <= + #TCQ maint_prescaler_tick_ns; + end + endgenerate + output wire maint_prescaler_tick_r; + assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl; + +// Refresh timebase. Nominically 7800 nS. + localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1); + wire refresh_tick_lcl; + generate + begin : refresh_timer + reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r; + reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns; + always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl + or refresh_tick_lcl or refresh_timer_r) begin + refresh_timer_ns = refresh_timer_r; + if (~init_calib_complete || refresh_tick_lcl) + refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0]; + else if (|refresh_timer_r && maint_prescaler_tick_r_lcl) + refresh_timer_ns = + refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0]; + end + always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns; + assign refresh_tick_lcl = (refresh_timer_r == + ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl; + end + endgenerate + output wire refresh_tick; + assign refresh_tick = refresh_tick_lcl; + +// ZQ timebase. Nominally 128 mS + localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1); + input app_zq_req; + input insert_maint_r1; + reg maint_zq_r_lcl; + reg zq_request = 1'b0; + generate + if (DRAM_TYPE == "DDR3") begin : zq_cntrl + reg zq_tick = 1'b0; + if (ZQ_TIMER_DIV !=0) begin : zq_timer + reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r; + reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns; + always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl + or zq_tick or zq_timer_r) begin + zq_timer_ns = zq_timer_r; + if (~init_calib_complete || zq_tick) + zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0]; + else if (|zq_timer_r && maint_prescaler_tick_r_lcl) + zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0]; + end + always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns; + always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r) + zq_tick = (zq_timer_r == + ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl); + end // zq_timer + +// ZQ request. Set request with timer tick, and when exiting PHY init. Never +// request if ZQ_TIMER_DIV == 0. + begin : zq_request_logic + wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl; + reg zq_request_r; + wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") && + ((~init_calib_complete && (ZQ_TIMER_DIV != 0)) || + (zq_request_r && ~zq_clears_zq_request) || + zq_tick || + (app_zq_req && init_calib_complete)); + always @(posedge clk) zq_request_r <= #TCQ zq_request_ns; + always @(/*AS*/init_calib_complete or zq_request_r) + zq_request = init_calib_complete && zq_request_r; + end // zq_request_logic + end + endgenerate + + // Self-refresh control + localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0); + localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1); + input app_sr_req; + reg maint_sre_r_lcl; + reg maint_srx_r_lcl; + reg sre_request = 1'b0; + wire inhbt_srx; + + generate begin : sr_cntrl + + // SRE request. Set request with user request. + begin : sre_request_logic + + reg sre_request_r; + wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl; + + wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request) + || (app_sr_req && init_calib_complete && ~maint_sre_r_lcl)); + + always @(posedge clk) sre_request_r <= #TCQ sre_request_ns; + + always @(init_calib_complete or sre_request_r) + sre_request = init_calib_complete && sre_request_r; + + end // sre_request_logic + + // CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR + begin : ckesr_timer + + reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}}; + reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}}; + + always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin + + ckesr_timer_ns = ckesr_timer_r; + + if (insert_maint_r1 && maint_sre_r_lcl) + ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0]; + else if(|ckesr_timer_r) + ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0]; + + end + + always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns; + + assign inhbt_srx = |ckesr_timer_r; + + end // ckesr_timer + + end + + endgenerate + +// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh +// DRAM maintenance operations and self-refresh have their own channel in the +// queue. There is also a single, very simple bank machine +// dedicated to these operations. Its assumed that the +// maintenance operations can be completed quickly enough +// to avoid any queuing. +// +// ZQ, refresh and self-refresh requests share a channel into controller. +// Self-refresh is appended to the uppermost bit of the request bus and ZQ is +// appended just below that. + + input[RANKS-1:0] refresh_request; + input maint_wip_r; + reg maint_req_r_lcl; + reg [RANK_WIDTH-1:0] maint_rank_r_lcl; + input [7:0] slot_0_present; + input [7:0] slot_1_present; + + generate + begin : maintenance_request + +// Maintenance request pipeline. + reg upd_last_master_r; + reg new_maint_rank_r; + wire maint_busy = upd_last_master_r || new_maint_rank_r || + maint_req_r_lcl || maint_wip_r; + wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]}; + //wire upd_last_master_ns = |maint_request && ~maint_busy; + wire upd_last_master_ns = |maint_request && ~maint_wip_r; + always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; + always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r; + always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r; + wire upd_last_master_pls = upd_last_master_r & (~new_maint_rank_r); + +// Arbitrate maintenance requests. + wire [RANKS+1:0] maint_grant_ns; + wire [RANKS+1:0] maint_grant_r; + mig_7series_v4_2_round_robin_arb # + (.WIDTH (RANKS+2)) + maint_arb0 + (.grant_ns (maint_grant_ns), + .grant_r (maint_grant_r), + .upd_last_master (upd_last_master_pls), + .current_master (maint_grant_r), + .req (maint_request), + .disable_grant (1'b0), + /*AUTOINST*/ + // Inputs + .clk (clk), + .rst (rst)); + +// Look at arbitration results. Decide if ZQ, refresh or self-refresh. +// If refresh select the maintenance rank from the winning rank controller. +// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to +// slots populated maint_rank_r is not used for comparisons in the queue for ZQ +// or self-refresh requests. The bank machine will enable CS for the number of +// states equal to the the number of occupied slots. This will produce a +// command to every occupied slot, but not in any particular order. + wire [7:0] present = slot_0_present | slot_1_present; + integer i; + reg [RANK_WIDTH-1:0] maint_rank_ns; + wire maint_zq_ns = ~rst && (upd_last_master_pls + ? maint_grant_r[RANKS] + : maint_zq_r_lcl); + wire maint_srx_ns = ~rst && (maint_sre_r_lcl + ? ~app_sr_req & ~inhbt_srx + : maint_srx_r_lcl && upd_last_master_pls + ? maint_grant_r[RANKS+1] + : maint_srx_r_lcl); + wire maint_sre_ns = ~rst && (upd_last_master_pls + ? maint_grant_r[RANKS+1] + : maint_sre_r_lcl && ~maint_srx_ns); + always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns + or maint_sre_ns or maint_srx_ns or present or rst + or upd_last_master_pls) begin + if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}}; + else begin + maint_rank_ns = maint_rank_r_lcl; + if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin + maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0]; + for (i=0; i<8; i=i+1) + if (~present[maint_rank_ns]) + maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0]; + end + else + if (upd_last_master_pls) + for (i=0; i1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + + localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS); + localparam RANK_WIDTH = clogb2(RANKS); + + localparam ECC_WIDTH = (ECC == "OFF")? + 0 : (DATA_WIDTH <= 4)? + 4 : (DATA_WIDTH <= 10)? + 5 : (DATA_WIDTH <= 26)? + 6 : (DATA_WIDTH <= 57)? + 7 : (DATA_WIDTH <= 120)? + 8 : (DATA_WIDTH <= 247)? + 9 : 10; + localparam DATA_BUF_OFFSET_WIDTH = 1; + localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH) + + BANK_WIDTH + ROW_WIDTH + COL_WIDTH + + DATA_BUF_OFFSET_WIDTH; + + localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH; + localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8; + localparam TEMP_MON_EN = (SIMULATION == "FALSE") ? "ON" : "OFF"; + // Enable or disable the temp monitor module + localparam tTEMPSAMPLE = 10000000; // sample every 10 us + localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock + `ifdef SKIP_CALIB + localparam SKIP_CALIB = "TRUE"; + `else + localparam SKIP_CALIB = "FALSE"; + `endif + + + localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK; + + + // Wire declarations + + wire [BM_CNT_WIDTH-1:0] bank_mach_next; + wire clk; + wire [1:0] clk_ref; + wire [1:0] iodelay_ctrl_rdy; + wire clk_ref_in; + wire sys_rst_o; + wire clk_div2; + wire rst_div2; + wire freq_refclk ; + wire mem_refclk ; + wire pll_lock ; + wire sync_pulse; + wire mmcm_ps_clk; + wire poc_sample_pd; + wire psen; + wire psincdec; + wire psdone; + wire iddr_rst; + wire ref_dll_lock; + wire rst_phaser_ref; + wire pll_locked; + + wire rst; + + wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err; + wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err; + wire ddr3_parity; + + + wire sys_clk_p; + wire sys_clk_n; + wire mmcm_clk; + wire clk_ref_p; + wire clk_ref_n; + wire [11:0] device_temp_s; + + // Debug port signals + wire dbg_idel_down_all; + wire dbg_idel_down_cpt; + wire dbg_idel_up_all; + wire dbg_idel_up_cpt; + wire dbg_sel_all_idel_cpt; + wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt; + wire dbg_sel_pi_incdec; + wire [DQS_CNT_WIDTH:0] dbg_byte_sel; + wire dbg_pi_f_inc; + wire dbg_pi_f_dec; + wire [5:0] dbg_pi_counter_read_val; + wire [8:0] dbg_po_counter_read_val; + + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt; + wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt; + wire [255:0] dbg_calib_top; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt; + wire [(6*RANKS)-1:0] dbg_rd_data_offset; + wire [255:0] dbg_phy_rdlvl; + wire [99:0] dbg_phy_wrcal; + wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt; + wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt; + wire [255:0] dbg_phy_wrlvl; + wire [255:0] dbg_phy_init; + wire [255:0] dbg_prbs_rdlvl; + wire [255:0] dbg_dqs_found_cal; + wire dbg_pi_phaselock_start; + wire dbg_pi_phaselocked_done; + wire dbg_pi_phaselock_err; + wire dbg_pi_dqsfound_start; + wire dbg_pi_dqsfound_done; + wire dbg_pi_dqsfound_err; + wire dbg_wrcal_start; + wire dbg_wrcal_done; + wire dbg_wrcal_err; + wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes; + wire [11:0] dbg_pi_phase_locked_phy4lanes; + wire dbg_oclkdelay_calib_start; + wire dbg_oclkdelay_calib_done; + wire [255:0] dbg_phy_oclkdelay_cal; + wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data; + wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect; + wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata; + wire dbg_rddata_valid; + wire [1:0] dbg_rdlvl_done; + wire [1:0] dbg_rdlvl_err; + wire [1:0] dbg_rdlvl_start; + wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt; + wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt; + wire [5:0] dbg_tap_cnt_during_wrlvl; + wire dbg_wl_edge_detect_valid; + wire dbg_wrlvl_done; + wire dbg_wrlvl_err; + wire dbg_wrlvl_start; + reg [63:0] dbg_rddata_r; + reg dbg_rddata_valid_r; + wire [53:0] ocal_tap_cnt; + wire [4:0] dbg_dqs; + wire [8:0] dbg_bit; + wire [8:0] rd_data_edge_detect_r; + wire [53:0] wl_po_fine_cnt; + wire [26:0] wl_po_coarse_cnt; + wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1; + wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2; + wire [5:0] dbg_data_offset; + wire [5:0] dbg_data_offset_1; + wire [5:0] dbg_data_offset_2; + + wire [390:0] ddr3_ila_wrpath_int; + wire [1023:0] ddr3_ila_rdpath_int; + wire [119:0] ddr3_ila_basic_int; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int; + + +//*************************************************************************** + + + + assign ui_clk = clk; + assign ui_clk_sync_rst = rst; + + assign sys_clk_p = 1'b0; + assign sys_clk_n = 1'b0; + assign clk_ref_p = 1'b0; + assign clk_ref_n = 1'b0; + assign device_temp = device_temp_s; + + + generate + if (REFCLK_TYPE == "USE_SYSTEM_CLOCK") + assign clk_ref_in = mmcm_clk; + else + assign clk_ref_in = clk_ref_i; + endgenerate + + mig_7series_v4_2_iodelay_ctrl # + ( + .TCQ (TCQ), + .IODELAY_GRP0 (IODELAY_GRP0), + .IODELAY_GRP1 (IODELAY_GRP1), + .REFCLK_TYPE (REFCLK_TYPE), + .SYSCLK_TYPE (SYSCLK_TYPE), + .SYS_RST_PORT (SYS_RST_PORT), + .RST_ACT_LOW (RST_ACT_LOW), + .DIFF_TERM_REFCLK (DIFF_TERM_REFCLK), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL) + ) + u_iodelay_ctrl + ( + // Outputs + .iodelay_ctrl_rdy (iodelay_ctrl_rdy), + .sys_rst_o (sys_rst_o), + .clk_ref (clk_ref), + // Inputs + .clk_ref_p (clk_ref_p), + .clk_ref_n (clk_ref_n), + .clk_ref_i (clk_ref_in), + .sys_rst (sys_rst) + ); + mig_7series_v4_2_clk_ibuf # + ( + .SYSCLK_TYPE (SYSCLK_TYPE), + .DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK) + ) + u_ddr3_clk_ibuf + ( + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .sys_clk_i (sys_clk_i), + .mmcm_clk (mmcm_clk) + ); + // Temperature monitoring logic + + generate + if (TEMP_MON_EN == "ON") begin: temp_mon_enabled + + mig_7series_v4_2_tempmon # + ( + .TCQ (TCQ), + .TEMP_MON_CONTROL (TEMP_MON_CONTROL), + .XADC_CLK_PERIOD (XADC_CLK_PERIOD), + .tTEMPSAMPLE (tTEMPSAMPLE) + ) + u_tempmon + ( + .clk (clk), + .xadc_clk (clk_ref[0]), + .rst (rst), + .device_temp_i (device_temp_i), + .device_temp (device_temp_s) + ); + end else begin: temp_mon_disabled + + assign device_temp_s = 'b0; + + end + endgenerate + + mig_7series_v4_2_infrastructure # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLKIN_PERIOD (CLKIN_PERIOD), + .SYSCLK_TYPE (SYSCLK_TYPE), + .CLKFBOUT_MULT (CLKFBOUT_MULT), + .DIVCLK_DIVIDE (DIVCLK_DIVIDE), + .CLKOUT0_PHASE (CLKOUT0_PHASE), + .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), + .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), + .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), + .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), + .MMCM_VCO (MMCM_VCO), + .MMCM_MULT_F (MMCM_MULT_F), + .MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), + .RST_ACT_LOW (RST_ACT_LOW), + .tCK (tCK), + .MEM_TYPE (DRAM_TYPE) + ) + u_ddr3_infrastructure + ( + // Outputs + .rstdiv0 (rst), + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .mem_refclk (mem_refclk), + .freq_refclk (freq_refclk), + .sync_pulse (sync_pulse), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .iddr_rst (iddr_rst), +// .auxout_clk (), + .ui_addn_clk_0 (), + .ui_addn_clk_1 (), + .ui_addn_clk_2 (), + .ui_addn_clk_3 (), + .ui_addn_clk_4 (), + .pll_locked (pll_locked), + .mmcm_locked (), + .rst_phaser_ref (rst_phaser_ref), + // Inputs + .psen (psen), + .psincdec (psincdec), + .mmcm_clk (mmcm_clk), + .sys_rst (sys_rst_o), + .iodelay_ctrl_rdy (iodelay_ctrl_rdy), + .ref_dll_lock (ref_dll_lock) + ); + + + mig_7series_v4_2_memc_ui_top_std # + ( + .TCQ (TCQ), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .AL (AL), + .PAYLOAD_WIDTH (PAYLOAD_WIDTH), + .BANK_WIDTH (BANK_WIDTH), + .BM_CNT_WIDTH (BM_CNT_WIDTH), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .CA_MIRROR (CA_MIRROR), + .DDR3_VDD_OP_VOLT (VDD_OP_VOLT), + .CK_WIDTH (CK_WIDTH), + .COL_WIDTH (COL_WIDTH), + .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1), + .CS_WIDTH (CS_WIDTH), + .nCS_PER_RANK (nCS_PER_RANK), + .CKE_WIDTH (CKE_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DM_WIDTH (DM_WIDTH), + .DQ_CNT_WIDTH (DQ_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .DRAM_WIDTH (DRAM_WIDTH), + .ECC (ECC), + .ECC_WIDTH (ECC_WIDTH), + .ECC_TEST (ECC_TEST), + .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), + .REFCLK_FREQ (REFCLK_FREQ), + .nAL (nAL), + .nBANK_MACHS (nBANK_MACHS), + .CKE_ODT_AUX (CKE_ODT_AUX), + .nCK_PER_CLK (nCK_PER_CLK), + .ORDERING (ORDERING), + .OUTPUT_DRV (OUTPUT_DRV), + .IBUF_LPWR_MODE (IBUF_LPWR_MODE), + .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN), + .BANK_TYPE (BANK_TYPE), + .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), + .IODELAY_GRP0 (IODELAY_GRP0), + .IODELAY_GRP1 (IODELAY_GRP1), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .REG_CTRL (REG_CTRL), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .CL (CL), + .CWL (CWL), + .tCK (tCK), + .tCKE (tCKE), + .tFAW (tFAW), + .tPRDI (tPRDI), + .tRAS (tRAS), + .tRCD (tRCD), + .tREFI (tREFI), + .tRFC (tRFC), + .tRP (tRP), + .tRRD (tRRD), + .tRTP (tRTP), + .tWTR (tWTR), + .tZQI (tZQI), + .tZQCS (tZQCS), + .USER_REFRESH (USER_REFRESH), + .TEMP_MON_EN (TEMP_MON_EN), + .WRLVL (WRLVL), + .DEBUG_PORT (DEBUG_PORT), + .CAL_WIDTH (CAL_WIDTH), + .RANK_WIDTH (RANK_WIDTH), + .RANKS (RANKS), + .ODT_WIDTH (ODT_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .APP_DATA_WIDTH (APP_DATA_WIDTH), + .APP_MASK_WIDTH (APP_MASK_WIDTH), + .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .CK_BYTE_MAP (CK_BYTE_MAP), + .ADDR_MAP (ADDR_MAP), + .BANK_MAP (BANK_MAP), + .CAS_MAP (CAS_MAP), + .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), + .CKE_MAP (CKE_MAP), + .ODT_MAP (ODT_MAP), + .CS_MAP (CS_MAP), + .PARITY_MAP (PARITY_MAP), + .RAS_MAP (RAS_MAP), + .WE_MAP (WE_MAP), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .DATA0_MAP (DATA0_MAP), + .DATA1_MAP (DATA1_MAP), + .DATA2_MAP (DATA2_MAP), + .DATA3_MAP (DATA3_MAP), + .DATA4_MAP (DATA4_MAP), + .DATA5_MAP (DATA5_MAP), + .DATA6_MAP (DATA6_MAP), + .DATA7_MAP (DATA7_MAP), + .DATA8_MAP (DATA8_MAP), + .DATA9_MAP (DATA9_MAP), + .DATA10_MAP (DATA10_MAP), + .DATA11_MAP (DATA11_MAP), + .DATA12_MAP (DATA12_MAP), + .DATA13_MAP (DATA13_MAP), + .DATA14_MAP (DATA14_MAP), + .DATA15_MAP (DATA15_MAP), + .DATA16_MAP (DATA16_MAP), + .DATA17_MAP (DATA17_MAP), + .MASK0_MAP (MASK0_MAP), + .MASK1_MAP (MASK1_MAP), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .IDELAY_ADJ (IDELAY_ADJ), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ), + .SLOT_0_CONFIG (SLOT_0_CONFIG), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .MEM_ADDR_ORDER (MEM_ADDR_ORDER), + .STARVE_LIMIT (STARVE_LIMIT), + .USE_CS_PORT (USE_CS_PORT), + .USE_DM_PORT (USE_DM_PORT), + .USE_ODT_PORT (USE_ODT_PORT), + .MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK), + .TAPSPERKCLK (TAPSPERKCLK), + .SKIP_CALIB (SKIP_CALIB), + .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) + ) + u_memc_ui_top_std + ( + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .clk_ref (clk_ref), + .mem_refclk (mem_refclk), //memory clock + .freq_refclk (freq_refclk), + .pll_lock (pll_locked), + .sync_pulse (sync_pulse), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .iddr_rst (iddr_rst), + .psen (psen), + .psincdec (psincdec), + .rst (rst), + .rst_phaser_ref (rst_phaser_ref), + .ref_dll_lock (ref_dll_lock), + +// Memory interface ports + .ddr_dq (ddr3_dq), + .ddr_dqs_n (ddr3_dqs_n), + .ddr_dqs (ddr3_dqs_p), + .ddr_addr (ddr3_addr), + .ddr_ba (ddr3_ba), + .ddr_cas_n (ddr3_cas_n), + .ddr_ck_n (ddr3_ck_n), + .ddr_ck (ddr3_ck_p), + .ddr_cke (ddr3_cke), + .ddr_cs_n (), + .ddr_dm (ddr3_dm), + .ddr_odt (ddr3_odt), + .ddr_ras_n (ddr3_ras_n), + .ddr_reset_n (ddr3_reset_n), + .ddr_parity (ddr3_parity), + .ddr_we_n (ddr3_we_n), + .bank_mach_next (bank_mach_next), + +// Application interface ports + .app_addr (app_addr), + .app_cmd (app_cmd), + .app_en (app_en), + .app_hi_pri (1'b0), + .app_wdf_data (app_wdf_data), + .app_wdf_end (app_wdf_end), + .app_wdf_mask (app_wdf_mask), + .app_wdf_wren (app_wdf_wren), + .app_ecc_multiple_err (app_ecc_multiple_err), + .app_ecc_single_err (app_ecc_single_err), + .app_rd_data (app_rd_data), + .app_rd_data_end (app_rd_data_end), + .app_rd_data_valid (app_rd_data_valid), + .app_rdy (app_rdy), + .app_wdf_rdy (app_wdf_rdy), + .app_sr_req (app_sr_req), + .app_sr_active (app_sr_active), + .app_ref_req (app_ref_req), + .app_ref_ack (app_ref_ack), + .app_zq_req (app_zq_req), + .app_zq_ack (app_zq_ack), + .app_raw_not_ecc ({2*nCK_PER_CLK{1'b0}}), + .app_correct_en_i (1'b1), + + .device_temp (device_temp_s), + + // skip calibration ports + `ifdef SKIP_CALIB + .calib_tap_req (calib_tap_req), + .calib_tap_load (calib_tap_load), + .calib_tap_addr (calib_tap_addr), + .calib_tap_val (calib_tap_val), + .calib_tap_load_done (calib_tap_load_done), + `else + .calib_tap_req (), + .calib_tap_load (1'b0), + .calib_tap_addr (7'b0), + .calib_tap_val (8'b0), + .calib_tap_load_done (1'b0), + `endif + +// Debug logic ports + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), + .dbg_sel_pi_incdec (dbg_sel_pi_incdec), + .dbg_sel_po_incdec (dbg_sel_po_incdec), + .dbg_byte_sel (dbg_byte_sel), + .dbg_pi_f_inc (dbg_pi_f_inc), + .dbg_pi_f_dec (dbg_pi_f_dec), + .dbg_po_f_inc (dbg_po_f_inc), + .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), + .dbg_po_f_dec (dbg_po_f_dec), + .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), + .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), + .dbg_calib_top (dbg_calib_top), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_rd_data_offset (dbg_rd_data_offset), + .dbg_phy_rdlvl (dbg_phy_rdlvl), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_rddata (dbg_rddata), + .dbg_rddata_valid (dbg_rddata_valid), + .dbg_rdlvl_done (dbg_rdlvl_done), + .dbg_rdlvl_err (dbg_rdlvl_err), + .dbg_rdlvl_start (dbg_rdlvl_start), + .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), + .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), + .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_wrlvl_done (dbg_wrlvl_done), + .dbg_wrlvl_err (dbg_wrlvl_err), + .dbg_wrlvl_start (dbg_wrlvl_start), + .dbg_phy_wrlvl (dbg_phy_wrlvl), + .dbg_phy_init (dbg_phy_init), + .dbg_prbs_rdlvl (dbg_prbs_rdlvl), + .dbg_pi_counter_read_val (dbg_pi_counter_read_val), + .dbg_po_counter_read_val (dbg_po_counter_read_val), + .dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int), + .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int), + .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int), + .dbg_pi_phaselock_start (dbg_pi_phaselock_start), + .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done), + .dbg_pi_phaselock_err (dbg_pi_phaselock_err), + .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), + .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), + .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), + .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err), + .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1), + .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2), + .dbg_data_offset (dbg_data_offset), + .dbg_data_offset_1 (dbg_data_offset_1), + .dbg_data_offset_2 (dbg_data_offset_2), + .dbg_wrcal_start (dbg_wrcal_start), + .dbg_wrcal_done (dbg_wrcal_done), + .dbg_wrcal_err (dbg_wrcal_err), + .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), + .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), + .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), + .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), + .dbg_dqs_found_cal (dbg_dqs_found_cal), + .init_calib_complete (init_calib_complete), + .dbg_poc () + ); + + + + + + + //********************************************************************* + // Resetting all RTL debug inputs as the debug ports are not enabled + //********************************************************************* + assign dbg_idel_down_all = 1'b0; + assign dbg_idel_down_cpt = 1'b0; + assign dbg_idel_up_all = 1'b0; + assign dbg_idel_up_cpt = 1'b0; + assign dbg_sel_all_idel_cpt = 1'b0; + assign dbg_sel_idel_cpt = 'b0; + assign dbg_byte_sel = 'd0; + assign dbg_sel_pi_incdec = 1'b0; + assign dbg_pi_f_inc = 1'b0; + assign dbg_pi_f_dec = 1'b0; + assign dbg_po_f_inc = 'b0; + assign dbg_po_f_dec = 'b0; + assign dbg_po_f_stg23_sel = 'b0; + assign dbg_sel_po_incdec = 'b0; + + + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v new file mode 100644 index 0000000..ad125c9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ddr3_mig_sim.v @@ -0,0 +1,1188 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.2 +// \ \ Application : MIG +// / / Filename : ddr3_mig.v +// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ +// \ \ / \ Date Created : Tue Sept 21 2010 +// \___\/\___\ +// +// Device : 7 Series +// Design Name : DDR3 SDRAM +// Purpose : +// Top-level module. This module can be instantiated in the +// system and interconnect as shown in user design wrapper file (user top module). +// In addition to the memory controller, the module instantiates: +// 1. Clock generation/distribution, reset logic +// 2. IDELAY control block +// 3. Debug logic +// Reference : +// Revision History : +//***************************************************************************** + +//`define SKIP_CALIB +`timescale 1ps/1ps + +module ddr3_mig # + ( + + //*************************************************************************** + // The following parameters refer to width of various ports + //*************************************************************************** + parameter BANK_WIDTH = 3, + // # of memory Bank Address bits. + parameter CK_WIDTH = 1, + // # of CK/CK# outputs to memory. + parameter COL_WIDTH = 10, + // # of memory Column Address bits. + parameter CS_WIDTH = 1, + // # of unique CS outputs to memory. + parameter nCS_PER_RANK = 1, + // # of unique CS outputs per rank for phy + parameter CKE_WIDTH = 1, + // # of CKE outputs to memory. + parameter DATA_BUF_ADDR_WIDTH = 5, + parameter DQ_CNT_WIDTH = 4, + // = ceil(log2(DQ_WIDTH)) + parameter DQ_PER_DM = 8, + parameter DM_WIDTH = 2, + // # of DM (data mask) + parameter DQ_WIDTH = 16, + // # of DQ (data) + parameter DQS_WIDTH = 2, + parameter DQS_CNT_WIDTH = 1, + // = ceil(log2(DQS_WIDTH)) + parameter DRAM_WIDTH = 8, + // # of DQ per DQS + parameter ECC = "OFF", + parameter DATA_WIDTH = 16, + parameter ECC_TEST = "OFF", + parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH, + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN", + //Possible Parameters + //1.BANK_ROW_COLUMN : Address mapping is + // in form of Bank Row Column. + //2.ROW_BANK_COLUMN : Address mapping is + // in the form of Row Bank Column. + //3.TG_TEST : Scrambles Address bits + // for distributed Addressing. + + //parameter nBANK_MACHS = 4, + parameter nBANK_MACHS = 4, + parameter RANKS = 1, + // # of Ranks. + parameter ODT_WIDTH = 1, + // # of ODT outputs to memory. + parameter ROW_WIDTH = 15, + // # of memory Row Address bits. + parameter ADDR_WIDTH = 29, + // # = RANK_WIDTH + BANK_WIDTH + // + ROW_WIDTH + COL_WIDTH; + // Chip Select is always tied to low for + // single rank devices + parameter USE_CS_PORT = 0, + // # = 1, When Chip Select (CS#) output is enabled + // = 0, When Chip Select (CS#) output is disabled + // If CS_N disabled, user must connect + // DRAM CS_N input(s) to ground + parameter USE_DM_PORT = 1, + // # = 1, When Data Mask option is enabled + // = 0, When Data Mask option is disbaled + // When Data Mask option is disabled in + // MIG Controller Options page, the logic + // related to Data Mask should not get + // synthesized + parameter USE_ODT_PORT = 1, + // # = 1, When ODT output is enabled + // = 0, When ODT output is disabled + // Parameter configuration for Dynamic ODT support: + // USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120". + // This configuration allows to save ODT pin mapping from FPGA. + // The user can tie the ODT input of DRAM to HIGH. + parameter IS_CLK_SHARED = "FALSE", + // # = "true" when clock is shared + // = "false" when clock is not shared + + parameter PHY_CONTROL_MASTER_BANK = 0, + // The bank index where master PHY_CONTROL resides, + // equal to the PLL residing bank + parameter MEM_DENSITY = "4Gb", + // Indicates the density of the Memory part + // Added for the sake of Vivado simulations + parameter MEM_SPEEDGRADE = "125", + // Indicates the Speed grade of Memory Part + // Added for the sake of Vivado simulations + parameter MEM_DEVICE_WIDTH = 16, + // Indicates the device width of the Memory Part + // Added for the sake of Vivado simulations + + //*************************************************************************** + // The following parameters are mode register settings + //*************************************************************************** + parameter AL = "0", + // DDR3 SDRAM: + // Additive Latency (Mode Register 1). + // # = "0", "CL-1", "CL-2". + // DDR2 SDRAM: + // Additive Latency (Extended Mode Register). + parameter nAL = 0, + // # Additive Latency in number of clock + // cycles. + parameter BURST_MODE = "8", + // DDR3 SDRAM: + // Burst Length (Mode Register 0). + // # = "8", "4", "OTF". + // DDR2 SDRAM: + // Burst Length (Mode Register). + // # = "8", "4". + parameter BURST_TYPE = "SEQ", + // DDR3 SDRAM: Burst Type (Mode Register 0). + // DDR2 SDRAM: Burst Type (Mode Register). + // # = "SEQ" - (Sequential), + // = "INT" - (Interleaved). + parameter CL = 5, + // in number of clock cycles + // DDR3 SDRAM: CAS Latency (Mode Register 0). + // DDR2 SDRAM: CAS Latency (Mode Register). + parameter CWL = 5, + // in number of clock cycles + // DDR3 SDRAM: CAS Write Latency (Mode Register 2). + // DDR2 SDRAM: Can be ignored + parameter OUTPUT_DRV = "HIGH", + // Output Driver Impedance Control (Mode Register 1). + // # = "HIGH" - RZQ/7, + // = "LOW" - RZQ/6. + parameter RTT_NOM = "60", + // RTT_NOM (ODT) (Mode Register 1). + // = "120" - RZQ/2, + // = "60" - RZQ/4, + // = "40" - RZQ/6. + parameter RTT_WR = "OFF", + // RTT_WR (ODT) (Mode Register 2). + // # = "OFF" - Dynamic ODT off, + // = "120" - RZQ/2, + // = "60" - RZQ/4, + parameter ADDR_CMD_MODE = "1T" , + // # = "1T", "2T". + parameter REG_CTRL = "OFF", + // # = "ON" - RDIMMs, + // = "OFF" - Components, SODIMMs, UDIMMs. + parameter CA_MIRROR = "OFF", + // C/A mirror opt for DDR3 dual rank + + parameter VDD_OP_VOLT = "150", + // # = "150" - 1.5V Vdd Memory part + // = "135" - 1.35V Vdd Memory part + + + //*************************************************************************** + // The following parameters are multiplier and divisor factors for PLLE2. + // Based on the selected design frequency these parameters vary. + //*************************************************************************** + parameter CLKIN_PERIOD = 3000, + // Input Clock Period + parameter CLKFBOUT_MULT = 4, + // write PLL VCO multiplier + parameter DIVCLK_DIVIDE = 1, + // write PLL VCO divisor + parameter CLKOUT0_PHASE = 0.0, + // Phase for PLL output clock (CLKOUT0) + parameter CLKOUT0_DIVIDE = 2, + // VCO output divisor for PLL output clock (CLKOUT0) + parameter CLKOUT1_DIVIDE = 4, + // VCO output divisor for PLL output clock (CLKOUT1) + parameter CLKOUT2_DIVIDE = 64, + // VCO output divisor for PLL output clock (CLKOUT2) + parameter CLKOUT3_DIVIDE = 16, + // VCO output divisor for PLL output clock (CLKOUT3) + parameter MMCM_VCO = 666, + // Max Freq (MHz) of MMCM VCO + parameter MMCM_MULT_F = 8, + // write MMCM VCO multiplier + parameter MMCM_DIVCLK_DIVIDE = 1, + // write MMCM VCO divisor + + //*************************************************************************** + // Memory Timing Parameters. These parameters varies based on the selected + // memory part. + //*************************************************************************** + parameter tCKE = 5000, + // memory tCKE paramter in pS + parameter tFAW = 40000, + // memory tRAW paramter in pS. + parameter tPRDI = 1_000_000, + // memory tPRDI paramter in pS. + parameter tRAS = 35000, + // memory tRAS paramter in pS. + parameter tRCD = 13750, + // memory tRCD paramter in pS. + parameter tREFI = 7800000, + // memory tREFI paramter in pS. + parameter tRFC = 260000, + // memory tRFC paramter in pS. + parameter tRP = 13750, + // memory tRP paramter in pS. + parameter tRRD = 7500, + // memory tRRD paramter in pS. + parameter tRTP = 7500, + // memory tRTP paramter in pS. + parameter tWTR = 7500, + // memory tWTR paramter in pS. + parameter tZQI = 128_000_000, + // memory tZQI paramter in nS. + parameter tZQCS = 64,//64, + // memory tZQCS paramter in clock cycles. + + //*************************************************************************** + // Simulation parameters + //*************************************************************************** + parameter SIM_BYPASS_INIT_CAL = "FAST", + // # = "OFF" - Complete memory init & + // calibration sequence + // # = "SKIP" - Not supported + // # = "FAST" - Complete memory init & use + // abbreviated calib sequence + + parameter SIMULATION = "TRUE", + // Should be TRUE during design simulations and + // FALSE during implementations + + //*************************************************************************** + // The following parameters varies based on the pin out entered in MIG GUI. + // Do not change any of these parameters directly by editing the RTL. + // Any changes required should be done through GUI and the design regenerated. + //*************************************************************************** + parameter BYTE_LANES_B0 = 4'b1111, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B1 = 4'b0000, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B2 = 4'b0000, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B3 = 4'b0000, + // Byte lanes used in an IO column. + parameter BYTE_LANES_B4 = 4'b0000, + // Byte lanes used in an IO column. + parameter DATA_CTL_B0 = 4'b1100, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B1 = 4'b0000, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B2 = 4'b0000, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B3 = 4'b0000, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter DATA_CTL_B4 = 4'b0000, + // Indicates Byte lane is data byte lane + // or control Byte lane. '1' in a bit + // position indicates a data byte lane and + // a '0' indicates a control byte lane + parameter PHY_0_BITLANES = 48'h3F7_3FE_FFF_BFF, + parameter PHY_1_BITLANES = 48'h000_000_000_000, + parameter PHY_2_BITLANES = 48'h000_000_000_000, + + // control/address/data pin mapping parameters + parameter CK_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter ADDR_MAP + = 192'h000_00B_009_002_000_011_005_007_004_003_014_006_010_008_001_015, + parameter BANK_MAP = 36'h013_01B_017, + parameter CAS_MAP = 12'h016, + parameter CKE_ODT_BYTE_MAP = 8'h00, + parameter CKE_MAP = 96'h000_000_000_000_000_000_000_01A, + parameter ODT_MAP = 96'h000_000_000_000_000_000_000_018, + parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, + parameter PARITY_MAP = 12'h000, + parameter RAS_MAP = 12'h012, + parameter WE_MAP = 12'h019, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_03_02, + parameter DATA0_MAP = 96'h025_027_029_023_028_026_021_022, + parameter DATA1_MAP = 96'h039_035_038_036_034_032_037_030, + parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, + parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_031_024, + parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, + + parameter SLOT_0_CONFIG = 8'b0000_0001, + // Mapping of Ranks. + parameter SLOT_1_CONFIG = 8'b0000_0000, + // Mapping of Ranks. + + //*************************************************************************** + // IODELAY and PHY related parameters + //*************************************************************************** + parameter IBUF_LPWR_MODE = "OFF", + // to phy_top + parameter DATA_IO_IDLE_PWRDWN = "ON", + // # = "ON", "OFF" + parameter BANK_TYPE = "HR_IO", + // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter DATA_IO_PRIM_TYPE = "HR_LP", + // # = "HP_LP", "HR_LP", "DEFAULT" + parameter CKE_ODT_AUX = "FALSE", + parameter USER_REFRESH = "OFF", + parameter WRLVL = "ON", + // # = "ON" - DDR3 SDRAM + // = "OFF" - DDR2 SDRAM. + parameter ORDERING = "NORM", + // # = "NORM", "STRICT", "RELAXED". + parameter CALIB_ROW_ADD = 16'h0000, + // Calibration row address will be used for + // calibration read and write operations + parameter CALIB_COL_ADD = 12'h000, + // Calibration column address will be used for + // calibration read and write operations + parameter CALIB_BA_ADD = 3'h0, + // Calibration bank address will be used for + // calibration read and write operations + parameter TCQ = 100, + parameter IDELAY_ADJ = "OFF", + parameter FINE_PER_BIT = "OFF", + parameter CENTER_COMP_MODE = "OFF", + parameter PI_VAL_ADJ = "OFF", + parameter IODELAY_GRP0 = "DDR3_IODELAY_MIG0", + // It is associated to a set of IODELAYs with + // an IDELAYCTRL that have same IODELAY CONTROLLER + // clock frequency (200MHz). + parameter IODELAY_GRP1 = "DDR3_IODELAY_MIG1", + // It is associated to a set of IODELAYs with + // an IDELAYCTRL that have same IODELAY CONTROLLER + // clock frequency (300MHz/400MHz). + parameter SYSCLK_TYPE = "NO_BUFFER", + // System clock type DIFFERENTIAL, SINGLE_ENDED, + // NO_BUFFER + parameter REFCLK_TYPE = "NO_BUFFER", + // Reference clock type DIFFERENTIAL, SINGLE_ENDED, + // NO_BUFFER, USE_SYSTEM_CLOCK + parameter SYS_RST_PORT = "FALSE", + // "TRUE" - if pin is selected for sys_rst + // and IBUF will be instantiated. + // "FALSE" - if pin is not selected for sys_rst + parameter FPGA_SPEED_GRADE = 2, + // FPGA speed grade + + parameter CMD_PIPE_PLUS1 = "ON", + // add pipeline stage between MC and PHY + parameter DRAM_TYPE = "DDR3", + parameter CAL_WIDTH = "HALF", + parameter STARVE_LIMIT = 2, + // # = 2,3,4. + parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE", + + + //*************************************************************************** + // Referece clock frequency parameters + //*************************************************************************** + parameter REFCLK_FREQ = 200.0, + // IODELAYCTRL reference clock frequency + parameter DIFF_TERM_REFCLK = "TRUE", + // Differential Termination for idelay + // reference clock input pins + //*************************************************************************** + // System clock frequency parameters + //*************************************************************************** + parameter tCK = 3000, + // memory tCK paramter. + // # = Clock Period in pS. + parameter nCK_PER_CLK = 4, + // # of memory CKs per fabric CLK + + parameter DIFF_TERM_SYSCLK = "TRUE", + // Differential Termination for System + // clock input pins + + + + + //*************************************************************************** + // Debug parameters + //*************************************************************************** + parameter DEBUG_PORT = "OFF", + // # = "ON" Enable debug signals/controls. + // = "OFF" Disable debug signals/controls. + + //*************************************************************************** + // Temparature monitor parameter + //*************************************************************************** + parameter TEMP_MON_CONTROL = "EXTERNAL", + // # = "INTERNAL", "EXTERNAL" + //*************************************************************************** + // FPGA Voltage Type parameter + //*************************************************************************** + parameter FPGA_VOLT_TYPE = "N", + // # = "L", "N". When FPGA VccINT is 0.9v, + // the value is "L", else it is "N" + + parameter RST_ACT_LOW = 1 + // =1 for active low reset, + // =0 for active high. + ) + ( + + // Inouts + inout [DQ_WIDTH-1:0] ddr3_dq, + inout [DQS_WIDTH-1:0] ddr3_dqs_n, + inout [DQS_WIDTH-1:0] ddr3_dqs_p, + + // Outputs + output [ROW_WIDTH-1:0] ddr3_addr, + output [BANK_WIDTH-1:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + output [CK_WIDTH-1:0] ddr3_ck_p, + output [CK_WIDTH-1:0] ddr3_ck_n, + output [CKE_WIDTH-1:0] ddr3_cke, + + + output [DM_WIDTH-1:0] ddr3_dm, + + output [ODT_WIDTH-1:0] ddr3_odt, + + + // Inputs + + // Single-ended system clock + input sys_clk_i, + + // Single-ended iodelayctrl clk (reference clock) + input clk_ref_i, + + // user interface signals + input [ADDR_WIDTH-1:0] app_addr, + input [2:0] app_cmd, + input app_en, + input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_wdf_data, + input app_wdf_end, + input [((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1:0] app_wdf_mask, + input app_wdf_wren, + output [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_rd_data, + output app_rd_data_end, + output app_rd_data_valid, + output app_rdy, + output app_wdf_rdy, + input app_sr_req, + input app_ref_req, + input app_zq_req, + output app_sr_active, + output app_ref_ack, + output app_zq_ack, + output ui_clk, + output ui_clk_sync_rst, + + + + + output init_calib_complete, + input [11:0] device_temp_i, + // The 12 MSB bits of the temperature sensor transfer + // function need to be connected to this port. This port + // will be synchronized w.r.t. to fabric clock internally. + output [11:0] device_temp, +`ifdef SKIP_CALIB + output calib_tap_req, + input calib_tap_load, + input [6:0] calib_tap_addr, + input [7:0] calib_tap_val, + input calib_tap_load_done, +`endif + + + // System reset - Default polarity of sys_rst pin is Active Low. + // System reset polarity will change based on the option + // selected in GUI. + input sys_rst + ); + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + + localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS); + localparam RANK_WIDTH = clogb2(RANKS); + + localparam ECC_WIDTH = (ECC == "OFF")? + 0 : (DATA_WIDTH <= 4)? + 4 : (DATA_WIDTH <= 10)? + 5 : (DATA_WIDTH <= 26)? + 6 : (DATA_WIDTH <= 57)? + 7 : (DATA_WIDTH <= 120)? + 8 : (DATA_WIDTH <= 247)? + 9 : 10; + localparam DATA_BUF_OFFSET_WIDTH = 1; + localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH) + + BANK_WIDTH + ROW_WIDTH + COL_WIDTH + + DATA_BUF_OFFSET_WIDTH; + + localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH; + localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8; + localparam TEMP_MON_EN = (SIMULATION == "TRUE") ? "ON" : "OFF"; + // Enable or disable the temp monitor module + localparam tTEMPSAMPLE = 10000000; // sample every 10 us + localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock + `ifdef SKIP_CALIB + localparam SKIP_CALIB = "TRUE"; + `else + localparam SKIP_CALIB = "FALSE"; + `endif + + + localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK; + + + // Wire declarations + + wire [BM_CNT_WIDTH-1:0] bank_mach_next; + wire clk; + wire [1:0] clk_ref; + wire [1:0] iodelay_ctrl_rdy; + wire clk_ref_in; + wire sys_rst_o; + wire clk_div2; + wire rst_div2; + wire freq_refclk ; + wire mem_refclk ; + wire pll_lock ; + wire sync_pulse; + wire mmcm_ps_clk; + wire poc_sample_pd; + wire psen; + wire psincdec; + wire psdone; + wire iddr_rst; + wire ref_dll_lock; + wire rst_phaser_ref; + wire pll_locked; + + wire rst; + + wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err; + wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err; + wire ddr3_parity; + + + wire sys_clk_p; + wire sys_clk_n; + wire mmcm_clk; + wire clk_ref_p; + wire clk_ref_n; + wire [11:0] device_temp_s; + + // Debug port signals + wire dbg_idel_down_all; + wire dbg_idel_down_cpt; + wire dbg_idel_up_all; + wire dbg_idel_up_cpt; + wire dbg_sel_all_idel_cpt; + wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt; + wire dbg_sel_pi_incdec; + wire [DQS_CNT_WIDTH:0] dbg_byte_sel; + wire dbg_pi_f_inc; + wire dbg_pi_f_dec; + wire [5:0] dbg_pi_counter_read_val; + wire [8:0] dbg_po_counter_read_val; + + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt; + wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt; + wire [255:0] dbg_calib_top; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt; + wire [(6*RANKS)-1:0] dbg_rd_data_offset; + wire [255:0] dbg_phy_rdlvl; + wire [99:0] dbg_phy_wrcal; + wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt; + wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt; + wire [255:0] dbg_phy_wrlvl; + wire [255:0] dbg_phy_init; + wire [255:0] dbg_prbs_rdlvl; + wire [255:0] dbg_dqs_found_cal; + wire dbg_pi_phaselock_start; + wire dbg_pi_phaselocked_done; + wire dbg_pi_phaselock_err; + wire dbg_pi_dqsfound_start; + wire dbg_pi_dqsfound_done; + wire dbg_pi_dqsfound_err; + wire dbg_wrcal_start; + wire dbg_wrcal_done; + wire dbg_wrcal_err; + wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes; + wire [11:0] dbg_pi_phase_locked_phy4lanes; + wire dbg_oclkdelay_calib_start; + wire dbg_oclkdelay_calib_done; + wire [255:0] dbg_phy_oclkdelay_cal; + wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data; + wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect; + wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata; + wire dbg_rddata_valid; + wire [1:0] dbg_rdlvl_done; + wire [1:0] dbg_rdlvl_err; + wire [1:0] dbg_rdlvl_start; + wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt; + wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt; + wire [5:0] dbg_tap_cnt_during_wrlvl; + wire dbg_wl_edge_detect_valid; + wire dbg_wrlvl_done; + wire dbg_wrlvl_err; + wire dbg_wrlvl_start; + reg [63:0] dbg_rddata_r; + reg dbg_rddata_valid_r; + wire [53:0] ocal_tap_cnt; + wire [4:0] dbg_dqs; + wire [8:0] dbg_bit; + wire [8:0] rd_data_edge_detect_r; + wire [53:0] wl_po_fine_cnt; + wire [26:0] wl_po_coarse_cnt; + wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1; + wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2; + wire [5:0] dbg_data_offset; + wire [5:0] dbg_data_offset_1; + wire [5:0] dbg_data_offset_2; + + wire [390:0] ddr3_ila_wrpath_int; + wire [1023:0] ddr3_ila_rdpath_int; + wire [119:0] ddr3_ila_basic_int; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int; + wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int; + + +//*************************************************************************** + + + + assign ui_clk = clk; + assign ui_clk_sync_rst = rst; + + assign sys_clk_p = 1'b0; + assign sys_clk_n = 1'b0; + assign clk_ref_p = 1'b0; + assign clk_ref_n = 1'b0; + assign device_temp = device_temp_s; + + + generate + if (REFCLK_TYPE == "USE_SYSTEM_CLOCK") + assign clk_ref_in = mmcm_clk; + else + assign clk_ref_in = clk_ref_i; + endgenerate + + mig_7series_v4_2_iodelay_ctrl # + ( + .TCQ (TCQ), + .IODELAY_GRP0 (IODELAY_GRP0), + .IODELAY_GRP1 (IODELAY_GRP1), + .REFCLK_TYPE (REFCLK_TYPE), + .SYSCLK_TYPE (SYSCLK_TYPE), + .SYS_RST_PORT (SYS_RST_PORT), + .RST_ACT_LOW (RST_ACT_LOW), + .DIFF_TERM_REFCLK (DIFF_TERM_REFCLK), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL) + ) + u_iodelay_ctrl + ( + // Outputs + .iodelay_ctrl_rdy (iodelay_ctrl_rdy), + .sys_rst_o (sys_rst_o), + .clk_ref (clk_ref), + // Inputs + .clk_ref_p (clk_ref_p), + .clk_ref_n (clk_ref_n), + .clk_ref_i (clk_ref_in), + .sys_rst (sys_rst) + ); + mig_7series_v4_2_clk_ibuf # + ( + .SYSCLK_TYPE (SYSCLK_TYPE), + .DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK) + ) + u_ddr3_clk_ibuf + ( + .sys_clk_p (sys_clk_p), + .sys_clk_n (sys_clk_n), + .sys_clk_i (sys_clk_i), + .mmcm_clk (mmcm_clk) + ); + // Temperature monitoring logic + + generate + if (TEMP_MON_EN == "ON") begin: temp_mon_enabled + + mig_7series_v4_2_tempmon # + ( + .TCQ (TCQ), + .TEMP_MON_CONTROL (TEMP_MON_CONTROL), + .XADC_CLK_PERIOD (XADC_CLK_PERIOD), + .tTEMPSAMPLE (tTEMPSAMPLE) + ) + u_tempmon + ( + .clk (clk), + .xadc_clk (clk_ref[0]), + .rst (rst), + .device_temp_i (device_temp_i), + .device_temp (device_temp_s) + ); + end else begin: temp_mon_disabled + + assign device_temp_s = 'b0; + + end + endgenerate + + mig_7series_v4_2_infrastructure # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLKIN_PERIOD (CLKIN_PERIOD), + .SYSCLK_TYPE (SYSCLK_TYPE), + .CLKFBOUT_MULT (CLKFBOUT_MULT), + .DIVCLK_DIVIDE (DIVCLK_DIVIDE), + .CLKOUT0_PHASE (CLKOUT0_PHASE), + .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), + .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), + .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), + .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), + .MMCM_VCO (MMCM_VCO), + .MMCM_MULT_F (MMCM_MULT_F), + .MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), + .RST_ACT_LOW (RST_ACT_LOW), + .tCK (tCK), + .MEM_TYPE (DRAM_TYPE) + ) + u_ddr3_infrastructure + ( + // Outputs + .rstdiv0 (rst), + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .mem_refclk (mem_refclk), + .freq_refclk (freq_refclk), + .sync_pulse (sync_pulse), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .iddr_rst (iddr_rst), +// .auxout_clk (), + .ui_addn_clk_0 (), + .ui_addn_clk_1 (), + .ui_addn_clk_2 (), + .ui_addn_clk_3 (), + .ui_addn_clk_4 (), + .pll_locked (pll_locked), + .mmcm_locked (), + .rst_phaser_ref (rst_phaser_ref), + // Inputs + .psen (psen), + .psincdec (psincdec), + .mmcm_clk (mmcm_clk), + .sys_rst (sys_rst_o), + .iodelay_ctrl_rdy (iodelay_ctrl_rdy), + .ref_dll_lock (ref_dll_lock) + ); + + + mig_7series_v4_2_memc_ui_top_std # + ( + .TCQ (TCQ), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .AL (AL), + .PAYLOAD_WIDTH (PAYLOAD_WIDTH), + .BANK_WIDTH (BANK_WIDTH), + .BM_CNT_WIDTH (BM_CNT_WIDTH), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .CA_MIRROR (CA_MIRROR), + .DDR3_VDD_OP_VOLT (VDD_OP_VOLT), + .CK_WIDTH (CK_WIDTH), + .COL_WIDTH (COL_WIDTH), + .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1), + .CS_WIDTH (CS_WIDTH), + .nCS_PER_RANK (nCS_PER_RANK), + .CKE_WIDTH (CKE_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .DM_WIDTH (DM_WIDTH), + .DQ_CNT_WIDTH (DQ_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .DRAM_WIDTH (DRAM_WIDTH), + .ECC (ECC), + .ECC_WIDTH (ECC_WIDTH), + .ECC_TEST (ECC_TEST), + .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), + .REFCLK_FREQ (REFCLK_FREQ), + .nAL (nAL), + .nBANK_MACHS (nBANK_MACHS), + .CKE_ODT_AUX (CKE_ODT_AUX), + .nCK_PER_CLK (nCK_PER_CLK), + .ORDERING (ORDERING), + .OUTPUT_DRV (OUTPUT_DRV), + .IBUF_LPWR_MODE (IBUF_LPWR_MODE), + .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN), + .BANK_TYPE (BANK_TYPE), + .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), + .IODELAY_GRP0 (IODELAY_GRP0), + .IODELAY_GRP1 (IODELAY_GRP1), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .REG_CTRL (REG_CTRL), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .CL (CL), + .CWL (CWL), + .tCK (tCK), + .tCKE (tCKE), + .tFAW (tFAW), + .tPRDI (tPRDI), + .tRAS (tRAS), + .tRCD (tRCD), + .tREFI (tREFI), + .tRFC (tRFC), + .tRP (tRP), + .tRRD (tRRD), + .tRTP (tRTP), + .tWTR (tWTR), + .tZQI (tZQI), + .tZQCS (tZQCS), + .USER_REFRESH (USER_REFRESH), + .TEMP_MON_EN (TEMP_MON_EN), + .WRLVL (WRLVL), + .DEBUG_PORT (DEBUG_PORT), + .CAL_WIDTH (CAL_WIDTH), + .RANK_WIDTH (RANK_WIDTH), + .RANKS (RANKS), + .ODT_WIDTH (ODT_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .APP_DATA_WIDTH (APP_DATA_WIDTH), + .APP_MASK_WIDTH (APP_MASK_WIDTH), + .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .CK_BYTE_MAP (CK_BYTE_MAP), + .ADDR_MAP (ADDR_MAP), + .BANK_MAP (BANK_MAP), + .CAS_MAP (CAS_MAP), + .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), + .CKE_MAP (CKE_MAP), + .ODT_MAP (ODT_MAP), + .CS_MAP (CS_MAP), + .PARITY_MAP (PARITY_MAP), + .RAS_MAP (RAS_MAP), + .WE_MAP (WE_MAP), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .DATA0_MAP (DATA0_MAP), + .DATA1_MAP (DATA1_MAP), + .DATA2_MAP (DATA2_MAP), + .DATA3_MAP (DATA3_MAP), + .DATA4_MAP (DATA4_MAP), + .DATA5_MAP (DATA5_MAP), + .DATA6_MAP (DATA6_MAP), + .DATA7_MAP (DATA7_MAP), + .DATA8_MAP (DATA8_MAP), + .DATA9_MAP (DATA9_MAP), + .DATA10_MAP (DATA10_MAP), + .DATA11_MAP (DATA11_MAP), + .DATA12_MAP (DATA12_MAP), + .DATA13_MAP (DATA13_MAP), + .DATA14_MAP (DATA14_MAP), + .DATA15_MAP (DATA15_MAP), + .DATA16_MAP (DATA16_MAP), + .DATA17_MAP (DATA17_MAP), + .MASK0_MAP (MASK0_MAP), + .MASK1_MAP (MASK1_MAP), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .IDELAY_ADJ (IDELAY_ADJ), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ), + .SLOT_0_CONFIG (SLOT_0_CONFIG), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .MEM_ADDR_ORDER (MEM_ADDR_ORDER), + .STARVE_LIMIT (STARVE_LIMIT), + .USE_CS_PORT (USE_CS_PORT), + .USE_DM_PORT (USE_DM_PORT), + .USE_ODT_PORT (USE_ODT_PORT), + .MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK), + .TAPSPERKCLK (TAPSPERKCLK), + .SKIP_CALIB (SKIP_CALIB), + .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) + ) + u_memc_ui_top_std + ( + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .clk_ref (clk_ref), + .mem_refclk (mem_refclk), //memory clock + .freq_refclk (freq_refclk), + .pll_lock (pll_locked), + .sync_pulse (sync_pulse), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .iddr_rst (iddr_rst), + .psen (psen), + .psincdec (psincdec), + .rst (rst), + .rst_phaser_ref (rst_phaser_ref), + .ref_dll_lock (ref_dll_lock), + +// Memory interface ports + .ddr_dq (ddr3_dq), + .ddr_dqs_n (ddr3_dqs_n), + .ddr_dqs (ddr3_dqs_p), + .ddr_addr (ddr3_addr), + .ddr_ba (ddr3_ba), + .ddr_cas_n (ddr3_cas_n), + .ddr_ck_n (ddr3_ck_n), + .ddr_ck (ddr3_ck_p), + .ddr_cke (ddr3_cke), + .ddr_cs_n (), + .ddr_dm (ddr3_dm), + .ddr_odt (ddr3_odt), + .ddr_ras_n (ddr3_ras_n), + .ddr_reset_n (ddr3_reset_n), + .ddr_parity (ddr3_parity), + .ddr_we_n (ddr3_we_n), + .bank_mach_next (bank_mach_next), + +// Application interface ports + .app_addr (app_addr), + .app_cmd (app_cmd), + .app_en (app_en), + .app_hi_pri (1'b0), + .app_wdf_data (app_wdf_data), + .app_wdf_end (app_wdf_end), + .app_wdf_mask (app_wdf_mask), + .app_wdf_wren (app_wdf_wren), + .app_ecc_multiple_err (app_ecc_multiple_err), + .app_ecc_single_err (app_ecc_single_err), + .app_rd_data (app_rd_data), + .app_rd_data_end (app_rd_data_end), + .app_rd_data_valid (app_rd_data_valid), + .app_rdy (app_rdy), + .app_wdf_rdy (app_wdf_rdy), + .app_sr_req (app_sr_req), + .app_sr_active (app_sr_active), + .app_ref_req (app_ref_req), + .app_ref_ack (app_ref_ack), + .app_zq_req (app_zq_req), + .app_zq_ack (app_zq_ack), + .app_raw_not_ecc ({2*nCK_PER_CLK{1'b0}}), + .app_correct_en_i (1'b1), + + .device_temp (device_temp_s), + + // skip calibration ports + `ifdef SKIP_CALIB + .calib_tap_req (calib_tap_req), + .calib_tap_load (calib_tap_load), + .calib_tap_addr (calib_tap_addr), + .calib_tap_val (calib_tap_val), + .calib_tap_load_done (calib_tap_load_done), + `else + .calib_tap_req (), + .calib_tap_load (1'b0), + .calib_tap_addr (7'b0), + .calib_tap_val (8'b0), + .calib_tap_load_done (1'b0), + `endif + +// Debug logic ports + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), + .dbg_sel_pi_incdec (dbg_sel_pi_incdec), + .dbg_sel_po_incdec (dbg_sel_po_incdec), + .dbg_byte_sel (dbg_byte_sel), + .dbg_pi_f_inc (dbg_pi_f_inc), + .dbg_pi_f_dec (dbg_pi_f_dec), + .dbg_po_f_inc (dbg_po_f_inc), + .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), + .dbg_po_f_dec (dbg_po_f_dec), + .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), + .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), + .dbg_calib_top (dbg_calib_top), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_rd_data_offset (dbg_rd_data_offset), + .dbg_phy_rdlvl (dbg_phy_rdlvl), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_rddata (dbg_rddata), + .dbg_rddata_valid (dbg_rddata_valid), + .dbg_rdlvl_done (dbg_rdlvl_done), + .dbg_rdlvl_err (dbg_rdlvl_err), + .dbg_rdlvl_start (dbg_rdlvl_start), + .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), + .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), + .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_wrlvl_done (dbg_wrlvl_done), + .dbg_wrlvl_err (dbg_wrlvl_err), + .dbg_wrlvl_start (dbg_wrlvl_start), + .dbg_phy_wrlvl (dbg_phy_wrlvl), + .dbg_phy_init (dbg_phy_init), + .dbg_prbs_rdlvl (dbg_prbs_rdlvl), + .dbg_pi_counter_read_val (dbg_pi_counter_read_val), + .dbg_po_counter_read_val (dbg_po_counter_read_val), + .dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int), + .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int), + .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int), + .dbg_pi_phaselock_start (dbg_pi_phaselock_start), + .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done), + .dbg_pi_phaselock_err (dbg_pi_phaselock_err), + .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), + .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), + .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), + .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err), + .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1), + .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2), + .dbg_data_offset (dbg_data_offset), + .dbg_data_offset_1 (dbg_data_offset_1), + .dbg_data_offset_2 (dbg_data_offset_2), + .dbg_wrcal_start (dbg_wrcal_start), + .dbg_wrcal_done (dbg_wrcal_done), + .dbg_wrcal_err (dbg_wrcal_err), + .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), + .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), + .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), + .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), + .dbg_dqs_found_cal (dbg_dqs_found_cal), + .init_calib_complete (init_calib_complete), + .dbg_poc () + ); + + + + + + + //********************************************************************* + // Resetting all RTL debug inputs as the debug ports are not enabled + //********************************************************************* + assign dbg_idel_down_all = 1'b0; + assign dbg_idel_down_cpt = 1'b0; + assign dbg_idel_up_all = 1'b0; + assign dbg_idel_up_cpt = 1'b0; + assign dbg_sel_all_idel_cpt = 1'b0; + assign dbg_sel_idel_cpt = 'b0; + assign dbg_byte_sel = 'd0; + assign dbg_sel_pi_incdec = 1'b0; + assign dbg_pi_f_inc = 1'b0; + assign dbg_pi_f_dec = 1'b0; + assign dbg_po_f_inc = 'b0; + assign dbg_po_f_dec = 'b0; + assign dbg_po_f_stg23_sel = 'b0; + assign dbg_sel_po_incdec = 'b0; + + + +endmodule + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v new file mode 100644 index 0000000..9f1f076 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v @@ -0,0 +1,173 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ecc_buf.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ecc_buf + #( + parameter TCQ = 100, + parameter PAYLOAD_WIDTH = 64, + parameter DATA_BUF_ADDR_WIDTH = 4, + parameter DATA_BUF_OFFSET_WIDTH = 1, + parameter DATA_WIDTH = 64, + parameter nCK_PER_CLK = 4 + ) + ( + /*AUTOARG*/ + // Outputs + rd_merge_data, + // Inputs + clk, rst, rd_data_addr, rd_data_offset, wr_data_addr, + wr_data_offset, rd_data, wr_ecc_buf + ); + + input clk; + input rst; + + // RMW architecture supports only 16 data buffer entries. + // Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but + // assume the upper bits are used for tagging. + + input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; + input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; + wire [4:0] buf_wr_addr; + + input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; + input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; + reg [4:0] buf_rd_addr_r; + + generate + if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits + always @(posedge clk) + buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset}; + assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset}; + end + else begin : lt_4_addr_bits + always @(posedge clk) + buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}}, + wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0], + wr_data_offset}; + assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}}, + rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0], + rd_data_offset}; + end + endgenerate + + input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; + reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload; + integer h; + always @(/*AS*/rd_data) + for (h=0; h<2*nCK_PER_CLK; h=h+1) + payload[h*DATA_WIDTH+:DATA_WIDTH] = + rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH]; + + input wr_ecc_buf; + localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH; + localparam FULL_RAM_CNT = (BUF_WIDTH/6); + localparam REMAINDER = BUF_WIDTH % 6; + localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); + localparam RAM_WIDTH = (RAM_CNT*6); + wire [RAM_WIDTH-1:0] buf_out_data; + generate + begin : ram_buf + wire [RAM_WIDTH-1:0] buf_in_data; + if (REMAINDER == 0) + assign buf_in_data = payload; + else + assign buf_in_data = {{6-REMAINDER{1'b0}}, payload}; + + genvar i; + for (i=0; i 0) + for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits + always @(/*AS*/ecc_rddata_r) + rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] = + ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH]; + end + endgenerate + + // Generate status information. + input ecc_status_valid; + output wire [2*nCK_PER_CLK-1:0] ecc_single; + output wire [2*nCK_PER_CLK-1:0] ecc_multiple; + genvar v; + generate + for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status + wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; + wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH]; + assign ecc_single[v] = ecc_status_valid && ~zero && odd; + assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd; + end + endgenerate + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v new file mode 100644 index 0000000..43754bc --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v @@ -0,0 +1,203 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ecc_gen.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1ps/1ps + +// Generate the ecc code. Note that the synthesizer should +// generate this as a static logic. Code in this block should +// never run during simulation phase, or directly impact timing. +// +// The code generated is a single correct, double detect code. +// It is the classic Hamming code. Instead, the code is +// optimized for minimal/balanced tree depth and size. See +// Hsiao IBM Technial Journal 1970. +// +// The code is returned as a single bit vector, h_rows. This was +// the only way to "subroutinize" this with the restrictions of +// disallowed include files and that matrices cannot be passed +// in ports. +// +// Factorial and the combos functions are defined. Combos +// simply computes the number of combinations from the set +// size and elements at a time. +// +// The function next_combo computes the next combination in +// lexicographical order given the "current" combination. Its +// output is undefined if given the last combination in the +// lexicographical order. +// +// next_combo is insensitive to the number of elements in the +// combinations. +// +// An H transpose matrix is generated because that's the easiest +// way to do it. The H transpose matrix is generated by taking +// the one at a time combinations, then the 3 at a time, then +// the 5 at a time. The number combinations used is equal to +// the width of the code (CODE_WIDTH). The boundaries between +// the 1, 3 and 5 groups are hardcoded in the for loop. +// +// At the same time the h_rows vector is generated from the +// H transpose matrix. + +module mig_7series_v4_2_ecc_gen + #( + parameter CODE_WIDTH = 72, + parameter ECC_WIDTH = 8, + parameter DATA_WIDTH = 64 + ) + ( + /*AUTOARG*/ + // Outputs + h_rows + ); + + + function integer factorial (input integer i); + integer index; + if (i == 1) factorial = 1; + else begin + factorial = 1; + for (index=2; index<=i; index=index+1) + factorial = factorial * index; + end + endfunction // factorial + + function integer combos (input integer n, k); + combos = factorial(n)/(factorial(k)*factorial(n-k)); + endfunction // combinations + + // function next_combo + // Given a combination, return the next combo in lexicographical + // order. Scans from right to left. Assumes the first combination + // is k ones all of the way to the left. + // + // Upon entry, initialize seen0, trig1, and ones. "seen0" means + // that a zero has been observed while scanning from right to left. + // "trig1" means that a one have been observed _after_ seen0 is set. + // "ones" counts the number of ones observed while scanning the input. + // + // If trig1 is one, just copy the input bit to the output and increment + // to the next bit. Otherwise set the the output bit to zero, if the + // input is a one, increment ones. If the input bit is a one and seen0 + // is true, dump out the accumulated ones. Set seen0 to the complement + // of the input bit. Note that seen0 is not used subsequent to trig1 + // getting set. + function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i); + integer index; + integer dump_index; + reg seen0; + reg trig1; +// integer ones; + reg [ECC_WIDTH-1:0] ones; + begin + seen0 = 1'b0; + trig1 = 1'b0; + ones = 0; + for (index=0; index=0;dump_index=dump_index-1) + if (dump_index>=index-ones) next_combo[dump_index] = 1'b1; + end + seen0 = ~i[index]; + end // else: !if(trig1) + end + end // function + endfunction // next_combo + + wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0]; + output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; + + localparam COMBOS_3 = combos(ECC_WIDTH, 3); + localparam COMBOS_5 = combos(ECC_WIDTH, 5); + genvar n; + genvar s; + generate + for (n=0; n DATA_WIDTH) + assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]= + wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]; + + end + endgenerate + + // Generate ECC and overlay onto mc_wrdata. + input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; + input [2*nCK_PER_CLK-1:0] raw_not_ecc; + reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r; + always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc; + output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata; + reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c; + genvar j; + integer k; + generate + for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word + always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin + mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] = + {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}}, + merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]}; + for (k=0; k 6) || (CL < 3))))); + // Not needed after the CWL fix for DDR2 + // ddr2_improper_CWL: assert property + // (@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL - CWL) != 1)))); +`endif + + mig_7series_v4_2_ddr_phy_top # + ( + .TCQ (TCQ), + .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), + .REFCLK_FREQ (REFCLK_FREQ), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .CA_MIRROR (CA_MIRROR), + .CK_BYTE_MAP (CK_BYTE_MAP), + .ADDR_MAP (ADDR_MAP), + .BANK_MAP (BANK_MAP), + .CAS_MAP (CAS_MAP), + .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), + .CKE_MAP (CKE_MAP), + .ODT_MAP (ODT_MAP), + .CKE_ODT_AUX (CKE_ODT_AUX), + .CS_MAP (CS_MAP), + .PARITY_MAP (PARITY_MAP), + .RAS_MAP (RAS_MAP), + .WE_MAP (WE_MAP), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .DATA0_MAP (DATA0_MAP), + .DATA1_MAP (DATA1_MAP), + .DATA2_MAP (DATA2_MAP), + .DATA3_MAP (DATA3_MAP), + .DATA4_MAP (DATA4_MAP), + .DATA5_MAP (DATA5_MAP), + .DATA6_MAP (DATA6_MAP), + .DATA7_MAP (DATA7_MAP), + .DATA8_MAP (DATA8_MAP), + .DATA9_MAP (DATA9_MAP), + .DATA10_MAP (DATA10_MAP), + .DATA11_MAP (DATA11_MAP), + .DATA12_MAP (DATA12_MAP), + .DATA13_MAP (DATA13_MAP), + .DATA14_MAP (DATA14_MAP), + .DATA15_MAP (DATA15_MAP), + .DATA16_MAP (DATA16_MAP), + .DATA17_MAP (DATA17_MAP), + .MASK0_MAP (MASK0_MAP), + .MASK1_MAP (MASK1_MAP), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .nCS_PER_RANK (nCS_PER_RANK), + .CS_WIDTH (CS_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + .PRE_REV3ES (PRE_REV3ES), + .CKE_WIDTH (CKE_WIDTH), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), + .DRAM_TYPE (DRAM_TYPE), + .BANK_WIDTH (BANK_WIDTH), + .CK_WIDTH (CK_WIDTH), + .COL_WIDTH (COL_WIDTH), + .DM_WIDTH (DM_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO), + .ROW_WIDTH (ROW_WIDTH), + .AL (AL), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .CL (nCL), + .CWL (nCWL), + .tRFC (tRFC), + .tREFI (tREFI), + .tCK (tCK), + .OUTPUT_DRV (OUTPUT_DRV), + .RANKS (RANKS), + .ODT_WIDTH (ODT_WIDTH), + .REG_CTRL (REG_CTRL), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .WRLVL (WRLVL), + .BANK_TYPE (BANK_TYPE), + .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), + .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + // Prevent the following simulation-related parameters from + // being overridden for synthesis - for synthesis only the + // default values of these parameters should be used + // synthesis translate_off + .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), + // synthesis translate_on + .USE_CS_PORT (USE_CS_PORT), + .USE_DM_PORT (USE_DM_PORT), + .USE_ODT_PORT (USE_ODT_PORT), + .MASTER_PHY_CTL (MASTER_PHY_CTL), + .DEBUG_PORT (DEBUG_PORT), + .IDELAY_ADJ (IDELAY_ADJ), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ), + .TAPSPERKCLK (TAPSPERKCLK), + .SKIP_CALIB (SKIP_CALIB), + .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) + ) + ddr_phy_top0 + ( + // Outputs + .calib_rd_data_offset_0 (calib_rd_data_offset_0), + .calib_rd_data_offset_1 (calib_rd_data_offset_1), + .calib_rd_data_offset_2 (calib_rd_data_offset_2), + .ddr_ck (ddr_ck), + .ddr_ck_n (ddr_ck_n), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_ras_n (ddr_ras_n), + .ddr_cas_n (ddr_cas_n), + .ddr_we_n (ddr_we_n), + .ddr_cs_n (ddr_cs_n), + .ddr_cke (ddr_cke), + .ddr_odt (ddr_odt), + .ddr_reset_n (ddr_reset_n), + .ddr_parity (ddr_parity), + .ddr_dm (ddr_dm), + .dbg_calib_top (dbg_calib_top), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_phy_rdlvl (dbg_phy_rdlvl), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_rddata (dbg_rddata), + .dbg_rdlvl_done (dbg_rdlvl_done), + .dbg_rdlvl_err (dbg_rdlvl_err), + .dbg_rdlvl_start (dbg_rdlvl_start), + .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_wrlvl_done (dbg_wrlvl_done), + .dbg_wrlvl_err (dbg_wrlvl_err), + .dbg_wrlvl_start (dbg_wrlvl_start), + .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), + .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .init_calib_complete (init_calib_complete_w), + .init_wrcal_complete (init_wrcal_complete_w), + .mc_address (mc_address), + .mc_aux_out0 (mc_aux_out0), + .mc_aux_out1 (mc_aux_out1), + .mc_bank (mc_bank), + .mc_cke (mc_cke), + .mc_odt (mc_odt), + .mc_cas_n (mc_cas_n), + .mc_cmd (mc_cmd), + .mc_cmd_wren (mc_cmd_wren), + .mc_cas_slot (mc_cas_slot), + .mc_cs_n (mc_cs_n), + .mc_ctl_wren (mc_ctl_wren), + .mc_data_offset (mc_data_offset), + .mc_data_offset_1 (mc_data_offset_1), + .mc_data_offset_2 (mc_data_offset_2), + .mc_rank_cnt (mc_rank_cnt), + .mc_ras_n (mc_ras_n), + .mc_reset_n (mc_reset_n), + .mc_we_n (mc_we_n), + .mc_wrdata (mc_wrdata), + .mc_wrdata_en (mc_wrdata_en), + .mc_wrdata_mask (mc_wrdata_mask), + .idle (idle), + .mem_refclk (mem_refclk), + .phy_mc_ctl_full (phy_mc_ctl_full), + .phy_mc_cmd_full (phy_mc_cmd_full), + .phy_mc_data_full (phy_mc_data_full), + .phy_rd_data (phy_rd_data), + .phy_rddata_valid (phy_rddata_valid), + .pll_lock (pll_lock), + .sync_pulse (sync_pulse), + // Inouts + .ddr_dqs (ddr_dqs), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dq (ddr_dq), + // Inputs + .clk_ref (clk_ref), + .freq_refclk (freq_refclk), + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .rst (rst), + .error (error), + .rst_tg_mc (rst_tg_mc), + .slot_0_present (slot_0_present), + .slot_1_present (slot_1_present), + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt) + + ,.device_temp (device_temp) + ,.tempmon_sample_en (tempmon_sample_en) + ,.psen (psen) + ,.psincdec (psincdec) + ,.psdone (psdone) + + ,.calib_tap_req (calib_tap_req) + ,.calib_tap_addr (calib_tap_addr) + ,.calib_tap_load (calib_tap_load) + ,.calib_tap_val (calib_tap_val) + ,.calib_tap_load_done (calib_tap_load_done) + + ,.dbg_sel_pi_incdec (dbg_sel_pi_incdec) + ,.dbg_sel_po_incdec (dbg_sel_po_incdec) + ,.dbg_byte_sel (dbg_byte_sel) + ,.dbg_pi_f_inc (dbg_pi_f_inc) + ,.dbg_po_f_inc (dbg_po_f_inc) + ,.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel) + ,.dbg_pi_f_dec (dbg_pi_f_dec) + ,.dbg_po_f_dec (dbg_po_f_dec) + ,.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt) + ,.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt) + ,.dbg_rddata_valid (dbg_rddata_valid) + ,.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt) + ,.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt) + ,.dbg_phy_wrlvl (dbg_phy_wrlvl) + ,.ref_dll_lock (ref_dll_lock) + ,.rst_phaser_ref (rst_phaser_ref) + ,.iddr_rst (iddr_rst) + ,.dbg_rd_data_offset (dbg_rd_data_offset) + ,.dbg_phy_init (dbg_phy_init) + ,.dbg_prbs_rdlvl (dbg_prbs_rdlvl) + ,.dbg_dqs_found_cal (dbg_dqs_found_cal) + ,.dbg_po_counter_read_val (dbg_po_counter_read_val) + ,.dbg_pi_counter_read_val (dbg_pi_counter_read_val) + ,.dbg_pi_phaselock_start (dbg_pi_phaselock_start) + ,.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done) + ,.dbg_pi_phaselock_err (dbg_pi_phaselock_err) + ,.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start) + ,.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done) + ,.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err) + ,.dbg_wrcal_start (dbg_wrcal_start) + ,.dbg_wrcal_done (dbg_wrcal_done) + ,.dbg_wrcal_err (dbg_wrcal_err) + ,.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal) + ,.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data) + ,.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start) + ,.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done) + ,.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r) + ,.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps) + ,.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps) + ,.dbg_poc (dbg_poc[1023:0]) + ); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v new file mode 100644 index 0000000..8f92036 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v @@ -0,0 +1,809 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 3.6 +// \ \ Application : MIG +// / / Filename : memc_ui_top_std.v +// /___/ /\ Date Last Modified : $Date: 2011/06/17 11:11:25 $ +// \ \ / \ Date Created : Fri Oct 08 2010 +// \___\/\___\ +// +// Device : 7 Series +// Design Name : DDR2 SDRAM & DDR3 SDRAM +// Purpose : +// Top level memory interface block. Instantiates a clock and +// reset generator, the memory controller, the phy and the +// user interface blocks. +// Reference : +// Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +(* X_CORE_INFO = "mig_7series_v4_2_ddr3_7Series, ddr3, 2018.3" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v4_2,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=0, CLK_PERIOD=3000, PHY_RATIO=4, CLKIN_PERIOD=3000, VCCAUX_IO=1.8V, MEMORY_TYPE=COMP, MEMORY_PART=mt41k256m16xx-125, DQ_WIDTH=16, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=0, USE_ODT_PORT=1, RTT_NOM=60, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=1, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=NO_BUFFER}" *) +module mig_7series_v4_2_memc_ui_top_std # + ( + parameter TCQ = 100, + parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 + parameter PAYLOAD_WIDTH = 64, + parameter ADDR_CMD_MODE = "UNBUF", + parameter AL = "0", // Additive Latency option + parameter BANK_WIDTH = 3, // # of bank bits + parameter BM_CNT_WIDTH = 2, // Bank machine counter width + parameter BURST_MODE = "8", // Burst length + parameter BURST_TYPE = "SEQ", // Burst type + parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank + parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory + parameter CL = 5, + parameter COL_WIDTH = 12, // column address width + parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY + parameter CS_WIDTH = 1, // # of unique CS outputs + parameter CKE_WIDTH = 1, // # of cke outputs + parameter CWL = 5, + parameter DATA_WIDTH = 64, + parameter DATA_BUF_ADDR_WIDTH = 5, + parameter DATA_BUF_OFFSET_WIDTH = 1, + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter DM_WIDTH = 8, // # of DM (data mask) + parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH)) + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_TYPE = "DDR3", + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter ECC = "OFF", + parameter ECC_WIDTH = 8, + parameter ECC_TEST = "OFF", + parameter MC_ERR_ADDR_WIDTH = 31, + parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides + parameter nAL = 0, // Additive latency (in clk cyc) + parameter nBANK_MACHS = 4, + parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK + parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank + parameter ORDERING = "NORM", + parameter IBUF_LPWR_MODE = "OFF", + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" + parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" + parameter IODELAY_GRP0 = "IODELAY_MIG0", + parameter IODELAY_GRP1 = "IODELAY_MIG1", + parameter FPGA_SPEED_GRADE = 1, + parameter OUTPUT_DRV = "HIGH", + parameter REG_CTRL = "OFF", + parameter RTT_NOM = "60", + parameter RTT_WR = "120", + parameter STARVE_LIMIT = 2, + parameter tCK = 2500, // pS + parameter tCKE = 10000, // pS + parameter tFAW = 40000, // pS + parameter tPRDI = 1_000_000, // pS + parameter tRAS = 37500, // pS + parameter tRCD = 12500, // pS + parameter tREFI = 7800000, // pS + parameter tRFC = 110000, // pS + parameter tRP = 12500, // pS + parameter tRRD = 10000, // pS + parameter tRTP = 7500, // pS + parameter tWTR = 7500, // pS + parameter tZQI = 128_000_000, // nS + parameter tZQCS = 64, // CKs + parameter USER_REFRESH = "OFF", // Whether user manages REF + parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon + parameter WRLVL = "OFF", + parameter DEBUG_PORT = "OFF", + parameter CAL_WIDTH = "HALF", + parameter RANK_WIDTH = 1, + parameter RANKS = 4, + parameter ODT_WIDTH = 1, + parameter ROW_WIDTH = 16, // DRAM address bus width + parameter ADDR_WIDTH = 32, + parameter APP_MASK_WIDTH = 8, + parameter APP_DATA_WIDTH = 64, + parameter [3:0] BYTE_LANES_B0 = 4'b1111, + parameter [3:0] BYTE_LANES_B1 = 4'b1111, + parameter [3:0] BYTE_LANES_B2 = 4'b1111, + parameter [3:0] BYTE_LANES_B3 = 4'b1111, + parameter [3:0] BYTE_LANES_B4 = 4'b1111, + parameter [3:0] DATA_CTL_B0 = 4'hc, + parameter [3:0] DATA_CTL_B1 = 4'hf, + parameter [3:0] DATA_CTL_B2 = 4'hf, + parameter [3:0] DATA_CTL_B3 = 4'h0, + parameter [3:0] DATA_CTL_B4 = 4'h0, + parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000, + parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000, + parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000, + + // control/address/data pin mapping parameters + parameter [143:0] CK_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter [191:0] ADDR_MAP + = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, + parameter [35:0] BANK_MAP = 36'h000_000_000, + parameter [11:0] CAS_MAP = 12'h000, + parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00, + parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000, + parameter CKE_ODT_AUX = "FALSE", + parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, + parameter [11:0] PARITY_MAP = 12'h000, + parameter [11:0] RAS_MAP = 12'h000, + parameter [11:0] WE_MAP = 12'h000, + parameter [143:0] DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000, + parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, + parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, + + parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001, + parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN", + // calibration Address. The address given below will be used for calibration + // read and write operations. + parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address + parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address + parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address + parameter SIM_BYPASS_INIT_CAL = "OFF", + parameter REFCLK_FREQ = 300.0, + parameter USE_CS_PORT = 1, // Support chip select output + parameter USE_DM_PORT = 1, // Support data mask output + parameter USE_ODT_PORT = 1, // Support ODT output + parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change + parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl + parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation + parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering + parameter SKIP_CALIB = "FALSE", + parameter TAPSPERKCLK = 56, + parameter FPGA_VOLT_TYPE = "N" + ) + ( + // Clock and reset ports + input clk, + input clk_div2, + input rst_div2, + input [1:0] clk_ref, + input mem_refclk , + input freq_refclk , + input pll_lock, + input sync_pulse , + input mmcm_ps_clk, + input poc_sample_pd, + + input rst, + + // memory interface ports + inout [DQ_WIDTH-1:0] ddr_dq, + inout [DQS_WIDTH-1:0] ddr_dqs_n, + inout [DQS_WIDTH-1:0] ddr_dqs, + output [ROW_WIDTH-1:0] ddr_addr, + output [BANK_WIDTH-1:0] ddr_ba, + output ddr_cas_n, + output [CK_WIDTH-1:0] ddr_ck_n, + output [CK_WIDTH-1:0] ddr_ck, + output [CKE_WIDTH-1:0] ddr_cke, + output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, + output [DM_WIDTH-1:0] ddr_dm, + output [ODT_WIDTH-1:0] ddr_odt, + output ddr_ras_n, + output ddr_reset_n, + output ddr_parity, + output ddr_we_n, + + output [BM_CNT_WIDTH-1:0] bank_mach_next, + + // user interface ports + input [ADDR_WIDTH-1:0] app_addr, + input [2:0] app_cmd, + input app_en, + input app_hi_pri, + input [APP_DATA_WIDTH-1:0] app_wdf_data, + input app_wdf_end, + input [APP_MASK_WIDTH-1:0] app_wdf_mask, + input app_wdf_wren, + input app_correct_en_i, + input [2*nCK_PER_CLK-1:0] app_raw_not_ecc, + output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err, + output [2*nCK_PER_CLK-1:0] app_ecc_single_err, + output [APP_DATA_WIDTH-1:0] app_rd_data, + output app_rd_data_end, + output app_rd_data_valid, + output app_rdy, + output app_wdf_rdy, + + input app_sr_req, + output app_sr_active, + input app_ref_req, + output app_ref_ack, + input app_zq_req, + output app_zq_ack, + + // Ports to be used with SKIP_CALIB defined + output calib_tap_req, + input [6:0] calib_tap_addr, + input calib_tap_load, + input [7:0] calib_tap_val, + input calib_tap_load_done, + + // temperature monitor ports + input [11:0] device_temp, + //phase shift clock control + output psen, + output psincdec, + input psdone, + // debug logic ports + input dbg_idel_down_all, + input dbg_idel_down_cpt, + input dbg_idel_up_all, + input dbg_idel_up_cpt, + input dbg_sel_all_idel_cpt, + input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, + output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata, + output [1:0] dbg_rdlvl_done, + output [1:0] dbg_rdlvl_err, + output [1:0] dbg_rdlvl_start, + output [5:0] dbg_tap_cnt_during_wrlvl, + output dbg_wl_edge_detect_valid, + output dbg_wrlvl_done, + output dbg_wrlvl_err, + output dbg_wrlvl_start, + output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, + + output init_calib_complete, + input dbg_sel_pi_incdec, + input dbg_sel_po_incdec, + input [DQS_CNT_WIDTH:0] dbg_byte_sel, + input dbg_pi_f_inc, + input dbg_pi_f_dec, + input dbg_po_f_inc, + input dbg_po_f_stg23_sel, + input dbg_po_f_dec, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, + output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, + output dbg_rddata_valid, + output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, + output ref_dll_lock, + input rst_phaser_ref, + input iddr_rst, + output [6*RANKS-1:0] dbg_rd_data_offset, + output [255:0] dbg_calib_top, + output [255:0] dbg_phy_wrlvl, + output [255:0] dbg_phy_rdlvl, + output [99:0] dbg_phy_wrcal, + output [255:0] dbg_phy_init, + output [255:0] dbg_prbs_rdlvl, + output [255:0] dbg_dqs_found_cal, + output [5:0] dbg_pi_counter_read_val, + output [8:0] dbg_po_counter_read_val, + output dbg_pi_phaselock_start, + output dbg_pi_phaselocked_done, + output dbg_pi_phaselock_err, + output dbg_pi_dqsfound_start, + output dbg_pi_dqsfound_done, + output dbg_pi_dqsfound_err, + output dbg_wrcal_start, + output dbg_wrcal_done, + output dbg_wrcal_err, + output [11:0] dbg_pi_dqs_found_lanes_phy4lanes, + output [11:0] dbg_pi_phase_locked_phy4lanes, + output [6*RANKS-1:0] dbg_calib_rd_data_offset_1, + output [6*RANKS-1:0] dbg_calib_rd_data_offset_2, + output [5:0] dbg_data_offset, + output [5:0] dbg_data_offset_1, + output [5:0] dbg_data_offset_2, + output dbg_oclkdelay_calib_start, + output dbg_oclkdelay_calib_done, + output [255:0] dbg_phy_oclkdelay_cal, + output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, + output [1023:0] dbg_poc + + ); + + localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0; + +// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r; +// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps; +// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps; + + wire correct_en; + wire [2*nCK_PER_CLK-1:0] raw_not_ecc; + wire [2*nCK_PER_CLK-1:0] ecc_single; + wire [2*nCK_PER_CLK-1:0] ecc_multiple; + wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; + wire [DQ_WIDTH/8-1:0] fi_xor_we; + wire [DQ_WIDTH-1:0] fi_xor_wrdata; + + wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; + wire wr_data_en; + wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; + wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; + wire rd_data_en; + wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; + wire accept; + wire accept_ns; + wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; + wire rd_data_end; + wire use_addr; + wire size; + wire [ROW_WIDTH-1:0] row; + wire [RANK_WIDTH-1:0] rank; + wire hi_priority; + wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr; + wire [COL_WIDTH-1:0] col; + wire [2:0] cmd; + wire [BANK_WIDTH-1:0] bank; + wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; + wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask; + + wire app_sr_req_i; + wire app_sr_active_i; + wire app_ref_req_i; + wire app_ref_ack_i; + wire app_zq_req_i; + wire app_zq_ack_i; + + wire rst_tg_mc; + wire error; + wire init_wrcal_complete; + reg reset /* synthesis syn_maxfan = 10 */; + + //*************************************************************************** + + always @(posedge clk) + reset <= #TCQ (rst | rst_tg_mc); + + + assign fi_xor_we = {DQ_WIDTH/8{1'b0}} ; + assign fi_xor_wrdata = {DQ_WIDTH{1'b0}} ; + + mig_7series_v4_2_mem_intfc # + ( + .TCQ (TCQ), + .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), + .PAYLOAD_WIDTH (PAYLOAD_WIDTH), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .AL (AL), + .BANK_WIDTH (BANK_WIDTH), + .BM_CNT_WIDTH (BM_CNT_WIDTH), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .CA_MIRROR (CA_MIRROR), + .CK_WIDTH (CK_WIDTH), + .COL_WIDTH (COL_WIDTH), + .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1), + .CS_WIDTH (CS_WIDTH), + .nCS_PER_RANK (nCS_PER_RANK), + .CKE_WIDTH (CKE_WIDTH), + .DATA_WIDTH (DATA_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .MASTER_PHY_CTL (MASTER_PHY_CTL), + .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), + .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), + .DM_WIDTH (DM_WIDTH), + .DQ_CNT_WIDTH (DQ_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .DRAM_WIDTH (DRAM_WIDTH), + .ECC (ECC), + .ECC_WIDTH (ECC_WIDTH), + .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), + .REFCLK_FREQ (REFCLK_FREQ), + .nAL (nAL), + .nBANK_MACHS (nBANK_MACHS), + .nCK_PER_CLK (nCK_PER_CLK), + .ORDERING (ORDERING), + .OUTPUT_DRV (OUTPUT_DRV), + .IBUF_LPWR_MODE (IBUF_LPWR_MODE), + .BANK_TYPE (BANK_TYPE), + .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), + .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .REG_CTRL (REG_CTRL), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .CL (CL), + .CWL (CWL), + .tCK (tCK), + .tCKE (tCKE), + .tFAW (tFAW), + .tPRDI (tPRDI), + .tRAS (tRAS), + .tRCD (tRCD), + .tREFI (tREFI), + .tRFC (tRFC), + .tRP (tRP), + .tRRD (tRRD), + .tRTP (tRTP), + .tWTR (tWTR), + .tZQI (tZQI), + .tZQCS (tZQCS), + .USER_REFRESH (USER_REFRESH), + .TEMP_MON_EN (TEMP_MON_EN), + .WRLVL (WRLVL), + .DEBUG_PORT (DEBUG_PORT), + .CAL_WIDTH (CAL_WIDTH), + .RANK_WIDTH (RANK_WIDTH), + .RANKS (RANKS), + .ODT_WIDTH (ODT_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .CK_BYTE_MAP (CK_BYTE_MAP), + .ADDR_MAP (ADDR_MAP), + .BANK_MAP (BANK_MAP), + .CAS_MAP (CAS_MAP), + .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), + .CKE_MAP (CKE_MAP), + .ODT_MAP (ODT_MAP), + .CKE_ODT_AUX (CKE_ODT_AUX), + .CS_MAP (CS_MAP), + .PARITY_MAP (PARITY_MAP), + .RAS_MAP (RAS_MAP), + .WE_MAP (WE_MAP), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .DATA0_MAP (DATA0_MAP), + .DATA1_MAP (DATA1_MAP), + .DATA2_MAP (DATA2_MAP), + .DATA3_MAP (DATA3_MAP), + .DATA4_MAP (DATA4_MAP), + .DATA5_MAP (DATA5_MAP), + .DATA6_MAP (DATA6_MAP), + .DATA7_MAP (DATA7_MAP), + .DATA8_MAP (DATA8_MAP), + .DATA9_MAP (DATA9_MAP), + .DATA10_MAP (DATA10_MAP), + .DATA11_MAP (DATA11_MAP), + .DATA12_MAP (DATA12_MAP), + .DATA13_MAP (DATA13_MAP), + .DATA14_MAP (DATA14_MAP), + .DATA15_MAP (DATA15_MAP), + .DATA16_MAP (DATA16_MAP), + .DATA17_MAP (DATA17_MAP), + .MASK0_MAP (MASK0_MAP), + .MASK1_MAP (MASK1_MAP), + .SLOT_0_CONFIG (SLOT_0_CONFIG), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .STARVE_LIMIT (STARVE_LIMIT), + .USE_CS_PORT (USE_CS_PORT), + .USE_DM_PORT (USE_DM_PORT), + .USE_ODT_PORT (USE_ODT_PORT), + .IDELAY_ADJ (IDELAY_ADJ), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ), + .TAPSPERKCLK (TAPSPERKCLK), + .SKIP_CALIB (SKIP_CALIB), + .FPGA_VOLT_TYPE (FPGA_VOLT_TYPE) + ) + mem_intfc0 + ( + .clk (clk), + .clk_div2 (clk_div2), + .rst_div2 (rst_div2), + .clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]), + .mem_refclk (mem_refclk), //memory clock + .freq_refclk (freq_refclk), + .pll_lock (pll_lock), + .sync_pulse (sync_pulse), + .mmcm_ps_clk (mmcm_ps_clk), + .poc_sample_pd (poc_sample_pd), + .rst (rst), + .error (error), + .reset (reset), + .rst_tg_mc (rst_tg_mc), + + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs (ddr_dqs), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck (ddr_ck), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_parity (ddr_parity), + .ddr_we_n (ddr_we_n), + + .slot_0_present (SLOT_0_CONFIG), + .slot_1_present (SLOT_1_CONFIG), + + .correct_en (correct_en), + .bank (bank), + .cmd (cmd), + .col (col), + .data_buf_addr (data_buf_addr), + .wr_data (wr_data), + .wr_data_mask (wr_data_mask), + .rank (rank), + .raw_not_ecc (raw_not_ecc), + .row (row), + .hi_priority (hi_priority), + .size (size), + .use_addr (use_addr), + .accept (accept), + .accept_ns (accept_ns), + .ecc_single (ecc_single), + .ecc_multiple (ecc_multiple), + .ecc_err_addr (ecc_err_addr), + .rd_data (rd_data), + .rd_data_addr (rd_data_addr), + .rd_data_en (rd_data_en), + .rd_data_end (rd_data_end), + .rd_data_offset (rd_data_offset), + .wr_data_addr (wr_data_addr), + .wr_data_en (wr_data_en), + .wr_data_offset (wr_data_offset), + .bank_mach_next (bank_mach_next), + .init_calib_complete (init_calib_complete), + .init_wrcal_complete (init_wrcal_complete), + .app_sr_req (app_sr_req_i), + .app_sr_active (app_sr_active_i), + .app_ref_req (app_ref_req_i), + .app_ref_ack (app_ref_ack_i), + .app_zq_req (app_zq_req_i), + .app_zq_ack (app_zq_ack_i), + + // skip calibration i/f + .calib_tap_req (calib_tap_req), + .calib_tap_load (calib_tap_load), + .calib_tap_addr (calib_tap_addr), + .calib_tap_val (calib_tap_val), + .calib_tap_load_done (calib_tap_load_done), + + .device_temp (device_temp), + .psen (psen), + .psincdec (psincdec), + .psdone (psdone), + .fi_xor_we (fi_xor_we), + .fi_xor_wrdata (fi_xor_wrdata), + + + + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), + .dbg_calib_top (dbg_calib_top), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_phy_rdlvl (dbg_phy_rdlvl), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_rddata (dbg_rddata), + .dbg_rdlvl_done (dbg_rdlvl_done), + .dbg_rdlvl_err (dbg_rdlvl_err), + .dbg_rdlvl_start (dbg_rdlvl_start), + .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_wrlvl_done (dbg_wrlvl_done), + .dbg_wrlvl_err (dbg_wrlvl_err), + .dbg_wrlvl_start (dbg_wrlvl_start), + + .dbg_sel_pi_incdec (dbg_sel_pi_incdec), + .dbg_sel_po_incdec (dbg_sel_po_incdec), + .dbg_byte_sel (dbg_byte_sel), + .dbg_pi_f_inc (dbg_pi_f_inc), + .dbg_pi_f_dec (dbg_pi_f_dec), + .dbg_po_f_inc (dbg_po_f_inc), + .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), + .dbg_po_f_dec (dbg_po_f_dec), + .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), + .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), + .dbg_rddata_valid (dbg_rddata_valid), + .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), + .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), + .dbg_phy_wrlvl (dbg_phy_wrlvl), + .dbg_pi_counter_read_val (dbg_pi_counter_read_val), + .dbg_po_counter_read_val (dbg_po_counter_read_val), + .ref_dll_lock (ref_dll_lock), + .rst_phaser_ref (rst_phaser_ref), + .iddr_rst (iddr_rst), + .dbg_rd_data_offset (dbg_rd_data_offset), + .dbg_phy_init (dbg_phy_init), + .dbg_prbs_rdlvl (dbg_prbs_rdlvl), + .dbg_dqs_found_cal (dbg_dqs_found_cal), + .dbg_pi_phaselock_start (dbg_pi_phaselock_start), + .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done), + .dbg_pi_phaselock_err (dbg_pi_phaselock_err), + .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), + .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), + .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err), + .dbg_wrcal_start (dbg_wrcal_start), + .dbg_wrcal_done (dbg_wrcal_done), + .dbg_wrcal_err (dbg_wrcal_err), + .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), + .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1), + .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2), + .dbg_data_offset (dbg_data_offset), + .dbg_data_offset_1 (dbg_data_offset_1), + .dbg_data_offset_2 (dbg_data_offset_2), + .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), + .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), + .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), + .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), + .prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r), + .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), + .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), + .dbg_poc (dbg_poc[1023:0]) + ); + + mig_7series_v4_2_ui_top # + ( + .TCQ (TCQ), + .APP_DATA_WIDTH (APP_DATA_WIDTH), + .APP_MASK_WIDTH (APP_MASK_WIDTH), + .BANK_WIDTH (BANK_WIDTH), + .COL_WIDTH (COL_WIDTH), + .CWL (CWL), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .ECC (ECC), + .ECC_TEST (ECC_TEST), + .nCK_PER_CLK (nCK_PER_CLK), + .ORDERING (ORDERING), + .RANKS (RANKS), + .RANK_WIDTH (RANK_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .MEM_ADDR_ORDER (MEM_ADDR_ORDER) + ) + u_ui_top + ( + .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), + .wr_data (wr_data[APP_DATA_WIDTH-1:0]), + .use_addr (use_addr), + .size (size), + .row (row), + .raw_not_ecc (raw_not_ecc), + .rank (rank), + .hi_priority (hi_priority), + .data_buf_addr (data_buf_addr), + .col (col), + .cmd (cmd), + .bank (bank), + .app_wdf_rdy (app_wdf_rdy), + .app_rdy (app_rdy), + .app_rd_data_valid (app_rd_data_valid), + .app_rd_data_end (app_rd_data_end), + .app_rd_data (app_rd_data), + .app_ecc_multiple_err (app_ecc_multiple_err), + .app_ecc_single_err (app_ecc_single_err), + .correct_en (correct_en), + .wr_data_offset (wr_data_offset), + .wr_data_en (wr_data_en), + .wr_data_addr (wr_data_addr), + .rst (reset), + .rd_data_offset (rd_data_offset), + .rd_data_end (rd_data_end), + .rd_data_en (rd_data_en), + .rd_data_addr (rd_data_addr), + .rd_data (rd_data[APP_DATA_WIDTH-1:0]), + .ecc_multiple (ecc_multiple), + .ecc_single (ecc_single), + .clk (clk), + .app_wdf_wren (app_wdf_wren), + .app_wdf_mask (app_wdf_mask), + .app_wdf_end (app_wdf_end), + .app_wdf_data (app_wdf_data), + .app_sz (1'b1), + .app_raw_not_ecc (app_raw_not_ecc), + .app_hi_pri (app_hi_pri), + .app_en (app_en), + .app_cmd (app_cmd), + .app_addr (app_addr), + .accept_ns (accept_ns), + .accept (accept), + .app_correct_en (app_correct_en_i), + .app_sr_req (app_sr_req), + .sr_req (app_sr_req_i), + .sr_active (app_sr_active_i), + .app_sr_active (app_sr_active), + .app_ref_req (app_ref_req), + .ref_req (app_ref_req_i), + .ref_ack (app_ref_ack_i), + .app_ref_ack (app_ref_ack), + .app_zq_req (app_zq_req), + .zq_req (app_zq_req_i), + .zq_ack (app_zq_ack_i), + .app_zq_ack (app_zq_ack) + ); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v new file mode 100644 index 0000000..0db9d4b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v @@ -0,0 +1,535 @@ +/***************************************************************** +-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $ +// $Author: $ +// $DateTime: $ +// $Change: $ +// Description: +// This verilog file is a paramertizable I/O termination for +// the single byte lane. +// to create a N byte-lane wide phy. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +////////////////////////////////////////////////////////////////// +*****************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_byte_group_io #( +// bit lane existance + parameter BITLANES = 12'b1111_1111_1111, + parameter BITLANES_OUTONLY = 12'b0000_0000_0000, + parameter PO_DATA_CTL = "FALSE", + parameter OSERDES_DATA_RATE = "DDR", + parameter OSERDES_DATA_WIDTH = 4, + parameter IDELAYE2_IDELAY_TYPE = "VARIABLE", + parameter IDELAYE2_IDELAY_VALUE = 00, + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter real TCK = 2500.0, +// local usage only, don't pass down + parameter BUS_WIDTH = 12, + parameter SYNTHESIS = "FALSE" + ) + ( + input [9:0] mem_dq_in, + output [BUS_WIDTH-1:0] mem_dq_out, + output [BUS_WIDTH-1:0] mem_dq_ts, + input mem_dqs_in, + output mem_dqs_out, + output mem_dqs_ts, + output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used + output dqs_to_phaser, + input iserdes_clk, + input iserdes_clkb, + input iserdes_clkdiv, + input phy_clk, + input rst, + input oserdes_rst, + input iserdes_rst, + input [1:0] oserdes_dqs, + input [1:0] oserdes_dqsts, + input [(4*BUS_WIDTH)-1:0] oserdes_dq, + input [1:0] oserdes_dqts, + input oserdes_clk, + input oserdes_clk_delayed, + input oserdes_clkdiv, + input idelay_inc, + input idelay_ce, + input idelay_ld, + input idelayctrl_refclk, + input [29:0] fine_delay , + input fine_delay_sel + ); + + + +/// INSTANCES + + +localparam ISERDES_DQ_DATA_RATE = "DDR"; +localparam ISERDES_DQ_DATA_WIDTH = 4; +localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE"; +localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE"; +localparam ISERDES_DQ_INIT_Q1 = 1'b0; +localparam ISERDES_DQ_INIT_Q2 = 1'b0; +localparam ISERDES_DQ_INIT_Q3 = 1'b0; +localparam ISERDES_DQ_INIT_Q4 = 1'b0; +localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3"; +localparam ISERDES_NUM_CE = 2; +localparam ISERDES_DQ_IOBDELAY = "IFD"; +localparam ISERDES_DQ_OFB_USED = "FALSE"; +localparam ISERDES_DQ_SERDES_MODE = "MASTER"; +localparam ISERDES_DQ_SRVAL_Q1 = 1'b0; +localparam ISERDES_DQ_SRVAL_Q2 = 1'b0; +localparam ISERDES_DQ_SRVAL_Q3 = 1'b0; +localparam ISERDES_DQ_SRVAL_Q4 = 1'b0; + +localparam IDELAY_FINEDELAY_USE = (TCK > 1500) ? "FALSE" : "TRUE"; + +wire [BUS_WIDTH-1:0] data_in_dly; +wire [BUS_WIDTH-1:0] oserdes_dq_buf; +wire [BUS_WIDTH-1:0] oserdes_dqts_buf; +wire oserdes_dqs_buf; +wire oserdes_dqsts_buf; +wire [9:0] data_in; +wire tbyte_out; +reg [29:0] fine_delay_r; + +assign mem_dq_out = oserdes_dq_buf; +assign mem_dq_ts = oserdes_dqts_buf; +assign data_in = mem_dq_in; + +assign mem_dqs_out = oserdes_dqs_buf; +assign mem_dqs_ts = oserdes_dqsts_buf; +assign dqs_to_phaser = mem_dqs_in; + +reg iserdes_clk_d; + +always @(*) + iserdes_clk_d = iserdes_clk; + +reg idelay_ld_rst; +reg rst_r1; +reg rst_r2; +reg rst_r3; +reg rst_r4; + +always @(posedge phy_clk) begin + rst_r1 <= #1 rst; + rst_r2 <= #1 rst_r1; + rst_r3 <= #1 rst_r2; + rst_r4 <= #1 rst_r3; +end + +always @(posedge phy_clk) begin + if (rst) + idelay_ld_rst <= #1 1'b1; + else if (rst_r4) + idelay_ld_rst <= #1 1'b0; +end + +always @ (posedge phy_clk) begin + if(rst) + fine_delay_r <= #1 1'b0; + else if(fine_delay_sel) + fine_delay_r <= #1 fine_delay; +end + + +genvar i; + +generate + +for ( i = 0; i != 10 && PO_DATA_CTL == "TRUE" ; i=i+1) begin : input_ + if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_ + + ISERDESE2 #( + .DATA_RATE ( ISERDES_DQ_DATA_RATE), + .DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH), + .DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN), + .DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN), + .INIT_Q1 ( ISERDES_DQ_INIT_Q1), + .INIT_Q2 ( ISERDES_DQ_INIT_Q2), + .INIT_Q3 ( ISERDES_DQ_INIT_Q3), + .INIT_Q4 ( ISERDES_DQ_INIT_Q4), + .INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE), + .NUM_CE ( ISERDES_NUM_CE), + .IOBDELAY ( ISERDES_DQ_IOBDELAY), + .OFB_USED ( ISERDES_DQ_OFB_USED), + .SERDES_MODE ( ISERDES_DQ_SERDES_MODE), + .SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1), + .SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2), + .SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3), + .SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4) + ) + iserdesdq + ( + .O (), + .Q1 (iserdes_dout[4*i + 3]), + .Q2 (iserdes_dout[4*i + 2]), + .Q3 (iserdes_dout[4*i + 1]), + .Q4 (iserdes_dout[4*i + 0]), + .Q5 (), + .Q6 (), + .Q7 (), + .Q8 (), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + + .BITSLIP (1'b0), + .CE1 (1'b1), + .CE2 (1'b1), + .CLK (iserdes_clk_d), + .CLKB (!iserdes_clk_d), + .CLKDIVP (iserdes_clkdiv), + .CLKDIV (), + .DDLY (data_in_dly[i]), + .D (data_in[i]), // dedicated route to iob for debugging + // or as needed, select with IOBDELAY + .DYNCLKDIVSEL (1'b0), + .DYNCLKSEL (1'b0), +// NOTE: OCLK is not used in this design, but is required to meet +// a design rule check in map and bitgen. Do not disconnect it. + .OCLK (oserdes_clk), + .OCLKB (), + .OFB (), + .RST (1'b0), +// .RST (iserdes_rst), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0) + ); + +localparam IDELAYE2_CINVCTRL_SEL = "FALSE"; +localparam IDELAYE2_DELAY_SRC = "IDATAIN"; +localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE"; +localparam IDELAYE2_PIPE_SEL = "FALSE"; +localparam IDELAYE2_ODELAY_TYPE = "FIXED"; +localparam IDELAYE2_REFCLK_FREQUENCY = ((FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) && TCK <= 1500) ? 400.0 : + (FPGA_SPEED_GRADE == 1 && TCK <= 1500) ? 300.0 : 200.0; +localparam IDELAYE2_SIGNAL_PATTERN = "DATA"; +localparam IDELAYE2_FINEDELAY_IN = "ADD_DLY"; + + if(IDELAY_FINEDELAY_USE == "TRUE") begin: idelay_finedelay_dq + (* IODELAY_GROUP = IODELAY_GRP *) + IDELAYE2_FINEDELAY #( + .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL), + .DELAY_SRC ( IDELAYE2_DELAY_SRC), + .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE), + .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE), + .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE), + .PIPE_SEL ( IDELAYE2_PIPE_SEL), + .FINEDELAY ( IDELAYE2_FINEDELAY_IN), + .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ), + .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN) + ) + idelaye2 + ( + .CNTVALUEOUT (), + .DATAOUT (data_in_dly[i]), + .C (phy_clk), // automatically wired by ISE + .CE (idelay_ce), + .CINVCTRL (), + .CNTVALUEIN (5'b00000), + .DATAIN (1'b0), + .IDATAIN (data_in[i]), + .IFDLY (fine_delay_r[i*3+:3]), + .INC (idelay_inc), + .LD (idelay_ld | idelay_ld_rst), + .LDPIPEEN (1'b0), + .REGRST (rst) + ); + end else begin : idelay_dq + (* IODELAY_GROUP = IODELAY_GRP *) + IDELAYE2 #( + .CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL), + .DELAY_SRC ( IDELAYE2_DELAY_SRC), + .HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE), + .IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE), + .IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE), + .PIPE_SEL ( IDELAYE2_PIPE_SEL), + .REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ), + .SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN) + ) + idelaye2 + ( + .CNTVALUEOUT (), + .DATAOUT (data_in_dly[i]), + .C (phy_clk), // automatically wired by ISE + .CE (idelay_ce), + .CINVCTRL (), + .CNTVALUEIN (5'b00000), + .DATAIN (1'b0), + .IDATAIN (data_in[i]), + .INC (idelay_inc), + .LD (idelay_ld | idelay_ld_rst), + .LDPIPEEN (1'b0), + .REGRST (rst) + ); + + end + end // iserdes_dq + else begin + assign iserdes_dout[4*i + 3] = 0; + assign iserdes_dout[4*i + 2] = 0; + assign iserdes_dout[4*i + 1] = 0; + assign iserdes_dout[4*i + 0] = 0; + end +end // input_ +endgenerate // iserdes_dq_ + +localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE; +localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ; +localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH; +localparam OSERDES_DQ_INIT_OQ = 1'b1; +localparam OSERDES_DQ_INIT_TQ = 1'b1; +localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT"; +localparam OSERDES_DQ_ODELAY_USED = 0; +localparam OSERDES_DQ_SERDES_MODE = "MASTER"; +localparam OSERDES_DQ_SRVAL_OQ = 1'b1; +localparam OSERDES_DQ_SRVAL_TQ = 1'b1; +// note: obuf used in control path case, no ts input so width irrelevant +localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1; + +localparam OSERDES_DQS_DATA_RATE_OQ = "DDR"; +localparam OSERDES_DQS_DATA_RATE_TQ = "DDR"; +localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr +localparam OSERDES_DQS_DATA_WIDTH = 4; +localparam ODDR_CLK_EDGE = "SAME_EDGE"; +localparam OSERDES_TBYTE_CTL = "TRUE"; + + +generate + +localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH; + + if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts + OSERDESE2 #( + .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), + .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), + .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), + .INIT_OQ (OSERDES_DQ_INIT_OQ), + .INIT_TQ (OSERDES_DQ_INIT_TQ), + .SERDES_MODE (OSERDES_DQ_SERDES_MODE), + .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ), + .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), + .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH), + .TBYTE_CTL ("TRUE"), + .TBYTE_SRC ("TRUE") + ) + oserdes_slave_ts + ( + .OFB (), + .OQ (), + .SHIFTOUT1 (), // not extended + .SHIFTOUT2 (), // not extended + .TFB (), + .TQ (), + .CLK (oserdes_clk), + .CLKDIV (oserdes_clkdiv), + .D1 (), + .D2 (), + .D3 (), + .D4 (), + .D5 (), + .D6 (), + .D7 (), + .D8 (), + .OCE (1'b1), + .RST (oserdes_rst), + .SHIFTIN1 (), // not extended + .SHIFTIN2 (), // not extended + .T1 (oserdes_dqts[0]), + .T2 (oserdes_dqts[0]), + .T3 (oserdes_dqts[1]), + .T4 (oserdes_dqts[1]), + .TCE (1'b1), + .TBYTEOUT (tbyte_out), + .TBYTEIN (tbyte_out) + ); + end // slave_ts + + for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_ + if ( BITLANES[i]) begin : oserdes_dq_ + + if ( PO_DATA_CTL == "TRUE" ) begin : ddr + + OSERDESE2 #( + .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), + .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), + .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), + .INIT_OQ (OSERDES_DQ_INIT_OQ), + .INIT_TQ (OSERDES_DQ_INIT_TQ), + .SERDES_MODE (OSERDES_DQ_SERDES_MODE), + .SRVAL_OQ (OSERDES_DQ_SRVAL_OQ), + .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), + .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH), + .TBYTE_CTL (OSERDES_TBYTE_CTL), + .TBYTE_SRC ("FALSE") + ) + oserdes_dq_i + ( + .OFB (), + .OQ (oserdes_dq_buf[i]), + .SHIFTOUT1 (), // not extended + .SHIFTOUT2 (), // not extended + .TBYTEOUT (), + .TFB (), + .TQ (oserdes_dqts_buf[i]), + .CLK (oserdes_clk), + .CLKDIV (oserdes_clkdiv), + .D1 (oserdes_dq[4 * i + 0]), + .D2 (oserdes_dq[4 * i + 1]), + .D3 (oserdes_dq[4 * i + 2]), + .D4 (oserdes_dq[4 * i + 3]), + .D5 (), + .D6 (), + .D7 (), + .D8 (), + .OCE (1'b1), + .RST (oserdes_rst), + .SHIFTIN1 (), // not extended + .SHIFTIN2 (), // not extended + .T1 (/*oserdes_dqts[0]*/), + .T2 (/*oserdes_dqts[0]*/), + .T3 (/*oserdes_dqts[1]*/), + .T4 (/*oserdes_dqts[1]*/), + .TCE (1'b1), + .TBYTEIN (tbyte_out) + ); + end + else begin : sdr + OSERDESE2 #( + .DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ), + .DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ), + .DATA_WIDTH (OSERDES_DQ_DATA_WIDTH), + .INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/), + .INIT_TQ (OSERDES_DQ_INIT_TQ), + .SERDES_MODE (OSERDES_DQ_SERDES_MODE), + .SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/), + .SRVAL_TQ (OSERDES_DQ_SRVAL_TQ), + .TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH) + ) + oserdes_dq_i + ( + .OFB (), + .OQ (oserdes_dq_buf[i]), + .SHIFTOUT1 (), // not extended + .SHIFTOUT2 (), // not extended + .TBYTEOUT (), + .TFB (), + .TQ (), + .CLK (oserdes_clk), + .CLKDIV (oserdes_clkdiv), + .D1 (oserdes_dq[4 * i + 0]), + .D2 (oserdes_dq[4 * i + 1]), + .D3 (oserdes_dq[4 * i + 2]), + .D4 (oserdes_dq[4 * i + 3]), + .D5 (), + .D6 (), + .D7 (), + .D8 (), + .OCE (1'b1), + .RST (oserdes_rst), + .SHIFTIN1 (), // not extended + .SHIFTIN2 (), // not extended + .T1 (), + .T2 (), + .T3 (), + .T4 (), + .TCE (1'b1), + .TBYTEIN () + ); + end // ddr + end // oserdes_dq_ + end // output_ + +endgenerate + +generate + + if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen + + ODDR + #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) + oddr_dqs + ( + .Q (oserdes_dqs_buf), + .D1 (oserdes_dqs[0]), + .D2 (oserdes_dqs[1]), + .C (oserdes_clk_delayed), + .R (1'b0), + .S (), + .CE (1'b1) + ); + + ODDR + #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) + oddr_dqsts + ( .Q (oserdes_dqsts_buf), + .D1 (oserdes_dqsts[0]), + .D2 (oserdes_dqsts[0]), + .C (oserdes_clk_delayed), + .R (), + .S (1'b0), + .CE (1'b1) + ); + + end // sdr rate + else begin:null_dqs + end +endgenerate + +endmodule // byte_group_io + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v new file mode 100644 index 0000000..7ba97f4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v @@ -0,0 +1,801 @@ +/*********************************************************** +-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $ +// $Author: gary $ +// $DateTime: 2010/05/11 18:05:17 $ +// $Change: 490882 $ +// Description: +// This verilog file is a parameterizable single 10 or 12 bit byte lane. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +//////////////////////////////////////////////////////////// +***********************************************************/ + + +`timescale 1ps/1ps + +//`include "phy.vh" + +module mig_7series_v4_2_ddr_byte_lane #( +// these are used to scale the index into phaser,calib,scan,mc vectors +// to access fields used in this instance + parameter ABCD = "A", // A,B,C, or D + parameter PO_DATA_CTL = "FALSE", + parameter BITLANES = 12'b1111_1111_1111, + parameter BITLANES_OUTONLY = 12'b1111_1111_1111, + parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, + parameter RCLK_SELECT_LANE = "B", + parameter PC_CLK_RATIO = 4, + parameter USE_PRE_POST_FIFO = "FALSE", +//OUT_FIFO + parameter OF_ALMOST_EMPTY_VALUE = 1, + parameter OF_ALMOST_FULL_VALUE = 1, + parameter OF_ARRAY_MODE = "UNDECLARED", + parameter OF_OUTPUT_DISABLE = "FALSE", + parameter OF_SYNCHRONOUS_MODE = "TRUE", +//IN_FIFO + parameter IF_ALMOST_EMPTY_VALUE = 1, + parameter IF_ALMOST_FULL_VALUE = 1, + parameter IF_ARRAY_MODE = "UNDECLARED", + parameter IF_SYNCHRONOUS_MODE = "TRUE", +//PHASER_IN + parameter PI_BURST_MODE = "TRUE", + parameter PI_CLKOUT_DIV = 2, + parameter PI_FREQ_REF_DIV = "NONE", + parameter PI_FINE_DELAY = 1, + parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", + parameter PI_SEL_CLK_OFFSET = 0, + + parameter PI_SYNC_IN_DIV_RST = "FALSE", +//PHASER_OUT + parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2, + parameter PO_FINE_DELAY = 0, + parameter PO_COARSE_BYPASS = "FALSE", + parameter PO_COARSE_DELAY = 0, + parameter PO_OCLK_DELAY = 0, + parameter PO_OCLKDELAY_INV = "TRUE", + parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF", + parameter PO_SYNC_IN_DIV_RST = "FALSE", +// OSERDES + parameter OSERDES_DATA_RATE = "DDR", + parameter OSERDES_DATA_WIDTH = 4, + +//IDELAY + parameter IDELAYE2_IDELAY_TYPE = "VARIABLE", + parameter IDELAYE2_IDELAY_VALUE = 00, + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter real TCK = 0.00, + parameter SYNTHESIS = "FALSE", + +// local constants, do not pass in from above + parameter BUS_WIDTH = 12, + parameter MSB_BURST_PEND_PO = 3, + parameter MSB_BURST_PEND_PI = 7, + parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8, + parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1 + ,parameter CKE_ODT_AUX = "FALSE" + ,parameter PI_DIV2_INCDEC = "FALSE" + )( + input rst, + input phy_clk, + input rst_pi_div2, + input clk_div2, + input freq_refclk, + input mem_refclk, + input idelayctrl_refclk, + input sync_pulse, + output [BUS_WIDTH-1:0] mem_dq_out, + output [BUS_WIDTH-1:0] mem_dq_ts, + input [9:0] mem_dq_in, + output mem_dqs_out, + output mem_dqs_ts, + input mem_dqs_in, + output [11:0] ddr_ck_out, + output rclk, + input if_empty_def, + output if_a_empty, + output if_empty, + output if_a_full, + output if_full, + output of_a_empty, + output of_empty, + output of_a_full, + output of_full, + output pre_fifo_a_full, + output [79:0] phy_din, + input [79:0] phy_dout, + input phy_cmd_wr_en, + input phy_data_wr_en, + input phy_rd_en, + input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus, + input idelay_inc, + input idelay_ce, + input idelay_ld, + input if_rst, + input [2:0] byte_rd_en_oth_lanes, + input [1:0] byte_rd_en_oth_banks, + output byte_rd_en, + + output po_coarse_overflow, + output po_fine_overflow, + output [8:0] po_counter_read_val, + input po_fine_enable, + input po_coarse_enable, + input [1:0] po_en_calib, + input po_fine_inc, + input po_coarse_inc, + input po_counter_load_en, + input po_counter_read_en, + input po_sel_fine_oclk_delay, + input [8:0] po_counter_load_val, + + input [1:0] pi_en_calib, + input pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input pi_counter_read_en, + input [5:0] pi_counter_load_val, + + output wire pi_iserdes_rst, + output pi_phase_locked, + output pi_fine_overflow, + output [5:0] pi_counter_read_val, + output wire pi_dqs_found, + output dqs_out_of_range, + input [29:0] fine_delay, + input fine_delay_sel +); + +localparam PHASER_INDEX = + (ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0)); +localparam L_OF_ARRAY_MODE = + (OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE : + (PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4"; +localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE : + (PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8"; + +localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ; +localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4; +localparam real L_FREQ_REF_PERIOD_NS = (TCK >= 2500.0) ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0; // DIV2 change +localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0; +localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0; +localparam ODDR_CLK_EDGE = "SAME_EDGE"; +localparam PO_DCD_CORRECTION = "ON"; +localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000; + +localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK >= 2500)) ? 1 : 0; // DIV2 change +localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK >= 2500)) ? "001" : "000"; // DIV2 change + +wire [1:0] oserdes_dqs; +wire [1:0] oserdes_dqs_ts; +wire [1:0] oserdes_dq_ts; + +wire [3:0] of_q9; +wire [3:0] of_q8; +wire [3:0] of_q7; +wire [7:0] of_q6; +wire [7:0] of_q5; +wire [3:0] of_q4; +wire [3:0] of_q3; +wire [3:0] of_q2; +wire [3:0] of_q1; +wire [3:0] of_q0; +wire [7:0] of_d9; +wire [7:0] of_d8; +wire [7:0] of_d7; +wire [7:0] of_d6; +wire [7:0] of_d5; +wire [7:0] of_d4; +wire [7:0] of_d3; +wire [7:0] of_d2; +wire [7:0] of_d1; +wire [7:0] of_d0; + +wire [7:0] if_q9; +wire [7:0] if_q8; +wire [7:0] if_q7; +wire [7:0] if_q6; +wire [7:0] if_q5; +wire [7:0] if_q4; +wire [7:0] if_q3; +wire [7:0] if_q2; +wire [7:0] if_q1; +wire [7:0] if_q0; +wire [3:0] if_d9; +wire [3:0] if_d8; +wire [3:0] if_d7; +wire [3:0] if_d6; +wire [3:0] if_d5; +wire [3:0] if_d4; +wire [3:0] if_d3; +wire [3:0] if_d2; +wire [3:0] if_d1; +wire [3:0] if_d0; + +wire [3:0] dummy_i5; +wire [3:0] dummy_i6; + +wire [48-1:0] of_dqbus; +wire [10*4-1:0] iserdes_dout; + +wire iserdes_clk; +wire iserdes_clkdiv; +wire ififo_wr_enable; +wire phy_rd_en_; + + +wire dqs_to_phaser; +wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en; +wire if_empty_; +wire if_a_empty_; +wire if_full_; +wire if_a_full_; +wire po_oserdes_rst; +wire empty_post_fifo; +reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */; +wire [79:0] rd_data; +reg [79:0] rd_data_r; + +reg ififo_rst = 1'b1; +reg ofifo_rst = 1'b1; + +wire of_wren_pre; +wire [79:0] pre_fifo_dout; +wire pre_fifo_full; +wire pre_fifo_rden; +wire [5:0] ddr_ck_out_q; +wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */; +wire oserdes_clkdiv; +wire oserdes_clk_delayed; +wire po_rd_enable; + +always @(posedge phy_clk) begin + ififo_rst <= #1 pi_rst_dqs_find | if_rst ; +// reset only data o-fifos on reset of dqs_found + ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst; +end + +// IN_FIFO EMPTY->RDEN TIMING FIX: +// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO +// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty +assign #(25) phy_rd_en_ = 1'b1; +//assign #(25) phy_rd_en_ = phy_rd_en; + +generate +if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null + assign if_empty = 0; + assign if_a_empty = 0; + assign if_full = 0; + assign if_a_full = 0; +end +else begin : if_empty_gen + assign if_empty = empty_post_fifo; + assign if_a_empty = if_a_empty_; + assign if_full = if_full_; + assign if_a_full = if_a_full_; +end +endgenerate + +generate +if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48 + assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0}; + assign phy_din = 80'h0; + assign byte_rd_en = 1'b1; +end +else begin : dq_gen_40 + + assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0}; + assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) : + ((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en); + + if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen + + // IN_FIFO EMPTY->RDEN TIMING FIX: + assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0}; + + always @(posedge phy_clk) begin + rd_data_r <= #(025) rd_data; + if_empty_r[0] <= #(025) if_empty_; + if_empty_r[1] <= #(025) if_empty_; + if_empty_r[2] <= #(025) if_empty_; + if_empty_r[3] <= #(025) if_empty_; + end + + + mig_7series_v4_2_ddr_if_post_fifo # + ( + .TCQ (25), // simulation CK->Q delay + .DEPTH (4), //2 // depth - account for up to 2 cycles of skew + .WIDTH (80) // width + ) + u_ddr_if_post_fifo + ( + .clk (phy_clk), + .rst (ififo_rst), + .empty_in (if_empty_r), + .rd_en_in (ififo_rd_en_in), + .d_in (rd_data_r), + .empty_out (empty_post_fifo), + .byte_rd_en (byte_rd_en), + .d_out (phy_din) + ); + + end + else begin : phy_din_gen + assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0}; + assign empty_post_fifo = if_empty_; + end + +end +endgenerate + + +assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout; + + +wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11); + + + + +generate + +if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen + assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout; + mig_7series_v4_2_ddr_of_pre_fifo # + ( + .TCQ (25), // simulation CK->Q delay + .DEPTH (9), // depth - set to 9 to accommodate flow control + .WIDTH (80) // width + ) + u_ddr_of_pre_fifo + ( + .clk (phy_clk), + .rst (ofifo_rst), + .full_in (of_full), + .wr_en_in (phy_wr_en), + .d_in (phy_dout), + .wr_en_out (of_wren_pre), + .d_out (pre_fifo_dout), + .afull (pre_fifo_a_full) + ); +end +else begin +// wire direct to ofifo + assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout; + assign of_wren_pre = phy_wr_en; +end + + +endgenerate + +/////////////////////////////////////////////////////////////////////////////// +// Synchronize pi_phase_locked to phy_clk domain +/////////////////////////////////////////////////////////////////////////////// +wire pi_phase_locked_w; +wire pi_dqs_found_w; +wire [5:0] pi_counter_read_val_w; +generate + if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_clk + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r1; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r2; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r3; + reg pi_phase_locked_r4; + + (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r1; + (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r2; + (* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r3; + reg pi_dqs_found_r4; + + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r1; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r2; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r3; + reg [5:0] pi_counter_read_val_r4; + + always @ (posedge phy_clk) begin + pi_phase_locked_r1 <= pi_phase_locked_w; + pi_phase_locked_r2 <= pi_phase_locked_r1; + pi_phase_locked_r3 <= pi_phase_locked_r2; + pi_dqs_found_r1 <= pi_dqs_found_w; + pi_dqs_found_r2 <= pi_dqs_found_r1; + pi_dqs_found_r3 <= pi_dqs_found_r2; + pi_counter_read_val_r1 <= pi_counter_read_val_w; + pi_counter_read_val_r2 <= pi_counter_read_val_r1; + pi_counter_read_val_r3 <= pi_counter_read_val_r2; + end + + always @ (posedge phy_clk) begin + if (rst) + pi_phase_locked_r4 <= 1'b0; + else if (pi_phase_locked_r2 == pi_phase_locked_r3) + pi_phase_locked_r4 <= pi_phase_locked_r3; + end + + always @ (posedge phy_clk) begin + if (rst) + pi_dqs_found_r4 <= 1'b0; + else if (pi_dqs_found_r2 == pi_dqs_found_r3) + pi_dqs_found_r4 <= pi_dqs_found_r3; + end + + always @ (posedge phy_clk) begin + if (rst) + pi_counter_read_val_r4 <= 1'b0; + else if (pi_counter_read_val_r2 == pi_counter_read_val_r3) + pi_counter_read_val_r4 <= pi_counter_read_val_r3; + end + + assign pi_phase_locked = pi_phase_locked_r4; + assign pi_dqs_found = pi_dqs_found_r4; + assign pi_counter_read_val = pi_counter_read_val_r4; + + end else begin: pahser_in_div4_clk + assign pi_phase_locked = pi_phase_locked_w; + assign pi_dqs_found = pi_dqs_found_w; + assign pi_counter_read_val = pi_counter_read_val_w; + end +endgenerate + + +generate + +if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen + +//if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_sys_clk +if (PI_DIV2_INCDEC == "TRUE") begin + +PHASER_IN_PHY #( + .BURST_MODE ( PI_BURST_MODE), + .CLKOUT_DIV ( PI_CLKOUT_DIV), + .DQS_AUTO_RECAL ( DQS_AUTO_RECAL), + .DQS_FIND_PATTERN ( DQS_FIND_PATTERN), + .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET), + .FINE_DELAY ( PI_FINE_DELAY), + .FREQ_REF_DIV ( PI_FREQ_REF_DIV), + .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC), + .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS), + .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS) +) phaser_in ( + .DQSFOUND (pi_dqs_found_w), + .DQSOUTOFRANGE (dqs_out_of_range), + .FINEOVERFLOW (pi_fine_overflow), + .PHASELOCKED (pi_phase_locked_w), + .ISERDESRST (pi_iserdes_rst), + .ICLKDIV (iserdes_clkdiv), + .ICLK (iserdes_clk), + .COUNTERREADVAL (pi_counter_read_val_w), + .RCLK (rclk), + .WRENABLE (ififo_wr_enable), + .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]), + .ENCALIBPHY (pi_en_calib), + .FINEENABLE (pi_fine_enable), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .RANKSELPHY (rank_sel_i), + .PHASEREFCLK (dqs_to_phaser), + .RSTDQSFIND (pi_rst_dqs_find), + .RST (rst_pi_div2), + .FINEINC (pi_fine_inc), + .COUNTERLOADEN (pi_counter_load_en), + .COUNTERREADEN (pi_counter_read_en), + .COUNTERLOADVAL (pi_counter_load_val), + .SYNCIN (sync_pulse), + .SYSCLK (clk_div2) +); +end + +else begin + +PHASER_IN_PHY #( + .BURST_MODE ( PI_BURST_MODE), + .CLKOUT_DIV ( PI_CLKOUT_DIV), + .DQS_AUTO_RECAL ( DQS_AUTO_RECAL), + .DQS_FIND_PATTERN ( DQS_FIND_PATTERN), + .SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET), + .FINE_DELAY ( PI_FINE_DELAY), + .FREQ_REF_DIV ( PI_FREQ_REF_DIV), + .OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC), + .SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS), + .PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS) +) phaser_in ( + .DQSFOUND (pi_dqs_found_w), + .DQSOUTOFRANGE (dqs_out_of_range), + .FINEOVERFLOW (pi_fine_overflow), + .PHASELOCKED (pi_phase_locked_w), + .ISERDESRST (pi_iserdes_rst), + .ICLKDIV (iserdes_clkdiv), + .ICLK (iserdes_clk), + .COUNTERREADVAL (pi_counter_read_val_w), + .RCLK (rclk), + .WRENABLE (ififo_wr_enable), + .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]), + .ENCALIBPHY (pi_en_calib), + .FINEENABLE (pi_fine_enable), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .RANKSELPHY (rank_sel_i), + .PHASEREFCLK (dqs_to_phaser), + .RSTDQSFIND (pi_rst_dqs_find), + .RST (rst), + .FINEINC (pi_fine_inc), + .COUNTERLOADEN (pi_counter_load_en), + .COUNTERREADEN (pi_counter_read_en), + .COUNTERLOADVAL (pi_counter_load_val), + .SYNCIN (sync_pulse), + .SYSCLK (phy_clk) +); + +end +end +else begin + assign pi_dqs_found_w = 1'b1; +// assign pi_dqs_out_of_range = 1'b0; + assign pi_phase_locked_w = 1'b1; +end + +endgenerate + +wire #0 phase_ref = freq_refclk; + +wire oserdes_clk; + + +PHASER_OUT_PHY #( + .CLKOUT_DIV ( PO_CLKOUT_DIV), + .DATA_CTL_N ( PO_DATA_CTL ), + .FINE_DELAY ( PO_FINE_DELAY), + .COARSE_BYPASS ( PO_COARSE_BYPASS ), + .COARSE_DELAY ( PO_COARSE_DELAY), + .OCLK_DELAY ( PO_OCLK_DELAY), + .OCLKDELAY_INV ( PO_OCLKDELAY_INV), + .OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC), + .SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .PHASEREFCLK_PERIOD ( 1), // dummy, not used + .PO ( PO_DCD_SETTING ), + .MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS) +) phaser_out ( + .COARSEOVERFLOW (po_coarse_overflow), + .CTSBUS (oserdes_dqs_ts), + .DQSBUS (oserdes_dqs), + .DTSBUS (oserdes_dq_ts), + .FINEOVERFLOW (po_fine_overflow), + .OCLKDIV (oserdes_clkdiv), + .OCLK (oserdes_clk), + .OCLKDELAYED (oserdes_clk_delayed), + .COUNTERREADVAL (po_counter_read_val), + .BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]), + .ENCALIBPHY (po_en_calib), + .RDENABLE (po_rd_enable), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .PHASEREFCLK (/*phase_ref*/), + .RST (rst), + .OSERDESRST (po_oserdes_rst), + .COARSEENABLE (po_coarse_enable), + .FINEENABLE (po_fine_enable), + .COARSEINC (po_coarse_inc), + .FINEINC (po_fine_inc), + .SELFINEOCLKDELAY (po_sel_fine_oclk_delay), + .COUNTERLOADEN (po_counter_load_en), + .COUNTERREADEN (po_counter_read_en), + .COUNTERLOADVAL (po_counter_load_val), + .SYNCIN (sync_pulse), + .SYSCLK (phy_clk) +); + + +generate + +if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen + +IN_FIFO #( + .ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ), + .ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ), + .ARRAY_MODE ( L_IF_ARRAY_MODE), + .SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE) +) in_fifo ( + .ALMOSTEMPTY (if_a_empty_), + .ALMOSTFULL (if_a_full_), + .EMPTY (if_empty_), + .FULL (if_full_), + .Q0 (if_q0), + .Q1 (if_q1), + .Q2 (if_q2), + .Q3 (if_q3), + .Q4 (if_q4), + .Q5 (if_q5), + .Q6 (if_q6), + .Q7 (if_q7), + .Q8 (if_q8), + .Q9 (if_q9), +//=== + .D0 (if_d0), + .D1 (if_d1), + .D2 (if_d2), + .D3 (if_d3), + .D4 (if_d4), + .D5 ({dummy_i5,if_d5}), + .D6 ({dummy_i6,if_d6}), + .D7 (if_d7), + .D8 (if_d8), + .D9 (if_d9), + .RDCLK (phy_clk), + .RDEN (phy_rd_en_), + .RESET (ififo_rst), + .WRCLK (iserdes_clkdiv), + .WREN (ififo_wr_enable) +); +end + +endgenerate + + + +OUT_FIFO #( + .ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .ARRAY_MODE (L_OF_ARRAY_MODE), + .OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + .SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE) +) out_fifo ( + .ALMOSTEMPTY (of_a_empty), + .ALMOSTFULL (of_a_full), + .EMPTY (of_empty), + .FULL (of_full), + .Q0 (of_q0), + .Q1 (of_q1), + .Q2 (of_q2), + .Q3 (of_q3), + .Q4 (of_q4), + .Q5 (of_q5), + .Q6 (of_q6), + .Q7 (of_q7), + .Q8 (of_q8), + .Q9 (of_q9), + .D0 (of_d0), + .D1 (of_d1), + .D2 (of_d2), + .D3 (of_d3), + .D4 (of_d4), + .D5 (of_d5), + .D6 (of_d6), + .D7 (of_d7), + .D8 (of_d8), + .D9 (of_d9), + .RDCLK (oserdes_clkdiv), + .RDEN (po_rd_enable), + .RESET (ofifo_rst), + .WRCLK (phy_clk), + .WREN (of_wren_pre) +); + + +mig_7series_v4_2_ddr_byte_group_io # + ( + .PO_DATA_CTL (PO_DATA_CTL), + .BITLANES (BITLANES), + .BITLANES_OUTONLY (BITLANES_OUTONLY), + .OSERDES_DATA_RATE (L_OSERDES_DATA_RATE), + .OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE), + .TCK (TCK), + .SYNTHESIS (SYNTHESIS) + ) + ddr_byte_group_io + ( + .mem_dq_out (mem_dq_out), + .mem_dq_ts (mem_dq_ts), + .mem_dq_in (mem_dq_in), + .mem_dqs_in (mem_dqs_in), + .mem_dqs_out (mem_dqs_out), + .mem_dqs_ts (mem_dqs_ts), + .rst (rst), + .oserdes_rst (po_oserdes_rst), + .iserdes_rst (pi_iserdes_rst ), + .iserdes_dout (iserdes_dout), + .dqs_to_phaser (dqs_to_phaser), + .phy_clk (phy_clk), + .iserdes_clk (iserdes_clk), + .iserdes_clkb (!iserdes_clk), + .iserdes_clkdiv (iserdes_clkdiv), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .idelayctrl_refclk (idelayctrl_refclk), + .oserdes_clk (oserdes_clk), + .oserdes_clk_delayed (oserdes_clk_delayed), + .oserdes_clkdiv (oserdes_clkdiv), + .oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}), + .oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}), + .oserdes_dq (of_dqbus), + .oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) + ); + +genvar i; +generate + for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop + if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen + ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE)) + ddr_ck ( + .C (oserdes_clk), + .R (1'b0), + .S (), + .D1 (1'b0), + .D2 (1'b1), + .CE (1'b1), + .Q (ddr_ck_out_q[i]) + ); + OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1])); + end // ddr_ck_gen + else begin : ddr_ck_null + assign ddr_ck_out[i*2+1:i*2] = 2'b0; + end + end // ddr_ck_gen_loop +endgenerate + +endmodule // byte_lane + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v new file mode 100644 index 0000000..687149d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v @@ -0,0 +1,2292 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_calib_top.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +//Purpose: +// Top-level for memory physical layer (PHY) interface +// NOTES: +// 1. Need to support multiple copies of CS outputs +// 2. DFI_DRAM_CKE_DISABLE not supported +// +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $ +**$Date: 2011/06/02 08:35:06 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_calib_top # + ( + parameter TCQ = 100, + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter tCK = 2500, // DDR3 SDRAM clock period + parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 + parameter CLK_PERIOD = 3333, // Internal clock period (in ps) + parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH + parameter HIGHEST_LANE = 4, + parameter HIGHEST_BANK = 3, + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + // five fields, one per possible I/O bank, 4 bits in each field, + // 1 per lane data=1/ctl=0 + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + // defines the byte lanes in I/O banks being used in the interface + // 1- Used, 0- Unused + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map + parameter CTL_BANK = 3'b000, // Bank used for control byte lanes + // Slot Conifg parameters + parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, + // DRAM bus widths + parameter BANK_WIDTH = 2, // # of bank bits + parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank + parameter COL_WIDTH = 10, // column address width + parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter ROW_WIDTH = 14, // DRAM address bus width + parameter RANKS = 1, // # of memory ranks in the interface + parameter CS_WIDTH = 1, // # of CS# signals in the interface + parameter CKE_WIDTH = 1, // # of cke outputs + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter PER_BIT_DESKEW = "ON", + // calibration Address. The address given below will be used for calibration + // read and write operations. + parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib + parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address + parameter CALIB_COL_ADD = 12'h000, // Calibration column address + parameter CALIB_BA_ADD = 3'h0, // Calibration bank address + // DRAM mode settings + parameter AL = "0", // Additive Latency option + parameter TEST_AL = "0", // Additive Latency for internal use + parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" + parameter BURST_MODE = "8", // Burst length + parameter BURST_TYPE = "SEQ", // Burst type + parameter nCL = 5, // Read CAS latency (in clk cyc) + parameter nCWL = 5, // Write CAS latency (in clk cyc) + parameter tRFC = 110000, // Refresh-to-command delay + parameter tREFI = 7800000, // pS Refresh-to-Refresh delay + parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option + parameter REG_CTRL = "ON", // "ON" for registered DIMM + parameter RTT_NOM = "60", // ODT Nominal termination value + parameter RTT_WR = "60", // ODT Write termination value + parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA + // 1 - ODT output from FPGA + parameter WRLVL = "OFF", // Enable write leveling + parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly + parameter POC_USE_METASTABLE_SAMP = "FALSE", + + // Simulation /debug options + parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps + parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps + parameter CKE_ODT_AUX = "FALSE", + parameter IDELAY_ADJ = "ON", + parameter FINE_PER_BIT = "ON", + parameter CENTER_COMP_MODE = "ON", + parameter PI_VAL_ADJ = "ON", + parameter TAPSPERKCLK = 56, + parameter DEBUG_PORT = "OFF", // Enable debug port + parameter SKIP_CALIB = "FALSE", + parameter PI_DIV2_INCDEC = "TRUE" + ) + ( + input clk, // Internal (logic) clock + input rst, // Reset sync'ed to CLK + // Slot present inputs + input [7:0] slot_0_present, + input [7:0] slot_1_present, + // Hard PHY signals + // From PHY Ctrl Block + input phy_ctl_ready, + input phy_ctl_full, + input phy_cmd_full, + input phy_data_full, + // To PHY Ctrl Block + output write_calib, + output read_calib, + output calib_ctl_wren, + output calib_cmd_wren, + output [1:0] calib_seq, + output [3:0] calib_aux_out, + output [nCK_PER_CLK -1:0] calib_cke, + output [1:0] calib_odt, + output [2:0] calib_cmd, + output calib_wrdata_en, + output [1:0] calib_rank_cnt, + output [1:0] calib_cas_slot, + output [5:0] calib_data_offset_0, + output [5:0] calib_data_offset_1, + output [5:0] calib_data_offset_2, + output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, + output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, + output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, + output [nCK_PER_CLK-1:0] phy_ras_n, + output [nCK_PER_CLK-1:0] phy_cas_n, + output [nCK_PER_CLK-1:0] phy_we_n, + output phy_reset_n, + // To hard PHY wrapper + output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */, + output reg calib_in_common/* synthesis syn_maxfan = 10 */, + output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */, + output reg [HIGHEST_BANK-1:0] calib_zero_ctrl, + output phy_if_empty_def, + output reg phy_if_reset, +// output reg ck_addr_ctl_delay_done, + // From DQS Phaser_In + input pi_phaselocked, + input pi_phase_locked_all, + input pi_found_dqs, + input pi_dqs_found_all, + input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + input [5:0] pi_counter_read_val, + // To DQS Phaser_In + output [HIGHEST_BANK-1:0] pi_rst_stg1_cal, + output pi_en_stg2_f, + output pi_stg2_f_incdec, + output pi_stg2_load, + output [5:0] pi_stg2_reg_l, + // To DQ IDELAY + output idelay_ce, + output idelay_inc, + output idelay_ld, + // To DQS Phaser_Out + output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */, + output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */, + output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */, + output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */, + output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */, + output po_counter_load_en, + input [8:0] po_counter_read_val, + // To command Phaser_Out + input phy_if_empty, + input [4:0] idelaye2_init_val, + input [5:0] oclkdelay_init_val, + + input tg_err, + output rst_tg_mc, + // Write data to OUT_FIFO + output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata, + // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew + output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, + // IN_FIFO read enable during write leveling, write calibration, + // and read leveling + // Read data from hard PHY fans out to mc and calib logic + input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata, + // To MC + output [6*RANKS-1:0] calib_rd_data_offset_0, + output [6*RANKS-1:0] calib_rd_data_offset_1, + output [6*RANKS-1:0] calib_rd_data_offset_2, + output phy_rddata_valid, + output calib_writes, + (* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */, + output init_wrcal_complete, + output pi_phase_locked_err, + output pi_dqsfound_err, + output wrcal_err, + input pd_out, + // input mmcm_ps_clk, //phase shift clock + // input oclkdelay_fb_clk, //Write DQS feedback clk + //phase shift clock control + output psen, + output psincdec, + input psdone, + input poc_sample_pd, + + // Ports to be used when SKIP_CALIB="TRUE" + output reg calib_tap_req, + input [6:0] calib_tap_addr, + input calib_tap_load, + input [7:0] calib_tap_val, + input calib_tap_load_done, + + // Debug Port + output dbg_pi_phaselock_start, + output dbg_pi_dqsfound_start, + output dbg_pi_dqsfound_done, + output dbg_wrcal_start, + output dbg_wrcal_done, + output dbg_wrlvl_start, + output dbg_wrlvl_done, + output dbg_wrlvl_err, + output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, + output [255:0] dbg_phy_wrlvl, + output [5:0] dbg_tap_cnt_during_wrlvl, + output dbg_wl_edge_detect_valid, + output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, + + // Write Calibration Logic + output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, + output [99:0] dbg_phy_wrcal, + + // Read leveling logic + output [1:0] dbg_rdlvl_start, + output [1:0] dbg_rdlvl_done, + output [1:0] dbg_rdlvl_err, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, + output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, + + // Delay control + input [11:0] device_temp, + input tempmon_sample_en, + input dbg_sel_pi_incdec, + input dbg_sel_po_incdec, + input [DQS_CNT_WIDTH:0] dbg_byte_sel, + input dbg_pi_f_inc, + input dbg_pi_f_dec, + input dbg_po_f_inc, + input dbg_po_f_stg23_sel, + input dbg_po_f_dec, + input dbg_idel_up_all, + input dbg_idel_down_all, + input dbg_idel_up_cpt, + input dbg_idel_down_cpt, + input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, + input dbg_sel_all_idel_cpt, + output [255:0] dbg_phy_rdlvl, // Read leveling calibration + output [255:0] dbg_calib_top, // General PHY debug + output dbg_oclkdelay_calib_start, + output dbg_oclkdelay_calib_done, + output [255:0] dbg_phy_oclkdelay_cal, + output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, + output [255:0] dbg_phy_init, + output [255:0] dbg_prbs_rdlvl, + output [255:0] dbg_dqs_found_cal, + output [1023:0] dbg_poc, + + output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, + output reg [DQS_CNT_WIDTH:0] byte_sel_cnt, + output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit + output fine_delay_sel + ); + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + +// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center +// align DQ and DQS on writes. Round (up or down) value to nearest integer +// localparam integer SHIFT_TBY4_TAP +// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) / +// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4); + +// Calculate number of slots in the system + localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); + + localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK >= 2500) || (SKIP_CALIB == "TRUE")) ? "OFF" : "ON"; //DIV2 change + + // Different CTL_LANES value for DDR2. In DDR2 during DQS found all + // the add,ctl & data phaser out fine delays will be adjusted. + // In DDR3 only the add/ctrl lane delays will be adjusted + localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1; + + localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK >= 2500)) ? "LEFT" : "RIGHT"; // DIV2 change IO Bank used for Memory I/F: "LEFT", "RIGHT" + + localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE"; + localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration + localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration + localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration + + //Per-bit deskew for higher freqency (>800Mhz) + //localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF"; + + //BYPASS + localparam BYPASS_COMPLEX_RDLVL = ((tCK > 2500) || (SKIP_CALIB == "TRUE")) ? "TRUE": "FALSE"; //"TRUE"; + localparam BYPASS_COMPLEX_OCAL = "TRUE"; + //localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE"; + + // 8*tREFI in ps is divided by the fabric clock period in ps + // 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times + localparam REFRESH_TIMER = (8*tREFI/(tCK*nCK_PER_CLK)) - 270; + + localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER); + + wire [2*8*nCK_PER_CLK-1:0] prbs_seed; + //wire [2*8*nCK_PER_CLK-1:0] prbs_out; + wire [8*DQ_WIDTH-1:0] prbs_out; + wire [7:0] prbs_rise0; + wire [7:0] prbs_fall0; + wire [7:0] prbs_rise1; + wire [7:0] prbs_fall1; + wire [7:0] prbs_rise2; + wire [7:0] prbs_fall2; + wire [7:0] prbs_rise3; + wire [7:0] prbs_fall3; + //wire [2*8*nCK_PER_CLK-1:0] prbs_o; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; + wire dqsfound_retry; + wire dqsfound_retry_done; + wire phy_rddata_en; + wire prech_done; + wire rdlvl_stg1_done; + reg rdlvl_stg1_done_r1; + wire pi_dqs_found_done; + wire rdlvl_stg1_err; + wire pi_dqs_found_err; + wire wrcal_pat_resume; + wire wrcal_resume_w; + wire rdlvl_prech_req; + wire rdlvl_last_byte_done; + wire rdlvl_stg1_start; + wire rdlvl_stg1_rank_done; + wire rdlvl_assrt_common; + wire pi_dqs_found_start; + wire pi_dqs_found_rank_done; + wire wl_sm_start; + wire wrcal_start; + wire wrcal_rd_wait; + wire wrcal_prech_req; + wire wrcal_pat_err; + wire wrcal_done; + wire wrlvl_done; + wire wrlvl_err; + wire wrlvl_start; + wire ck_addr_cmd_delay_done; + wire po_ck_addr_cmd_delay_done; + wire pi_calib_done; + wire detect_pi_found_dqs; + wire [5:0] rd_data_offset_0; + wire [5:0] rd_data_offset_1; + wire [5:0] rd_data_offset_2; + wire [6*RANKS-1:0] rd_data_offset_ranks_0; + wire [6*RANKS-1:0] rd_data_offset_ranks_1; + wire [6*RANKS-1:0] rd_data_offset_ranks_2; + wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0; + wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1; + wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2; + wire cmd_po_stg2_f_incdec; + wire cmd_po_stg2_incdec_ddr2_c; + wire cmd_po_en_stg2_f; + wire cmd_po_en_stg2_ddr2_c; + wire cmd_po_stg2_c_incdec; + wire cmd_po_en_stg2_c; + wire po_stg2_ddr2_incdec; + wire po_en_stg2_ddr2; + wire dqs_po_stg2_f_incdec; + wire dqs_po_en_stg2_f; + wire dqs_wl_po_stg2_c_incdec; + wire wrcal_po_stg2_c_incdec; + wire dqs_wl_po_en_stg2_c; + wire wrcal_po_en_stg2_c; + wire [N_CTL_LANES-1:0] ctl_lane_cnt; + reg [N_CTL_LANES-1:0] ctl_lane_sel; + wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt; + wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt; + wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt; + wire [8:0] dqs_wl_po_stg2_reg_l; + wire dqs_wl_po_stg2_load; + wire [8:0] dqs_po_stg2_reg_l; + wire dqs_po_stg2_load; + wire dqs_po_dec_done; + wire pi_fine_dly_dec_done; + wire rdlvl_pi_stg2_f_incdec; + wire rdlvl_pi_stg2_f_en; + wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt; + //reg [DQS_CNT_WIDTH:0] byte_sel_cnt; + wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt; + wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt; + wire phase_locked_err; + wire phy_ctl_rdy_dly; + wire idelay_ce_int; + wire idelay_inc_int; + reg idelay_ce_r1; + reg idelay_ce_r2; + reg idelay_inc_r1; + reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */; + reg po_dly_req_r; + wire wrcal_read_req; + wire wrcal_act_req; + wire temp_wrcal_done; + wire tg_timer_done; + wire no_rst_tg_mc; + wire calib_complete; + reg reset_if_r1; + reg reset_if_r2; + reg reset_if_r3; + reg reset_if_r4; + reg reset_if_r5; + reg reset_if_r6; + reg reset_if_r7; + reg reset_if_r8; + reg reset_if_r9; + reg reset_if; + wire phy_if_reset_w; + wire pi_phaselock_start; + + reg dbg_pi_f_inc_r; + reg dbg_pi_f_en_r; + reg dbg_sel_pi_incdec_r; + + reg dbg_po_f_inc_r; + reg dbg_po_f_stg23_sel_r; + reg dbg_po_f_en_r; + reg dbg_sel_po_incdec_r; + + reg tempmon_pi_f_inc_r; + reg tempmon_pi_f_en_r; + reg tempmon_sel_pi_incdec_r; + + reg ck_addr_cmd_delay_done_r1; + reg ck_addr_cmd_delay_done_r2; + reg ck_addr_cmd_delay_done_r3; + reg ck_addr_cmd_delay_done_r4; + reg ck_addr_cmd_delay_done_r5; + reg ck_addr_cmd_delay_done_r6; +// wire oclk_init_delay_start; + wire oclk_prech_req; + wire oclk_calib_resume; + wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt; + wire oclkdelay_calib_start; + wire oclkdelay_calib_done; + wire complex_oclk_prech_req; + wire complex_oclk_calib_resume; + wire complex_oclkdelay_calib_start; + wire complex_oclkdelay_calib_done; + wire complex_ocal_num_samples_inc; + wire complex_ocal_num_samples_done_r; + wire [2:0] complex_ocal_rd_victim_sel; + wire complex_ocal_ref_req; + wire complex_ocal_ref_done; + wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val; + wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val; + + wire wrlvl_final; + wire complex_wrlvl_final; + reg wrlvl_final_mux; + wire wrlvl_final_if_rst; + wire wrlvl_byte_redo; + wire wrlvl_byte_done; + wire early1_data; + wire early2_data; + wire po_stg23_sel; + wire po_stg23_incdec; + wire po_en_stg23; + wire complex_po_stg23_sel; + wire complex_po_stg23_incdec; + wire complex_po_en_stg23; + wire mpr_rdlvl_done; + wire mpr_rdlvl_start; + wire mpr_last_byte_done; + wire mpr_rnk_done; + wire mpr_end_if_reset; + wire mpr_rdlvl_err; + wire rdlvl_err; + wire prbs_rdlvl_start; + wire prbs_rdlvl_done; + wire prbs_rdlvl_done_complex; + reg prbs_rdlvl_done_r1; + wire prbs_last_byte_done; + wire prbs_rdlvl_prech_req; + wire prbs_pi_stg2_f_incdec; + wire prbs_pi_stg2_f_en; + wire complex_sample_cnt_inc; + wire complex_sample_cnt_inc_ocal; + wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt; + wire prbs_gen_clk_en; + wire prbs_gen_oclk_clk_en; + wire rd_data_offset_cal_done; + wire fine_adjust_done; + wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt; + wire ck_po_stg2_f_indec; + wire ck_po_stg2_f_en; + wire dqs_found_prech_req; + wire tempmon_pi_f_inc; + wire tempmon_pi_f_dec; + wire tempmon_sel_pi_incdec; + wire wrcal_sanity_chk; + wire wrcal_sanity_chk_done; + wire wrlvl_done_w; + wire wrlvl_rank_done; + wire done_dqs_tap_inc; + wire [2:0] rd_victim_sel; + wire [2:0] victim_sel; + wire [DQS_CNT_WIDTH:0] victim_byte_cnt; + wire complex_wr_done; + wire complex_victim_inc; + + wire reset_rd_addr; + wire complex_ocal_reset_rd_addr; + + wire oclkdelay_center_calib_start; + wire poc_error; + + wire prbs_ignore_first_byte; + wire prbs_ignore_last_bytes; + + //stg3 tap values + // wire [6*DQS_WIDTH-1:0] oclkdelay_center_val; + + //byte selection + // wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt; + + //INC/DEC for stg3 taps + // wire ocal_ctr_po_stg23_sel; + // wire ocal_ctr_po_stg23_incdec; + // wire ocal_ctr_po_en_stg23; + + //Write resume for DQS toggling + wire oclk_center_write_resume; + wire oclkdelay_center_calib_done; + + //Write request to toggle DQS for limit module + wire lim2init_write_request; + wire lim_done; + + // Bypass complex ocal + wire complex_oclkdelay_calib_start_w; + wire complex_oclkdelay_calib_done_w; + wire [2:0] complex_ocal_rd_victim_sel_w; + wire complex_wrlvl_final_w; + + wire [255:0] dbg_ocd_lim; + + //with MMCM phase detect logic + //wire mmcm_edge_detect_rdy; // ready for MMCM detect + //wire ktap_at_rightedge; // stg3 tap at right edge + //wire ktap_at_leftedge; // stg3 tap at left edge + //wire mmcm_tap_at_center; // indicate stg3 tap at center + //wire mmcm_ps_clkphase_ok; // ps clkphase is OK + //wire mmcm_edge_detect_done; // mmcm edge detect is done + //wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done + //wire reset_mmcm; //mmcm detect logic reset per byte + + // wire [255:0] dbg_phy_oclkdelay_center_cal; + + //PI inc/dec prevention during READ + wire rdlvl_pi_incdec; + wire complex_act_start; + wire complex_pi_incdec_done; + wire num_samples_done_r; + wire complex_init_pi_dec_done; + + wire calib_tap_inc_start; + wire calib_tap_inc_done; + wire calib_tap_end_if_reset; + wire [5:0] calib_tap_inc_byte_cnt; + wire calib_po_f_en; + wire calib_po_f_incdec; + wire calib_po_sel_stg2stg3; + wire calib_po_c_en; + wire calib_po_c_inc; + wire calib_pi_f_en; + wire calib_pi_f_incdec; + wire calib_idelay_ce; + wire calib_idelay_inc; + wire coarse_dec_err; + reg skip_cal_tempmon_samp_en; + wire tempmon_done_skip; + + wire skip_cal_po_pi_dec_done; + reg [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt; + reg [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt; + reg [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt; + reg [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt; + reg [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt; + reg [11:0] calib_device_temp; + wire [127:0] dbg_skip_cal; + + //***************************************************************************** + // Assertions to check correctness of parameter values + //***************************************************************************** + // synthesis translate_off + initial + begin + if (RANKS == 0) begin + $display ("Error: Invalid RANKS parameter. Must be 1 or greater"); + $finish; + end + if (phy_ctl_full == 1'b1) begin + $display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode"); + $finish; + end + end + // synthesis translate_on + + //*************************************************************************** + // Debug + //*************************************************************************** + reg if_empty_reg; + reg pi_stg2_en_reg; + + assign prbs_rdlvl_done = (SIM_CAL_OPTION == "FAST_CAL")? rdlvl_stg1_done : prbs_rdlvl_done_complex; + + assign dbg_pi_phaselock_start = pi_phaselock_start; + assign dbg_pi_dqsfound_start = pi_dqs_found_start; + assign dbg_pi_dqsfound_done = pi_dqs_found_done; + assign dbg_wrcal_start = wrcal_start; + assign dbg_wrcal_done = wrcal_done; + + // Unused for now - use these as needed to bring up lower level signals + //assign dbg_calib_top = dbg_ocd_lim; + assign dbg_calib_top[0] = pi_stg2_en_reg ; + assign dbg_calib_top[1] = if_empty_reg ; + assign dbg_calib_top[3] = coarse_dec_err; + assign dbg_calib_top[4] = calib_tap_inc_start; + assign dbg_calib_top[5] = calib_tap_inc_done; + assign dbg_calib_top[6+:63] = dbg_skip_cal; + + always @ (posedge clk) begin + if_empty_reg <= #TCQ phy_if_empty; + pi_stg2_en_reg <= #TCQ pi_en_stg2_f; + end + + // Write Level and write calibration debug observation ports + assign dbg_wrlvl_start = wrlvl_start; + assign dbg_wrlvl_done = wrlvl_done; + assign dbg_wrlvl_err = wrlvl_err; + + // Read Level debug observation ports + assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start}; + assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done}; + assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err}; + + assign dbg_oclkdelay_calib_done = oclkdelay_calib_done; + assign dbg_oclkdelay_calib_start = oclkdelay_calib_start; + + //*************************************************************************** + // Write leveling dependent signals + //*************************************************************************** + + assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0; + assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1; + assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done : + (po_ck_addr_cmd_delay_done + && pi_fine_dly_dec_done) ; + +generate + if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib + assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start; + assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done; + assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel; + assign complex_wrlvl_final_w = complex_wrlvl_final; + end else begin: bypass_complex_ocal + assign complex_oclkdelay_calib_start_w = 1'b0; + assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done; + assign complex_ocal_rd_victim_sel_w = 'd0; + assign complex_wrlvl_final_w = 1'b0; + end +endgenerate + + + generate + genvar i; + for (i = 0; i <= 2; i = i+1) begin : bankwise_signal + + assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel : + (complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 ) + // (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0)) + ) || calib_po_sel_stg2stg3 || dbg_po_f_stg23_sel_r; + + assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec || + cmd_po_stg2_incdec_ddr2_c || + calib_po_c_inc || + dqs_wl_po_stg2_c_incdec; + + assign po_en_stg2_c[i] = cmd_po_en_stg2_c || + cmd_po_en_stg2_ddr2_c || + calib_po_c_en || + dqs_wl_po_en_stg2_c; + + assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec || + cmd_po_stg2_f_incdec || + ck_po_stg2_f_indec || + po_stg23_incdec || + calib_po_f_incdec || + // complex_po_stg23_incdec || + // ocal_ctr_po_stg23_incdec || + dbg_po_f_inc_r; + + assign po_en_stg2_f[i] = dqs_po_en_stg2_f || + cmd_po_en_stg2_f || + ck_po_stg2_f_en || + po_en_stg23 || + calib_po_f_en || + // complex_po_en_stg23 || + // ocal_ctr_po_en_stg23 || + dbg_po_f_en_r; + + end + endgenerate + + assign pi_stg2_f_incdec = (calib_pi_f_incdec | dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r); + assign pi_en_stg2_f = (calib_pi_f_en | dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r); + + assign idelay_ce = (idelay_ce_r2 | calib_idelay_ce); + assign idelay_inc = (idelay_inc_r2 | calib_idelay_inc); + + assign po_counter_load_en = 1'b0; + + assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt; + assign complex_oclk_calib_resume = oclk_calib_resume; + assign complex_ocal_ref_req = oclk_prech_req; + + +// Added single stage flop to meet timing + always @(posedge clk) begin + if (SKIP_CALIB == "FALSE") + init_calib_complete <= calib_complete; + else + init_calib_complete <= tempmon_done_skip; + end + + assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0; + assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1; + assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2; + + //*************************************************************************** + // Hard PHY signals + //*************************************************************************** + + assign pi_phase_locked_err = phase_locked_err; + assign pi_dqsfound_err = pi_dqs_found_err; + assign wrcal_err = wrcal_pat_err; + assign rst_tg_mc = 1'b0; + +//Restart WRLVL after oclkdealy cal + always @ (posedge clk) + wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final; + + + always @(posedge clk) + phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset | + reset_if | wrlvl_final_if_rst | calib_tap_end_if_reset); + + //*************************************************************************** + // Phaser_IN inc dec control for debug + //*************************************************************************** + + always @(posedge clk) begin + if (rst) begin + dbg_pi_f_inc_r <= #TCQ 1'b0; + dbg_pi_f_en_r <= #TCQ 1'b0; + dbg_sel_pi_incdec_r <= #TCQ 1'b0; + end else begin + dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc; + dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec); + dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec; + end + end + + //*************************************************************************** + // Phaser_OUT inc dec control for debug + //*************************************************************************** + + always @(posedge clk) begin + if (rst) begin + dbg_po_f_inc_r <= #TCQ 1'b0; + dbg_po_f_stg23_sel_r<= #TCQ 1'b0; + dbg_po_f_en_r <= #TCQ 1'b0; + dbg_sel_po_incdec_r <= #TCQ 1'b0; + end else begin + dbg_po_f_inc_r <= #TCQ dbg_po_f_inc; + dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel; + dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec); + dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec; + end + end + + //*************************************************************************** + // Phaser_IN inc dec control for temperature tracking + //*************************************************************************** + + always @(posedge clk) begin + if (rst) begin + tempmon_pi_f_inc_r <= #TCQ 1'b0; + tempmon_pi_f_en_r <= #TCQ 1'b0; + tempmon_sel_pi_incdec_r <= #TCQ 1'b0; + end else begin + tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc; + tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec); + tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec; + end + end + + //*************************************************************************** + // OCLKDELAY calibration signals + //*************************************************************************** + + // Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3 + // and increment/decrement of Phaser_Out stage 3 delay + always @(posedge clk) begin + ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done; + ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1; + ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2; + ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3; + ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4; + ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5; + end + + + + + //*************************************************************************** + // MUX select logic to select current byte undergoing calibration + // Use DQS_CAL_MAP to determine the correlation between the physical + // byte numbering, and the byte numbering within the hard PHY + //*************************************************************************** +generate + if (SKIP_CALIB == "TRUE") begin: gen_byte_sel_skip_calib + always @(posedge clk) begin + if (rst) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else if (~skip_cal_po_pi_dec_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done) begin + ctl_lane_sel <= #TCQ ctl_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~fine_adjust_done && rd_data_offset_cal_done) begin + if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~pi_calib_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~pi_dqs_found_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~calib_tap_inc_done) begin + byte_sel_cnt <= #TCQ calib_tap_inc_byte_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin + byte_sel_cnt <= #TCQ dbg_byte_sel; + calib_in_common <= #TCQ 1'b0; + end else if (tempmon_sel_pi_incdec) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end + end + end else if (tCK >= 2500) begin: gen_byte_sel_div2 // DIV2 change + + always @(posedge clk) begin + if (rst) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done) begin + ctl_lane_sel <= #TCQ ctl_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~fine_adjust_done && rd_data_offset_cal_done) begin + if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~pi_calib_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~pi_dqs_found_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~wrlvl_done_w) begin + if (SIM_CAL_OPTION != "FAST_CAL") begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b0; + end else begin + // Special case for FAST_CAL simulation only to ensure that + // calib_in_common isn't asserted too soon + if (!phy_ctl_rdy_dly) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b1; + end + end + end else if (~mpr_rdlvl_done) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~oclkdelay_calib_done) begin + byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~rdlvl_stg1_done && pi_calib_done) begin + if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin + byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin + byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if ((~wrcal_done) && (DRAM_TYPE == "DDR3")) begin + byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin + byte_sel_cnt <= #TCQ dbg_byte_sel; + calib_in_common <= #TCQ 1'b0; + end else if (tempmon_sel_pi_incdec) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end + end + end else begin: gen_byte_sel_div1 + + always @(posedge clk) begin + if (rst) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~ck_addr_cmd_delay_done) begin + ctl_lane_sel <= #TCQ ctl_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~fine_adjust_done && rd_data_offset_cal_done) begin + if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ 'd0; + ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~pi_calib_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~pi_dqs_found_done) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end else if (~wrlvl_done_w) begin + if (SIM_CAL_OPTION != "FAST_CAL") begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b0; + end else begin + // Special case for FAST_CAL simulation only to ensure that + // calib_in_common isn't asserted too soon + if (!phy_ctl_rdy_dly) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b0; + end else begin + byte_sel_cnt <= #TCQ po_stg2_wl_cnt; + calib_in_common <= #TCQ 1'b1; + end + end + end else if (~mpr_rdlvl_done) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~oclkdelay_calib_done) begin + byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin + byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~rdlvl_stg1_done && pi_calib_done) begin + if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b1; + end else begin + byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end + end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin + byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin + byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; + calib_in_common <= #TCQ 1'b0; + end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin + byte_sel_cnt <= #TCQ dbg_byte_sel; + calib_in_common <= #TCQ 1'b0; + end else if (tempmon_sel_pi_incdec) begin + byte_sel_cnt <= #TCQ 'd0; + calib_in_common <= #TCQ 1'b1; + end + end + + end +endgenerate + + // verilint STARC-2.2.3.3 off + always @(posedge clk) begin + if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin + calib_sel <= #TCQ 6'b000100; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done) || ~skip_cal_po_pi_dec_done) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + if (~dqs_po_dec_done && (WRLVL != "ON")) + //if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON"))) + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; + else + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin + if(WRLVL =="ON") begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2]; + calib_sel[5:3] <= #TCQ CTL_BANK; + if (|pi_rst_stg1_cal) begin + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + end else begin + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; + calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0; + end + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else begin // if (WRLVL =="ON") + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + if(~ck_addr_cmd_delay_done) + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + else + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; + end // else: !if(WRLVL =="ON") + end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") && + rdlvl_assrt_common) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else if (tempmon_sel_pi_incdec) begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + end else begin + calib_sel[2] <= #TCQ 1'b0; + calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; + calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; + calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; + if (~calib_in_common) begin + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; + calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0; + end else + calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; + end + end + // verilint STARC-2.2.3.3 on + // Logic to reset IN_FIFO flags to account for the possibility that + // one or more PHASER_IN's have not correctly found the DQS preamble + // If this happens, we can still complete read leveling, but the # of + // words written into the IN_FIFO's may be an odd #, so that if the + // IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word + // of data left that can only be flushed out by reseting the IN_FIFO + always @(posedge clk) begin + rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; + prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; + reset_if_r1 <= #TCQ reset_if; + reset_if_r2 <= #TCQ reset_if_r1; + reset_if_r3 <= #TCQ reset_if_r2; + reset_if_r4 <= #TCQ reset_if_r3; + reset_if_r5 <= #TCQ reset_if_r4; + reset_if_r6 <= #TCQ reset_if_r5; + reset_if_r7 <= #TCQ reset_if_r6; + reset_if_r8 <= #TCQ reset_if_r7; + reset_if_r9 <= #TCQ reset_if_r8; + end + + always @(posedge clk) begin + if (rst || reset_if_r9) + reset_if <= #TCQ 1'b0; + else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || + (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + reset_if <= #TCQ 1'b1; + end + + assign phy_if_empty_def = 1'b0; + + // DQ IDELAY tap inc and ce signals registered to control calib_in_common + // signal during read leveling in FAST_CAL mode. The calib_in_common signal + // is only asserted for IDELAY tap increments not Phaser_IN tap increments + // in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load + // inputs are used. + always @(posedge clk) begin + if (rst) begin + idelay_ce_r1 <= #TCQ 1'b0; + idelay_ce_r2 <= #TCQ 1'b0; + idelay_inc_r1 <= #TCQ 1'b0; + idelay_inc_r2 <= #TCQ 1'b0; + end else begin + idelay_ce_r1 <= #TCQ idelay_ce_int; + idelay_ce_r2 <= #TCQ idelay_ce_r1; + idelay_inc_r1 <= #TCQ idelay_inc_int; + idelay_inc_r2 <= #TCQ idelay_inc_r1; + end + end + + //*************************************************************************** + // Delay all Outputs using Phaser_Out fine taps + //*************************************************************************** + + assign init_wrcal_complete = 1'b0; + + //*************************************************************************** + // PRBS Generator for Read Leveling Stage 1 - read window detection and + // DQS Centering + //*************************************************************************** + + // Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat + assign prbs_seed = 64'h9966aa559966aa55; + + // A single PRBS generator + // writes 64-bits every 4to1 fabric clock cycle and + // write 32-bits every 2to1 fabric clock cycle + // used for complex read leveling and complex oclkdealy calib + mig_7series_v4_2_ddr_prbs_gen # + ( + .TCQ (TCQ), + .PRBS_WIDTH (2*8*nCK_PER_CLK), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .VCCO_PAT_EN (VCCO_PAT_EN), + .VCCAUX_PAT_EN (VCCAUX_PAT_EN), + .ISI_PAT_EN (ISI_PAT_EN), + .FIXED_VICTIM (FIXED_VICTIM) + ) + u_ddr_prbs_gen + (.prbs_ignore_first_byte (prbs_ignore_first_byte), + .prbs_ignore_last_bytes (prbs_ignore_last_bytes), + .clk_i (clk), + .clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en), + .rst_i (rst), + .prbs_o (prbs_out), + .prbs_seed_i (prbs_seed), + .phy_if_empty (phy_if_empty), + .prbs_rdlvl_start (prbs_rdlvl_start), + .prbs_rdlvl_done (prbs_rdlvl_done), + .complex_wr_done (complex_wr_done), + .victim_sel (victim_sel), + .byte_cnt (victim_byte_cnt), + .dbg_prbs_gen (), + .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr) + ); + + +// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1, +// Rise2, Fall2, Rise3, Fall3 data + generate + if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign prbs_o = prbs_out; + /*assign prbs_rise0 = prbs_out[7:0]; + assign prbs_fall0 = prbs_out[15:8]; + assign prbs_rise1 = prbs_out[23:16]; + assign prbs_fall1 = prbs_out[31:24]; + assign prbs_rise2 = prbs_out[39:32]; + assign prbs_fall2 = prbs_out[47:40]; + assign prbs_rise3 = prbs_out[55:48]; + assign prbs_fall3 = prbs_out[63:56]; + assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2, + prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ + end else begin :gen_ck_per_clk2 + assign prbs_o = prbs_out[4*DQ_WIDTH-1:0]; + /*assign prbs_rise0 = prbs_out[7:0]; + assign prbs_fall0 = prbs_out[15:8]; + assign prbs_rise1 = prbs_out[23:16]; + assign prbs_fall1 = prbs_out[31:24]; + assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ + end + endgenerate + + + //*************************************************************************** + // Initialization / Master PHY state logic (overall control during memory + // init, timing leveling) + //*************************************************************************** + + mig_7series_v4_2_ddr_phy_init # + ( + .tCK (tCK), + .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .DRAM_TYPE (DRAM_TYPE), + .PRBS_WIDTH (PRBS_WIDTH), + .BANK_WIDTH (BANK_WIDTH), + .CA_MIRROR (CA_MIRROR), + .COL_WIDTH (COL_WIDTH), + .nCS_PER_RANK (nCS_PER_RANK), + .DQ_WIDTH (DQ_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .CS_WIDTH (CS_WIDTH), + .RANKS (RANKS), + .CKE_WIDTH (CKE_WIDTH), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .AL (AL), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .nCL (nCL), + .nCWL (nCWL), + .tRFC (tRFC), + .REFRESH_TIMER (REFRESH_TIMER), + .REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH), + .OUTPUT_DRV (OUTPUT_DRV), + .REG_CTRL (REG_CTRL), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .WRLVL (WRLVL), + .USE_ODT_PORT (USE_ODT_PORT), + .DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE), + .nSLOTS (nSLOTS), + .SIM_INIT_OPTION (SIM_INIT_OPTION), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .CKE_ODT_AUX (CKE_ODT_AUX), + .PRE_REV3ES (PRE_REV3ES), + .TEST_AL (TEST_AL), + .FIXED_VICTIM (FIXED_VICTIM), + .BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL), + .SKIP_CALIB (SKIP_CALIB) + ) + u_ddr_phy_init + ( + .clk (clk), + .rst (rst), + .prbs_o (prbs_o), + .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), + .delay_incdec_done (ck_addr_cmd_delay_done), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_phaselock_start (pi_phaselock_start), + .pi_phase_locked_err (phase_locked_err), + .pi_calib_done (pi_calib_done), + .phy_if_empty (phy_if_empty), + .phy_ctl_ready (phy_ctl_ready), + .phy_ctl_full (phy_ctl_full), + .phy_cmd_full (phy_cmd_full), + .phy_data_full (phy_data_full), + .calib_ctl_wren (calib_ctl_wren), + .calib_cmd_wren (calib_cmd_wren), + .calib_wrdata_en (calib_wrdata_en), + .calib_seq (calib_seq), + .calib_aux_out (calib_aux_out), + .calib_rank_cnt (calib_rank_cnt), + .calib_cas_slot (calib_cas_slot), + .calib_data_offset_0 (calib_data_offset_0), + .calib_data_offset_1 (calib_data_offset_1), + .calib_data_offset_2 (calib_data_offset_2), + .calib_cmd (calib_cmd), + .calib_cke (calib_cke), + .calib_odt (calib_odt), + .write_calib (write_calib), + .read_calib (read_calib), + .wrlvl_done (wrlvl_done), + .wrlvl_rank_done (wrlvl_rank_done), + .wrlvl_byte_done (wrlvl_byte_done), + .wrlvl_byte_redo (wrlvl_byte_redo), + .wrlvl_final (wrlvl_final_mux), + .wrlvl_final_if_rst (wrlvl_final_if_rst), + .oclkdelay_calib_start (oclkdelay_calib_start), + .oclkdelay_calib_done (oclkdelay_calib_done), + .oclk_prech_req (oclk_prech_req), + .oclk_calib_resume (oclk_calib_resume), + .lim_wr_req (lim2init_write_request), + .lim_done (lim_done), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w), + .complex_oclk_calib_resume (complex_oclk_calib_resume), + .complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt), + .complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal), + .complex_ocal_num_samples_inc (complex_ocal_num_samples_inc), + .complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r), + .complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr), + .complex_ocal_ref_req (complex_ocal_ref_req), + .complex_ocal_ref_done (complex_ocal_ref_done), + .done_dqs_tap_inc (done_dqs_tap_inc), + .wl_sm_start (wl_sm_start), + .wr_lvl_start (wrlvl_start), + .slot_0_present (slot_0_present), + .slot_1_present (slot_1_present), + .mpr_rdlvl_done (mpr_rdlvl_done), + .mpr_rdlvl_start (mpr_rdlvl_start), + .mpr_last_byte_done (mpr_last_byte_done), + .mpr_rnk_done (mpr_rnk_done), + .mpr_end_if_reset (mpr_end_if_reset), + .rdlvl_stg1_done (rdlvl_stg1_done), + .rdlvl_stg1_rank_done (rdlvl_stg1_rank_done), + .rdlvl_stg1_start (rdlvl_stg1_start), + .rdlvl_prech_req (rdlvl_prech_req), + .rdlvl_last_byte_done (rdlvl_last_byte_done), + .prbs_rdlvl_start (prbs_rdlvl_start), + .complex_wr_done (complex_wr_done), + .prbs_rdlvl_done (prbs_rdlvl_done), + .prbs_last_byte_done (prbs_last_byte_done), + .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), + .complex_victim_inc (complex_victim_inc), + .rd_victim_sel (rd_victim_sel), + .complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel), + .pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt), + .victim_sel (victim_sel), + .victim_byte_cnt (victim_byte_cnt), + .prbs_gen_clk_en (prbs_gen_clk_en), + .prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en), + .complex_sample_cnt_inc(complex_sample_cnt_inc), + .pi_dqs_found_start (pi_dqs_found_start), + .dqsfound_retry (dqsfound_retry), + .dqs_found_prech_req (dqs_found_prech_req), + .pi_dqs_found_rank_done(pi_dqs_found_rank_done), + .pi_dqs_found_done (pi_dqs_found_done), + .detect_pi_found_dqs (detect_pi_found_dqs), + .rd_data_offset_0 (rd_data_offset_0), + .rd_data_offset_1 (rd_data_offset_1), + .rd_data_offset_2 (rd_data_offset_2), + .rd_data_offset_ranks_0(rd_data_offset_ranks_0), + .rd_data_offset_ranks_1(rd_data_offset_ranks_1), + .rd_data_offset_ranks_2(rd_data_offset_ranks_2), + .wrcal_start (wrcal_start), + .wrcal_rd_wait (wrcal_rd_wait), + .wrcal_prech_req (wrcal_prech_req), + .wrcal_resume (wrcal_resume_w), + .wrcal_read_req (wrcal_read_req), + .wrcal_act_req (wrcal_act_req), + .wrcal_sanity_chk (wrcal_sanity_chk), + .temp_wrcal_done (temp_wrcal_done), + .wrcal_sanity_chk_done (wrcal_sanity_chk_done), + .tg_timer_done (tg_timer_done), + .no_rst_tg_mc (no_rst_tg_mc), + .wrcal_done (wrcal_done), + .prech_done (prech_done), + .calib_writes (calib_writes), + .init_calib_complete (calib_complete), + .phy_address (phy_address), + .phy_bank (phy_bank), + .phy_cas_n (phy_cas_n), + .phy_cs_n (phy_cs_n), + .phy_ras_n (phy_ras_n), + .phy_reset_n (phy_reset_n), + .phy_we_n (phy_we_n), + .phy_wrdata (phy_wrdata), + .phy_rddata_en (phy_rddata_en), + .phy_rddata_valid (phy_rddata_valid), + .dbg_phy_init (dbg_phy_init), + .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr), + .oclkdelay_center_calib_start (oclkdelay_center_calib_start), + .oclk_center_write_resume (oclk_center_write_resume), + .oclkdelay_center_calib_done (oclkdelay_center_calib_done), + .rdlvl_pi_incdec (rdlvl_pi_incdec), + .complex_act_start (complex_act_start), + .complex_pi_incdec_done (complex_pi_incdec_done), + .complex_init_pi_dec_done (complex_init_pi_dec_done), + .num_samples_done_r (num_samples_done_r), + .calib_tap_inc_start (calib_tap_inc_start), + .calib_tap_end_if_reset (calib_tap_end_if_reset), + .calib_tap_inc_done (calib_tap_inc_done) + ); + + + //***************************************************************** + // Write Calibration + //***************************************************************** + + mig_7series_v4_2_ddr_phy_wrcal # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .SIM_CAL_OPTION (SIM_CAL_OPTION) + ) + u_ddr_phy_wrcal + ( + .clk (clk), + .rst (rst), + .wrcal_start (wrcal_start), + .wrcal_rd_wait (wrcal_rd_wait), + .wrcal_sanity_chk (wrcal_sanity_chk), + .dqsfound_retry_done (pi_dqs_found_done), + .dqsfound_retry (dqsfound_retry), + .wrcal_read_req (wrcal_read_req), + .wrcal_act_req (wrcal_act_req), + .phy_rddata_en (phy_rddata_en), + .wrcal_done (wrcal_done), + .wrcal_pat_err (wrcal_pat_err), + .wrcal_prech_req (wrcal_prech_req), + .temp_wrcal_done (temp_wrcal_done), + .wrcal_sanity_chk_done (wrcal_sanity_chk_done), + .prech_done (prech_done), + .rd_data (phy_rddata), + .wrcal_pat_resume (wrcal_pat_resume), + .po_stg2_wrcal_cnt (po_stg2_wrcal_cnt), + .phy_if_reset (phy_if_reset_w), + .wl_po_coarse_cnt (wl_po_coarse_cnt), + .wl_po_fine_cnt (wl_po_fine_cnt), + .wrlvl_byte_redo (wrlvl_byte_redo), + .wrlvl_byte_done (wrlvl_byte_done), + .early1_data (early1_data), + .early2_data (early2_data), + .idelay_ld (idelay_ld), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt) + ); + + + + //*************************************************************************** + // Write-leveling calibration logic + //*************************************************************************** + + generate + if ((WRLVL == "ON") && (SKIP_CALIB == "FALSE")) begin: mb_wrlvl_inst + + mig_7series_v4_2_ddr_phy_wrlvl # + ( + .TCQ (TCQ), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .RANKS (1), + .CLK_PERIOD (CLK_PERIOD), + .nCK_PER_CLK (nCK_PER_CLK), + .SIM_CAL_OPTION (SIM_CAL_OPTION) + ) + u_ddr_phy_wrlvl + ( + .clk (clk), + .rst (rst), + .phy_ctl_ready (phy_ctl_ready), + .wr_level_start (wrlvl_start), + .wl_sm_start (wl_sm_start), + .wrlvl_byte_redo (wrlvl_byte_redo), + .wrcal_cnt (po_stg2_wrcal_cnt), + .early1_data (early1_data), + .early2_data (early2_data), + .wrlvl_final (wrlvl_final_mux), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt), + .wrlvl_byte_done (wrlvl_byte_done), + .oclkdelay_calib_done (oclkdelay_calib_done), + .rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]), + .dqs_po_dec_done (dqs_po_dec_done), + .phy_ctl_rdy_dly (phy_ctl_rdy_dly), + .wr_level_done (wrlvl_done), + .wrlvl_rank_done (wrlvl_rank_done), + .done_dqs_tap_inc (done_dqs_tap_inc), + .dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec), + .dqs_po_en_stg2_f (dqs_po_en_stg2_f), + .dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec), + .dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c), + .po_counter_read_val (po_counter_read_val), + .po_stg2_wl_cnt (po_stg2_wl_cnt), + .wrlvl_err (wrlvl_err), + .wl_po_coarse_cnt (wl_po_coarse_cnt), + .wl_po_fine_cnt (wl_po_fine_cnt), + .dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_dqs_count (), + .dbg_wl_state (), + .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), + .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), + .dbg_phy_wrlvl (dbg_phy_wrlvl) + ); + + + mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay # + ( + .TCQ (TCQ), + .tCK (tCK), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .N_CTL_LANES (N_CTL_LANES), + .SIM_CAL_OPTION(SIM_CAL_OPTION) + ) + u_ddr_phy_ck_addr_cmd_delay + ( + .clk (clk), + .rst (rst), + .cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done), + .ctl_lane_cnt (ctl_lane_cnt), + .po_stg2_f_incdec (cmd_po_stg2_f_incdec), + .po_en_stg2_f (cmd_po_en_stg2_f), + .po_stg2_c_incdec (cmd_po_stg2_c_incdec), + .po_en_stg2_c (cmd_po_en_stg2_c), + .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) + ); + + assign cmd_po_stg2_incdec_ddr2_c = 1'b0; + assign cmd_po_en_stg2_ddr2_c = 1'b0; + + end else if ((WRLVL == "ON") && (SKIP_CALIB == "TRUE")) begin: wrlvl_on_skip_calib + + mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay # + ( + .TCQ (TCQ), + .tCK (tCK), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .N_CTL_LANES (N_CTL_LANES), + .SIM_CAL_OPTION(SIM_CAL_OPTION) + ) + u_ddr_phy_ck_addr_cmd_delay + ( + .clk (clk), + .rst (rst), + .cmd_delay_start (skip_cal_po_pi_dec_done), + .ctl_lane_cnt (ctl_lane_cnt), + .po_stg2_f_incdec (cmd_po_stg2_f_incdec), + .po_en_stg2_f (cmd_po_en_stg2_f), + .po_stg2_c_incdec (cmd_po_stg2_c_incdec), + .po_en_stg2_c (cmd_po_en_stg2_c), + .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) + ); + + assign dqs_po_dec_done = 1'b1; + assign wrlvl_byte_done = 1'b1; + assign wrlvl_rank_done = 1'b1; + assign phy_ctl_rdy_dly = 1'b1; + assign done_dqs_tap_inc = 1'b1; + assign po_stg2_wl_cnt = 'h0; + assign wl_po_coarse_cnt = 'h0; + assign wl_po_fine_cnt = 'h0; + assign dbg_tap_cnt_during_wrlvl = 'h0; + assign dbg_wl_edge_detect_valid = 'h0; + assign dbg_rd_data_edge_detect = 'h0; + assign dbg_wrlvl_fine_tap_cnt = 'h0; + assign dbg_wrlvl_coarse_tap_cnt = 'h0; + assign dbg_phy_wrlvl = 'h0; + + assign wrlvl_done = 1'b1; + assign wrlvl_err = 1'b0; + assign dqs_po_stg2_f_incdec = 1'b0; + assign dqs_po_en_stg2_f = 1'b0; + assign dqs_wl_po_en_stg2_c = 1'b0; + assign dqs_wl_po_stg2_c_incdec = 1'b0; + + assign cmd_po_stg2_incdec_ddr2_c = 1'b0; + assign cmd_po_en_stg2_ddr2_c = 1'b0; + + end else begin: mb_wrlvl_off + + mig_7series_v4_2_ddr_phy_wrlvl_off_delay # + ( + .TCQ (TCQ), + .tCK (tCK), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .PO_INITIAL_DLY(60), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .N_CTL_LANES (N_CTL_LANES) + ) + u_phy_wrlvl_off_delay + ( + .clk (clk), + .rst (rst), + .pi_fine_dly_dec_done (pi_fine_dly_dec_done), + .cmd_delay_start (phy_ctl_ready), + .ctl_lane_cnt (ctl_lane_cnt), + .po_s2_incdec_f (cmd_po_stg2_f_incdec), + .po_en_s2_f (cmd_po_en_stg2_f), + .po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c), + .po_en_s2_c (cmd_po_en_stg2_ddr2_c), + .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done), + .po_dec_done (dqs_po_dec_done), + .phy_ctl_rdy_dly (phy_ctl_rdy_dly) + ); + + assign wrlvl_byte_done = 1'b1; + assign wrlvl_rank_done = 1'b1; + assign po_stg2_wl_cnt = 'h0; + assign wl_po_coarse_cnt = 'h0; + assign wl_po_fine_cnt = 'h0; + assign dbg_tap_cnt_during_wrlvl = 'h0; + assign dbg_wl_edge_detect_valid = 'h0; + assign dbg_rd_data_edge_detect = 'h0; + assign dbg_wrlvl_fine_tap_cnt = 'h0; + assign dbg_wrlvl_coarse_tap_cnt = 'h0; + assign dbg_phy_wrlvl = 'h0; + + assign wrlvl_done = 1'b1; + assign wrlvl_err = 1'b0; + assign dqs_po_stg2_f_incdec = 1'b0; + assign dqs_po_en_stg2_f = 1'b0; + assign dqs_wl_po_en_stg2_c = 1'b0; + assign cmd_po_stg2_c_incdec = 1'b0; + assign dqs_wl_po_stg2_c_incdec = 1'b0; + assign cmd_po_en_stg2_c = 1'b0; + + end + endgenerate + + generate + if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib + + localparam SAMPCNTRWIDTH = 17; + localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 512 : 4; //MG from 2048 + localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK); + localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10; + localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 512 : 1; //MG from 2048 + localparam POC_PCT_SAMPS_SOLID = 80; + localparam SCAN_PCT_SAMPS_SOLID = 95; + + mig_7series_v4_2_ddr_phy_oclkdelay_cal # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + //.DRAM_TYPE (DRAM_TYPE), + .DRAM_WIDTH (DRAM_WIDTH), + //.OCAL_EN (OCAL_EN), + .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), + .PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SAMPLES (SAMPLES), + .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL) + //.tCK (tCK) + ) + u_ddr_phy_oclkdelay_cal + (/*AUTOINST*/ + // Outputs + .prbs_ignore_first_byte (prbs_ignore_first_byte), + .prbs_ignore_last_bytes (prbs_ignore_last_bytes), + .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), + .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]), + .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]), + .lim2init_write_request (lim2init_write_request), + .lim_done (lim_done), + .oclk_calib_resume (oclk_calib_resume), + .oclk_prech_req (oclk_prech_req), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_calib_done (oclkdelay_calib_done), + .po_en_stg23 (po_en_stg23), + .po_stg23_incdec (po_stg23_incdec), + .po_stg23_sel (po_stg23_sel), + .psen (psen), + .psincdec (psincdec), + .wrlvl_final (wrlvl_final), + .rd_victim_sel (complex_ocal_rd_victim_sel), + .ocal_num_samples_done_r (complex_ocal_num_samples_done_r), + .complex_wrlvl_final (complex_wrlvl_final), + .poc_error (poc_error), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w), + .metaQ (pd_out), + //.oclk_init_delay_start (oclk_init_delay_start), + .po_counter_read_val (po_counter_read_val), + .oclkdelay_calib_start (oclkdelay_calib_start), + .oclkdelay_init_val (oclkdelay_init_val[5:0]), + .poc_sample_pd (poc_sample_pd), + .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .phy_rddata_en (phy_rddata_en), + .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .prech_done (prech_done), + .psdone (psdone), + .rst (rst), + .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]), + .ocal_num_samples_inc (complex_ocal_num_samples_inc), + .oclkdelay_center_calib_start (oclkdelay_center_calib_start), + .oclk_center_write_resume (oclk_center_write_resume), + .oclkdelay_center_calib_done (oclkdelay_center_calib_done), + .dbg_ocd_lim (dbg_ocd_lim), + .dbg_poc (dbg_poc[1023:0]) ); + + end else begin : oclk_calib_disabled + + assign wrlvl_final = 'b0; + assign psen = 'b0; + assign psincdec = 'b0; + assign po_stg23_sel = 'b0; + assign po_stg23_incdec = 'b0; + assign po_en_stg23 = 'b0; + assign oclkdelay_calib_cnt = 'b0; + assign oclk_prech_req = 'b0; + assign oclk_calib_resume = 'b0; + assign oclkdelay_calib_done = 1'b1; + assign dbg_phy_oclkdelay_cal = 'h0; + assign dbg_oclkdelay_rd_data = 'h0; + + end + endgenerate + //*************************************************************************** + // Read data-offset calibration required for Phaser_In + //*************************************************************************** + + generate + if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right + mig_7series_v4_2_ddr_phy_dqs_found_cal # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .nCL (nCL), + .AL (AL), + .nCWL (nCWL), + //.RANKS (RANKS), + .RANKS (1), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .REG_CTRL (REG_CTRL), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DRAM_TYPE (DRAM_TYPE), + .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), + .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), + .HIGHEST_LANE (HIGHEST_LANE), + .HIGHEST_BANK (HIGHEST_BANK), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4) + ) + u_ddr_phy_dqs_found_cal + ( + .clk (clk), + .rst (rst), + .pi_dqs_found_start (pi_dqs_found_start), + .dqsfound_retry (dqsfound_retry), + .detect_pi_found_dqs (detect_pi_found_dqs), + .prech_done (prech_done), + .pi_dqs_found_lanes (pi_dqs_found_lanes), + .pi_rst_stg1_cal (pi_rst_stg1_cal), + .rd_data_offset_0 (rd_data_offset_0), + .rd_data_offset_1 (rd_data_offset_1), + .rd_data_offset_2 (rd_data_offset_2), + .pi_dqs_found_rank_done (pi_dqs_found_rank_done), + .pi_dqs_found_done (pi_dqs_found_done), + .dqsfound_retry_done (dqsfound_retry_done), + .dqs_found_prech_req (dqs_found_prech_req), + .pi_dqs_found_err (pi_dqs_found_err), + .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), + .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), + .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), + .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), + .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), + .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), + .po_counter_read_val (po_counter_read_val), + .rd_data_offset_cal_done (rd_data_offset_cal_done), + .fine_adjust_done (fine_adjust_done), + .fine_adjust_lane_cnt (fine_adjust_lane_cnt), + .ck_po_stg2_f_indec (ck_po_stg2_f_indec), + .ck_po_stg2_f_en (ck_po_stg2_f_en), + .dbg_dqs_found_cal (dbg_dqs_found_cal) + ); + end else begin: dqsfind_calib_left + mig_7series_v4_2_ddr_phy_dqs_found_cal_hr # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .nCL (nCL), + .AL (AL), + .nCWL (nCWL), + //.RANKS (RANKS), + .RANKS (1), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .REG_CTRL (REG_CTRL), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DRAM_TYPE (DRAM_TYPE), + .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), + .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), + .HIGHEST_LANE (HIGHEST_LANE), + .HIGHEST_BANK (HIGHEST_BANK), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4) + ) + u_ddr_phy_dqs_found_cal_hr + ( + .clk (clk), + .rst (rst), + .pi_dqs_found_start (pi_dqs_found_start), + .dqsfound_retry (dqsfound_retry), + .detect_pi_found_dqs (detect_pi_found_dqs), + .prech_done (prech_done), + .pi_dqs_found_lanes (pi_dqs_found_lanes), + .pi_rst_stg1_cal (pi_rst_stg1_cal), + .rd_data_offset_0 (rd_data_offset_0), + .rd_data_offset_1 (rd_data_offset_1), + .rd_data_offset_2 (rd_data_offset_2), + .pi_dqs_found_rank_done (pi_dqs_found_rank_done), + .pi_dqs_found_done (pi_dqs_found_done), + .dqsfound_retry_done (dqsfound_retry_done), + .dqs_found_prech_req (dqs_found_prech_req), + .pi_dqs_found_err (pi_dqs_found_err), + .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), + .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), + .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), + .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), + .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), + .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), + .po_counter_read_val (po_counter_read_val), + .rd_data_offset_cal_done (rd_data_offset_cal_done), + .fine_adjust_done (fine_adjust_done), + .fine_adjust_lane_cnt (fine_adjust_lane_cnt), + .ck_po_stg2_f_indec (ck_po_stg2_f_indec), + .ck_po_stg2_f_en (ck_po_stg2_f_en), + .dbg_dqs_found_cal (dbg_dqs_found_cal) + ); + end + endgenerate + + //*************************************************************************** + // Read-leveling calibration logic + //*************************************************************************** +generate +if (SKIP_CALIB == "FALSE") begin:ddr_phy_rdlvl_gen + mig_7series_v4_2_ddr_phy_rdlvl # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .CLK_PERIOD (CLK_PERIOD), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .RANKS (1), + .PER_BIT_DESKEW (PER_BIT_DESKEW), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DEBUG_PORT (DEBUG_PORT), + .DRAM_TYPE (DRAM_TYPE), + .OCAL_EN (OCAL_EN), + .IDELAY_ADJ (IDELAY_ADJ), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_phy_rdlvl + ( + .clk (clk), + .rst (rst), + .mpr_rdlvl_done (mpr_rdlvl_done), + .mpr_rdlvl_start (mpr_rdlvl_start), + .mpr_last_byte_done (mpr_last_byte_done), + .mpr_rnk_done (mpr_rnk_done), + .rdlvl_stg1_start (rdlvl_stg1_start), + .rdlvl_stg1_done (rdlvl_stg1_done), + .rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done), + .rdlvl_stg1_err (rdlvl_stg1_err), + .mpr_rdlvl_err (mpr_rdlvl_err), + .rdlvl_err (rdlvl_err), + .rdlvl_prech_req (rdlvl_prech_req), + .rdlvl_last_byte_done (rdlvl_last_byte_done), + .rdlvl_assrt_common (rdlvl_assrt_common), + .prech_done (prech_done), + .phy_if_empty (phy_if_empty), + .idelaye2_init_val (idelaye2_init_val), + .rd_data (phy_rddata), + .pi_en_stg2_f (rdlvl_pi_stg2_f_en), + .pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec), + .pi_stg2_load (pi_stg2_load), + .pi_stg2_reg_l (pi_stg2_reg_l), + .dqs_po_dec_done (dqs_po_dec_done), + .pi_counter_read_val (pi_counter_read_val), + .pi_fine_dly_dec_done (pi_fine_dly_dec_done), + .idelay_ce (idelay_ce_int), + .idelay_inc (idelay_inc_int), + .idelay_ld (idelay_ld), + .wrcal_cnt (po_stg2_wrcal_cnt), + .pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt), + .dlyval_dq (dlyval_dq), + .rdlvl_pi_incdec (rdlvl_pi_incdec), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), + .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), + .dbg_phy_rdlvl (dbg_phy_rdlvl) + ); +end else begin:ddr_phy_rdlvl_off + + assign mpr_rdlvl_done = 1'b1; + assign mpr_last_byte_done = 1'b1; + assign mpr_rnk_done = 1'b1; + assign rdlvl_stg1_done = 1'b1; + assign rdlvl_stg1_rank_done = 1'b1; + assign rdlvl_last_byte_done = 1'b1; + assign pi_fine_dly_dec_done = 1'b1; + assign rdlvl_prech_req = 1'b0; + assign rdlvl_stg1_err = 1'b0; + assign mpr_rdlvl_err = 1'b0; + assign rdlvl_err = 1'b0; + assign rdlvl_assrt_common = 1'b0; + assign rdlvl_pi_stg2_f_en = 1'b0; + assign rdlvl_pi_stg2_f_incdec = 1'b0; + assign pi_stg2_rdlvl_cnt = 'h0; + assign idelay_ce_int = 1'b0; + assign idelay_inc_int = 1'b0; + assign rdlvl_pi_incdec = 1'b0; + assign dbg_phy_rdlvl = 'h0; + assign dbg_cpt_first_edge_cnt = 'h0; + assign dbg_cpt_second_edge_cnt = 'h0; + assign dbg_cpt_tap_cnt = 'h0; + assign dbg_dq_idelay_tap_cnt = 'h0; + +end +endgenerate + +generate +if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen + mig_7series_v4_2_ddr_phy_prbs_rdlvl # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .RANKS (1), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .PRBS_WIDTH (PRBS_WIDTH), + .FIXED_VICTIM (FIXED_VICTIM), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ) + ) + u_ddr_phy_prbs_rdlvl + ( + .clk (clk), + .rst (rst), + .prbs_rdlvl_start (prbs_rdlvl_start), + .prbs_rdlvl_done (prbs_rdlvl_done_complex), + .prbs_last_byte_done (prbs_last_byte_done), + .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), + .complex_sample_cnt_inc (complex_sample_cnt_inc), + .prech_done (prech_done), + .phy_if_empty (phy_if_empty), + .rd_data (phy_rddata), + .compare_data (prbs_o), + .pi_counter_read_val (pi_counter_read_val), + .pi_en_stg2_f (prbs_pi_stg2_f_en), + .pi_stg2_f_incdec (prbs_pi_stg2_f_incdec), + .dbg_prbs_rdlvl (dbg_prbs_rdlvl), + .pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt), + .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), + .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), + .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), + .rd_victim_sel (rd_victim_sel), + .complex_victim_inc (complex_victim_inc), + .reset_rd_addr (reset_rd_addr), + .fine_delay_incdec_pb (fine_delay_incdec_pb), + .fine_delay_sel (fine_delay_sel), + .complex_act_start (complex_act_start), + .num_samples_done_r (num_samples_done_r), + .complex_pi_incdec_done (complex_pi_incdec_done), + .complex_init_pi_dec_done (complex_init_pi_dec_done) + ); +end else begin:ddr_phy_prbs_rdlvl_off + + assign prbs_rdlvl_done_complex = rdlvl_stg1_done ; + //assign prbs_last_byte_done = rdlvl_stg1_rank_done ; + assign prbs_last_byte_done = rdlvl_stg1_done; + assign reset_rd_addr = 1'b0; + assign prbs_rdlvl_prech_req = 1'b0 ; + assign prbs_pi_stg2_f_en = 1'b0 ; + assign prbs_pi_stg2_f_incdec = 1'b0 ; + assign pi_stg2_prbs_rdlvl_cnt = 'b0 ; + assign dbg_prbs_rdlvl = 'h0 ; + assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}}; + assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; + assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; + assign complex_pi_incdec_done = 'b0; + assign complex_init_pi_dec_done = 'b1; + assign num_samples_done_r = 'b0; +end +endgenerate + + //*************************************************************************** + // Inc/Dec Phaser_Out, Phaser_In, and IDELAY taps to match calibration values + //*************************************************************************** + + generate + if (SKIP_CALIB == "TRUE") begin: gen_skip_calib_tap + + // Generate request to get calibration tap values per byte + always @(posedge clk) begin + if (rst) + calib_tap_req <= #TCQ 1'b0; + else if (phy_ctl_ready) + calib_tap_req <= #TCQ 1'b1; + end + + + // Store calibration values to registers + always @(posedge clk) begin + if (rst) begin + calib_po_coarse_tap_cnt <= #TCQ 'd0; + calib_po_stage3_tap_cnt <= #TCQ 'd0; + calib_po_stage2_tap_cnt <= #TCQ 'd0; + calib_pi_stage2_tap_cnt <= #TCQ 'd0; + calib_idelay_tap_cnt <= #TCQ 'd0; + calib_device_temp <= #TCQ 'd0; + end else if (calib_tap_load) begin + case (calib_tap_addr[2:0]) + 3'b000: + calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0]; + 3'b001: + calib_po_stage3_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; + 3'b010: + calib_po_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; + 3'b011: + calib_pi_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0]; + 3'b100: + calib_idelay_tap_cnt[5*calib_tap_addr[6:3]+:5] <= #TCQ calib_tap_val[4:0]; + 3'b110: + if (&calib_tap_addr[6:3]) + calib_device_temp[7:0] <= #TCQ calib_tap_val[7:0]; + 3'b111: + if (&calib_tap_addr[6:3]) + calib_device_temp[11:8] <= #TCQ calib_tap_val[3:0]; + default: + calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0]; + endcase + end + end + + + mig_7series_v4_2_ddr_skip_calib_tap # + ( + .TCQ (TCQ), + .DQS_WIDTH (DQS_WIDTH) + ) + u_ddr_skip_calib_tap + ( + .rst (rst), + .clk (clk), + .phy_ctl_ready (phy_ctl_ready), + .load_done (calib_tap_load_done), + .calib_tap_inc_start (calib_tap_inc_start), + .calib_tap_inc_done (calib_tap_inc_done), + .calib_tap_inc_byte_cnt (calib_tap_inc_byte_cnt), + .calib_po_stage2_tap_cnt (calib_po_stage2_tap_cnt), + .calib_po_stage3_tap_cnt (calib_po_stage3_tap_cnt), + .calib_po_coarse_tap_cnt (calib_po_coarse_tap_cnt), + .calib_pi_stage2_tap_cnt (calib_pi_stage2_tap_cnt), + .calib_idelay_tap_cnt (calib_idelay_tap_cnt), + .po_counter_read_val (po_counter_read_val), + .pi_counter_read_val (pi_counter_read_val), + .calib_po_f_en (calib_po_f_en), + .calib_po_f_incdec (calib_po_f_incdec), + .calib_po_sel_stg2stg3 (calib_po_sel_stg2stg3), + .calib_po_c_en (calib_po_c_en), + .calib_po_c_inc (calib_po_c_inc), + .calib_pi_f_en (calib_pi_f_en), + .calib_pi_f_incdec (calib_pi_f_incdec), + .calib_idelay_ce (calib_idelay_ce), + .calib_idelay_inc (calib_idelay_inc), + .skip_cal_po_pi_dec_done (skip_cal_po_pi_dec_done), + .coarse_dec_err (coarse_dec_err), + .dbg_skip_cal (dbg_skip_cal) + ); + + // Generate tempmon_sample_en pulses for temperature adjustment + reg [8:0] samp_en_cnt; + + always @ (posedge clk) begin + if (rst || tempmon_done_skip || (samp_en_cnt == 'd0)) + samp_en_cnt <= #TCQ 'd267; + else if (calib_complete && (samp_en_cnt > 'd0)) + samp_en_cnt <= #TCQ samp_en_cnt - 1; + end + + always @ (posedge clk) begin + if (rst || tempmon_done_skip) + skip_cal_tempmon_samp_en <= #TCQ 1'b0; + else if (samp_en_cnt == 'd260) + skip_cal_tempmon_samp_en <= #TCQ 1'b1; + else + skip_cal_tempmon_samp_en <= #TCQ 1'b0; + end + + + + end else begin: skip_calib_tap_off + assign calib_po_f_en = 1'b0; + assign calib_po_f_incdec = 1'b0; + assign calib_po_sel_stg2stg3 = 1'b0; + assign calib_po_c_en = 1'b0; + assign calib_po_c_inc = 1'b0; + assign calib_pi_f_en = 1'b0; + assign calib_pi_f_incdec = 1'b0; + assign calib_idelay_ce = 1'b0; + assign calib_idelay_inc = 1'b0; + assign calib_tap_inc_done = 1'b0; + assign calib_tap_inc_byte_cnt = 'd0; + assign skip_cal_po_pi_dec_done = 1'b1; + + always @(posedge clk) begin + calib_tap_req <= #TCQ 1'b0; + calib_device_temp <= #TCQ 'd0; + skip_cal_tempmon_samp_en <= #TCQ 1'b0; + end + +end +endgenerate + + //*************************************************************************** + // Temperature induced PI tap adjustment logic + //*************************************************************************** + + mig_7series_v4_2_ddr_phy_tempmon # + ( + .SKIP_CALIB (SKIP_CALIB), + .TCQ (TCQ) + ) + ddr_phy_tempmon_0 + ( + .rst (rst), + .clk (clk), + .calib_complete (calib_complete), + .tempmon_pi_f_inc (tempmon_pi_f_inc), + .tempmon_pi_f_dec (tempmon_pi_f_dec), + .tempmon_sel_pi_incdec (tempmon_sel_pi_incdec), + .device_temp (device_temp), + .calib_device_temp (calib_device_temp), + .tempmon_sample_en (tempmon_sample_en | skip_cal_tempmon_samp_en), + .tempmon_done_skip (tempmon_done_skip) + ); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v new file mode 100644 index 0000000..9c7ce2b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v @@ -0,0 +1,213 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Feb 08 2011 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_ddr_if_post_fifo # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter DEPTH = 4, // # of entries + parameter WIDTH = 32 // data bus width + ) + ( + input clk, // clock + input rst, // synchronous reset + input [3:0] empty_in, + input rd_en_in, + input [WIDTH-1:0] d_in, // write data from controller + output empty_out, + output byte_rd_en, + output [WIDTH-1:0] d_out // write data to OUT_FIFO + ); + + // # of bits used to represent read/write pointers + localparam PTR_BITS + = (DEPTH == 2) ? 1 : + (((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx); + + integer i; + + reg [WIDTH-1:0] mem[0:DEPTH-1]; + (* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */; + (* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */; + reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; + // Register duplication to reduce the fan out + (* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; + reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; + wire [WIDTH-1:0] mem_out; + (* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */; + + task updt_ptrs; + input rd; + input wr; + reg [1:0] next_rd_ptr; + reg [1:0] next_wr_ptr; + begin + next_rd_ptr = (rd_ptr + 1'b1)%DEPTH; + next_wr_ptr = (wr_ptr + 1'b1)%DEPTH; + casez ({rd, wr, my_empty[1], my_full[1]}) + 4'b00zz: ; // No access, do nothing + 4'b0100: begin + // Write when neither empty, nor full; check for full + wr_ptr <= #TCQ next_wr_ptr; + my_full[0] <= #TCQ (next_wr_ptr == rd_ptr); + my_full[1] <= #TCQ (next_wr_ptr == rd_ptr); + //mem[wr_ptr] <= #TCQ d_in; + end + 4'b0110: begin + // Write when empty; no need to check for full + wr_ptr <= #TCQ next_wr_ptr; + my_empty <= #TCQ 5'b00000; + //mem[wr_ptr] <= #TCQ d_in; + end + 4'b1000: begin + // Read when neither empty, nor full; check for empty + rd_ptr <= #TCQ next_rd_ptr; + rd_ptr_timing <= #TCQ next_rd_ptr; + my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr); + my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr); + end + 4'b1001: begin + // Read when full; no need to check for empty + rd_ptr <= #TCQ next_rd_ptr; + rd_ptr_timing <= #TCQ next_rd_ptr; + my_full[0] <= #TCQ 1'b0; + my_full[1] <= #TCQ 1'b0; + end + 4'b1100, 4'b1101, 4'b1110: begin + // Read and write when empty, full, or neither empty/full; no need + // to check for empty or full conditions + rd_ptr <= #TCQ next_rd_ptr; + rd_ptr_timing <= #TCQ next_rd_ptr; + wr_ptr <= #TCQ next_wr_ptr; + //mem[wr_ptr] <= #TCQ d_in; + end + 4'b0101, 4'b1010: ; + // Read when empty, Write when full; Keep all pointers the same + // and don't change any of the flags (i.e. ignore the read/write). + // This might happen because a faulty DQS_FOUND calibration could + // result in excessive skew between when the various IN_FIFO's + // first become not empty. In this case, the data going to each + // post-FIFO/IN_FIFO should be read out and discarded + // synthesis translate_off + default: begin + // Covers any other cases, in particular for simulation if + // any signals are X's + $display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b", + $time, rd, wr, my_empty[1], my_full[1]); + rd_ptr <= #TCQ 2'bxx; + rd_ptr_timing <= #TCQ 2'bxx; + wr_ptr <= #TCQ 2'bxx; + end + // synthesis translate_on + endcase + end + endtask + + + assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr]; + // The combined IN_FIFO + post FIFO is only "empty" when both are empty + assign empty_out = empty_in[0] & my_empty[0]; + assign byte_rd_en = !empty_in[3] || !my_empty[3]; + + always @(posedge clk) + if (rst) begin + my_empty <= #TCQ 5'b11111; + my_full <= #TCQ 2'b00; + rd_ptr <= #TCQ 'b0; + rd_ptr_timing <= #TCQ 'b0; + wr_ptr <= #TCQ 'b0; + end else begin + // Special mode: If IN_FIFO has data, and controller is reading at + // the same time, then operate post-FIFO in "passthrough" mode (i.e. + // don't update any of the read/write pointers, and route IN_FIFO + // data to post-FIFO data) + if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ; + else + // Otherwise, we're writing to FIFO when IN_FIFO is not empty, + // and reading from the FIFO based on the rd_en_in signal (read + // enable from controller). The functino updt_ptrs should catch + // an illegal conditions. + updt_ptrs(rd_en_in, !empty_in[1]); + end + + + assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) | + (rd_en_in & !my_empty[2]))); + + + always @ (posedge clk) + begin + if (wr_en) + mem[wr_ptr] <= #TCQ d_in; + end + + assign mem_out = mem[rd_ptr_timing]; + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v new file mode 100644 index 0000000..3e1fb10 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v @@ -0,0 +1,1805 @@ +/*********************************************************** +-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $ +// $Author: gary $ +// $DateTime: 2010/05/11 18:05:17 $ +// $Change: 490882 $ +// Description: +// This verilog file is a parameterizable wrapper instantiating +// up to 5 memory banks of 4-lane phy primitives. There +// There are always 2 control banks leaving 18 lanes for data. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +//////////////////////////////////////////////////////////// +***********************************************************/ + + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_mc_phy + #( +// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0 + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + parameter RCLK_SELECT_BANK = 0, + parameter RCLK_SELECT_LANE = "B", + parameter RCLK_SELECT_EDGE = 4'b1111, + parameter GENERATE_DDR_CK_MAP = "0B", + parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002, + parameter USE_PRE_POST_FIFO = "TRUE", + parameter SYNTHESIS = "FALSE", + parameter PO_CTL_COARSE_BYPASS = "FALSE", + parameter PI_SEL_CLK_OFFSET = 6, + + parameter PHYCTL_CMD_FIFO = "FALSE", + parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio + +// common to all i/o banks + parameter PHY_FOUR_WINDOW_CLOCKS = 63, + parameter PHY_EVENTS_DELAY = 18, + parameter PHY_COUNT_EN = "TRUE", + parameter PHY_SYNC_MODE = "TRUE", + parameter PHY_DISABLE_SEQ_MATCH = "FALSE", + parameter MASTER_PHY_CTL = 0, +// common to instance 0 + parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff, + parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000, + parameter PHY_0_LANE_REMAP = 16'h3210, + parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE", + parameter PHY_0_IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter NUM_DDR_CK = 1, + parameter PHY_0_DATA_CTL = DATA_CTL_B0, + parameter PHY_0_CMD_OFFSET = 0, + parameter PHY_0_RD_CMD_OFFSET_0 = 0, + parameter PHY_0_RD_CMD_OFFSET_1 = 0, + parameter PHY_0_RD_CMD_OFFSET_2 = 0, + parameter PHY_0_RD_CMD_OFFSET_3 = 0, + parameter PHY_0_RD_DURATION_0 = 0, + parameter PHY_0_RD_DURATION_1 = 0, + parameter PHY_0_RD_DURATION_2 = 0, + parameter PHY_0_RD_DURATION_3 = 0, + parameter PHY_0_WR_CMD_OFFSET_0 = 0, + parameter PHY_0_WR_CMD_OFFSET_1 = 0, + parameter PHY_0_WR_CMD_OFFSET_2 = 0, + parameter PHY_0_WR_CMD_OFFSET_3 = 0, + parameter PHY_0_WR_DURATION_0 = 0, + parameter PHY_0_WR_DURATION_1 = 0, + parameter PHY_0_WR_DURATION_2 = 0, + parameter PHY_0_WR_DURATION_3 = 0, + parameter PHY_0_AO_WRLVL_EN = 0, + parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) + parameter PHY_0_OF_ALMOST_FULL_VALUE = 1, + parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1, +// per lane parameters + parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE", + parameter PHY_0_A_PI_CLKOUT_DIV = 2, + parameter PHY_0_A_PO_CLKOUT_DIV = 2, + parameter PHY_0_A_BURST_MODE = "TRUE", + parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF", + parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", + parameter PHY_0_A_PO_OCLK_DELAY = 25, + parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE", + parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4", + parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4", + parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED", + parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED", + parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE", + parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00, + parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + +// common to instance 1 + parameter PHY_1_BITLANES = PHY_0_BITLANES, + parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000, + parameter PHY_1_LANE_REMAP = 16'h3210, + parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE", + parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP, + parameter PHY_1_DATA_CTL = DATA_CTL_B1, + parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET, + parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0, + parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1, + parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2, + parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3, + parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0, + parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1, + parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2, + parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3, + parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0, + parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1, + parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2, + parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3, + parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0, + parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1, + parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2, + parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3, + parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN, + parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE) + parameter PHY_1_OF_ALMOST_FULL_VALUE = 1, + parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1, +// per lane parameters + parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV, + parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV, + parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV, + parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE, + parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC, + parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC , + parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, + parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, + parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY, + parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV, + parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE, + parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + +// common to instance 2 + parameter PHY_2_BITLANES = PHY_0_BITLANES, + parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000, + parameter PHY_2_LANE_REMAP = 16'h3210, + parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE", + parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP, + parameter PHY_2_DATA_CTL = DATA_CTL_B2, + parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET, + parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0, + parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1, + parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2, + parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3, + parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0, + parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1, + parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2, + parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3, + parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0, + parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1, + parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2, + parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3, + parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0, + parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1, + parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2, + parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3, + parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN, + parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE) + parameter PHY_2_OF_ALMOST_FULL_VALUE = 1, + parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1, +// per lane parameters + parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV, + parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV , + parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV, + parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE , + parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC, + parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC, + parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE, + parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE, + parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY, + parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, + parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, + parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY, + parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV, + parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE, + parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH, + parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE, + parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE, + parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE", + parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"), + parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"), + parameter TCK = 2500, + +// local computational use, do not pass down + parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3]) + + (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3]) + , // must not delete comma for syntax + parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))), + parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) , + parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) , + parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) , + parameter HIGHEST_LANE_B3 = 0, + parameter HIGHEST_LANE_B4 = 0, + + parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))), + parameter LP_DDR_CK_WIDTH = 2, + parameter GENERATE_SIGNAL_SPLIT = "FALSE" + ,parameter CKE_ODT_AUX = "FALSE" + ,parameter PI_DIV2_INCDEC = "FALSE" + ) + ( + input rst, + input ddr_rst_in_n , + input phy_clk, + input clk_div2, + input freq_refclk, + input mem_refclk, + input mem_refclk_div4, + input pll_lock, + input sync_pulse, + input auxout_clk, + input idelayctrl_refclk, + input [HIGHEST_LANE*80-1:0] phy_dout, + input phy_cmd_wr_en, + input phy_data_wr_en, + input phy_rd_en, + input [31:0] phy_ctl_wd, + input [3:0] aux_in_1, + input [3:0] aux_in_2, + input [5:0] data_offset_1, + input [5:0] data_offset_2, + input phy_ctl_wr, + input if_rst, + input if_empty_def, + input cke_in, + input idelay_ce, + input idelay_ld, + input idelay_inc, + input phyGo, + input input_sink, + output if_a_empty, + output if_empty /* synthesis syn_maxfan = 3 */, + output if_empty_or, + output if_empty_and, + output of_ctl_a_full, + output of_data_a_full, + output of_ctl_full, + output of_data_full, + output pre_data_a_full, + output [HIGHEST_LANE*80-1:0] phy_din, + output phy_ctl_a_full, + output wire [3:0] phy_ctl_full, + output [HIGHEST_LANE*12-1:0] mem_dq_out, + output [HIGHEST_LANE*12-1:0] mem_dq_ts, + input [HIGHEST_LANE*10-1:0] mem_dq_in, + output [HIGHEST_LANE-1:0] mem_dqs_out, + output [HIGHEST_LANE-1:0] mem_dqs_ts, + input [HIGHEST_LANE-1:0] mem_dqs_in, + +(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller + output phy_ctl_ready, // to fabric + output reg rst_out, // to memory + output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk, +// output rclk, + output mcGo, + output ref_dll_lock, +// calibration signals + input phy_write_calib, + input phy_read_calib, + input [5:0] calib_sel, + input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank + input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs + input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane + input calib_in_common, + input [2:0] po_fine_enable, + input [2:0] po_coarse_enable, + input [2:0] po_fine_inc, + input [2:0] po_coarse_inc, + input po_counter_load_en, + input [2:0] po_sel_fine_oclk_delay, + input [8:0] po_counter_load_val, + input po_counter_read_en, + output reg po_coarse_overflow, + output reg po_fine_overflow, + output reg [8:0] po_counter_read_val, + + + input [HIGHEST_BANK-1:0] pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input pi_counter_read_en, + input [5:0] pi_counter_load_val, + output reg pi_fine_overflow, + output reg [5:0] pi_counter_read_val, + + output reg pi_phase_locked, + output pi_phase_locked_all, + output reg pi_dqs_found, + output pi_dqs_found_all, + output pi_dqs_found_any, + output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, + output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + output reg pi_dqs_out_of_range, + input [29:0] fine_delay, + input fine_delay_sel + ); + + +wire [7:0] calib_zero_inputs_int ; +wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ; + +//Added the temporary variable for concadination operation +wire [2:0] calib_sel_byte0 ; +wire [2:0] calib_sel_byte1 ; +wire [2:0] calib_sel_byte2 ; + +wire [4:0] po_coarse_overflow_w; +wire [4:0] po_fine_overflow_w; +wire [8:0] po_counter_read_val_w[4:0]; +wire [4:0] pi_fine_overflow_w; +wire [5:0] pi_counter_read_val_w[4:0]; +wire [4:0] pi_dqs_found_w; +wire [4:0] pi_dqs_found_all_w; +wire [4:0] pi_dqs_found_any_w; +wire [4:0] pi_dqs_out_of_range_w; +wire [4:0] pi_phase_locked_w; +wire [4:0] pi_phase_locked_all_w; +wire [4:0] rclk_w; +wire [HIGHEST_BANK-1:0] phy_ctl_ready_w; +wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0]; +wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_; + + +wire [3:0] if_q0; +wire [3:0] if_q1; +wire [3:0] if_q2; +wire [3:0] if_q3; +wire [3:0] if_q4; +wire [7:0] if_q5; +wire [7:0] if_q6; +wire [3:0] if_q7; +wire [3:0] if_q8; +wire [3:0] if_q9; + +wire [31:0] _phy_ctl_wd; +wire [3:0] aux_in_[4:1]; +wire [3:0] rst_out_w; + +wire freq_refclk_split; +wire mem_refclk_split; +wire mem_refclk_div4_split; +wire sync_pulse_split; +wire phy_clk_split0; +wire phy_ctl_clk_split0; +wire [31:0] phy_ctl_wd_split0; +wire phy_ctl_wr_split0; +wire phy_ctl_clk_split1; +wire phy_clk_split1; +wire [31:0] phy_ctl_wd_split1; +wire phy_ctl_wr_split1; +wire [5:0] phy_data_offset_1_split1; +wire phy_ctl_clk_split2; +wire phy_clk_split2; +wire [31:0] phy_ctl_wd_split2; +wire phy_ctl_wr_split2; +wire [5:0] phy_data_offset_2_split2; +wire [HIGHEST_LANE*80-1:0] phy_dout_split0; +wire phy_cmd_wr_en_split0; +wire phy_data_wr_en_split0; +wire phy_rd_en_split0; +wire [HIGHEST_LANE*80-1:0] phy_dout_split1; +wire phy_cmd_wr_en_split1; +wire phy_data_wr_en_split1; +wire phy_rd_en_split1; +wire [HIGHEST_LANE*80-1:0] phy_dout_split2; +wire phy_cmd_wr_en_split2; +wire phy_data_wr_en_split2; +wire phy_rd_en_split2; + +wire phy_ctl_mstr_empty; +wire [HIGHEST_BANK-1:0] phy_ctl_empty; + +wire _phy_ctl_a_full_f; +wire _phy_ctl_a_empty_f; +wire _phy_ctl_full_f; +wire _phy_ctl_empty_f; +wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p; +wire [HIGHEST_BANK-1:0] _phy_ctl_full_p; +wire [HIGHEST_BANK-1:0] of_ctl_a_full_v; +wire [HIGHEST_BANK-1:0] of_ctl_full_v; +wire [HIGHEST_BANK-1:0] of_data_a_full_v; +wire [HIGHEST_BANK-1:0] of_data_full_v; +wire [HIGHEST_BANK-1:0] pre_data_a_full_v; +wire [HIGHEST_BANK-1:0] if_empty_v; +wire [HIGHEST_BANK-1:0] byte_rd_en_v; +wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks; +wire [HIGHEST_BANK-1:0] if_empty_or_v; +wire [HIGHEST_BANK-1:0] if_empty_and_v; +wire [HIGHEST_BANK-1:0] if_a_empty_v; + +localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4"; +localparam IF_SYNCHRONOUS_MODE = "FALSE"; +localparam IF_SLOW_WR_CLK = "FALSE"; +localparam IF_SLOW_RD_CLK = "FALSE"; + +localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE"; +localparam RCLK_NEG_EDGE = 3'b000; +localparam RCLK_POS_EDGE = 3'b111; + +localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF; +localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF; +localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF; + +// hi, lo positions for data offset field, MIG doesn't allow defines +localparam PC_DATA_OFFSET_RANGE_HI = 22; +localparam PC_DATA_OFFSET_RANGE_LO = 17; + +/* Phaser_In Output source coding table + "PHASE_REF" : 4'b0000; + "DELAYED_MEM_REF" : 4'b0101; + "DELAYED_PHASE_REF" : 4'b0011; + "DELAYED_REF" : 4'b0001; + "FREQ_REF" : 4'b1000; + "MEM_REF" : 4'b0010; +*/ + +localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF"; + + +localparam DDR_TCK = TCK; + +localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); +localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0; +localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line +localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line +localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta + +/* +Intrinsic delay of Phaser In Stage 1 +@3300ps - 1.939ns - 58.8% +@2500ps - 1.657ns - 66.3% +@1875ps - 1.263ns - 67.4% +@1500ps - 1.021ns - 68.1% +@1250ps - 0.868ns - 69.4% +@1072ps - 0.752ns - 70.1% +@938ps - 0.667ns - 71.1% +*/ + +// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0 +// Fraction of a full DDR_TCK period +localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 : + ((DDR_TCK < 1005) ? 0.667 : + (DDR_TCK < 1160) ? 0.752 : + (DDR_TCK < 1375) ? 0.868 : + (DDR_TCK < 1685) ? 1.021 : + (DDR_TCK < 2185) ? 1.263 : + (DDR_TCK < 2900) ? 1.657 : + (DDR_TCK < 3100) ? 1.771 : 1.939)*1000; +/* +Intrinsic delay of Phaser In Stage 2 +@3300ps - 0.912ns - 27.6% - single tap - 13ps +@3000ps - 0.848ns - 28.3% - single tap - 11ps +@2500ps - 1.264ns - 50.6% - single tap - 19ps +@1875ps - 1.000ns - 53.3% - single tap - 15ps +@1500ps - 0.848ns - 56.5% - single tap - 11ps +@1250ps - 0.736ns - 58.9% - single tap - 9ps +@1072ps - 0.664ns - 61.9% - single tap - 8ps +@938ps - 0.608ns - 64.8% - single tap - 7ps +*/ +// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps) +localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor +/* +Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1 +@3300ps - 1.294ns - 39.2% +@2500ps - 1.294ns - 51.8% +@1875ps - 1.030ns - 54.9% +@1500ps - 0.878ns - 58.5% +@1250ps - 0.766ns - 61.3% +@1072ps - 0.694ns - 64.7% +@938ps - 0.638ns - 68.0% + +Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0 +@3300ps - 2.084ns - 63.2% - single tap - 20ps +@2500ps - 2.084ns - 81.9% - single tap - 19ps +@1875ps - 1.676ns - 89.4% - single tap - 15ps +@1500ps - 1.444ns - 96.3% - single tap - 11ps +@1250ps - 1.276ns - 102.1% - single tap - 9ps +@1072ps - 1.164ns - 108.6% - single tap - 8ps +@938ps - 1.076ns - 114.7% - single tap - 7ps +*/ +// Fraction of a full DDR_TCK period +localparam real PO_STG1_INTRINSIC_DELAY = 0; +localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor +localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor +localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY + + (PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY); + +// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can +// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this, +// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments +// to the stage 2 delay can be made after reset is removed. + +localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line +localparam real PO_CIRC_BUF_META_ZONE = 200.0; +localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0; +localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK; +// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold +// If it is not more than the threshold than we must push the delay after the clock period plus a guardband. + +//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated. +localparam integer PO_CIRC_BUF_DELAY = 60; + +//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 : +// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE : +// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE; + +localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line +localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE; +localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY; +localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY; +localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE); +localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi +// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path +// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the +// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment +// is within the range of the stage 2 delay line in the Phaser_In. +localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY); +localparam integer PO_DELAY_INT = PO_DELAY; +localparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK); + +// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is +// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge. +// note that in this case PI_OFFSET is negative so invert before subtracting. +localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0 + ? PI_OFFSET + : ((-PI_OFFSET) < DDR_TCK/2) ? + (DDR_TCK/2 - (- PI_OFFSET)) : + (DDR_TCK - (- PI_OFFSET)) ; + +localparam real PI_STG2_DELAY = + (PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ? + PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND); +localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE; + +localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE)); + +localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; +localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; +localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ; + +localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ; + +localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ; + +localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ; +localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ; + + +localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC; + +localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC; + +localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; +localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC; + +wire _phy_clk; + +wire [2:0] mcGo_w; +wire [HIGHEST_BANK-1:0] ref_dll_lock_w; +reg [15:0] mcGo_r; + + +assign ref_dll_lock = & ref_dll_lock_w; + +initial begin + if ( SYNTHESIS == "FALSE" ) begin + $display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1); + $display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1); + $display("%m : HIGHEST_BANK = %d", HIGHEST_BANK); + + $display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD); + $display("%m : DDR_TCK = %0d ", DDR_TCK); + $display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE); + $display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY); + $display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET); + $display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE); + $display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY); + $display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY); + $display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY); + $display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY); + $display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY); + $display("%m : PO_DELAY = %0.2f ", PO_DELAY); + $display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY); + $display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY); + + $display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY); + $display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY); + $display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY); + $display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY); + $display("%m : PI_OFFSET = %0.2f ", PI_OFFSET); + if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used."); + $display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY); + $display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND); + $display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY); + $display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE); + end // SYNTHESIS + if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY); +end + + assign sync_pulse_split = sync_pulse; + assign mem_refclk_split = mem_refclk; + assign freq_refclk_split = freq_refclk; + assign mem_refclk_div4_split = mem_refclk_div4; + assign phy_ctl_clk_split0 = _phy_clk; + assign phy_ctl_wd_split0 = phy_ctl_wd; + assign phy_ctl_wr_split0 = phy_ctl_wr; + assign phy_clk_split0 = phy_clk; + assign phy_cmd_wr_en_split0 = phy_cmd_wr_en; + assign phy_data_wr_en_split0 = phy_data_wr_en; + assign phy_rd_en_split0 = phy_rd_en; + assign phy_dout_split0 = phy_dout; + assign phy_ctl_clk_split1 = phy_clk; + assign phy_ctl_wd_split1 = phy_ctl_wd; + assign phy_data_offset_1_split1 = data_offset_1; + assign phy_ctl_wr_split1 = phy_ctl_wr; + assign phy_clk_split1 = phy_clk; + assign phy_cmd_wr_en_split1 = phy_cmd_wr_en; + assign phy_data_wr_en_split1 = phy_data_wr_en; + assign phy_rd_en_split1 = phy_rd_en; + assign phy_dout_split1 = phy_dout; + assign phy_ctl_clk_split2 = phy_clk; + assign phy_ctl_wd_split2 = phy_ctl_wd; + assign phy_data_offset_2_split2 = data_offset_2; + assign phy_ctl_wr_split2 = phy_ctl_wr; + assign phy_clk_split2 = phy_clk; + assign phy_cmd_wr_en_split2 = phy_cmd_wr_en; + assign phy_data_wr_en_split2 = phy_data_wr_en; + assign phy_rd_en_split2 = phy_rd_en; + assign phy_dout_split2 = phy_dout; + +// these wires are needed to coerce correct synthesis +// the synthesizer did not always see the widths of the +// parameters as 4 bits. + +wire [3:0] blb0 = BYTE_LANES_B0; +wire [3:0] blb1 = BYTE_LANES_B1; +wire [3:0] blb2 = BYTE_LANES_B2; + +wire [3:0] dcb0 = DATA_CTL_B0; +wire [3:0] dcb1 = DATA_CTL_B1; +wire [3:0] dcb2 = DATA_CTL_B2; + +assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0}); +assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0}); +assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0]; +assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs}; +//Added to remove concadination in the instantiation +assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ; +assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ; +assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ; + +assign calib_zero_lanes_int = calib_zero_lanes; + +assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0]; + +assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL]; + +assign of_ctl_a_full = |of_ctl_a_full_v; +assign of_ctl_full = |of_ctl_full_v; +assign of_data_a_full = |of_data_a_full_v; +assign of_data_full = |of_data_full_v; +assign pre_data_a_full= |pre_data_a_full_v; +// if if_empty_def == 1, empty is asserted only if all are empty; +// this allows the user to detect a skewed fifo depth and self-clear +// if desired. It avoids a reset to clear the flags. +assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v; +assign if_empty_or = |if_empty_or_v; +assign if_empty_and = &if_empty_and_v; +assign if_a_empty = |if_a_empty_v; + + +generate +genvar i; +for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen + case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff) + 16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; + 16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; + 16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; + 16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; + 16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; + 16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; + 16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; + 16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; + 16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11; + 16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11; + 16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11; + 16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11; + default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff )); + endcase +end +endgenerate + +//assign rclk = rclk_w[RCLK_SELECT_BANK]; + +reg rst_auxout; +reg rst_auxout_r; +reg rst_auxout_rr; + +always @(posedge auxout_clk or posedge rst) begin + if ( rst) begin + rst_auxout_r <= #(1) 1'b1; + rst_auxout_rr <= #(1) 1'b1; + end + else begin + rst_auxout_r <= #(1) rst; + rst_auxout_rr <= #(1) rst_auxout_r; + end +end +if ( LP_RCLK_SELECT_EDGE[0]) begin + always @(posedge auxout_clk or posedge rst) begin + if ( rst) begin + rst_auxout <= #(1) 1'b1; + end + else begin + rst_auxout <= #(1) rst_auxout_rr; + end + end +end +else begin + always @(negedge auxout_clk or posedge rst) begin + if ( rst) begin + rst_auxout <= #(1) 1'b1; + end + else begin + rst_auxout <= #(1) rst_auxout_rr; + end + end +end + +localparam L_RESET_SELECT_BANK = + (BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK; + +always @(*) begin + rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n; +end + +always @(posedge phy_clk) begin + if ( rst) + mcGo_r <= #(1) 0; + else + mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w; +end + +assign mcGo = mcGo_r[15]; + + +generate + + +// this is an optional 1 clock delay to add latency to the phy_control programming path + +if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft + reg [31:0] phy_wd_reg = 0; + reg [3:0] aux_in1_reg = 0; + reg [3:0] aux_in2_reg = 0; + reg sfifo_ready = 0; + assign _phy_ctl_wd = phy_wd_reg; + assign aux_in_[1] = aux_in1_reg; + assign aux_in_[2] = aux_in2_reg; + assign phy_ctl_a_full = |_phy_ctl_a_full_p; + assign phy_ctl_full[0] = |_phy_ctl_full_p; + assign phy_ctl_full[1] = |_phy_ctl_full_p; + assign phy_ctl_full[2] = |_phy_ctl_full_p; + assign phy_ctl_full[3] = |_phy_ctl_full_p; + assign _phy_clk = phy_clk; + + always @(posedge phy_clk) begin + phy_wd_reg <= #1 phy_ctl_wd; + aux_in1_reg <= #1 aux_in_1; + aux_in2_reg <= #1 aux_in_2; + sfifo_ready <= #1 phy_ctl_wr; + end + +end + +else if (PHYCTL_CMD_FIFO == "FALSE") begin + assign _phy_ctl_wd = phy_ctl_wd; + assign aux_in_[1] = aux_in_1; + assign aux_in_[2] = aux_in_2; + assign phy_ctl_a_full = |_phy_ctl_a_full_p; + assign phy_ctl_full[0] = |_phy_ctl_full_p; + assign phy_ctl_full[3:1] = 3'b000; + assign _phy_clk = phy_clk; + +end +endgenerate + + +// instance of four-lane phy + +generate + +if (HIGHEST_BANK == 3) begin : banks_3 + assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]}; + assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]}; + assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]}; +end +else if (HIGHEST_BANK == 2) begin : banks_2 + assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1}; + assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1}; +end +else begin : banks_1 + assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1}; +end + +if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0 +mig_7series_v4_2_ddr_phy_4lanes # + ( + .BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */ + .DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */ + .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), + .PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY), + .BITLANES (PHY_0_BITLANES), + .BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), + .BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK), + .LAST_BANK (PHY_0_IS_LAST_BANK), + .LANE_REMAP (PHY_0_LANE_REMAP), + .OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE), + .IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE), + .GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL), + .IODELAY_GRP (PHY_0_IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .NUM_DDR_CK (NUM_DDR_CK), + .TCK (TCK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .PC_CLK_RATIO (PHY_CLK_RATIO), + .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), + .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), + .PC_BURST_MODE (PHY_0_A_BURST_MODE), + .PC_SYNC_MODE (PHY_SYNC_MODE), + .PC_MULTI_REGION (PHY_MULTI_REGION), + .PC_PHY_COUNT_EN (PHY_COUNT_EN), + .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), + .PC_CMD_OFFSET (PHY_0_CMD_OFFSET), + .PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), + .PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), + .PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), + .PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), + .PC_RD_DURATION_0 (PHY_0_RD_DURATION_0), + .PC_RD_DURATION_1 (PHY_0_RD_DURATION_1), + .PC_RD_DURATION_2 (PHY_0_RD_DURATION_2), + .PC_RD_DURATION_3 (PHY_0_RD_DURATION_3), + .PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), + .PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), + .PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), + .PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), + .PC_WR_DURATION_0 (PHY_0_WR_DURATION_0), + .PC_WR_DURATION_1 (PHY_0_WR_DURATION_1), + .PC_WR_DURATION_2 (PHY_0_WR_DURATION_2), + .PC_WR_DURATION_3 (PHY_0_WR_DURATION_3), + .PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN), + .PC_AO_TOGGLE (PHY_0_AO_TOGGLE), + + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + + .A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY), + .B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY), + .C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY), + .D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY), + + .A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), + .A_PI_BURST_MODE (PHY_0_A_BURST_MODE), + .A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC), + .B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC), + .C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC), + .D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC), + .A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC), + .A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV), + .A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE), + .B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE), + .C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE), + .D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE), + .A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE), + .B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE), + .C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE), + .D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE), + .A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE), + .A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH), + .B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE), + .B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH), + .C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE), + .C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH), + .D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE), + .D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH), + .A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE), + .A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) +) + u_ddr_phy_4lanes +( + .rst (rst), + .phy_clk (phy_clk_split0), + .clk_div2 (clk_div2), + .phy_ctl_clk (phy_ctl_clk_split0), + .phy_ctl_wd (phy_ctl_wd_split0), + .data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]), + .phy_ctl_wr (phy_ctl_wr_split0), + .mem_refclk (mem_refclk_split), + .freq_refclk (freq_refclk_split), + .mem_refclk_div4 (mem_refclk_div4_split), + .sync_pulse (sync_pulse_split), + .phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]), + .phy_cmd_wr_en (phy_cmd_wr_en_split0), + .phy_data_wr_en (phy_data_wr_en_split0), + .phy_rd_en (phy_rd_en_split0), + .pll_lock (pll_lock), + .ddr_clk (ddr_clk_w[0]), + .rclk (), + .rst_out (rst_out_w[0]), + .mcGo (mcGo_w[0]), + .ref_dll_lock (ref_dll_lock_w[0]), + .idelayctrl_refclk (idelayctrl_refclk), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .phy_ctl_mstr_empty (phy_ctl_mstr_empty), + .if_rst (if_rst), + .if_empty_def (if_empty_def), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]), + .if_a_empty (if_a_empty_v[0]), + .if_empty (if_empty_v[0]), + .byte_rd_en (byte_rd_en_v[0]), + .if_empty_or (if_empty_or_v[0]), + .if_empty_and (if_empty_and_v[0]), + .of_ctl_a_full (of_ctl_a_full_v[0]), + .of_data_a_full (of_data_a_full_v[0]), + .of_ctl_full (of_ctl_full_v[0]), + .of_data_full (of_data_full_v[0]), + .pre_data_a_full (pre_data_a_full_v[0]), + .phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]), + .phy_ctl_a_full (_phy_ctl_a_full_p[0]), + .phy_ctl_full (_phy_ctl_full_p[0]), + .phy_ctl_empty (phy_ctl_empty[0]), + .mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]), + .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]), + .mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]), + .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]), + .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]), + .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]), + .aux_out (aux_out_[3:0]), + .phy_ctl_ready (phy_ctl_ready_w[0]), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), +// .scan_test_bus_A (scan_test_bus_A), +// .scan_test_bus_B (), +// .scan_test_bus_C (), +// .scan_test_bus_D (), + .phyGo (phyGo), + .input_sink (input_sink), + + .calib_sel (calib_sel_byte0), + .calib_zero_ctrl (calib_zero_ctrl[0]), + .calib_zero_lanes (calib_zero_lanes_int[3:0]), + .calib_in_common (calib_in_common), + .po_coarse_enable (po_coarse_enable[0]), + .po_fine_enable (po_fine_enable[0]), + .po_fine_inc (po_fine_inc[0]), + .po_coarse_inc (po_coarse_inc[0]), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (po_coarse_overflow_w[0]), + .po_fine_overflow (po_fine_overflow_w[0]), + .po_counter_read_val (po_counter_read_val_w[0]), + + .pi_rst_dqs_find (pi_rst_dqs_find[0]), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (pi_fine_overflow_w[0]), + .pi_counter_read_val (pi_counter_read_val_w[0]), + .pi_dqs_found (pi_dqs_found_w[0]), + .pi_dqs_found_all (pi_dqs_found_all_w[0]), + .pi_dqs_found_any (pi_dqs_found_any_w[0]), + .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]), + .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]), + .pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]), + .pi_phase_locked (pi_phase_locked_w[0]), + .pi_phase_locked_all (pi_phase_locked_all_w[0]), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) +); + + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[0] <= #100 0; + aux_out[2] <= #100 0; + end + else begin + aux_out[0] <= #100 aux_out_[0]; + aux_out[2] <= #100 aux_out_[2]; + end + end + if ( LP_RCLK_SELECT_EDGE[0]) begin + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[1] <= #100 0; + aux_out[3] <= #100 0; + end + else begin + aux_out[1] <= #100 aux_out_[1]; + aux_out[3] <= #100 aux_out_[3]; + end + end + end + else begin + always @(negedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[1] <= #100 0; + aux_out[3] <= #100 0; + end + else begin + aux_out[1] <= #100 aux_out_[1]; + aux_out[3] <= #100 aux_out_[3]; + end + end + end +end +else begin + if ( HIGHEST_BANK > 0) begin + assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0; + assign _phy_ctl_a_full_p[0] = 0; + assign of_ctl_a_full_v[0] = 0; + assign of_ctl_full_v[0] = 0; + assign of_data_a_full_v[0] = 0; + assign of_data_full_v[0] = 0; + assign pre_data_a_full_v[0] = 0; + assign if_empty_v[0] = 0; + assign byte_rd_en_v[0] = 1; + always @(*) + aux_out[3:0] = 0; + end + assign pi_dqs_found_w[0] = 1; + assign pi_dqs_found_all_w[0] = 1; + assign pi_dqs_found_any_w[0] = 0; + assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111; + assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111; + assign pi_dqs_out_of_range_w[0] = 0; + assign pi_phase_locked_w[0] = 1; + assign po_fine_overflow_w[0] = 0; + assign po_coarse_overflow_w[0] = 0; + assign po_fine_overflow_w[0] = 0; + assign pi_fine_overflow_w[0] = 0; + assign po_counter_read_val_w[0] = 0; + assign pi_counter_read_val_w[0] = 0; + assign mcGo_w[0] = 1; + if ( RCLK_SELECT_BANK == 0) + always @(*) + aux_out[3:0] = 0; +end + +if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1 + +mig_7series_v4_2_ddr_phy_4lanes # + ( + .BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */ + .DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */ + .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), + .PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY), + .BITLANES (PHY_1_BITLANES), + .BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), + .BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK), + .LAST_BANK (PHY_1_IS_LAST_BANK ), + .LANE_REMAP (PHY_1_LANE_REMAP), + .OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE), + .IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE), + .GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL), + .IODELAY_GRP (PHY_1_IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .NUM_DDR_CK (NUM_DDR_CK), + .TCK (TCK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .PC_CLK_RATIO (PHY_CLK_RATIO), + .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), + .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), + .PC_BURST_MODE (PHY_1_A_BURST_MODE), + .PC_SYNC_MODE (PHY_SYNC_MODE), + .PC_MULTI_REGION (PHY_MULTI_REGION), + .PC_PHY_COUNT_EN (PHY_COUNT_EN), + .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), + .PC_CMD_OFFSET (PHY_1_CMD_OFFSET), + .PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0), + .PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1), + .PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2), + .PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3), + .PC_RD_DURATION_0 (PHY_1_RD_DURATION_0), + .PC_RD_DURATION_1 (PHY_1_RD_DURATION_1), + .PC_RD_DURATION_2 (PHY_1_RD_DURATION_2), + .PC_RD_DURATION_3 (PHY_1_RD_DURATION_3), + .PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0), + .PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1), + .PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2), + .PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3), + .PC_WR_DURATION_0 (PHY_1_WR_DURATION_0), + .PC_WR_DURATION_1 (PHY_1_WR_DURATION_1), + .PC_WR_DURATION_2 (PHY_1_WR_DURATION_2), + .PC_WR_DURATION_3 (PHY_1_WR_DURATION_3), + .PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN), + .PC_AO_TOGGLE (PHY_1_AO_TOGGLE), + + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + + .A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY), + .B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY), + .C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY), + .D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY), + + .A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV), + .A_PI_BURST_MODE (PHY_1_A_BURST_MODE), + .A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC), + .B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC), + .C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC), + .D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC), + .A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC), + .A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY), + .A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV), + .A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE), + .B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE), + .C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE), + .D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE), + .A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE), + .B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE), + .C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE), + .D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE), + .A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE), + .A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH), + .B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE), + .B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH), + .C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE), + .C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH), + .D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE), + .D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH), + .A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE), + .A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) +) + u_ddr_phy_4lanes +( + .rst (rst), + .phy_clk (phy_clk_split1), + .clk_div2 (clk_div2), + .phy_ctl_clk (phy_ctl_clk_split1), + .phy_ctl_wd (phy_ctl_wd_split1), + .data_offset (phy_data_offset_1_split1), + .phy_ctl_wr (phy_ctl_wr_split1), + .mem_refclk (mem_refclk_split), + .freq_refclk (freq_refclk_split), + .mem_refclk_div4 (mem_refclk_div4_split), + .sync_pulse (sync_pulse_split), + .phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]), + .phy_cmd_wr_en (phy_cmd_wr_en_split1), + .phy_data_wr_en (phy_data_wr_en_split1), + .phy_rd_en (phy_rd_en_split1), + .pll_lock (pll_lock), + .ddr_clk (ddr_clk_w[1]), + .rclk (), + .rst_out (rst_out_w[1]), + .mcGo (mcGo_w[1]), + .ref_dll_lock (ref_dll_lock_w[1]), + .idelayctrl_refclk (idelayctrl_refclk), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .phy_ctl_mstr_empty (phy_ctl_mstr_empty), + .if_rst (if_rst), + .if_empty_def (if_empty_def), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]), + .if_a_empty (if_a_empty_v[1]), + .if_empty (if_empty_v[1]), + .byte_rd_en (byte_rd_en_v[1]), + .if_empty_or (if_empty_or_v[1]), + .if_empty_and (if_empty_and_v[1]), + .of_ctl_a_full (of_ctl_a_full_v[1]), + .of_data_a_full (of_data_a_full_v[1]), + .of_ctl_full (of_ctl_full_v[1]), + .of_data_full (of_data_full_v[1]), + .pre_data_a_full (pre_data_a_full_v[1]), + .phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]), + .phy_ctl_a_full (_phy_ctl_a_full_p[1]), + .phy_ctl_full (_phy_ctl_full_p[1]), + .phy_ctl_empty (phy_ctl_empty[1]), + .mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]), + .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]), + .mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]), + .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]), + .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]), + .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]), + .aux_out (aux_out_[7:4]), + .phy_ctl_ready (phy_ctl_ready_w[1]), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), +// .scan_test_bus_A (scan_test_bus_A), +// .scan_test_bus_B (), +// .scan_test_bus_C (), +// .scan_test_bus_D (), + .phyGo (phyGo), + .input_sink (input_sink), + + .calib_sel (calib_sel_byte1), + .calib_zero_ctrl (calib_zero_ctrl[1]), + .calib_zero_lanes (calib_zero_lanes_int[7:4]), + .calib_in_common (calib_in_common), + .po_coarse_enable (po_coarse_enable[1]), + .po_fine_enable (po_fine_enable[1]), + .po_fine_inc (po_fine_inc[1]), + .po_coarse_inc (po_coarse_inc[1]), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (po_coarse_overflow_w[1]), + .po_fine_overflow (po_fine_overflow_w[1]), + .po_counter_read_val (po_counter_read_val_w[1]), + + .pi_rst_dqs_find (pi_rst_dqs_find[1]), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (pi_fine_overflow_w[1]), + .pi_counter_read_val (pi_counter_read_val_w[1]), + .pi_dqs_found (pi_dqs_found_w[1]), + .pi_dqs_found_all (pi_dqs_found_all_w[1]), + .pi_dqs_found_any (pi_dqs_found_any_w[1]), + .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]), + .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]), + .pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]), + .pi_phase_locked (pi_phase_locked_w[1]), + .pi_phase_locked_all (pi_phase_locked_all_w[1]), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) +); + + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[4] <= #100 0; + aux_out[6] <= #100 0; + end + else begin + aux_out[4] <= #100 aux_out_[4]; + aux_out[6] <= #100 aux_out_[6]; + end + end + if ( LP_RCLK_SELECT_EDGE[1]) begin + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[5] <= #100 0; + aux_out[7] <= #100 0; + end + else begin + aux_out[5] <= #100 aux_out_[5]; + aux_out[7] <= #100 aux_out_[7]; + end + end + end + else begin + always @(negedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[5] <= #100 0; + aux_out[7] <= #100 0; + end + else begin + aux_out[5] <= #100 aux_out_[5]; + aux_out[7] <= #100 aux_out_[7]; + end + end + end +end +else begin + if ( HIGHEST_BANK > 1) begin + assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0; + assign _phy_ctl_a_full_p[1] = 0; + assign of_ctl_a_full_v[1] = 0; + assign of_ctl_full_v[1] = 0; + assign of_data_a_full_v[1] = 0; + assign of_data_full_v[1] = 0; + assign pre_data_a_full_v[1] = 0; + assign if_empty_v[1] = 0; + assign byte_rd_en_v[1] = 1; + assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111; + assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111; + always @(*) + aux_out[7:4] = 0; + end + assign pi_dqs_found_w[1] = 1; + assign pi_dqs_found_all_w[1] = 1; + assign pi_dqs_found_any_w[1] = 0; + assign pi_dqs_out_of_range_w[1] = 0; + assign pi_phase_locked_w[1] = 1; + assign po_coarse_overflow_w[1] = 0; + assign po_fine_overflow_w[1] = 0; + assign pi_fine_overflow_w[1] = 0; + assign po_counter_read_val_w[1] = 0; + assign pi_counter_read_val_w[1] = 0; + assign mcGo_w[1] = 1; +end + +if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2 + +mig_7series_v4_2_ddr_phy_4lanes # + ( + .BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */ + .DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */ + .PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS), + .PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY), + .BITLANES (PHY_2_BITLANES), + .BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), + .BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK), + .LAST_BANK (PHY_2_IS_LAST_BANK ), + .LANE_REMAP (PHY_2_LANE_REMAP), + .OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE), + .IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE), + .GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL), + .IODELAY_GRP (PHY_2_IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .NUM_DDR_CK (NUM_DDR_CK), + .TCK (TCK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .PC_CLK_RATIO (PHY_CLK_RATIO), + .PC_EVENTS_DELAY (PHY_EVENTS_DELAY), + .PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS), + .PC_BURST_MODE (PHY_2_A_BURST_MODE), + .PC_SYNC_MODE (PHY_SYNC_MODE), + .PC_MULTI_REGION (PHY_MULTI_REGION), + .PC_PHY_COUNT_EN (PHY_COUNT_EN), + .PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH), + .PC_CMD_OFFSET (PHY_2_CMD_OFFSET), + .PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0), + .PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1), + .PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2), + .PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3), + .PC_RD_DURATION_0 (PHY_2_RD_DURATION_0), + .PC_RD_DURATION_1 (PHY_2_RD_DURATION_1), + .PC_RD_DURATION_2 (PHY_2_RD_DURATION_2), + .PC_RD_DURATION_3 (PHY_2_RD_DURATION_3), + .PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0), + .PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1), + .PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2), + .PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3), + .PC_WR_DURATION_0 (PHY_2_WR_DURATION_0), + .PC_WR_DURATION_1 (PHY_2_WR_DURATION_1), + .PC_WR_DURATION_2 (PHY_2_WR_DURATION_2), + .PC_WR_DURATION_3 (PHY_2_WR_DURATION_3), + .PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN), + .PC_AO_TOGGLE (PHY_2_AO_TOGGLE), + + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + + .A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY), + .B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY), + .C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY), + .D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY), + .A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV), + .A_PI_BURST_MODE (PHY_2_A_BURST_MODE), + .A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC), + .B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC), + .C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC), + .D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC), + .A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC), + .A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY), + .A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV), + .A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE), + .B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE), + .C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE), + .D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE), + .A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE), + .B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE), + .C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE), + .D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE), + .A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE), + .A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH), + .B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE), + .B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH), + .C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE), + .C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH), + .D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE), + .D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH), + .A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE), + .A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) +) + u_ddr_phy_4lanes +( + .rst (rst), + .phy_clk (phy_clk_split2), + .clk_div2 (clk_div2), + .phy_ctl_clk (phy_ctl_clk_split2), + .phy_ctl_wd (phy_ctl_wd_split2), + .data_offset (phy_data_offset_2_split2), + .phy_ctl_wr (phy_ctl_wr_split2), + .mem_refclk (mem_refclk_split), + .freq_refclk (freq_refclk_split), + .mem_refclk_div4 (mem_refclk_div4_split), + .sync_pulse (sync_pulse_split), + .phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]), + .phy_cmd_wr_en (phy_cmd_wr_en_split2), + .phy_data_wr_en (phy_data_wr_en_split2), + .phy_rd_en (phy_rd_en_split2), + .pll_lock (pll_lock), + .ddr_clk (ddr_clk_w[2]), + .rclk (), + .rst_out (rst_out_w[2]), + .mcGo (mcGo_w[2]), + .ref_dll_lock (ref_dll_lock_w[2]), + .idelayctrl_refclk (idelayctrl_refclk), + .idelay_inc (idelay_inc), + .idelay_ce (idelay_ce), + .idelay_ld (idelay_ld), + .phy_ctl_mstr_empty (phy_ctl_mstr_empty), + .if_rst (if_rst), + .if_empty_def (if_empty_def), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]), + .if_a_empty (if_a_empty_v[2]), + .if_empty (if_empty_v[2]), + .byte_rd_en (byte_rd_en_v[2]), + .if_empty_or (if_empty_or_v[2]), + .if_empty_and (if_empty_and_v[2]), + .of_ctl_a_full (of_ctl_a_full_v[2]), + .of_data_a_full (of_data_a_full_v[2]), + .of_ctl_full (of_ctl_full_v[2]), + .of_data_full (of_data_full_v[2]), + .pre_data_a_full (pre_data_a_full_v[2]), + .phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]), + .phy_ctl_a_full (_phy_ctl_a_full_p[2]), + .phy_ctl_full (_phy_ctl_full_p[2]), + .phy_ctl_empty (phy_ctl_empty[2]), + .mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]), + .mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]), + .mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]), + .mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]), + .mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]), + .mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]), + .aux_out (aux_out_[11:8]), + .phy_ctl_ready (phy_ctl_ready_w[2]), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), +// .scan_test_bus_A (scan_test_bus_A), +// .scan_test_bus_B (), +// .scan_test_bus_C (), +// .scan_test_bus_D (), + .phyGo (phyGo), + .input_sink (input_sink), + + .calib_sel (calib_sel_byte2), + .calib_zero_ctrl (calib_zero_ctrl[2]), + .calib_zero_lanes (calib_zero_lanes_int[11:8]), + .calib_in_common (calib_in_common), + .po_coarse_enable (po_coarse_enable[2]), + .po_fine_enable (po_fine_enable[2]), + .po_fine_inc (po_fine_inc[2]), + .po_coarse_inc (po_coarse_inc[2]), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (po_coarse_overflow_w[2]), + .po_fine_overflow (po_fine_overflow_w[2]), + .po_counter_read_val (po_counter_read_val_w[2]), + + .pi_rst_dqs_find (pi_rst_dqs_find[2]), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (pi_fine_overflow_w[2]), + .pi_counter_read_val (pi_counter_read_val_w[2]), + .pi_dqs_found (pi_dqs_found_w[2]), + .pi_dqs_found_all (pi_dqs_found_all_w[2]), + .pi_dqs_found_any (pi_dqs_found_any_w[2]), + .pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]), + .pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]), + .pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]), + .pi_phase_locked (pi_phase_locked_w[2]), + .pi_phase_locked_all (pi_phase_locked_all_w[2]), + .fine_delay (fine_delay), + .fine_delay_sel (fine_delay_sel) +); + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[8] <= #100 0; + aux_out[10] <= #100 0; + end + else begin + aux_out[8] <= #100 aux_out_[8]; + aux_out[10] <= #100 aux_out_[10]; + end + end + if ( LP_RCLK_SELECT_EDGE[1]) begin + always @(posedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[9] <= #100 0; + aux_out[11] <= #100 0; + end + else begin + aux_out[9] <= #100 aux_out_[9]; + aux_out[11] <= #100 aux_out_[11]; + end + end + end + else begin + always @(negedge auxout_clk or posedge rst_auxout) begin + if (rst_auxout) begin + aux_out[9] <= #100 0; + aux_out[11] <= #100 0; + end + else begin + aux_out[9] <= #100 aux_out_[9]; + aux_out[11] <= #100 aux_out_[11]; + end + end + end +end +else begin + if ( HIGHEST_BANK > 2) begin + assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0; + assign _phy_ctl_a_full_p[2] = 0; + assign of_ctl_a_full_v[2] = 0; + assign of_ctl_full_v[2] = 0; + assign of_data_a_full_v[2] = 0; + assign of_data_full_v[2] = 0; + assign pre_data_a_full_v[2] = 0; + assign if_empty_v[2] = 0; + assign byte_rd_en_v[2] = 1; + assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111; + assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111; + always @(*) + aux_out[11:8] = 0; + end + assign pi_dqs_found_w[2] = 1; + assign pi_dqs_found_all_w[2] = 1; + assign pi_dqs_found_any_w[2] = 0; + assign pi_dqs_out_of_range_w[2] = 0; + assign pi_phase_locked_w[2] = 1; + assign po_coarse_overflow_w[2] = 0; + assign po_fine_overflow_w[2] = 0; + assign po_counter_read_val_w[2] = 0; + assign pi_counter_read_val_w[2] = 0; + assign mcGo_w[2] = 1; +end +endgenerate + +generate + +// for single bank , emit an extra phaser_in to generate rclk +// so that auxout can be placed in another region +// if desired + +if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0) +begin : phaser_in_rclk + +localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY; + +PHASER_IN_PHY #( + .BURST_MODE ( PHY_0_A_BURST_MODE), + .CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV), + .FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV), + .REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS), + .FINE_DELAY ( L_EXTRA_PI_FINE_DELAY), + .OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC) +) phaser_in_rclk ( + .DQSFOUND (), + .DQSOUTOFRANGE (), + .FINEOVERFLOW (), + .PHASELOCKED (), + .ISERDESRST (), + .ICLKDIV (), + .ICLK (), + .COUNTERREADVAL (), + .RCLK (), + .WRENABLE (), + .BURSTPENDINGPHY (), + .ENCALIBPHY (), + .FINEENABLE (0), + .FREQREFCLK (freq_refclk), + .MEMREFCLK (mem_refclk), + .RANKSELPHY (0), + .PHASEREFCLK (), + .RSTDQSFIND (0), + .RST (rst), + .FINEINC (), + .COUNTERLOADEN (), + .COUNTERREADEN (), + .COUNTERLOADVAL (), + .SYNCIN (sync_pulse), + .SYSCLK (phy_clk) +); + +end + +endgenerate + + + +always @(*) begin + case (calib_sel[5:3]) + 3'b000: begin + po_coarse_overflow = po_coarse_overflow_w[0]; + po_fine_overflow = po_fine_overflow_w[0]; + po_counter_read_val = po_counter_read_val_w[0]; + pi_fine_overflow = pi_fine_overflow_w[0]; + pi_counter_read_val = pi_counter_read_val_w[0]; + pi_phase_locked = pi_phase_locked_w[0]; + if ( calib_in_common) + pi_dqs_found = pi_dqs_found_any; + else + pi_dqs_found = pi_dqs_found_w[0]; + pi_dqs_out_of_range = pi_dqs_out_of_range_w[0]; + end + 3'b001: begin + po_coarse_overflow = po_coarse_overflow_w[1]; + po_fine_overflow = po_fine_overflow_w[1]; + po_counter_read_val = po_counter_read_val_w[1]; + pi_fine_overflow = pi_fine_overflow_w[1]; + pi_counter_read_val = pi_counter_read_val_w[1]; + pi_phase_locked = pi_phase_locked_w[1]; + if ( calib_in_common) + pi_dqs_found = pi_dqs_found_any; + else + pi_dqs_found = pi_dqs_found_w[1]; + pi_dqs_out_of_range = pi_dqs_out_of_range_w[1]; + end + 3'b010: begin + po_coarse_overflow = po_coarse_overflow_w[2]; + po_fine_overflow = po_fine_overflow_w[2]; + po_counter_read_val = po_counter_read_val_w[2]; + pi_fine_overflow = pi_fine_overflow_w[2]; + pi_counter_read_val = pi_counter_read_val_w[2]; + pi_phase_locked = pi_phase_locked_w[2]; + if ( calib_in_common) + pi_dqs_found = pi_dqs_found_any; + else + pi_dqs_found = pi_dqs_found_w[2]; + pi_dqs_out_of_range = pi_dqs_out_of_range_w[2]; + end + default: begin + po_coarse_overflow = 0; + po_fine_overflow = 0; + po_counter_read_val = 0; + pi_fine_overflow = 0; + pi_counter_read_val = 0; + pi_phase_locked = 0; + pi_dqs_found = 0; + pi_dqs_out_of_range = 0; + end + endcase +end + +endmodule // mc_phy + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v new file mode 100644 index 0000000..47b42ad --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v @@ -0,0 +1,1686 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ddr_mc_phy_wrapper.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Oct 10 2010 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Wrapper file that encompasses the MC_PHY module +// instantiation and handles the vector remapping between +// the MC_PHY ports and the user's DDR3 ports. Vector +// remapping affects DDR3 control, address, and DQ/DQS/DM. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_ddr_mc_phy_wrapper # + ( + parameter TCQ = 100, // Register delay (simulation only) + parameter tCK = 2500, // ps + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" + parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio + parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank + parameter BANK_WIDTH = 3, // # of bank address + parameter CKE_WIDTH = 1, // # of clock enable outputs + parameter CS_WIDTH = 1, // # of chip select + parameter CK_WIDTH = 1, // # of CK + parameter CWL = 5, // CAS Write latency + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter DM_WIDTH = 8, // # of data mask + parameter DQ_WIDTH = 16, // # of data bits + parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of strobe pairs + parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) + parameter RANKS = 4, // # of ranks + parameter ODT_WIDTH = 1, // # of ODT outputs + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter REG_CTRL = "OFF", // "ON" for registered DIMM + parameter ROW_WIDTH = 16, // # of row/column address + parameter USE_CS_PORT = 1, // Support chip select output + parameter USE_DM_PORT = 1, // Support data mask output + parameter USE_ODT_PORT = 1, // Support ODT output + parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option + parameter LP_DDR_CK_WIDTH = 2, + + // Hard PHY parameters + parameter PHYCTL_CMD_FIFO = "FALSE", + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter PHY_0_BITLANES = 48'h0000_0000_0000, + parameter PHY_1_BITLANES = 48'h0000_0000_0000, + parameter PHY_2_BITLANES = 48'h0000_0000_0000, + // Parameters calculated outside of this block + parameter HIGHEST_BANK = 3, // Highest I/O bank index + parameter HIGHEST_LANE = 12, // Highest byte lane index + // ** Pin mapping parameters + // Parameters for mapping between hard PHY and physical DDR3 signals + // There are 2 classes of parameters: + // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of + // 8-bit elements. Each element indicates the bank and byte lane + // location of that particular signal. The bit lane in this case + // doesn't need to be specified, either because there's only one + // pin pair in each byte lane that the DQS or CK pair can be + // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte + // lane needs to be specified in order to determine which byte + // lane generates the RCLK (Note that CKE, and ODT must be located + // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) + // [7:4] = bank # (0-4) + // [3:0] = byte lane # (0-3) + // - All other MAP parameters: These consist of 12-bit elements. Each + // element indicates the bank, byte lane, and bit lane location of + // that particular signal: + // [11:8] = bank # (0-4) + // [7:4] = byte lane # (0-3) + // [3:0] = bit lane # (0-11) + // Note that not all elements in all parameters will be used - it + // depends on the actual widths of the DDR3 buses. The parameters are + // structured to support a maximum of: + // - DQS groups: 18 + // - data mask bits: 18 + // In addition, the default parameter size of some of the parameters will + // support a certain number of bits, however, this can be expanded at + // compile time by expanding the width of the vector passed into this + // parameter + // - chip selects: 10 + // - bank bits: 3 + // - address bits: 16 + parameter CK_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter ADDR_MAP + = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, + parameter BANK_MAP = 36'h000_000_000, + parameter CAS_MAP = 12'h000, + parameter CKE_ODT_BYTE_MAP = 8'h00, + parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, + parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, + parameter CKE_ODT_AUX = "FALSE", + parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, + parameter PARITY_MAP = 12'h000, + parameter RAS_MAP = 12'h000, + parameter WE_MAP = 12'h000, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + // DATAx_MAP parameter is used for byte lane X in the design + parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, + // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] + parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, + parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, + // Simulation options + parameter SIM_CAL_OPTION = "NONE", + + // The PHY_CONTROL primitive in the bank where PLL exists is declared + // as the Master PHY_CONTROL. + parameter MASTER_PHY_CTL = 1, + parameter DRAM_WIDTH = 8, + parameter PI_DIV2_INCDEC = "FALSE" + ) + ( + input rst, + input iddr_rst, + input clk, + input clk_div2, + input freq_refclk, + input mem_refclk, + input pll_lock, + input sync_pulse, + input mmcm_ps_clk, + input idelayctrl_refclk, + input phy_cmd_wr_en, + input phy_data_wr_en, + input [31:0] phy_ctl_wd, + input phy_ctl_wr, + input phy_if_empty_def, + input phy_if_reset, + input [5:0] data_offset_1, + input [5:0] data_offset_2, + input [3:0] aux_in_1, + input [3:0] aux_in_2, + output [4:0] idelaye2_init_val, + output [5:0] oclkdelay_init_val, + output if_empty, + output phy_ctl_full, + output phy_cmd_full, + output phy_data_full, + output phy_pre_data_a_full, + output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, + output phy_mc_go, + input phy_write_calib, + input phy_read_calib, + input calib_in_common, + input [5:0] calib_sel, + input [DQS_CNT_WIDTH:0] byte_sel_cnt, + input [DRAM_WIDTH-1:0] fine_delay_incdec_pb, + input fine_delay_sel, + input [HIGHEST_BANK-1:0] calib_zero_inputs, + input [HIGHEST_BANK-1:0] calib_zero_ctrl, + input [2:0] po_fine_enable, + input [2:0] po_coarse_enable, + input [2:0] po_fine_inc, + input [2:0] po_coarse_inc, + input po_counter_load_en, + input po_counter_read_en, + input [2:0] po_sel_fine_oclk_delay, + input [8:0] po_counter_load_val, + output [8:0] po_counter_read_val, + output [5:0] pi_counter_read_val, + input [HIGHEST_BANK-1:0] pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input [5:0] pi_counter_load_val, + input idelay_ce, + input idelay_inc, + input idelay_ld, + input idle, + output pi_phase_locked, + output pi_phase_locked_all, + output pi_dqs_found, + output pi_dqs_found_all, + output pi_dqs_out_of_range, + // From/to calibration logic/soft PHY + input phy_init_data_sel, + input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, + input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, + input [nCK_PER_CLK-1:0] mux_cas_n, + input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, + input [nCK_PER_CLK-1:0] mux_ras_n, + input [1:0] mux_odt, + input [nCK_PER_CLK-1:0] mux_cke, + input [nCK_PER_CLK-1:0] mux_we_n, + input [nCK_PER_CLK-1:0] parity_in, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, + input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, + input mux_reset_n, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + // Memory I/F + output [ROW_WIDTH-1:0] ddr_addr, + output [BANK_WIDTH-1:0] ddr_ba, + output ddr_cas_n, + output [CKE_WIDTH-1:0] ddr_cke, + output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, + output [DM_WIDTH-1:0] ddr_dm, + output [ODT_WIDTH-1:0] ddr_odt, + output ddr_parity, + output ddr_ras_n, + output ddr_we_n, + output ddr_reset_n, + inout [DQ_WIDTH-1:0] ddr_dq, + inout [DQS_WIDTH-1:0] ddr_dqs, + inout [DQS_WIDTH-1:0] ddr_dqs_n, + //output iodelay_ctrl_rdy, + output pd_out + + ,input dbg_pi_counter_read_en + ,output ref_dll_lock + ,input rst_phaser_ref + ,output [11:0] dbg_pi_phase_locked_phy4lanes + ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes + ); + + function [71:0] generate_bytelanes_ddr_ck; + input [143:0] ck_byte_map; + integer v ; + begin + generate_bytelanes_ddr_ck = 'b0 ; + for (v = 0; v < CK_WIDTH; v = v + 1) begin + if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) + generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; + else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) + generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; + else + generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; + end + end + endfunction + + function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; + input [143:0] ck_byte_map; + integer g; + begin + generate_ddr_ck_map = 'b0 ; + for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin + generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : + (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : + (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; + generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : + (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location + end + end + endfunction + + + + // Enable low power mode for input buffer + localparam IBUF_LOW_PWR + = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : + ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); + + // Ratio of data to strobe + localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; + // number of data phases per internal clock + localparam PHASE_PER_CLK = 2*nCK_PER_CLK; + // used to determine routing to OUT_FIFO for control/address for 2:1 + // vs. 4:1 memory:internal clock ratio modes + localparam PHASE_DIV = 4 / nCK_PER_CLK; + + localparam CLK_PERIOD = tCK * nCK_PER_CLK; + + // Create an aggregate parameters for data mapping to reduce # of generate + // statements required in remapping code. Need to account for the case + // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP + // parameter will have fewer than 8 elements used + localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], + DATA16_MAP[12*DQ_PER_DQS-1:0], + DATA15_MAP[12*DQ_PER_DQS-1:0], + DATA14_MAP[12*DQ_PER_DQS-1:0], + DATA13_MAP[12*DQ_PER_DQS-1:0], + DATA12_MAP[12*DQ_PER_DQS-1:0], + DATA11_MAP[12*DQ_PER_DQS-1:0], + DATA10_MAP[12*DQ_PER_DQS-1:0], + DATA9_MAP[12*DQ_PER_DQS-1:0], + DATA8_MAP[12*DQ_PER_DQS-1:0], + DATA7_MAP[12*DQ_PER_DQS-1:0], + DATA6_MAP[12*DQ_PER_DQS-1:0], + DATA5_MAP[12*DQ_PER_DQS-1:0], + DATA4_MAP[12*DQ_PER_DQS-1:0], + DATA3_MAP[12*DQ_PER_DQS-1:0], + DATA2_MAP[12*DQ_PER_DQS-1:0], + DATA1_MAP[12*DQ_PER_DQS-1:0], + DATA0_MAP[12*DQ_PER_DQS-1:0]}; + // Same deal, but for data mask mapping + localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; + localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; + localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; + + // Temporary parameters to determine which bank is outputting the CK/CK# + // Eventually there will be support for multiple CK/CK# output + //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); + //// Temporary method to force MC_PHY to generate ODDR associated with + //// CK/CK# output only for a single byte lane in the design. All banks + //// that won't be generating the CK/CK# will have "UNUSED" as their + //// PHY_GENERATE_DDR_CK parameter + //localparam TMP_PHY_0_GENERATE_DDR_CK + // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : + // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : + // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : + // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); + //localparam TMP_PHY_1_GENERATE_DDR_CK + // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : + // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : + // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : + // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); + //localparam TMP_PHY_2_GENERATE_DDR_CK + // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : + // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : + // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : + // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); + + // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx + // which indicates which bit lanes in data byte lanes are + // output-only bitlanes (e.g. used specifically for data mask outputs) + function [143:0] calc_phy_bitlanes_outonly; + input [215:0] data_mask_in; + integer z; + begin + calc_phy_bitlanes_outonly = 'b0; + // Only enable BITLANES parameters for data masks if, well, if + // the data masks are actually enabled + if (USE_DM_PORT == 1) + for (z = 0; z < DM_WIDTH; z = z + 1) + calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + + 12*data_mask_in[(12*z+4)+:2] + + data_mask_in[12*z+:4]] = 1'b1; + end + endfunction + + localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); + localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; + localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; + localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; + + // Determine which bank and byte lane generates the RCLK used to clock + // out the auxilliary (ODT, CKE) outputs + localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON + = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : + ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); + localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON + = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : + ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : + ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : + ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); + + localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF + = (CKE_MAP[11:8] == 4'h0) ? 0 : + ((CKE_MAP[11:8] == 4'h1) ? 1 : + ((CKE_MAP[11:8] == 4'h2) ? 2 : + ((CKE_MAP[11:8] == 4'h3) ? 3 : + ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); + localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF + = (CKE_MAP[7:4] == 4'h0) ? "A" : + ((CKE_MAP[7:4] == 4'h1) ? "B" : + ((CKE_MAP[7:4] == 4'h2) ? "C" : + ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); + + + localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; + localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; + + + //*************************************************************************** + // OCLKDELAYED tap setting calculation: + // Parameters for calculating amount of phase shifting output clock to + // achieve 90 degree offset between DQS and DQ on writes + //*************************************************************************** + + //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz + // and 1.25 for Mem_RefClk > 300 MHz + //localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK >= 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";//DIV2 change + localparam PO_OCLKDELAY_INV = (tCK >= 2500) ? "FALSE" : "TRUE";//DIV2 change + + //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, + //DIV4: MemRefClk < 200 MHz + localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : + tCK >= 2500 ? "DIV2": "NONE";//DIV2 change + + localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : + PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); + + // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output + localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; + + // Whether OCLK_DELAY output comes inverted or not + localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); + + // Phaser-Out Stage3 Tap delay for 90 deg shift. + // Maximum tap delay is FreqRefClk period distributed over 64 taps + // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; + localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - + (INT_DELAY + HALF_CYCLE_DELAY)) + * 63 * FREQ_REF_DIV; + //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; + + localparam integer PHY_0_A_PO_OCLK_DELAY_HW + = (tCK > 2273) ? 34 : + (tCK > 2000) ? 33 : + (tCK > 1724) ? 32 : + (tCK > 1515) ? 31 : + (tCK > 1315) ? 30 : + (tCK > 1136) ? 29 : + (tCK > 1021) ? 28 : 27; + + // Note that simulation requires a different value than in H/W because of the + // difference in the way delays are modeled + localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? // DIV2 change + ((tCK >= 2500) ? 0 : + (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : + (tCK >= 2500) ? 0 : MC_OCLK_DELAY; + + // Initial DQ IDELAY value + localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : + (tCK < 1000) ? 0 : + (tCK < 1330) ? 0 : + (tCK < 2300) ? 0 : + (tCK < 2500) ? 2 : 0; + //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; + + // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? + localparam PHY_0_RD_CMD_OFFSET_0 = 10; + localparam PHY_0_RD_CMD_OFFSET_1 = 10; + localparam PHY_0_RD_CMD_OFFSET_2 = 10; + localparam PHY_0_RD_CMD_OFFSET_3 = 10; + // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing + localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; + localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; + localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; + localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; + // 4:1 and 2:1 have different values + localparam PHY_0_WR_DURATION_0 = 7; + localparam PHY_0_WR_DURATION_1 = 7; + localparam PHY_0_WR_DURATION_2 = 7; + localparam PHY_0_WR_DURATION_3 = 7; + // Aux_out parameters for toggle mode (CKE) + localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; + localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : + (CWL < 7) ? + 4 + ((CWL_M % 2) ? 0 : 1) : + 5 + ((CWL_M % 2) ? 0 : 1); + + // temporary parameter to enable/disable PHY PC counters. In both 4:1 and + // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to + // avoid making too many changes at once. + localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; + + + wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; + wire [HIGHEST_LANE-1:0] mem_dqs_in; + wire [HIGHEST_LANE-1:0] mem_dqs_out; + wire [HIGHEST_LANE-1:0] mem_dqs_ts; + wire [HIGHEST_LANE*10-1:0] mem_dq_in; + wire [HIGHEST_LANE*12-1:0] mem_dq_out; + wire [HIGHEST_LANE*12-1:0] mem_dq_ts; + wire [DQ_WIDTH-1:0] in_dq; + wire [DQS_WIDTH-1:0] in_dqs; + wire [ROW_WIDTH-1:0] out_addr; + wire [BANK_WIDTH-1:0] out_ba; + wire out_cas_n; + wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; + wire [DM_WIDTH-1:0] out_dm; + wire [ODT_WIDTH -1:0] out_odt; + wire [CKE_WIDTH -1 :0] out_cke ; + wire [DQ_WIDTH-1:0] out_dq; + wire [DQS_WIDTH-1:0] out_dqs; + wire out_parity; + wire out_ras_n; + wire out_we_n; + wire [HIGHEST_LANE*80-1:0] phy_din; + wire [HIGHEST_LANE*80-1:0] phy_dout; + wire phy_rd_en; + wire [DM_WIDTH-1:0] ts_dm; + wire [DQ_WIDTH-1:0] ts_dq; + wire [DQS_WIDTH-1:0] ts_dqs; + wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr; + wire [DQS_WIDTH-1:0] pd_out_pre; + //wire metaQ; + + reg [31:0] phy_ctl_wd_i1; + reg [31:0] phy_ctl_wd_i2; + reg phy_ctl_wr_i1; + reg phy_ctl_wr_i2; + reg [5:0] data_offset_1_i1; + reg [5:0] data_offset_1_i2; + reg [5:0] data_offset_2_i1; + reg [5:0] data_offset_2_i2; + wire [31:0] phy_ctl_wd_temp; + wire phy_ctl_wr_temp; + wire [5:0] data_offset_1_temp; + wire [5:0] data_offset_2_temp; + wire [5:0] data_offset_1_of; + wire [5:0] data_offset_2_of; + wire [31:0] phy_ctl_wd_of; + wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; + wire [3:0] phy_ctl_full_temp; + + wire data_io_idle_pwrdwn; + reg [29:0] fine_delay_mod; //3 bit per DQ + reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb + + wire iddr_rst_i; + + (* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1; + + // Always read from input data FIFOs when not empty + assign phy_rd_en = !if_empty; + + // IDELAYE2 initial value + assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; + assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; + + // Idle powerdown when there are no pending reads in the MC + assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; + assign iddr_rst_i = iddr_rst; + //*************************************************************************** + // Auxiliary output steering + //*************************************************************************** + + // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be + // mapped to ddr_odt and the aux_out[7:4] from one of the data banks + // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the + // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. + generate + if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins + if (CKE_WIDTH == 1) begin : gen_cke + // Explicitly instantiate OBUF to ensure that these are present + // in the netlist. Typically this is not required since NGDBUILD + // at the top-level knows to infer an I/O/IOBUF and therefore a + // top-level LOC constraint can be attached to that pin. This does + // not work when a hierarchical flow is used and the LOC is applied + // at the individual core-level UCF + OBUF u_cke_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), + .O (ddr_cke) + ); + end else begin: gen_2rank_cke + OBUF u_cke0_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), + .O (ddr_cke[0]) + ); + OBUF u_cke1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), + .O (ddr_cke[1]) + ); + end + end + endgenerate + + generate + if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins + if (USE_ODT_PORT == 1) begin : gen_use_odt + // Explicitly instantiate OBUF to ensure that these are present + // in the netlist. Typically this is not required since NGDBUILD + // at the top-level knows to infer an I/O/IOBUF and therefore a + // top-level LOC constraint can be attached to that pin. This does + // not work when a hierarchical flow is used and the LOC is applied + // at the individual core-level UCF + OBUF u_odt_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), + .O (ddr_odt[0]) + ); + if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt + OBUF u_odt1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), + .O (ddr_odt[1]) + ); + end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt + OBUF u_odt1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), + .O (ddr_odt[1]) + ); + end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt + OBUF u_odt1_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), + .O (ddr_odt[1]) + ); + OBUF u_odt2_obuf + ( + .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), + .O (ddr_odt[2]) + ); + end + end else begin + assign ddr_odt = 'b0; + end + end + endgenerate + + //*************************************************************************** + // Read data bit steering + //*************************************************************************** + + // Transpose elements of rd_data_map to form final read data output: + // phy_din elements are grouped according to "physical bit" - e.g. + // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical + // bit per clock cycle: + // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, + // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} + // whereas rd_data is are grouped according to "phase" - e.g. + // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, + // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} + // therefore rd_data is formed by transposing phy_din - e.g. + // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY + // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then + // the assignments for bits of rd_data corresponding to DQ[1:0] + // would be: + // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], + // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] + // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], + // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] + generate + genvar i, j; + for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 + for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 + assign rd_data[DQ_WIDTH*j + i] + = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ + 80*FULL_DATA_MAP[(12*i+4)+:2] + + 8*FULL_DATA_MAP[12*i+:4]) + j]; + end + end + endgenerate + + //generage idelay_inc per bits + + reg [11:0] cal_tmp; + reg [95:0] byte_sel_data_map; + + assign byte_sel_cnt_w1 = byte_sel_cnt; + + always @ (posedge clk) begin + byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96]; + end + + always @ (posedge clk) begin + fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00}; + fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00}; + fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00}; + fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00}; + fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00}; + fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00}; + fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00}; + fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00}; + fine_delay_sel_r <= #TCQ fine_delay_sel; + end + + //*************************************************************************** + // Control/address + //*************************************************************************** + + assign out_cas_n + = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; + + generate + // if signal placed on bit lanes [0-9] + if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 + // Determine routing based on clock ratio mode. If running in 4:1 + // mode, then all four bits from logic are used. If 2:1 mode, only + // 2-bits are provided by logic, and each bit is repeated 2x to form + // 4-bit input to IN_FIFO, e.g. + // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} + // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} + assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + + 8*CAS_MAP[3:0])+:4] + = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], + mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; + end else begin: gen_cas_ge10 + // If signal is placed in bit lane [10] or [11], route to upper + // nibble of phy_dout lane [5] or [6] respectively (in this case + // phy_dout lane [5, 6] are multiplexed to take input for two + // different SDR signals - this is how bits[10,11] need to be + // provided to the OUT_FIFO + assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + + 8*(CAS_MAP[3:0]-5) + 4)+:4] + = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], + mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; + end + endgenerate + + assign out_ras_n + = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; + + generate + if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 + assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + + 8*RAS_MAP[3:0])+:4] + = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], + mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; + end else begin: gen_ras_ge10 + assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + + 8*(RAS_MAP[3:0]-5) + 4)+:4] + = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], + mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; + end + endgenerate + + assign out_we_n + = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; + + generate + if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 + assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + + 8*WE_MAP[3:0])+:4] + = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], + mux_we_n[1/PHASE_DIV], mux_we_n[0]}; + end else begin: gen_we_ge10 + assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + + 8*(WE_MAP[3:0]-5) + 4)+:4] + = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], + mux_we_n[1/PHASE_DIV], mux_we_n[0]}; + end + endgenerate + + generate + if (REG_CTRL == "ON") begin: gen_parity_out + // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs + assign out_parity + = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + + PARITY_MAP[3:0]]; + if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 + assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + + 8*PARITY_MAP[3:0])+:4] + = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], + parity_in[1/PHASE_DIV], parity_in[0]}; + end else begin: gen_ge10 + assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + + 8*(PARITY_MAP[3:0]-5) + 4)+:4] + = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], + parity_in[1/PHASE_DIV], parity_in[0]}; + end + end + endgenerate + + //***************************************************************** + + generate + genvar m, n,x; + + //***************************************************************** + // Control/address (multi-bit) buses + //***************************************************************** + + // Row/Column address + for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out + assign out_addr[m] + = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + + 12*ADDR_MAP[(12*m+4)+:2] + + ADDR_MAP[12*m+:4]]; + + if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + // For multi-bit buses, we also have to deal with transposition + // when going from the logic-side control bus to phy_dout + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + + 80*ADDR_MAP[(12*m+4)+:2] + + 8*ADDR_MAP[12*m+:4] + n] + = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + + 80*ADDR_MAP[(12*m+4)+:2] + + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] + = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + + // Bank address + for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out + assign out_ba[m] + = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + + 12*BANK_MAP[(12*m+4)+:2] + + BANK_MAP[12*m+:4]]; + + if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + + 80*BANK_MAP[(12*m+4)+:2] + + 8*BANK_MAP[12*m+:4] + n] + = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + + 80*BANK_MAP[(12*m+4)+:2] + + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] + = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + + // Chip select + if (USE_CS_PORT == 1) begin: gen_cs_n_out + for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out + assign out_cs_n[m] + = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + + 12*CS_MAP[(12*m+4)+:2] + + CS_MAP[12*m+:4]]; + if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CS_MAP[(12*m+8)+:3] + + 80*CS_MAP[(12*m+4)+:2] + + 8*CS_MAP[12*m+:4] + n] + = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CS_MAP[(12*m+8)+:3] + + 80*CS_MAP[(12*m+4)+:2] + + 8*(CS_MAP[12*m+:4]-5) + 4 + n] + = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; + end + end + end + end + + + if(CKE_ODT_AUX == "FALSE") begin + // ODT_ports + wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; + + if(RANKS == 1) begin + for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin + assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; + end + end else begin + for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin + assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; + assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; + end + end + + if (USE_ODT_PORT == 1) begin: gen_odt_out + for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 + assign out_odt[m] + = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + + 12*ODT_MAP[(12*m+4)+:2] + + ODT_MAP[12*m+:4]]; + if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + + 80*ODT_MAP[(12*m+4)+:2] + + 8*ODT_MAP[12*m+:4] + n] + = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + + 80*ODT_MAP[(12*m+4)+:2] + + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] + = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + end + + + wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; + + for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin + assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; + end + + + + for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out + assign out_cke[m] + = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + + 12*CKE_MAP[(12*m+4)+:2] + + CKE_MAP[12*m+:4]]; + if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + + 80*CKE_MAP[(12*m+4)+:2] + + 8*CKE_MAP[12*m+:4] + n] + = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; + end + end else begin: gen_ge10 + for (n = 0; n < 4; n = n + 1) begin: loop_xpose + assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + + 80*CKE_MAP[(12*m+4)+:2] + + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] + = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; + end + end + end + end + + //***************************************************************** + // Data mask + //***************************************************************** + + if (USE_DM_PORT == 1) begin: gen_dm_out + for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out + assign out_dm[m] + = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + + 12*FULL_MASK_MAP[(12*m+4)+:2] + + FULL_MASK_MAP[12*m+:4]]; + assign ts_dm[m] + = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + + 12*FULL_MASK_MAP[(12*m+4)+:2] + + FULL_MASK_MAP[12*m+:4]]; + for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose + assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + + 80*FULL_MASK_MAP[(12*m+4)+:2] + + 8*FULL_MASK_MAP[12*m+:4] + n] + = mux_wrdata_mask[DM_WIDTH*n + m]; + end + end + end + + //***************************************************************** + // Input and output DQ + //***************************************************************** + + for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout + // to MC_PHY + assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + + 10*FULL_DATA_MAP[(12*m+4)+:2] + + FULL_DATA_MAP[12*m+:4]] + = in_dq[m]; + // to I/O buffers + assign out_dq[m] + = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + + 12*FULL_DATA_MAP[(12*m+4)+:2] + + FULL_DATA_MAP[12*m+:4]]; + assign ts_dq[m] + = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + + 12*FULL_DATA_MAP[(12*m+4)+:2] + + FULL_DATA_MAP[12*m+:4]]; + for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose + assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + + 80*FULL_DATA_MAP[(12*m+4)+:2] + + 8*FULL_DATA_MAP[12*m+:4] + n] + = mux_wrdata[DQ_WIDTH*n + m]; + end + end + + //***************************************************************** + // Input and output DQS + //***************************************************************** + + for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout + // to MC_PHY + assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] + = in_dqs[m]; + // to I/O buffers + assign out_dqs[m] + = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; + assign ts_dqs[m] + = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; + end + endgenerate + + assign pd_out = pd_out_pre[byte_sel_cnt_w1]; + + + //*************************************************************************** + // Memory I/F output and I/O buffer instantiation + //*************************************************************************** + + // Note on instantiation - generally at the minimum, it's not required to + // instantiate the output buffers - they can be inferred by the synthesis + // tool, and there aren't any attributes that need to be associated with + // them. Consider as a future option to take out the OBUF instantiations + + OBUF u_cas_n_obuf + ( + .I (out_cas_n), + .O (ddr_cas_n) + ); + + OBUF u_ras_n_obuf + ( + .I (out_ras_n), + .O (ddr_ras_n) + ); + + OBUF u_we_n_obuf + ( + .I (out_we_n), + .O (ddr_we_n) + ); + + generate + genvar p; + + for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf + OBUF u_addr_obuf + ( + .I (out_addr[p]), + .O (ddr_addr[p]) + ); + end + + for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf + OBUF u_bank_obuf + ( + .I (out_ba[p]), + .O (ddr_ba[p]) + ); + end + + if (USE_CS_PORT == 1) begin: gen_cs_n_obuf + for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf + OBUF u_cs_n_obuf + ( + .I (out_cs_n[p]), + .O (ddr_cs_n[p]) + ); + end + end + if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo + if (USE_ODT_PORT== 1) begin: gen_odt_obuf + for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf + OBUF u_cs_n_obuf + ( + .I (out_odt[p]), + .O (ddr_odt[p]) + ); + end + end + for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf + OBUF u_cs_n_obuf + ( + .I (out_cke[p]), + .O (ddr_cke[p]) + ); + end + end + + if (REG_CTRL == "ON") begin: gen_parity_obuf + // Generate addr/ctrl parity output only for DDR3 registered DIMMs + OBUF u_parity_obuf + ( + .I (out_parity), + .O (ddr_parity) + ); + end else begin: gen_parity_tieoff + assign ddr_parity = 1'b0; + end + + if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf + // Generate reset output only for DDR3 and DDR2 RDIMMs + OBUF u_reset_obuf + ( + .I (mux_reset_n), + .O (ddr_reset_n) + ); + end else begin: gen_reset_tieoff + assign ddr_reset_n = 1'b1; + end + + if (USE_DM_PORT == 1) begin: gen_dm_obuf + for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm + OBUFT u_dm_obuf + ( + .I (out_dm[p]), + .T (ts_dm[p]), + .O (ddr_dm[p]) + ); + end + end else begin: gen_dm_tieoff + assign ddr_dm = 'b0; + end + + if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP + for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf + IOBUF_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dq + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dq[p]), + .T (ts_dq[p]), + .O (in_dq[p]), + .IO (ddr_dq[p]) + ); + end + end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR + for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf + IOBUF_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dq + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dq[p]), + .T (ts_dq[p]), + .O (in_dq[p]), + .IO (ddr_dq[p]) + ); + end + end else begin: gen_dq_iobuf_default + for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf + IOBUF # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dq + ( + .I (out_dq[p]), + .T (ts_dq[p]), + .O (in_dq[p]), + .IO (ddr_dq[p]) + ); + end + end + + //if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP + if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP + for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf + if ((DRAM_TYPE == "DDR2") && + (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se + IOBUF_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dqs + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]) + ); + assign ddr_dqs_n[p] = 1'b0; + assign pd_out_pre[p] = 1'b0; + end else if ((DRAM_TYPE == "DDR2") || + (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff + IOBUFDS_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE") + ) + u_iobuf_dqs + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + assign pd_out_pre[p] = 1'b0; + end else begin: gen_dqs_diff + IOBUFDS_DIFF_OUT_DCIEN # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE"), + .SIM_DEVICE ("7SERIES"), + .USE_IBUFDISABLE ("FALSE") + ) + u_iobuf_dqs + ( + .DCITERMDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .TM (ts_dqs[p]), + .TS (ts_dqs[p]), + .OB (in_dqs_lpbk_to_iddr[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + + mig_7series_v4_2_poc_pd # + ( + .TCQ (TCQ), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) + ) + u_iddr_edge_det + ( + .clk (clk), + .iddr_rst (iddr_rst_i), + .kclk (in_dqs_lpbk_to_iddr[p]), + .mmcm_ps_clk (mmcm_ps_clk), + .pd_out (pd_out_pre[p]) + ); + end + end + //end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR + end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR + for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf + if ((DRAM_TYPE == "DDR2") && + (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se + IOBUF_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dqs + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]) + ); + assign ddr_dqs_n[p] = 1'b0; + assign pd_out_pre[p] = 1'b0; + end else if ((DRAM_TYPE == "DDR2") || + (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff + IOBUFDS_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE") + ) + u_iobuf_dqs + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + .IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + assign pd_out_pre[p] = 1'b0; + end else begin: gen_dqs_diff + IOBUFDS_DIFF_OUT_INTERMDISABLE # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE"), + .SIM_DEVICE ("7SERIES"), + .USE_IBUFDISABLE ("FALSE") + ) + u_iobuf_dqs + ( + .INTERMDISABLE (data_io_idle_pwrdwn), + //.IBUFDISABLE (data_io_idle_pwrdwn), + .I (out_dqs[p]), + .TM (ts_dqs[p]), + .TS (ts_dqs[p]), + .OB (in_dqs_lpbk_to_iddr[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + + mig_7series_v4_2_poc_pd # + ( + .TCQ (TCQ), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) + ) + u_iddr_edge_det + ( + .clk (clk), + .iddr_rst (iddr_rst_i), + .kclk (in_dqs_lpbk_to_iddr[p]), + .mmcm_ps_clk (mmcm_ps_clk), + .pd_out (pd_out_pre[p]) + ); + end + end + end else begin: gen_dqs_iobuf_default + for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf + if ((DRAM_TYPE == "DDR2") && + (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se + IOBUF # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR) + ) + u_iobuf_dqs + ( + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]) + ); + assign ddr_dqs_n[p] = 1'b0; + assign pd_out_pre[p] = 1'b0; + end else begin: gen_dqs_diff + IOBUFDS # + ( + .IBUF_LOW_PWR (IBUF_LOW_PWR), + .DQS_BIAS ("TRUE") + ) + u_iobuf_dqs + ( + .I (out_dqs[p]), + .T (ts_dqs[p]), + .O (in_dqs[p]), + .IO (ddr_dqs[p]), + .IOB (ddr_dqs_n[p]) + ); + assign pd_out_pre[p] = 1'b0; + end + end + end + + endgenerate + + always @(posedge clk) begin + phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; + phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; + phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; + phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; + data_offset_1_i1 <= #TCQ data_offset_1; + data_offset_1_i2 <= #TCQ data_offset_1_i1; + data_offset_2_i1 <= #TCQ data_offset_2; + data_offset_2_i2 <= #TCQ data_offset_2_i1; + end + + + // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. + // 2:1 mode the command goes through pre fifo + assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; + assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; + assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; + assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; + + generate + begin + + mig_7series_v4_2_ddr_of_pre_fifo # + ( + .TCQ (25), + .DEPTH (8), + .WIDTH (32) + ) + phy_ctl_pre_fifo_0 + ( + .clk (clk), + .rst (rst), + .full_in (phy_ctl_full_temp[1]), + .wr_en_in (phy_ctl_wr), + .d_in (phy_ctl_wd), + .wr_en_out (phy_ctl_wr_of), + .d_out (phy_ctl_wd_of) + ); + + mig_7series_v4_2_ddr_of_pre_fifo # + ( + .TCQ (25), + .DEPTH (8), + .WIDTH (6) + ) + phy_ctl_pre_fifo_1 + ( + .clk (clk), + .rst (rst), + .full_in (phy_ctl_full_temp[2]), + .wr_en_in (phy_ctl_wr), + .d_in (data_offset_1), + .wr_en_out (), + .d_out (data_offset_1_of) + ); + + mig_7series_v4_2_ddr_of_pre_fifo # + ( + .TCQ (25), + .DEPTH (8), + .WIDTH (6) + ) + phy_ctl_pre_fifo_2 + ( + .clk (clk), + .rst (rst), + .full_in (phy_ctl_full_temp[3]), + .wr_en_in (phy_ctl_wr), + .d_in (data_offset_2), + .wr_en_out (), + .d_out (data_offset_2_of) + ); + + end + endgenerate + + + + //*************************************************************************** + // Hard PHY instantiation + //*************************************************************************** + + assign phy_ctl_full = phy_ctl_full_temp[0]; + + mig_7series_v4_2_ddr_mc_phy # + ( + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), + .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), + .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), + .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), + .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), + //.CKE_ODT_AUX (CKE_ODT_AUX), + .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), + .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), + .NUM_DDR_CK (CK_WIDTH), + .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), + .PO_CTL_COARSE_BYPASS ("FALSE"), + .PHYCTL_CMD_FIFO ("FALSE"), + .PHY_CLK_RATIO (nCK_PER_CLK), + .MASTER_PHY_CTL (MASTER_PHY_CTL), + .PHY_FOUR_WINDOW_CLOCKS (63), + .PHY_EVENTS_DELAY (18), + .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN + .PHY_SYNC_MODE ("FALSE"), + .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), + .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" + .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), + .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), + .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE + .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), + .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), + .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), + .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), + .PHY_0_RD_DURATION_0 (6), + .PHY_0_RD_DURATION_1 (6), + .PHY_0_RD_DURATION_2 (6), + .PHY_0_RD_DURATION_3 (6), + .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), + .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), + .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), + .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), + .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), + .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), + .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), + .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), + .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), + .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), + .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), + //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), + //.PHY_1_NUM_DDR_CK (1), + .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), + //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), + //.PHY_2_NUM_DDR_CK (1), + .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), + .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), + .TCK (tCK), + .PHY_0_IODELAY_GRP (IODELAY_GRP), + .PHY_1_IODELAY_GRP (IODELAY_GRP), + .PHY_2_IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .CKE_ODT_AUX (CKE_ODT_AUX), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_mc_phy + ( + .rst (rst), + // Don't use MC_PHY to generate DDR_RESET_N output. Instead + // generate this output outside of MC_PHY (and synchronous to CLK) + .ddr_rst_in_n (1'b1), + .phy_clk (clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + // Remove later - always same connection as phy_clk port + .mem_refclk_div4 (clk), + .pll_lock (pll_lock), + .auxout_clk (), + .sync_pulse (sync_pulse), + // IDELAYCTRL instantiated outside of mc_phy module + .idelayctrl_refclk (), + .phy_dout (phy_dout), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phy_ctl_wd (phy_ctl_wd_temp), + .phy_ctl_wr (phy_ctl_wr_temp), + .if_empty_def (phy_if_empty_def), + .if_rst (phy_if_reset), + .phyGo ('b1), + .aux_in_1 (aux_in_1), + .aux_in_2 (aux_in_2), + // No support yet for different data offsets for different I/O banks + // (possible use in supporting wider range of skew among bytes) + .data_offset_1 (data_offset_1_temp), + .data_offset_2 (data_offset_2_temp), + .cke_in (), + .if_a_empty (), + .if_empty (if_empty), + .if_empty_or (), + .if_empty_and (), + .of_ctl_a_full (), + // .of_data_a_full (phy_data_full), + .of_ctl_full (phy_cmd_full), + .of_data_full (), + .pre_data_a_full (phy_pre_data_a_full), + .idelay_ld (idelay_ld), + .idelay_ce (idelay_ce), + .idelay_inc (idelay_inc), + .input_sink (), + .phy_din (phy_din), + .phy_ctl_a_full (), + .phy_ctl_full (phy_ctl_full_temp), + .mem_dq_out (mem_dq_out), + .mem_dq_ts (mem_dq_ts), + .mem_dq_in (mem_dq_in), + .mem_dqs_out (mem_dqs_out), + .mem_dqs_ts (mem_dqs_ts), + .mem_dqs_in (mem_dqs_in), + .aux_out (aux_out), + .phy_ctl_ready (), + .rst_out (), + .ddr_clk (ddr_clk), + //.rclk (), + .mcGo (phy_mc_go), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), + .calib_sel (calib_sel), + .calib_in_common (calib_in_common), + .calib_zero_inputs (calib_zero_inputs), + .calib_zero_ctrl (calib_zero_ctrl), + .calib_zero_lanes ('b0), + .po_fine_enable (po_fine_enable), + .po_coarse_enable (po_coarse_enable), + .po_fine_inc (po_fine_inc), + .po_coarse_inc (po_coarse_inc), + .po_counter_load_en (po_counter_load_en), + .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), + .po_counter_load_val (po_counter_load_val), + .po_counter_read_en (po_counter_read_en), + .po_coarse_overflow (), + .po_fine_overflow (), + .po_counter_read_val (po_counter_read_val), + .pi_rst_dqs_find (pi_rst_dqs_find), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_read_en (dbg_pi_counter_read_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_fine_overflow (), + .pi_counter_read_val (pi_counter_read_val), + .pi_phase_locked (pi_phase_locked), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_dqs_found (), + .pi_dqs_found_any (pi_dqs_found), + .pi_dqs_found_all (pi_dqs_found_all), + .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), + // Currently not being used. May be used in future if periodic + // reads become a requirement. This output could be used to signal + // a catastrophic failure in read capture and the need for + // re-calibration. + .pi_dqs_out_of_range (pi_dqs_out_of_range) + + ,.ref_dll_lock (ref_dll_lock) + ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) + ,.fine_delay (fine_delay_mod) + ,.fine_delay_sel (fine_delay_sel_r) +// ,.rst_phaser_ref (rst_phaser_ref) + ); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v new file mode 100644 index 0000000..c7521c1 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v @@ -0,0 +1,211 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ddr_of_pre_fifo.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Feb 08 2011 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries +//Reference : +//Revision History : +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $ +**$Date: 2011/06/02 08:35:07 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $ +******************************************************************************/ + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_ddr_of_pre_fifo # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter DEPTH = 4, // # of entries + parameter WIDTH = 32 // data bus width + ) + ( + input clk, // clock + input rst, // synchronous reset + input full_in, // FULL flag from OUT_FIFO + input wr_en_in, // write enable from controller + input [WIDTH-1:0] d_in, // write data from controller + output wr_en_out, // write enable to OUT_FIFO + output [WIDTH-1:0] d_out, // write data to OUT_FIFO + output afull // almost full signal to controller + ); + + // # of bits used to represent read/write pointers + localparam PTR_BITS + = (DEPTH == 2) ? 1 : + ((DEPTH == 3) || (DEPTH == 4)) ? 2 : + (((DEPTH == 5) || (DEPTH == 6) || + (DEPTH == 7) || (DEPTH == 8)) ? 3 : + DEPTH == 9 ? 4 : 'bx); + + // Set watermark. Always give the MC 5 cycles to engage flow control. + localparam ALMOST_FULL_VALUE = DEPTH - 5; + + integer i; + + reg [WIDTH-1:0] mem[0:DEPTH-1] ; + reg [8:0] my_empty /* synthesis syn_maxfan = 3 */; + reg [5:0] my_full /* synthesis syn_maxfan = 3 */; + reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; + reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; + (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; + (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */; + reg [PTR_BITS:0] entry_cnt; + wire [PTR_BITS-1:0] nxt_rd_ptr; + wire [PTR_BITS-1:0] nxt_wr_ptr; + wire [WIDTH-1:0] mem_out; + (* max_fanout = 50 *) wire wr_en; + + assign d_out = my_empty[0] ? d_in : mem_out; + assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in); + assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in)); + + always @ (posedge clk) + if (wr_en) + mem[wr_ptr] <= #TCQ d_in; + + assign mem_out = mem[rd_ptr]; + + assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH; + + always @ (posedge clk) + begin + if (rst) begin + rd_ptr <= 'b0; + rd_ptr_timing <= 'b0; + end + else if ((!my_empty[4]) & (!full_in)) begin + rd_ptr <= nxt_rd_ptr; + rd_ptr_timing <= nxt_rd_ptr; + end + end + + always @ (posedge clk) + begin + if (rst) + my_empty <= 9'h1ff; + else begin + if (my_empty[2] & !my_full[3] & full_in & wr_en_in) + my_empty[3:0] <= 4'b0000; + else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin + my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing); + end + if (my_empty[8] & !my_full[5] & full_in & wr_en_in) + my_empty[8:4] <= 5'b00000; + else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin + my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing); + my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing); + end + end + end + + assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH; + + always @ (posedge clk) + begin + if (rst) begin + wr_ptr <= 'b0; + wr_ptr_timing <= 'b0; + end + else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin + wr_ptr <= nxt_wr_ptr; + wr_ptr_timing <= nxt_wr_ptr; + end + end + + always @ (posedge clk) + begin + if (rst) + my_full <= 6'b000000; + else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in) + my_full <= 6'b000000; + else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin + my_full[0] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[1] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[2] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[3] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[4] <= (nxt_wr_ptr == rd_ptr_timing); + my_full[5] <= (nxt_wr_ptr == rd_ptr_timing); + end + end + + always @ (posedge clk) + begin + if (rst) + entry_cnt <= 'b0; + else if (wr_en_in & full_in & !my_full[4]) + entry_cnt <= entry_cnt + 1'b1; + else if (!wr_en_in & !full_in & !my_empty[7]) + entry_cnt <= entry_cnt - 1'b1; + end + + assign afull = (entry_cnt >= ALMOST_FULL_VALUE); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v new file mode 100644 index 0000000..4931872 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v @@ -0,0 +1,2057 @@ +/********************************************************** +-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). A Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +// +// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. +// +// +// Owner: Gary Martin +// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $ +// $Author: gary $ +// $DateTime: 2010/05/11 18:05:17 $ +// $Change: 490882 $ +// Description: +// This verilog file is the parameterizable 4-byte lane phy primitive top +// This module may be ganged to create an N-lane phy. +// +// History: +// Date Engineer Description +// 04/01/2010 G. Martin Initial Checkin. +// +/////////////////////////////////////////////////////////// +**********************************************************/ + +`timescale 1ps/1ps + +`define PC_DATA_OFFSET_RANGE 22:17 + +module mig_7series_v4_2_ddr_phy_4lanes #( +parameter GENERATE_IDELAYCTRL = "TRUE", +parameter IODELAY_GRP = "IODELAY_MIG", +parameter FPGA_SPEED_GRADE = 1, +parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" +parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010, +parameter NUM_DDR_CK = 1, +// next three parameter fields correspond to byte lanes for lane order DCBA +parameter BYTE_LANES = 4'b1111, // lane existence, one per lane +parameter DATA_CTL_N = 4'b1111, // data or control, per lane +parameter BITLANES = 48'hffff_ffff_ffff, +parameter BITLANES_OUTONLY = 48'h0000_0000_0000, +parameter LANE_REMAP = 16'h3210,// 4-bit index + // used to rewire to one of four + // input/output buss lanes + // example: 0321 remaps lanes as: + // D->A + // C->D + // B->C + // A->B +parameter LAST_BANK = "FALSE", +parameter USE_PRE_POST_FIFO = "FALSE", +parameter RCLK_SELECT_LANE = "B", +parameter real TCK = 0.00, +parameter SYNTHESIS = "FALSE", +parameter PO_CTL_COARSE_BYPASS = "FALSE", +parameter PO_FINE_DELAY = 0, +parameter PI_SEL_CLK_OFFSET = 0, + +// phy_control paramter used in other paramsters +parameter PC_CLK_RATIO = 4, + +//phaser_in parameters +parameter A_PI_FREQ_REF_DIV = "NONE", +parameter A_PI_CLKOUT_DIV = 2, +parameter A_PI_BURST_MODE = "TRUE", +parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF", +parameter A_PI_FINE_DELAY = 60, +parameter A_PI_SYNC_IN_DIV_RST = "TRUE", + +parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, +parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, +parameter B_PI_BURST_MODE = A_PI_BURST_MODE, +parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, +parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY, +parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, + +parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, +parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, +parameter C_PI_BURST_MODE = A_PI_BURST_MODE, +parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, +parameter C_PI_FINE_DELAY = 0, +parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, + +parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV, +parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV, +parameter D_PI_BURST_MODE = A_PI_BURST_MODE, +parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC, +parameter D_PI_FINE_DELAY = 0, +parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST, + +//phaser_out parameters +parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2, +parameter A_PO_FINE_DELAY = PO_FINE_DELAY, +parameter A_PO_COARSE_DELAY = 0, +parameter A_PO_OCLK_DELAY = 0, +parameter A_PO_OCLKDELAY_INV = "FALSE", +parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF", +parameter A_PO_SYNC_IN_DIV_RST = "TRUE", +//parameter A_PO_SYNC_IN_DIV_RST = "FALSE", + +parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2, +parameter B_PO_FINE_DELAY = PO_FINE_DELAY, +parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY, +parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY, +parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, +parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, +parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, + +parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2, +parameter C_PO_FINE_DELAY = PO_FINE_DELAY, +parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY, +parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY, +parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, +parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, +parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, + +parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2, +parameter D_PO_FINE_DELAY = PO_FINE_DELAY, +parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY, +parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY, +parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV, +parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC, +parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST, + +parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE", +parameter A_IDELAYE2_IDELAY_VALUE = 00, +parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, +parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, +parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, +parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, +parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE, +parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE, + + +// phy_control parameters + +parameter PC_BURST_MODE = "TRUE", +parameter PC_DATA_CTL_N = DATA_CTL_N, +parameter PC_CMD_OFFSET = 0, +parameter PC_RD_CMD_OFFSET_0 = 0, +parameter PC_RD_CMD_OFFSET_1 = 0, +parameter PC_RD_CMD_OFFSET_2 = 0, +parameter PC_RD_CMD_OFFSET_3 = 0, +parameter PC_CO_DURATION = 1, +parameter PC_DI_DURATION = 1, +parameter PC_DO_DURATION = 1, +parameter PC_RD_DURATION_0 = 0, +parameter PC_RD_DURATION_1 = 0, +parameter PC_RD_DURATION_2 = 0, +parameter PC_RD_DURATION_3 = 0, +parameter PC_WR_CMD_OFFSET_0 = 5, +parameter PC_WR_CMD_OFFSET_1 = 5, +parameter PC_WR_CMD_OFFSET_2 = 5, +parameter PC_WR_CMD_OFFSET_3 = 5, +parameter PC_WR_DURATION_0 = 6, +parameter PC_WR_DURATION_1 = 6, +parameter PC_WR_DURATION_2 = 6, +parameter PC_WR_DURATION_3 = 6, +parameter PC_AO_WRLVL_EN = 0, +parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE) +parameter PC_FOUR_WINDOW_CLOCKS = 63, +parameter PC_EVENTS_DELAY = 18, +parameter PC_PHY_COUNT_EN = "TRUE", +parameter PC_SYNC_MODE = "TRUE", +parameter PC_DISABLE_SEQ_MATCH = "TRUE", +parameter PC_MULTI_REGION = "FALSE", + +// io fifo parameters + +parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4", +parameter OF_ALMOST_EMPTY_VALUE = 1, +parameter OF_ALMOST_FULL_VALUE = 1, +parameter OF_OUTPUT_DISABLE = "TRUE", +parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE, + +parameter A_OS_DATA_RATE = "DDR", +parameter A_OS_DATA_WIDTH = 4, +parameter B_OS_DATA_RATE = A_OS_DATA_RATE, +parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH, +parameter C_OS_DATA_RATE = A_OS_DATA_RATE, +parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH, +parameter D_OS_DATA_RATE = A_OS_DATA_RATE, +parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH, + + +parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8", +parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE, +parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE, +parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE, +parameter IF_ALMOST_EMPTY_VALUE = 1, +parameter IF_ALMOST_FULL_VALUE = 1, +parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE, + + +// this is used locally, not for external pushdown +// NOTE: the 0+ is needed in each to coerce to integer for addition. +// otherwise 4x 1'b values are added producing a 1'b value. +parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1), +parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])), + +parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]), + +parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES, +// assume odt per rank + any declared cke's +parameter AUXOUT_WIDTH = 4, +parameter LP_DDR_CK_WIDTH = 2 +,parameter CKE_ODT_AUX = "FALSE" +,parameter PI_DIV2_INCDEC = "FALSE" +) +( + +//`include "phy.vh" + + input rst, + input phy_clk, + input clk_div2, + input phy_ctl_clk, + input freq_refclk, + input mem_refclk, + input mem_refclk_div4, + input pll_lock, + input sync_pulse, + input idelayctrl_refclk, + input [HIGHEST_LANE*80-1:0] phy_dout, + input phy_cmd_wr_en, + input phy_data_wr_en, + input phy_rd_en, + input phy_ctl_mstr_empty, + input [31:0] phy_ctl_wd, + input [`PC_DATA_OFFSET_RANGE] data_offset, + input phy_ctl_wr, + input if_empty_def, + input phyGo, + input input_sink, + + output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory + output rclk, + output if_a_empty, + output if_empty, + output byte_rd_en, + output if_empty_or, + output if_empty_and, + output of_ctl_a_full, + output of_data_a_full, + output of_ctl_full, + output of_data_full, + output pre_data_a_full, + output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus + output phy_ctl_empty, + output phy_ctl_a_full, + output phy_ctl_full, + output [HIGHEST_LANE*12-1:0]mem_dq_out, + output [HIGHEST_LANE*12-1:0]mem_dq_ts, + input [HIGHEST_LANE*10-1:0]mem_dq_in, + output [HIGHEST_LANE-1:0] mem_dqs_out, + output [HIGHEST_LANE-1:0] mem_dqs_ts, + input [HIGHEST_LANE-1:0] mem_dqs_in, + input [1:0] byte_rd_en_oth_banks, + + output [AUXOUT_WIDTH-1:0] aux_out, + output reg rst_out = 0, + output reg mcGo=0, + output phy_ctl_ready, + output ref_dll_lock, + input if_rst, + input phy_read_calib, + input phy_write_calib, + input idelay_inc, + input idelay_ce, + input idelay_ld, + input [2:0] calib_sel, + input calib_zero_ctrl, + input [HIGHEST_LANE-1:0] calib_zero_lanes, + input calib_in_common, + input po_fine_enable, + input po_coarse_enable, + input po_fine_inc, + input po_coarse_inc, + input po_counter_load_en, + input po_counter_read_en, + input [8:0] po_counter_load_val, + input po_sel_fine_oclk_delay, + output reg po_coarse_overflow, + output reg po_fine_overflow, + output reg [8:0] po_counter_read_val, + + + + input pi_rst_dqs_find, + input pi_fine_enable, + input pi_fine_inc, + input pi_counter_load_en, + input pi_counter_read_en, + input [5:0] pi_counter_load_val, + output reg pi_fine_overflow, + output reg [5:0] pi_counter_read_val, + + output reg pi_dqs_found, + output pi_dqs_found_all, + output pi_dqs_found_any, + output [HIGHEST_LANE-1:0] pi_phase_locked_lanes, + output [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + output reg pi_dqs_out_of_range, + output reg pi_phase_locked, + output pi_phase_locked_all, + input [29:0] fine_delay, + input fine_delay_sel +); + +localparam DATA_CTL_A = (~DATA_CTL_N[0]); +localparam DATA_CTL_B = (~DATA_CTL_N[1]); +localparam DATA_CTL_C = (~DATA_CTL_N[2]); +localparam DATA_CTL_D = (~DATA_CTL_N[3]); +localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0]; +localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1]; +localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2]; +localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3]; +localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0]; +localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1]; +localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2]; +localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3]; +localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE"; +localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE"; +localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE"; +localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE"; +localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE"; +localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE"; +localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE"; +localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE"; + +localparam IO_A_START = 41; +localparam IO_A_END = 40; +localparam IO_B_START = 43; +localparam IO_B_END = 42; +localparam IO_C_START = 45; +localparam IO_C_END = 44; +localparam IO_D_START = 47; +localparam IO_D_END = 46; +localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1; +localparam IO_A_X_END = (IO_A_X_START-1); +localparam IO_B_X_START = (IO_A_X_START + 2); +localparam IO_B_X_END = (IO_B_X_START -1); +localparam IO_C_X_START = (IO_B_X_START + 2); +localparam IO_C_X_END = (IO_C_X_START -1); +localparam IO_D_X_START = (IO_C_X_START + 2); +localparam IO_D_X_END = (IO_D_X_START -1); + +localparam MSB_BURST_PEND_PO = 3; +localparam MSB_BURST_PEND_PI = 7; +localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8; +localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1; + +wire [1:0] oserdes_dqs; +wire [1:0] oserdes_dqs_ts; +wire [1:0] oserdes_dq_ts; + + +wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus; +wire [7:0] in_rank; +wire [11:0] IO_A; +wire [11:0] IO_B; +wire [11:0] IO_C; +wire [11:0] IO_D; + +wire [319:0] phy_din_remap; + +reg A_po_counter_read_en; +wire [8:0] A_po_counter_read_val; +reg A_pi_counter_read_en; +wire [5:0] A_pi_counter_read_val; +wire A_pi_fine_overflow; +wire A_po_coarse_overflow; +wire A_po_fine_overflow; +wire A_pi_dqs_found; +wire A_pi_dqs_out_of_range; +wire A_pi_phase_locked; +wire A_pi_iserdes_rst; +reg A_pi_fine_enable; +reg A_pi_fine_inc; +reg A_pi_counter_load_en; +reg [5:0] A_pi_counter_load_val; +reg A_pi_rst_dqs_find; + + +reg A_po_fine_enable; +reg A_po_coarse_enable; + reg A_po_fine_inc /* synthesis syn_maxfan = 3 */; +reg A_po_sel_fine_oclk_delay; +reg A_po_coarse_inc; +reg A_po_counter_load_en; +reg [8:0] A_po_counter_load_val; +wire A_rclk; +reg A_idelay_ce; +reg A_idelay_ld; +reg [29:0] A_fine_delay; +reg A_fine_delay_sel; + +reg B_po_counter_read_en; +wire [8:0] B_po_counter_read_val; +reg B_pi_counter_read_en; +wire [5:0] B_pi_counter_read_val; +wire B_pi_fine_overflow; +wire B_po_coarse_overflow; +wire B_po_fine_overflow; +wire B_pi_phase_locked; +wire B_pi_iserdes_rst; +wire B_pi_dqs_found; +wire B_pi_dqs_out_of_range; +reg B_pi_fine_enable; +reg B_pi_fine_inc; +reg B_pi_counter_load_en; +reg [5:0] B_pi_counter_load_val; +reg B_pi_rst_dqs_find; + + +reg B_po_fine_enable; +reg B_po_coarse_enable; + reg B_po_fine_inc /* synthesis syn_maxfan = 3 */; +reg B_po_coarse_inc; +reg B_po_sel_fine_oclk_delay; +reg B_po_counter_load_en; +reg [8:0] B_po_counter_load_val; +wire B_rclk; +reg B_idelay_ce; +reg B_idelay_ld; +reg [29:0] B_fine_delay; +reg B_fine_delay_sel; + + +reg C_pi_fine_inc; +reg D_pi_fine_inc; +reg C_pi_fine_enable; +reg D_pi_fine_enable; +reg C_po_counter_load_en; +reg D_po_counter_load_en; +reg C_po_coarse_inc; +reg D_po_coarse_inc; + reg C_po_fine_inc /* synthesis syn_maxfan = 3 */; + reg D_po_fine_inc /* synthesis syn_maxfan = 3 */; +reg C_po_sel_fine_oclk_delay; +reg D_po_sel_fine_oclk_delay; +reg [5:0] C_pi_counter_load_val; +reg [5:0] D_pi_counter_load_val; +reg [8:0] C_po_counter_load_val; +reg [8:0] D_po_counter_load_val; +reg C_po_coarse_enable; +reg D_po_coarse_enable; +reg C_po_fine_enable; +reg D_po_fine_enable; +wire C_po_coarse_overflow; +wire D_po_coarse_overflow; +wire C_po_fine_overflow; +wire D_po_fine_overflow; +wire [8:0] C_po_counter_read_val; +wire [8:0] D_po_counter_read_val; +reg C_po_counter_read_en; +reg D_po_counter_read_en; +wire C_pi_dqs_found; +wire D_pi_dqs_found; +wire C_pi_fine_overflow; +wire D_pi_fine_overflow; +reg C_pi_counter_read_en; +reg D_pi_counter_read_en; +reg C_pi_counter_load_en; +reg D_pi_counter_load_en; +wire C_pi_phase_locked; +wire C_pi_iserdes_rst; +wire D_pi_phase_locked; +wire D_pi_iserdes_rst; +wire C_pi_dqs_out_of_range; +wire D_pi_dqs_out_of_range; +wire [5:0] C_pi_counter_read_val; +wire [5:0] D_pi_counter_read_val; +wire C_rclk; +wire D_rclk; +reg C_idelay_ce; +reg D_idelay_ce; +reg C_idelay_ld; +reg D_idelay_ld; +reg C_pi_rst_dqs_find; +reg D_pi_rst_dqs_find; +reg [29:0] C_fine_delay; +reg [29:0] D_fine_delay; +reg C_fine_delay_sel; +reg D_fine_delay_sel; + +wire pi_iserdes_rst; + +wire A_if_empty; +wire B_if_empty; +wire C_if_empty; +wire D_if_empty; +wire A_byte_rd_en; +wire B_byte_rd_en; +wire C_byte_rd_en; +wire D_byte_rd_en; +wire A_if_a_empty; +wire B_if_a_empty; +wire C_if_a_empty; +wire D_if_a_empty; +//wire A_if_full; +//wire B_if_full; +//wire C_if_full; +//wire D_if_full; +//wire A_of_empty; +//wire B_of_empty; +//wire C_of_empty; +//wire D_of_empty; +wire A_of_full; +wire B_of_full; +wire C_of_full; +wire D_of_full; +wire A_of_ctl_full; +wire B_of_ctl_full; +wire C_of_ctl_full; +wire D_of_ctl_full; +wire A_of_data_full; +wire B_of_data_full; +wire C_of_data_full; +wire D_of_data_full; +wire A_of_a_full; +wire B_of_a_full; +wire C_of_a_full; +wire D_of_a_full; +wire A_pre_fifo_a_full; +wire B_pre_fifo_a_full; +wire C_pre_fifo_a_full; +wire D_pre_fifo_a_full; +wire A_of_ctl_a_full; +wire B_of_ctl_a_full; +wire C_of_ctl_a_full; +wire D_of_ctl_a_full; +wire A_of_data_a_full; +wire B_of_data_a_full; +wire C_of_data_a_full; +wire D_of_data_a_full; +wire A_pre_data_a_full; +wire B_pre_data_a_full; +wire C_pre_data_a_full; +wire D_pre_data_a_full; +wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation +wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; // +wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; // +wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; // + +wire [3:0] dummy_data; + +wire [31:0] _phy_ctl_wd; + +wire [1:0] phy_encalib; + +assign pi_dqs_found_all = + (! PRESENT_DATA_A | A_pi_dqs_found) & + (! PRESENT_DATA_B | B_pi_dqs_found) & + (! PRESENT_DATA_C | C_pi_dqs_found) & + (! PRESENT_DATA_D | D_pi_dqs_found) ; + +assign pi_dqs_found_any = + ( PRESENT_DATA_A & A_pi_dqs_found) | + ( PRESENT_DATA_B & B_pi_dqs_found) | + ( PRESENT_DATA_C & C_pi_dqs_found) | + ( PRESENT_DATA_D & D_pi_dqs_found) ; + +assign pi_phase_locked_all = + (! PRESENT_DATA_A | A_pi_phase_locked) & + (! PRESENT_DATA_B | B_pi_phase_locked) & + (! PRESENT_DATA_C | C_pi_phase_locked) & + (! PRESENT_DATA_D | D_pi_phase_locked); + +wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal + // which is combined into another signals such that + // the other signal isn't changed. The purpose + // is to fake the tools into ignoring dangling inputs. + // Because it is anded with 1'b0, the contributing signals + // are folded as constants or trimmed. + + +assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty); +assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) : + (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en); +assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty); +assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty); +assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty; +//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ; +//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty; +assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ; +assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ; +assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ; +assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ; +assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full; + + +function [79:0] part_select_80; +input [319:0] vector; +input [1:0] select; +begin + case (select) + 2'b00 : part_select_80[79:0] = vector[1*80-1:0*80]; + 2'b01 : part_select_80[79:0] = vector[2*80-1:1*80]; + 2'b10 : part_select_80[79:0] = vector[3*80-1:2*80]; + 2'b11 : part_select_80[79:0] = vector[4*80-1:3*80]; + endcase +end +endfunction + +wire [319:0] phy_dout_remap; + +reg rst_out_trig = 1'b0; +reg [31:0] rclk_delay; +reg rst_edge1 = 1'b0; +reg rst_edge2 = 1'b0; +reg rst_edge3 = 1'b0; +reg rst_edge_detect = 1'b0; +wire rclk_; +reg rst_out_start = 1'b0 ; +reg rst_primitives=0; +reg A_rst_primitives=0; +reg B_rst_primitives=0; +reg C_rst_primitives=0; +reg D_rst_primitives=0; + +`ifdef USE_PHY_CONTROL_TEST + wire [15:0] test_output; + wire [15:0] test_input; + wire [2:0] test_select=0; + wire scan_enable = 0; +`endif + +generate + +genvar i; + +if (RCLK_SELECT_LANE == "A") begin + assign rclk_ = A_rclk; + assign pi_iserdes_rst = A_pi_iserdes_rst; + end +else if (RCLK_SELECT_LANE == "B") begin + assign rclk_ = B_rclk; + assign pi_iserdes_rst = B_pi_iserdes_rst; + end +else if (RCLK_SELECT_LANE == "C") begin + assign rclk_ = C_rclk; + assign pi_iserdes_rst = C_pi_iserdes_rst; + end +else if (RCLK_SELECT_LANE == "D") begin + assign rclk_ = D_rclk; + assign pi_iserdes_rst = D_pi_iserdes_rst; + end +else begin + assign rclk_ = B_rclk; // default + end + +endgenerate + +assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk; +assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk; +assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk; +assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk; + +assign pi_phase_locked_lanes = + {(! PRESENT_DATA_D[0] | D_pi_phase_locked), + (! PRESENT_DATA_C[0] | C_pi_phase_locked) , + (! PRESENT_DATA_B[0] | B_pi_phase_locked) , + (! PRESENT_DATA_A[0] | A_pi_phase_locked)}; + +assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found}; + +// this block scrubs X from rclk_delay[11] +reg rclk_delay_11; +always @(rclk_delay[11]) begin : rclk_delay_11_blk + if ( rclk_delay[11]) + rclk_delay_11 = 1; + else + rclk_delay_11 = 0; +end + +always @(posedge phy_clk or posedge rst ) begin +// scrub 4-state values from rclk_delay[11] + if ( rst) begin + rst_out <= #1 0; + end + else begin + if ( rclk_delay_11) + rst_out <= #1 1; + end +end + +always @(posedge phy_clk ) begin + // phy_ctl_ready drives reset of the system + rst_primitives <= !phy_ctl_ready ; + A_rst_primitives <= rst_primitives ; + B_rst_primitives <= rst_primitives ; + C_rst_primitives <= rst_primitives ; + D_rst_primitives <= rst_primitives ; + + rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo); + mcGo <= #1 rst_out ; + +end + +//reset synchronized to clk_div2 + (* ASYNC_REG = "TRUE" *) reg A_pi_rst_div2; + (* ASYNC_REG = "TRUE" *) reg B_pi_rst_div2; + (* ASYNC_REG = "TRUE" *) reg C_pi_rst_div2; + (* ASYNC_REG = "TRUE" *) reg D_pi_rst_div2; +generate + if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2 + (* ASYNC_REG = "TRUE" *) reg pi_rst_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_rst_div2r2; + + always @(posedge clk_div2) begin + pi_rst_div2r1 <= rst_primitives; + pi_rst_div2r2 <= pi_rst_div2r1; + A_pi_rst_div2 <= pi_rst_div2r2; + B_pi_rst_div2 <= pi_rst_div2r2; + C_pi_rst_div2 <= pi_rst_div2r2; + D_pi_rst_div2 <= pi_rst_div2r2; + end + end else begin: phaser_in_div4 + always @ (*) begin + A_pi_rst_div2 <= 1'b0; + B_pi_rst_div2 <= 1'b0; + C_pi_rst_div2 <= 1'b0; + D_pi_rst_div2 <= 1'b0; + end + end +endgenerate + +generate + + if (BYTE_LANES[0]) begin + assign dummy_data[0] = 0; + end + else begin + assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80]; + end + if (BYTE_LANES[1]) begin + assign dummy_data[1] = 0; + end + else begin + assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80]; + end + if (BYTE_LANES[2]) begin + assign dummy_data[2] = 0; + end + else begin + assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80]; + end + if (BYTE_LANES[3]) begin + assign dummy_data[3] = 0; + end + else begin + assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80]; + end + + if (PRESENT_DATA_A) begin + assign A_of_data_full = A_of_full; + assign A_of_ctl_full = 0; + assign A_of_data_a_full = A_of_a_full; + assign A_of_ctl_a_full = 0; + assign A_pre_data_a_full = A_pre_fifo_a_full; + end + else begin + assign A_of_ctl_full = A_of_full; + assign A_of_data_full = 0; + assign A_of_ctl_a_full = A_of_a_full; + assign A_of_data_a_full = 0; + assign A_pre_data_a_full = 0; + end + if (PRESENT_DATA_B) begin + assign B_of_data_full = B_of_full; + assign B_of_ctl_full = 0; + assign B_of_data_a_full = B_of_a_full; + assign B_of_ctl_a_full = 0; + assign B_pre_data_a_full = B_pre_fifo_a_full; + end + else begin + assign B_of_ctl_full = B_of_full; + assign B_of_data_full = 0; + assign B_of_ctl_a_full = B_of_a_full; + assign B_of_data_a_full = 0; + assign B_pre_data_a_full = 0; + end + if (PRESENT_DATA_C) begin + assign C_of_data_full = C_of_full; + assign C_of_ctl_full = 0; + assign C_of_data_a_full = C_of_a_full; + assign C_of_ctl_a_full = 0; + assign C_pre_data_a_full = C_pre_fifo_a_full; + end + else begin + assign C_of_ctl_full = C_of_full; + assign C_of_data_full = 0; + assign C_of_ctl_a_full = C_of_a_full; + assign C_of_data_a_full = 0; + assign C_pre_data_a_full = 0; + end + if (PRESENT_DATA_D) begin + assign D_of_data_full = D_of_full; + assign D_of_ctl_full = 0; + assign D_of_data_a_full = D_of_a_full; + assign D_of_ctl_a_full = 0; + assign D_pre_data_a_full = D_pre_fifo_a_full; + end + else begin + assign D_of_ctl_full = D_of_full; + assign D_of_data_full = 0; + assign D_of_ctl_a_full = D_of_a_full; + assign D_of_data_a_full = 0; + assign D_pre_data_a_full = 0; + end +// byte lane must exist and be data lane. + if (PRESENT_DATA_A ) + case ( LANE_REMAP[1:0] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0]; + endcase + else + case ( LANE_REMAP[1:0] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + + if (PRESENT_DATA_B ) + case ( LANE_REMAP[5:4] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80]; + endcase + else + if (HIGHEST_LANE > 1) + case ( LANE_REMAP[5:4] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + + if (PRESENT_DATA_C) + case ( LANE_REMAP[9:8] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160]; + endcase + else + if (HIGHEST_LANE > 2) + case ( LANE_REMAP[9:8] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + + if (PRESENT_DATA_D ) + case ( LANE_REMAP[13:12] ) + 2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240]; + 2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240]; + 2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240]; + 2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240]; + endcase + else + if (HIGHEST_LANE > 3) + case ( LANE_REMAP[13:12] ) + 2'b00 : assign phy_din[1*80-1:0] = 80'h0; + 2'b01 : assign phy_din[2*80-1:80] = 80'h0; + 2'b10 : assign phy_din[3*80-1:160] = 80'h0; + 2'b11 : assign phy_din[4*80-1:240] = 80'h0; + endcase + +if (HIGHEST_LANE > 1) + assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]}; +if (HIGHEST_LANE == 1) + assign _phy_ctl_wd = phy_ctl_wd; + + +//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst)); +BUFIO rclk_buf(.I(rclk_), .O(rclk) ); + +if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A + + assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0])); + + mig_7series_v4_2_ddr_byte_lane # + ( + .ABCD ("A"), + .PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[11:0]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (A_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (A_PI_BURST_MODE), + .PI_CLKOUT_DIV (A_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (A_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (A_PO_CLKOUT_DIV), + .PO_FINE_DELAY (A_PO_FINE_DELAY), + .PO_COARSE_BYPASS (A_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (A_PO_COARSE_DELAY), + .PO_OCLK_DELAY (A_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (A_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_A( + .mem_dq_out (mem_dq_out[11:0]), + .mem_dq_ts (mem_dq_ts[11:0]), + .mem_dq_in (mem_dq_in[9:0]), + .mem_dqs_out (mem_dqs_out[0]), + .mem_dqs_ts (mem_dqs_ts[0]), + .mem_dqs_in (mem_dqs_in[0]), + .rst (A_rst_primitives), + .rst_pi_div2 (A_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (A_ddr_clk), + .rclk (A_rclk), + .pi_dqs_found (A_pi_dqs_found), + .dqs_out_of_range (A_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (A_if_a_empty), + .if_empty (A_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*A_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*A_of_empty*/), + .of_a_full (A_of_a_full), + .of_full (A_of_full), + .pre_fifo_a_full (A_pre_fifo_a_full), + .phy_din (phy_din_remap[79:0]), + .phy_dout (phy_dout_remap[79:0]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (A_byte_rd_en), +// calibration signals + .idelay_inc (idelay_inc), + .idelay_ce (A_idelay_ce), + .idelay_ld (A_idelay_ld), + .pi_rst_dqs_find (A_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (A_po_fine_enable), + .po_coarse_enable (A_po_coarse_enable), + .po_fine_inc (A_po_fine_inc), + .po_coarse_inc (A_po_coarse_inc), + .po_counter_load_en (A_po_counter_load_en), + .po_counter_read_en (A_po_counter_read_en), + .po_counter_load_val (A_po_counter_load_val), + .po_coarse_overflow (A_po_coarse_overflow), + .po_fine_overflow (A_po_fine_overflow), + .po_counter_read_val (A_po_counter_read_val), + .po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (A_pi_fine_enable), + .pi_fine_inc (A_pi_fine_inc), + .pi_counter_load_en (A_pi_counter_load_en), + .pi_counter_read_en (A_pi_counter_read_en), + .pi_counter_load_val (A_pi_counter_load_val), + .pi_fine_overflow (A_pi_fine_overflow), + .pi_counter_read_val (A_pi_counter_read_val), + .pi_iserdes_rst (A_pi_iserdes_rst), + .pi_phase_locked (A_pi_phase_locked), + .fine_delay (A_fine_delay), + .fine_delay_sel (A_fine_delay_sel) +); + +end +else begin : no_ddr_byte_lane_A + assign A_of_a_full = 1'b0; + assign A_of_full = 1'b0; + assign A_pre_fifo_a_full = 1'b0; + assign A_if_empty = 1'b0; + assign A_byte_rd_en = 1'b1; + assign A_if_a_empty = 1'b0; + assign A_pi_phase_locked = 1; + assign A_pi_dqs_found = 1; + assign A_rclk = 0; + assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign A_pi_counter_read_val = 0; + assign A_po_counter_read_val = 0; + assign A_pi_fine_overflow = 0; + assign A_po_coarse_overflow = 0; + assign A_po_fine_overflow = 0; +end + +if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B + + assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4])); + mig_7series_v4_2_ddr_byte_lane # + ( + .ABCD ("B"), + .PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[23:12]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (B_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (B_PI_BURST_MODE), + .PI_CLKOUT_DIV (B_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (B_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (B_PO_CLKOUT_DIV), + .PO_FINE_DELAY (B_PO_FINE_DELAY), + .PO_COARSE_BYPASS (B_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (B_PO_COARSE_DELAY), + .PO_OCLK_DELAY (B_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (B_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_B( + .mem_dq_out (mem_dq_out[23:12]), + .mem_dq_ts (mem_dq_ts[23:12]), + .mem_dq_in (mem_dq_in[19:10]), + .mem_dqs_out (mem_dqs_out[1]), + .mem_dqs_ts (mem_dqs_ts[1]), + .mem_dqs_in (mem_dqs_in[1]), + .rst (B_rst_primitives), + .rst_pi_div2 (B_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (B_ddr_clk), + .rclk (B_rclk), + .pi_dqs_found (B_pi_dqs_found), + .dqs_out_of_range (B_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (B_if_a_empty), + .if_empty (B_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*B_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*B_of_empty*/), + .of_a_full (B_of_a_full), + .of_full (B_of_full), + .pre_fifo_a_full (B_pre_fifo_a_full), + .phy_din (phy_din_remap[159:80]), + .phy_dout (phy_dout_remap[159:80]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (B_byte_rd_en), +// calibration signals + .idelay_inc (idelay_inc), + .idelay_ce (B_idelay_ce), + .idelay_ld (B_idelay_ld), + .pi_rst_dqs_find (B_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (B_po_fine_enable), + .po_coarse_enable (B_po_coarse_enable), + .po_fine_inc (B_po_fine_inc), + .po_coarse_inc (B_po_coarse_inc), + .po_counter_load_en (B_po_counter_load_en), + .po_counter_read_en (B_po_counter_read_en), + .po_counter_load_val (B_po_counter_load_val), + .po_coarse_overflow (B_po_coarse_overflow), + .po_fine_overflow (B_po_fine_overflow), + .po_counter_read_val (B_po_counter_read_val), + .po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (B_pi_fine_enable), + .pi_fine_inc (B_pi_fine_inc), + .pi_counter_load_en (B_pi_counter_load_en), + .pi_counter_read_en (B_pi_counter_read_en), + .pi_counter_load_val (B_pi_counter_load_val), + .pi_fine_overflow (B_pi_fine_overflow), + .pi_counter_read_val (B_pi_counter_read_val), + .pi_iserdes_rst (B_pi_iserdes_rst), + .pi_phase_locked (B_pi_phase_locked), + .fine_delay (B_fine_delay), + .fine_delay_sel (B_fine_delay_sel) +); +end +else begin : no_ddr_byte_lane_B + assign B_of_a_full = 1'b0; + assign B_of_full = 1'b0; + assign B_pre_fifo_a_full = 1'b0; + assign B_if_empty = 1'b0; + assign B_if_a_empty = 1'b0; + assign B_byte_rd_en = 1'b1; + assign B_pi_phase_locked = 1; + assign B_pi_dqs_found = 1; + assign B_rclk = 0; + assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign B_pi_counter_read_val = 0; + assign B_po_counter_read_val = 0; + assign B_pi_fine_overflow = 0; + assign B_po_coarse_overflow = 0; + assign B_po_fine_overflow = 0; +end + +if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C + + assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8])); + mig_7series_v4_2_ddr_byte_lane # + ( + .ABCD ("C"), + .PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[35:24]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (C_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (C_PI_BURST_MODE), + .PI_CLKOUT_DIV (C_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (C_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (C_PO_CLKOUT_DIV), + .PO_FINE_DELAY (C_PO_FINE_DELAY), + .PO_COARSE_BYPASS (C_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (C_PO_COARSE_DELAY), + .PO_OCLK_DELAY (C_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (C_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_C( + .mem_dq_out (mem_dq_out[35:24]), + .mem_dq_ts (mem_dq_ts[35:24]), + .mem_dq_in (mem_dq_in[29:20]), + .mem_dqs_out (mem_dqs_out[2]), + .mem_dqs_ts (mem_dqs_ts[2]), + .mem_dqs_in (mem_dqs_in[2]), + .rst (C_rst_primitives), + .rst_pi_div2 (C_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (C_ddr_clk), + .rclk (C_rclk), + .pi_dqs_found (C_pi_dqs_found), + .dqs_out_of_range (C_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (C_if_a_empty), + .if_empty (C_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*C_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*C_of_empty*/), + .of_a_full (C_of_a_full), + .of_full (C_of_full), + .pre_fifo_a_full (C_pre_fifo_a_full), + .phy_din (phy_din_remap[239:160]), + .phy_dout (phy_dout_remap[239:160]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (C_byte_rd_en), +// calibration signals + .idelay_inc (idelay_inc), + .idelay_ce (C_idelay_ce), + .idelay_ld (C_idelay_ld), + .pi_rst_dqs_find (C_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (C_po_fine_enable), + .po_coarse_enable (C_po_coarse_enable), + .po_fine_inc (C_po_fine_inc), + .po_coarse_inc (C_po_coarse_inc), + .po_counter_load_en (C_po_counter_load_en), + .po_counter_read_en (C_po_counter_read_en), + .po_counter_load_val (C_po_counter_load_val), + .po_coarse_overflow (C_po_coarse_overflow), + .po_fine_overflow (C_po_fine_overflow), + .po_counter_read_val (C_po_counter_read_val), + .po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (C_pi_fine_enable), + .pi_fine_inc (C_pi_fine_inc), + .pi_counter_load_en (C_pi_counter_load_en), + .pi_counter_read_en (C_pi_counter_read_en), + .pi_counter_load_val (C_pi_counter_load_val), + .pi_fine_overflow (C_pi_fine_overflow), + .pi_counter_read_val (C_pi_counter_read_val), + .pi_iserdes_rst (C_pi_iserdes_rst), + .pi_phase_locked (C_pi_phase_locked), + .fine_delay (C_fine_delay), + .fine_delay_sel (C_fine_delay_sel) +); + +end +else begin : no_ddr_byte_lane_C + assign C_of_a_full = 1'b0; + assign C_of_full = 1'b0; + assign C_pre_fifo_a_full = 1'b0; + assign C_if_empty = 1'b0; + assign C_byte_rd_en = 1'b1; + assign C_if_a_empty = 1'b0; + assign C_pi_phase_locked = 1; + assign C_pi_dqs_found = 1; + assign C_rclk = 0; + assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign C_pi_counter_read_val = 0; + assign C_po_counter_read_val = 0; + assign C_pi_fine_overflow = 0; + assign C_po_coarse_overflow = 0; + assign C_po_fine_overflow = 0; +end + +if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D + assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12])); + + mig_7series_v4_2_ddr_byte_lane # + ( + .ABCD ("D"), + .PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"), + .BITLANES (BITLANES[47:36]), + .BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]), + .OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE), + .OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE), + .OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE), + //.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE), + //.OF_ARRAY_MODE (D_OF_ARRAY_MODE), + //.IF_ARRAY_MODE (IF_ARRAY_MODE), + .IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE), + .IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE), + .IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .BANK_TYPE (BANK_TYPE), + .BYTELANES_DDR_CK (BYTELANES_DDR_CK), + .RCLK_SELECT_LANE (RCLK_SELECT_LANE), + .USE_PRE_POST_FIFO (USE_PRE_POST_FIFO), + .SYNTHESIS (SYNTHESIS), + .TCK (TCK), + .PC_CLK_RATIO (PC_CLK_RATIO), + .PI_BURST_MODE (D_PI_BURST_MODE), + .PI_CLKOUT_DIV (D_PI_CLKOUT_DIV), + .PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV), + .PI_FINE_DELAY (D_PI_FINE_DELAY), + .PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC), + .PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST), + .PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET), + .PO_CLKOUT_DIV (D_PO_CLKOUT_DIV), + .PO_FINE_DELAY (D_PO_FINE_DELAY), + .PO_COARSE_BYPASS (D_PO_COARSE_BYPASS), + .PO_COARSE_DELAY (D_PO_COARSE_DELAY), + .PO_OCLK_DELAY (D_PO_OCLK_DELAY), + .PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV), + .PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC), + .PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST), + .OSERDES_DATA_RATE (D_OS_DATA_RATE), + .OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH), + .IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE), + .IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE) + ,.CKE_ODT_AUX (CKE_ODT_AUX) + ,.PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + ddr_byte_lane_D( + .mem_dq_out (mem_dq_out[47:36]), + .mem_dq_ts (mem_dq_ts[47:36]), + .mem_dq_in (mem_dq_in[39:30]), + .mem_dqs_out (mem_dqs_out[3]), + .mem_dqs_ts (mem_dqs_ts[3]), + .mem_dqs_in (mem_dqs_in[3]), + .rst (D_rst_primitives), + .rst_pi_div2 (D_pi_rst_div2), + .phy_clk (phy_clk), + .clk_div2 (clk_div2), + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .idelayctrl_refclk (idelayctrl_refclk), + .sync_pulse (sync_pulse), + .ddr_ck_out (D_ddr_clk), + .rclk (D_rclk), + .pi_dqs_found (D_pi_dqs_found), + .dqs_out_of_range (D_pi_dqs_out_of_range), + .if_empty_def (if_empty_def), + .if_a_empty (D_if_a_empty), + .if_empty (D_if_empty), + .if_a_full (/*if_a_full*/), + .if_full (/*D_if_full*/), + .of_a_empty (/*of_a_empty*/), + .of_empty (/*D_of_empty*/), + .of_a_full (D_of_a_full), + .of_full (D_of_full), + .pre_fifo_a_full (D_pre_fifo_a_full), + .phy_din (phy_din_remap[319:240]), + .phy_dout (phy_dout_remap[319:240]), + .phy_cmd_wr_en (phy_cmd_wr_en), + .phy_data_wr_en (phy_data_wr_en), + .phy_rd_en (phy_rd_en), + .phaser_ctl_bus (phaser_ctl_bus), + .idelay_inc (idelay_inc), + .idelay_ce (D_idelay_ce), + .idelay_ld (D_idelay_ld), + .if_rst (if_rst), + .byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}), + .byte_rd_en_oth_banks (byte_rd_en_oth_banks), + .byte_rd_en (D_byte_rd_en), +// calibration signals + .pi_rst_dqs_find (D_pi_rst_dqs_find), + .po_en_calib (phy_encalib), + .po_fine_enable (D_po_fine_enable), + .po_coarse_enable (D_po_coarse_enable), + .po_fine_inc (D_po_fine_inc), + .po_coarse_inc (D_po_coarse_inc), + .po_counter_load_en (D_po_counter_load_en), + .po_counter_read_en (D_po_counter_read_en), + .po_counter_load_val (D_po_counter_load_val), + .po_coarse_overflow (D_po_coarse_overflow), + .po_fine_overflow (D_po_fine_overflow), + .po_counter_read_val (D_po_counter_read_val), + .po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay), + .pi_en_calib (phy_encalib), + .pi_fine_enable (D_pi_fine_enable), + .pi_fine_inc (D_pi_fine_inc), + .pi_counter_load_en (D_pi_counter_load_en), + .pi_counter_read_en (D_pi_counter_read_en), + .pi_counter_load_val (D_pi_counter_load_val), + .pi_fine_overflow (D_pi_fine_overflow), + .pi_counter_read_val (D_pi_counter_read_val), + .pi_iserdes_rst (D_pi_iserdes_rst), + .pi_phase_locked (D_pi_phase_locked), + .fine_delay (D_fine_delay), + .fine_delay_sel (D_fine_delay_sel) +); +end +else begin : no_ddr_byte_lane_D + assign D_of_a_full = 1'b0; + assign D_of_full = 1'b0; + assign D_pre_fifo_a_full = 1'b0; + assign D_if_empty = 1'b0; + assign D_byte_rd_en = 1'b1; + assign D_if_a_empty = 1'b0; + assign D_rclk = 0; + assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}}; + assign D_pi_dqs_found = 1; + assign D_pi_phase_locked = 1; + assign D_pi_counter_read_val = 0; + assign D_po_counter_read_val = 0; + assign D_pi_fine_overflow = 0; + assign D_po_coarse_overflow = 0; + assign D_po_fine_overflow = 0; +end +endgenerate + + +assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank; + +PHY_CONTROL #( + .AO_WRLVL_EN ( PC_AO_WRLVL_EN), + .AO_TOGGLE ( PC_AO_TOGGLE), + .BURST_MODE ( PC_BURST_MODE), + .CO_DURATION ( PC_CO_DURATION ), + .CLK_RATIO ( PC_CLK_RATIO), + .DATA_CTL_A_N ( PC_DATA_CTL_A), + .DATA_CTL_B_N ( PC_DATA_CTL_B), + .DATA_CTL_C_N ( PC_DATA_CTL_C), + .DATA_CTL_D_N ( PC_DATA_CTL_D), + .DI_DURATION ( PC_DI_DURATION ), + .DO_DURATION ( PC_DO_DURATION ), + .EVENTS_DELAY ( PC_EVENTS_DELAY), + .FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS), + .MULTI_REGION ( PC_MULTI_REGION ), + .PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN), + .DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH), + .SYNC_MODE ( PC_SYNC_MODE), + .CMD_OFFSET ( PC_CMD_OFFSET), + + .RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0), + .RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1), + .RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2), + .RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3), + .RD_DURATION_0 ( PC_RD_DURATION_0), + .RD_DURATION_1 ( PC_RD_DURATION_1), + .RD_DURATION_2 ( PC_RD_DURATION_2), + .RD_DURATION_3 ( PC_RD_DURATION_3), + .WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0), + .WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1), + .WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2), + .WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3), + .WR_DURATION_0 ( PC_WR_DURATION_0), + .WR_DURATION_1 ( PC_WR_DURATION_1), + .WR_DURATION_2 ( PC_WR_DURATION_2), + .WR_DURATION_3 ( PC_WR_DURATION_3) +) phy_control_i ( + .AUXOUTPUT (aux_out), + .INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]), + .INRANKA (in_rank[1:0]), + .INRANKB (in_rank[3:2]), + .INRANKC (in_rank[5:4]), + .INRANKD (in_rank[7:6]), + .OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]), + .PCENABLECALIB (phy_encalib), + .PHYCTLALMOSTFULL (phy_ctl_a_full), + .PHYCTLEMPTY (phy_ctl_empty), + .PHYCTLFULL (phy_ctl_full), + .PHYCTLREADY (phy_ctl_ready), + .MEMREFCLK (mem_refclk), + .PHYCLK (phy_ctl_clk), + .PHYCTLMSTREMPTY (phy_ctl_mstr_empty), + .PHYCTLWD (_phy_ctl_wd), + .PHYCTLWRENABLE (phy_ctl_wr), + .PLLLOCK (pll_lock), + .REFDLLLOCK (ref_dll_lock), // is reset while !locked + .RESET (rst), + .SYNCIN (sync_pulse), + .READCALIBENABLE (phy_read_calib), + .WRITECALIBENABLE (phy_write_calib) +`ifdef USE_PHY_CONTROL_TEST + , .TESTINPUT (16'b0), + .TESTOUTPUT (test_output), + .TESTSELECT (test_select), + .SCANENABLEN (scan_enable) +`endif +); + + + +// register outputs to give extra slack in timing +always @(posedge phy_clk ) begin + case (calib_sel[1:0]) + 2'h0: begin + po_coarse_overflow <= #1 A_po_coarse_overflow; + po_fine_overflow <= #1 A_po_fine_overflow; + po_counter_read_val <= #1 A_po_counter_read_val; + + pi_fine_overflow <= #1 A_pi_fine_overflow; + pi_counter_read_val<= #1 A_pi_counter_read_val; + + pi_phase_locked <= #1 A_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 A_pi_dqs_found; + pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range; + end + + 2'h1: begin + po_coarse_overflow <= #1 B_po_coarse_overflow; + po_fine_overflow <= #1 B_po_fine_overflow; + po_counter_read_val <= #1 B_po_counter_read_val; + + pi_fine_overflow <= #1 B_pi_fine_overflow; + pi_counter_read_val <= #1 B_pi_counter_read_val; + + pi_phase_locked <= #1 B_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 B_pi_dqs_found; + pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range; + end + + 2'h2: begin + po_coarse_overflow <= #1 C_po_coarse_overflow; + po_fine_overflow <= #1 C_po_fine_overflow; + po_counter_read_val <= #1 C_po_counter_read_val; + + pi_fine_overflow <= #1 C_pi_fine_overflow; + pi_counter_read_val <= #1 C_pi_counter_read_val; + + pi_phase_locked <= #1 C_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 C_pi_dqs_found; + pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range; + end + + 2'h3: begin + po_coarse_overflow <= #1 D_po_coarse_overflow; + po_fine_overflow <= #1 D_po_fine_overflow; + po_counter_read_val <= #1 D_po_counter_read_val; + + pi_fine_overflow <= #1 D_pi_fine_overflow; + pi_counter_read_val <= #1 D_pi_counter_read_val; + + pi_phase_locked <= #1 D_pi_phase_locked; + if ( calib_in_common) + pi_dqs_found <= #1 pi_dqs_found_any; + else + pi_dqs_found <= #1 D_pi_dqs_found; + pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range; + + end + default: begin + po_coarse_overflow <= po_coarse_overflow; + end + endcase +end + +wire B_mux_ctrl; +wire C_mux_ctrl; +wire D_mux_ctrl; +generate + if (HIGHEST_LANE > 1) + assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1])); + else + assign B_mux_ctrl = 0; + if (HIGHEST_LANE > 2) + assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2])); + else + assign C_mux_ctrl = 0; + if (HIGHEST_LANE > 3) + assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3])); + else + assign D_mux_ctrl = 0; +endgenerate + +always @(*) begin + A_pi_fine_enable = 0; + A_pi_fine_inc = 0; + A_pi_counter_load_en = 0; + A_pi_counter_read_en = 0; + A_pi_counter_load_val = 0; + A_pi_rst_dqs_find = 0; + + + A_po_fine_enable = 0; + A_po_coarse_enable = 0; + A_po_fine_inc = 0; + A_po_coarse_inc = 0; + A_po_counter_load_en = 0; + A_po_counter_read_en = 0; + A_po_counter_load_val = 0; + A_po_sel_fine_oclk_delay = 0; + + A_idelay_ce = 0; + A_idelay_ld = 0; + A_fine_delay = 0; + A_fine_delay_sel = 0; + + B_pi_fine_enable = 0; + B_pi_fine_inc = 0; + B_pi_counter_load_en = 0; + B_pi_counter_read_en = 0; + B_pi_counter_load_val = 0; + B_pi_rst_dqs_find = 0; + + + B_po_fine_enable = 0; + B_po_coarse_enable = 0; + B_po_fine_inc = 0; + B_po_coarse_inc = 0; + B_po_counter_load_en = 0; + B_po_counter_read_en = 0; + B_po_counter_load_val = 0; + B_po_sel_fine_oclk_delay = 0; + + B_idelay_ce = 0; + B_idelay_ld = 0; + B_fine_delay = 0; + B_fine_delay_sel = 0; + + C_pi_fine_enable = 0; + C_pi_fine_inc = 0; + C_pi_counter_load_en = 0; + C_pi_counter_read_en = 0; + C_pi_counter_load_val = 0; + C_pi_rst_dqs_find = 0; + + + C_po_fine_enable = 0; + C_po_coarse_enable = 0; + C_po_fine_inc = 0; + C_po_coarse_inc = 0; + C_po_counter_load_en = 0; + C_po_counter_read_en = 0; + C_po_counter_load_val = 0; + C_po_sel_fine_oclk_delay = 0; + + C_idelay_ce = 0; + C_idelay_ld = 0; + C_fine_delay = 0; + C_fine_delay_sel = 0; + + D_pi_fine_enable = 0; + D_pi_fine_inc = 0; + D_pi_counter_load_en = 0; + D_pi_counter_read_en = 0; + D_pi_counter_load_val = 0; + D_pi_rst_dqs_find = 0; + + + D_po_fine_enable = 0; + D_po_coarse_enable = 0; + D_po_fine_inc = 0; + D_po_coarse_inc = 0; + D_po_counter_load_en = 0; + D_po_counter_read_en = 0; + D_po_counter_load_val = 0; + D_po_sel_fine_oclk_delay = 0; + + D_idelay_ce = 0; + D_idelay_ld = 0; + D_fine_delay = 0; + D_fine_delay_sel = 0; + + if ( calib_sel[2]) begin + // if this is asserted, all calib signals are deasserted + A_pi_fine_enable = 0; + A_pi_fine_inc = 0; + A_pi_counter_load_en = 0; + A_pi_counter_read_en = 0; + A_pi_counter_load_val = 0; + A_pi_rst_dqs_find = 0; + + + A_po_fine_enable = 0; + A_po_coarse_enable = 0; + A_po_fine_inc = 0; + A_po_coarse_inc = 0; + A_po_counter_load_en = 0; + A_po_counter_read_en = 0; + A_po_counter_load_val = 0; + A_po_sel_fine_oclk_delay = 0; + + A_idelay_ce = 0; + A_idelay_ld = 0; + A_fine_delay = 0; + A_fine_delay_sel = 0; + + B_pi_fine_enable = 0; + B_pi_fine_inc = 0; + B_pi_counter_load_en = 0; + B_pi_counter_read_en = 0; + B_pi_counter_load_val = 0; + B_pi_rst_dqs_find = 0; + + + B_po_fine_enable = 0; + B_po_coarse_enable = 0; + B_po_fine_inc = 0; + B_po_coarse_inc = 0; + B_po_counter_load_en = 0; + B_po_counter_read_en = 0; + B_po_counter_load_val = 0; + B_po_sel_fine_oclk_delay = 0; + + B_idelay_ce = 0; + B_idelay_ld = 0; + B_fine_delay = 0; + B_fine_delay_sel = 0; + + + C_pi_fine_enable = 0; + C_pi_fine_inc = 0; + C_pi_counter_load_en = 0; + C_pi_counter_read_en = 0; + C_pi_counter_load_val = 0; + C_pi_rst_dqs_find = 0; + + + C_po_fine_enable = 0; + C_po_coarse_enable = 0; + C_po_fine_inc = 0; + C_po_coarse_inc = 0; + C_po_counter_load_en = 0; + C_po_counter_read_en = 0; + C_po_counter_load_val = 0; + C_po_sel_fine_oclk_delay = 0; + + C_idelay_ce = 0; + C_idelay_ld = 0; + C_fine_delay = 0; + C_fine_delay_sel = 0; + + + D_pi_fine_enable = 0; + D_pi_fine_inc = 0; + D_pi_counter_load_en = 0; + D_pi_counter_read_en = 0; + D_pi_counter_load_val = 0; + D_pi_rst_dqs_find = 0; + + + D_po_fine_enable = 0; + D_po_coarse_enable = 0; + D_po_fine_inc = 0; + D_po_coarse_inc = 0; + D_po_counter_load_en = 0; + D_po_counter_read_en = 0; + D_po_counter_load_val = 0; + D_po_sel_fine_oclk_delay = 0; + + D_idelay_ce = 0; + D_idelay_ld = 0; + D_fine_delay = 0; + D_fine_delay_sel = 0; + + end else + if (calib_in_common) begin + // if this is asserted, each signal is broadcast to all phasers + // in common + if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin + A_pi_fine_enable = pi_fine_enable; + A_pi_fine_inc = pi_fine_inc; + A_pi_counter_load_en = pi_counter_load_en; + A_pi_counter_read_en = pi_counter_read_en; + A_pi_counter_load_val = pi_counter_load_val; + A_pi_rst_dqs_find = pi_rst_dqs_find; + + + A_po_fine_enable = po_fine_enable; + A_po_coarse_enable = po_coarse_enable; + A_po_fine_inc = po_fine_inc; + A_po_coarse_inc = po_coarse_inc; + A_po_counter_load_en = po_counter_load_en; + A_po_counter_read_en = po_counter_read_en; + A_po_counter_load_val = po_counter_load_val; + A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + A_idelay_ce = idelay_ce; + A_idelay_ld = idelay_ld; + A_fine_delay = fine_delay ; + A_fine_delay_sel = fine_delay_sel; + end + + if ( B_mux_ctrl) begin + B_pi_fine_enable = pi_fine_enable; + B_pi_fine_inc = pi_fine_inc; + B_pi_counter_load_en = pi_counter_load_en; + B_pi_counter_read_en = pi_counter_read_en; + B_pi_counter_load_val = pi_counter_load_val; + B_pi_rst_dqs_find = pi_rst_dqs_find; + + + B_po_fine_enable = po_fine_enable; + B_po_coarse_enable = po_coarse_enable; + B_po_fine_inc = po_fine_inc; + B_po_coarse_inc = po_coarse_inc; + B_po_counter_load_en = po_counter_load_en; + B_po_counter_read_en = po_counter_read_en; + B_po_counter_load_val = po_counter_load_val; + B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + B_idelay_ce = idelay_ce; + B_idelay_ld = idelay_ld; + B_fine_delay = fine_delay ; + B_fine_delay_sel = fine_delay_sel; + end + + if ( C_mux_ctrl) begin + C_pi_fine_enable = pi_fine_enable; + C_pi_fine_inc = pi_fine_inc; + C_pi_counter_load_en = pi_counter_load_en; + C_pi_counter_read_en = pi_counter_read_en; + C_pi_counter_load_val = pi_counter_load_val; + C_pi_rst_dqs_find = pi_rst_dqs_find; + + + C_po_fine_enable = po_fine_enable; + C_po_coarse_enable = po_coarse_enable; + C_po_fine_inc = po_fine_inc; + C_po_coarse_inc = po_coarse_inc; + C_po_counter_load_en = po_counter_load_en; + C_po_counter_read_en = po_counter_read_en; + C_po_counter_load_val = po_counter_load_val; + C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + C_idelay_ce = idelay_ce; + C_idelay_ld = idelay_ld; + C_fine_delay = fine_delay ; + C_fine_delay_sel = fine_delay_sel; + end + + if ( D_mux_ctrl) begin + D_pi_fine_enable = pi_fine_enable; + D_pi_fine_inc = pi_fine_inc; + D_pi_counter_load_en = pi_counter_load_en; + D_pi_counter_read_en = pi_counter_read_en; + D_pi_counter_load_val = pi_counter_load_val; + D_pi_rst_dqs_find = pi_rst_dqs_find; + + + D_po_fine_enable = po_fine_enable; + D_po_coarse_enable = po_coarse_enable; + D_po_fine_inc = po_fine_inc; + D_po_coarse_inc = po_coarse_inc; + D_po_counter_load_en = po_counter_load_en; + D_po_counter_read_en = po_counter_read_en; + D_po_counter_load_val = po_counter_load_val; + D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + D_idelay_ce = idelay_ce; + D_idelay_ld = idelay_ld; + D_fine_delay = fine_delay ; + D_fine_delay_sel = fine_delay_sel; + end + end + else begin + // otherwise, only a single phaser is selected + + + case (calib_sel[1:0]) + 0: begin + A_pi_fine_enable = pi_fine_enable; + A_pi_fine_inc = pi_fine_inc; + A_pi_counter_load_en = pi_counter_load_en; + A_pi_counter_read_en = pi_counter_read_en; + A_pi_counter_load_val = pi_counter_load_val; + A_pi_rst_dqs_find = pi_rst_dqs_find; + + + A_po_fine_enable = po_fine_enable; + A_po_coarse_enable = po_coarse_enable; + A_po_fine_inc = po_fine_inc; + A_po_coarse_inc = po_coarse_inc; + A_po_counter_load_en = po_counter_load_en; + A_po_counter_read_en = po_counter_read_en; + A_po_counter_load_val = po_counter_load_val; + A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + A_idelay_ce = idelay_ce; + A_idelay_ld = idelay_ld; + A_fine_delay = fine_delay ; + A_fine_delay_sel = fine_delay_sel; + + end + 1: begin + B_pi_fine_enable = pi_fine_enable; + B_pi_fine_inc = pi_fine_inc; + B_pi_counter_load_en = pi_counter_load_en; + B_pi_counter_read_en = pi_counter_read_en; + B_pi_counter_load_val = pi_counter_load_val; + B_pi_rst_dqs_find = pi_rst_dqs_find; + + + B_po_fine_enable = po_fine_enable; + B_po_coarse_enable = po_coarse_enable; + B_po_fine_inc = po_fine_inc; + B_po_coarse_inc = po_coarse_inc; + B_po_counter_load_en = po_counter_load_en; + B_po_counter_read_en = po_counter_read_en; + B_po_counter_load_val = po_counter_load_val; + B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + B_idelay_ce = idelay_ce; + B_idelay_ld = idelay_ld; + B_fine_delay = fine_delay ; + B_fine_delay_sel = fine_delay_sel; + + end + + 2: begin + C_pi_fine_enable = pi_fine_enable; + C_pi_fine_inc = pi_fine_inc; + C_pi_counter_load_en = pi_counter_load_en; + C_pi_counter_read_en = pi_counter_read_en; + C_pi_counter_load_val = pi_counter_load_val; + C_pi_rst_dqs_find = pi_rst_dqs_find; + + + C_po_fine_enable = po_fine_enable; + C_po_coarse_enable = po_coarse_enable; + C_po_fine_inc = po_fine_inc; + C_po_coarse_inc = po_coarse_inc; + C_po_counter_load_en = po_counter_load_en; + C_po_counter_read_en = po_counter_read_en; + C_po_counter_load_val = po_counter_load_val; + C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + C_idelay_ce = idelay_ce; + C_idelay_ld = idelay_ld; + C_fine_delay = fine_delay ; + C_fine_delay_sel = fine_delay_sel; + + end + + 3: begin + D_pi_fine_enable = pi_fine_enable; + D_pi_fine_inc = pi_fine_inc; + D_pi_counter_load_en = pi_counter_load_en; + D_pi_counter_read_en = pi_counter_read_en; + D_pi_counter_load_val = pi_counter_load_val; + D_pi_rst_dqs_find = pi_rst_dqs_find; + + + D_po_fine_enable = po_fine_enable; + D_po_coarse_enable = po_coarse_enable; + D_po_fine_inc = po_fine_inc; + D_po_coarse_inc = po_coarse_inc; + D_po_counter_load_en = po_counter_load_en; + D_po_counter_load_val = po_counter_load_val; + D_po_counter_read_en = po_counter_read_en; + D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay; + + D_idelay_ce = idelay_ce; + D_idelay_ld = idelay_ld; + D_fine_delay = fine_delay ; + D_fine_delay_sel = fine_delay_sel; + + end + endcase + end +end + +//obligatory phaser-ref +PHASER_REF phaser_ref_i( + + .LOCKED (ref_dll_lock), + .CLKIN (freq_refclk), + .PWRDWN (1'b0), + .RST ( ! pll_lock) + +); + + +// optional idelay_ctrl +generate +if ( GENERATE_IDELAYCTRL == "TRUE") +IDELAYCTRL idelayctrl ( + .RDY (/*idelayctrl_rdy*/), + .REFCLK (idelayctrl_refclk), + .RST (rst) +); +endgenerate + + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v new file mode 100644 index 0000000..1b26bfd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v @@ -0,0 +1,234 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_ck_addr_cmd_delay.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Shift CK/Address/Commands/Controls +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay # + ( + parameter TCQ = 100, + parameter tCK = 3636, + parameter DQS_CNT_WIDTH = 3, + parameter N_CTL_LANES = 3, + parameter SIM_CAL_OPTION = "NONE" + ) + ( + input clk, + input rst, + // Start only after PO_CIRC_BUF_DELAY decremented + input cmd_delay_start, + // Control lane being shifted using Phaser_Out fine delay taps + output reg [N_CTL_LANES-1:0] ctl_lane_cnt, + // Inc/dec Phaser_Out fine delay line + output reg po_stg2_f_incdec, + output reg po_en_stg2_f, + output reg po_stg2_c_incdec, + output reg po_en_stg2_c, + // Completed delaying CK/Address/Commands/Controls + output po_ck_addr_cmd_delay_done + ); + + localparam TAP_CNT_LIMIT = 63; + + //Calculate the tap resolution of the PHASER based on the clock period + localparam FREQ_REF_DIV = (tCK > 5000 ? 4 : + tCK > 2500 ? 2 : 1); + + localparam integer PHASER_TAP_RES = ((tCK/2)/64); + + // Determine whether 300 ps or 350 ps delay required + localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300; + + // Determine the number of Phaser_Out taps required to delay by 300 ps + // 300 ps is the PCB trace uncertainty between CK and DQS byte groups + + + // Increment control byte lanes + localparam TAP_CNT = 0; + //localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES; + //Decrement control byte lanes + localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29; + + + + + reg delay_dec_done; + reg delay_done_r1; + reg delay_done_r2; + reg delay_done_r3; + reg delay_done_r4 /* synthesis syn_maxfan = 10 */; + reg [5:0] delay_cnt_r; + reg [5:0] delaydec_cnt_r; + reg po_cnt_inc; + reg po_cnt_dec; + reg [3:0] wait_cnt_r; + + assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4; + + always @(posedge clk) begin + if (rst || po_cnt_dec || po_cnt_inc) + wait_cnt_r <= #TCQ 'd8; + else if (cmd_delay_start && (wait_cnt_r > 'd0)) + wait_cnt_r <= #TCQ wait_cnt_r - 1; + end + + always @(posedge clk) begin + if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0)) + po_cnt_inc <= #TCQ 1'b0; + else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1)) + po_cnt_inc <= #TCQ 1'b1; + else + po_cnt_inc <= #TCQ 1'b0; + end + + //Tap decrement + always @(posedge clk) begin + if (rst || (delaydec_cnt_r == 'd0)) + po_cnt_dec <= #TCQ 1'b0; + else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1)) + po_cnt_dec <= #TCQ 1'b1; + else + po_cnt_dec <= #TCQ 1'b0; + end + + //po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane + //the alignment is started once the + always @(posedge clk) begin + if (rst) begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b0; + po_stg2_c_incdec <= #TCQ 1'b0; + po_en_stg2_c <= #TCQ 1'b0; + end else begin + if (po_cnt_dec) begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b1; + end else begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b0; + end + if (po_cnt_inc) begin + po_stg2_c_incdec <= #TCQ 1'b1; + po_en_stg2_c <= #TCQ 1'b1; + end else begin + po_stg2_c_incdec <= #TCQ 1'b0; + po_en_stg2_c <= #TCQ 1'b0; + end + end + end + + // delay counter to count 2 cycles + // Increment coarse taps by 2 for all control byte lanes + // to mitigate late writes + always @(posedge clk) begin + // load delay counter with init value + if (rst || (tCK >= 2500) || (SIM_CAL_OPTION == "FAST_CAL")) + delay_cnt_r <= #TCQ 'd0; + else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) + delay_cnt_r <= #TCQ 'd1; + else if (po_cnt_inc && (delay_cnt_r > 6'd0)) + delay_cnt_r <= #TCQ delay_cnt_r - 1; + end + + // delay counter to count TAP_DEC cycles + always @(posedge clk) begin + // load delay counter with init value of TAP_DEC + if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1))) + delaydec_cnt_r <= #TCQ TAP_DEC; + else if (po_cnt_dec && (delaydec_cnt_r > 6'd0)) + delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1; + end + + //ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle + //This ensures all ctrl byte lanes have had their output phase shifted. + always @(posedge clk) begin + if (rst || ~cmd_delay_start ) + ctl_lane_cnt <= #TCQ 6'b0; + else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1)) + ctl_lane_cnt <= #TCQ ctl_lane_cnt; + else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0)) + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + end + + // All control lanes have decremented to 31 fine taps from 46 + always @(posedge clk) begin + if (rst || ~cmd_delay_start) begin + delay_dec_done <= #TCQ 1'b0; + end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) || + ((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin + delay_dec_done <= #TCQ 1'b1; + end + end + + + + always @(posedge clk) begin + delay_done_r1 <= #TCQ delay_dec_done; + delay_done_r2 <= #TCQ delay_done_r1; + delay_done_r3 <= #TCQ delay_done_r2; + delay_done_r4 <= #TCQ delay_done_r3; + end + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v new file mode 100644 index 0000000..1f31088 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v @@ -0,0 +1,1199 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_dqs_found_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Read leveling calibration logic +// NOTES: +// 1. Phaser_In DQSFOUND calibration +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ +**$Date: 2011/06/02 08:35:08 $ +**$Author: +**$Revision: +**$Source: +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_dqs_found_cal # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter nCL = 5, // Read CAS latency + parameter AL = "0", + parameter nCWL = 5, // Write CAS latency + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter RANKS = 1, // # of memory ranks in the system + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter REG_CTRL = "ON", // "ON" for registered DIMM + parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps + parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate + parameter N_CTL_LANES = 3, // Number of control byte lanes + parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) + parameter HIGHEST_BANK = 3, // Sum of I/O Banks + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf + ) + ( + input clk, + input rst, + input dqsfound_retry, + // From phy_init + input pi_dqs_found_start, + input detect_pi_found_dqs, + input prech_done, + // DQSFOUND per Phaser_IN + input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + + output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, + + // To phy_init + output [5:0] rd_data_offset_0, + output [5:0] rd_data_offset_1, + output [5:0] rd_data_offset_2, + output pi_dqs_found_rank_done, + output pi_dqs_found_done, + output reg pi_dqs_found_err, + output [6*RANKS-1:0] rd_data_offset_ranks_0, + output [6*RANKS-1:0] rd_data_offset_ranks_1, + output [6*RANKS-1:0] rd_data_offset_ranks_2, + output reg dqsfound_retry_done, + output reg dqs_found_prech_req, + //To MC + output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, + + input [8:0] po_counter_read_val, + output rd_data_offset_cal_done, + output fine_adjust_done, + output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, + output reg ck_po_stg2_f_indec, + output reg ck_po_stg2_f_en, + output [255:0] dbg_dqs_found_cal + ); + + + // For non-zero AL values + localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; + + // Adding the register dimm latency to write latency + localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; + + // Added to reduce simulation time + localparam LATENCY_FACTOR = 13; + + localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; + + localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), + (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), + (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), + (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), + (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), + (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), + (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), + (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), + (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), + (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), + (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), + (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), + (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), + (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), + (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), + (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), + (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), + (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), + (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), + (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; + + localparam FINE_ADJ_IDLE = 4'h0; + localparam RST_POSTWAIT = 4'h1; + localparam RST_POSTWAIT1 = 4'h2; + localparam RST_WAIT = 4'h3; + localparam FINE_ADJ_INIT = 4'h4; + localparam FINE_INC = 4'h5; + localparam FINE_INC_WAIT = 4'h6; + localparam FINE_INC_PREWAIT = 4'h7; + localparam DETECT_PREWAIT = 4'h8; + localparam DETECT_DQSFOUND = 4'h9; + localparam PRECH_WAIT = 4'hA; + localparam FINE_DEC = 4'hB; + localparam FINE_DEC_WAIT = 4'hC; + localparam FINE_DEC_PREWAIT = 4'hD; + localparam FINAL_WAIT = 4'hE; + localparam FINE_ADJ_DONE = 4'hF; + + + integer k,l,m,n,p,q,r,s; + + reg dqs_found_start_r; + reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; + reg rank_done_r; + reg rank_done_r1; + reg dqs_found_done_r; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; + reg init_dqsfound_done_r; + reg init_dqsfound_done_r1; + reg init_dqsfound_done_r2; + reg init_dqsfound_done_r3; + reg init_dqsfound_done_r4; + reg init_dqsfound_done_r5; + reg [1:0] rnk_cnt_r; + reg [2:0 ] final_do_index[0:RANKS-1]; + reg [5:0 ] final_do_max[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; + reg [10*HIGHEST_BANK-1:0] retry_cnt; + reg dqsfound_retry_r1; + wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; + + // CK/Control byte lanes fine adjust stage + reg fine_adjust; + reg [N_CTL_LANES-1:0] ctl_lane_cnt; + reg [3:0] fine_adj_state_r; + reg fine_adjust_done_r; + reg rst_dqs_find; + reg rst_dqs_find_r1; + reg rst_dqs_find_r2; + reg [5:0] init_dec_cnt; + reg [5:0] dec_cnt; + reg [5:0] inc_cnt; + reg final_dec_done; + reg init_dec_done; + reg first_fail_detect; + reg second_fail_detect; + reg [5:0] first_fail_taps; + reg [5:0] second_fail_taps; + reg [5:0] stable_pass_cnt; + reg [3:0] detect_rd_cnt; + + + + + //*************************************************************************** + // Debug signals + // + //*************************************************************************** + assign dbg_dqs_found_cal[5:0] = first_fail_taps; + assign dbg_dqs_found_cal[11:6] = second_fail_taps; + assign dbg_dqs_found_cal[12] = first_fail_detect; + assign dbg_dqs_found_cal[13] = second_fail_detect; + assign dbg_dqs_found_cal[14] = fine_adjust_done_r; + + + assign pi_dqs_found_rank_done = rank_done_r; + assign pi_dqs_found_done = dqs_found_done_r; + + generate + genvar rnk_cnt; + if (HIGHEST_BANK == 3) begin // Three Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; + end + end else if (HIGHEST_BANK == 2) begin // Two Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end else begin // Single Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end + endgenerate + + // final_data_offset is used during write calibration and during + // normal operation. One rd_data_offset value per rank for entire + // interface + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : + final_data_offset[rnk_cnt_r][12+:6]; + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = 'd0; + end else begin + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = 'd0; + assign rd_data_offset_2 = 'd0; + end + endgenerate + + assign rd_data_offset_cal_done = init_dqsfound_done_r; + assign fine_adjust_lane_cnt = ctl_lane_cnt; + + //************************************************************************** + // DQSFOUND all and any generation + // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are + // asserted + // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx + // is asserted + //************************************************************************** + + generate + if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) + assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; + else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) + assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) + assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) + assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; + endgenerate + + always @(posedge clk) begin + if (rst) begin + for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found + pi_dqs_found_all_bank[k] <= #TCQ 'b0; + pi_dqs_found_any_bank[k] <= #TCQ 'b0; + end + end else if (pi_dqs_found_start) begin + for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found + pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & + (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & + (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & + (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); + pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | + (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | + (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | + (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); + end + end + end + + + always @(posedge clk) begin + pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; + pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; + end + +//***************************************************************************** +// Counter to increase number of 4 back-to-back reads per rd_data_offset and +// per CK/A/C tap value +//***************************************************************************** + + always @(posedge clk) begin + if (rst || (detect_rd_cnt == 'd0)) + detect_rd_cnt <= #TCQ NUM_READS; + else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) + detect_rd_cnt <= #TCQ detect_rd_cnt - 1; + end + + + //************************************************************************** + // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls + // + //************************************************************************** + + assign fine_adjust_done = fine_adjust_done_r; + + always @(posedge clk) begin + rst_dqs_find_r1 <= #TCQ rst_dqs_find; + rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; + end + + always @(posedge clk) begin + if(rst)begin + fine_adjust <= #TCQ 1'b0; + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; + fine_adjust_done_r <= #TCQ 1'b0; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b0; + init_dec_cnt <= #TCQ 'd31; + dec_cnt <= #TCQ 'd0; + inc_cnt <= #TCQ 'd0; + init_dec_done <= #TCQ 1'b0; + final_dec_done <= #TCQ 1'b0; + first_fail_detect <= #TCQ 1'b0; + second_fail_detect <= #TCQ 1'b0; + first_fail_taps <= #TCQ 'd0; + second_fail_taps <= #TCQ 'd0; + stable_pass_cnt <= #TCQ 'd0; + dqs_found_prech_req<= #TCQ 1'b0; + end else begin + case (fine_adj_state_r) + + FINE_ADJ_IDLE: begin + if (init_dqsfound_done_r5) begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + rst_dqs_find <= #TCQ 1'b0; + end else begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + rst_dqs_find <= #TCQ 1'b1; + end + end + end + + RST_WAIT: begin + if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin + rst_dqs_find <= #TCQ 1'b0; + if (|init_dec_cnt) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else if (final_dec_done) + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + else + fine_adj_state_r <= #TCQ RST_POSTWAIT; + end + end + + RST_POSTWAIT: begin + fine_adj_state_r <= #TCQ RST_POSTWAIT1; + end + + RST_POSTWAIT1: begin + fine_adj_state_r <= #TCQ FINE_ADJ_INIT; + end + + FINE_ADJ_INIT: begin + //if (detect_pi_found_dqs && (inc_cnt < 'd63)) + fine_adj_state_r <= #TCQ FINE_INC; + end + + FINE_INC: begin + fine_adj_state_r <= #TCQ FINE_INC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b1; + ck_po_stg2_f_en <= #TCQ 1'b1; + if (ctl_lane_cnt == N_CTL_LANES-1) + inc_cnt <= #TCQ inc_cnt + 1; + end + + FINE_INC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + end + + FINE_INC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_INC; + end + + DETECT_PREWAIT: begin + if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) + fine_adj_state_r <= #TCQ DETECT_DQSFOUND; + else + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + + DETECT_DQSFOUND: begin + if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ 'd0; + if (~first_fail_detect && (inc_cnt == 'd63)) begin + // First failing tap detected at 63 taps + // then decrement to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin + // First failing tap detected at greater than 30 taps + // then stop looking for second edge and decrement + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ (inc_cnt>>1) + 1; + end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin + // First failing tap detected, continue incrementing + // until either second failing tap detected or 63 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin + // Consecutive 30 taps of passing region was not found + // continue incrementing + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt == 'd63)) begin + if (stable_pass_cnt < 'd30) begin + // Consecutive 30 taps of passing region was not found + // from tap 0 to 63 so decrement back to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else begin + // Consecutive 30 taps of passing region was found + // between first_fail_taps and 63 + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end else begin + // Second failing tap detected, decrement to center of + // failing taps + second_fail_detect <= #TCQ 1'b1; + second_fail_taps <= #TCQ inc_cnt; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + fine_adj_state_r <= #TCQ FINE_DEC; + end + end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ stable_pass_cnt + 1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || + (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else if (inc_cnt < 'd63) begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end else begin + fine_adj_state_r <= #TCQ FINE_DEC; + if (~first_fail_detect || (first_fail_taps > 'd33)) + // No failing taps detected, decrement by 31 + dec_cnt <= #TCQ 'd32; + //else if (first_fail_detect && (stable_pass_cnt > 'd28)) + // // First failing tap detected between 0 and 34 + // // decrement midpoint between 63 and failing tap + // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + else + // First failing tap detected + // decrement to midpoint between 63 and failing tap + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end + end + + PRECH_WAIT: begin + if (prech_done) begin + dqs_found_prech_req <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + end + + + FINE_DEC: begin + fine_adj_state_r <= #TCQ FINE_DEC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b1; + if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) + init_dec_cnt <= #TCQ init_dec_cnt - 1; + else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) + dec_cnt <= #TCQ dec_cnt - 1; + end + + FINE_DEC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else begin + fine_adj_state_r <= #TCQ FINAL_WAIT; + if ((init_dec_cnt == 'd0) && ~init_dec_done) + init_dec_done <= #TCQ 1'b1; + else + final_dec_done <= #TCQ 1'b1; + end + end + end + + FINE_DEC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_DEC; + end + + FINAL_WAIT: begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + + FINE_ADJ_DONE: begin + if (&pi_dqs_found_all_bank) begin + fine_adjust_done_r <= #TCQ 1'b1; + rst_dqs_find <= #TCQ 1'b0; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + end + end + + endcase + end + end + + + + +//***************************************************************************** + + + always@(posedge clk) + dqs_found_start_r <= #TCQ pi_dqs_found_start; + + + always @(posedge clk) begin + if (rst) + rnk_cnt_r <= #TCQ 2'b00; + else if (init_dqsfound_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r; + else if (rank_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + end + + //***************************************************************** + // Read data_offset calibration done signal + //***************************************************************** + + always @(posedge clk) begin + if (rst || (|pi_rst_stg1_cal_r)) + init_dqsfound_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank) begin + if (rnk_cnt_r == RANKS-1) + init_dqsfound_done_r <= #TCQ 1'b1; + else + init_dqsfound_done_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst || + (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) + rank_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) + rank_done_r <= #TCQ 1'b1; + else + rank_done_r <= #TCQ 1'b0; + end + + always @(posedge clk) begin + pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; + pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; + pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; + init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; + init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; + init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; + init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; + init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; + rank_done_r1 <= #TCQ rank_done_r; + dqsfound_retry_r1 <= #TCQ dqsfound_retry; + end + + + always @(posedge clk) begin + if (rst) + dqs_found_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && + (fine_adj_state_r == FINE_ADJ_DONE)) + dqs_found_done_r <= #TCQ 1'b1; + else + dqs_found_done_r <= #TCQ 1'b0; + end + + + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[2]) || + (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[20+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[2]) + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; + else + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[2] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[2] <= #TCQ 1'b1; + end + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; + end + + always @(posedge clk) begin + if (rst) begin + for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop + rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && + //(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][12+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1; + end + +//***************************************************************************** +// Two I/O Bank Interface +//***************************************************************************** + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; + end +//***************************************************************************** +// One I/O Bank Interface +//***************************************************************************** + end else begin // One I/O Bank Interface + + // Read data offset value for all DQS in Bank0 + always @(posedge clk) begin + if (rst) begin + for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop + rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1))) + rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r] + <= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1; + end + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted even with 3 dqfound retries + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + end + endgenerate + + always @(posedge clk) begin + if (rst) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; + else if (rst_dqs_find) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; + else + pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; + end + + + + // Final read data offset value to be used during write calibration and + // normal operation + generate + genvar i; + genvar j; + for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop + reg [5:0] final_do_cand [RANKS-1:0]; + // combinatorially select the candidate offset for the bank + // indexed by final_do_index + if (HIGHEST_BANK == 3) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; + default: final_do_cand[i] = 'd0; + endcase + end + end else if (HIGHEST_BANK == 2) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end else begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = 'd0; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end + + always @(posedge clk) begin + if (rst) + final_do_max[i] <= #TCQ 0; + else begin + final_do_max[i] <= #TCQ final_do_max[i]; // default + case (final_do_index[i]) + 3'b000: if ( | DATA_PRESENT[3:0]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b001: if ( | DATA_PRESENT[7:4]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b010: if ( | DATA_PRESENT[11:8]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + default: + final_do_max[i] <= #TCQ final_do_max[i]; + endcase + end + end + + always @(posedge clk) + if (rst) begin + final_do_index[i] <= #TCQ 0; + end + else begin + final_do_index[i] <= #TCQ final_do_index[i] + 1; + end + + for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop + + always @(posedge clk) begin + if (rst) begin + final_data_offset[i][6*j+:6] <= #TCQ 'b0; + end + else begin + //if (dqsfound_retry[j]) + // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + //else + if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin + if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane + final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + if (CWL_M % 2) // odd latency CAS slot 1 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; + else // even latency CAS slot 0 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + end + end + else if (init_dqsfound_done_r5 ) begin + if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes + final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; + final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; + end + end + end + end + end + end + endgenerate + + + // Error generation in case pi_found_dqs signal from Phaser_IN + // is not asserted when a common rddata_offset value is used + + always @(posedge clk) begin + pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; + end + + + +endmodule + + + + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v new file mode 100644 index 0000000..ea56635 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v @@ -0,0 +1,1200 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_dqs_found_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Read leveling calibration logic +// NOTES: +// 1. Phaser_In DQSFOUND calibration +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ +**$Date: 2011/06/02 08:35:08 $ +**$Author: +**$Revision: +**$Source: +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_dqs_found_cal_hr # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter nCL = 5, // Read CAS latency + parameter AL = "0", + parameter nCWL = 5, // Write CAS latency + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter RANKS = 1, // # of memory ranks in the system + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter REG_CTRL = "ON", // "ON" for registered DIMM + parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps + parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate + parameter N_CTL_LANES = 3, // Number of control byte lanes + parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) + parameter HIGHEST_BANK = 3, // Sum of I/O Banks + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf + ) + ( + input clk, + input rst, + input dqsfound_retry, + // From phy_init + input pi_dqs_found_start, + input detect_pi_found_dqs, + input prech_done, + // DQSFOUND per Phaser_IN + input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, + + output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, + + // To phy_init + output [5:0] rd_data_offset_0, + output [5:0] rd_data_offset_1, + output [5:0] rd_data_offset_2, + output pi_dqs_found_rank_done, + output pi_dqs_found_done, + output reg pi_dqs_found_err, + output [6*RANKS-1:0] rd_data_offset_ranks_0, + output [6*RANKS-1:0] rd_data_offset_ranks_1, + output [6*RANKS-1:0] rd_data_offset_ranks_2, + output reg dqsfound_retry_done, + output reg dqs_found_prech_req, + //To MC + output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, + output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, + + input [8:0] po_counter_read_val, + output rd_data_offset_cal_done, + output fine_adjust_done, + output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, + output reg ck_po_stg2_f_indec, + output reg ck_po_stg2_f_en, + output [255:0] dbg_dqs_found_cal + ); + + + // For non-zero AL values + localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; + + // Adding the register dimm latency to write latency + localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; + + // Added to reduce simulation time + localparam LATENCY_FACTOR = 13; + + localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; + + localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), + (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), + (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), + (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), + (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), + (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), + (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), + (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), + (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), + (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), + (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), + (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), + (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), + (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), + (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), + (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), + (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), + (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), + (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), + (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; + + localparam FINE_ADJ_IDLE = 4'h0; + localparam RST_POSTWAIT = 4'h1; + localparam RST_POSTWAIT1 = 4'h2; + localparam RST_WAIT = 4'h3; + localparam FINE_ADJ_INIT = 4'h4; + localparam FINE_INC = 4'h5; + localparam FINE_INC_WAIT = 4'h6; + localparam FINE_INC_PREWAIT = 4'h7; + localparam DETECT_PREWAIT = 4'h8; + localparam DETECT_DQSFOUND = 4'h9; + localparam PRECH_WAIT = 4'hA; + localparam FINE_DEC = 4'hB; + localparam FINE_DEC_WAIT = 4'hC; + localparam FINE_DEC_PREWAIT = 4'hD; + localparam FINAL_WAIT = 4'hE; + localparam FINE_ADJ_DONE = 4'hF; + + + integer k,l,m,n,p,q,r,s; + + reg dqs_found_start_r; + reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; + reg rank_done_r; + reg rank_done_r1; + reg dqs_found_done_r; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; + reg init_dqsfound_done_r; + reg init_dqsfound_done_r1; + reg init_dqsfound_done_r2; + reg init_dqsfound_done_r3; + reg init_dqsfound_done_r4; + reg init_dqsfound_done_r5; + reg [1:0] rnk_cnt_r; + reg [2:0 ] final_do_index[0:RANKS-1]; + reg [5:0 ] final_do_max[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; + reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; + reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; + reg [10*HIGHEST_BANK-1:0] retry_cnt; + reg dqsfound_retry_r1; + wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; + reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; + reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; + + // CK/Control byte lanes fine adjust stage + reg fine_adjust; + reg [N_CTL_LANES-1:0] ctl_lane_cnt; + reg [3:0] fine_adj_state_r; + reg fine_adjust_done_r; + reg rst_dqs_find; + reg rst_dqs_find_r1; + reg rst_dqs_find_r2; + reg [5:0] init_dec_cnt; + reg [5:0] dec_cnt; + reg [5:0] inc_cnt; + reg final_dec_done; + reg init_dec_done; + reg first_fail_detect; + reg second_fail_detect; + reg [5:0] first_fail_taps; + reg [5:0] second_fail_taps; + reg [5:0] stable_pass_cnt; + reg [3:0] detect_rd_cnt; + + + + + //*************************************************************************** + // Debug signals + // + //*************************************************************************** + assign dbg_dqs_found_cal[5:0] = first_fail_taps; + assign dbg_dqs_found_cal[11:6] = second_fail_taps; + assign dbg_dqs_found_cal[12] = first_fail_detect; + assign dbg_dqs_found_cal[13] = second_fail_detect; + assign dbg_dqs_found_cal[14] = fine_adjust_done_r; + + + assign pi_dqs_found_rank_done = rank_done_r; + assign pi_dqs_found_done = dqs_found_done_r; + + generate + genvar rnk_cnt; + if (HIGHEST_BANK == 3) begin // Three Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; + end + end else if (HIGHEST_BANK == 2) begin // Two Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end else begin // Single Bank Interface + for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop + assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; + assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; + assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; + assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; + end + end + endgenerate + + // final_data_offset is used during write calibration and during + // normal operation. One rd_data_offset value per rank for entire + // interface + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : + final_data_offset[rnk_cnt_r][12+:6]; + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : + final_data_offset[rnk_cnt_r][6+:6]; + assign rd_data_offset_2 = 'd0; + end else begin + assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : + final_data_offset[rnk_cnt_r][0+:6]; + assign rd_data_offset_1 = 'd0; + assign rd_data_offset_2 = 'd0; + end + endgenerate + + assign rd_data_offset_cal_done = init_dqsfound_done_r; + assign fine_adjust_lane_cnt = ctl_lane_cnt; + + //************************************************************************** + // DQSFOUND all and any generation + // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are + // asserted + // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx + // is asserted + //************************************************************************** + + generate + if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) + assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; + else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) + assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) + assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; + else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) + assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; + endgenerate + + always @(posedge clk) begin + if (rst) begin + for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found + pi_dqs_found_all_bank[k] <= #TCQ 'b0; + pi_dqs_found_any_bank[k] <= #TCQ 'b0; + end + end else if (pi_dqs_found_start) begin + for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found + pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & + (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & + (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & + (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); + pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | + (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | + (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | + (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); + end + end + end + + + always @(posedge clk) begin + pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; + pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; + end + +//***************************************************************************** +// Counter to increase number of 4 back-to-back reads per rd_data_offset and +// per CK/A/C tap value +//***************************************************************************** + + always @(posedge clk) begin + if (rst || (detect_rd_cnt == 'd0)) + detect_rd_cnt <= #TCQ NUM_READS; + else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) + detect_rd_cnt <= #TCQ detect_rd_cnt - 1; + end + + //************************************************************************** + // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls + // + //************************************************************************** + + assign fine_adjust_done = fine_adjust_done_r; + + always @(posedge clk) begin + rst_dqs_find_r1 <= #TCQ rst_dqs_find; + rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; + end + + always @(posedge clk) begin + if(rst)begin + fine_adjust <= #TCQ 1'b0; + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; + fine_adjust_done_r <= #TCQ 1'b0; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b0; + init_dec_cnt <= #TCQ 'd31; + dec_cnt <= #TCQ 'd0; + inc_cnt <= #TCQ 'd0; + init_dec_done <= #TCQ 1'b0; + final_dec_done <= #TCQ 1'b0; + first_fail_detect <= #TCQ 1'b0; + second_fail_detect <= #TCQ 1'b0; + first_fail_taps <= #TCQ 'd0; + second_fail_taps <= #TCQ 'd0; + stable_pass_cnt <= #TCQ 'd0; + dqs_found_prech_req<= #TCQ 1'b0; + end else begin + case (fine_adj_state_r) + + FINE_ADJ_IDLE: begin + if (init_dqsfound_done_r5) begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + rst_dqs_find <= #TCQ 1'b0; + end else begin + fine_adjust <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + rst_dqs_find <= #TCQ 1'b1; + end + end + end + + RST_WAIT: begin + if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin + rst_dqs_find <= #TCQ 1'b0; + if (|init_dec_cnt) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else if (final_dec_done) + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + else + fine_adj_state_r <= #TCQ RST_POSTWAIT; + end + end + + RST_POSTWAIT: begin + fine_adj_state_r <= #TCQ RST_POSTWAIT1; + end + + RST_POSTWAIT1: begin + fine_adj_state_r <= #TCQ FINE_ADJ_INIT; + end + + FINE_ADJ_INIT: begin + //if (detect_pi_found_dqs && (inc_cnt < 'd63)) + fine_adj_state_r <= #TCQ FINE_INC; + end + + FINE_INC: begin + fine_adj_state_r <= #TCQ FINE_INC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b1; + ck_po_stg2_f_en <= #TCQ 1'b1; + if (ctl_lane_cnt == N_CTL_LANES-1) + inc_cnt <= #TCQ inc_cnt + 1; + end + + FINE_INC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + end + + FINE_INC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_INC; + end + + DETECT_PREWAIT: begin + if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) + fine_adj_state_r <= #TCQ DETECT_DQSFOUND; + else + fine_adj_state_r <= #TCQ DETECT_PREWAIT; + end + + DETECT_DQSFOUND: begin + if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ 'd0; + if (~first_fail_detect && (inc_cnt == 'd63)) begin + // First failing tap detected at 63 taps + // then decrement to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin + // First failing tap detected at greater than 30 taps + // then stop looking for second edge and decrement + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ (inc_cnt>>1) + 1; + end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin + // First failing tap detected, continue incrementing + // until either second failing tap detected or 63 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin + // Consecutive 30 taps of passing region was not found + // continue incrementing + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + rst_dqs_find <= #TCQ 1'b1; + if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else + fine_adj_state_r <= #TCQ RST_WAIT; + end else if (first_fail_detect && (inc_cnt == 'd63)) begin + if (stable_pass_cnt < 'd30) begin + // Consecutive 30 taps of passing region was not found + // from tap 0 to 63 so decrement back to 31 + first_fail_detect <= #TCQ 1'b1; + first_fail_taps <= #TCQ inc_cnt; + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ 'd32; + end else begin + // Consecutive 30 taps of passing region was found + // between first_fail_taps and 63 + fine_adj_state_r <= #TCQ FINE_DEC; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end else begin + // Second failing tap detected, decrement to center of + // failing taps + second_fail_detect <= #TCQ 1'b1; + second_fail_taps <= #TCQ inc_cnt; + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + fine_adj_state_r <= #TCQ FINE_DEC; + end + end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin + stable_pass_cnt <= #TCQ stable_pass_cnt + 1; + if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || + (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin + dqs_found_prech_req <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ PRECH_WAIT; + end else if (inc_cnt < 'd63) begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end else begin + fine_adj_state_r <= #TCQ FINE_DEC; + if (~first_fail_detect || (first_fail_taps > 'd33)) + // No failing taps detected, decrement by 31 + dec_cnt <= #TCQ 'd32; + //else if (first_fail_detect && (stable_pass_cnt > 'd28)) + // // First failing tap detected between 0 and 34 + // // decrement midpoint between 63 and failing tap + // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + else + // First failing tap detected + // decrement to midpoint between 63 and failing tap + dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); + end + end + end + + PRECH_WAIT: begin + if (prech_done) begin + dqs_found_prech_req <= #TCQ 1'b0; + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + end + + + FINE_DEC: begin + fine_adj_state_r <= #TCQ FINE_DEC_WAIT; + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b1; + if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) + init_dec_cnt <= #TCQ init_dec_cnt - 1; + else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) + dec_cnt <= #TCQ dec_cnt - 1; + end + + FINE_DEC_WAIT: begin + ck_po_stg2_f_indec <= #TCQ 1'b0; + ck_po_stg2_f_en <= #TCQ 1'b0; + if (ctl_lane_cnt != N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + end else if (ctl_lane_cnt == N_CTL_LANES-1) begin + ctl_lane_cnt <= #TCQ 'd0; + if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) + fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; + else begin + fine_adj_state_r <= #TCQ FINAL_WAIT; + if ((init_dec_cnt == 'd0) && ~init_dec_done) + init_dec_done <= #TCQ 1'b1; + else + final_dec_done <= #TCQ 1'b1; + end + end + end + + FINE_DEC_PREWAIT: begin + fine_adj_state_r <= #TCQ FINE_DEC; + end + + FINAL_WAIT: begin + rst_dqs_find <= #TCQ 1'b1; + fine_adj_state_r <= #TCQ RST_WAIT; + end + + FINE_ADJ_DONE: begin + if (&pi_dqs_found_all_bank) begin + fine_adjust_done_r <= #TCQ 1'b1; + rst_dqs_find <= #TCQ 1'b0; + fine_adj_state_r <= #TCQ FINE_ADJ_DONE; + end + end + + endcase + end + end + + + + +//***************************************************************************** + + + always@(posedge clk) + dqs_found_start_r <= #TCQ pi_dqs_found_start; + + + always @(posedge clk) begin + if (rst) + rnk_cnt_r <= #TCQ 2'b00; + else if (init_dqsfound_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r; + else if (rank_done_r) + rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + end + + //***************************************************************** + // Read data_offset calibration done signal + //***************************************************************** + + always @(posedge clk) begin + if (rst || (|pi_rst_stg1_cal_r)) + init_dqsfound_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank) begin + if (rnk_cnt_r == RANKS-1) + init_dqsfound_done_r <= #TCQ 1'b1; + else + init_dqsfound_done_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst || + (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) + rank_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) + rank_done_r <= #TCQ 1'b1; + else + rank_done_r <= #TCQ 1'b0; + end + + always @(posedge clk) begin + pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; + pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; + pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; + init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; + init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; + init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; + init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; + init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; + rank_done_r1 <= #TCQ rank_done_r; + dqsfound_retry_r1 <= #TCQ dqsfound_retry; + end + + + always @(posedge clk) begin + if (rst) + dqs_found_done_r <= #TCQ 1'b0; + else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && + (fine_adj_state_r == FINE_ADJ_DONE)) + dqs_found_done_r <= #TCQ 1'b1; + else + dqs_found_done_r <= #TCQ 1'b0; + end + + + generate + if (HIGHEST_BANK == 3) begin // Three I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[2]) || + (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) + pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[20+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[2]) + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; + else + retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; + end + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[2] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[2] <= #TCQ 1'b1; + end + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; + end + + always @(posedge clk) begin + if (rst) begin + for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop + rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && + //(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][12+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1; + end + +//***************************************************************************** +// Two I/O Bank Interface +//***************************************************************************** + end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[1]) || + (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) + pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[10+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[1]) + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; + else + retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; + end + + + // Error generation in case pi_dqs_found_all_bank + // is not asserted + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[1] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[1] <= #TCQ 1'b1; + end + + + // Read data offset value for all DQS in a Bank + always @(posedge clk) begin + if (rst) begin + for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop + rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][0+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; + end + + always @(posedge clk) begin + if (rst) begin + for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop + rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && + //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r][6+:6] + <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; + end +//***************************************************************************** +// One I/O Bank Interface +//***************************************************************************** + end else begin // One I/O Bank Interface + + // Read data offset value for all DQS in Bank0 + always @(posedge clk) begin + if (rst) begin + for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop + rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2; + end + end else if ((rank_done_r1 && ~init_dqsfound_done_r) || + (rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1))) + rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2; + else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && + //(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) && + (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) + rd_byte_data_offset[rnk_cnt_r] + <= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1; + end + + // Reset read data offset calibration in all DQS Phaser_INs + // in a Bank after the read data offset value for a rank is determined + // or if within a Bank DQSFOUND is not asserted for all DQSs + always @(posedge clk) begin + if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; + else if ((pi_dqs_found_start && ~dqs_found_start_r) || + //(dqsfound_retry[0]) || + (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || fine_adjust) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + else if (pi_rst_stg1_cal_r[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; + else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) + pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; + end + + //***************************************************************************** + // Retry counter to track number of DQSFOUND retries + //***************************************************************************** + + always @(posedge clk) begin + if (rst || rank_done_r) + retry_cnt[0+:10] <= #TCQ 'b0; + else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && + ~pi_dqs_found_all_bank[0]) + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; + else + retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; + end + + + // Error generation in case pi_dqs_found_all_bank + // is not asserted even with 3 dqfound retries + always @(posedge clk) begin + if (rst) + pi_dqs_found_err_r[0] <= #TCQ 1'b0; + else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && + (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) + pi_dqs_found_err_r[0] <= #TCQ 1'b1; + end + + end + endgenerate + + always @(posedge clk) begin + if (rst) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; + else if (rst_dqs_find) + pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; + else + pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; + end + + + + // Final read data offset value to be used during write calibration and + // normal operation + generate + genvar i; + genvar j; + for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop + reg [5:0] final_do_cand [RANKS-1:0]; + // combinatorially select the candidate offset for the bank + // indexed by final_do_index + if (HIGHEST_BANK == 3) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; + default: final_do_cand[i] = 'd0; + endcase + end + end else if (HIGHEST_BANK == 2) begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end else begin + always @(*) begin + case (final_do_index[i]) + 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; + 3'b001: final_do_cand[i] = 'd0; + 3'b010: final_do_cand[i] = 'd0; + default: final_do_cand[i] = 'd0; + endcase + end + end + + always @(posedge clk) begin + if (rst) + final_do_max[i] <= #TCQ 0; + else begin + final_do_max[i] <= #TCQ final_do_max[i]; // default + case (final_do_index[i]) + 3'b000: if ( | DATA_PRESENT[3:0]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b001: if ( | DATA_PRESENT[7:4]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + 3'b010: if ( | DATA_PRESENT[11:8]) + if (final_do_max[i] < final_do_cand[i]) + if (CWL_M % 2) // odd latency CAS slot 1 + final_do_max[i] <= #TCQ final_do_cand[i] - 1; + else + final_do_max[i] <= #TCQ final_do_cand[i]; + default: + final_do_max[i] <= #TCQ final_do_max[i]; + endcase + end + end + + always @(posedge clk) + if (rst) begin + final_do_index[i] <= #TCQ 0; + end + else begin + final_do_index[i] <= #TCQ final_do_index[i] + 1; + end + + for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop + + always @(posedge clk) begin + if (rst) begin + final_data_offset[i][6*j+:6] <= #TCQ 'b0; + end + else begin + //if (dqsfound_retry[j]) + // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + //else + if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin + if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane + final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + if (CWL_M % 2) // odd latency CAS slot 1 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; + else // even latency CAS slot 0 + final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; + end + end + else if (init_dqsfound_done_r5 ) begin + if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes + final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; + final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; + end + end + end + end + end + end + endgenerate + + + // Error generation in case pi_found_dqs signal from Phaser_IN + // is not asserted when a common rddata_offset value is used + + always @(posedge clk) begin + pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; + end + + + +endmodule + + + + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v new file mode 100644 index 0000000..036d4ec --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v @@ -0,0 +1,5498 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_init.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Memory initialization and overall master state control during +// initialization and calibration. Specifically, the following functions +// are performed: +// 1. Memory initialization (initial AR, mode register programming, etc.) +// 2. Initiating write leveling +// 3. Generate training pattern writes for read leveling. Generate +// memory readback for read leveling. +// This module has an interface for providing control/address and write +// data to the PHY Control Block during initialization/calibration. +// Once initialization and calibration are complete, control is passed to the MC. +// +//Reference: +//Revision History: +// +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ +**$Date: 2011/06/02 08:35:09 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + + +module mig_7series_v4_2_ddr_phy_init # + ( + parameter tCK = 1500, // DDRx SDRAM clock period + parameter TCQ = 100, + parameter nCK_PER_CLK = 4, // # of memory clocks per CLK + parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) + parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA + // 1 - ODT output from FPGA + parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 + // 150 - 1.50 V + // 135 - 1.35 V + // 125 - 1.25 V + parameter VREF = "EXTERNAL", // Internal or external Vref + parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH + parameter BANK_WIDTH = 2, + parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank + parameter COL_WIDTH = 10, + parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for + // component I/F with CS_WIDTH=1, + // nCS_PER_RANK=# of components + parameter DQ_WIDTH = 64, + parameter DQS_WIDTH = 8, + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter ROW_WIDTH = 14, + parameter CS_WIDTH = 1, + parameter RANKS = 1, // # of memory ranks in the interface + parameter CKE_WIDTH = 1, // # of cke outputs + parameter DRAM_TYPE = "DDR3", + parameter REG_CTRL = "ON", + parameter ADDR_CMD_MODE= "1T", + + // calibration Address + parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address + parameter CALIB_COL_ADD = 12'h000, // Calibration column address + parameter CALIB_BA_ADD = 3'h0, // Calibration bank address + + // DRAM mode settings + parameter AL = "0", // Additive Latency option + parameter BURST_MODE = "8", // Burst length + parameter BURST_TYPE = "SEQ", // Burst type +// parameter nAL = 0, // Additive latency (in clk cyc) + parameter nCL = 5, // Read CAS latency (in clk cyc) + parameter nCWL = 5, // Write CAS latency (in clk cyc) + parameter tRFC = 110000, // Refresh-to-command delay (in ps) + parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes + parameter REFRESH_TIMER_WIDTH = 8, + parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option + parameter RTT_NOM = "60", // Nominal ODT termination value + parameter RTT_WR = "60", // Write ODT termination value + parameter WRLVL = "ON", // Enable write leveling +// parameter PHASE_DETECT = "ON", // Enable read phase detector + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter nSLOTS = 1, // Number of DIMM SLOTs in the system + parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" + parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" + parameter CKE_ODT_AUX = "FALSE", + parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration + parameter TEST_AL = "0", // Internal use for ICM verification + parameter FIXED_VICTIM = "TRUE", + parameter BYPASS_COMPLEX_OCAL = "FALSE", + parameter SKIP_CALIB = "FALSE" + ) + ( + input clk, + input rst, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, + input delay_incdec_done, + input ck_addr_cmd_delay_done, + input pi_phase_locked_all, + input pi_dqs_found_done, + input dqsfound_retry, + input dqs_found_prech_req, + output reg pi_phaselock_start, + output pi_phase_locked_err, + output pi_calib_done, + input phy_if_empty, + // Read/write calibration interface + input wrlvl_done, + input wrlvl_rank_done, + input wrlvl_byte_done, + input wrlvl_byte_redo, + input wrlvl_final, + output reg wrlvl_final_if_rst, + input oclkdelay_calib_done, + input oclk_prech_req, + input oclk_calib_resume, + input lim_done, + input lim_wr_req, + output reg oclkdelay_calib_start, + //complex oclkdelay calibration + input complex_oclkdelay_calib_done, + input complex_oclk_prech_req, + input complex_oclk_calib_resume, + output reg complex_oclkdelay_calib_start, + input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt + output reg complex_ocal_num_samples_inc, + input complex_ocal_num_samples_done_r, + input [2:0] complex_ocal_rd_victim_sel, + output reg complex_ocal_reset_rd_addr, + input complex_ocal_ref_req, + output reg complex_ocal_ref_done, + + input done_dqs_tap_inc, + input [5:0] rd_data_offset_0, + input [5:0] rd_data_offset_1, + input [5:0] rd_data_offset_2, + input [6*RANKS-1:0] rd_data_offset_ranks_0, + input [6*RANKS-1:0] rd_data_offset_ranks_1, + input [6*RANKS-1:0] rd_data_offset_ranks_2, + input pi_dqs_found_rank_done, + input wrcal_done, + input wrcal_prech_req, + input wrcal_read_req, + input wrcal_act_req, + input temp_wrcal_done, + input [7:0] slot_0_present, + input [7:0] slot_1_present, + output reg wl_sm_start, + output reg wr_lvl_start, + output reg wrcal_start, + output reg wrcal_rd_wait, + output reg wrcal_sanity_chk, + output reg tg_timer_done, + output reg no_rst_tg_mc, + input rdlvl_stg1_done, + input rdlvl_stg1_rank_done, + output reg rdlvl_stg1_start, + output reg pi_dqs_found_start, + output reg detect_pi_found_dqs, + // rdlvl stage 1 precharge requested after each DQS + input rdlvl_prech_req, + input rdlvl_last_byte_done, + input wrcal_resume, + input wrcal_sanity_chk_done, + // MPR read leveling + input mpr_rdlvl_done, + input mpr_rnk_done, + input mpr_last_byte_done, + output reg mpr_rdlvl_start, + output reg mpr_end_if_reset, + + // PRBS Read Leveling + input prbs_rdlvl_done, + input prbs_last_byte_done, + input prbs_rdlvl_prech_req, + input complex_victim_inc, + input [2:0] rd_victim_sel, + input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, + output reg [2:0] victim_sel, + output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, + output reg prbs_rdlvl_start, + output reg prbs_gen_clk_en, + output reg prbs_gen_oclk_clk_en, + output reg complex_sample_cnt_inc, + output reg complex_sample_cnt_inc_ocal, + output reg complex_wr_done, + + // Signals shared btw multiple calibration stages + output reg prech_done, + // Data select / status + output reg init_calib_complete, + // Signal to mask memory model error for Invalid latching edge + output reg calib_writes, + // PHY address/control + // 2 commands to PHY Control Block per div 2 clock in 2:1 mode + // 4 commands to PHY Control Block per div 4 clock in 4:1 mode + output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, + output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, + output reg [nCK_PER_CLK-1:0] phy_ras_n, + output reg [nCK_PER_CLK-1:0] phy_cas_n, + output reg [nCK_PER_CLK-1:0] phy_we_n, + output reg phy_reset_n, + output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, + + // Hard PHY Interface signals + input phy_ctl_ready, + input phy_ctl_full, + input phy_cmd_full, + input phy_data_full, + output reg calib_ctl_wren, + output reg calib_cmd_wren, + output reg [1:0] calib_seq, + output reg write_calib, + output reg read_calib, + // PHY_Ctl_Wd + output reg [2:0] calib_cmd, + // calib_aux_out used for CKE and ODT + output reg [3:0] calib_aux_out, + output reg [1:0] calib_odt , + output reg [nCK_PER_CLK-1:0] calib_cke , + output [1:0] calib_rank_cnt, + output reg [1:0] calib_cas_slot, + output reg [5:0] calib_data_offset_0, + output reg [5:0] calib_data_offset_1, + output reg [5:0] calib_data_offset_2, + // PHY OUT_FIFO + output reg calib_wrdata_en, + output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, + // PHY Read + output phy_rddata_en, + output phy_rddata_valid, + output [255:0] dbg_phy_init, + input reset_rd_addr, + //OCAL centering calibration + input oclkdelay_center_calib_start, + input oclk_center_write_resume, + input oclkdelay_center_calib_done, + input rdlvl_pi_incdec, //rdlvl pi dec + input complex_pi_incdec_done, + input num_samples_done_r, + input complex_init_pi_dec_done, + output reg complex_act_start, + output reg calib_tap_inc_start, + output reg calib_tap_end_if_reset, + input calib_tap_inc_done + ); + +//***************************************************************************** +// Assertions to be added +//***************************************************************************** +// The phy_ctl_full signal must never be asserted in synchronous mode of +// operation either 4:1 or 2:1 +// +// The RANKS parameter must never be set to '0' by the user +// valid values: 1 to 4 +// +//***************************************************************************** + + //*************************************************************************** + + // Number of Read level stage 1 writes limited to a SDRAM row + // The address of Read Level stage 1 reads must also be limited + // to a single SDRAM row + // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 + localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : + (BURST_MODE == "4") ? 8 : 4; + + + localparam ADDR_INC = (BURST_MODE == "8") ? 8 : + (BURST_MODE == "4") ? 4 : 8; + + // In a 2 slot dual rank per system RTT_NOM values + // for Rank2 and Rank3 default to 40 ohms + localparam RTT_NOM2 = "40"; + localparam RTT_NOM3 = "40"; + + localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; + + // Specifically for use with half-frequency controller (nCK_PER_CLK=2) + // = 1 if burst length = 4, = 0 if burst length = 8. Determines how + // often row command needs to be issued during read-leveling + // For DDR3 the burst length is fixed during calibration + localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : + (BURST_MODE == "8") ? 1'b0 : + ((BURST_MODE == "4") ? 1'b1 : 1'b0); + + + + + //*************************************************************************** + // Counter values used to determine bus timing + // NOTE on all counter terminal counts - these can/should be one less than + // the actual delay to take into account extra clock cycle delay in + // generating the corresponding "done" signal + //*************************************************************************** + + localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; + + // Calculate initial delay required in number of CLK clock cycles + // to delay initially. The counter is clocked by [CLK/1024] - which + // is approximately division by 1000 - note that the formulas below will + // result in more than the minimum wait time because of this approximation. + // NOTE: For DDR3 JEDEC specifies to delay reset + // by 200us, and CKE by an additional 500us after power-up + // For DDR2 CKE is delayed by 200us after power up. + localparam DDR3_RESET_DELAY_NS = 200000; + localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; + localparam DDR2_CKE_DELAY_NS = 200000; + localparam PWRON_RESET_DELAY_CNT = + ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); + localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? + (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : + (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); + // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation + // needs to be reworked. + localparam DDR2_INIT_PRE_DELAY_PS = 400000; + localparam DDR2_INIT_PRE_CNT = + ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; + + // Calculate tXPR time: reset from CKE HIGH to valid command after power-up + // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock + // cycles because this counter actually starts up before CKE is asserted + // to memory. + localparam TXPR_DELAY_CNT = + (5*CLK_MEM_PERIOD > tRFC+10000) ? + (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : + (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; + + // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV + localparam TDLLK_TZQINIT_DELAY_CNT = 255; + + // TWR values in ns. Both DDR2 and DDR3 have the same value. + // 15000ns/tCK + localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? + (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; + + // time to wait between consecutive commands in PHY_INIT - this is a + // generic number, and must be large enough to account for worst case + // timing parameter (tRFC - refresh-to-active) across all memory speed + // grades and operating frequencies. Expressed in clk + // (Divided by 4 or Divided by 2) clock cycles. + localparam CNTNEXT_CMD = 7'b1111111; + + // Counter values to keep track of which MR register to load during init + // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode + // register configured during initialization. + // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init + localparam INIT_CNT_MR2 = 2'b00; + localparam INIT_CNT_MR3 = 2'b01; + localparam INIT_CNT_MR1 = 2'b10; + localparam INIT_CNT_MR0 = 2'b11; + localparam INIT_CNT_MR_DONE = 2'b11; + + // Register chip programmable values for DDR3 + // The register chip for the registered DIMM needs to be programmed + // before the initialization of the registered DIMM. + // Address for the control word is in : DBA2, DA2, DA1, DA0 + // Data for the control word is in: DBA1 DBA0, DA4, DA3 + // The values will be stored in the local param in the following format + // {DBA[2:0], DA[4:0]} + + // RC0 is global features control word. Address == 000 + + localparam REG_RC0 = 8'b00000000; + + // RC1 Clock driver enable control word. Enables or disables the four + // output clocks in the register chip. For single rank and dual rank + // two clocks will be enabled and for quad rank all the four clocks + // will be enabled. Address == 000. Data = 0110 for single and dual rank. + // = 0000 for quad rank + localparam REG_RC1 = 8'b00000001; + + // RC2 timing control word. Set in 1T timing mode + // Address = 010. Data = 0000 + localparam REG_RC2 = 8'b00000010; + + // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) + // This setting is specific to RDIMMs from Micron Technology + localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; + + // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) + // This setting is specific to RDIMMs from Micron Technology + localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; + + // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) + // This setting is specific to RDIMMs from Micron Technology + localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; + + // RC10 timing control work. Setting the data to 0000 + localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : + (tCK >= 1250 && tCK < 1500) ? 4'b0011 : + (tCK >= 1500 && tCK < 1875) ? 4'b0010 : + (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; + + localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; + + localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; + localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : + (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : + {1'b0,VREF_ENCODING,2'b00} ; + + localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; + + // For non-zero AL values + localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; + + // Adding the register dimm latency to write latency + localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; + + // Count value to generate pi_phase_locked_err signal + localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; + + // Timeout interval for detecting error with Traffic Generator + localparam [13:0] TG_TIMER_TIMEOUT + = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; + + //bit num per DQS + localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; + + //COMPLEX_ROW_CNT_BYTE + localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; + localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; + + // Master state machine encoding + localparam INIT_IDLE = 7'b0000000; //0 + localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 + localparam INIT_LOAD_MR = 7'b0000010; //2 + localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 + localparam INIT_ZQCL = 7'b0000100; //4 + localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 + localparam INIT_WRLVL_START = 7'b0000110; //6 + localparam INIT_WRLVL_WAIT = 7'b0000111; //7 + localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 + localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 + localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A + localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B + localparam INIT_RDLVL_ACT = 7'b0001100; //C + localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D + localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E + localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F + localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 + localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 + localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 + localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 + localparam INIT_PRECHARGE = 7'b0010100; //14 + localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 + localparam INIT_DONE = 7'b0010110; //16 + localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 + localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 + localparam INIT_REFRESH = 7'b0011001; //19 + localparam INIT_REFRESH_WAIT = 7'b0011010; //1A + localparam INIT_REG_WRITE = 7'b0011011; //1B + localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C + localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D + localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E + localparam INIT_WRCAL_ACT = 7'b0011111; //1F + localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 + localparam INIT_WRCAL_WRITE = 7'b0100001; //21 + localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 + localparam INIT_WRCAL_READ = 7'b0100011; //23 + localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 + localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 + localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 + localparam INIT_MPR_RDEN = 7'b0100111; //27 + localparam INIT_MPR_WAIT = 7'b0101000; //28 + localparam INIT_MPR_READ = 7'b0101001; //29 + localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A + localparam INIT_MPR_DISABLE = 7'b0101011; //2B + localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C + localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D + localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E + localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F + localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 + localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 + localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 + localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 + localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 + localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 + localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 + localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 + localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 + localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 + localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A + localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B + localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C + localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D + localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E + localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F + localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 + localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 + localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 + localparam INIT_RDLVL_COMPLEX_PI_WAIT = 7'b1000011; //43 + localparam INIT_SKIP_CALIB_WAIT = 7'b1000100; //44 + + integer i, j, k, l, m, n, p, q; + + reg pi_dqs_found_all_r; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; + (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; + reg pi_calib_rank_done_r; + reg [13:0] pi_phaselock_timer; + reg stg1_wr_done; + reg rnk_ref_cnt; + reg pi_dqs_found_done_r1; + reg pi_dqs_found_rank_done_r; + reg read_calib_int; + reg read_calib_r; + reg pi_calib_done_r; + reg pi_calib_done_r1; + reg burst_addr_r; + reg [1:0] chip_cnt_r; + reg [6:0] cnt_cmd_r; + reg cnt_cmd_done_r; + reg cnt_cmd_done_m7_r; + reg [7:0] cnt_dllk_zqinit_r; + reg cnt_dllk_zqinit_done_r; + reg cnt_init_af_done_r; + reg [1:0] cnt_init_af_r; + reg [1:0] cnt_init_data_r; + reg [1:0] cnt_init_mr_r; + reg cnt_init_mr_done_r; + reg cnt_init_pre_wait_done_r; + reg [7:0] cnt_init_pre_wait_r; + reg [9:0] cnt_pwron_ce_r; + reg cnt_pwron_cke_done_r; + reg cnt_pwron_cke_done_r1; + reg [8:0] cnt_pwron_r; + reg cnt_pwron_reset_done_r; + reg cnt_txpr_done_r; + reg [7:0] cnt_txpr_r; + reg ddr2_pre_flag_r; + reg ddr2_refresh_flag_r; + reg ddr3_lm_done_r; + reg [4:0] enable_wrlvl_cnt; + reg init_complete_r; + reg init_complete_r1; + reg init_complete_r2; +(* keep = "true" *) reg init_complete_r_timing; +(* keep = "true" *) reg init_complete_r1_timing; + reg [6:0] init_next_state; + reg [6:0] init_state_r; + reg [6:0] init_state_r1; + wire [15:0] load_mr0; + wire [15:0] load_mr1; + wire [15:0] load_mr2; + wire [15:0] load_mr3; + reg mem_init_done_r; + reg [1:0] mr2_r [0:3]; + reg [2:0] mr1_r [0:3]; + reg new_burst_r; + reg [15:0] wrcal_start_dly_r; + wire wrcal_start_pre; + reg wrcal_resume_r; + // Only one ODT signal per rank in PHY Control Block + reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; + reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; + + reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; + reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; + wire prech_done_pre; + reg [15:0] prech_done_dly_r; + reg prech_pending_r; + reg prech_req_posedge_r; + reg prech_req_r; + reg pwron_ce_r; + reg first_rdlvl_pat_r; + reg first_wrcal_pat_r; + reg phy_wrdata_en; + reg phy_wrdata_en_r1; + reg [1:0] wrdata_pat_cnt; + reg [1:0] wrcal_pat_cnt; + reg [ROW_WIDTH-1:0] address_w; + reg [BANK_WIDTH-1:0] bank_w; + reg rdlvl_stg1_done_r1; + reg rdlvl_stg1_start_int; + reg [15:0] rdlvl_start_dly0_r; + reg rdlvl_start_pre; + reg rdlvl_last_byte_done_r; + wire rdlvl_rd; + wire rdlvl_wr; + reg rdlvl_wr_r; + wire rdlvl_wr_rd; + reg [3:0] reg_ctrl_cnt_r; + reg [1:0] tmp_mr2_r [0:3]; + reg [2:0] tmp_mr1_r [0:3]; + reg wrlvl_done_r; + reg wrlvl_done_r1; + reg wrlvl_rank_done_r1; + reg wrlvl_rank_done_r2; + reg wrlvl_rank_done_r3; + reg wrlvl_rank_done_r4; + reg wrlvl_rank_done_r5; + reg wrlvl_rank_done_r6; + reg wrlvl_rank_done_r7; + reg [2:0] wrlvl_rank_cntr; + reg wrlvl_odt_ctl; + reg wrlvl_odt; + reg wrlvl_active; + reg wrlvl_active_r1; + reg [2:0] num_reads; + reg temp_wrcal_done_r; + reg temp_lmr_done; + reg extend_cal_pat; + reg [13:0] tg_timer; + reg tg_timer_go; + reg cnt_wrcal_rd; + reg [3:0] cnt_wait; + reg [7:0] wrcal_reads; + reg [8:0] stg1_wr_rd_cnt; + reg phy_data_full_r; + reg wr_level_dqs_asrt; + reg wr_level_dqs_asrt_r1; + reg [1:0] dqs_asrt_cnt; + + + reg [3:0] num_refresh; + wire oclkdelay_calib_start_pre; + reg [15:0] oclkdelay_start_dly_r; + reg [3:0] oclk_wr_cnt; + reg [3:0] wrcal_wr_cnt; + reg wrlvl_final_r; + + + reg prbs_rdlvl_done_r1; + reg prbs_rdlvl_done_r2; + reg prbs_rdlvl_done_r3; + reg prbs_last_byte_done_r; + reg phy_if_empty_r; + reg prbs_pat_resume_int; + reg complex_row0_wr_done; + reg complex_row1_wr_done; + reg complex_row0_rd_done; + reg complex_row1_rd_done; + reg complex_row0_rd_done_r1; + reg [3:0] complex_wait_cnt; + reg [3:0] complex_num_reads; + reg [3:0] complex_num_reads_dec; + reg [ROW_WIDTH-1:0] complex_address; + reg wr_victim_inc; + reg [2:0] wr_victim_sel; + reg [7:0] complex_row_cnt; + + reg complex_sample_cnt_inc_r1; + reg complex_sample_cnt_inc_r2; + reg complex_odt_ext; + reg complex_ocal_odt_ext; + + reg wrcal_final_chk; + wire prech_req; + + reg reset_rd_addr_r1; + reg complex_rdlvl_int_ref_req; + reg ext_int_ref_req; + + //complex OCLK delay calibration + reg [7:0] complex_row_cnt_ocal; + reg [4:0] complex_num_writes; + reg [4:0] complex_num_writes_dec; + reg complex_oclkdelay_calib_start_int; + reg complex_oclkdelay_calib_start_r1; + reg complex_oclkdelay_calib_start_r2; + reg complex_oclkdelay_calib_done_r1; + // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; + reg [2:0] wr_victim_sel_ocal; + + reg complex_row1_rd_done_r1; //time for switch to write + reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) + reg complex_byte_rd_done; //read for the byte is done + reg complex_byte_rd_done_r1; + // reg complex_row_change; //every 16 rows of read, it is set to "0" for write + reg ocal_num_samples_inc; //1 read/write is done + reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen + + reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining + reg prech_done_r1, prech_done_r2, prech_done_r3; + reg mask_lim_done; + reg complex_mask_lim_done; + reg oclkdelay_calib_start_int; + reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; + reg oclkdelay_int_ref_req; + reg [3:0] ocal_act_wait_cnt; + reg oclk_calib_resume_level; + reg ocal_last_byte_done; + wire mmcm_wr; //MMCM centering write. no CS will be set + + wire exit_ocal_complex_resume_wait = + init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; + + reg calib_tap_inc_done_r1; + + + + //*************************************************************************** + // Debug + //*************************************************************************** + + //synthesis translate_off + always @(posedge mem_init_done_r) begin + if (!rst) + $display ("PHY_INIT: Memory Initialization completed at %t", $time); + end + + always @(posedge wrlvl_done) begin + if (!rst && (WRLVL == "ON")) + $display ("PHY_INIT: Write Leveling completed at %t", $time); + end + + always @(posedge rdlvl_stg1_done) begin + if (!rst) + $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); + end + + always @(posedge mpr_rdlvl_done) begin + if (!rst) + $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); + end + + always @(posedge oclkdelay_calib_done) begin + if (!rst) + $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); + end + + always @(posedge pi_calib_done_r1) begin + if (!rst) + $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); + end + + always @(posedge pi_dqs_found_done) begin + if (!rst) + $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); + end + + always @(posedge wrcal_done) begin + if (!rst && (WRLVL == "ON")) + $display ("PHY_INIT: Write Calibration completed at %t", $time); + end + + always@(posedge prbs_rdlvl_done)begin + if(!rst) + $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); + end + + + always@(posedge complex_oclkdelay_calib_done)begin + if(!rst) + $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); + end + always@(posedge oclkdelay_center_calib_done)begin + if(!rst) + $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); + end + + //synthesis translate_on + + assign dbg_phy_init[5:0] = init_state_r; + assign dbg_phy_init[6+:8] = complex_row_cnt; + assign dbg_phy_init[14+:3] = victim_sel; + assign dbg_phy_init[17+:4] = victim_byte_cnt; + assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; + assign dbg_phy_init[30+:15] = complex_address; + assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; + assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; + assign dbg_phy_init[61] =prech_req_posedge_r ; + + + //*************************************************************************** + // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage + //*************************************************************************** + +// assign pi_phaselock_calib_cnt = dqs_cnt_r; + + assign pi_calib_done = pi_calib_done_r1; + + //prevent PI incdec during complex read + always @ (posedge clk) + complex_act_start <= #TCQ (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT); + + //detect rising edge of prbs_rdlvl_done to reset all control sighals + always @ (posedge clk) begin + prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; + end + + always @(posedge clk) begin + if (rst) + wrcal_final_chk <= #TCQ 1'b0; + else if ((init_next_state == INIT_WRCAL_ACT) && (wrcal_done || (SKIP_CALIB == "TRUE")) && + (DRAM_TYPE == "DDR3")) + wrcal_final_chk <= #TCQ 1'b1; + end + + always @(posedge clk) begin + rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; + prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; + prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; + prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; + wrcal_resume_r <= #TCQ wrcal_resume; + wrcal_sanity_chk <= #TCQ wrcal_final_chk; + end + + always @(posedge clk) begin + if (rst) + mpr_end_if_reset <= #TCQ 1'b0; + else if (mpr_last_byte_done && (num_refresh != 'd0)) + mpr_end_if_reset <= #TCQ 1'b1; + else + mpr_end_if_reset <= #TCQ 1'b0; + end + + // Siganl to mask memory model error for Invalid latching edge + + always @(posedge clk) + if (rst) + calib_writes <= #TCQ 1'b0; + else if ((init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ)) + calib_writes <= #TCQ 1'b1; + else + calib_writes <= #TCQ 1'b0; + + always @(posedge clk) + if (rst) + wrcal_rd_wait <= #TCQ 1'b0; + else if (init_state_r == INIT_WRCAL_READ_WAIT) + wrcal_rd_wait <= #TCQ 1'b1; + else + wrcal_rd_wait <= #TCQ 1'b0; + + //*************************************************************************** + // Signal PHY completion when calibration is finished + // Signal assertion is delayed by four clock cycles to account for the + // multi cycle path constraint to (phy_init_data_sel) signal. + //*************************************************************************** + + always @(posedge clk) + if (rst) begin + init_complete_r <= #TCQ 1'b0; + init_complete_r_timing <= #TCQ 1'b0; + init_complete_r1 <= #TCQ 1'b0; + init_complete_r1_timing <= #TCQ 1'b0; + init_complete_r2 <= #TCQ 1'b0; + init_calib_complete <= #TCQ 1'b0; + end else begin + if (init_state_r == INIT_DONE) begin + init_complete_r <= #TCQ 1'b1; + init_complete_r_timing <= #TCQ 1'b1; + end + init_complete_r1 <= #TCQ init_complete_r; + init_complete_r1_timing <= #TCQ init_complete_r_timing; + init_complete_r2 <= #TCQ init_complete_r1; + init_calib_complete <= #TCQ init_complete_r2; + end + + always @ (posedge clk) + if (rst) + complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; + else + complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; + + //reset read address for starting complex ocaldealy calib + always @ (posedge clk) begin + complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); + + end + + //first write for complex oclkdealy calib + always @ (posedge clk) begin + if (rst) + complex_ocal_wr_start <= #TCQ 'b0; + else + complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; + end + + //ocal stg3 centering start +// always @ (posedge clk) +// if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; +// else +// oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; + + //*************************************************************************** + // Instantiate FF for the phy_init_data_sel signal. A multi cycle path + // constraint will be assigned to this signal. This signal will only be + // used within the PHY + //*************************************************************************** + +// FDRSE u_ff_phy_init_data_sel +// ( +// .Q (phy_init_data_sel), +// .C (clk), +// .CE (1'b1), +// .D (init_complete_r), +// .R (1'b0), +// .S (1'b0) +// ) /* synthesis syn_preserve=1 */ +// /* synthesis syn_replicate = 0 */; + + + //*************************************************************************** + // Mode register programming + //*************************************************************************** + + //***************************************************************** + // DDR3 Load mode reg0 + // Mode Register (MR0): + // [15:13] - unused - 000 + // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), + // 1 (DLL maintained) + // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) + // [8] - DLL reset - 0 or 1 + // [7] - Test Mode - 0 (normal) + // [6:4],[2] - CAS latency - CAS_LAT + // [3] - Burst Type - BURST_TYPE + // [1:0] - Burst Length - BURST_LEN + // DDR2 Load mode register + // Mode Register (MR): + // [15:14] - unused - 00 + // [13] - reserved - 0 + // [12] - Power-down mode - 0 (normal) + // [11:9] - write recovery - write recovery for Auto Precharge + // (tWR/tCK = 6) + // [8] - DLL reset - 0 or 1 + // [7] - Test Mode - 0 (normal) + // [6:4] - CAS latency - CAS_LAT + // [3] - Burst Type - BURST_TYPE + // [2:0] - Burst Length - BURST_LEN + + //***************************************************************** + generate + if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 + assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : + (BURST_MODE == "OTF") ? 2'b01 : + (BURST_MODE == "4") ? 2'b10 : 2'b11; + assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency + assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; + assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : + ((nCL == 6) || (nCL == 14)) ? 3'b010 : + (nCL == 7) ? 3'b011 : + (nCL == 8) ? 3'b100 : + (nCL == 9) ? 3'b101 : + (nCL == 10) ? 3'b110 : + (nCL == 11) ? 3'b111 : + (nCL == 12) ? 3'b000 : 3'b111; + assign load_mr0[7] = 1'b0; + assign load_mr0[8] = 1'b1; // Reset DLL (init only) + assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : + (TWR_CYC == 6) ? 3'b010 : + (TWR_CYC == 7) ? 3'b011 : + (TWR_CYC == 8) ? 3'b100 : + (TWR_CYC == 9) ? 3'b101 : + (TWR_CYC == 10) ? 3'b101 : + (TWR_CYC == 11) ? 3'b110 : + (TWR_CYC == 12) ? 3'b110 : + (TWR_CYC == 13) ? 3'b111 : + (TWR_CYC == 14) ? 3'b111 : + (TWR_CYC == 15) ? 3'b000 : + (TWR_CYC == 16) ? 3'b000 : 3'b010; + assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' + assign load_mr0[15:13] = 3'b000; + end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen + assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : + (BURST_MODE == "4") ? 3'b010 : 3'b111; + assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; + assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : + (nCL == 4) ? 3'b100 : + (nCL == 5) ? 3'b101 : + (nCL == 6) ? 3'b110 : 3'b111; + assign load_mr0[7] = 1'b0; + assign load_mr0[8] = 1'b1; // Reset DLL (init only) + assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : + (TWR_CYC == 3) ? 3'b010 : + (TWR_CYC == 4) ? 3'b011 : + (TWR_CYC == 5) ? 3'b100 : + (TWR_CYC == 6) ? 3'b101 : 3'b010; + assign load_mr0[15:12]= 4'b0000; // Reserved + end + endgenerate + + //***************************************************************** + // DDR3 Load mode reg1 + // Mode Register (MR1): + // [15:13] - unused - 00 + // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) + // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) + // [10] - reserved - 0 (must be '0') + // [9] - RTT[2] - 0 + // [8] - reserved - 0 (must be '0') + // [7] - write leveling - 0 (disabled), 1 (enabled) + // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) + // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) + // [4:3] - Additive CAS - ADDITIVE_CAS + // [2] - RTT[0] + // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) + // [0] - DLL enable - 0 (normal) + // DDR2 ext mode register + // Extended Mode Register (MR): + // [15:14] - unused - 00 + // [13] - reserved - 0 + // [12] - output enable - 0 (enabled) + // [11] - RDQS enable - 0 (disabled) + // [10] - DQS# enable - 0 (enabled) + // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) + // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) + // [5:3] - Additive CAS - ADDITIVE_CAS + // [2] - RTT[0] + // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) + // [0] - DLL enable - 0 (normal) + //***************************************************************** + + generate + if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 + assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization + assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; + assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || + (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; + assign load_mr1[4:3] = (AL == "0") ? 2'b00 : + (AL == "CL-1") ? 2'b01 : + (AL == "CL-2") ? 2'b10 : 2'b11; + assign load_mr1[5] = 1'b0; + assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? + 1'b1 : 1'b0; + assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence + assign load_mr1[8] = 1'b0; + assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? + 1'b1 : 1'b0; + assign load_mr1[10] = 1'b0; + assign load_mr1[15:11] = 5'b00000; + end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 + assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization + assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; + assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? + 1'b1 : 1'b0; + assign load_mr1[5:3] = (AL == "0") ? 3'b000 : + (AL == "1") ? 3'b001 : + (AL == "2") ? 3'b010 : + (AL == "3") ? 3'b011 : + (AL == "4") ? 3'b100 : 3'b111; + assign load_mr1[6] = ((RTT_NOM_int == "50") || + (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; + assign load_mr1[9:7] = 3'b000; + assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; + assign load_mr1[15:11] = 5'b00000; + + end + endgenerate + + //***************************************************************** + // DDR3 Load mode reg2 + // Mode Register (MR2): + // [15:11] - unused - 00 + // [10:9] - RTT_WR - 00 (Dynamic ODT off) + // [8] - reserved - 0 (must be '0') + // [7] - self-refresh temperature range - + // 0 (normal), 1 (extended) + // [6] - Auto Self-Refresh - 0 (manual), 1(auto) + // [5:3] - CAS Write Latency (CWL) - + // 000 (5 for 400 MHz device), + // 001 (6 for 400 MHz to 533 MHz devices), + // 010 (7 for 533 MHz to 667 MHz devices), + // 011 (8 for 667 MHz to 800 MHz) + // [2:0] - Partial Array Self-Refresh (Optional) - + // 000 (full array) + // Not used for DDR2 + //***************************************************************** + generate + if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 + assign load_mr2[2:0] = 3'b000; + assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : + (nCWL == 6) ? 3'b001 : + (nCWL == 7) ? 3'b010 : + (nCWL == 8) ? 3'b011 : + (nCWL == 9) ? 3'b100 : + (nCWL == 10) ? 3'b101 : + (nCWL == 11) ? 3'b110 : 3'b111; + assign load_mr2[6] = 1'b0; + assign load_mr2[7] = 1'b0; + assign load_mr2[8] = 1'b0; + // Dynamic ODT disabled + assign load_mr2[10:9] = 2'b00; + assign load_mr2[15:11] = 5'b00000; + end else begin: gen_load_mr2_DDR2 + assign load_mr2[15:0] = 16'd0; + end + endgenerate + + //***************************************************************** + // DDR3 Load mode reg3 + // Mode Register (MR3): + // [15:3] - unused - All zeros + // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) + // [1:0] - MPR location - 00 (Predefined pattern) + //***************************************************************** + + assign load_mr3[1:0] = 2'b00; + assign load_mr3[2] = 1'b0; + assign load_mr3[15:3] = 13'b0000000000000; + + // For multi-rank systems the rank being accessed during writes in + // Read Leveling must be sent to phy_write for the bitslip logic + assign calib_rank_cnt = chip_cnt_r; + + //*************************************************************************** + // Logic to begin initial calibration, and to handle precharge requests + // during read-leveling (to avoid tRAS violations if individual read + // levelling calibration stages take more than max{tRAS) to complete). + //*************************************************************************** + + // Assert when readback for each stage of read-leveling begins. However, + // note this indicates only when the read command is issued and when + // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not + // indicate when the read data is present on the bus (when this happens + // after the read command is issued depends on CAS LATENCY) - there will + // need to be some delay before valid data is present on the bus. +// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); + + // Assert when read back for oclkdelay calibration begins + assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); + + // Assert when read back for write calibration begins + assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); + + // Common precharge signal done signal - pulses only when there has been + // a precharge issued as a result of a PRECH_REQ pulse. Note also a common + // PRECH_DONE signal is used for all blocks + assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || + (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || + (init_state_r == INIT_MPR_RDEN) || + ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || + ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || + ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done + (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && + prech_pending_r && + !prech_req_posedge_r); + + always @(posedge clk) + if (rst) + calib_tap_inc_start <= #TCQ 1'b0; + else if (init_state_r == INIT_SKIP_CALIB_WAIT) + calib_tap_inc_start <= #TCQ 1'b1; + + always @(posedge clk) + calib_tap_inc_done_r1 <= #TCQ calib_tap_inc_done; + + always @(posedge clk) + if (rst || (init_state_r == INIT_WRCAL_WRITE)) + calib_tap_end_if_reset <= #TCQ 1'b0; + else if (calib_tap_inc_done && ~calib_tap_inc_done_r1) + calib_tap_end_if_reset <= #TCQ 1'b1; + + always @(posedge clk) + if (rst) + pi_phaselock_start <= #TCQ 1'b0; + else if (init_state_r == INIT_PI_PHASELOCK_READS) + pi_phaselock_start <= #TCQ 1'b1; + + // Delay start of each calibration by 16 clock cycles to ensure that when + // calibration logic begins, read data is already appearing on the bus. + // Each circuit should synthesize using an SRL16. Assume that reset is + // long enough to clear contents of SRL16. + always @(posedge clk) begin + rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; + prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; + rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], + rdlvl_start_pre}; + wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], + wrcal_start_pre}; + oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], + oclkdelay_calib_start_pre}; + prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], + prech_done_pre}; + end + + always @(posedge clk) + if (rst) + oclkdelay_calib_start_int <= #TCQ 1'b0; + else if (oclkdelay_start_dly_r[5]) + oclkdelay_calib_start_int <= #TCQ 1'b1; + + always @(posedge clk) begin + if (rst) + ocal_last_byte_done <= #TCQ 1'b0; + else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) + ocal_last_byte_done <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) + oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; + else if (oclkdelay_calib_start_int) begin + if (oclkdelay_ref_cnt > 'd0) + oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; + else + oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; + end + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) + oclkdelay_int_ref_req <= #TCQ 1'b0; + else if (oclkdelay_ref_cnt == 'd1) + oclkdelay_int_ref_req <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst) + ocal_act_wait_cnt <= #TCQ 'd0; + else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) + ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; + else + ocal_act_wait_cnt <= #TCQ 'd0; + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_OCLKDELAY_READ)) + oclk_calib_resume_level <= #TCQ 1'b0; + else if (oclk_calib_resume) + oclk_calib_resume_level <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) + complex_rdlvl_int_ref_req <= #TCQ 1'b0; + else if (oclkdelay_ref_cnt == 'd1) +// complex_rdlvl_int_ref_req <= #TCQ 1'b1; + complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue + end + + always @(posedge clk) begin + if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) + ext_int_ref_req <= #TCQ 1'b0; + else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) + ext_int_ref_req <= #TCQ 1'b1; + end + + + always @(posedge clk) begin + prech_done <= #TCQ prech_done_dly_r[15]; + prech_done_r1 <= #TCQ prech_done_dly_r[15]; + prech_done_r2 <= #TCQ prech_done_r1; + prech_done_r3 <= #TCQ prech_done_r2; + end + + + always @(posedge clk) + if (rst) + mpr_rdlvl_start <= #TCQ 1'b0; + else if (pi_dqs_found_done && + (init_state_r == INIT_MPR_READ)) + mpr_rdlvl_start <= #TCQ 1'b1; + + always @(posedge clk) + phy_if_empty_r <= #TCQ phy_if_empty; + + always @(posedge clk) + if (rst || + ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) + prbs_gen_clk_en <= #TCQ 1'b0; + else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || + ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || + ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) + || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) + prbs_gen_clk_en <= #TCQ 1'b1; + + //Enable for complex oclkdelay - used in prbs gen + always @(posedge clk) + if (rst || + ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || + (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || + ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || + (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || + (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT)) + prbs_gen_oclk_clk_en <= #TCQ 1'b0; + else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 + ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || + ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || + exit_ocal_complex_resume_wait || + ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) + || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) + prbs_gen_oclk_clk_en <= #TCQ 1'b1; + +generate +if (RANKS < 2) begin + always @(posedge clk) + if (rst) begin + rdlvl_stg1_start <= #TCQ 1'b0; + rdlvl_stg1_start_int <= #TCQ 1'b0; + rdlvl_start_pre <= #TCQ 1'b0; + prbs_rdlvl_start <= #TCQ 1'b0; + end else begin + if (pi_dqs_found_done && cnt_cmd_done_r && + (init_state_r == INIT_RDLVL_ACT_WAIT)) + rdlvl_stg1_start_int <= #TCQ 1'b1; + if (pi_dqs_found_done && + (init_state_r == INIT_RDLVL_STG1_READ))begin + rdlvl_start_pre <= #TCQ 1'b1; + rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; + end + if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && + (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin + prbs_rdlvl_start <= #TCQ 1'b1; + end + end +end else begin + always @(posedge clk) + if (rst || rdlvl_stg1_rank_done) begin + rdlvl_stg1_start <= #TCQ 1'b0; + rdlvl_stg1_start_int <= #TCQ 1'b0; + rdlvl_start_pre <= #TCQ 1'b0; + prbs_rdlvl_start <= #TCQ 1'b0; + end else begin + if (pi_dqs_found_done && cnt_cmd_done_r && + (init_state_r == INIT_RDLVL_ACT_WAIT)) + rdlvl_stg1_start_int <= #TCQ 1'b1; + if (pi_dqs_found_done && + (init_state_r == INIT_RDLVL_STG1_READ))begin + rdlvl_start_pre <= #TCQ 1'b1; + rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; + end + if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && + (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin + prbs_rdlvl_start <= #TCQ 1'b1; + end + end +end +endgenerate + + + always @(posedge clk) begin + if (rst || dqsfound_retry || wrlvl_byte_redo) begin + pi_dqs_found_start <= #TCQ 1'b0; + wrcal_start <= #TCQ 1'b0; + end else begin + if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) + pi_dqs_found_start <= #TCQ 1'b1; + if (wrcal_start_dly_r[5]) + wrcal_start <= #TCQ 1'b1; + end + end // else: !if(rst) + + + always @(posedge clk) + if (rst) + oclkdelay_calib_start <= #TCQ 1'b0; + else if (oclkdelay_start_dly_r[5]) + oclkdelay_calib_start <= #TCQ 1'b1; + + always @(posedge clk) + if (rst) + pi_dqs_found_done_r1 <= #TCQ 1'b0; + else + pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; + + + always @(posedge clk) + wrlvl_final_r <= #TCQ wrlvl_final; + + // Reset IN_FIFO after final write leveling to make sure the FIFO + // pointers are initialized + always @(posedge clk) + if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) + wrlvl_final_if_rst <= #TCQ 1'b0; + else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && + (init_state_r == INIT_WRLVL_LOAD_MR2)) + wrlvl_final_if_rst <= #TCQ 1'b1; + + // Constantly enable DQS while write leveling is enabled in the memory + // This is more to get rid of warnings in simulation, can later change + // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted + + always @(posedge clk) + if (rst || + ((init_state_r1 != INIT_WRLVL_START) && + (init_state_r == INIT_WRLVL_START))) + wrlvl_odt_ctl <= #TCQ 1'b0; + else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) + wrlvl_odt_ctl <= #TCQ 1'b1; + + generate + if (nCK_PER_CLK == 4) begin: en_cnt_div4 + always @ (posedge clk) + if (rst) + enable_wrlvl_cnt <= #TCQ 5'd0; + else if ((init_state_r == INIT_WRLVL_START) || + (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) + enable_wrlvl_cnt <= #TCQ 5'd12; + else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) + enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; + + // ODT stays asserted as long as write_calib + // signal is asserted + always @(posedge clk) + if (rst || wrlvl_odt_ctl) + wrlvl_odt <= #TCQ 1'b0; + else if (enable_wrlvl_cnt == 5'd1) + wrlvl_odt <= #TCQ 1'b1; + + end else begin: en_cnt_div2 + always @ (posedge clk) + if (rst) + enable_wrlvl_cnt <= #TCQ 5'd0; + else if ((init_state_r == INIT_WRLVL_START) || + (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) + enable_wrlvl_cnt <= #TCQ 5'd21; + else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) + enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; + + // ODT stays asserted as long as write_calib + // signal is asserted + always @(posedge clk) + if (rst || wrlvl_odt_ctl) + wrlvl_odt <= #TCQ 1'b0; + else if (enable_wrlvl_cnt == 5'd1) + wrlvl_odt <= #TCQ 1'b1; + + end + endgenerate + + always @(posedge clk) + if (rst || wrlvl_rank_done || done_dqs_tap_inc) + wrlvl_active <= #TCQ 1'b0; + else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) + wrlvl_active <= #TCQ 1'b1; + +// signal used to assert DQS for write leveling. +// the DQS will be asserted once every 16 clock cycles. + always @(posedge clk)begin + if(rst || (enable_wrlvl_cnt != 5'd1)) begin + wr_level_dqs_asrt <= #TCQ 1'd0; + end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin + wr_level_dqs_asrt <= #TCQ 1'd1; + end + end + + always @ (posedge clk) begin + if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) + dqs_asrt_cnt <= #TCQ 2'd0; + else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) + dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); + end + + always @ (posedge clk) begin + if (rst || ~wrlvl_active) + wr_lvl_start <= #TCQ 1'd0; + else if (dqs_asrt_cnt == 2'd3) + wr_lvl_start <= #TCQ 1'd1; + end + + + always @(posedge clk) begin + if (rst) + wl_sm_start <= #TCQ 1'b0; + else + wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; + end + + + always @(posedge clk) begin + wrlvl_active_r1 <= #TCQ wrlvl_active; + wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; + wrlvl_done_r <= #TCQ wrlvl_done; + wrlvl_done_r1 <= #TCQ wrlvl_done_r; + wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; + wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; + wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; + wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; + wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; + wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; + wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; + end + + always @ (posedge clk) begin + //if (rst) + wrlvl_rank_cntr <= #TCQ 3'd0; + //else if (wrlvl_rank_done) + // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; + end + + //***************************************************************** + // Precharge request logic - those calibration logic blocks + // that require greater than tRAS(max) to finish must break up + // their calibration into smaller units of time, with precharges + // issued in between. This is done using the XXX_PRECH_REQ and + // PRECH_DONE handshaking between PHY_INIT and those blocks + //***************************************************************** + + // Shared request from multiple sources + assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | + (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); + + // Handshaking logic to force precharge during read leveling, and to + // notify read leveling logic when precharge has been initiated and + // it's okay to proceed with leveling again + always @(posedge clk) + if (rst) begin + prech_req_r <= #TCQ 1'b0; + prech_req_posedge_r <= #TCQ 1'b0; + prech_pending_r <= #TCQ 1'b0; + end else begin + prech_req_r <= #TCQ prech_req; + prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; + if (prech_req_posedge_r) + prech_pending_r <= #TCQ 1'b1; + // Clear after we've finished with the precharge and have + // returned to issuing read leveling calibration reads + else if (prech_done_pre) + prech_pending_r <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || prech_done_r3) + mask_lim_done <= #TCQ 1'b0; + else if (prech_pending_r) + mask_lim_done <= #TCQ 1'b1; + end + + always @(posedge clk) begin + if (rst || prbs_rdlvl_done_r3) + complex_mask_lim_done <= #TCQ 1'b0; + else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) + complex_mask_lim_done <= #TCQ 1'b1; + end + + //Complex oclkdelay calibrration + + //*************************************************************************** + // Various timing counters + //*************************************************************************** + + //***************************************************************** + // Generic delay for various states that require it (e.g. for turnaround + // between read and write). Make this a sufficiently large number of clock + // cycles to cover all possible frequencies and memory components) + // Requirements for this counter: + // 1. Greater than tMRD + // 2. tRFC (refresh-active) for DDR2 + // 3. (list the other requirements, slacker...) + //***************************************************************** + + always @(posedge clk) begin + case (init_state_r) + INIT_LOAD_MR_WAIT, + INIT_WRLVL_LOAD_MR_WAIT, + INIT_WRLVL_LOAD_MR2_WAIT, + INIT_MPR_WAIT, + INIT_MPR_DISABLE_PREWAIT, + INIT_MPR_DISABLE_WAIT, + INIT_OCLKDELAY_ACT_WAIT, + INIT_OCLKDELAY_WRITE_WAIT, + INIT_RDLVL_ACT_WAIT, + INIT_RDLVL_STG1_WRITE_READ, + INIT_RDLVL_STG2_READ_WAIT, + INIT_WRCAL_ACT_WAIT, + INIT_WRCAL_WRITE_READ, + INIT_WRCAL_READ_WAIT, + INIT_PRECHARGE_PREWAIT, + INIT_PRECHARGE_WAIT, + INIT_DDR2_PRECHARGE_WAIT, + INIT_REG_WRITE_WAIT, + INIT_REFRESH_WAIT, + INIT_REFRESH_RNK2_WAIT: begin + if (phy_ctl_full || phy_cmd_full) + cnt_cmd_r <= #TCQ cnt_cmd_r; + else + cnt_cmd_r <= #TCQ cnt_cmd_r + 1; + end + INIT_WRLVL_WAIT: + cnt_cmd_r <= #TCQ 'b0; + default: + cnt_cmd_r <= #TCQ 'b0; + endcase + end + + // pulse when count reaches terminal count + always @(posedge clk) + cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); + + // For ODT deassertion - hold throughout post read/write wait stage, but + // deassert before next command. The post read/write stage is very long, so + // we simply address the longest case here plus some margin. + always @(posedge clk) + cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); + +//************************************************************************ +// Added to support PO fine delay inc when TG errors + always @(posedge clk) begin + case (init_state_r) + INIT_WRCAL_READ_WAIT: begin + if (phy_ctl_full || phy_cmd_full) + cnt_wait <= #TCQ cnt_wait; + else + cnt_wait <= #TCQ cnt_wait + 1; + end + default: + cnt_wait <= #TCQ 'b0; + endcase + end + + always @(posedge clk) + cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); + + always @(posedge clk) begin + if (rst || ~temp_wrcal_done) + temp_lmr_done <= #TCQ 1'b0; + else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) + temp_lmr_done <= #TCQ 1'b1; + end + + always @(posedge clk) + temp_wrcal_done_r <= #TCQ temp_wrcal_done; + + always @(posedge clk) + if (rst) begin + tg_timer_go <= #TCQ 1'b0; + end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && + (init_state_r == INIT_WRCAL_READ_WAIT)) begin + tg_timer_go <= #TCQ 1'b1; + end else begin + tg_timer_go <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || + (init_state_r == INIT_PRECHARGE_PREWAIT)) + tg_timer <= #TCQ 'd0; + else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && + tg_timer_go && + (tg_timer != TG_TIMER_TIMEOUT)) + tg_timer <= #TCQ tg_timer + 1; + end + + always @(posedge clk) begin + if (rst) + tg_timer_done <= #TCQ 1'b0; + else if (tg_timer == TG_TIMER_TIMEOUT) + tg_timer_done <= #TCQ 1'b1; + else + tg_timer_done <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst) + no_rst_tg_mc <= #TCQ 1'b0; + else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) + no_rst_tg_mc <= #TCQ 1'b1; + else + no_rst_tg_mc <= #TCQ 1'b0; + end + +//************************************************************************ + + always @(posedge clk) begin + if (rst) + detect_pi_found_dqs <= #TCQ 1'b0; + else if ((cnt_cmd_r == 7'b0111111) && + (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) + detect_pi_found_dqs <= #TCQ 1'b1; + else + detect_pi_found_dqs <= #TCQ 1'b0; + end + + //***************************************************************** + // Initial delay after power-on for RESET, CKE + // NOTE: Could reduce power consumption by turning off these counters + // after initial power-up (at expense of more logic) + // NOTE: Likely can combine multiple counters into single counter + //***************************************************************** + + // Create divided by 1024 version of clock + always @(posedge clk) + if (rst) begin + cnt_pwron_ce_r <= #TCQ 10'h000; + pwron_ce_r <= #TCQ 1'b0; + end else begin + cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; + pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); + end + + // "Main" power-on counter - ticks every CLKDIV/1024 cycles + always @(posedge clk) + if (rst) + cnt_pwron_r <= #TCQ 'b0; + else if (pwron_ce_r) + cnt_pwron_r <= #TCQ cnt_pwron_r + 1; + + always @(posedge clk) + if (rst || ~phy_ctl_ready) begin + cnt_pwron_reset_done_r <= #TCQ 1'b0; + cnt_pwron_cke_done_r <= #TCQ 1'b0; + end else begin + // skip power-up count for simulation purposes only + if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || + (SIM_INIT_OPTION == "SKIP_INIT")) begin + cnt_pwron_reset_done_r <= #TCQ 1'b1; + cnt_pwron_cke_done_r <= #TCQ 1'b1; + end else begin + // otherwise, create latched version of done signal for RESET, CKE + if (DRAM_TYPE == "DDR3") begin + if (!cnt_pwron_reset_done_r) + cnt_pwron_reset_done_r + <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); + if (!cnt_pwron_cke_done_r) + cnt_pwron_cke_done_r + <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); + end else begin // DDR2 + cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed + if (!cnt_pwron_cke_done_r) + cnt_pwron_cke_done_r + <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); + end + end + end // else: !if(rst || ~phy_ctl_ready) + + + always @(posedge clk) + cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; + + // Keep RESET asserted and CKE deasserted until after power-on delay + always @(posedge clk or posedge rst) begin + if (rst) + phy_reset_n <= #TCQ 1'b0; + else + phy_reset_n <= #TCQ cnt_pwron_reset_done_r; +// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; + end + + //***************************************************************** + // Counter for tXPR (pronouned "Tax-Payer") - wait time after + // CKE deassertion before first MRS command can be asserted + //***************************************************************** + + always @(posedge clk) + if (!cnt_pwron_cke_done_r) begin + cnt_txpr_r <= #TCQ 'b0; + cnt_txpr_done_r <= #TCQ 1'b0; + end else begin + cnt_txpr_r <= #TCQ cnt_txpr_r + 1; + if (!cnt_txpr_done_r) + cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); + end + + //***************************************************************** + // Counter for the initial 400ns wait for issuing precharge all + // command after CKE assertion. Only for DDR2. + //***************************************************************** + + always @(posedge clk) + if (!cnt_pwron_cke_done_r) begin + cnt_init_pre_wait_r <= #TCQ 'b0; + cnt_init_pre_wait_done_r <= #TCQ 1'b0; + end else begin + cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; + if (!cnt_init_pre_wait_done_r) + cnt_init_pre_wait_done_r + <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); + end + + //***************************************************************** + // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish + // (tZQINIT). Both take the same amount of time (512*tCK) + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_ZQCL) begin + cnt_dllk_zqinit_r <= #TCQ 'b0; + cnt_dllk_zqinit_done_r <= #TCQ 1'b0; + end else if (~(phy_ctl_full || phy_cmd_full)) begin + cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; + if (!cnt_dllk_zqinit_done_r) + cnt_dllk_zqinit_done_r + <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); + end + + //***************************************************************** + // Keep track of which MRS counter needs to be programmed during + // memory initialization + // The counter and the done signal are reset an additional time + // for DDR2. The same signals are used for the additional DDR2 + // initialization sequence. + //***************************************************************** + + always @(posedge clk) + if ((init_state_r == INIT_IDLE)|| + ((init_state_r == INIT_REFRESH) + && (~mem_init_done_r))) begin + cnt_init_mr_r <= #TCQ 'b0; + cnt_init_mr_done_r <= #TCQ 1'b0; + end else if (init_state_r == INIT_LOAD_MR) begin + cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; + cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); + end + + + //***************************************************************** + // Flag to tell if the first precharge for DDR2 init sequence is + // done + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) + ddr2_pre_flag_r<= #TCQ 'b0; + else if (init_state_r == INIT_LOAD_MR) + ddr2_pre_flag_r<= #TCQ 1'b1; + // reset the flag for multi rank case + else if ((ddr2_refresh_flag_r) && + (init_state_r == INIT_LOAD_MR_WAIT)&& + (cnt_cmd_done_r) && (cnt_init_mr_done_r)) + ddr2_pre_flag_r <= #TCQ 'b0; + + //***************************************************************** + // Flag to tell if the refresh stat for DDR2 init sequence is + // reached + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) + ddr2_refresh_flag_r<= #TCQ 'b0; + else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) + // reset the flag for multi rank case + ddr2_refresh_flag_r<= #TCQ 1'b1; + else if ((ddr2_refresh_flag_r) && + (init_state_r == INIT_LOAD_MR_WAIT)&& + (cnt_cmd_done_r) && (cnt_init_mr_done_r)) + ddr2_refresh_flag_r <= #TCQ 'b0; + + //***************************************************************** + // Keep track of the number of auto refreshes for DDR2 + // initialization. The spec asks for a minimum of two refreshes. + // Four refreshes are performed here. The two extra refreshes is to + // account for the 200 clock cycle wait between step h and l. + // Without the two extra refreshes we would have to have a + // wait state. + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) begin + cnt_init_af_r <= #TCQ 'b0; + cnt_init_af_done_r <= #TCQ 1'b0; + end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin + cnt_init_af_r <= #TCQ cnt_init_af_r + 1; + cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); + end + + //***************************************************************** + // Keep track of the register control word programming for + // DDR3 RDIMM + //***************************************************************** + + always @(posedge clk) + if (init_state_r == INIT_IDLE) + reg_ctrl_cnt_r <= #TCQ 'b0; + else if (init_state_r == INIT_REG_WRITE) + reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; + + generate + if (RANKS < 2) begin: one_rank + always @(posedge clk) + if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || + (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) + stg1_wr_done <= #TCQ 1'b0; + else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) + stg1_wr_done <= #TCQ 1'b1; + end else begin: two_ranks + always @(posedge clk) + if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || + (complex_byte_rd_done) || prbs_rdlvl_done_pulse || + (rdlvl_stg1_rank_done )) + stg1_wr_done <= #TCQ 1'b0; + else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) + stg1_wr_done <= #TCQ 1'b1; + end + endgenerate + + always @(posedge clk) + if (rst) + rnk_ref_cnt <= #TCQ 1'b0; + else if (stg1_wr_done && + (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) + rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; + + + always @(posedge clk) + if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) + num_refresh <= #TCQ 'd0; + else if ((init_state_r == INIT_REFRESH) && + (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || + (rdlvl_stg1_done && ~prbs_rdlvl_done) || + (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || + ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || + ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) + num_refresh <= #TCQ num_refresh + 1; + + + //*************************************************************************** + // Initialization state machine + //*************************************************************************** + + //***************************************************************** + // Next-state logic + //***************************************************************** + + always @(posedge clk) + if (rst)begin + init_state_r <= #TCQ INIT_IDLE; + init_state_r1 <= #TCQ INIT_IDLE; + end else begin + init_state_r <= #TCQ init_next_state; + init_state_r1 <= #TCQ init_state_r; + end + + always @(*) begin + init_next_state = init_state_r; + (* full_case, parallel_case *) case (init_state_r) + + //******************************************************* + // DRAM initialization + //******************************************************* + + // Initial state - wait for: + // 1. Power-on delays to pass + // 2. PHY Control Block to assert phy_ctl_ready + // 3. PHY Control FIFO must not be FULL + // 4. Read path initialization to finish + INIT_IDLE: + if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done + && ~(phy_ctl_full || phy_cmd_full) ) begin + // If skipping memory initialization (simulation only) + if (SIM_INIT_OPTION == "SKIP_INIT") + //if (WRLVL == "ON") + // Proceed to write leveling + // init_next_state = INIT_WRLVL_START; + //else //if (SIM_CAL_OPTION != "SKIP_CAL") + // Proceed to Phaser_In phase lock + init_next_state = INIT_RDLVL_ACT; + // else + // Skip read leveling + //init_next_state = INIT_DONE; + else + init_next_state = INIT_WAIT_CKE_EXIT; + end + + // Wait minimum of Reset CKE exit time (tXPR = max(tXS, + INIT_WAIT_CKE_EXIT: + if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") + && ~(phy_ctl_full || phy_cmd_full)) begin + if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || + (RANKS > 1))) + //register write for reg dimm. Some register chips + // have the register chip in a pre-programmed state + // in that case the nCS_PER_RANK == 1 && RANKS == 1 + init_next_state = INIT_REG_WRITE; + else + // Load mode register - this state is repeated multiple times + init_next_state = INIT_LOAD_MR; + end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") + && ~(phy_ctl_full || phy_cmd_full)) + // DDR2 start with a precharge all command + init_next_state = INIT_DDR2_PRECHARGE; + + INIT_REG_WRITE: + init_next_state = INIT_REG_WRITE_WAIT; + + INIT_REG_WRITE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if(reg_ctrl_cnt_r == 4'd8) + init_next_state = INIT_LOAD_MR; + else + init_next_state = INIT_REG_WRITE; + end + + INIT_LOAD_MR: + init_next_state = INIT_LOAD_MR_WAIT; + // After loading MR, wait at least tMRD + + INIT_LOAD_MR_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + // If finished loading all mode registers, proceed to next step + if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) + // for ddr3 when the correct burst length is writtern at end + init_next_state = INIT_PRECHARGE; + else if (~wrcal_done && temp_lmr_done) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (cnt_init_mr_done_r)begin + if(DRAM_TYPE == "DDR3") + init_next_state = INIT_ZQCL; + else begin //DDR2 + if(ddr2_refresh_flag_r)begin + // memory initialization per rank for multi-rank case + if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) + init_next_state = INIT_DDR2_MULTI_RANK; + else + init_next_state = INIT_RDLVL_ACT; + // ddr2 initialization done.load mode state after refresh + end else + init_next_state = INIT_DDR2_PRECHARGE; + end + end else + init_next_state = INIT_LOAD_MR; + end + + // DDR2 multi rank transition state + INIT_DDR2_MULTI_RANK: + init_next_state = INIT_DDR2_MULTI_RANK_WAIT; + + INIT_DDR2_MULTI_RANK_WAIT: + init_next_state = INIT_DDR2_PRECHARGE; + + // Initial ZQ calibration + INIT_ZQCL: + init_next_state = INIT_WAIT_DLLK_ZQINIT; + + // Wait until both DLL have locked, and ZQ calibration done + INIT_WAIT_DLLK_ZQINIT: + if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) + // memory initialization per rank for multi-rank case + if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) + init_next_state = INIT_LOAD_MR; + //else if (WRLVL == "ON") + // init_next_state = INIT_WRLVL_START; + else + // skip write-leveling (e.g. for DDR2 interface) + init_next_state = INIT_RDLVL_ACT; + + // Initial precharge for DDR2 + INIT_DDR2_PRECHARGE: + init_next_state = INIT_DDR2_PRECHARGE_WAIT; + + INIT_DDR2_PRECHARGE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if (ddr2_pre_flag_r) + init_next_state = INIT_REFRESH; + else // from precharge state initially go to load mode + init_next_state = INIT_LOAD_MR; + end + + INIT_REFRESH: + if ((SKIP_CALIB == "TRUE") && ~calib_tap_inc_done && pi_dqs_found_done) + init_next_state = INIT_SKIP_CALIB_WAIT; + else if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) + init_next_state = INIT_REFRESH_RNK2_WAIT; + else + init_next_state = INIT_REFRESH_WAIT; + + INIT_REFRESH_RNK2_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_PRECHARGE; + + INIT_REFRESH_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin + if(cnt_init_af_done_r && (~mem_init_done_r)) + // go to lm state as part of DDR2 init sequence + init_next_state = INIT_LOAD_MR; + // Go to state to issue back-to-back writes during limit check and centering + else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin + if (num_refresh == 'd8) + init_next_state = INIT_OCAL_CENTER_ACT; + else + init_next_state = INIT_REFRESH; + end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && + complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) + init_next_state = INIT_WRLVL_START; + else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) + init_next_state = INIT_WRLVL_START; + else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done + && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 + && mem_init_done_r) begin + if (num_refresh == 'd8) begin + if (BYPASS_COMPLEX_OCAL == "FALSE") + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else + init_next_state = INIT_WRCAL_ACT; + end else + init_next_state = INIT_REFRESH; + end else if (~pi_dqs_found_done || + (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || + ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || + ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin + if (num_refresh == 'd8) + init_next_state = INIT_RDLVL_ACT; + else + init_next_state = INIT_REFRESH; + end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") + && (CLK_PERIOD/nCK_PER_CLK > 2500)) + init_next_state = INIT_WRLVL_LOAD_MR2; + else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) + && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) + init_next_state = INIT_WRCAL_ACT; + else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin + if (num_refresh == 'd8) + init_next_state = INIT_MPR_RDEN; + else + init_next_state = INIT_REFRESH; + end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 + (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) + init_next_state = INIT_WRLVL_LOAD_MR2; + else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) + && pi_dqs_found_done) + init_next_state = INIT_WRCAL_ACT; + else if (mem_init_done_r) begin + if (RANKS < 2) + init_next_state = INIT_RDLVL_ACT; + else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) + init_next_state = INIT_PRECHARGE; + else + init_next_state = INIT_RDLVL_ACT; + end else // to DDR2 init state as part of DDR2 init sequence + init_next_state = INIT_REFRESH; + end + + INIT_SKIP_CALIB_WAIT: + if (calib_tap_inc_done) + init_next_state = INIT_WRCAL_ACT; + + + //****************************************************** + // Write Leveling + //******************************************************* + + // Enable write leveling in MR1 and start write leveling + // for current rank + INIT_WRLVL_START: + init_next_state = INIT_WRLVL_WAIT; + + // Wait for both MR load and write leveling to complete + // (write leveling should take much longer than MR load..) + INIT_WRLVL_WAIT: + if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_WRLVL_LOAD_MR; + + // Disable write leveling in MR1 for current rank + INIT_WRLVL_LOAD_MR: + init_next_state = INIT_WRLVL_LOAD_MR_WAIT; + + INIT_WRLVL_LOAD_MR_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_WRLVL_LOAD_MR2; + + // Load MR2 to set ODT: Dynamic ODT for single rank case + // And ODTs for multi-rank case as well + INIT_WRLVL_LOAD_MR2: + init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; + + // Wait tMRD before proceeding + INIT_WRLVL_LOAD_MR2_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + //if (wrlvl_byte_done) + // init_next_state = INIT_PRECHARGE_PREWAIT; + // else if ((RANKS == 2) && wrlvl_rank_done_r2) + // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; + if (~wrlvl_done_r1) + init_next_state = INIT_WRLVL_START; + else if (SIM_CAL_OPTION == "SKIP_CAL") + // If skip rdlvl, then we're done + init_next_state = INIT_DONE; + else + // Otherwise, proceed to read leveling + //init_next_state = INIT_RDLVL_ACT; + init_next_state = INIT_PRECHARGE_PREWAIT; + end + + //******************************************************* + // Read Leveling + //******************************************************* + + // single row activate. All subsequent read leveling writes and + // read will take place in this row + INIT_RDLVL_ACT: + init_next_state = INIT_RDLVL_ACT_WAIT; + + // hang out for awhile before issuing subsequent column commands + // it's also possible to reach this state at various points + // during read leveling - determine what the current stage is + INIT_RDLVL_ACT_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + // Just finished an activate. Now either write, read, or precharge + // depending on where we are in the training sequence + if (!pi_calib_done_r1) + init_next_state = INIT_PI_PHASELOCK_READS; + else if (!pi_dqs_found_done) + // (!pi_dqs_found_start || pi_dqs_found_rank_done)) + init_next_state = INIT_RDLVL_STG2_READ; + else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) + init_next_state = INIT_WRCAL_ACT_WAIT; + else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || + (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin + // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl + if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) + init_next_state = INIT_RDLVL_ACT_WAIT; + else + init_next_state = INIT_RDLVL_STG1_WRITE; + end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin + if (rdlvl_last_byte_done || prbs_last_byte_done) + // Added to avoid extra reads at the end of read leveling + init_next_state = INIT_RDLVL_ACT_WAIT; + else begin + // Case 2: If in stage 1, and just precharged after training + // previous byte, then continue reading + if (rdlvl_stg1_done) + init_next_state = INIT_RDLVL_STG1_WRITE_READ; + else + init_next_state = INIT_RDLVL_STG1_READ; + end + end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && + (CLK_PERIOD/nCK_PER_CLK > 2500)) + init_next_state = INIT_WRCAL_ACT_WAIT; + else + // Otherwise, if we're finished with calibration, then precharge + // the row - silly, because we just opened it - possible to take + // this out by adding logic to avoid the ACT in first place. Make + // sure that cnt_cmd_done will handle tRAS(min) + init_next_state = INIT_PRECHARGE_PREWAIT; + end + + //************************************************** + // Back-to-back reads for Phaser_IN Phase locking + // DQS to FREQ_REF clock + //************************************************** + + INIT_PI_PHASELOCK_READS: + if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) + init_next_state = INIT_PRECHARGE_PREWAIT; + + //********************************************* + // Stage 1 read-leveling (write and continuous read) + //********************************************* + + // Write training pattern for stage 1 + // PRBS pattern of TBD length + INIT_RDLVL_STG1_WRITE: + // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle + // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words + // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words + // An entire row worth of writes issued before proceeding to reads + // The number of write is (2^column width)/burst length to accomodate + // PRBS pattern for window detection. + //VCCO/VCCAUX write is not done + if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) + init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; + //back to back write from row1 + else if (stg1_wr_rd_cnt == 9'd1) begin + if (rdlvl_stg1_done_r1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else + init_next_state = INIT_RDLVL_STG1_WRITE_READ; + end + + INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: + if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) + //At the end of the byte, it goes to REFRESH + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; + + INIT_RDLVL_COMPLEX_PRECHARGE: + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; + + INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: + if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) begin + if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 + // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode + if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) + init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 + else if (lim_done && complex_oclkdelay_calib_start_r2) + init_next_state = INIT_RDLVL_COMPLEX_ACT; + else + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; + end else + init_next_state = INIT_RDLVL_COMPLEX_ACT; + end + + + INIT_RDLVL_COMPLEX_ACT: + //only for sampling boundary it need to wait + //when initial pi dec is not done in complex per-bit, it need to wait + if(prbs_rdlvl_start && (num_samples_done_r || ~complex_init_pi_dec_done)) + init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT; + else init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; + + //wait PI movement is done before proceeding read + INIT_RDLVL_COMPLEX_PI_WAIT: + if(complex_pi_incdec_done) + init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; + + INIT_RDLVL_COMPLEX_ACT_WAIT: + if (complex_rdlvl_int_ref_req || prech_req_posedge_r) //prech req always happen in this state + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) begin + if (oclkdelay_center_calib_start) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + else if (stg1_wr_done) + init_next_state = INIT_RDLVL_COMPLEX_READ; + else if (~complex_row1_wr_done) + if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write + init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; + else + init_next_state = INIT_RDLVL_STG1_WRITE; + else + init_next_state = INIT_RDLVL_STG1_WRITE_READ; + end + + // Write-read turnaround + INIT_RDLVL_STG1_WRITE_READ: + if (reset_rd_addr_r1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin + if (rdlvl_stg1_done_r1) + //before going to read, wait for PI inc/dec done + init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT; + else + init_next_state = INIT_RDLVL_STG1_READ; + end + + // Continuous read, where interruptible by precharge request from + // calibration logic. Also precharges when stage 1 is complete + // No precharges when reads provided to Phaser_IN for phase locking + // FREQ_REF to read DQS since data integrity is not important. + INIT_RDLVL_STG1_READ: + if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || + prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + + INIT_RDLVL_COMPLEX_READ: + if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) + else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) + init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; + //For back-to-back reads from row1 (ISI pattern) + else if (stg1_wr_rd_cnt == 'd1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + + INIT_RDLVL_COMPLEX_READ_WAIT: + if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (stg1_wr_rd_cnt == 'd1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) + init_next_state = INIT_RDLVL_COMPLEX_READ; + + + //********************************************* + // DQSFOUND calibration (set of 4 reads with gaps) + //********************************************* + + // Read of training data. Note that Stage 2 is not a constant read, + // instead there is a large gap between each set of back-to-back reads + INIT_RDLVL_STG2_READ: + // 4 read commands issued back-to-back + if (num_reads == 'b1) + init_next_state = INIT_RDLVL_STG2_READ_WAIT; + + // Wait before issuing the next set of reads. If a precharge request + // comes in then handle - this can occur after stage 2 calibration is + // completed for a DQS group + INIT_RDLVL_STG2_READ_WAIT: + if (~(phy_ctl_full || phy_cmd_full)) begin + if (pi_dqs_found_rank_done || + pi_dqs_found_done || prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (cnt_cmd_done_r) + init_next_state = INIT_RDLVL_STG2_READ; + end + + + //****************************************************************** + // MPR Read Leveling for DDR3 OCLK_DELAYED calibration + //****************************************************************** + + // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 + // to enable Multi Purpose Register (MPR) Read + INIT_MPR_RDEN: + init_next_state = INIT_MPR_WAIT; + + //Wait tMRD, tMOD + INIT_MPR_WAIT: + if (cnt_cmd_done_r) begin + init_next_state = INIT_MPR_READ; + end + + // Issue back-to-back read commands to read from MPR with + // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined + // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) + INIT_MPR_READ: + if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) + init_next_state = INIT_MPR_DISABLE_PREWAIT; + + INIT_MPR_DISABLE_PREWAIT: + if (cnt_cmd_done_r) + init_next_state = INIT_MPR_DISABLE; + + // Issue Load Mode Register 3 command with A[2]=0 to disable + // MPR read + INIT_MPR_DISABLE: + init_next_state = INIT_MPR_DISABLE_WAIT; + + INIT_MPR_DISABLE_WAIT: + init_next_state = INIT_PRECHARGE_PREWAIT; + + + //*********************************************************************** + // OCLKDELAY Calibration + //*********************************************************************** + + // This calibration requires single write followed by single read to + // determine the Phaser_Out stage 3 delay required to center write DQS + // in write DQ valid window. + + // Single Row Activate command before issuing Write command + INIT_OCLKDELAY_ACT: + init_next_state = INIT_OCLKDELAY_ACT_WAIT; + + INIT_OCLKDELAY_ACT_WAIT: + if (cnt_cmd_done_r && ~oclk_prech_req) + init_next_state = INIT_OCLKDELAY_WRITE; + else if (oclkdelay_calib_done || prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + + INIT_OCLKDELAY_WRITE: + if (oclk_wr_cnt == 4'd1) + init_next_state = INIT_OCLKDELAY_WRITE_WAIT; + + INIT_OCLKDELAY_WRITE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if (oclkdelay_int_ref_req) + init_next_state = INIT_PRECHARGE_PREWAIT; + else + init_next_state = INIT_OCLKDELAY_READ; + end + + INIT_OCLKDELAY_READ: + init_next_state = INIT_OCLKDELAY_READ_WAIT; + + INIT_OCLKDELAY_READ_WAIT: + if (~(phy_ctl_full || phy_cmd_full)) begin + if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) + init_next_state = INIT_OCLKDELAY_WRITE; + else if (oclkdelay_calib_done || prech_req_posedge_r || + wrlvl_final || oclkdelay_int_ref_req) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (oclkdelay_center_calib_start) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + end + + + //********************************************* + // Write calibration + //********************************************* + + // single row activate + INIT_WRCAL_ACT: + init_next_state = INIT_WRCAL_ACT_WAIT; + + // hang out for awhile before issuing subsequent column command + INIT_WRCAL_ACT_WAIT: + if (cnt_cmd_done_r && ~wrcal_prech_req) + init_next_state = INIT_WRCAL_WRITE; + else if (wrcal_done || prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + + // Write training pattern for write calibration + INIT_WRCAL_WRITE: + // Once we've issued enough commands for 8 words - proceed to reads + //if (burst_addr_r == 1'b1) + if (wrcal_wr_cnt == 4'd1) + init_next_state = INIT_WRCAL_WRITE_READ; + + // Write-read turnaround + INIT_WRCAL_WRITE_READ: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_WRCAL_READ; + else if (dqsfound_retry) + init_next_state = INIT_RDLVL_STG2_READ_WAIT; + + + INIT_WRCAL_READ: + if (burst_addr_r == 1'b1) + init_next_state = INIT_WRCAL_READ_WAIT; + + INIT_WRCAL_READ_WAIT: + if (~(phy_ctl_full || phy_cmd_full)) begin + if (wrcal_resume_r) begin + if (wrcal_final_chk) + init_next_state = INIT_WRCAL_READ; + else + init_next_state = INIT_WRCAL_WRITE; + end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || + // Added to support PO fine delay inc when TG errors + wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (dqsfound_retry) + init_next_state = INIT_RDLVL_STG2_READ_WAIT; + else if (wrcal_read_req && cnt_wrcal_rd) + init_next_state = INIT_WRCAL_MULT_READS; + end + + INIT_WRCAL_MULT_READS: + // multiple read commands issued back-to-back + if (wrcal_reads == 'b1) + init_next_state = INIT_WRCAL_READ_WAIT; + + //********************************************* + // Handling of precharge during and in between read-level stages + //********************************************* + + // Make sure we aren't violating any timing specs by precharging + // immediately + INIT_PRECHARGE_PREWAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) + init_next_state = INIT_PRECHARGE; + + // Initiate precharge + INIT_PRECHARGE: + init_next_state = INIT_PRECHARGE_WAIT; + + INIT_PRECHARGE_WAIT: + if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin + if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || + (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && + (DRAM_TYPE == "DDR2"))) + init_next_state = INIT_DONE; + else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && + pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) + init_next_state = INIT_WRCAL_ACT; + else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) + && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) + && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin + // after all calibration program the correct burst length + init_next_state = INIT_LOAD_MR; + // Added to support PO fine delay inc when TG errors + end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) + init_next_state = INIT_WRCAL_READ_WAIT; + else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) + // If read leveling finished, proceed to write calibration + init_next_state = INIT_REFRESH; + else + // Otherwise, open row for read-leveling purposes + init_next_state = INIT_REFRESH; + end + + //******************************************************* + // COMPLEX OCLK calibration - for fragmented write + //******************************************************* + INIT_OCAL_COMPLEX_ACT: + init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; + + INIT_OCAL_COMPLEX_ACT_WAIT: + if (complex_wait_cnt =='d15) + init_next_state = INIT_RDLVL_STG1_WRITE; + + INIT_OCAL_COMPLEX_WRITE_WAIT: + if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (stg1_wr_rd_cnt == 'd1) + init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; + else if (complex_wait_cnt == 'd15) + init_next_state = INIT_RDLVL_STG1_WRITE; + + //wait for all srg2/stg3 tap movement is done and go back to write again + INIT_OCAL_COMPLEX_RESUME_WAIT: + if (complex_oclk_calib_resume) + init_next_state = INIT_RDLVL_STG1_WRITE; + else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) + init_next_state = INIT_PRECHARGE_PREWAIT; + + //******************************************************* + // OCAL STG3 Centering calibration + //******************************************************* + INIT_OCAL_CENTER_ACT: + init_next_state = INIT_OCAL_CENTER_ACT_WAIT; + + INIT_OCAL_CENTER_ACT_WAIT: + if (ocal_act_wait_cnt == 'd15) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + + INIT_OCAL_CENTER_WRITE: + if(!oclk_center_write_resume && !lim_wr_req) + init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; + + INIT_OCAL_CENTER_WRITE_WAIT: + //if (oclkdelay_center_calib_done || prech_req_posedge_r) + if (prech_req_posedge_r) + init_next_state = INIT_PRECHARGE_PREWAIT; + else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) + init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; + else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) + init_next_state = INIT_OCLKDELAY_READ_WAIT; + else if (oclk_center_write_resume || lim_wr_req) + init_next_state = INIT_OCAL_CENTER_WRITE; + + //******************************************************* + // Initialization/Calibration done. Take a long rest, relax + //******************************************************* + + INIT_DONE: + init_next_state = INIT_DONE; + + endcase + end + + //***************************************************************** + // Initialization done signal - asserted before leveling starts + //***************************************************************** + + + always @(posedge clk) + if (rst) + mem_init_done_r <= #TCQ 1'b0; + else if ((!cnt_dllk_zqinit_done_r && + (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && + (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) + || ( (init_state_r == INIT_LOAD_MR_WAIT) && + (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) + && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) + mem_init_done_r <= #TCQ 1'b1; + + //***************************************************************** + // Write Calibration signal to PHY Control Block - asserted before + // Write Leveling starts + //***************************************************************** + + //generate + //if (RANKS < 2) begin: ranks_one + always @(posedge clk) begin + if (rst || (done_dqs_tap_inc && + (init_state_r == INIT_WRLVL_LOAD_MR2))) + write_calib <= #TCQ 1'b0; + else if (wrlvl_active_r1) + write_calib <= #TCQ 1'b1; + end + //end else begin: ranks_two + // always @(posedge clk) begin + // if (rst || + // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && + // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || + // (SIM_CAL_OPTION == "FAST_CAL")))) + // write_calib <= #TCQ 1'b0; + // else if (wrlvl_active_r1) + // write_calib <= #TCQ 1'b1; + // end + //end + //endgenerate + + //***************************************************************** + // Read Calibration signal to PHY Control Block - asserted after + // Write Leveling during PHASER_IN phase locking stage. + // Must be de-asserted before Read Leveling + //***************************************************************** + + always @(posedge clk) begin + if (rst || pi_calib_done_r1) + read_calib_int <= #TCQ 1'b0; + else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && + (cnt_cmd_r == CNTNEXT_CMD)) + read_calib_int <= #TCQ 1'b1; + end + + always @(posedge clk) + read_calib_r <= #TCQ read_calib_int; + + + always @(posedge clk) begin + if (rst || pi_calib_done_r1) + read_calib <= #TCQ 1'b0; + else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) + read_calib <= #TCQ 1'b1; + end + + + always @(posedge clk) + if (rst) + pi_calib_done_r <= #TCQ 1'b0; + else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) + pi_calib_done_r <= #TCQ 1'b1; + + always @(posedge clk) + if (rst) + pi_calib_rank_done_r <= #TCQ 1'b0; + else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) + pi_calib_rank_done_r <= #TCQ 1'b1; + else + pi_calib_rank_done_r <= #TCQ 1'b0; + + always @(posedge clk) begin + if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) + pi_phaselock_timer <= #TCQ 'd0; + else if (((init_state_r == INIT_PI_PHASELOCK_READS) && + (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || + tg_timer_go) + pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; + else + pi_phaselock_timer <= #TCQ pi_phaselock_timer; + end + + assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; + + //***************************************************************** + // DDR3 final burst length programming done. For DDR3 during + // calibration the burst length is fixed to BL8. After calibration + // the correct burst length is programmed. + //***************************************************************** + always @(posedge clk) + if (rst) + ddr3_lm_done_r <= #TCQ 1'b0; + else if ((init_state_r == INIT_LOAD_MR_WAIT) && + (chip_cnt_r == RANKS-1) && wrcal_done) + ddr3_lm_done_r <= #TCQ 1'b1; + + always @(posedge clk) begin + pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; + pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; + pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; + pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; + pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; + pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; + pi_calib_done_r1 <= #TCQ pi_calib_done_r; + end + + //*************************************************************************** + // Logic for deep memory (multi-rank) configurations + //*************************************************************************** + + // For DDR3 asserted when + +generate + if (RANKS < 2) begin: single_rank + always @(posedge clk) + chip_cnt_r <= #TCQ 2'b00; + end else begin: dual_rank + always @(posedge clk) + if (rst || + // Set chip_cnt_r to 2'b00 after both Ranks are read leveled + (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done && (SKIP_CALIB == "FALSE")) || + // Set chip_cnt_r to 2'b00 after both Ranks are write leveled + (wrlvl_done_r && + (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin + chip_cnt_r <= #TCQ 2'b00; + end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && + (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && + (DRAM_TYPE == "DDR3")) || + ((init_state_r==INIT_REFRESH_RNK2_WAIT) && + (cnt_cmd_r=='d36)) || + //mpr_rnk_done || + //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || + //(stg1_wr_done && (init_state_r == INIT_REFRESH) && + //~(rnk_ref_cnt && rdlvl_last_byte_done)) || + + // Increment chip_cnt_r to issue Refresh to second rank + (~pi_dqs_found_all_r && + (init_state_r==INIT_PRECHARGE_PREWAIT) && + (cnt_cmd_r=='d36) && (SKIP_CALIB == "FALSE")) || + + // Increment chip_cnt_r when DQSFOUND done for the Rank + (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r && (SKIP_CALIB == "FALSE")) || + ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r + && wrcal_done) || + ((init_state_r == INIT_DDR2_MULTI_RANK) + && (DRAM_TYPE == "DDR2"))) begin + if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || + // condition to increment chip_cnt during + // final burst length programming for DDR3 + ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || + && (chip_cnt_r != RANKS-1)) + chip_cnt_r <= #TCQ chip_cnt_r + 1; + else + chip_cnt_r <= #TCQ 2'b00; + end + end + endgenerate +// verilint STARC-2.2.3.3 off +generate + if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if (init_state_r == INIT_REG_WRITE) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if(!(CWL_M%2)) begin + phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; + end else begin + phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; + end + end else if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) //even CWL + phy_int_cs_n[0] <= #TCQ 1'b0; + else // odd CWL + phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end + end else if (RANKS == 1) begin: DDR3_1rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) begin //even CWL + for (n = 0; n < nCS_PER_RANK; n = n + 1) begin + phy_int_cs_n[n] <= #TCQ 1'b0; + end + end else begin //odd CWL + for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin + phy_int_cs_n[p] <= #TCQ 1'b0; + end + end + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end + end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if (init_state_r == INIT_REG_WRITE) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if(!(CWL_M%2)) begin + phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; + end else begin + phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; + end + end else begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + case (chip_cnt_r) + 2'b00:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) //even CWL + phy_int_cs_n[0] <= #TCQ 1'b0; + else // odd CWL + phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + 2'b01:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) //even CWL + phy_int_cs_n[1] <= #TCQ 1'b0; + else // odd CWL + phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + endcase + end + end + end else if (RANKS == 2) begin: DDR3_2rank + always @(posedge clk) begin + if (rst) + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + else if (init_state_r == INIT_REG_WRITE) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if(!(CWL_M%2)) begin + phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; + end else begin + phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; + phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; + end + end else begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + case (chip_cnt_r) + 2'b00:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) begin //even CWL + for (n = 0; n < nCS_PER_RANK; n = n + 1) begin + phy_int_cs_n[n] <= #TCQ 1'b0; + end + end else begin // odd CWL + for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin + phy_int_cs_n[p] <= #TCQ 1'b0; + end + end + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + 2'b01:begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + if (!(CWL_M % 2)) begin //even CWL + for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin + phy_int_cs_n[q] <= #TCQ 1'b0; + end + end else begin // odd CWL + for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin + phy_int_cs_n[m] <= #TCQ 1'b0; + end + end + end else + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin + // + // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; + //end + end + endcase + end + end // always @ (posedge clk) + end +// verilint STARC-2.2.3.3 on + // commented out for now. Need it for DDR2 2T timing + /* end else begin: DDR2 + always @(posedge clk) + if (rst) begin + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end else begin + if (init_state_r == INIT_REG_WRITE) begin + // All ranks selected simultaneously + phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; + end else if ((wrlvl_odt) || + (init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH)) begin + phy_int_cs_n[0] <= #TCQ 1'b0; + end + else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; + end // else: !if(rst) + end // block: DDR2 */ +endgenerate + + assign phy_cs_n = phy_int_cs_n; + + //*************************************************************************** + // Write/read burst logic for calibration + //*************************************************************************** + + assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE); + assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || + ((init_state_r == INIT_RDLVL_STG1_READ) && ~rdlvl_pi_incdec) || //rdlvl pi dec + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + ((init_state_r == INIT_MPR_READ) && ~rdlvl_pi_incdec) || + (init_state_r == INIT_WRCAL_MULT_READS); + assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; + assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering +// assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); + + //*************************************************************************** + // Address generation and logic to count # of writes/reads issued during + // certain stages of calibration + //*************************************************************************** + + // Column address generation logic: + // Keep track of the current column address - since all bursts are in + // increments of 8 only during calibration, we need to keep track of + // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 + + always @(posedge clk) + if (rst || wrcal_done) + burst_addr_r <= #TCQ 1'b0; + else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || + (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || + (init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS) || + (init_state_r == INIT_WRCAL_READ_WAIT)) + burst_addr_r <= #TCQ 1'b1; + else if (rdlvl_wr_rd && new_burst_r) + burst_addr_r <= #TCQ ~burst_addr_r; + else + burst_addr_r <= #TCQ 1'b0; + + // Read Level Stage 1 requires writes to the entire row since + // a PRBS pattern is being written. This counter keeps track + // of the number of writes which depends on the column width + // The (stg1_wr_rd_cnt==9'd0) condition was added so the col + // address wraps around during stage1 reads + always @(posedge clk) + if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && + ~rdlvl_stg1_done)) + stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; + else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || + (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || + (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin + if (~complex_row0_wr_done || wr_victim_inc || + (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) + stg1_wr_rd_cnt <= #TCQ 'd127; + else + stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; + end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) + ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) + stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; + + always @(posedge clk) + if (rst) + wr_victim_inc <= #TCQ 1'b0; + else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) + wr_victim_inc <= #TCQ 1'b1; + else + wr_victim_inc <= #TCQ 1'b0; + + always @(posedge clk) + reset_rd_addr_r1 <= #TCQ reset_rd_addr; + +generate + if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) + complex_row_cnt <= #TCQ 'd0; + else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || + complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin + // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 + if ((complex_row_cnt < DQ_PER_DQS*2-1) && ~stg1_wr_done) + complex_row_cnt <= #TCQ complex_row_cnt + 1; + // During reads row count requires different conditions for increments + else if (stg1_wr_done) begin + if (reset_rd_addr_r1) + complex_row_cnt <= #TCQ 'd0; + // When looping multiple times in the same victim bit in a byte + else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) + complex_row_cnt <= #TCQ rd_victim_sel*2; + // When looping through victim bits within a byte + else if (complex_row_cnt < DQ_PER_DQS*2-1) + complex_row_cnt <= #TCQ complex_row_cnt + 1; + // When the number of samples is done and tap is incremented within a byte + else + complex_row_cnt <= #TCQ 'd0; + end + end + end else begin: row_cnt_victim_fixed + always @(posedge clk) + if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) + complex_row_cnt <= #TCQ 'd0; + else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) + complex_row_cnt <= #TCQ 'd1; + else + complex_row_cnt <= #TCQ 'd0; + end +endgenerate + +//row count + + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) + complex_row_cnt_ocal <= #TCQ 'd0; + else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || + (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin + // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 + if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin + complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; + end + end + + always @(posedge clk) + if (rst) + complex_odt_ext <= #TCQ 1'b0; + else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) + complex_odt_ext <= #TCQ 1'b0; + else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) + complex_odt_ext <= #TCQ 1'b1; + + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1))) begin + wr_victim_sel <= #TCQ 'd0; + end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin + wr_victim_sel <= #TCQ wr_victim_sel + 1; + end + + always @(posedge clk) + if (rst) begin + wr_victim_sel_ocal <= #TCQ 'd0; + end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin + wr_victim_sel_ocal <= #TCQ 'd0; + end else if (prbs_rdlvl_done && wr_victim_inc) begin + wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; + end + + always @(posedge clk) + if (rst) begin + victim_sel <= #TCQ 'd0; + victim_byte_cnt <= #TCQ 'd0; + end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin + victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; + victim_byte_cnt <= #TCQ 'd0; + end else begin + if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) + victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; + victim_byte_cnt <= #TCQ 'd0; + end + +generate + if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate + always @(posedge clk) + if (rst || (wr_victim_inc && (complex_row_cnt < DQ_PER_DQS*2-1) && ~prbs_rdlvl_done) || + (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal 'd85) begin + if (complex_num_reads < 'd6) + complex_num_reads <= #TCQ complex_num_reads + 1; + else + complex_num_reads <= #TCQ 'd1; + // Initila value for VCCAUX pattern is 3, 7, and 12 + end else if (stg1_wr_rd_cnt > 'd73) begin + if (stg1_wr_rd_cnt == 'd85) + complex_num_reads <= #TCQ 'd3; + else if (complex_num_reads < 'd5) + complex_num_reads <= #TCQ complex_num_reads + 1; + end else if (stg1_wr_rd_cnt > 'd39) begin + if (stg1_wr_rd_cnt == 'd73) + complex_num_reads <= #TCQ 'd7; + else if (complex_num_reads < 'd10) + complex_num_reads <= #TCQ complex_num_reads + 1; + end else begin + if (stg1_wr_rd_cnt == 'd39) + complex_num_reads <= #TCQ 'd12; + else if (complex_num_reads < 'd14) + complex_num_reads <= #TCQ complex_num_reads + 1; + end + // Initialize to 1 at the start of reads or after precharge and activate + end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || + ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) + complex_num_reads <= #TCQ 'd1; + + always @(posedge clk) + if (rst) + complex_num_reads_dec <= #TCQ 'd1; + else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || + ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) + complex_num_reads_dec <= #TCQ complex_num_reads; + else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) + complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; + + always @(posedge clk) + if (rst) + complex_address <= #TCQ 'd0; + else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || + ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) + complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; + + + always @ (posedge clk) + if (rst) + complex_oclkdelay_calib_start_int <= #TCQ 'b0; + else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 + complex_oclkdelay_calib_start_int <= #TCQ 'b1; + + always @(posedge clk) begin + complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; + complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; + end + + always @ (posedge clk) + if (rst) + complex_oclkdelay_calib_start <= #TCQ 'b0; + else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 + complex_oclkdelay_calib_start <= #TCQ 'b1; + + //packet fragmentation for complex oclkdealy calib write + always @(posedge clk) + if (rst || prbs_rdlvl_done_pulse) begin + complex_num_writes <= #TCQ 'd1; + end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin + if (stg1_wr_rd_cnt > 'd85) begin + if (complex_num_writes < 'd6) + complex_num_writes <= #TCQ complex_num_writes + 1; + else + complex_num_writes <= #TCQ 'd1; + // Initila value for VCCAUX pattern is 3, 7, and 12 + end else if (stg1_wr_rd_cnt > 'd73) begin + if (stg1_wr_rd_cnt == 'd85) + complex_num_writes <= #TCQ 'd3; + else if (complex_num_writes < 'd5) + complex_num_writes <= #TCQ complex_num_writes + 1; + end else if (stg1_wr_rd_cnt > 'd39) begin + if (stg1_wr_rd_cnt == 'd73) + complex_num_writes <= #TCQ 'd7; + else if (complex_num_writes < 'd10) + complex_num_writes <= #TCQ complex_num_writes + 1; + end else begin + if (stg1_wr_rd_cnt == 'd39) + complex_num_writes <= #TCQ 'd12; + else if (complex_num_writes < 'd14) + complex_num_writes <= #TCQ complex_num_writes + 1; + end + // Initialize to 1 at the start of write or after precharge and activate + end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) + complex_num_writes <= #TCQ 'd30; + else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) + complex_num_writes <= #TCQ 'd1; + + always @(posedge clk) + if (rst || prbs_rdlvl_done_pulse) + complex_num_writes_dec <= #TCQ 'd1; + else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || + ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) + complex_num_writes_dec <= #TCQ complex_num_writes; + else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) + complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; + + always @(posedge clk) + if (rst) + complex_sample_cnt_inc_ocal <= #TCQ 1'b0; + else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) + complex_sample_cnt_inc_ocal <= #TCQ 1'b1; + else + complex_sample_cnt_inc_ocal <= #TCQ 1'b0; + + always @(posedge clk) + if (rst) + complex_sample_cnt_inc <= #TCQ 1'b0; + else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) + complex_sample_cnt_inc <= #TCQ 1'b1; + else + complex_sample_cnt_inc <= #TCQ 1'b0; + + always @(posedge clk) begin + complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; + complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; + end + + //complex refresh req + always @ (posedge clk) begin + if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) + complex_ocal_ref_done <= #TCQ 1'b1; + else if (init_state_r == INIT_RDLVL_STG1_WRITE) + complex_ocal_ref_done <= #TCQ 1'b0; + end + + //complex ocal odt extention + always @(posedge clk) + if (rst) + complex_ocal_odt_ext <= #TCQ 1'b0; + else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) + complex_ocal_odt_ext <= #TCQ 1'b0; + else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) + complex_ocal_odt_ext <= #TCQ 1'b1; + + // OCLKDELAY calibration requires multiple writes because + // write can be up to 2 cycles early since OCLKDELAY tap + // can go down to 0 + always @(posedge clk) + if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || + (oclk_wr_cnt == 4'd0)) + oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; + else if ((init_state_r == INIT_OCLKDELAY_WRITE) && + new_burst_r && ~phy_data_full) + oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; + + // Write calibration requires multiple writes because + // write can be up to 2 cycles early due to new write + // leveling algorithm to avoid late writes + always @(posedge clk) + if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || + (wrcal_wr_cnt == 4'd0)) + wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; + else if ((init_state_r == INIT_WRCAL_WRITE) && + new_burst_r && ~phy_data_full) + wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; + + +generate +if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 + // 4 back-to-back reads with gaps for + // read data_offset calibration (rdlvl stage 2) + always @(posedge clk) + if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) + num_reads <= #TCQ 3'b000; + else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) + num_reads <= #TCQ num_reads - 1; + else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || + phy_cmd_full && new_burst_r) + num_reads <= #TCQ 3'b011; +end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 + // 4 back-to-back reads with gaps for + // read data_offset calibration (rdlvl stage 2) + always @(posedge clk) + if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) + num_reads <= #TCQ 3'b000; + else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) + num_reads <= #TCQ num_reads - 1; + else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || + phy_cmd_full && new_burst_r) + num_reads <= #TCQ 3'b111; +end +endgenerate + + // back-to-back reads during write calibration + always @(posedge clk) + if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) + wrcal_reads <= #TCQ 2'b00; + else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) + wrcal_reads <= #TCQ wrcal_reads - 1; + else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || + phy_cmd_full && new_burst_r) + wrcal_reads <= #TCQ 'd255; + + // determine how often to issue row command during read leveling writes + // and reads + always @(posedge clk) + if (rdlvl_wr_rd) begin + // 2:1 mode - every other command issued is a data command + // 4:1 mode - every command issued is a data command + if (nCK_PER_CLK == 2) begin + if (!phy_ctl_full) + new_burst_r <= #TCQ ~new_burst_r; + end else + new_burst_r <= #TCQ 1'b1; + end else + new_burst_r <= #TCQ 1'b1; + + // indicate when a write is occurring. PHY_WRDATA_EN must be asserted + // simultaneous with the corresponding command/address for CWL = 5,6 + always @(posedge clk) begin + rdlvl_wr_r <= #TCQ rdlvl_wr; + calib_wrdata_en <= #TCQ phy_wrdata_en; + end + + always @(posedge clk) begin + if (rst || wrcal_done) + extend_cal_pat <= #TCQ 1'b0; + else if (temp_lmr_done && (PRE_REV3ES == "ON")) + extend_cal_pat <= #TCQ 1'b1; + end + + + generate + if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 + // Write data enable asserted for one DIV4 clock cycle + // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. + always @(*) begin + if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_WRCAL_WRITE))) + phy_wrdata_en = 1'b1; + else + phy_wrdata_en = 1'b0; + end + end else begin: wrdqen_div2 // block: wrdqen_div4 + always @(*) + if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) + | phy_wrdata_en_r1) + phy_wrdata_en = 1'b1; + else + phy_wrdata_en = 1'b0; + + always @(posedge clk) + phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r + & ~phy_data_full; + + always @(posedge clk) begin + if (!phy_wrdata_en & first_rdlvl_pat_r) + wrdata_pat_cnt <= #TCQ 2'b00; + else if (wrdata_pat_cnt == 2'b11) + wrdata_pat_cnt <= #TCQ 2'b10; + else + wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; + end + + always @(posedge clk) begin + if (!phy_wrdata_en & first_wrcal_pat_r) + wrcal_pat_cnt <= #TCQ 2'b00; + else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) + wrcal_pat_cnt <= #TCQ 2'b00; + else if (wrcal_pat_cnt == 2'b11) + wrcal_pat_cnt <= #TCQ 2'b10; + else + wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; + end + + end + endgenerate + + + // indicate when a write is occurring. PHY_RDDATA_EN must be asserted + // simultaneous with the corresponding command/address. PHY_RDDATA_EN + // is used during read-leveling to determine read latency + assign phy_rddata_en = ~phy_if_empty; + + // Read data valid generation for MC and User Interface after calibration is + // complete + assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; + + //*************************************************************************** + // Generate training data written at start of each read-leveling stage + // For every stage of read leveling, 8 words are written into memory + // The format is as follows (shown as {rise,fall}): + // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 + // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 + //*************************************************************************** + + + always @(posedge clk) + if ((init_state_r == INIT_IDLE) || + (init_state_r == INIT_RDLVL_STG1_WRITE)) + cnt_init_data_r <= #TCQ 2'b00; + else if (phy_wrdata_en) + cnt_init_data_r <= #TCQ cnt_init_data_r + 1; + else if (init_state_r == INIT_WRCAL_WRITE) + cnt_init_data_r <= #TCQ 2'b10; + + + // write different sequence for very + // first write to memory only. Used to help us differentiate + // if the writes are "early" or "on-time" during read leveling + always @(posedge clk) + if (rst || rdlvl_stg1_rank_done) + first_rdlvl_pat_r <= #TCQ 1'b1; + else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) + first_rdlvl_pat_r <= #TCQ 1'b0; + + + always @(posedge clk) + if (rst || wrcal_resume || + (init_state_r == INIT_WRCAL_ACT_WAIT)) + first_wrcal_pat_r <= #TCQ 1'b1; + else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) + first_wrcal_pat_r <= #TCQ 1'b0; + +generate + if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first + + always @(posedge clk) + if (~oclkdelay_calib_done) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}}; + else if (!rdlvl_stg1_done) begin + // The 16 words for stage 1 write data in 2:1 mode is written + // over 4 consecutive controller clock cycles. Note that write + // data follows phy_wrdata_en by one clock cycle + case (wrdata_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}}, + {DQ_WIDTH/4{4'h9}}}; + end + + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + endcase + end else if (!prbs_rdlvl_done && ~phy_data_full) begin + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, + {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, + {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + end else if (!wrcal_done) begin + case (wrcal_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}}; + end + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h5}}}; + end + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, + {DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h4}}}; + end + endcase + end + + end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first + + always @(posedge clk) + if (~oclkdelay_calib_done) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; + else if (!rdlvl_stg1_done && ~phy_data_full) + // write different sequence for very + // first write to memory only. Used to help us differentiate + // if the writes are "early" or "on-time" during read leveling + if (first_rdlvl_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; + else + // For all others, change the first two words written in order + // to differentiate the "early write" and "on-time write" + // readback patterns during read leveling + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, + {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, + {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + else if (!wrcal_done) + if (first_wrcal_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; + else + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + + + end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first + + always @(posedge clk) + if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; + else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin + if (extend_cal_pat) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; + else if (first_wrcal_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; + else + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + end else if (!rdlvl_stg1_done && ~phy_data_full) begin + // write different sequence for very + // first write to memory only. Used to help us differentiate + // if the writes are "early" or "on-time" during read leveling + if (first_rdlvl_pat_r) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; + else + // For all others, change the first two words written in order + // to differentiate the "early write" and "on-time write" + // readback patterns during read leveling + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, + {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; + end else if (!prbs_rdlvl_done && ~phy_data_full) + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, + {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, + {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + else if (!complex_oclkdelay_calib_done && ~phy_data_full) + phy_wrdata <= #TCQ prbs_o; + end else begin: wrdq_div1_2to1_wrcal_first + + always @(posedge clk) + if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}, + {DQ_WIDTH/4{4'h0}}}; + else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin + case (wrcal_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h0}}, + {DQ_WIDTH/4{4'hF}}}; + end + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hA}}, + {DQ_WIDTH/4{4'h5}}}; + end + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, + {DQ_WIDTH/4{4'hD}}, + {DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h4}}}; + end + endcase + end else if (!rdlvl_stg1_done) begin + // The 16 words for stage 1 write data in 2:1 mode is written + // over 4 consecutive controller clock cycles. Note that write + // data follows phy_wrdata_en by one clock cycle + case (wrdata_pat_cnt) + 2'b00: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h3}}, + {DQ_WIDTH/4{4'h9}}}; + end + + 2'b01: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + + 2'b10: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, + {DQ_WIDTH/4{4'h7}}, + {DQ_WIDTH/4{4'h1}}, + {DQ_WIDTH/4{4'hB}}}; + end + + 2'b11: begin + phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, + {DQ_WIDTH/4{4'h2}}, + {DQ_WIDTH/4{4'h9}}, + {DQ_WIDTH/4{4'hC}}}; + end + endcase + end else if (!prbs_rdlvl_done && ~phy_data_full) begin + phy_wrdata <= #TCQ prbs_o; + // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in + // prbs_o being concatenated 8 times resulting in DQ_WIDTH + /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, + {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, + {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, + {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ + end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin + phy_wrdata <= #TCQ prbs_o; + end + + end +endgenerate + + //*************************************************************************** + // Memory control/address + //*************************************************************************** + + + // Phases [2] and [3] are always deasserted for 4:1 mode + generate + if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff + always @(posedge clk) begin + phy_ras_n[3:2] <= #TCQ 3'b11; + phy_cas_n[3:2] <= #TCQ 3'b11; + phy_we_n[3:2] <= #TCQ 3'b11; + end + end + endgenerate + + // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging + // (4) auto refresh + // verilint STARC-2.7.3.3b off + generate + if (!(CWL_M % 2)) begin: even_cwl + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_REFRESH) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin + phy_ras_n[0] <= #TCQ 1'b0; + phy_ras_n[1] <= #TCQ 1'b1; + end else begin + phy_ras_n[0] <= #TCQ 1'b1; + phy_ras_n[1] <= #TCQ 1'b1; + end + end + + // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command + // (3) auto refresh + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_REFRESH) || + (rdlvl_wr_rd && new_burst_r))begin + phy_cas_n[0] <= #TCQ 1'b0; + phy_cas_n[1] <= #TCQ 1'b1; + end else begin + phy_cas_n[0] <= #TCQ 1'b1; + phy_cas_n[1] <= #TCQ 1'b1; + end + end + // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only + // occur during read leveling), (3) Issuing ZQ Long Calib command, + // (4) Precharge + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE)|| + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (rdlvl_wr && new_burst_r))begin + phy_we_n[0] <= #TCQ 1'b0; + phy_we_n[1] <= #TCQ 1'b1; + end else begin + phy_we_n[0] <= #TCQ 1'b1; + phy_we_n[1] <= #TCQ 1'b1; + end + end + end else begin: odd_cwl + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (init_state_r == INIT_REFRESH))begin + phy_ras_n[0] <= #TCQ 1'b1; + phy_ras_n[1] <= #TCQ 1'b0; + end else begin + phy_ras_n[0] <= #TCQ 1'b1; + phy_ras_n[1] <= #TCQ 1'b1; + end + end + // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command + // (3) auto refresh + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_REFRESH) || + (rdlvl_wr_rd && new_burst_r))begin + phy_cas_n[0] <= #TCQ 1'b1; + phy_cas_n[1] <= #TCQ 1'b0; + end else begin + phy_cas_n[0] <= #TCQ 1'b1; + phy_cas_n[1] <= #TCQ 1'b1; + end + end + // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only + // occur during read leveling), (3) Issuing ZQ Long Calib command, + // (4) Precharge + always @(posedge clk) begin + if ((init_state_r == INIT_LOAD_MR) || + (init_state_r == INIT_MPR_RDEN) || + (init_state_r == INIT_MPR_DISABLE) || + (init_state_r == INIT_REG_WRITE) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_WRLVL_START) || + (init_state_r == INIT_WRLVL_LOAD_MR) || + (init_state_r == INIT_WRLVL_LOAD_MR2) || + (init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_DDR2_PRECHARGE)|| + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (rdlvl_wr && new_burst_r))begin + phy_we_n[0] <= #TCQ 1'b1; + phy_we_n[1] <= #TCQ 1'b0; + end else begin + phy_we_n[0] <= #TCQ 1'b1; + phy_we_n[1] <= #TCQ 1'b1; + end + end + end + endgenerate +// verilint STARC-2.7.3.3b on + + + // Assign calib_cmd for the command field in PHY_Ctl_Word + always @(posedge clk) begin + if (wr_level_dqs_asrt) begin + // Request to toggle DQS during write leveling + calib_cmd <= #TCQ 3'b001; + if (CWL_M % 2) begin // odd write latency + calib_data_offset_0 <= #TCQ CWL_M + 3; + calib_data_offset_1 <= #TCQ CWL_M + 3; + calib_data_offset_2 <= #TCQ CWL_M + 3; + calib_cas_slot <= #TCQ 2'b01; + end else begin // even write latency + calib_data_offset_0 <= #TCQ CWL_M + 2; + calib_data_offset_1 <= #TCQ CWL_M + 2; + calib_data_offset_2 <= #TCQ CWL_M + 2; + calib_cas_slot <= #TCQ 2'b00; + end + end else if (rdlvl_wr && new_burst_r) begin + // Write Command + calib_cmd <= #TCQ 3'b001; + if (CWL_M % 2) begin // odd write latency + calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; + calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; + calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; + calib_cas_slot <= #TCQ 2'b01; + end else begin // even write latency + calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; + calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; + calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; + calib_cas_slot <= #TCQ 2'b00; + end + end else if (rdlvl_rd && new_burst_r) begin + // Read Command + calib_cmd <= #TCQ 3'b011; + if (CWL_M % 2) + calib_cas_slot <= #TCQ 2'b01; + else + calib_cas_slot <= #TCQ 2'b00; + if (~pi_calib_done_r1) begin + calib_data_offset_0 <= #TCQ 6'd0; + calib_data_offset_1 <= #TCQ 6'd0; + calib_data_offset_2 <= #TCQ 6'd0; + end else if (~pi_dqs_found_done_r1) begin + calib_data_offset_0 <= #TCQ rd_data_offset_0; + calib_data_offset_1 <= #TCQ rd_data_offset_1; + calib_data_offset_2 <= #TCQ rd_data_offset_2; + end else begin + calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; + calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; + calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; + end + end else begin + // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, + // Active, Refresh + calib_cmd <= #TCQ 3'b100; + calib_data_offset_0 <= #TCQ 6'd0; + calib_data_offset_1 <= #TCQ 6'd0; + calib_data_offset_2 <= #TCQ 6'd0; + if (CWL_M % 2) + calib_cas_slot <= #TCQ 2'b01; + else + calib_cas_slot <= #TCQ 2'b00; + end + end + + // Write Enable to PHY_Control FIFO always asserted + // No danger of this FIFO being Full with 4:1 sync clock ratio + // This is also the write enable to the command OUT_FIFO + always @(posedge clk) begin + if (rst) begin + calib_ctl_wren <= #TCQ 1'b0; + calib_cmd_wren <= #TCQ 1'b0; + calib_seq <= #TCQ 2'b00; + end else if (cnt_pwron_cke_done_r && phy_ctl_ready + && ~(phy_ctl_full || phy_cmd_full )) begin + calib_ctl_wren <= #TCQ 1'b1; + calib_cmd_wren <= #TCQ 1'b1; + calib_seq <= #TCQ calib_seq + 1; + end else begin + calib_ctl_wren <= #TCQ 1'b0; + calib_cmd_wren <= #TCQ 1'b0; + calib_seq <= #TCQ calib_seq; + end + end + + generate + genvar rnk_i; + for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk + always @(posedge clk) begin + if (rst) begin + mr2_r[rnk_i] <= #TCQ 2'b00; + mr1_r[rnk_i] <= #TCQ 3'b000; + end else begin + mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; + mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; + end + end + end + endgenerate + + // ODT assignment based on slot config and slot present + // For single slot systems slot_1_present input will be ignored + // Assuming component interfaces to be single slot systems + generate + if (nSLOTS == 1) begin: gen_single_slot_odt + always @(posedge clk) begin + if (rst) begin + tmp_mr2_r[1] <= #TCQ 2'b00; + tmp_mr2_r[2] <= #TCQ 2'b00; + tmp_mr2_r[3] <= #TCQ 2'b00; + tmp_mr1_r[1] <= #TCQ 3'b000; + tmp_mr1_r[2] <= #TCQ 3'b000; + tmp_mr1_r[3] <= #TCQ 3'b000; + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; + phy_tmp_odt_r <= #TCQ 4'b0000; + phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; + end else begin + case ({slot_0_present[0],slot_0_present[1], + slot_0_present[2],slot_0_present[3]}) + // Single slot configuration with quad rank + // Assuming same behavior as single slot dual rank for now + // DDR2 does not have quad rank parts + 4'b1111: begin + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 RTT_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 RTT_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + phy_tmp_odt_r <= #TCQ 4'b0001; + // Chip Select assignments + phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) + ) +: nCS_PER_RANK] <= #TCQ 'b0; + end + + // Single slot configuration with single rank + 4'b1000: begin + phy_tmp_odt_r <= #TCQ 4'b0001; + if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin + phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; + end else begin + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; + end + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 RTT_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 RTT_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + + // Single slot configuration with dual rank + 4'b1100: begin + phy_tmp_odt_r <= #TCQ 4'b0001; + // Chip Select assignments + + phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) + ) +: nCS_PER_RANK] <= #TCQ 'b0; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + + default: begin + phy_tmp_odt_r <= #TCQ 4'b0001; + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + endcase + end + end + end else if (nSLOTS == 2) begin: gen_dual_slot_odt + always @ (posedge clk) begin + if (rst) begin + tmp_mr2_r[1] <= #TCQ 2'b00; + tmp_mr2_r[2] <= #TCQ 2'b00; + tmp_mr2_r[3] <= #TCQ 2'b00; + tmp_mr1_r[1] <= #TCQ 3'b000; + tmp_mr1_r[2] <= #TCQ 3'b000; + tmp_mr1_r[3] <= #TCQ 3'b000; + phy_tmp_odt_r <= #TCQ 4'b0000; + phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; + phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; + end else begin + case ({slot_0_present[0],slot_0_present[1], + slot_1_present[0],slot_1_present[1]}) + // Two slot configuration, one slot present, single rank + 4'b10_00: begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r <= #TCQ 4'b0001; + end + phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + 4'b00_10: begin + + //Rank1 ODT enabled + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r <= #TCQ 4'b0001; + end + phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank1 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank1 Rtt_NOM defaults to 120 ohms + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + // Two slot configuration, one slot present, dual rank + 4'b00_11: begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r + <= #TCQ 4'b0001; + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + 4'b11_00: begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // odt turned on only during write + phy_tmp_odt_r <= #TCQ 4'b0001; + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank1 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + end + // Two slot configuration, one rank per slot + 4'b10_10: begin + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r == 2'b00)begin + phy_tmp_odt_r + <= #TCQ 4'b0010; //bit0 for rank0 + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0001; //bit0 for rank0 + end + end else begin + if((init_state_r == INIT_WRLVL_WAIT) || + (init_next_state == INIT_RDLVL_STG1_WRITE) || + (init_next_state == INIT_WRCAL_WRITE) || + (init_next_state == INIT_OCAL_CENTER_WRITE) || + (init_next_state == INIT_OCLKDELAY_WRITE)) + phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) + else if ((init_next_state == INIT_PI_PHASELOCK_READS) || + (init_next_state == INIT_MPR_READ) || + (init_next_state == INIT_RDLVL_STG1_READ) || + (init_next_state == INIT_RDLVL_COMPLEX_READ) || + (init_next_state == INIT_RDLVL_STG2_READ) || + (init_next_state == INIT_OCLKDELAY_READ) || + (init_next_state == INIT_WRCAL_READ) || + (init_next_state == INIT_WRCAL_MULT_READS)) + phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : + (RTT_WR == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + end + end + // Two Slots - One slot with dual rank and other with single rank + 4'b10_11: begin + + //Rank3 Rtt_NOM + tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + tmp_mr2_r[2] <= #TCQ 2'b00; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[1] <= #TCQ 3'b000; + end + //Slot1 Rank1 or Rank3 is being written + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r == 2'b00)begin + phy_tmp_odt_r + <= #TCQ 4'b0010; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0001; + end + end else begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + if (chip_cnt_r[0] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0011; + //Slot0 Rank0 is being written + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted + end + end else if ((init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS))begin + if (chip_cnt_r == 2'b00) begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0001; + end + end + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + + end + // Two Slots - One slot with dual rank and other with single rank + 4'b11_10: begin + + //Rank2 Rtt_NOM + tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : + (RTT_NOM2 == "120") ? 3'b010 : + (RTT_NOM2 == "20") ? 3'b100 : + (RTT_NOM2 == "30") ? 3'b101 : + (RTT_NOM2 == "40") ? 3'b011: + 3'b000; + tmp_mr2_r[2] <= #TCQ 2'b00; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011: + 3'b000; + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r[1] == 1'b1)begin + phy_tmp_odt_r <= + #TCQ 4'b0001; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0100; // rank 2 ODT asserted + end + end else begin + if (// wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + + if (chip_cnt_r[1] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0110; + end else begin + phy_tmp_odt_r <= + #TCQ 4'b0101; + end + end else if ((init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS)) begin + + if (chip_cnt_r[1] == 1'b1) begin + phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ 4'b0010; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + end + end + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + end + // Two Slots - two ranks per slot + 4'b11_11: begin + //Rank2 Rtt_NOM + tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : + (RTT_NOM2 == "120") ? 3'b010 : + (RTT_NOM2 == "20") ? 3'b100 : + (RTT_NOM2 == "30") ? 3'b101 : + (RTT_NOM2 == "40") ? 3'b011 : + 3'b000; + //Rank3 Rtt_NOM + tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : + (RTT_NOM3 == "120") ? 3'b010 : + (RTT_NOM3 == "20") ? 3'b100 : + (RTT_NOM3 == "30") ? 3'b101 : + (RTT_NOM3 == "40") ? 3'b011 : + 3'b000; + tmp_mr2_r[2] <= #TCQ 2'b00; + tmp_mr2_r[3] <= #TCQ 2'b00; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done && + (wrlvl_rank_cntr==3'd0))) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + end else begin + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM after write leveling completes + tmp_mr1_r[1] <= #TCQ 3'b000; + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM after write leveling completes + tmp_mr1_r[0] <= #TCQ 3'b000; + end + + if(DRAM_TYPE == "DDR2")begin + if(chip_cnt_r[1] == 1'b1)begin + phy_tmp_odt_r + <= #TCQ 4'b0001; + end else begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + end + end else begin + if (//wrlvl_odt || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + //Slot1 Rank1 or Rank3 is being written + if (chip_cnt_r[0] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0110; + //Slot0 Rank0 or Rank2 is being written + end else begin + phy_tmp_odt_r + <= #TCQ 4'b1001; + end + end else if ((init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS))begin + //Slot1 Rank1 or Rank3 is being read + if (chip_cnt_r[0] == 1'b1) begin + phy_tmp_odt_r + <= #TCQ 4'b0100; + //Slot0 Rank0 or Rank2 is being read + end else begin + phy_tmp_odt_r + <= #TCQ 4'b1000; + end + end + end + + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + end + default: begin + phy_tmp_odt_r <= #TCQ 4'b1111; + // Chip Select assignments + phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] + <= #TCQ {nCS_PER_RANK{1'b0}}; + if ((RTT_WR == "OFF") || + ((WRLVL=="ON") && ~wrlvl_done)) begin + //Rank0 Dynamic ODT disabled + tmp_mr2_r[0] <= #TCQ 2'b00; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + 3'b000; + //Rank1 Dynamic ODT disabled + tmp_mr2_r[1] <= #TCQ 2'b00; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : + (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "60") ? 3'b010 : + 3'b000; + end else begin + //Rank0 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank0 Rtt_NOM + tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + //Rank1 Dynamic ODT defaults to 120 ohms + tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : + 2'b10; + //Rank1 Rtt_NOM + tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : + (RTT_NOM_int == "120") ? 3'b010 : + (RTT_NOM_int == "20") ? 3'b100 : + (RTT_NOM_int == "30") ? 3'b101 : + (RTT_NOM_int == "40") ? 3'b011 : + 3'b000; + end + end + endcase + end + end + end + endgenerate + + + // PHY only supports two ranks. + // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 + // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 + +generate +if(CKE_ODT_AUX == "FALSE") begin + if ((nSLOTS == 1) && (RANKS < 2)) begin + always @(posedge clk) + if (rst) begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; + calib_odt <= 2'b00 ; + end else begin + if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; + end else begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || + wrlvl_rank_done || wrlvl_rank_done_r1 || + (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + complex_odt_ext || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + complex_ocal_odt_ext || + (init_state_r == INIT_OCLKDELAY_WRITE)|| + (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin + // Quad rank in a single slot + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 1) && (RANKS <= 2)) begin + always @(posedge clk) + if (rst) begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; + calib_odt <= 2'b00 ; + end else begin + if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; + end else begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || + wrlvl_rank_done_r2 || + (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || + complex_odt_ext || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_WRITE_READ) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + complex_ocal_odt_ext || + (init_state_r == INIT_OCLKDELAY_WRITE)|| + (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin + // Dual rank in a single slot + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 2) && (RANKS == 2)) begin + always @(posedge clk) + if (rst)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; + calib_odt <= 2'b00 ; + end else begin + if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; + end else begin + calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; + end + if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || + ((DRAM_TYPE == "DDR3") && + (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin + calib_odt[0] <= #TCQ 1'b0; + calib_odt[1] <= #TCQ 1'b0; + end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE)) begin + // Quad rank in a single slot + if (nCK_PER_CLK == 2) begin + calib_odt[0] + <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; + calib_odt[1] + <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; + end else begin + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end + // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 + end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && + ((init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_MPR_READ) || + (init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ) || + (init_state_r == INIT_RDLVL_STG2_READ) || + (init_state_r == INIT_OCLKDELAY_READ) || + (init_state_r == INIT_WRCAL_READ) || + (init_state_r == INIT_WRCAL_MULT_READS))) begin + if (nCK_PER_CLK == 2) begin + calib_odt[0] + <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; + calib_odt[1] + <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; + end else begin + calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; + calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; + end + // disable well before next command and before disabling write leveling + end else if(cnt_cmd_done_m7_r || + (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) + calib_odt <= #TCQ 2'b00; + end + end +end else begin//USE AUX OUTPUT for routing CKE and ODT. + if ((nSLOTS == 1) && (RANKS < 2)) begin + always @(posedge clk) + if (rst) begin + calib_aux_out <= #TCQ 4'b0000; + end else begin + if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin + calib_aux_out[0] <= #TCQ 1'b1; + calib_aux_out[2] <= #TCQ 1'b1; + end else begin + calib_aux_out[0] <= #TCQ 1'b0; + calib_aux_out[2] <= #TCQ 1'b0; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || + wrlvl_rank_done || wrlvl_rank_done_r1 || + (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE))) begin + // Quad rank in a single slot + calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; + calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 1) && (RANKS <= 2)) begin + always @(posedge clk) + if (rst) begin + calib_aux_out <= #TCQ 4'b0000; + end else begin + if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin + calib_aux_out[0] <= #TCQ 1'b1; + calib_aux_out[2] <= #TCQ 1'b1; + end else begin + calib_aux_out[0] <= #TCQ 1'b0; + calib_aux_out[2] <= #TCQ 1'b0; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || + wrlvl_rank_done_r2 || + (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE))) begin + // Dual rank in a single slot + calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; + calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; + end else begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end + end + end else if ((nSLOTS == 2) && (RANKS == 2)) begin + always @(posedge clk) + if (rst) + calib_aux_out <= #TCQ 4'b0000; + else begin + if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin + calib_aux_out[0] <= #TCQ 1'b1; + calib_aux_out[2] <= #TCQ 1'b1; + end else begin + calib_aux_out[0] <= #TCQ 1'b0; + calib_aux_out[2] <= #TCQ 1'b0; + end + if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || + wrlvl_rank_done_r2 || + (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end else if (((DRAM_TYPE == "DDR3") + ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) + && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || + (init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_WRITE))) begin + // Quad rank in a single slot + if (nCK_PER_CLK == 2) begin + calib_aux_out[1] + <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; + calib_aux_out[3] + <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; + end else begin + calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; + calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; + end + end else begin + calib_aux_out[1] <= #TCQ 1'b0; + calib_aux_out[3] <= #TCQ 1'b0; + end + end + end +end +endgenerate + + //***************************************************************** + // memory address during init + //***************************************************************** + + always @(posedge clk) + phy_data_full_r <= #TCQ phy_data_full; +// verilint STARC-2.7.3.3b off + always @(*)begin + // Bus 0 for address/bank never used + address_w = 'b0; + bank_w = 'b0; + if ((init_state_r == INIT_PRECHARGE) || + (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || + (init_state_r == INIT_ZQCL) || + (init_state_r == INIT_DDR2_PRECHARGE)) begin + // Set A10=1 for ZQ long calibration or Precharge All + address_w = 'b0; + address_w[10] = 1'b1; + bank_w = 'b0; + end else if (init_state_r == INIT_WRLVL_START) begin + // Enable wrlvl in MR1 + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[2] = mr1_r[chip_cnt_r][0]; + address_w[6] = mr1_r[chip_cnt_r][1]; + address_w[9] = mr1_r[chip_cnt_r][2]; + address_w[7] = 1'b1; + end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin + // Finished with write leveling, disable wrlvl in MR1 + // For single rank disable Rtt_Nom + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[2] = mr1_r[chip_cnt_r][0]; + address_w[6] = mr1_r[chip_cnt_r][1]; + address_w[9] = mr1_r[chip_cnt_r][2]; + end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin + // Set RTT_WR in MR2 after write leveling disabled + bank_w[1:0] = 2'b10; + address_w = load_mr2[ROW_WIDTH-1:0]; + address_w[10:9] = mr2_r[chip_cnt_r]; + end else if (init_state_r == INIT_MPR_READ) begin + address_w = 'b0; + bank_w = 'b0; + end else if (init_state_r == INIT_MPR_RDEN) begin + // Enable MPR read with LMR3 and A2=1 + bank_w[BANK_WIDTH-1:0] = 'd3; + address_w = {ROW_WIDTH{1'b0}}; + address_w[2] = 1'b1; + end else if (init_state_r == INIT_MPR_DISABLE) begin + // Disable MPR read with LMR3 and A2=0 + bank_w[BANK_WIDTH-1:0] = 'd3; + address_w = {ROW_WIDTH{1'b0}}; + end else if ((init_state_r == INIT_REG_WRITE)& + (DRAM_TYPE == "DDR3"))begin + // bank_w is assigned a 3 bit value. In some + // DDR2 cases there will be only two bank bits. + //Qualifying the condition with DDR3 + bank_w = 'b0; + address_w = 'b0; + case (reg_ctrl_cnt_r) + 4'h1:begin + address_w[4:0] = REG_RC1[4:0]; + bank_w = REG_RC1[7:5]; + end + 4'h2: address_w[4:0] = REG_RC2[4:0]; + 4'h3: begin + address_w[4:0] = REG_RC3[4:0]; + bank_w = REG_RC3[7:5]; + end + 4'h4: begin + address_w[4:0] = REG_RC4[4:0]; + bank_w = REG_RC4[7:5]; + end + 4'h5: begin + address_w[4:0] = REG_RC5[4:0]; + bank_w = REG_RC5[7:5]; + end + 4'h6: begin + address_w[4:0] = REG_RC10[4:0]; + bank_w = REG_RC10[7:5]; + end + 4'h7: begin + address_w[4:0] = REG_RC11[4:0]; + bank_w = REG_RC11[7:5]; + end + default: address_w[4:0] = REG_RC0[4:0]; + endcase + end else if (init_state_r == INIT_LOAD_MR) begin + // If loading mode register, look at cnt_init_mr to determine + // which MR is currently being programmed + address_w = 'b0; + bank_w = 'b0; + if(DRAM_TYPE == "DDR3")begin + if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin + // end of the calibration programming correct + // burst length + if (TEST_AL == "0") begin + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + address_w[8]= 1'b0; //Don't reset DLL + end else begin + // programming correct AL value + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + if (TEST_AL == "CL-1") + address_w[4:3]= 2'b01; // AL="CL-1" + else + address_w[4:3]= 2'b10; // AL="CL-2" + end + end else begin + case (cnt_init_mr_r) + INIT_CNT_MR2: begin + bank_w[1:0] = 2'b10; + address_w = load_mr2[ROW_WIDTH-1:0]; + address_w[10:9] = mr2_r[chip_cnt_r]; + end + INIT_CNT_MR3: begin + bank_w[1:0] = 2'b11; + address_w = load_mr3[ROW_WIDTH-1:0]; + end + INIT_CNT_MR1: begin + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[2] = mr1_r[chip_cnt_r][0]; + address_w[6] = mr1_r[chip_cnt_r][1]; + address_w[9] = mr1_r[chip_cnt_r][2]; + end + INIT_CNT_MR0: begin + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + // fixing it to BL8 for calibration + address_w[1:0] = 2'b00; + end + default: begin + bank_w = {BANK_WIDTH{1'bx}}; + address_w = {ROW_WIDTH{1'bx}}; + end + endcase + end + end else begin // DDR2 + case (cnt_init_mr_r) + INIT_CNT_MR2: begin + if(~ddr2_refresh_flag_r)begin + bank_w[1:0] = 2'b10; + address_w = load_mr2[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + address_w[8]= 1'b0; + //MRS command without resetting DLL + end + end + INIT_CNT_MR3: begin + if(~ddr2_refresh_flag_r)begin + bank_w[1:0] = 2'b11; + address_w = load_mr3[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + address_w[8]= 1'b0; + //MRS command without resetting DLL. Repeted again + // because there is an extra state. + end + end + INIT_CNT_MR1: begin + bank_w[1:0] = 2'b01; + if(~ddr2_refresh_flag_r)begin + address_w = load_mr1[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + address_w = load_mr1[ROW_WIDTH-1:0]; + address_w[9:7] = 3'b111; + //OCD default state + end + end + INIT_CNT_MR0: begin + if(~ddr2_refresh_flag_r)begin + bank_w[1:0] = 2'b00; + address_w = load_mr0[ROW_WIDTH-1:0]; + end else begin // second set of lm commands + bank_w[1:0] = 2'b01; + address_w = load_mr1[ROW_WIDTH-1:0]; + if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin + // always disable odt for rank 1 and rank 3 as per SPEC + address_w[2] = 'b0; + address_w[6] = 'b0; + end + //OCD exit + end + end + default: begin + bank_w = {BANK_WIDTH{1'bx}}; + address_w = {ROW_WIDTH{1'bx}}; + end + endcase + end + end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || + (init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_STG1_READ) || + (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin + // Writing and reading PRBS pattern for read leveling stage 1 + // Need to support burst length 4 or 8. PRBS pattern will be + // written to entire row and read back from the same row repeatedly + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || + ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + end else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin + if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || + // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) + address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; + else + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end + //need to add address for complex oclkdelay calib + end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || + (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + end else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin + if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) + // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) + address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; + else + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end + + end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || + (init_state_r == INIT_OCAL_CENTER_WRITE) || + (init_state_r == INIT_OCLKDELAY_READ)) begin + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if (oclk_wr_cnt == NUM_STG1_WR_RD) + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end else if ((init_state_r == INIT_WRCAL_WRITE) || + (init_state_r == INIT_WRCAL_READ)) begin + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + if (wrcal_wr_cnt == NUM_STG1_WR_RD) + address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; + else if (phy_data_full_r || (!new_burst_r)) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; + else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) + address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; + end else if ((init_state_r == INIT_WRCAL_MULT_READS) || + (init_state_r == INIT_RDLVL_STG2_READ)) begin + // when writing or reading back training pattern for read leveling stage2 + // need to support burst length of 4 or 8. This may mean issuing + // multiple commands to cover the entire range of addresses accessed + // during read leveling. + // Hard coding A[12] to 1 so that it will always be burst length of 8 + // for DDR3. Does not have any effect on DDR2. + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; + address_w[COL_WIDTH-1:0] = + {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; + address_w[12] = 1'b1; + end else if ((init_state_r == INIT_RDLVL_ACT) || + (init_state_r == INIT_RDLVL_COMPLEX_ACT) || + (init_state_r == INIT_WRCAL_ACT) || + (init_state_r == INIT_OCAL_COMPLEX_ACT) || + (init_state_r == INIT_OCAL_CENTER_ACT) || + (init_state_r == INIT_OCLKDELAY_ACT)) begin + + bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; + //if (stg1_wr_rd_cnt == 'd22) + // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; + //else + address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : + CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; + end else begin + bank_w = {BANK_WIDTH{1'bx}}; + address_w = {ROW_WIDTH{1'bx}}; + end + end + // verilint STARC-2.7.3.3b on + // registring before sending out + generate + genvar r,s; + if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror + for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop + always @(posedge clk) begin + phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; + phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; + end + end + end else begin: gen_mirror + // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) + // Mirror for the 2nd rank only. Logic needs to be enhanced to account + // for multiple slots, currently only supports one slot, 2-rank config + + for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop + for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba + + always @(posedge clk) + if (chip_cnt_r == 2'b00) begin + phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; + end else begin + phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; + end + + end + end + + for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop + for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr + always @(posedge clk) + if (chip_cnt_r == 2'b00) begin + phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; + end else begin + phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ + (s == 3) ? 4 : + ((s == 4) ? 3 : + ((s == 5) ? 6 : + ((s == 6) ? 5 : + ((s == 7) ? 8 : + ((s == 8) ? 7 : s)))))]; + end + end + end + + end + endgenerate + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v new file mode 100644 index 0000000..8b5fc72 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v @@ -0,0 +1,286 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_cntlr.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Steps through the major sections of the output clock +// delay algorithm. Enabling various subblocks at the right time. +// +// Steps through each byte of the interface. +// +// Implements both the simple and complex data pattern. +// +// for each byte in interface +// begin +// Limit +// Scan - which includes DQS centering +// Precharge +// end +// set _wrlvl and _done equal to one +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ocd_cntlr # + (parameter TCQ = 100, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8) + (/*AUTOARG*/ + // Outputs + wrlvl_final, complex_wrlvl_final, oclk_init_delay_done, + ocd_prech_req, lim_start, complex_oclkdelay_calib_done, + oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2, + phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt, + reset_scan, + // Inputs + clk, rst, prech_done, oclkdelay_calib_start, + complex_oclkdelay_calib_start, lim_done, phy_rddata_en, + po_counter_read_val, po_rdy, scan_done + ); + + localparam ONE = 1; + + input clk; + input rst; + + output wrlvl_final, complex_wrlvl_final; + reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r; + always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns; + always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns; + assign wrlvl_final = wrlvl_final_r; + assign complex_wrlvl_final = complex_wrlvl_final_r; + + // Completed initial delay increment + output oclk_init_delay_done; // may not need this... maybe for fast cal mode. + assign oclk_init_delay_done = 1'b1; + + // Precharge done status from ddr_phy_init + input prech_done; + reg ocd_prech_req_ns, ocd_prech_req_r; + always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns; + output ocd_prech_req; + assign ocd_prech_req = ocd_prech_req_r; + + input oclkdelay_calib_start, complex_oclkdelay_calib_start; + input lim_done; + + reg lim_start_ns, lim_start_r; + always @(posedge clk) lim_start_r <= #TCQ lim_start_ns; + output lim_start; + assign lim_start = lim_start_r; + + reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r; + always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns; + output complex_oclkdelay_calib_done; + assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r; + + reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r; + always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns; + output oclkdelay_calib_done; + assign oclkdelay_calib_done = oclkdelay_calib_done_r; + + input phy_rddata_en; + reg prde_r1, prde_r2; + always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en; + always @(posedge clk) prde_r2 <= #TCQ prde_r1; + wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en; + + reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3; + always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde; + always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1; + always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2; + output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3; + assign phy_rddata_en_1 = phy_rddata_en_r1; + assign phy_rddata_en_2 = phy_rddata_en_r2; + assign phy_rddata_en_3 = phy_rddata_en_r3; + + input [8:0] po_counter_read_val; + reg ocd_cntlr2stg2_dec_r; + output ocd_cntlr2stg2_dec; + assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r; + input po_rdy; + + reg [3:0] po_rd_wait_ns, po_rd_wait_r; + always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns; + + reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r; + always @(posedge clk) byte_r <= #TCQ byte_ns; + output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + assign oclkdelay_calib_cnt = {1'b0, byte_r}; + + reg reset_scan_ns, reset_scan_r; + always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns; + output reset_scan; + assign reset_scan = reset_scan_r; + input scan_done; + + reg [2:0] sm_ns, sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + + // Primary state machine. + + always @(*) begin + + // Default next state assignments. + + byte_ns = byte_r; + complex_wrlvl_final_ns = complex_wrlvl_final_r; + lim_start_ns = lim_start_r; + oclkdelay_calib_done_ns = oclkdelay_calib_done_r; + complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r; + ocd_cntlr2stg2_dec_r = 1'b0; + po_rd_wait_ns = po_rd_wait_r; + if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1; + reset_scan_ns = reset_scan_r; + wrlvl_final_ns = wrlvl_final_r; + sm_ns = sm_r; + ocd_prech_req_ns= 1'b0; + + if (rst == 1'b1) begin + + // RESET next states + complex_oclkdelay_calib_done_ns = 1'b0; + complex_wrlvl_final_ns = 1'b0; + sm_ns = /*AK("READY")*/3'd0; + lim_start_ns = 1'b0; + oclkdelay_calib_done_ns = 1'b0; + reset_scan_ns = 1'b1; + wrlvl_final_ns = 1'b0; + end else + + // State based actions and next states. + case (sm_r) + /*AL("READY")*/3'd0: begin + byte_ns = {DQS_CNT_WIDTH{1'b0}}; + if (oclkdelay_calib_start && ~oclkdelay_calib_done_r || + complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r) + begin + sm_ns = /*AK("LIMIT_START")*/3'd1; + lim_start_ns = 1'b1; + end + end + + /*AL("LIMIT_START")*/3'd1: + sm_ns = /*AK("LIMIT_WAIT")*/3'd2; + + /*AL("LIMIT_WAIT")*/3'd2:begin + if (lim_done) begin + lim_start_ns = 1'b0; + sm_ns = /*AK("SCAN")*/3'd3; + reset_scan_ns = 1'b0; + end + end + + /*AL("SCAN")*/3'd3:begin + if (scan_done) begin + reset_scan_ns = 1'b1; + sm_ns = /*AK("COMPUTE")*/3'd4; + end + end + + /*AL("COMPUTE")*/3'd4:begin + sm_ns = /*AK("PRECHARGE")*/3'd5; + ocd_prech_req_ns = 1'b1; + end + + /*AL("PRECHARGE")*/3'd5:begin + if (prech_done) sm_ns = /*AK("DONE")*/3'd6; + end + + /*AL("DONE")*/3'd6:begin + byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0]; + if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin + byte_ns = {DQS_CNT_WIDTH{1'b0}}; + po_rd_wait_ns = 4'd8; + sm_ns = /*AK("STG2_2_ZERO")*/3'd7; + end else begin + sm_ns = /*AK("LIMIT_START")*/3'd1; + lim_start_ns = 1'b1; + end + end + + /*AL("STG2_2_ZERO")*/3'd7: + if (~|po_rd_wait_r && po_rdy) + if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1; + else begin + if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin + sm_ns = /*AK("READY")*/3'd0; + oclkdelay_calib_done_ns= 1'b1; + wrlvl_final_ns = 1'b1; + if (complex_oclkdelay_calib_start) begin + complex_oclkdelay_calib_done_ns = 1'b1; + complex_wrlvl_final_ns = 1'b1; + end + end else begin + byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0]; + po_rd_wait_ns = 4'd8; + end + end // else: !if(|po_counter_read_val[5:0]) + + endcase // case (sm_r) + end // always @ begin + +endmodule // mig_7series_v4_2_ddr_phy_ocd_cntlr + +// Local Variables: +// verilog-autolabel-prefix: "3'd" +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v new file mode 100644 index 0000000..db2d8f7 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v @@ -0,0 +1,232 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_data.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Data comparison for both "non-complex" and "complex" data. +// +// Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata +// bus is compared against a fixed ones and zeros pattern, or against data +// provided on the prob_o bus. +// +// In the case of complex data, the phy_rddata data is delayed by two +// clocks to match up with the prbs_o data. +// +// For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered. +// A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ +// bus, 64 bytes are delivered on each clock. +// +// In 2:1 mode the DRAM burst is delivered on two fabric clocks. For +// an 8 byte bus, 32 bytes are delivered with each fabric clock. +// +// For the most part, this block does not use phy_rddata_en. It delivers +// its results and depends on downstream logic to know when its valid. +// +// phy_rddata_en is used for the PRBS compares when the last line of data +// needs to be carried over to a subsequent line. +// +// Since we work on a byte at a time, the comparison only works on +// one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to +// select the proper 8 bytes out of both the phy_rddata and prob_o streams. +// +// Comparisons are computed for "zero" or "rise" data, and "oneeighty" or +// "fall" data. The "oneeighty" compares assumes the rising edge clock is +// landing in the oneeighty data. +// +// For the simple data, we don't need to worry about first byte or last +// byte conditions because the sampled data is taken from the middle +// of a 4 burst segment. +// +// The complex (or PRBS) data starts and stops. And we need to be +// careful about ignoring compares that might be using invalid latched +// data. The PRBS generator provides prbs_ignore_first_byte and +// prbs_ignore_last_bytes. The comparison block is procedural. It +// first compares across the entire line, then comes back and overwrites +// any byte compare results as indicated by the _ignore_ wires. +// +// The compares generate an eight bit vector, one for each byte. The +// final step is to bitwise AND this eight bit vector. We end up +// with two sets of two bits. Zero and oneeighty for the fixed pattern +// and the prbs. +// +// complex_oclkdelay_calib_start is used to +// select between the fixed and prbs compares. The final output +// is a two bit match bus. +// +// There is a deprecated feature to mask the compare for any byte. +// +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ocd_data # + (parameter TCQ = 100, + parameter nCK_PER_CLK = 4, + parameter DQS_CNT_WIDTH = 3, + parameter DQ_WIDTH = 64) + (/*AUTOARG*/ + // Outputs + match, + // Inputs + clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o, + oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes, + phy_rddata_en_1 + ); + + localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000; + + input clk; + input rst; + + input complex_oclkdelay_calib_start; + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata; + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + + reg [DQ_WIDTH-1:0] word, word_shifted; + + reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r; + always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns; + always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r; + always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1; + always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns; + + input prbs_ignore_first_byte, prbs_ignore_last_bytes; + reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r; + always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte; + always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes; + + input phy_rddata_en_1; + reg [7:0] last_byte_r; + wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r; + + wire [7:0] last_byte_ns; + generate if (nCK_PER_CLK == 4) begin + assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r; + end else begin + assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r; + end endgenerate + always @(posedge clk) last_byte_r <= #TCQ last_byte_ns; + + reg second_half_ns, second_half_r; + always @(posedge clk) second_half_r <= #TCQ second_half_ns; + always @(*) begin + second_half_ns = second_half_r; + if (rst) second_half_ns = 1'b0; + else second_half_ns = phy_rddata_en_1 ^ second_half_r; + end + + reg [7:0] comp0, comp180, prbs0, prbs180; + + integer ii; + always @(*) begin + comp0 = 8'hff; + comp180 = 8'hff; + prbs0 = 8'hff; + prbs180 = 8'hff; + data_bytes_ns = 64'b0; + prbs_bytes_ns = 64'b0; + for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) + begin + word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH]; + word_shifted = word >> oclkdelay_calib_cnt*8; + data_bytes_ns[ii*8+:8] = word_shifted[7:0]; + + word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH]; + word_shifted = word >> oclkdelay_calib_cnt*8; + prbs_bytes_ns[ii*8+:8] = word_shifted[7:0]; + + comp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00); + comp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff); + + prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8]; + end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1) + prbs180[0] = last_byte_r == prbs_bytes_r[7:0]; + for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1) + prbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8]; + if (nCK_PER_CLK == 4) begin + if (prbs_ignore_last_bytes_r) begin + prbs0[7:6] = 2'b11; + prbs180[7] = 1'b1; + end + if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; + end else begin + if (second_half_r) begin + if (prbs_ignore_last_bytes_r) begin + prbs0[3:2] = 2'b11; + prbs180[3] = 1'b1; + end + end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1; + end // else: !if(nCK_PER_CLK == 4) + end // always @ (*) + + wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK; + wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK; + wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK; + wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK; + + output [1:0] match; + assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked}; + + +endmodule // mig_7series_v4_2_ddr_phy_ocd_data + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v new file mode 100644 index 0000000..c6ed70e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v @@ -0,0 +1,232 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_edge.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Detects and stores edges as the test pattern is scanned via +// manipulating the phaser out stage 3 taps. +// +// Scanning always proceeds from the left to the right. For more +// on the scanning algorithm, see the _po_cntlr block. +// +// Four scan results are reported. The edges at fuzz2zero, +// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge +// has a 6 bit stg3 tap value and a valid bit. The valid bits +// are reset before the scan starts. +// +// Once reset_scan is set low, this block waits for the first +// samp_done while scanning_right. This marks the left end +// of the scan, and initializes prev_samp_r with samp_result and +// sets the prev_samp_r valid bit to one. +// +// At each subesquent samp_done, the previous samp is compared +// to the current samp_result. The case statement details how +// edges are identified. +// +// Original design assumed fuzz between valid regions. Design +// has been updated to tolerate transitions from zero to oneeight +// and vice-versa without fuzz in between. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ocd_edge # + (parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero, + oneeighty2fuzz, fuzz2oneeighty, + // Inputs + clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right, + samp_result, stg3 + ); + + + localparam [1:0] NULL = 2'b11, + FUZZ = 2'b00, + ONEEIGHTY = 2'b10, + ZERO = 2'b01; + + input clk; + + input samp_done; + input phy_rddata_en_2; + wire samp_valid = samp_done && phy_rddata_en_2; + + input reset_scan; + + input scanning_right; + + reg prev_samp_valid_ns, prev_samp_valid_r; + always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns; + always @(*) begin + prev_samp_valid_ns = prev_samp_valid_r; + if (reset_scan) prev_samp_valid_ns = 1'b0; + else if (samp_valid) prev_samp_valid_ns = 1'b1; + end + + input [1:0] samp_result; + + reg [1:0] prev_samp_ns, prev_samp_r; + always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns; + always @(*) + if (samp_valid) prev_samp_ns = samp_result; + else prev_samp_ns = prev_samp_r; + + reg scan_right_ns, scan_right_r; + always @(posedge clk) scan_right_r <= #TCQ scan_right_ns; + output scan_right; + assign scan_right = scan_right_r; + + input [5:0] stg3; + + reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r; + always @(posedge clk) z2f_r <= #TCQ z2f_ns; + always @(posedge clk) f2z_r <= #TCQ f2z_ns; + always @(posedge clk) o2f_r <= #TCQ o2f_ns; + always @(posedge clk) f2o_r <= #TCQ f2o_ns; + + output z2f, f2z, o2f, f2o; + assign z2f = z2f_r; + assign f2z = f2z_r; + assign o2f = o2f_r; + assign f2o = f2o_r; + + reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r, + oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r; + always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns; + always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns; + always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns; + always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns; + + output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty; + assign zero2fuzz = zero2fuzz_r; + assign fuzz2zero = fuzz2zero_r; + assign oneeighty2fuzz = oneeighty2fuzz_r; + assign fuzz2oneeighty = fuzz2oneeighty_r; + + always @(*) begin + z2f_ns = z2f_r; + f2z_ns = f2z_r; + o2f_ns = o2f_r; + f2o_ns = f2o_r; + zero2fuzz_ns = zero2fuzz_r; + fuzz2zero_ns = fuzz2zero_r; + oneeighty2fuzz_ns = oneeighty2fuzz_r; + fuzz2oneeighty_ns = fuzz2oneeighty_r; + scan_right_ns = 1'b0; + + if (reset_scan) begin + z2f_ns = 1'b0; + f2z_ns = 1'b0; + o2f_ns = 1'b0; + f2o_ns = 1'b0; + end + else if (samp_valid && prev_samp_valid_r) + case (prev_samp_r) + FUZZ : + if (scanning_right) begin + if (samp_result == ZERO) begin + fuzz2zero_ns = stg3; + f2z_ns = 1'b1; + end + if (samp_result == ONEEIGHTY) begin + fuzz2oneeighty_ns = stg3; + f2o_ns = 1'b1; + end + end + ZERO : begin + if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right; + if (scanning_right) begin + if (samp_result == FUZZ) begin + zero2fuzz_ns = stg3 - 6'b1; + z2f_ns = 1'b1; + end + if (samp_result == ONEEIGHTY) begin + zero2fuzz_ns = stg3 - 6'b1; + z2f_ns = 1'b1; + fuzz2oneeighty_ns = stg3; + f2o_ns = 1'b1; + end + end + end + ONEEIGHTY : + if (scanning_right) begin + if (samp_result == FUZZ) begin + oneeighty2fuzz_ns = stg3 - 6'b1; + o2f_ns = 1'b1; + end + if (samp_result == ZERO) + if (f2o_r) begin + oneeighty2fuzz_ns = stg3 - 6'b1; + o2f_ns = 1'b1; + end else begin + fuzz2zero_ns = stg3; + f2z_ns = 1'b1; + end + + end // if (scanning_right) +// NULL : // Should never happen + endcase + end + +endmodule // mig_7series_v4_2_ddr_phy_ocd_edge + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v new file mode 100644 index 0000000..a54b770 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v @@ -0,0 +1,599 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_oclkdelay_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 +// delay +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ocd_lim # + (parameter TAPCNTRWIDTH = 7, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 9, + parameter TCQ = 100, + parameter TAPSPERKCLK = 56, + parameter TDQSS_DEGREES = 60, + parameter BYPASS_COMPLEX_OCAL = "FALSE") + (/*AUTOARG*/ + // Outputs + lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right, + lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done, + lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim, + // Inputs + clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead, + poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead, + poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt, + simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done, + prech_done, oclkdelay_calib_cnt + ); + + function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, + input [TAPCNTRWIDTH-1:0] b, + input integer base); + begin + mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b; + end + endfunction // mod_sub + + input clk; + input rst; + + input lim_start; + input po_rdy; + input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead; + input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail; + input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead; + input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail; + input [5:0] oclkdelay_init_val; + input [5:0] wl_po_fine_cnt; + input [5:0] simp_stg3_final_sel; + input oclkdelay_calib_done; + input poc2lim_detect_done; + input prech_done; + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + + + output lim2init_write_request; + output lim2init_prech_req; + output lim2poc_rdy; + output lim2poc_ktap_right; // I think this can be defaulted. + output lim2stg3_inc; + output lim2stg3_dec; + output lim2stg2_inc; + output lim2stg2_dec; + output lim_done; + output [5:0] lim2ocal_stg3_right_lim; + output [5:0] lim2ocal_stg3_left_lim; + output [255:0] dbg_ocd_lim; + + // Stage 3 taps can move an additional + or - 60 degrees from the write level position + // Convert 60 degrees to MMCM taps. 360/60=6. + //localparam real DIV_FACTOR = 360/TDQSS_DEGREES; + //localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; + localparam DIV_FACTOR = 360/TDQSS_DEGREES; + localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR; + localparam WAIT_CNT = 15; + + localparam IDLE = 14'b00_0000_0000_0001; + localparam INIT = 14'b00_0000_0000_0010; + localparam WAIT_WR_REQ = 14'b00_0000_0000_0100; + localparam WAIT_POC_DONE = 14'b00_0000_0000_1000; + localparam WAIT_STG3 = 14'b00_0000_0001_0000; + localparam STAGE3_INC = 14'b00_0000_0010_0000; + localparam STAGE3_DEC = 14'b00_0000_0100_0000; + localparam STAGE2_INC = 14'b00_0000_1000_0000; + localparam STAGE2_DEC = 14'b00_0001_0000_0000; + localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000; + localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000; + localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000; + localparam PRECH_REQUEST = 14'b01_0000_0000_0000; + localparam LIMIT_DONE = 14'b10_0000_0000_0000; + +// Flip-flops + reg [5:0] stg3_init_val; + reg [13:0] lim_state; + reg lim_start_r; + reg ktap_right_r; + reg write_request_r; + reg prech_req_r; + reg poc_ready_r; + reg wait_cnt_en_r; + reg wait_cnt_done; + reg [3:0] wait_cnt_r; + reg [5:0] stg3_tap_cnt; + reg [5:0] stg2_tap_cnt; + reg [5:0] stg3_left_lim; + reg [5:0] stg3_right_lim; + reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim; + reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim; + reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim; + reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim; + reg [5:0] stg3_dec_val; + reg [5:0] stg3_inc_val; + reg detect_done_r; + reg stg3_dec_r; + reg stg2_inc_r; + reg stg3_inc2init_val_r; + reg stg3_inc2init_val_r1; + reg stg3_dec2init_val_r; + reg stg3_dec2init_val_r1; + reg stg3_dec_req_r; + reg stg3_inc_req_r; + reg stg2_dec_req_r; + reg stg2_inc_req_r; + reg stg3_init_dec_r; + reg [TAPCNTRWIDTH:0] mmcm_current; + reg [TAPCNTRWIDTH:0] mmcm_init_trail; + reg [TAPCNTRWIDTH:0] mmcm_init_lead; + reg done_r; + + reg [13:0] lim_nxt_state; + reg ktap_right; + reg write_request; + reg prech_req; + reg poc_ready; + reg stg3_dec; + reg stg2_inc; + reg stg3_inc2init_val; + reg stg3_dec2init_val; + reg stg3_dec_req; + reg stg3_inc_req; + reg stg2_dec_req; + reg stg2_inc_req; + reg stg3_init_dec; + reg done; + reg oclkdelay_calib_done_r; + + wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK); + wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK); + + /***************************************************************************/ + // Debug signals + /***************************************************************************/ + + assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0]; + assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0]; + assign dbg_ocd_lim[255:108] = 'd0; + + + + + assign lim2init_write_request = write_request_r; + assign lim2init_prech_req = prech_req_r; + assign lim2poc_ktap_right = ktap_right_r; + assign lim2poc_rdy = poc_ready_r; + assign lim2ocal_stg3_left_lim = stg3_left_lim; + assign lim2ocal_stg3_right_lim = stg3_right_lim; + assign lim2stg3_dec = stg3_dec_req_r; + assign lim2stg3_inc = stg3_inc_req_r; + assign lim2stg2_dec = stg2_dec_req_r; + assign lim2stg2_inc = stg2_inc_req_r; + assign lim_done = done_r; + + +/**************************Wait Counter Start*********************************/ +// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3 +// To avoid DQS toggling when stage2 and 3 taps are moving + always @(posedge clk) begin + if ((lim_state == WAIT_WR_REQ) || + (lim_state == WAIT_STG3) || + (lim_state == INIT)) + wait_cnt_en_r <= #TCQ 1'b1; + else + wait_cnt_en_r <= #TCQ 1'b0; + end + +// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3 +// To avoid DQS toggling when stage2 and 3 taps are moving + always @(posedge clk) begin + if (!wait_cnt_en_r) begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b0; + end else begin + if (wait_cnt_r != WAIT_CNT - 1) begin + wait_cnt_r <= #TCQ wait_cnt_r + 1; + wait_cnt_done <= #TCQ 1'b0; + end else begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b1; + end + end + end +/**************************Wait Counter End***********************************/ + +// Flip-flops + + always @(posedge clk) begin + if (rst) + oclkdelay_calib_done_r <= #TCQ 1'b0; + else + oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done; + end + + always @(posedge clk) begin + if (rst) + stg3_init_val <= #TCQ oclkdelay_init_val; + else if (oclkdelay_calib_done) + stg3_init_val <= #TCQ simp_stg3_final_sel; + else + stg3_init_val <= #TCQ oclkdelay_init_val; + end + + always @(posedge clk) begin + if (rst) begin + lim_state <= #TCQ IDLE; + lim_start_r <= #TCQ 1'b0; + ktap_right_r <= #TCQ 1'b0; + write_request_r <= #TCQ 1'b0; + prech_req_r <= #TCQ 1'b0; + poc_ready_r <= #TCQ 1'b0; + detect_done_r <= #TCQ 1'b0; + stg3_dec_r <= #TCQ 1'b0; + stg2_inc_r <= #TCQ 1'b0; + stg3_inc2init_val_r <= #TCQ 1'b0; + stg3_inc2init_val_r1<= #TCQ 1'b0; + stg3_dec2init_val_r <= #TCQ 1'b0; + stg3_dec2init_val_r1<= #TCQ 1'b0; + stg3_dec_req_r <= #TCQ 1'b0; + stg3_inc_req_r <= #TCQ 1'b0; + stg2_dec_req_r <= #TCQ 1'b0; + stg2_inc_req_r <= #TCQ 1'b0; + done_r <= #TCQ 1'b0; + stg3_dec_val <= #TCQ 'd0; + stg3_inc_val <= #TCQ 'd0; + stg3_init_dec_r <= #TCQ 1'b0; + end else begin + lim_state <= #TCQ lim_nxt_state; + lim_start_r <= #TCQ lim_start; + ktap_right_r <= #TCQ ktap_right; + write_request_r <= #TCQ write_request; + prech_req_r <= #TCQ prech_req; + poc_ready_r <= #TCQ poc_ready; + detect_done_r <= #TCQ poc2lim_detect_done; + stg3_dec_r <= #TCQ stg3_dec; + stg2_inc_r <= #TCQ stg2_inc; + stg3_inc2init_val_r <= #TCQ stg3_inc2init_val; + stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r; + stg3_dec2init_val_r <= #TCQ stg3_dec2init_val; + stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r; + stg3_dec_req_r <= #TCQ stg3_dec_req; + stg3_inc_req_r <= #TCQ stg3_inc_req; + stg2_dec_req_r <= #TCQ stg2_dec_req; + stg2_inc_req_r <= #TCQ stg2_inc_req; + stg3_init_dec_r <= #TCQ stg3_init_dec; + done_r <= #TCQ done; + if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2)) + stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2); + else + stg3_dec_val <= #TCQ 'd0; + if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2)) + stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2); + else + stg3_inc_val <= #TCQ 'd63; + end + end + +// Keeping track of stage 3 tap count + always @(posedge clk) begin + if (rst) + stg3_tap_cnt <= #TCQ stg3_init_val; + else if ((lim_state == IDLE) || (lim_state == INIT)) + stg3_tap_cnt <= #TCQ stg3_init_val; + else if (lim_state == STAGE3_INC) + stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1; + else if (lim_state == STAGE3_DEC) + stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1; + end + +// Keeping track of stage 2 tap count + always @(posedge clk) begin + if (rst) + stg2_tap_cnt <= #TCQ 'd0; + else if ((lim_state == IDLE) || (lim_state == INIT)) + stg2_tap_cnt <= #TCQ wl_po_fine_cnt; + else if (lim_state == STAGE2_INC) + stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1; + else if (lim_state == STAGE2_DEC) + stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1; + end + +// Keeping track of MMCM tap count + always @(posedge clk) begin + if (rst) begin + mmcm_init_trail <= #TCQ 'd0; + mmcm_init_lead <= #TCQ 'd0; + end else if (poc2lim_detect_done && !detect_done_r) begin + if (stg3_tap_cnt == stg3_dec_val) + mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail; + if (stg3_tap_cnt == stg3_inc_val) + mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead; + end + end + + always @(posedge clk) begin + if (rst) begin + mmcm_current <= #TCQ 'd0; + end else if (stg3_dec_r) begin + if (stg3_tap_cnt == stg3_dec_val) + mmcm_current <= #TCQ mmcm_init_trail; + else + mmcm_current <= #TCQ poc2lim_rise_align_taps_lead; + end else begin + if (stg3_tap_cnt == stg3_inc_val) + mmcm_current <= #TCQ mmcm_init_lead; + else + mmcm_current <= #TCQ poc2lim_rise_align_taps_trail; + end + end + +// Record Stage3 Left Limit + always @(posedge clk) begin + if (rst) begin + stg3_left_lim <= #TCQ 'd0; + simp_stg3_left_lim <= #TCQ 'd0; + cmplx_stg3_left_lim <= #TCQ 'd0; + end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin + stg3_left_lim <= #TCQ stg3_tap_cnt; + if (oclkdelay_calib_done) + cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + else + simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + end else if (lim_start && !lim_start_r) + stg3_left_lim <= #TCQ 'd0; + end + +// Record Stage3 Right Limit + always @(posedge clk) begin + if (rst) begin + stg3_right_lim <= #TCQ 'd0; + cmplx_stg3_right_lim <= #TCQ 'd0; + simp_stg3_right_lim <= #TCQ 'd0; + end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin + stg3_right_lim <= #TCQ stg3_tap_cnt; + if (oclkdelay_calib_done) + cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + else + simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt; + end else if (lim_start && !lim_start_r) + stg3_right_lim <= #TCQ 'd0; + end + + always @(*) begin + lim_nxt_state = lim_state; + ktap_right = ktap_right_r; + write_request = write_request_r; + prech_req = prech_req_r; + poc_ready = poc_ready_r; + stg3_dec = stg3_dec_r; + stg2_inc = stg2_inc_r; + stg3_inc2init_val = stg3_inc2init_val_r; + stg3_dec2init_val = stg3_dec2init_val_r; + stg3_dec_req = stg3_dec_req_r; + stg3_inc_req = stg3_inc_req_r; + stg2_inc_req = stg2_inc_req_r; + stg2_dec_req = stg2_dec_req_r; + stg3_init_dec = stg3_init_dec_r; + done = done_r; + + + case(lim_state) + IDLE: begin + if (lim_start && !lim_start_r) begin + lim_nxt_state = INIT; + stg3_dec = 1'b1; + stg2_inc = 1'b1; + stg3_init_dec = 1'b1; + done = 1'b0; + end + //New start of limit module for complex oclkdelay calib + else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin + done = 1'b0; + end + end + INIT: begin + ktap_right = 1'b1; + // Initial stage 2 increment to 63 for left limit + if (wait_cnt_done) + lim_nxt_state = STAGE2_TAP_CHK; + end + // Wait for DQS to toggle before asserting poc_ready + WAIT_WR_REQ: begin + write_request = 1'b1; + if (wait_cnt_done) begin + poc_ready = 1'b1; + lim_nxt_state = WAIT_POC_DONE; + end + end + // Wait for POC detect done signal + WAIT_POC_DONE: begin + if (poc2lim_detect_done) begin + write_request = 1'b0; + poc_ready = 1'b0; + lim_nxt_state = WAIT_STG3; + end + end + // Wait for DQS to stop toggling before stage3 inc/dec + WAIT_STG3: begin + if (wait_cnt_done) begin + if (stg3_dec_r) begin + // Check for Stage 3 underflow and MMCM tap limit + if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS)) + lim_nxt_state = STAGE3_DEC; + else begin + stg3_dec = 1'b0; + stg3_inc2init_val = 1'b1; + lim_nxt_state = STAGE3_INC; + end + end else begin // Stage 3 being incremented + // Check for Stage 3 overflow and MMCM tap limit + if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS)) + lim_nxt_state = STAGE3_INC; + else begin + stg3_dec2init_val = 1'b1; + lim_nxt_state = STAGE3_DEC; + end + end + end + end + STAGE3_INC: begin + stg3_inc_req = 1'b1; + lim_nxt_state = STG3_INCDEC_WAIT; + end + STAGE3_DEC: begin + stg3_dec_req = 1'b1; + lim_nxt_state = STG3_INCDEC_WAIT; + end + // Wait for stage3 inc/dec to complete (po_rdy) + STG3_INCDEC_WAIT: begin + stg3_dec_req = 1'b0; + stg3_inc_req = 1'b0; + if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin + if (stg3_init_dec_r) begin + // Initial decrement of stage 3 + if (stg3_tap_cnt > stg3_dec_val) + lim_nxt_state = STAGE3_DEC; + else begin + lim_nxt_state = WAIT_WR_REQ; + stg3_init_dec = 1'b0; + end + end else if (stg3_dec2init_val_r) begin + if (stg3_tap_cnt > stg3_init_val) + lim_nxt_state = STAGE3_DEC; + else + lim_nxt_state = STAGE2_TAP_CHK; + end else if (stg3_inc2init_val_r) begin + if (stg3_tap_cnt < stg3_inc_val) + lim_nxt_state = STAGE3_INC; + else + lim_nxt_state = STAGE2_TAP_CHK; + end else begin + lim_nxt_state = WAIT_WR_REQ; + end + end + end + // Check for overflow and underflow of stage2 taps + STAGE2_TAP_CHK: begin + if (stg3_dec2init_val_r) begin + // Increment stage 2 to write level tap value at the end of limit detection + if (stg2_tap_cnt < wl_po_fine_cnt) + lim_nxt_state = STAGE2_INC; + else begin + lim_nxt_state = PRECH_REQUEST; + end + end else if (stg3_inc2init_val_r) begin + // Decrement stage 2 to '0' to determine right limit + if (stg2_tap_cnt > 'd0) + lim_nxt_state = STAGE2_DEC; + else begin + lim_nxt_state = PRECH_REQUEST; + stg3_inc2init_val = 1'b0; + end + end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin + // Initial increment to 63 + lim_nxt_state = STAGE2_INC; + end else begin + lim_nxt_state = STG3_INCDEC_WAIT; + stg2_inc = 1'b0; + end + end + STAGE2_INC: begin + stg2_inc_req = 1'b1; + lim_nxt_state = STG2_INCDEC_WAIT; + end + STAGE2_DEC: begin + stg2_dec_req = 1'b1; + lim_nxt_state = STG2_INCDEC_WAIT; + end + // Wait for stage3 inc/dec to complete (po_rdy) + STG2_INCDEC_WAIT: begin + stg2_inc_req = 1'b0; + stg2_dec_req = 1'b0; + if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy) + lim_nxt_state = STAGE2_TAP_CHK; + end + PRECH_REQUEST: begin + prech_req = 1'b1; + if (prech_done) begin + prech_req = 1'b0; + if (stg3_dec2init_val_r) + lim_nxt_state = LIMIT_DONE; + else + lim_nxt_state = WAIT_WR_REQ; + end + end + LIMIT_DONE: begin + done = 1'b1; + ktap_right = 1'b0; + stg3_dec2init_val = 1'b0; + lim_nxt_state = IDLE; + end + default: begin + lim_nxt_state = IDLE; + end + endcase + end + + +endmodule //mig_7_series_v4_0_ddr_phy_ocd_lim + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v new file mode 100644 index 0000000..1d55026 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v @@ -0,0 +1,208 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_mux.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: The limit block and the _po_cntlr block both manipulate +// the phaser out and the POC. This block muxes those commands +// together, and encapsulates logic required for meeting phaser +// setup and wait times. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ocd_mux # + (parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy, + po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel, + po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req, + // Inputs + clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right, + lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec, + lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec, + ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt, + oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + localparam PO_WAIT = 15; + localparam POW_WIDTH = clogb2(PO_WAIT); + localparam ONE = 1; + localparam TWO = 2; + + input clk; + input rst; + + input ocd_ktap_right, ocd_ktap_left; + input lim2poc_ktap_right; + output ktap_at_left_edge, ktap_at_right_edge; + assign ktap_at_left_edge = ocd_ktap_left; + assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right; + + input lim2poc_rdy; + input ocd_edge_detect_rdy; + output mmcm_edge_detect_rdy; + assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy; + + // po_stg3_incdec and po_en_stg3 are deprecated and should be removed. + output po_stg3_incdec; + output po_en_stg3; + assign po_stg3_incdec = 1'b0; + assign po_en_stg3 = 1'b0; + + + reg [1:0] po_setup_ns, po_setup_r; + always @(posedge clk) po_setup_r <= #TCQ po_setup_ns; + + input lim2stg2_inc; + input lim2stg2_dec; + + input lim2stg3_inc; + input lim2stg3_dec; + + input ocd2stg2_inc; + input ocd2stg2_dec; + input ocd_cntlr2stg2_dec; + + input ocd2stg3_inc; + input ocd2stg3_dec; + + wire setup_po = + lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec || + ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec; + + always @(*) begin + po_setup_ns = po_setup_r; + if (rst) po_setup_ns = 2'b00; + else if (setup_po) po_setup_ns = 2'b11; + else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01; + end + + reg po_en_stg23_r; + wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01; + always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns; + output po_en_stg23; + assign po_en_stg23 = po_en_stg23_r; + + wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec; + + reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns; + reg po_stg23_sel_r; + // Reset to zero at the end. Makes adjust stg2 at end of centering + // get the correct value of po_counter_read_val. + wire po_stg23_sel_ns = ~rst && (setup_po + ? sel_stg3 + ? 1'b1 + : 1'b0 + : po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0])); + always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns; + output po_stg23_sel; + assign po_stg23_sel = po_stg23_sel_r; + + wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc; + + reg po_stg23_incdec_r; + wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r); + always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns; + output po_stg23_incdec; + assign po_stg23_incdec = po_stg23_incdec_r; + + + always @(posedge clk) po_wait_r <= #TCQ po_wait_ns; + always @(*) begin + po_wait_ns = po_wait_r; + if (rst) po_wait_ns = {POW_WIDTH{1'b0}}; + else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0]; + else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0]; + end + + wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns); + reg po_rdy_r; + always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns; + + output po_rdy; + assign po_rdy = po_rdy_r; + + input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6; + output [5:0] wl_po_fine_cnt_sel; + assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0]; + + input lim2init_prech_req; + input ocd_prech_req; + output oclk_prech_req; + assign oclk_prech_req = ocd_prech_req || lim2init_prech_req; + +endmodule // mig_7series_v4_2_ddr_phy_ocd_mux + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v new file mode 100644 index 0000000..62f4ea5 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v @@ -0,0 +1,595 @@ + +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_po_cntlr.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Manipulates phaser out stg2f and stg3 on behalf of +// scan and DQS centering. +// +// Maintains a shadow of the phaser out stg2f and stg3 tap settings. +// The stg3 shadow is 6 bits, just like the phaser out. stg2f is +// 8 bits. This allows the po_cntlr to track how far past the stg2f +// saturation points we have gone when stepping to the limits of stg3. +// This way we're can stay in sync when we step back from the saturation +// limits. +// +// Looks at the edge values and determines which case has been +// detected by the scan. Uses the results to drive the centering. +// +// Main state machine waits until it sees reset_scan go to zero. While +// waiting it is writing the initialzation values to the stg2 and stg3 +// shadows. When reset_scan goes low, taps_set is pulsed. This +// tells the sampling block to begin sampling. When the sampling +// block has finished sampling this setting of the phaser out taps, +// is signals by setting samp_done. When the main state machine +// sees samp_done it sets the next value in the phaser out and +// waits for the phaser out to be ready before beginning the next +// sample. +// +// Turns out phy_init is sensitive to the length of the ocal_num_samples_done +// pulse. Something like a precharge and activate time. Added feature +// to resume_wait to wait at least 32 cycles between assertion and +// subsequent deassertion of ocal_num_samples_done. +// +// Also turns out phy_init needs help to get into consistent +// starting state for complex cal. This can be done by preseting +// ocal_num_samples_done to one. Then waiting for 32 fabric clocks, +// turn off _done and then assert _resume. +// +// Scanning algorithm. +// +// Phaser manipulation algoritm. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ocd_po_cntlr # + (parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter nCK_PER_CLK = 4, + parameter SAMPLES = 128, + parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start, + oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc, + ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final, + cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets, + scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy, + taps_set, use_noise_window, ocal_scan_win_not_found, + // Inputs + clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim, + lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start, + po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done, + mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz, + fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o, + scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + input clk; + input rst; + + input reset_scan; + reg scan_done_r; + output scan_done; + assign scan_done = scan_done_r; + output [5:0] simp_stg3_final_sel; + + reg cmplx_samples_done_ns, cmplx_samples_done_r; + always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns; + output ocal_num_samples_done_r; + assign ocal_num_samples_done_r = cmplx_samples_done_r; + + // Write Level signals during OCLKDELAY calibration + input [5:0] oclkdelay_init_val; + input [5:0] lim2ocal_stg3_right_lim; + input [5:0] lim2ocal_stg3_left_lim; + + input complex_oclkdelay_calib_start; + + reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r; + always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns; + output oclkdelay_center_calib_start; + assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r; + + reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r; + always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns; + output oclkdelay_center_calib_done; + assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r; + + reg oclk_center_write_resume_ns, oclk_center_write_resume_r; + always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns; + output oclk_center_write_resume; + assign oclk_center_write_resume = oclk_center_write_resume_r; + + reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r; + output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec; + assign ocd2stg2_inc = ocd2stg2_inc_r; + assign ocd2stg2_dec = ocd2stg2_dec_r; + assign ocd2stg3_inc = ocd2stg3_inc_r; + assign ocd2stg3_dec = ocd2stg3_dec_r; + + // Remember, two stage 2 steps for every stg 3 step. And we need a sign bit. + reg [8:0] stg2_ns, stg2_r; + always @(posedge clk) stg2_r <= #TCQ stg2_ns; + + reg [5:0] stg3_ns, stg3_r; + always @(posedge clk) stg3_r <= #TCQ stg3_ns; + output [5:0] stg3; + assign stg3 = stg3_r; + + input [5:0] wl_po_fine_cnt_sel; + + input [8:0] po_counter_read_val; + reg [5:0] po_counter_read_val_r; + always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0]; + + reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r; + always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns; + always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns; + output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; + assign simp_stg3_final = simp_stg3_final_r; + assign cmplx_stg3_final = cmplx_stg3_final_r; + + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6; + assign simp_stg3_final_sel = simp_stg3_final_shft[5:0]; + wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val; + + wire signed [8:0] stg2_steps = stg3_r > stg3_init + ? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)}) + : 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)}); + + wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps; + reg signed [8:0] stg2_target_r; + always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns; + + reg [5:0] stg2_final_ns, stg2_final_r; + always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns; + always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1 + ? 6'd0 + : stg2_target_r > 9'd63 + ? 6'd63 + : stg2_target_r[5:0]; + + wire final_stg2_inc = stg2_final_r > po_counter_read_val_r; + wire final_stg2_dec = stg2_final_r < po_counter_read_val_r; + + wire left_lim = stg3_r == lim2ocal_stg3_left_lim; + wire right_lim = stg3_r == lim2ocal_stg3_right_lim; + + reg [1:0] ninety_offsets_ns, ninety_offsets_r; + always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns; + output [1:0] ninety_offsets; + assign ninety_offsets = ninety_offsets_r; + + reg scanning_right_ns, scanning_right_r; + always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns; + output scanning_right; + assign scanning_right = scanning_right_r; + + reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r; + always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns; + always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns; + output ocd_ktap_left, ocd_ktap_right; + assign ocd_ktap_left = ocd_ktap_left_r; + assign ocd_ktap_right = ocd_ktap_right_r; + + reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r; + always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns; + output ocd_edge_detect_rdy; + assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r; + + input mmcm_edge_detect_done; + input mmcm_lbclk_edge_aligned; + input poc_backup; + reg poc_backup_ns, poc_backup_r; + always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns; + + reg taps_set_r; + output taps_set; + assign taps_set = taps_set_r; + + input phy_rddata_en_3; + + input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty; + input z2f, f2z, o2f, f2o; + + wire zero = f2z && z2f; + wire noise = z2f && f2o; + wire oneeighty = f2o && o2f; + + reg win_not_found; + reg [1:0] ninety_offsets_final_ns, ninety_offsets_final_r; + always @(posedge clk) ninety_offsets_final_r <= #TCQ ninety_offsets_final_ns; + reg [5:0] left, right, current_edge; + always @(*) begin + left = lim2ocal_stg3_left_lim; + right = lim2ocal_stg3_right_lim; + ninety_offsets_final_ns = 2'd0; + win_not_found = 1'b0; + if (zero) begin + left = fuzz2zero; + right = zero2fuzz; + end + else if (noise) begin + left = zero2fuzz; + right = fuzz2oneeighty; + ninety_offsets_final_ns = 2'd1; + end + else if (oneeighty) begin + left = fuzz2oneeighty; + right = oneeighty2fuzz; + ninety_offsets_final_ns = 2'd2; + end + else if (z2f) begin + right = zero2fuzz; + end + else if (f2o) begin + left = fuzz2oneeighty; + ninety_offsets_final_ns = 2'd2; + end + else if (f2z) begin + left = fuzz2zero; + end + else win_not_found = 1'b1; + current_edge = ocd_ktap_left_r ? left : right; + end // always @ begin + + output use_noise_window; + assign use_noise_window = ninety_offsets == 2'd1; + + reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r; + always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns; + output ocal_scan_win_not_found; + assign ocal_scan_win_not_found = ocal_scan_win_not_found_r; + + wire inc_po_ns = current_edge > stg3_r; + wire dec_po_ns = current_edge < stg3_r; + reg inc_po_r, dec_po_r; + always @(posedge clk) inc_po_r <= #TCQ inc_po_ns; + always @(posedge clk) dec_po_r <= #TCQ dec_po_ns; + + input scan_right; + + wire left_stop = left_lim || scan_right; + wire right_stop = right_lim || o2f; + + // POC samples every other fabric clock. + localparam POC_SAMPLE_CLEAR_WAIT = SAMPLES * 2 > 15 ? SAMPLES * 2 : 15; + localparam MAX_RESUME_WAIT = POC_SAMPLE_CLEAR_WAIT > 31 ? POC_SAMPLE_CLEAR_WAIT : 31; + localparam RESUME_WAIT_WIDTH = clogb2(MAX_RESUME_WAIT + 1); + + reg [RESUME_WAIT_WIDTH-1:0] resume_wait_ns, resume_wait_r; + always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns; + + wire resume_wait = |resume_wait_r; + + reg po_done_ns, po_done_r; + always @(posedge clk) po_done_r <= #TCQ po_done_ns; + + input samp_done; + + input po_rdy; + + reg up_ns, up_r; + always @(posedge clk) up_r <= #TCQ up_ns; + + reg [1:0] two_ns, two_r; + always @(posedge clk) two_r <= #TCQ two_ns; + + +/* wire stg2_zero = ~|stg2_r; + wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0 + : stg2_r > 9'd63 + ? 9'd63 + : stg2_r; */ + + reg [3:0] sm_ns, sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + + reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r; + always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns; + always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3 + ? ~phy_rddata_en_3_second_r + : phy_rddata_en_3_second_r); + wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3; + + reg po_center_wait; + reg po_slew; + reg po_finish_scan; + + always @(*) begin + + // Default next state assignments. + + cmplx_samples_done_ns = cmplx_samples_done_r; + cmplx_stg3_final_ns = cmplx_stg3_final_r; + scanning_right_ns = scanning_right_r; + ninety_offsets_ns = ninety_offsets_r; + ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r; + ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r; + ocd_ktap_left_ns = ocd_ktap_left_r; + ocd_ktap_right_ns = ocd_ktap_right_r; + ocd2stg2_inc_r = 1'b0; + ocd2stg2_dec_r = 1'b0; + ocd2stg3_inc_r = 1'b0; + ocd2stg3_dec_r = 1'b0; + oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r; + oclkdelay_center_calib_done_ns = 1'b0; + oclk_center_write_resume_ns = oclk_center_write_resume_r; + po_center_wait = 1'b0; + po_done_ns = po_done_r; + po_finish_scan = 1'b0; + po_slew = 1'b0; + poc_backup_ns = poc_backup_r; + scan_done_r = 1'b0; + simp_stg3_final_ns = simp_stg3_final_r; + sm_ns = sm_r; + taps_set_r = 1'b0; + up_ns = up_r; + stg2_ns = stg2_r; + stg3_ns = stg3_r; + two_ns = two_r; + resume_wait_ns = resume_wait_r; + + if (rst == 1'b1) begin + + // RESET next states + cmplx_samples_done_ns = 1'b0; + ocal_scan_win_not_found_ns = 1'b0; + ocd_ktap_left_ns = 1'b0; + ocd_ktap_right_ns = 1'b0; + ocd_edge_detect_rdy_ns = 1'b0; + oclk_center_write_resume_ns = 1'b0; + oclkdelay_center_calib_start_ns = 1'b0; + po_done_ns = 1'b1; + resume_wait_ns = 5'd0; + sm_ns = /*AK("READY")*/4'd0; + + end else + + // State based actions and next states. + case (sm_r) + + /*AL("READY")*/4'd0:begin + poc_backup_ns = 1'b0; + stg2_ns = {3'b0, wl_po_fine_cnt_sel}; + stg3_ns = stg3_init; + scanning_right_ns = 1'b0; + if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; + if (!reset_scan && ~resume_wait) begin + cmplx_samples_done_ns = 1'b0; + ocal_scan_win_not_found_ns = 1'b0; + taps_set_r = 1'b1; + sm_ns = /*AK("SAMPLING")*/4'd1; + end + end + + /*AL("SAMPLING")*/4'd1:begin + if (samp_done && use_samp_done) begin + if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1; + scanning_right_ns = scanning_right_r || left_stop; + if (right_stop && scanning_right_r) begin + oclkdelay_center_calib_start_ns = 1'b1; + ocd_ktap_left_ns = 1'b1; + ocal_scan_win_not_found_ns = win_not_found; + sm_ns = /*AK("SLEW_PO")*/4'd3; + end else begin + if (scanning_right_ns) ocd2stg3_inc_r = 1'b1; + else ocd2stg3_dec_r = 1'b1; + sm_ns = /*AK("PO_WAIT")*/4'd2; + end + end + end + + /*AL("PO_WAIT")*/4'd2:begin + if (po_done_r && ~resume_wait) begin + taps_set_r = 1'b1; + sm_ns = /*AK("SAMPLING")*/4'd1; + cmplx_samples_done_ns = 1'b0; + end + end + + /*AL("SLEW_PO")*/4'd3:begin + po_slew = 1'b1; + ninety_offsets_ns = |ninety_offsets_final_r ? 2'b01 : 2'b00; + if (~resume_wait) begin + if (po_done_r) begin + if (inc_po_r) ocd2stg3_inc_r = 1'b1; + else if (dec_po_r) ocd2stg3_dec_r = 1'b1; + else if (~resume_wait) begin + cmplx_samples_done_ns = 1'b0; + sm_ns = /*AK("ALIGN_EDGES")*/4'd4; + oclk_center_write_resume_ns = 1'b1; + end + end // if (po_done) + end + end // case: 3'd3 + + /*AL("ALIGN_EDGES")*/4'd4: + if (~resume_wait) begin + if (mmcm_edge_detect_done) begin + ocd_edge_detect_rdy_ns = 1'b0; + if (ocd_ktap_left_r) begin + ocd_ktap_left_ns = 1'b0; + ocd_ktap_right_ns = 1'b1; + oclk_center_write_resume_ns = 1'b0; + sm_ns = /*AK("SLEW_PO")*/4'd3; + end else if (ocd_ktap_right_r) begin + ocd_ktap_right_ns = 1'b0; + sm_ns = /*AK("WAIT_ONE")*/4'd5; + end else if (~mmcm_lbclk_edge_aligned) begin + sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6; + oclk_center_write_resume_ns = 1'b0; + end else begin + if (ninety_offsets_r != ninety_offsets_final_r && ocd_edge_detect_rdy_r) begin + ninety_offsets_ns = ninety_offsets_r + 2'b01; + sm_ns = /*AK("WAIT_ONE")*/4'd5; + end else begin + oclk_center_write_resume_ns = 1'b0; + poc_backup_ns = poc_backup; +// stg2_ns = stg2_2_zero; + sm_ns = /*AK("FINISH_SCAN")*/4'd8; + end + end // else: !if(~mmcm_lbclk_edge_aligned) + end else ocd_edge_detect_rdy_ns = 1'b1; + end // if (~resume_wait) + + + /*AL("WAIT_ONE")*/4'd5: + sm_ns = /*AK("ALIGN_EDGES")*/4'd4; + + /*AL("DQS_STOP_WAIT")*/4'd6: + if (~resume_wait) begin + ocd2stg3_dec_r = 1'b1; + sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7; + end + + /*AL("CENTER_PO_WAIT")*/4'd7: begin + po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols. + if (po_done_r) begin + sm_ns = /*AK("ALIGN_EDGES")*/4'd4; + oclk_center_write_resume_ns = 1'b1; + end + end + + /*AL("FINISH_SCAN")*/4'd8: begin + po_finish_scan = 1'b1; + if (resume_wait_r == 5'd1) begin + if (~poc_backup_r) begin + oclkdelay_center_calib_done_ns = 1'b1; + oclkdelay_center_calib_start_ns = 1'b0; + end + end + if (~resume_wait) begin + if (po_rdy) + if (poc_backup_r) begin + ocd2stg3_inc_r = 1'b1; + poc_backup_ns = 1'b0; + end + else if (~final_stg2_inc && ~final_stg2_dec) begin + if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; + else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r; + sm_ns = /*AK("READY")*/4'd0; + scan_done_r = 1'b1; + end else begin + ocd2stg2_inc_r = final_stg2_inc; + ocd2stg2_dec_r = final_stg2_dec; + end + end // if (~resume_wait) + end // case: 4'd8 + + endcase // case (sm_r) + + if (ocd2stg3_inc_r) begin + stg3_ns = stg3_r + 6'h1; + up_ns = 1'b0; + end + if (ocd2stg3_dec_r) begin + stg3_ns = stg3_r - 6'h1; + up_ns = 1'b1; + end + if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin + po_done_ns = 1'b0; + two_ns = 2'b00; + end + + if (~po_done_r) + if (po_rdy) + if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1; + else begin + two_ns = two_r + 2'b1; + if (up_r) begin + stg2_ns = stg2_r + 9'b1; + if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1; + end else begin + stg2_ns = stg2_r - 9'b1; + if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1; + end + end // else: !if(two_r == 2'b10) + + if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 'b1; + else if (oclk_center_write_resume_ns && ~oclk_center_write_resume_r) + resume_wait_ns = POC_SAMPLE_CLEAR_WAIT[RESUME_WAIT_WIDTH-1:0]; + else if (~oclk_center_write_resume_ns && oclk_center_write_resume_r) resume_wait_ns = 'd15; + else if (cmplx_samples_done_ns & ~cmplx_samples_done_r || + complex_oclkdelay_calib_start & reset_scan || + poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 'd31; + else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 'd1; + + end // always @ begin + +endmodule // mig_7series_v4_2_ddr_phy_ocd_po_cntlr + +// Local Variables: +// verilog-autolabel-prefix: "4'd" +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v new file mode 100644 index 0000000..bd20f0b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v @@ -0,0 +1,330 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_v4_0_phy_ocd_samp.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Controls the number of samples and generates an aggregate +//sampling result. +// +// The following shows the nesting of the sampling loop. Nominally built +// to accomodate the "complex" sampling protocol. Adapted for use with +// "simple" samplng. +// +// simple complex +// +// samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION +// rd_victim_sel 0 0 to 7 +// data_cnt 1 157 +// +// First it collects comparison results provided on the +// two bit "match" bus. A particular phaser tap setting may be recorded one +// or many times depending on various parameter settings. +// The two bit match bus corresponds to comparisons for the +// zero or rising phase, and the oneeighty or falling phase. The "aggregate" +// starts out as NULL and then begins collecting comparison results +// when phy_rddata_en_1 is high. The first result is always set into +// the aggregate result. Subsequent results that match aggregate, don't +// make any change. Subsequent compare results that don't match cause the aggregate +// to turn to FUZZ. +// +// A "sample" is defined as a single DRAM burst for the simple step, and +// an entire 157 DRAM data bursts across the 8 victim bits for complex. +// +// Once all samples have been taken, the samp_result is computed by +// comparing the number of successful compares against the threshold. +// +// The second function is to track and control the number of samples. For +// "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS. +// For "complex" data, nominally +// the complex data pattern consists of a sequence of 157 DRAM chunks. This +// sequence is run with each bit in the byte designated as the "victim". This sequence +// is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only +// repeated once. +// +// This block generates oclk_calib_resume. For the simple pattern, a single DRAM +// burst is returned For complex its 157 which indicates the start of the 157*50 +// sequence for a bit. samp_done is pulsed. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_ocd_samp # + (parameter nCK_PER_CLK = 4, + parameter OCAL_SIMPLE_SCAN_SAMPS = 2, + parameter SCAN_PCT_SAMPS_SOLID = 95, + parameter TCQ = 100, + parameter SIM_CAL_OPTION = "NONE") + (/*AUTOARG*/ + // Outputs + samp_done, oclk_calib_resume, rd_victim_sel, samp_result, + // Inputs + complex_oclkdelay_calib_start, clk, rst, reset_scan, + ocal_num_samples_inc, match, phy_rddata_en_1, taps_set, + phy_rddata_en_2 + ); + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + localparam ONE = 1; + + localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157; + localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1; + + localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8; + + localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1; + + // Plus one because were counting in natural numbers. + localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS + ? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1; + + // Remember SAMPLES is natural number counting. One corresponds to one sample. + localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; + localparam integer SIMP_SAMPS_HALF_THRESH = SIMP_SAMPS_SOLID_THRESH/2; + localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; + localparam integer CMPLX_SAMPS_HALF_THRESH = CMPLX_SAMPS_SOLID_THRESH/2; + + input complex_oclkdelay_calib_start; + + wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start + ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] + : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; + + localparam [1:0] NULL = 2'b11, + FUZZ = 2'b00, + ONEEIGHTY = 2'b10, + ZERO = 2'b01; + + input clk; + input rst; + + input reset_scan; + + // Given the need to count phy_data_en, this is not useful. + input ocal_num_samples_inc; + + input [1:0] match; + + input phy_rddata_en_1; + + input taps_set; + + reg samp_done_ns, samp_done_r; + always @(posedge clk) samp_done_r <= #TCQ samp_done_ns; + output samp_done; + assign samp_done = samp_done_r; + + input phy_rddata_en_2; + wire samp_valid = samp_done_r && phy_rddata_en_2; + + reg [1:0] agg_samp_ns, agg_samp_r; + always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns; + + reg oclk_calib_resume_ns, oclk_calib_resume_r; + always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns; + output oclk_calib_resume; + assign oclk_calib_resume = oclk_calib_resume_r; + + // Complex data counting. + // Inner most loop. 157 phy_data_en. + reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r; + always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns; + + // Nominally, 50 samples of the above 157 phy_data_en. + reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r; + always @(posedge clk) samps_r <= #TCQ samps_ns; + + // Step through the 8 bits in the byte. + reg [2:0] rd_victim_sel_ns, rd_victim_sel_r; + always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns; + output [2:0] rd_victim_sel; + assign rd_victim_sel = rd_victim_sel_r; + + reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r; + always @(posedge clk) zero_r <= #TCQ zero_ns; + always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns; + + wire [SAMP_CNT_WIDTH-1:0] samp_thresh = (complex_oclkdelay_calib_start + ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0] + : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]); + + wire [SAMP_CNT_WIDTH-1:0] samp_half_thresh = (complex_oclkdelay_calib_start + ? CMPLX_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0] + : SIMP_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]); + + wire zero_ge_thresh = zero_r >= samp_thresh; + wire zero_le_half_thresh = zero_r <= samp_half_thresh; + wire oneeighty_ge_thresh = oneeighty_r >= samp_thresh; + wire oneeighty_le_half_thresh = oneeighty_r <= samp_half_thresh; + + reg [1:0] samp_result_ns, samp_result_r; + always @(posedge clk) samp_result_r <= #TCQ samp_result_ns; + always @(*) + if (rst) samp_result_ns = 'b0; + else begin + samp_result_ns = samp_result_r; + if (samp_valid) begin + if (~samp_result_r[0] && zero_ge_thresh) samp_result_ns[0] = 'b1; + if (samp_result_r[0] && zero_le_half_thresh) samp_result_ns[0] = 'b0; + if (~samp_result_r[1] && oneeighty_ge_thresh) samp_result_ns[1] = 'b1; + if (samp_result_r[1] && oneeighty_le_half_thresh) samp_result_ns[1] = 'b0; + end + end + + output [1:0] samp_result; + assign samp_result = samp_result_ns; + + reg [0:0] sm_ns, sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + + wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start + ? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0] + : SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0]; + wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0; + wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0]; + wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0]; + + // Primary state machine. + + always @(*) begin + + // Default next state assignments. + + agg_samp_ns = agg_samp_r; + data_cnt_ns = data_cnt_r; + oclk_calib_resume_ns = 1'b0; + oneeighty_ns = oneeighty_r; + rd_victim_sel_ns = rd_victim_sel_r; + samp_done_ns = samp_done_r; + samps_ns = samps_r; + sm_ns = sm_r; + zero_ns = zero_r; + + if (rst == 1'b1) begin + // RESET next states + sm_ns = /*AK("READY")*/1'd0; + + end else + + // State based actions and next states. + case (sm_r) + + /*AL("READY")*/1'd0:begin + agg_samp_ns = NULL; + data_cnt_ns = data_cnt; + oneeighty_ns = 'b0; + zero_ns = 'b0; + rd_victim_sel_ns = 3'b0; + samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] + : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; + + + if (taps_set) begin + samp_done_ns = 1'b0; + sm_ns = /*AK("AWAITING_DATA")*/1'd1; + oclk_calib_resume_ns = 1'b1; + end + end + + /*AL("AWAITING_DATA")*/1'd1:begin + if (phy_rddata_en_1) begin + + case (agg_samp_r) + NULL : if (~&match) agg_samp_ns = match; + ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ; + FUZZ : ; + endcase // case (agg_samp_r) + + if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0]; + else begin + data_cnt_ns = data_cnt; + if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1; + else begin + rd_victim_sel_ns = 3'h0; + if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0]; + if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0]; + agg_samp_ns = NULL; + if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0]; + else samp_done_ns = 1'b1; + end + end + + if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0; + else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end; + end + end + + endcase // case (sm_r) + end // always @ begin + + +endmodule // mig_7series_v4_2_ddr_phy_ocd_samp + +// Local Variables: +// verilog-autolabel-prefix: "1'd" +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v new file mode 100644 index 0000000..5ab999b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v @@ -0,0 +1,553 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_oclkdelay_cal.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 +// delay +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_oclkdelay_cal # + (parameter TCQ = 100, + parameter nCK_PER_CLK = 4, + parameter DRAM_WIDTH = 8, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter DQ_WIDTH = 64, + parameter MMCM_SAMP_WAIT = 10, + parameter OCAL_SIMPLE_SCAN_SAMPS = 2, + parameter PCT_SAMPS_SOLID = 95, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter SCAN_PCT_SAMPS_SOLID = 95, + parameter SIM_CAL_OPTION = "NONE", + parameter SAMPCNTRWIDTH = 8, + parameter SAMPLES = 128, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 56, + parameter BYPASS_COMPLEX_OCAL = "FALSE") + (/*AUTOARG*/ + // Outputs + wrlvl_final, rd_victim_sel, psincdec, psen, poc_error, po_stg23_sel, + po_stg23_incdec, po_en_stg23, oclkdelay_center_calib_start, + oclkdelay_center_calib_done, oclk_prech_req, + oclk_center_write_resume, oclk_calib_resume, + ocal_num_samples_done_r, lim2init_write_request, dbg_poc, + complex_wrlvl_final, complex_oclkdelay_calib_done, + oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data, + oclkdelay_calib_done, lim_done, dbg_ocd_lim, + // Inputs + wl_po_fine_cnt, rst, psdone, prech_done, prbs_o, + prbs_ignore_last_bytes, prbs_ignore_first_byte, poc_sample_pd, + po_counter_read_val, phy_rddata_en, phy_rddata, oclkdelay_init_val, + oclkdelay_calib_start, ocal_num_samples_inc, metaQ, + complex_oclkdelay_calib_start, clk + ); + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input clk; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ... + input complex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v, ... + input metaQ; // To u_poc of mig_7series_v4_2_poc_top.v + input ocal_num_samples_inc; // To u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v + input oclkdelay_calib_start; // To u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + input [5:0] oclkdelay_init_val; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ... + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v + input phy_rddata_en; // To u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + input [8:0] po_counter_read_val; // To u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v, ... + input poc_sample_pd; // To u_poc of mig_7series_v4_2_poc_top.v + input prbs_ignore_first_byte; // To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v + input prbs_ignore_last_bytes; // To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; // To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v + input prech_done; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ... + input psdone; // To u_poc of mig_7series_v4_2_poc_top.v + input rst; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ... + input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; // To u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output complex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + output complex_wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + output [1023:0] dbg_poc; // From u_poc of mig_7series_v4_2_poc_top.v + output lim2init_write_request; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + output ocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + output oclk_calib_resume; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v + output oclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + output oclk_prech_req; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + output oclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + output oclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + output po_en_stg23; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + output po_stg23_incdec; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + output po_stg23_sel; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + output poc_error; // From u_poc of mig_7series_v4_2_poc_top.v + output psen; // From u_poc of mig_7series_v4_2_poc_top.v + output psincdec; // From u_poc of mig_7series_v4_2_poc_top.v + output [2:0] rd_victim_sel; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v + output wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire f2o; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire f2z; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire [5:0] fuzz2oneeighty; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire [5:0] fuzz2zero; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire ktap_at_left_edge; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + wire ktap_at_right_edge; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + wire lim2init_prech_req; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire [5:0] lim2ocal_stg3_left_lim; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire [5:0] lim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire lim2poc_ktap_right; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire lim2poc_rdy; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire lim2stg2_dec; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire lim2stg2_inc; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire lim2stg3_dec; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire lim2stg3_inc; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v + wire lim_start; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + wire [1:0] match; // From u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v + wire mmcm_edge_detect_done; // From u_poc of mig_7series_v4_2_poc_top.v + wire mmcm_edge_detect_rdy; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + wire mmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v4_2_poc_top.v + wire [1:0] ninety_offsets; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire o2f; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire ocd2stg2_dec; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire ocd2stg2_inc; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire ocd2stg3_dec; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire ocd2stg3_inc; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire ocd_cntlr2stg2_dec; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + wire ocd_edge_detect_rdy; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire ocd_ktap_left; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire ocd_ktap_right; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire ocd_prech_req; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + wire [5:0] oneeighty2fuzz; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire phy_rddata_en_1; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + wire phy_rddata_en_2; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + wire phy_rddata_en_3; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + wire po_rdy; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + wire poc_backup; // From u_poc of mig_7series_v4_2_poc_top.v + wire reset_scan; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v + wire [TAPCNTRWIDTH-1:0] rise_lead_right; // From u_poc of mig_7series_v4_2_poc_top.v + wire [TAPCNTRWIDTH-1:0] rise_trail_right; // From u_poc of mig_7series_v4_2_poc_top.v + wire samp_done; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v + wire [1:0] samp_result; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v + wire scan_done; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire scan_right; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire scanning_right; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire [5:0] simp_stg3_final_sel; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire [5:0] stg3; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire taps_set; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire use_noise_window; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v + wire [5:0] wl_po_fine_cnt_sel; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v + wire z2f; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + wire [5:0] zero2fuzz; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v + // End of automatics + wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; + wire ocal_scan_win_not_found; + + + output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; + output [255:0] dbg_phy_oclkdelay_cal; + output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data; + output oclkdelay_calib_done; + + output lim_done; + output [255:0] dbg_ocd_lim; + + // Debug signals + assign dbg_phy_oclkdelay_cal[0] = f2o; + assign dbg_phy_oclkdelay_cal[1] = f2z; + assign dbg_phy_oclkdelay_cal[2] = o2f; + assign dbg_phy_oclkdelay_cal[3] = z2f; + assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty; + assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero; + assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz; + assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz; + assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt; + assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start; + assign dbg_phy_oclkdelay_cal[32] = lim_done; + assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ; + assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ; + assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0]; + assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0]; + assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found; + assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start; + assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done; + assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0]; + + /*mig_7series_v4_2_ddr_phy_ocd_lim AUTO_TEMPLATE( + .TDQSS_DEGREES (), + .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]), + .poc2lim_detect_done (mmcm_edge_detect_done), + .poc2lim_fall_align_taps_.* ({TAPCNTRWIDTH{1'b0}}), + .poc2lim_rise_align_taps_lead (rise_lead_right), + .poc2lim_rise_align_taps_trail (rise_trail_right),); */ + + mig_7series_v4_2_ddr_phy_ocd_lim # + (/*AUTOINSTPARAM*/ + // Parameters + .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ), + .TDQSS_DEGREES ()) // Templated + u_ocd_lim + (/*AUTOINST*/ + // Outputs + .dbg_ocd_lim (dbg_ocd_lim[255:0]), + .lim2init_prech_req (lim2init_prech_req), + .lim2init_write_request (lim2init_write_request), + .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), + .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), + .lim2poc_ktap_right (lim2poc_ktap_right), + .lim2poc_rdy (lim2poc_rdy), + .lim2stg2_dec (lim2stg2_dec), + .lim2stg2_inc (lim2stg2_inc), + .lim2stg3_dec (lim2stg3_dec), + .lim2stg3_inc (lim2stg3_inc), + .lim_done (lim_done), + // Inputs + .clk (clk), + .lim_start (lim_start), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_calib_done (oclkdelay_calib_done), + .oclkdelay_init_val (oclkdelay_init_val[5:0]), + .po_rdy (po_rdy), + .poc2lim_detect_done (mmcm_edge_detect_done), // Templated + .poc2lim_fall_align_taps_lead ({TAPCNTRWIDTH{1'b0}}), // Templated + .poc2lim_fall_align_taps_trail ({TAPCNTRWIDTH{1'b0}}), // Templated + .poc2lim_rise_align_taps_lead (rise_lead_right), // Templated + .poc2lim_rise_align_taps_trail (rise_trail_right), // Templated + .prech_done (prech_done), + .rst (rst), + .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), + .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0])); // Templated + + /*mig_7series_v4_2_poc_top AUTO_TEMPLATE( + .CCENABLE (0), + .LANE_CNT_WIDTH (DQS_CNT_WIDTH), + .SCANFROMRIGHT (1), + .lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), + .pd_out (metaQ),); */ + + mig_7series_v4_2_poc_top # + (/*AUTOINSTPARAM*/ + // Parameters + .CCENABLE (0), // Templated + .LANE_CNT_WIDTH (DQS_CNT_WIDTH), // Templated + .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), + .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SAMPLES (SAMPLES), + .SCANFROMRIGHT (1), // Templated + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_poc + (/*AUTOINST*/ + // Outputs + .dbg_poc (dbg_poc[1023:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .poc_backup (poc_backup), + .poc_error (poc_error), + .psen (psen), + .psincdec (psincdec), + .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), + .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), + // Inputs + .clk (clk), + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), // Templated + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .ninety_offsets (ninety_offsets[1:0]), + .pd_out (metaQ), // Templated + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .rst (rst), + .use_noise_window (use_noise_window)); + + /*mig_7series_v4_2_ddr_phy_ocd_mux AUTO_TEMPLATE( + .po_stg3_incdec (), + .po_en_stg3 (),); */ + + mig_7series_v4_2_ddr_phy_ocd_mux # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .TCQ (TCQ)) + u_ocd_mux + (/*AUTOINST*/ + // Outputs + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .oclk_prech_req (oclk_prech_req), + .po_en_stg23 (po_en_stg23), + .po_en_stg3 (), // Templated + .po_rdy (po_rdy), + .po_stg23_incdec (po_stg23_incdec), + .po_stg23_sel (po_stg23_sel), + .po_stg3_incdec (), // Templated + .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), + // Inputs + .clk (clk), + .lim2init_prech_req (lim2init_prech_req), + .lim2poc_ktap_right (lim2poc_ktap_right), + .lim2poc_rdy (lim2poc_rdy), + .lim2stg2_dec (lim2stg2_dec), + .lim2stg2_inc (lim2stg2_inc), + .lim2stg3_dec (lim2stg3_dec), + .lim2stg3_inc (lim2stg3_inc), + .ocd2stg2_dec (ocd2stg2_dec), + .ocd2stg2_inc (ocd2stg2_inc), + .ocd2stg3_dec (ocd2stg3_dec), + .ocd2stg3_inc (ocd2stg3_inc), + .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), + .ocd_edge_detect_rdy (ocd_edge_detect_rdy), + .ocd_ktap_left (ocd_ktap_left), + .ocd_ktap_right (ocd_ktap_right), + .ocd_prech_req (ocd_prech_req), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .rst (rst), + .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0])); + + mig_7series_v4_2_ddr_phy_ocd_data # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK)) + u_ocd_data + (/*AUTOINST*/ + // Outputs + .match (match[1:0]), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .phy_rddata_en_1 (phy_rddata_en_1), + .prbs_ignore_first_byte (prbs_ignore_first_byte), + .prbs_ignore_last_bytes (prbs_ignore_last_bytes), + .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), + .rst (rst)); + + mig_7series_v4_2_ddr_phy_ocd_samp # + (/*AUTOINSTPARAM*/ + // Parameters + .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), + .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK)) + u_ocd_samp + (/*AUTOINST*/ + // Outputs + .oclk_calib_resume (oclk_calib_resume), + .rd_victim_sel (rd_victim_sel[2:0]), + .samp_done (samp_done), + .samp_result (samp_result[1:0]), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .match (match[1:0]), + .ocal_num_samples_inc (ocal_num_samples_inc), + .phy_rddata_en_1 (phy_rddata_en_1), + .phy_rddata_en_2 (phy_rddata_en_2), + .reset_scan (reset_scan), + .rst (rst), + .taps_set (taps_set)); + + mig_7series_v4_2_ddr_phy_ocd_edge # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ)) + u_ocd_edge + (/*AUTOINST*/ + // Outputs + .f2o (f2o), + .f2z (f2z), + .fuzz2oneeighty (fuzz2oneeighty[5:0]), + .fuzz2zero (fuzz2zero[5:0]), + .o2f (o2f), + .oneeighty2fuzz (oneeighty2fuzz[5:0]), + .scan_right (scan_right), + .z2f (z2f), + .zero2fuzz (zero2fuzz[5:0]), + // Inputs + .clk (clk), + .phy_rddata_en_2 (phy_rddata_en_2), + .reset_scan (reset_scan), + .samp_done (samp_done), + .samp_result (samp_result[1:0]), + .scanning_right (scanning_right), + .stg3 (stg3[5:0])); + + /*mig_7series_v4_2_ddr_phy_ocd_cntlr AUTO_TEMPLATE( + .oclk_init_delay_done (),); */ + + mig_7series_v4_2_ddr_phy_ocd_cntlr # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .TCQ (TCQ)) + u_ocd_cntlr + (/*AUTOINST*/ + // Outputs + .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), + .complex_wrlvl_final (complex_wrlvl_final), + .lim_start (lim_start), + .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), + .ocd_prech_req (ocd_prech_req), + .oclk_init_delay_done (), // Templated + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_calib_done (oclkdelay_calib_done), + .phy_rddata_en_1 (phy_rddata_en_1), + .phy_rddata_en_2 (phy_rddata_en_2), + .phy_rddata_en_3 (phy_rddata_en_3), + .reset_scan (reset_scan), + .wrlvl_final (wrlvl_final), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .lim_done (lim_done), + .oclkdelay_calib_start (oclkdelay_calib_start), + .phy_rddata_en (phy_rddata_en), + .po_counter_read_val (po_counter_read_val[8:0]), + .po_rdy (po_rdy), + .prech_done (prech_done), + .rst (rst), + .scan_done (scan_done)); + + + mig_7series_v4_2_ddr_phy_ocd_po_cntlr # + (/*AUTOINSTPARAM*/ + // Parameters + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .SAMPLES (SAMPLES), + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK)) + u_ocd_po_cntlr + (.cmplx_stg3_final (cmplx_stg3_final[DQS_WIDTH*6-1:0]), + .ocal_scan_win_not_found (ocal_scan_win_not_found), + .simp_stg3_final (simp_stg3_final[DQS_WIDTH*6-1:0]), + /*AUTOINST*/ + // Outputs + .ninety_offsets (ninety_offsets[1:0]), + .ocal_num_samples_done_r (ocal_num_samples_done_r), + .ocd2stg2_dec (ocd2stg2_dec), + .ocd2stg2_inc (ocd2stg2_inc), + .ocd2stg3_dec (ocd2stg3_dec), + .ocd2stg3_inc (ocd2stg3_inc), + .ocd_edge_detect_rdy (ocd_edge_detect_rdy), + .ocd_ktap_left (ocd_ktap_left), + .ocd_ktap_right (ocd_ktap_right), + .oclk_center_write_resume (oclk_center_write_resume), + .oclkdelay_center_calib_done (oclkdelay_center_calib_done), + .oclkdelay_center_calib_start (oclkdelay_center_calib_start), + .scan_done (scan_done), + .scanning_right (scanning_right), + .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), + .stg3 (stg3[5:0]), + .taps_set (taps_set), + .use_noise_window (use_noise_window), + // Inputs + .clk (clk), + .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), + .f2o (f2o), + .f2z (f2z), + .fuzz2oneeighty (fuzz2oneeighty[5:0]), + .fuzz2zero (fuzz2zero[5:0]), + .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), + .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .o2f (o2f), + .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), + .oclkdelay_init_val (oclkdelay_init_val[5:0]), + .oneeighty2fuzz (oneeighty2fuzz[5:0]), + .phy_rddata_en_3 (phy_rddata_en_3), + .po_counter_read_val (po_counter_read_val[8:0]), + .po_rdy (po_rdy), + .poc_backup (poc_backup), + .reset_scan (reset_scan), + .rst (rst), + .samp_done (samp_done), + .scan_right (scan_right), + .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), + .z2f (z2f), + .zero2fuzz (zero2fuzz[5:0])); + + +endmodule // mig_7series_v4_2_ddr_phy_oclkdelay_cal + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v new file mode 100644 index 0000000..8303e6f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v @@ -0,0 +1,5684 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_prbs_rdlvl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// PRBS Read leveling calibration logic +// NOTES: +// 1. Window detection with PRBS pattern. +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ +**$Date: 2011/06/24 14:49:00 $ +**$Author: mgeorge $ +**$Revision: 1.2 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_prbs_rdlvl # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter RANKS = 1, // # of DRAM ranks + parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps + parameter PRBS_WIDTH = 8, // PRBS generator output width + parameter FIXED_VICTIM = "TRUE", // No victim rotation when "TRUE" + parameter FINE_PER_BIT = "ON", + parameter CENTER_COMP_MODE = "ON", + parameter PI_VAL_ADJ = "ON" + ) + ( + input clk, + input rst, + // Calibration status, control signals + input prbs_rdlvl_start, + (* max_fanout = 100 *) output reg prbs_rdlvl_done, + output reg prbs_last_byte_done, + output reg prbs_rdlvl_prech_req, + input complex_sample_cnt_inc, + input prech_done, + input phy_if_empty, + // Captured data in fabric clock domain + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + //Expected data from PRBS generator + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data, + // Decrement initial Phaser_IN Fine tap delay + input [5:0] pi_counter_read_val, + // Stage 1 calibration outputs + output reg pi_en_stg2_f, + output reg pi_stg2_f_incdec, + output [255:0] dbg_prbs_rdlvl, + output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, + output reg [2:0] rd_victim_sel, + output reg complex_victim_inc, + output reg reset_rd_addr, + + output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, + output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, + output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, + output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit + output reg fine_delay_sel, //fine delay selection - actual update of fine delay + output reg num_samples_done_r, + input complex_act_start, //read is done. ready for PI movement + output complex_init_pi_dec_done, //Initial PI incdec is done. ready for start + output reg complex_pi_incdec_done //PI incdec is done. ready for Read + ); + + + + + localparam [5:0] PRBS_IDLE = 6'h00; + localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01; + localparam [5:0] PRBS_PAT_COMPARE = 6'h02; + localparam [5:0] PRBS_DEC_DQS = 6'h03; + localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04; + localparam [5:0] PRBS_INC_DQS = 6'h05; + localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06; + localparam [5:0] PRBS_CALC_TAPS = 6'h07; + localparam [5:0] PRBS_NEXT_DQS = 6'h08; + localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09; + localparam [5:0] PRBS_DONE = 6'h0A; + localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B; + localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C; + + localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center + localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle + localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail + localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle + localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss + localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size + localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt + localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_INC = 6'h14; //wait for read is done before PI inc + localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_DEC = 6'h15; //wait for read is done before PI dec + + localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd12 : 12'h001; //MG from 50 + localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001; + localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001; + + //minimum valid window for centering + localparam MIN_WIN = 8; + localparam [MIN_WIN-1:0] MATCH_ALL_ONE = {MIN_WIN{1'b1}}; + localparam [MIN_WIN-1:0] MIN_PASS = {MIN_WIN{1'b0}}; //8'b00000000 + localparam [MIN_WIN-1:0] MIN_LEFT = {1'b1,{{MIN_WIN-1}{1'b0}}}; //8'b10000000 + + wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing; + reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r; + reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r; + reg prbs_prech_req_r; + reg [5:0] prbs_state_r; + reg [5:0] prbs_state_r1; + reg wait_state_cnt_en_r; + reg [3:0] wait_state_cnt_r; + reg cnt_wait_state; + reg err_chk_invalid; + // reg found_edge_r; + reg prbs_found_1st_edge_r; + reg prbs_found_2nd_edge_r; + reg [5:0] prbs_1st_edge_taps_r; + // reg found_stable_eye_r; + reg [5:0] prbs_dqs_tap_cnt_r; + reg [5:0] prbs_dec_tap_calc_plus_3; + reg [5:0] prbs_dec_tap_calc_minus_3; + reg prbs_dqs_tap_limit_r; + reg [5:0] prbs_inc_tap_cnt; + reg [5:0] prbs_dec_tap_cnt; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4; + reg mux_rd_valid_r; + reg rd_valid_r1; + reg rd_valid_r2; + reg rd_valid_r3; + reg new_cnt_dqs_r; + reg prbs_tap_en_r; + reg prbs_tap_inc_r; + reg pi_en_stg2_f_timing; + reg pi_stg2_f_incdec_timing; + wire [DQ_WIDTH-1:0] rd_data_rise0; + wire [DQ_WIDTH-1:0] rd_data_fall0; + wire [DQ_WIDTH-1:0] rd_data_rise1; + wire [DQ_WIDTH-1:0] rd_data_fall1; + wire [DQ_WIDTH-1:0] rd_data_rise2; + wire [DQ_WIDTH-1:0] rd_data_fall2; + wire [DQ_WIDTH-1:0] rd_data_rise3; + wire [DQ_WIDTH-1:0] rd_data_fall3; + wire [DQ_WIDTH-1:0] compare_data_r0; + wire [DQ_WIDTH-1:0] compare_data_f0; + wire [DQ_WIDTH-1:0] compare_data_r1; + wire [DQ_WIDTH-1:0] compare_data_f1; + wire [DQ_WIDTH-1:0] compare_data_r2; + wire [DQ_WIDTH-1:0] compare_data_f2; + wire [DQ_WIDTH-1:0] compare_data_r3; + wire [DQ_WIDTH-1:0] compare_data_f3; + reg [DRAM_WIDTH-1:0] compare_data_rise0_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall0_r1; + reg [DRAM_WIDTH-1:0] compare_data_rise1_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall1_r1; + reg [DRAM_WIDTH-1:0] compare_data_rise2_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall2_r1; + reg [DRAM_WIDTH-1:0] compare_data_rise3_r1; + reg [DRAM_WIDTH-1:0] compare_data_fall3_r1; + reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; + reg [5:0] prbs_2nd_edge_taps_r; + + // reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r; + reg [5:0] rdlvl_cpt_tap_cnt; + reg prbs_rdlvl_start_r; + + reg compare_err; + reg compare_err_r0; + reg compare_err_f0; + reg compare_err_r1; + reg compare_err_f1; + reg compare_err_r2; + reg compare_err_f2; + reg compare_err_r3; + reg compare_err_f3; + reg compare_err_latch; + + reg samples_cnt1_en_r; + reg samples_cnt2_en_r; + reg [11:0] samples_cnt_r; + reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync + reg [DQS_WIDTH-1:0] prbs_tap_mod; + + //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps; + //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps; + + //************************************************************************** + // signals for per-bit algorithm of fine_delay calculations + //************************************************************************** + reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit + reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit + reg [MIN_WIN*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit + reg [MIN_WIN-1:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail) + reg [MIN_WIN-1:0] match_flag_or; //5 consecute match flag of all bits (1: any bit fail) + reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation + reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update + reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update + reg right_edge_found; //smallest right_edge found + reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit + reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit + reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge) + reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit + reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge + reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits + reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte + reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte + reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center) + reg [6:0] center_calc; //used for calculate the dec tap for centering + reg [5:0] right_edge_ref; //ref_bit right edge + reg [5:0] left_edge_ref; //ref_bit left edge + + reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit + reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge + reg compare_err_pb_and; //indicate all bit fail + reg compare_err_pb_or; //indicate any bit fail + reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit) + reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage) + wire fine_calib; //turn on/off fine delay calibration + + reg [5:0] mem_out_dec; + reg [5:0] dec_cnt; + reg fine_dly_error; //indicate it has wrong left/right edge + reg edge_det_error; //indicate it has wrong left/right edge + + wire center_comp; + wire pi_adj; + + reg no_err_win_detected; + reg no_err_win_detected_latch; + reg [1:0] valid_window_cnt; //number of valid window in the scan + reg double_window_ind; //indication of double window + + //if inital PI dec is not done, init SM should wait until it is done + reg complex_init_pi_dec_done_r; //if inital PI dec is not done, init SM should wait until it is done + wire complex_rdlvl_err; + + //************************************************************************** + // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 + // coarse delay + //************************************************************************** + assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r; + + //fine delay turn on + assign fine_calib = (FINE_PER_BIT=="ON")? 1:0; + assign center_comp = (CENTER_COMP_MODE == "ON")? 1: 0; + assign pi_adj = (PI_VAL_ADJ == "ON")?1:0; + + //Debug error flag + assign complex_rdlvl_err = fine_dly_error | edge_det_error; + + //initial dec is only happening for per-bit + assign complex_init_pi_dec_done = fine_calib? complex_init_pi_dec_done_r : 1'b1; + + assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6]; + assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2]; + assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6]; + assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2]; + assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ; + assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2]; + assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ; + assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2]; + assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6]; + assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2]; + assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6]; + assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2]; + assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6]; + assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2]; + assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6]; + assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2]; + + assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6]; + assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2]; + assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ; + assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2]; + assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6]; + assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2]; + assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6]; + assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2]; + assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6]; + assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2]; + assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6]; + assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2]; + assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6]; + assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2]; + assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6]; + assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2]; + + assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val; + assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r; + + assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r; + assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r; + assign dbg_prbs_rdlvl[142] = compare_err; + assign dbg_prbs_rdlvl[143] = phy_if_empty; + assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start; + assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done; + assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r; + assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ; + assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6]; + assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]}; + assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ; + assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0]; + + assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0]; + assign dbg_prbs_rdlvl[184] = rd_valid_r2; + assign dbg_prbs_rdlvl[185] = compare_err_r0; + assign dbg_prbs_rdlvl[186] = compare_err_f0; + assign dbg_prbs_rdlvl[187] = compare_err_r1; + assign dbg_prbs_rdlvl[188] = compare_err_f1; + assign dbg_prbs_rdlvl[189] = compare_err_r2; + assign dbg_prbs_rdlvl[190] = compare_err_f2; + assign dbg_prbs_rdlvl[191] = compare_err_r3; + assign dbg_prbs_rdlvl[192] = compare_err_f3; + assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb; + assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb; + assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ; + assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ; + assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb; + assign dbg_prbs_rdlvl[229] = fine_delay_sel; + assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r; + assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt; + assign dbg_prbs_rdlvl[244+:5] = match_flag_and[4:0]; + assign dbg_prbs_rdlvl[249+:2] = stage_cnt; + assign dbg_prbs_rdlvl[251] = fine_inc_stage; + assign dbg_prbs_rdlvl[252] = compare_err_pb_and; + assign dbg_prbs_rdlvl[253] = right_edge_found; + assign dbg_prbs_rdlvl[254] = complex_rdlvl_err; + assign dbg_prbs_rdlvl[255] = double_window_ind; + + //************************************************************************** + // Record first and second edges found during calibration + //************************************************************************** + generate + always @(posedge clk) + if (rst) begin + dbg_prbs_first_edge_taps <= #TCQ 'b0; + dbg_prbs_second_edge_taps <= #TCQ 'b0; + end else if (prbs_state_r == PRBS_CALC_TAPS) begin + // Record tap counts of first and second edge edges during + // calibration for each DQS group. If neither edge has + // been found, then those taps will remain 0 + if (prbs_found_1st_edge_r) + dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ prbs_1st_edge_taps_r; + if (prbs_found_2nd_edge_r) + dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ prbs_2nd_edge_taps_r; + end else if (prbs_state_r == FINE_CALC_TAPS) begin + if(stage_cnt == 'd2) begin + dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ largest_left_edge; + dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ smallest_right_edge; + end + end + endgenerate + + //double window indication flag + always @ (posedge clk) + if (rst) double_window_ind <= #TCQ 1'd0; + else double_window_ind <= #TCQ double_window_ind? 1'b1: (valid_window_cnt > 1); + + //padded calculation + always @ (smallest_right_edge or largest_left_edge) + center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge}; + //*************************************************************************** + //*************************************************************************** + // Data mux to route appropriate bit to calibration logic - i.e. calibration + // is done sequentially, one bit (or DQS group) at a time + //*************************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; + assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + end else begin: rd_data_div2_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; + assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign compare_data_r2 = 'h0; + assign compare_data_f2 = 'h0; + assign compare_data_r3 = 'h0; + assign compare_data_f3 = 'h0; + end + endgenerate + + always @(posedge clk) begin + rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r; + end + + // Register outputs for improved timing. + // NOTE: Will need to change when per-bit DQ deskew is supported. + // Currenly all bits in DQS group are checked in aggregate + generate + genvar mux_i; + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + //Compare data + compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + end + end + endgenerate + + generate + genvar muxr2_i; + if (nCK_PER_CLK == 4) begin: gen_mux_div4 + for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4 + always @(posedge clk) begin + if (mux_rd_valid_r) begin + mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; + mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; + mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; + mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; + mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i]; + mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i]; + mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i]; + mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i]; + end + //pipeline stage + mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; + mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; + mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; + mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; + mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i]; + mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i]; + mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i]; + mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i]; + //pipeline stage + mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; + mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; + mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; + mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; + mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i]; + mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i]; + mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i]; + mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i]; + end + end + end else if (nCK_PER_CLK == 2) begin: gen_mux_div2 + for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2 + always @(posedge clk) begin + if (mux_rd_valid_r) begin + mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; + mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; + mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; + mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; + mux_rd_rise2_r2[muxr2_i] <= 'h0; + mux_rd_fall2_r2[muxr2_i] <= 'h0; + mux_rd_rise3_r2[muxr2_i] <= 'h0; + mux_rd_fall3_r2[muxr2_i] <= 'h0; + end + mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; + mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; + mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; + mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; + mux_rd_rise2_r3[muxr2_i] <= 'h0; + mux_rd_fall2_r3[muxr2_i] <= 'h0; + mux_rd_rise3_r3[muxr2_i] <= 'h0; + mux_rd_fall3_r3[muxr2_i] <= 'h0; + + //pipeline stage + mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; + mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; + mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; + mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; + mux_rd_rise2_r4[muxr2_i] <= 'h0; + mux_rd_fall2_r4[muxr2_i] <= 'h0; + mux_rd_rise3_r4[muxr2_i] <= 'h0; + mux_rd_fall3_r4[muxr2_i] <= 'h0; + end + end + end + endgenerate + + + // Registered signal indicates when mux_rd_rise/fall_r is valid + always @(posedge clk) begin + mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start; + rd_valid_r1 <= #TCQ mux_rd_valid_r; + rd_valid_r2 <= #TCQ rd_valid_r1; + rd_valid_r3 <= #TCQ rd_valid_r2; + end + + + + +// Counter counts # of samples compared +// Reset sample counter when not "sampling" +// Otherwise, count # of samples compared +// Same counter is shared for three samples checked + always @(posedge clk) + if (rst) + samples_cnt_r <= #TCQ 'b0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) begin + samples_cnt_r <= #TCQ 'b0; + end else if (complex_sample_cnt_inc) begin + samples_cnt_r <= #TCQ samples_cnt_r + 1; + /*if (!rd_valid_r1 || + (prbs_state_r == PRBS_DEC_DQS_WAIT) || + (prbs_state_r == PRBS_INC_DQS_WAIT) || + (prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS) || + (samples_cnt_r == NUM_SAMPLES_CNT) || + (samples_cnt_r == NUM_SAMPLES_CNT1)) + samples_cnt_r <= #TCQ 'b0; + else if (rd_valid_r1 && + (((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) || + ((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) || + ((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r))) + samples_cnt_r <= #TCQ samples_cnt_r + 1;*/ + end + +// Count #2 enable generation +// Assert when correct number of samples compared + always @(posedge clk) + if (rst) + samples_cnt1_en_r <= #TCQ 1'b0; + else begin + if ((prbs_state_r == PRBS_IDLE) || + (prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS) || + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) + samples_cnt1_en_r <= #TCQ 1'b0; + else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1) + samples_cnt1_en_r <= #TCQ 1'b1; + end + +// Counter #3 enable generation +// Assert when correct number of samples compared + always @(posedge clk) + if (rst) + samples_cnt2_en_r <= #TCQ 1'b0; + else begin + if ((prbs_state_r == PRBS_IDLE) || + (prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS) || + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) + samples_cnt2_en_r <= #TCQ 1'b0; + else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r) + samples_cnt2_en_r <= #TCQ 1'b1; + end + +// Victim selection logic + always @(posedge clk) + if (rst) + rd_victim_sel <= #TCQ 'd0; + else if (num_samples_done_r) + rd_victim_sel <= #TCQ 'd0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) begin + if (rd_victim_sel < 'd7) + rd_victim_sel <= #TCQ rd_victim_sel + 1; + end + +// Output row count increment pulse to phy_init + always @(posedge clk) + if (rst) + complex_victim_inc <= #TCQ 1'b0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) + complex_victim_inc <= #TCQ 1'b1; + else + complex_victim_inc <= #TCQ 1'b0; + +generate + if (FIXED_VICTIM == "TRUE") begin: victim_fixed + always @(posedge clk) + if (rst) + num_samples_done_r <= #TCQ 1'b0; + else if ((prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS)|| + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == FINE_PI_DEC)) + num_samples_done_r <= #TCQ 'b0; + else if (samples_cnt_r == NUM_SAMPLES_CNT) + num_samples_done_r <= #TCQ 1'b1; + end else begin: victim_not_fixed + always @(posedge clk) + if (rst) + num_samples_done_r <= #TCQ 1'b0; + else if ((prbs_state_r == PRBS_DEC_DQS) || + (prbs_state_r == PRBS_INC_DQS)|| + (prbs_state_r == FINE_PI_INC) || + (prbs_state_r == FINE_PI_DEC)) + num_samples_done_r <= #TCQ 'b0; + else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7)) + num_samples_done_r <= #TCQ 1'b1; + end +endgenerate + + + //*************************************************************************** + // Compare Read Data for the byte being Leveled with Expected data from PRBS + // generator. Resulting compare_err signal used to determine read data valid + // edge. + //*************************************************************************** + generate + if (nCK_PER_CLK == 4) begin: cmp_err_4to1 + always @ (posedge clk) begin + if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin + compare_err <= #TCQ 1'b0; + compare_err_r0 <= #TCQ 1'b0; + compare_err_f0 <= #TCQ 1'b0; + compare_err_r1 <= #TCQ 1'b0; + compare_err_f1 <= #TCQ 1'b0; + compare_err_r2 <= #TCQ 1'b0; + compare_err_f2 <= #TCQ 1'b0; + compare_err_r3 <= #TCQ 1'b0; + compare_err_f3 <= #TCQ 1'b0; + end else if (rd_valid_r2) begin + compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); + compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); + compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); + compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); + compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1); + compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1); + compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1); + compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1); + compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | + compare_err_r1 | compare_err_f1 | + compare_err_r2 | compare_err_f2 | + compare_err_r3 | compare_err_f3); + end + end + end else begin: cmp_err_2to1 + always @ (posedge clk) begin + if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin + compare_err <= #TCQ 1'b0; + compare_err_r0 <= #TCQ 1'b0; + compare_err_f0 <= #TCQ 1'b0; + compare_err_r1 <= #TCQ 1'b0; + compare_err_f1 <= #TCQ 1'b0; + end else if (rd_valid_r2) begin + compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); + compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); + compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); + compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); + compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | + compare_err_r1 | compare_err_f1); + end + end + end + endgenerate + + //Sticky bit compare_err + always @ (posedge clk) + if (prbs_state_r == PRBS_PAT_COMPARE) + compare_err_latch <= #TCQ compare_err? 1'b1: compare_err_latch; + else + compare_err_latch <= #TCQ 1'b0; + +//*************************************************************************** +// Decrement initial Phaser_IN fine delay value before proceeding with +// read calibration +//*************************************************************************** + + +//*************************************************************************** +// Demultiplexor to control Phaser_IN delay values +//*************************************************************************** + +// Read DQS + always @(posedge clk) begin + if (rst) begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end else if (prbs_tap_en_r) begin +// Change only specified DQS + pi_en_stg2_f_timing <= #TCQ 1'b1; + pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r; + end else begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end + end + +// registered for timing + always @(posedge clk) begin + pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; + pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; + end + +//*************************************************************************** +// generate request to PHY_INIT logic to issue precharged. Required when +// calibration can take a long time (during which there are only constant +// reads present on this bus). In this case need to issue perioidic +// precharges to avoid tRAS violation. This signal must meet the following +// requirements: (1) only transition from 0->1 when prech is first needed, +// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted +//*************************************************************************** + + always @(posedge clk) + if (rst) + prbs_rdlvl_prech_req <= #TCQ 1'b0; + else + prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r; + +//***************************************************************** +// keep track of edge tap counts found, and current capture clock +// tap count +//***************************************************************** + + always @(posedge clk) + if (rst) begin + prbs_dqs_tap_cnt_r <= #TCQ 'b0; + rdlvl_cpt_tap_cnt <= #TCQ 'b0; + end else if (new_cnt_dqs_r) begin + prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val; + rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val; + end else if (prbs_tap_en_r) begin + if (prbs_tap_inc_r) + prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1; + else if (prbs_dqs_tap_cnt_r != 'd0) + prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1; + end + + always @(posedge clk) + if (rst) begin + prbs_dec_tap_calc_plus_3 <= #TCQ 'b0; + prbs_dec_tap_calc_minus_3 <= #TCQ 'b0; + end else if (new_cnt_dqs_r) begin + prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011; + prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100; + end else begin + prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3); + prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3); + end + + always @(posedge clk) + if (rst || new_cnt_dqs_r) + prbs_dqs_tap_limit_r <= #TCQ 1'b0; + else if (prbs_dqs_tap_cnt_r == 6'd63) + prbs_dqs_tap_limit_r <= #TCQ 1'b1; + else + prbs_dqs_tap_limit_r <= #TCQ 1'b0; + + // Temp wire for timing. + // The following in the always block below causes timing issues + // due to DSP block inference + // 6*prbs_dqs_cnt_r. + // replacing this with two left shifts + one left shift to avoid + // DSP multiplier. + + assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r}; + + + always @(posedge clk) + prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing; + + + // Storing DQS tap values at the end of each DQS read leveling + always @(posedge clk) begin + if (rst) begin + prbs_final_dqs_tap_cnt_r <= #TCQ 'b0; + end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin + prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6] + <= #TCQ prbs_dqs_tap_cnt_r; + end + end + + + + + //***************************************************************** + + always @(posedge clk) begin + prbs_state_r1 <= #TCQ prbs_state_r; + prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start; + end + +// Wait counter for wait states + always @(posedge clk) + if ((prbs_state_r == PRBS_NEW_DQS_WAIT) || + (prbs_state_r == PRBS_INC_DQS_WAIT) || + (prbs_state_r == PRBS_DEC_DQS_WAIT) || + (prbs_state_r == FINE_PI_DEC_WAIT) || + (prbs_state_r == FINE_PI_INC_WAIT) || + (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) + wait_state_cnt_en_r <= #TCQ 1'b1; + else + wait_state_cnt_en_r <= #TCQ 1'b0; + + always @(posedge clk) + if (!wait_state_cnt_en_r) begin + wait_state_cnt_r <= #TCQ 'b0; + cnt_wait_state <= #TCQ 1'b0; + end else begin + if (wait_state_cnt_r < 'd15) begin + wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1; + cnt_wait_state <= #TCQ 1'b0; + end else begin + // Need to reset to 0 to handle the case when there are two + // different WAIT states back-to-back + wait_state_cnt_r <= #TCQ 'b0; + cnt_wait_state <= #TCQ 1'b1; + end + end + + always @ (posedge clk) + err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14); + + +//***************************************************************** +// compare error checking per-bit +//**************************************************************** + + generate + genvar pb_i; + if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1 + for(pb_i=0 ; pb_i prbs_dqs_tap_cnt_r -(MIN_WIN-1))? 'd0 + : prbs_dqs_tap_cnt_r-(MIN_WIN-1)-left_edge_ref; + //right edge is updated when match flag becomes 000000001 (8 success, 1 fail) + end else if (match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_PASS && compare_err_pb_latch_r[eg]) begin + right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1; + right_edge_found_pb[eg] <= #TCQ 1'b1; + //check the gain of bit - update only for right edge found + if(~right_edge_found_pb[eg]) + right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)? + ((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]): + ((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]); + //no right edge found + end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin + right_edge_pb[eg*6+:6] <= #TCQ 6'h3f; + right_edge_found_pb[eg] <= #TCQ 1'b1; + //right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge) + right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])? + (right_edge_ref - right_edge_pb[eg*6+:6]) : 0; + end + //update match flag - shift and update + match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ {match_flag_pb[(eg*MIN_WIN)+:(MIN_WIN-1)],compare_err_pb_latch_r[eg]}; + end else if (prbs_state_r == FINE_PI_DEC) begin + left_edge_found_pb[eg] <= #TCQ 1'b0; + right_edge_found_pb[eg] <= #TCQ 1'b0; + left_loss_pb[eg*6+:6] <= #TCQ 'b0; + right_gain_pb[eg*6+:6] <= #TCQ 'b0; + match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE ; //new fix + left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge + end else if (prbs_state_r == FINE_PI_INC) begin + left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge + end + end + end //always + end //for + endgenerate + + //update fine_delay according to loss/gain value per bit + generate + genvar f_pb; + for(f_pb=0; f_pbleft_loss_pb[f_pb*6+:6])?1'b1:1'b0; + end + end + end + endgenerate + + //fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3) + always @ (posedge clk) begin + if (rst) + fine_inc_stage <= #TCQ 'b1; + else + fine_inc_stage <= #TCQ (stage_cnt!='d3); + end +//***************************************************************** + + always @(posedge clk) + if (rst) begin + prbs_dqs_cnt_r <= #TCQ 'b0; + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + prbs_prech_req_r <= #TCQ 1'b0; + prbs_state_r <= #TCQ PRBS_IDLE; + prbs_found_1st_edge_r <= #TCQ 1'b0; + prbs_found_2nd_edge_r <= #TCQ 1'b0; + prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx; + prbs_inc_tap_cnt <= #TCQ 'b0; + prbs_dec_tap_cnt <= #TCQ 'b0; + new_cnt_dqs_r <= #TCQ 1'b0; + if (SIM_CAL_OPTION == "FAST_CAL") + prbs_rdlvl_done <= #TCQ 1'b1; + else + prbs_rdlvl_done <= #TCQ 1'b0; + prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx; + prbs_last_byte_done <= #TCQ 1'b0; + prbs_tap_mod <= #TCQ 'd0; + reset_rd_addr <= #TCQ 'b0; + fine_pi_dec_cnt <= #TCQ 'b0; + match_flag_and <= #TCQ MATCH_ALL_ONE; + match_flag_or <= #TCQ MATCH_ALL_ONE; + no_err_win_detected <= #TCQ 1'b0; + no_err_win_detected_latch <= #TCQ 1'b0; + valid_window_cnt <= 2'd0; + stage_cnt <= #TCQ 2'b00; + right_edge_found <= #TCQ 1'b0; + largest_left_edge <= #TCQ 6'b000000; + smallest_right_edge <= #TCQ 6'b111111; + num_samples_done_ind <= #TCQ 'b0; + fine_delay_sel <= #TCQ 'b0; + fine_dly_error <= #TCQ 'b0; + edge_det_error <= #TCQ 'b0; + complex_pi_incdec_done <= #TCQ 1'b0; + complex_init_pi_dec_done_r <= #TCQ 1'b0; + end else begin + + case (prbs_state_r) + + PRBS_IDLE: begin + prbs_last_byte_done <= #TCQ 1'b0; + prbs_prech_req_r <= #TCQ 1'b0; + if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin + if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin + prbs_state_r <= #TCQ PRBS_DONE; + reset_rd_addr <= #TCQ 1'b1; + end else begin + new_cnt_dqs_r <= #TCQ 1'b1; + prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; + fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. + end + end + end + + // Wait for the new DQS group to change + // also gives time for the read data IN_FIFO to + // output the updated data for the new DQS group + PRBS_NEW_DQS_WAIT: begin + reset_rd_addr <= #TCQ 'b0; + prbs_last_byte_done <= #TCQ 1'b0; + prbs_prech_req_r <= #TCQ 1'b0; + stage_cnt <= #TCQ 2'b0; + match_flag_and <= #TCQ MATCH_ALL_ONE; + match_flag_or <= #TCQ MATCH_ALL_ONE; + no_err_win_detected <= #TCQ 1'b0; + no_err_win_detected_latch <= #TCQ 1'b0; + if (cnt_wait_state) begin + new_cnt_dqs_r <= #TCQ 1'b0; + prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE; + //For normal, it doesn't have initial pi incdec + complex_pi_incdec_done <= #TCQ fine_calib? complex_pi_incdec_done: 1'b1; + end + end + + // Check for presence of data eye edge. During this state, we + // sample the read data multiple times, and look for changes + // in the read data, specifically: + // 1. A change in the read data compared with the value of + // read data from the previous delay tap. This indicates + // that the most recent tap delay increment has moved us + // into either a new window, or moved/kept us in the + // transition/jitter region between windows. Note that this + // condition only needs to be checked for once, and for + // logistical purposes, we check this soon after entering + // this state (see comment in PRBS_PAT_COMPARE below for + // why this is done) + // 2. A change in the read data while we are in this state + // (i.e. in the absence of a tap delay increment). This + // indicates that we're close enough to a window edge that + // jitter will cause the read data to change even in the + // absence of a tap delay change + PRBS_PAT_COMPARE: begin + // Continue to sample read data and look for edges until the + // appropriate time interval (shorter for simulation-only, + // much, much longer for actual h/w) has elapsed + //comparision started - wait for next PI movement after read + complex_pi_incdec_done <= #TCQ 1'b0; //need to be wait for new incdec done + if (num_samples_done_r) begin + if (prbs_dqs_tap_limit_r) + // Only one edge detected and ran out of taps since only one + // bit time worth of taps available for window detection. This + // can happen if at tap 0 DQS is in previous window which results + // in only left edge being detected. Or at tap 0 DQS is in the + // current window resulting in only right edge being detected. + // Depending on the frequency this case can also happen if at + // tap 0 DQS is in the left noise region resulting in only left + // edge being detected. + prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; + else if (compare_err_latch || (prbs_dqs_tap_cnt_r == 'd0)) begin + // Sticky bit - asserted after we encounter an edge, although + // the current edge may not be considered the "first edge" this + // just means we found at least one edge + prbs_found_1st_edge_r <= #TCQ 1'b1; + + // Both edges of data valid window found: + // If we've found a second edge after a region of stability + // then we must have just passed the second ("right" edge of + // the window. Record this second_edge_taps = current tap-1, + // because we're one past the actual second edge tap, where + // the edge taps represent the extremes of the data valid + // window (i.e. smallest & largest taps where data still valid + if (prbs_found_1st_edge_r) begin + prbs_found_2nd_edge_r <= #TCQ 1'b1; + prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1; + prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; + end else begin + // Otherwise, an edge was found (just not the "second" edge) + // Assuming DQS is in the correct window at tap 0 of Phaser IN + // fine tap. The first edge found is the right edge of the valid + // window and is the beginning of the jitter region hence done! + if (compare_err_latch) + prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1; + else + prbs_1st_edge_taps_r <= #TCQ 'd0; + + prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; + end + end else begin + // Otherwise, if we haven't found an edge.... + // If we still have taps left to use, then keep incrementing + if (prbs_found_1st_edge_r) + //prbs_state_r <= #TCQ PRBS_INC_DQS; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; + else + //prbs_state_r <= #TCQ PRBS_DEC_DQS; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end + end + end + + // Increment Phaser_IN delay for DQS + PRBS_INC_DQS: begin + prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT; + if (prbs_inc_tap_cnt > 'd0) + prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1; + if (~prbs_dqs_tap_limit_r) begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b1; + end + end + + // Wait for Phaser_In to settle, before checking again for an edge + // only all INC is done, incdec done is asserted + PRBS_INC_DQS_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if (cnt_wait_state) begin + if (prbs_inc_tap_cnt > 'd0) + prbs_state_r <= #TCQ PRBS_INC_DQS; //centering + else begin + prbs_state_r <= #TCQ PRBS_PAT_COMPARE; + complex_pi_incdec_done <= #TCQ 1'b1; + end + end + end + + // Calculate final value of Phaser_IN taps. At this point, one or both + // edges of data eye have been found, and/or all taps have been + // exhausted looking for the edges + // NOTE: The amount to be decrement by is calculated, not the + // absolute setting for DQS. + // CENTER compensation with shift by 1 + //wait finishing the read before PI dec to center + PRBS_CALC_TAPS: begin + if (center_comp) begin + prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj; + fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end else begin //No center compensation + if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin + // Both edges detected + prbs_dec_tap_cnt + <= #TCQ ((prbs_2nd_edge_taps_r - + prbs_1st_edge_taps_r)>>1) + 1 + pi_adj; + edge_det_error <= #TCQ edge_det_error? 1'b1: + (prbs_1st_edge_taps_r >= prbs_2nd_edge_taps_r); + end else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin + // Only left edge detected + prbs_dec_tap_cnt + <= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj; + end else begin + // No edges detected + edge_det_error <= #TCQ 1'b1; + prbs_dec_tap_cnt + <= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj; + end + // Now use the value we just calculated to decrement CPT taps + // to the desired calibration point + //wait finishing the read before PI dec to center + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end + end + + // decrement capture clock for final adjustment - center + // capture clock in middle of data eye. This adjustment will occur + // only when both the edges are found usign CPT taps. Must do this + // incrementally to avoid clock glitching (since CPT drives clock + // divider within each ISERDES) + PRBS_DEC_DQS: begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b0; + // once adjustment is complete, we're done with calibration for + // this DQS, repeat for next DQS + if (prbs_dec_tap_cnt > 'd0) + prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1; + if (prbs_dec_tap_cnt == 6'b000001) begin + prbs_state_r <= #TCQ PRBS_NEXT_DQS; + //only all DEC is done, incdec done is asserted + complex_pi_incdec_done <= #TCQ 1'b1; + end else + prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT; + end + + PRBS_DEC_DQS_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if (cnt_wait_state) begin + if (prbs_dec_tap_cnt > 'd0) + prbs_state_r <= #TCQ PRBS_DEC_DQS; + else begin + //PI movement is done, go to read and compare + complex_pi_incdec_done <= #TCQ 1'b1; + prbs_state_r <= #TCQ PRBS_PAT_COMPARE; + end + end + end + + // Determine whether we're done, or have more DQS's to calibrate + // Also request precharge after every byte, as appropriate + PRBS_NEXT_DQS: begin + //Need to do initial dec for per-bit algorithm + complex_init_pi_dec_done_r <= #TCQ 1'b0; + reset_rd_addr <= #TCQ 'b1; + prbs_prech_req_r <= #TCQ 1'b1; + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + // Prepare for another iteration with next DQS group + prbs_found_1st_edge_r <= #TCQ 1'b0; + prbs_found_2nd_edge_r <= #TCQ 1'b0; + prbs_1st_edge_taps_r <= #TCQ 'd0; + prbs_2nd_edge_taps_r <= #TCQ 'd0; + largest_left_edge <= #TCQ 6'b000000; + smallest_right_edge <= #TCQ 6'b111111; + if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin + prbs_last_byte_done <= #TCQ 1'b1; + end + + // Wait until precharge that occurs in between calibration of + // DQS groups is finished + if (prech_done) begin + prbs_prech_req_r <= #TCQ 1'b0; + if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin + // All DQS groups done + prbs_state_r <= #TCQ PRBS_DONE; + end else begin + // Process next DQS group + new_cnt_dqs_r <= #TCQ 1'b1; + prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1; + prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT; + end + end + end + + PRBS_NEW_DQS_PREWAIT: begin + if (cnt_wait_state) begin + prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; + fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. + end + end + + PRBS_CALC_TAPS_PRE: + begin + //Wait for new PI movement + complex_pi_incdec_done <= #TCQ 1'b0; + prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT; + if(center_comp && ~fine_calib) begin + if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r; + else largest_left_edge <= #TCQ 6'd0; + if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r; + else smallest_right_edge <= #TCQ 6'd63; + end + end + + //wait for center compensation + PRBS_CALC_TAPS_WAIT: + begin + prbs_state_r <= #TCQ PRBS_CALC_TAPS; + end + //if it is fine_inc stage (first/second stage): dec to 0 + //if it is fine_dec stage (third stage): dec to center + FINE_PI_DEC: begin + fine_delay_sel <= #TCQ 'b0; + if(fine_pi_dec_cnt > 0) begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b0; + fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1; + end + prbs_state_r <= #TCQ FINE_PI_DEC_WAIT; + end + //wait for phaser_in tap decrement. + //if first/second stage is done, goes to FINE_PI_INC + //if last stage is done, goes to NEXT_DQS + //All PI DEC is done, incdec done is asserted + FINE_PI_DEC_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if(cnt_wait_state) begin + if(fine_pi_dec_cnt >0) + prbs_state_r <= #TCQ FINE_PI_DEC; + else begin + complex_pi_incdec_done <= #TCQ 1'b1; + if(fine_inc_stage) + prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap "0" + else + prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS + end + end + end + + //finish the read before PI increament + RD_DONE_WAIT_FOR_PI_INC_INC: begin + if(complex_act_start) + prbs_state_r <= #TCQ fine_calib? FINE_PI_INC: PRBS_INC_DQS; + end + + FINE_PI_INC: begin + //prevent left edge update after valid window found + if(|left_edge_updated && ~no_err_win_detected_latch) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1); + + if (no_err_win_detected) begin + //ignore previous right edge updated if valid window shown after + right_edge_found <= #TCQ 'b0; + end else if(|right_edge_found_pb && ~right_edge_found) begin + smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ; + right_edge_found <= #TCQ 'b1; + end + //until minimum window is detected, left edge can be updated + //once minimum window is detected, no further left edge update will be done + if(no_err_win_detected) no_err_win_detected_latch <= #TCQ 1'b1; + prbs_state_r <= #TCQ FINE_PI_INC_WAIT; + if(~prbs_dqs_tap_limit_r) begin + prbs_tap_en_r <= #TCQ 1'b1; + prbs_tap_inc_r <= #TCQ 1'b1; + end + end + + //wait for phase_in tap increment + //need to do pattern compare for every bit + FINE_PI_INC_WAIT: begin + prbs_tap_en_r <= #TCQ 1'b0; + prbs_tap_inc_r <= #TCQ 1'b0; + if (cnt_wait_state) begin + prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; + //PI movement is done, go to read and compare + complex_pi_incdec_done <= #TCQ 1'b1; + end + end + + //compare per bit data and update flags,left/right edge + FINE_PAT_COMPARE_PER_BIT: begin + //comparision started - initial pi dec is done, wait for another pi movement after read + complex_init_pi_dec_done_r <= #TCQ 1'b1; + complex_pi_incdec_done <= #TCQ 1'b0; + if(num_samples_done_r) begin //sampling boundary + //update and_flag - shift and add + match_flag_and <= #TCQ {match_flag_and[MIN_WIN-2:0],compare_err_pb_and}; + match_flag_or <= #TCQ {match_flag_or[MIN_WIN-2:0],compare_err_pb_or}; + + //to solve false left/right edge detection + if({match_flag_or[MIN_WIN-2:0],compare_err_pb_or} == MIN_PASS) begin //if it detect minimum window + no_err_win_detected <= #TCQ 1'b1; + valid_window_cnt <= #TCQ valid_window_cnt + 'd1; + end else begin + no_err_win_detected <= #TCQ 1'b0; + end + //if it is consecutive 8 passing taps followed by fail or tap limit (finish the search) + //don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage + //Or if all right edge are found + if((match_flag_and == MIN_PASS && compare_err_pb_and && (prbs_dqs_tap_cnt_r > MIN_WIN )) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin + prbs_state_r <= #TCQ FINE_CALC_TAPS; + //if all right edge are alined (all right edge found at the same time), update smallest right edge in here + //doesnt need to set right_edge_found to 1 since it is not used after this stage + if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1; + end else begin + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; //keep increase until all fail + end + num_samples_done_ind <= num_samples_done_r; + end + end + //for fine_inc stage, inc all fine delay + //for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain) + // put phaser_in taps to the center + FINE_CALC_TAPS: begin + if(num_samples_done_ind || num_samples_done_r) begin + num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set + right_edge_found <= #TCQ 1'b0; //reset right edge found + match_flag_and <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits + match_flag_or <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits + no_err_win_detected <= #TCQ 1'b0; + no_err_win_detected_latch <= #TCQ 1'b0; + prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT; + valid_window_cnt <= #TCQ 2'd0; //reset valid window counter + end + end + + FINE_CALC_TAPS_WAIT: begin //wait for ROM read out + if(stage_cnt == 'd2) begin //last stage : back to center + if(center_comp) begin + fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1 + fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error; + end else begin + fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1 + fine_dly_error <= #TCQ 1'b0; + end + end else begin + fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r; + end + if (bit_cnt == DRAM_WIDTH) begin + fine_delay_sel <= #TCQ 'b1; + stage_cnt <= #TCQ stage_cnt + 1; + prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC; + end + + end + + //wait for finishing the read before PI movement + RD_DONE_WAIT_FOR_PI_INC_DEC: begin + if (complex_act_start & ~complex_rdlvl_err) + prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC: PRBS_DEC_DQS; + end + + // Done with this stage of calibration + PRBS_DONE: begin + prbs_prech_req_r <= #TCQ 1'b0; + prbs_last_byte_done <= #TCQ 1'b0; + prbs_rdlvl_done <= #TCQ ~complex_rdlvl_err; + reset_rd_addr <= #TCQ 1'b0; + end + + endcase + end + + //ROM generation for dec counter + always @ (largest_left_edge or smallest_right_edge) begin + case ({largest_left_edge, smallest_right_edge}) + 12'd0 : mem_out_dec = 6'b111111; + 12'd1 : mem_out_dec = 6'b111111; + 12'd2 : mem_out_dec = 6'b111111; + 12'd3 : mem_out_dec = 6'b111111; + 12'd4 : mem_out_dec = 6'b111111; + 12'd5 : mem_out_dec = 6'b111111; + 12'd6 : mem_out_dec = 6'b000100; + 12'd7 : mem_out_dec = 6'b000101; + 12'd8 : mem_out_dec = 6'b000101; + 12'd9 : mem_out_dec = 6'b000110; + 12'd10 : mem_out_dec = 6'b000110; + 12'd11 : mem_out_dec = 6'b000111; + 12'd12 : mem_out_dec = 6'b001000; + 12'd13 : mem_out_dec = 6'b001000; + 12'd14 : mem_out_dec = 6'b001001; + 12'd15 : mem_out_dec = 6'b001010; + 12'd16 : mem_out_dec = 6'b001010; + 12'd17 : mem_out_dec = 6'b001011; + 12'd18 : mem_out_dec = 6'b001011; + 12'd19 : mem_out_dec = 6'b001100; + 12'd20 : mem_out_dec = 6'b001100; + 12'd21 : mem_out_dec = 6'b001100; + 12'd22 : mem_out_dec = 6'b001100; + 12'd23 : mem_out_dec = 6'b001101; + 12'd24 : mem_out_dec = 6'b001100; + 12'd25 : mem_out_dec = 6'b001100; + 12'd26 : mem_out_dec = 6'b001101; + 12'd27 : mem_out_dec = 6'b001110; + 12'd28 : mem_out_dec = 6'b001110; + 12'd29 : mem_out_dec = 6'b001111; + 12'd30 : mem_out_dec = 6'b010000; + 12'd31 : mem_out_dec = 6'b010001; + 12'd32 : mem_out_dec = 6'b010001; + 12'd33 : mem_out_dec = 6'b010010; + 12'd34 : mem_out_dec = 6'b010010; + 12'd35 : mem_out_dec = 6'b010010; + 12'd36 : mem_out_dec = 6'b010011; + 12'd37 : mem_out_dec = 6'b010100; + 12'd38 : mem_out_dec = 6'b010100; + 12'd39 : mem_out_dec = 6'b010101; + 12'd40 : mem_out_dec = 6'b010101; + 12'd41 : mem_out_dec = 6'b010110; + 12'd42 : mem_out_dec = 6'b010110; + 12'd43 : mem_out_dec = 6'b010111; + 12'd44 : mem_out_dec = 6'b011000; + 12'd45 : mem_out_dec = 6'b011001; + 12'd46 : mem_out_dec = 6'b011001; + 12'd47 : mem_out_dec = 6'b011010; + 12'd48 : mem_out_dec = 6'b011010; + 12'd49 : mem_out_dec = 6'b011011; + 12'd50 : mem_out_dec = 6'b011011; + 12'd51 : mem_out_dec = 6'b011100; + 12'd52 : mem_out_dec = 6'b011100; + 12'd53 : mem_out_dec = 6'b011100; + 12'd54 : mem_out_dec = 6'b011100; + 12'd55 : mem_out_dec = 6'b011100; + 12'd56 : mem_out_dec = 6'b011100; + 12'd57 : mem_out_dec = 6'b011100; + 12'd58 : mem_out_dec = 6'b011100; + 12'd59 : mem_out_dec = 6'b011101; + 12'd60 : mem_out_dec = 6'b011110; + 12'd61 : mem_out_dec = 6'b011111; + 12'd62 : mem_out_dec = 6'b100000; + 12'd63 : mem_out_dec = 6'b100000; + 12'd64 : mem_out_dec = 6'b111111; + 12'd65 : mem_out_dec = 6'b111111; + 12'd66 : mem_out_dec = 6'b111111; + 12'd67 : mem_out_dec = 6'b111111; + 12'd68 : mem_out_dec = 6'b111111; + 12'd69 : mem_out_dec = 6'b111111; + 12'd70 : mem_out_dec = 6'b111111; + 12'd71 : mem_out_dec = 6'b000100; + 12'd72 : mem_out_dec = 6'b000100; + 12'd73 : mem_out_dec = 6'b000101; + 12'd74 : mem_out_dec = 6'b000110; + 12'd75 : mem_out_dec = 6'b000111; + 12'd76 : mem_out_dec = 6'b000111; + 12'd77 : mem_out_dec = 6'b001000; + 12'd78 : mem_out_dec = 6'b001001; + 12'd79 : mem_out_dec = 6'b001001; + 12'd80 : mem_out_dec = 6'b001010; + 12'd81 : mem_out_dec = 6'b001010; + 12'd82 : mem_out_dec = 6'b001011; + 12'd83 : mem_out_dec = 6'b001011; + 12'd84 : mem_out_dec = 6'b001011; + 12'd85 : mem_out_dec = 6'b001011; + 12'd86 : mem_out_dec = 6'b001011; + 12'd87 : mem_out_dec = 6'b001100; + 12'd88 : mem_out_dec = 6'b001011; + 12'd89 : mem_out_dec = 6'b001100; + 12'd90 : mem_out_dec = 6'b001100; + 12'd91 : mem_out_dec = 6'b001101; + 12'd92 : mem_out_dec = 6'b001110; + 12'd93 : mem_out_dec = 6'b001111; + 12'd94 : mem_out_dec = 6'b001111; + 12'd95 : mem_out_dec = 6'b010000; + 12'd96 : mem_out_dec = 6'b010001; + 12'd97 : mem_out_dec = 6'b010001; + 12'd98 : mem_out_dec = 6'b010010; + 12'd99 : mem_out_dec = 6'b010010; + 12'd100 : mem_out_dec = 6'b010011; + 12'd101 : mem_out_dec = 6'b010011; + 12'd102 : mem_out_dec = 6'b010100; + 12'd103 : mem_out_dec = 6'b010100; + 12'd104 : mem_out_dec = 6'b010100; + 12'd105 : mem_out_dec = 6'b010101; + 12'd106 : mem_out_dec = 6'b010110; + 12'd107 : mem_out_dec = 6'b010111; + 12'd108 : mem_out_dec = 6'b010111; + 12'd109 : mem_out_dec = 6'b011000; + 12'd110 : mem_out_dec = 6'b011001; + 12'd111 : mem_out_dec = 6'b011001; + 12'd112 : mem_out_dec = 6'b011010; + 12'd113 : mem_out_dec = 6'b011010; + 12'd114 : mem_out_dec = 6'b011011; + 12'd115 : mem_out_dec = 6'b011011; + 12'd116 : mem_out_dec = 6'b011011; + 12'd117 : mem_out_dec = 6'b011011; + 12'd118 : mem_out_dec = 6'b011011; + 12'd119 : mem_out_dec = 6'b011011; + 12'd120 : mem_out_dec = 6'b011011; + 12'd121 : mem_out_dec = 6'b011011; + 12'd122 : mem_out_dec = 6'b011100; + 12'd123 : mem_out_dec = 6'b011101; + 12'd124 : mem_out_dec = 6'b011110; + 12'd125 : mem_out_dec = 6'b011110; + 12'd126 : mem_out_dec = 6'b011111; + 12'd127 : mem_out_dec = 6'b100000; + 12'd128 : mem_out_dec = 6'b111111; + 12'd129 : mem_out_dec = 6'b111111; + 12'd130 : mem_out_dec = 6'b111111; + 12'd131 : mem_out_dec = 6'b111111; + 12'd132 : mem_out_dec = 6'b111111; + 12'd133 : mem_out_dec = 6'b111111; + 12'd134 : mem_out_dec = 6'b111111; + 12'd135 : mem_out_dec = 6'b111111; + 12'd136 : mem_out_dec = 6'b000100; + 12'd137 : mem_out_dec = 6'b000101; + 12'd138 : mem_out_dec = 6'b000101; + 12'd139 : mem_out_dec = 6'b000110; + 12'd140 : mem_out_dec = 6'b000110; + 12'd141 : mem_out_dec = 6'b000111; + 12'd142 : mem_out_dec = 6'b001000; + 12'd143 : mem_out_dec = 6'b001001; + 12'd144 : mem_out_dec = 6'b001001; + 12'd145 : mem_out_dec = 6'b001010; + 12'd146 : mem_out_dec = 6'b001010; + 12'd147 : mem_out_dec = 6'b001010; + 12'd148 : mem_out_dec = 6'b001010; + 12'd149 : mem_out_dec = 6'b001010; + 12'd150 : mem_out_dec = 6'b001010; + 12'd151 : mem_out_dec = 6'b001011; + 12'd152 : mem_out_dec = 6'b001010; + 12'd153 : mem_out_dec = 6'b001011; + 12'd154 : mem_out_dec = 6'b001100; + 12'd155 : mem_out_dec = 6'b001101; + 12'd156 : mem_out_dec = 6'b001101; + 12'd157 : mem_out_dec = 6'b001110; + 12'd158 : mem_out_dec = 6'b001111; + 12'd159 : mem_out_dec = 6'b010000; + 12'd160 : mem_out_dec = 6'b010000; + 12'd161 : mem_out_dec = 6'b010001; + 12'd162 : mem_out_dec = 6'b010001; + 12'd163 : mem_out_dec = 6'b010010; + 12'd164 : mem_out_dec = 6'b010010; + 12'd165 : mem_out_dec = 6'b010011; + 12'd166 : mem_out_dec = 6'b010011; + 12'd167 : mem_out_dec = 6'b010100; + 12'd168 : mem_out_dec = 6'b010100; + 12'd169 : mem_out_dec = 6'b010101; + 12'd170 : mem_out_dec = 6'b010101; + 12'd171 : mem_out_dec = 6'b010110; + 12'd172 : mem_out_dec = 6'b010111; + 12'd173 : mem_out_dec = 6'b010111; + 12'd174 : mem_out_dec = 6'b011000; + 12'd175 : mem_out_dec = 6'b011001; + 12'd176 : mem_out_dec = 6'b011001; + 12'd177 : mem_out_dec = 6'b011010; + 12'd178 : mem_out_dec = 6'b011010; + 12'd179 : mem_out_dec = 6'b011010; + 12'd180 : mem_out_dec = 6'b011010; + 12'd181 : mem_out_dec = 6'b011010; + 12'd182 : mem_out_dec = 6'b011010; + 12'd183 : mem_out_dec = 6'b011010; + 12'd184 : mem_out_dec = 6'b011010; + 12'd185 : mem_out_dec = 6'b011011; + 12'd186 : mem_out_dec = 6'b011100; + 12'd187 : mem_out_dec = 6'b011100; + 12'd188 : mem_out_dec = 6'b011101; + 12'd189 : mem_out_dec = 6'b011110; + 12'd190 : mem_out_dec = 6'b011111; + 12'd191 : mem_out_dec = 6'b100000; + 12'd192 : mem_out_dec = 6'b111111; + 12'd193 : mem_out_dec = 6'b111111; + 12'd194 : mem_out_dec = 6'b111111; + 12'd195 : mem_out_dec = 6'b111111; + 12'd196 : mem_out_dec = 6'b111111; + 12'd197 : mem_out_dec = 6'b111111; + 12'd198 : mem_out_dec = 6'b111111; + 12'd199 : mem_out_dec = 6'b111111; + 12'd200 : mem_out_dec = 6'b111111; + 12'd201 : mem_out_dec = 6'b000100; + 12'd202 : mem_out_dec = 6'b000100; + 12'd203 : mem_out_dec = 6'b000101; + 12'd204 : mem_out_dec = 6'b000110; + 12'd205 : mem_out_dec = 6'b000111; + 12'd206 : mem_out_dec = 6'b001000; + 12'd207 : mem_out_dec = 6'b001000; + 12'd208 : mem_out_dec = 6'b001001; + 12'd209 : mem_out_dec = 6'b001001; + 12'd210 : mem_out_dec = 6'b001001; + 12'd211 : mem_out_dec = 6'b001001; + 12'd212 : mem_out_dec = 6'b001001; + 12'd213 : mem_out_dec = 6'b001001; + 12'd214 : mem_out_dec = 6'b001001; + 12'd215 : mem_out_dec = 6'b001010; + 12'd216 : mem_out_dec = 6'b001010; + 12'd217 : mem_out_dec = 6'b001011; + 12'd218 : mem_out_dec = 6'b001011; + 12'd219 : mem_out_dec = 6'b001100; + 12'd220 : mem_out_dec = 6'b001101; + 12'd221 : mem_out_dec = 6'b001110; + 12'd222 : mem_out_dec = 6'b001111; + 12'd223 : mem_out_dec = 6'b001111; + 12'd224 : mem_out_dec = 6'b010000; + 12'd225 : mem_out_dec = 6'b010000; + 12'd226 : mem_out_dec = 6'b010001; + 12'd227 : mem_out_dec = 6'b010001; + 12'd228 : mem_out_dec = 6'b010010; + 12'd229 : mem_out_dec = 6'b010010; + 12'd230 : mem_out_dec = 6'b010011; + 12'd231 : mem_out_dec = 6'b010011; + 12'd232 : mem_out_dec = 6'b010011; + 12'd233 : mem_out_dec = 6'b010100; + 12'd234 : mem_out_dec = 6'b010100; + 12'd235 : mem_out_dec = 6'b010101; + 12'd236 : mem_out_dec = 6'b010110; + 12'd237 : mem_out_dec = 6'b010111; + 12'd238 : mem_out_dec = 6'b011000; + 12'd239 : mem_out_dec = 6'b011000; + 12'd240 : mem_out_dec = 6'b011001; + 12'd241 : mem_out_dec = 6'b011001; + 12'd242 : mem_out_dec = 6'b011001; + 12'd243 : mem_out_dec = 6'b011001; + 12'd244 : mem_out_dec = 6'b011001; + 12'd245 : mem_out_dec = 6'b011001; + 12'd246 : mem_out_dec = 6'b011001; + 12'd247 : mem_out_dec = 6'b011001; + 12'd248 : mem_out_dec = 6'b011010; + 12'd249 : mem_out_dec = 6'b011010; + 12'd250 : mem_out_dec = 6'b011011; + 12'd251 : mem_out_dec = 6'b011100; + 12'd252 : mem_out_dec = 6'b011101; + 12'd253 : mem_out_dec = 6'b011110; + 12'd254 : mem_out_dec = 6'b011110; + 12'd255 : mem_out_dec = 6'b011111; + 12'd256 : mem_out_dec = 6'b111111; + 12'd257 : mem_out_dec = 6'b111111; + 12'd258 : mem_out_dec = 6'b111111; + 12'd259 : mem_out_dec = 6'b111111; + 12'd260 : mem_out_dec = 6'b111111; + 12'd261 : mem_out_dec = 6'b111111; + 12'd262 : mem_out_dec = 6'b111111; + 12'd263 : mem_out_dec = 6'b111111; + 12'd264 : mem_out_dec = 6'b111111; + 12'd265 : mem_out_dec = 6'b111111; + 12'd266 : mem_out_dec = 6'b000100; + 12'd267 : mem_out_dec = 6'b000101; + 12'd268 : mem_out_dec = 6'b000110; + 12'd269 : mem_out_dec = 6'b000110; + 12'd270 : mem_out_dec = 6'b000111; + 12'd271 : mem_out_dec = 6'b001000; + 12'd272 : mem_out_dec = 6'b001000; + 12'd273 : mem_out_dec = 6'b001000; + 12'd274 : mem_out_dec = 6'b001000; + 12'd275 : mem_out_dec = 6'b001000; + 12'd276 : mem_out_dec = 6'b001000; + 12'd277 : mem_out_dec = 6'b001000; + 12'd278 : mem_out_dec = 6'b001000; + 12'd279 : mem_out_dec = 6'b001001; + 12'd280 : mem_out_dec = 6'b001001; + 12'd281 : mem_out_dec = 6'b001010; + 12'd282 : mem_out_dec = 6'b001011; + 12'd283 : mem_out_dec = 6'b001100; + 12'd284 : mem_out_dec = 6'b001101; + 12'd285 : mem_out_dec = 6'b001101; + 12'd286 : mem_out_dec = 6'b001110; + 12'd287 : mem_out_dec = 6'b001111; + 12'd288 : mem_out_dec = 6'b001111; + 12'd289 : mem_out_dec = 6'b010000; + 12'd290 : mem_out_dec = 6'b010000; + 12'd291 : mem_out_dec = 6'b010001; + 12'd292 : mem_out_dec = 6'b010001; + 12'd293 : mem_out_dec = 6'b010010; + 12'd294 : mem_out_dec = 6'b010010; + 12'd295 : mem_out_dec = 6'b010011; + 12'd296 : mem_out_dec = 6'b010010; + 12'd297 : mem_out_dec = 6'b010011; + 12'd298 : mem_out_dec = 6'b010100; + 12'd299 : mem_out_dec = 6'b010101; + 12'd300 : mem_out_dec = 6'b010110; + 12'd301 : mem_out_dec = 6'b010110; + 12'd302 : mem_out_dec = 6'b010111; + 12'd303 : mem_out_dec = 6'b011000; + 12'd304 : mem_out_dec = 6'b011000; + 12'd305 : mem_out_dec = 6'b011000; + 12'd306 : mem_out_dec = 6'b011000; + 12'd307 : mem_out_dec = 6'b011000; + 12'd308 : mem_out_dec = 6'b011000; + 12'd309 : mem_out_dec = 6'b011000; + 12'd310 : mem_out_dec = 6'b011000; + 12'd311 : mem_out_dec = 6'b011001; + 12'd312 : mem_out_dec = 6'b011001; + 12'd313 : mem_out_dec = 6'b011010; + 12'd314 : mem_out_dec = 6'b011011; + 12'd315 : mem_out_dec = 6'b011100; + 12'd316 : mem_out_dec = 6'b011100; + 12'd317 : mem_out_dec = 6'b011101; + 12'd318 : mem_out_dec = 6'b011110; + 12'd319 : mem_out_dec = 6'b011111; + 12'd320 : mem_out_dec = 6'b111111; + 12'd321 : mem_out_dec = 6'b111111; + 12'd322 : mem_out_dec = 6'b111111; + 12'd323 : mem_out_dec = 6'b111111; + 12'd324 : mem_out_dec = 6'b111111; + 12'd325 : mem_out_dec = 6'b111111; + 12'd326 : mem_out_dec = 6'b111111; + 12'd327 : mem_out_dec = 6'b111111; + 12'd328 : mem_out_dec = 6'b111111; + 12'd329 : mem_out_dec = 6'b111111; + 12'd330 : mem_out_dec = 6'b111111; + 12'd331 : mem_out_dec = 6'b000100; + 12'd332 : mem_out_dec = 6'b000101; + 12'd333 : mem_out_dec = 6'b000110; + 12'd334 : mem_out_dec = 6'b000111; + 12'd335 : mem_out_dec = 6'b001000; + 12'd336 : mem_out_dec = 6'b000111; + 12'd337 : mem_out_dec = 6'b000111; + 12'd338 : mem_out_dec = 6'b000111; + 12'd339 : mem_out_dec = 6'b000111; + 12'd340 : mem_out_dec = 6'b000111; + 12'd341 : mem_out_dec = 6'b000111; + 12'd342 : mem_out_dec = 6'b001000; + 12'd343 : mem_out_dec = 6'b001001; + 12'd344 : mem_out_dec = 6'b001001; + 12'd345 : mem_out_dec = 6'b001010; + 12'd346 : mem_out_dec = 6'b001011; + 12'd347 : mem_out_dec = 6'b001011; + 12'd348 : mem_out_dec = 6'b001100; + 12'd349 : mem_out_dec = 6'b001101; + 12'd350 : mem_out_dec = 6'b001110; + 12'd351 : mem_out_dec = 6'b001110; + 12'd352 : mem_out_dec = 6'b001111; + 12'd353 : mem_out_dec = 6'b001111; + 12'd354 : mem_out_dec = 6'b010000; + 12'd355 : mem_out_dec = 6'b010000; + 12'd356 : mem_out_dec = 6'b010001; + 12'd357 : mem_out_dec = 6'b010001; + 12'd358 : mem_out_dec = 6'b010001; + 12'd359 : mem_out_dec = 6'b010010; + 12'd360 : mem_out_dec = 6'b010010; + 12'd361 : mem_out_dec = 6'b010011; + 12'd362 : mem_out_dec = 6'b010100; + 12'd363 : mem_out_dec = 6'b010100; + 12'd364 : mem_out_dec = 6'b010101; + 12'd365 : mem_out_dec = 6'b010110; + 12'd366 : mem_out_dec = 6'b010111; + 12'd367 : mem_out_dec = 6'b011000; + 12'd368 : mem_out_dec = 6'b010111; + 12'd369 : mem_out_dec = 6'b010111; + 12'd370 : mem_out_dec = 6'b010111; + 12'd371 : mem_out_dec = 6'b010111; + 12'd372 : mem_out_dec = 6'b010111; + 12'd373 : mem_out_dec = 6'b010111; + 12'd374 : mem_out_dec = 6'b011000; + 12'd375 : mem_out_dec = 6'b011001; + 12'd376 : mem_out_dec = 6'b011001; + 12'd377 : mem_out_dec = 6'b011010; + 12'd378 : mem_out_dec = 6'b011010; + 12'd379 : mem_out_dec = 6'b011011; + 12'd380 : mem_out_dec = 6'b011100; + 12'd381 : mem_out_dec = 6'b011101; + 12'd382 : mem_out_dec = 6'b011101; + 12'd383 : mem_out_dec = 6'b011110; + 12'd384 : mem_out_dec = 6'b111111; + 12'd385 : mem_out_dec = 6'b111111; + 12'd386 : mem_out_dec = 6'b111111; + 12'd387 : mem_out_dec = 6'b111111; + 12'd388 : mem_out_dec = 6'b111111; + 12'd389 : mem_out_dec = 6'b111111; + 12'd390 : mem_out_dec = 6'b111111; + 12'd391 : mem_out_dec = 6'b111111; + 12'd392 : mem_out_dec = 6'b111111; + 12'd393 : mem_out_dec = 6'b111111; + 12'd394 : mem_out_dec = 6'b111111; + 12'd395 : mem_out_dec = 6'b111111; + 12'd396 : mem_out_dec = 6'b000101; + 12'd397 : mem_out_dec = 6'b000110; + 12'd398 : mem_out_dec = 6'b000110; + 12'd399 : mem_out_dec = 6'b000111; + 12'd400 : mem_out_dec = 6'b000110; + 12'd401 : mem_out_dec = 6'b000110; + 12'd402 : mem_out_dec = 6'b000110; + 12'd403 : mem_out_dec = 6'b000110; + 12'd404 : mem_out_dec = 6'b000110; + 12'd405 : mem_out_dec = 6'b000111; + 12'd406 : mem_out_dec = 6'b001000; + 12'd407 : mem_out_dec = 6'b001000; + 12'd408 : mem_out_dec = 6'b001001; + 12'd409 : mem_out_dec = 6'b001001; + 12'd410 : mem_out_dec = 6'b001010; + 12'd411 : mem_out_dec = 6'b001011; + 12'd412 : mem_out_dec = 6'b001100; + 12'd413 : mem_out_dec = 6'b001100; + 12'd414 : mem_out_dec = 6'b001101; + 12'd415 : mem_out_dec = 6'b001110; + 12'd416 : mem_out_dec = 6'b001110; + 12'd417 : mem_out_dec = 6'b001111; + 12'd418 : mem_out_dec = 6'b001111; + 12'd419 : mem_out_dec = 6'b010000; + 12'd420 : mem_out_dec = 6'b010000; + 12'd421 : mem_out_dec = 6'b010000; + 12'd422 : mem_out_dec = 6'b010001; + 12'd423 : mem_out_dec = 6'b010001; + 12'd424 : mem_out_dec = 6'b010010; + 12'd425 : mem_out_dec = 6'b010011; + 12'd426 : mem_out_dec = 6'b010011; + 12'd427 : mem_out_dec = 6'b010100; + 12'd428 : mem_out_dec = 6'b010101; + 12'd429 : mem_out_dec = 6'b010110; + 12'd430 : mem_out_dec = 6'b010111; + 12'd431 : mem_out_dec = 6'b010111; + 12'd432 : mem_out_dec = 6'b010110; + 12'd433 : mem_out_dec = 6'b010110; + 12'd434 : mem_out_dec = 6'b010110; + 12'd435 : mem_out_dec = 6'b010110; + 12'd436 : mem_out_dec = 6'b010110; + 12'd437 : mem_out_dec = 6'b010111; + 12'd438 : mem_out_dec = 6'b010111; + 12'd439 : mem_out_dec = 6'b011000; + 12'd440 : mem_out_dec = 6'b011001; + 12'd441 : mem_out_dec = 6'b011001; + 12'd442 : mem_out_dec = 6'b011010; + 12'd443 : mem_out_dec = 6'b011011; + 12'd444 : mem_out_dec = 6'b011011; + 12'd445 : mem_out_dec = 6'b011100; + 12'd446 : mem_out_dec = 6'b011101; + 12'd447 : mem_out_dec = 6'b011110; + 12'd448 : mem_out_dec = 6'b111111; + 12'd449 : mem_out_dec = 6'b111111; + 12'd450 : mem_out_dec = 6'b111111; + 12'd451 : mem_out_dec = 6'b111111; + 12'd452 : mem_out_dec = 6'b111111; + 12'd453 : mem_out_dec = 6'b111111; + 12'd454 : mem_out_dec = 6'b111111; + 12'd455 : mem_out_dec = 6'b111111; + 12'd456 : mem_out_dec = 6'b111111; + 12'd457 : mem_out_dec = 6'b111111; + 12'd458 : mem_out_dec = 6'b111111; + 12'd459 : mem_out_dec = 6'b111111; + 12'd460 : mem_out_dec = 6'b111111; + 12'd461 : mem_out_dec = 6'b000101; + 12'd462 : mem_out_dec = 6'b000110; + 12'd463 : mem_out_dec = 6'b000110; + 12'd464 : mem_out_dec = 6'b000110; + 12'd465 : mem_out_dec = 6'b000110; + 12'd466 : mem_out_dec = 6'b000110; + 12'd467 : mem_out_dec = 6'b000110; + 12'd468 : mem_out_dec = 6'b000110; + 12'd469 : mem_out_dec = 6'b000111; + 12'd470 : mem_out_dec = 6'b000111; + 12'd471 : mem_out_dec = 6'b001000; + 12'd472 : mem_out_dec = 6'b001000; + 12'd473 : mem_out_dec = 6'b001001; + 12'd474 : mem_out_dec = 6'b001010; + 12'd475 : mem_out_dec = 6'b001011; + 12'd476 : mem_out_dec = 6'b001011; + 12'd477 : mem_out_dec = 6'b001100; + 12'd478 : mem_out_dec = 6'b001101; + 12'd479 : mem_out_dec = 6'b001110; + 12'd480 : mem_out_dec = 6'b001110; + 12'd481 : mem_out_dec = 6'b001110; + 12'd482 : mem_out_dec = 6'b001111; + 12'd483 : mem_out_dec = 6'b001111; + 12'd484 : mem_out_dec = 6'b010000; + 12'd485 : mem_out_dec = 6'b010000; + 12'd486 : mem_out_dec = 6'b010000; + 12'd487 : mem_out_dec = 6'b010001; + 12'd488 : mem_out_dec = 6'b010001; + 12'd489 : mem_out_dec = 6'b010010; + 12'd490 : mem_out_dec = 6'b010011; + 12'd491 : mem_out_dec = 6'b010100; + 12'd492 : mem_out_dec = 6'b010101; + 12'd493 : mem_out_dec = 6'b010101; + 12'd494 : mem_out_dec = 6'b010110; + 12'd495 : mem_out_dec = 6'b010110; + 12'd496 : mem_out_dec = 6'b010110; + 12'd497 : mem_out_dec = 6'b010110; + 12'd498 : mem_out_dec = 6'b010101; + 12'd499 : mem_out_dec = 6'b010101; + 12'd500 : mem_out_dec = 6'b010110; + 12'd501 : mem_out_dec = 6'b010111; + 12'd502 : mem_out_dec = 6'b010111; + 12'd503 : mem_out_dec = 6'b011000; + 12'd504 : mem_out_dec = 6'b011000; + 12'd505 : mem_out_dec = 6'b011001; + 12'd506 : mem_out_dec = 6'b011010; + 12'd507 : mem_out_dec = 6'b011010; + 12'd508 : mem_out_dec = 6'b011011; + 12'd509 : mem_out_dec = 6'b011100; + 12'd510 : mem_out_dec = 6'b011101; + 12'd511 : mem_out_dec = 6'b011101; + 12'd512 : mem_out_dec = 6'b111111; + 12'd513 : mem_out_dec = 6'b111111; + 12'd514 : mem_out_dec = 6'b111111; + 12'd515 : mem_out_dec = 6'b111111; + 12'd516 : mem_out_dec = 6'b111111; + 12'd517 : mem_out_dec = 6'b111111; + 12'd518 : mem_out_dec = 6'b111111; + 12'd519 : mem_out_dec = 6'b111111; + 12'd520 : mem_out_dec = 6'b111111; + 12'd521 : mem_out_dec = 6'b111111; + 12'd522 : mem_out_dec = 6'b111111; + 12'd523 : mem_out_dec = 6'b111111; + 12'd524 : mem_out_dec = 6'b111111; + 12'd525 : mem_out_dec = 6'b111111; + 12'd526 : mem_out_dec = 6'b000100; + 12'd527 : mem_out_dec = 6'b000101; + 12'd528 : mem_out_dec = 6'b000100; + 12'd529 : mem_out_dec = 6'b000100; + 12'd530 : mem_out_dec = 6'b000100; + 12'd531 : mem_out_dec = 6'b000101; + 12'd532 : mem_out_dec = 6'b000101; + 12'd533 : mem_out_dec = 6'b000110; + 12'd534 : mem_out_dec = 6'b000111; + 12'd535 : mem_out_dec = 6'b000111; + 12'd536 : mem_out_dec = 6'b000111; + 12'd537 : mem_out_dec = 6'b001000; + 12'd538 : mem_out_dec = 6'b001001; + 12'd539 : mem_out_dec = 6'b001010; + 12'd540 : mem_out_dec = 6'b001011; + 12'd541 : mem_out_dec = 6'b001011; + 12'd542 : mem_out_dec = 6'b001100; + 12'd543 : mem_out_dec = 6'b001101; + 12'd544 : mem_out_dec = 6'b001101; + 12'd545 : mem_out_dec = 6'b001101; + 12'd546 : mem_out_dec = 6'b001110; + 12'd547 : mem_out_dec = 6'b001110; + 12'd548 : mem_out_dec = 6'b001110; + 12'd549 : mem_out_dec = 6'b001111; + 12'd550 : mem_out_dec = 6'b010000; + 12'd551 : mem_out_dec = 6'b010000; + 12'd552 : mem_out_dec = 6'b010001; + 12'd553 : mem_out_dec = 6'b010001; + 12'd554 : mem_out_dec = 6'b010010; + 12'd555 : mem_out_dec = 6'b010010; + 12'd556 : mem_out_dec = 6'b010011; + 12'd557 : mem_out_dec = 6'b010100; + 12'd558 : mem_out_dec = 6'b010100; + 12'd559 : mem_out_dec = 6'b010100; + 12'd560 : mem_out_dec = 6'b010100; + 12'd561 : mem_out_dec = 6'b010100; + 12'd562 : mem_out_dec = 6'b010100; + 12'd563 : mem_out_dec = 6'b010101; + 12'd564 : mem_out_dec = 6'b010101; + 12'd565 : mem_out_dec = 6'b010110; + 12'd566 : mem_out_dec = 6'b010111; + 12'd567 : mem_out_dec = 6'b010111; + 12'd568 : mem_out_dec = 6'b010111; + 12'd569 : mem_out_dec = 6'b011000; + 12'd570 : mem_out_dec = 6'b011001; + 12'd571 : mem_out_dec = 6'b011010; + 12'd572 : mem_out_dec = 6'b011010; + 12'd573 : mem_out_dec = 6'b011011; + 12'd574 : mem_out_dec = 6'b011100; + 12'd575 : mem_out_dec = 6'b011101; + 12'd576 : mem_out_dec = 6'b111111; + 12'd577 : mem_out_dec = 6'b111111; + 12'd578 : mem_out_dec = 6'b111111; + 12'd579 : mem_out_dec = 6'b111111; + 12'd580 : mem_out_dec = 6'b111111; + 12'd581 : mem_out_dec = 6'b111111; + 12'd582 : mem_out_dec = 6'b111111; + 12'd583 : mem_out_dec = 6'b111111; + 12'd584 : mem_out_dec = 6'b111111; + 12'd585 : mem_out_dec = 6'b111111; + 12'd586 : mem_out_dec = 6'b111111; + 12'd587 : mem_out_dec = 6'b111111; + 12'd588 : mem_out_dec = 6'b111111; + 12'd589 : mem_out_dec = 6'b111111; + 12'd590 : mem_out_dec = 6'b111111; + 12'd591 : mem_out_dec = 6'b000100; + 12'd592 : mem_out_dec = 6'b000011; + 12'd593 : mem_out_dec = 6'b000011; + 12'd594 : mem_out_dec = 6'b000100; + 12'd595 : mem_out_dec = 6'b000101; + 12'd596 : mem_out_dec = 6'b000101; + 12'd597 : mem_out_dec = 6'b000110; + 12'd598 : mem_out_dec = 6'b000110; + 12'd599 : mem_out_dec = 6'b000111; + 12'd600 : mem_out_dec = 6'b000111; + 12'd601 : mem_out_dec = 6'b001000; + 12'd602 : mem_out_dec = 6'b001001; + 12'd603 : mem_out_dec = 6'b001010; + 12'd604 : mem_out_dec = 6'b001010; + 12'd605 : mem_out_dec = 6'b001011; + 12'd606 : mem_out_dec = 6'b001100; + 12'd607 : mem_out_dec = 6'b001101; + 12'd608 : mem_out_dec = 6'b001101; + 12'd609 : mem_out_dec = 6'b001101; + 12'd610 : mem_out_dec = 6'b001110; + 12'd611 : mem_out_dec = 6'b001110; + 12'd612 : mem_out_dec = 6'b001110; + 12'd613 : mem_out_dec = 6'b001111; + 12'd614 : mem_out_dec = 6'b010000; + 12'd615 : mem_out_dec = 6'b010000; + 12'd616 : mem_out_dec = 6'b010000; + 12'd617 : mem_out_dec = 6'b010001; + 12'd618 : mem_out_dec = 6'b010001; + 12'd619 : mem_out_dec = 6'b010010; + 12'd620 : mem_out_dec = 6'b010010; + 12'd621 : mem_out_dec = 6'b010011; + 12'd622 : mem_out_dec = 6'b010011; + 12'd623 : mem_out_dec = 6'b010100; + 12'd624 : mem_out_dec = 6'b010011; + 12'd625 : mem_out_dec = 6'b010011; + 12'd626 : mem_out_dec = 6'b010100; + 12'd627 : mem_out_dec = 6'b010100; + 12'd628 : mem_out_dec = 6'b010101; + 12'd629 : mem_out_dec = 6'b010110; + 12'd630 : mem_out_dec = 6'b010110; + 12'd631 : mem_out_dec = 6'b010111; + 12'd632 : mem_out_dec = 6'b010111; + 12'd633 : mem_out_dec = 6'b011000; + 12'd634 : mem_out_dec = 6'b011001; + 12'd635 : mem_out_dec = 6'b011001; + 12'd636 : mem_out_dec = 6'b011010; + 12'd637 : mem_out_dec = 6'b011011; + 12'd638 : mem_out_dec = 6'b011100; + 12'd639 : mem_out_dec = 6'b011100; + 12'd640 : mem_out_dec = 6'b111111; + 12'd641 : mem_out_dec = 6'b111111; + 12'd642 : mem_out_dec = 6'b111111; + 12'd643 : mem_out_dec = 6'b111111; + 12'd644 : mem_out_dec = 6'b111111; + 12'd645 : mem_out_dec = 6'b111111; + 12'd646 : mem_out_dec = 6'b111111; + 12'd647 : mem_out_dec = 6'b111111; + 12'd648 : mem_out_dec = 6'b111111; + 12'd649 : mem_out_dec = 6'b111111; + 12'd650 : mem_out_dec = 6'b111111; + 12'd651 : mem_out_dec = 6'b111111; + 12'd652 : mem_out_dec = 6'b111111; + 12'd653 : mem_out_dec = 6'b111111; + 12'd654 : mem_out_dec = 6'b111111; + 12'd655 : mem_out_dec = 6'b111111; + 12'd656 : mem_out_dec = 6'b000011; + 12'd657 : mem_out_dec = 6'b000011; + 12'd658 : mem_out_dec = 6'b000100; + 12'd659 : mem_out_dec = 6'b000100; + 12'd660 : mem_out_dec = 6'b000101; + 12'd661 : mem_out_dec = 6'b000110; + 12'd662 : mem_out_dec = 6'b000110; + 12'd663 : mem_out_dec = 6'b000111; + 12'd664 : mem_out_dec = 6'b000111; + 12'd665 : mem_out_dec = 6'b001000; + 12'd666 : mem_out_dec = 6'b001001; + 12'd667 : mem_out_dec = 6'b001001; + 12'd668 : mem_out_dec = 6'b001010; + 12'd669 : mem_out_dec = 6'b001011; + 12'd670 : mem_out_dec = 6'b001100; + 12'd671 : mem_out_dec = 6'b001100; + 12'd672 : mem_out_dec = 6'b001100; + 12'd673 : mem_out_dec = 6'b001101; + 12'd674 : mem_out_dec = 6'b001101; + 12'd675 : mem_out_dec = 6'b001101; + 12'd676 : mem_out_dec = 6'b001110; + 12'd677 : mem_out_dec = 6'b001111; + 12'd678 : mem_out_dec = 6'b001111; + 12'd679 : mem_out_dec = 6'b010000; + 12'd680 : mem_out_dec = 6'b010000; + 12'd681 : mem_out_dec = 6'b010000; + 12'd682 : mem_out_dec = 6'b010001; + 12'd683 : mem_out_dec = 6'b010001; + 12'd684 : mem_out_dec = 6'b010010; + 12'd685 : mem_out_dec = 6'b010010; + 12'd686 : mem_out_dec = 6'b010011; + 12'd687 : mem_out_dec = 6'b010011; + 12'd688 : mem_out_dec = 6'b010011; + 12'd689 : mem_out_dec = 6'b010011; + 12'd690 : mem_out_dec = 6'b010100; + 12'd691 : mem_out_dec = 6'b010100; + 12'd692 : mem_out_dec = 6'b010101; + 12'd693 : mem_out_dec = 6'b010101; + 12'd694 : mem_out_dec = 6'b010110; + 12'd695 : mem_out_dec = 6'b010111; + 12'd696 : mem_out_dec = 6'b010111; + 12'd697 : mem_out_dec = 6'b011000; + 12'd698 : mem_out_dec = 6'b011000; + 12'd699 : mem_out_dec = 6'b011001; + 12'd700 : mem_out_dec = 6'b011010; + 12'd701 : mem_out_dec = 6'b011011; + 12'd702 : mem_out_dec = 6'b011011; + 12'd703 : mem_out_dec = 6'b011100; + 12'd704 : mem_out_dec = 6'b111111; + 12'd705 : mem_out_dec = 6'b111111; + 12'd706 : mem_out_dec = 6'b111111; + 12'd707 : mem_out_dec = 6'b111111; + 12'd708 : mem_out_dec = 6'b111111; + 12'd709 : mem_out_dec = 6'b111111; + 12'd710 : mem_out_dec = 6'b111111; + 12'd711 : mem_out_dec = 6'b111111; + 12'd712 : mem_out_dec = 6'b111111; + 12'd713 : mem_out_dec = 6'b111111; + 12'd714 : mem_out_dec = 6'b111111; + 12'd715 : mem_out_dec = 6'b111111; + 12'd716 : mem_out_dec = 6'b111111; + 12'd717 : mem_out_dec = 6'b111111; + 12'd718 : mem_out_dec = 6'b111111; + 12'd719 : mem_out_dec = 6'b111111; + 12'd720 : mem_out_dec = 6'b111111; + 12'd721 : mem_out_dec = 6'b000011; + 12'd722 : mem_out_dec = 6'b000100; + 12'd723 : mem_out_dec = 6'b000100; + 12'd724 : mem_out_dec = 6'b000101; + 12'd725 : mem_out_dec = 6'b000101; + 12'd726 : mem_out_dec = 6'b000110; + 12'd727 : mem_out_dec = 6'b000111; + 12'd728 : mem_out_dec = 6'b000111; + 12'd729 : mem_out_dec = 6'b000111; + 12'd730 : mem_out_dec = 6'b001000; + 12'd731 : mem_out_dec = 6'b001001; + 12'd732 : mem_out_dec = 6'b001010; + 12'd733 : mem_out_dec = 6'b001011; + 12'd734 : mem_out_dec = 6'b001011; + 12'd735 : mem_out_dec = 6'b001100; + 12'd736 : mem_out_dec = 6'b001100; + 12'd737 : mem_out_dec = 6'b001101; + 12'd738 : mem_out_dec = 6'b001101; + 12'd739 : mem_out_dec = 6'b001101; + 12'd740 : mem_out_dec = 6'b001110; + 12'd741 : mem_out_dec = 6'b001110; + 12'd742 : mem_out_dec = 6'b001111; + 12'd743 : mem_out_dec = 6'b010000; + 12'd744 : mem_out_dec = 6'b001111; + 12'd745 : mem_out_dec = 6'b010000; + 12'd746 : mem_out_dec = 6'b010000; + 12'd747 : mem_out_dec = 6'b010001; + 12'd748 : mem_out_dec = 6'b010001; + 12'd749 : mem_out_dec = 6'b010010; + 12'd750 : mem_out_dec = 6'b010010; + 12'd751 : mem_out_dec = 6'b010011; + 12'd752 : mem_out_dec = 6'b010010; + 12'd753 : mem_out_dec = 6'b010011; + 12'd754 : mem_out_dec = 6'b010011; + 12'd755 : mem_out_dec = 6'b010100; + 12'd756 : mem_out_dec = 6'b010101; + 12'd757 : mem_out_dec = 6'b010101; + 12'd758 : mem_out_dec = 6'b010110; + 12'd759 : mem_out_dec = 6'b010110; + 12'd760 : mem_out_dec = 6'b010111; + 12'd761 : mem_out_dec = 6'b010111; + 12'd762 : mem_out_dec = 6'b011000; + 12'd763 : mem_out_dec = 6'b011001; + 12'd764 : mem_out_dec = 6'b011010; + 12'd765 : mem_out_dec = 6'b011010; + 12'd766 : mem_out_dec = 6'b011011; + 12'd767 : mem_out_dec = 6'b011100; + 12'd768 : mem_out_dec = 6'b111111; + 12'd769 : mem_out_dec = 6'b111111; + 12'd770 : mem_out_dec = 6'b111111; + 12'd771 : mem_out_dec = 6'b111111; + 12'd772 : mem_out_dec = 6'b111111; + 12'd773 : mem_out_dec = 6'b111111; + 12'd774 : mem_out_dec = 6'b111111; + 12'd775 : mem_out_dec = 6'b111111; + 12'd776 : mem_out_dec = 6'b111111; + 12'd777 : mem_out_dec = 6'b111111; + 12'd778 : mem_out_dec = 6'b111111; + 12'd779 : mem_out_dec = 6'b111111; + 12'd780 : mem_out_dec = 6'b111111; + 12'd781 : mem_out_dec = 6'b111111; + 12'd782 : mem_out_dec = 6'b111111; + 12'd783 : mem_out_dec = 6'b111111; + 12'd784 : mem_out_dec = 6'b111111; + 12'd785 : mem_out_dec = 6'b111111; + 12'd786 : mem_out_dec = 6'b000011; + 12'd787 : mem_out_dec = 6'b000100; + 12'd788 : mem_out_dec = 6'b000101; + 12'd789 : mem_out_dec = 6'b000101; + 12'd790 : mem_out_dec = 6'b000110; + 12'd791 : mem_out_dec = 6'b000110; + 12'd792 : mem_out_dec = 6'b000110; + 12'd793 : mem_out_dec = 6'b000111; + 12'd794 : mem_out_dec = 6'b001000; + 12'd795 : mem_out_dec = 6'b001001; + 12'd796 : mem_out_dec = 6'b001010; + 12'd797 : mem_out_dec = 6'b001010; + 12'd798 : mem_out_dec = 6'b001011; + 12'd799 : mem_out_dec = 6'b001100; + 12'd800 : mem_out_dec = 6'b001100; + 12'd801 : mem_out_dec = 6'b001100; + 12'd802 : mem_out_dec = 6'b001101; + 12'd803 : mem_out_dec = 6'b001101; + 12'd804 : mem_out_dec = 6'b001110; + 12'd805 : mem_out_dec = 6'b001110; + 12'd806 : mem_out_dec = 6'b001111; + 12'd807 : mem_out_dec = 6'b010000; + 12'd808 : mem_out_dec = 6'b001111; + 12'd809 : mem_out_dec = 6'b001111; + 12'd810 : mem_out_dec = 6'b010000; + 12'd811 : mem_out_dec = 6'b010000; + 12'd812 : mem_out_dec = 6'b010001; + 12'd813 : mem_out_dec = 6'b010001; + 12'd814 : mem_out_dec = 6'b010010; + 12'd815 : mem_out_dec = 6'b010010; + 12'd816 : mem_out_dec = 6'b010010; + 12'd817 : mem_out_dec = 6'b010011; + 12'd818 : mem_out_dec = 6'b010011; + 12'd819 : mem_out_dec = 6'b010100; + 12'd820 : mem_out_dec = 6'b010100; + 12'd821 : mem_out_dec = 6'b010101; + 12'd822 : mem_out_dec = 6'b010110; + 12'd823 : mem_out_dec = 6'b010110; + 12'd824 : mem_out_dec = 6'b010110; + 12'd825 : mem_out_dec = 6'b010111; + 12'd826 : mem_out_dec = 6'b011000; + 12'd827 : mem_out_dec = 6'b011001; + 12'd828 : mem_out_dec = 6'b011001; + 12'd829 : mem_out_dec = 6'b011010; + 12'd830 : mem_out_dec = 6'b011011; + 12'd831 : mem_out_dec = 6'b011100; + 12'd832 : mem_out_dec = 6'b111111; + 12'd833 : mem_out_dec = 6'b111111; + 12'd834 : mem_out_dec = 6'b111111; + 12'd835 : mem_out_dec = 6'b111111; + 12'd836 : mem_out_dec = 6'b111111; + 12'd837 : mem_out_dec = 6'b111111; + 12'd838 : mem_out_dec = 6'b111111; + 12'd839 : mem_out_dec = 6'b111111; + 12'd840 : mem_out_dec = 6'b111111; + 12'd841 : mem_out_dec = 6'b111111; + 12'd842 : mem_out_dec = 6'b111111; + 12'd843 : mem_out_dec = 6'b111111; + 12'd844 : mem_out_dec = 6'b111111; + 12'd845 : mem_out_dec = 6'b111111; + 12'd846 : mem_out_dec = 6'b111111; + 12'd847 : mem_out_dec = 6'b111111; + 12'd848 : mem_out_dec = 6'b111111; + 12'd849 : mem_out_dec = 6'b111111; + 12'd850 : mem_out_dec = 6'b111111; + 12'd851 : mem_out_dec = 6'b000100; + 12'd852 : mem_out_dec = 6'b000100; + 12'd853 : mem_out_dec = 6'b000101; + 12'd854 : mem_out_dec = 6'b000101; + 12'd855 : mem_out_dec = 6'b000110; + 12'd856 : mem_out_dec = 6'b000110; + 12'd857 : mem_out_dec = 6'b000111; + 12'd858 : mem_out_dec = 6'b001000; + 12'd859 : mem_out_dec = 6'b001001; + 12'd860 : mem_out_dec = 6'b001001; + 12'd861 : mem_out_dec = 6'b001010; + 12'd862 : mem_out_dec = 6'b001011; + 12'd863 : mem_out_dec = 6'b001100; + 12'd864 : mem_out_dec = 6'b001100; + 12'd865 : mem_out_dec = 6'b001100; + 12'd866 : mem_out_dec = 6'b001100; + 12'd867 : mem_out_dec = 6'b001101; + 12'd868 : mem_out_dec = 6'b001101; + 12'd869 : mem_out_dec = 6'b001110; + 12'd870 : mem_out_dec = 6'b001111; + 12'd871 : mem_out_dec = 6'b001111; + 12'd872 : mem_out_dec = 6'b001110; + 12'd873 : mem_out_dec = 6'b001111; + 12'd874 : mem_out_dec = 6'b001111; + 12'd875 : mem_out_dec = 6'b010000; + 12'd876 : mem_out_dec = 6'b010000; + 12'd877 : mem_out_dec = 6'b010001; + 12'd878 : mem_out_dec = 6'b010001; + 12'd879 : mem_out_dec = 6'b010010; + 12'd880 : mem_out_dec = 6'b010010; + 12'd881 : mem_out_dec = 6'b010010; + 12'd882 : mem_out_dec = 6'b010011; + 12'd883 : mem_out_dec = 6'b010100; + 12'd884 : mem_out_dec = 6'b010100; + 12'd885 : mem_out_dec = 6'b010101; + 12'd886 : mem_out_dec = 6'b010101; + 12'd887 : mem_out_dec = 6'b010110; + 12'd888 : mem_out_dec = 6'b010110; + 12'd889 : mem_out_dec = 6'b010111; + 12'd890 : mem_out_dec = 6'b011000; + 12'd891 : mem_out_dec = 6'b011000; + 12'd892 : mem_out_dec = 6'b011001; + 12'd893 : mem_out_dec = 6'b011010; + 12'd894 : mem_out_dec = 6'b011011; + 12'd895 : mem_out_dec = 6'b011011; + 12'd896 : mem_out_dec = 6'b111111; + 12'd897 : mem_out_dec = 6'b111111; + 12'd898 : mem_out_dec = 6'b111111; + 12'd899 : mem_out_dec = 6'b111111; + 12'd900 : mem_out_dec = 6'b111111; + 12'd901 : mem_out_dec = 6'b111111; + 12'd902 : mem_out_dec = 6'b111111; + 12'd903 : mem_out_dec = 6'b111111; + 12'd904 : mem_out_dec = 6'b111111; + 12'd905 : mem_out_dec = 6'b111111; + 12'd906 : mem_out_dec = 6'b111111; + 12'd907 : mem_out_dec = 6'b111111; + 12'd908 : mem_out_dec = 6'b111111; + 12'd909 : mem_out_dec = 6'b111111; + 12'd910 : mem_out_dec = 6'b111111; + 12'd911 : mem_out_dec = 6'b111111; + 12'd912 : mem_out_dec = 6'b111111; + 12'd913 : mem_out_dec = 6'b111111; + 12'd914 : mem_out_dec = 6'b111111; + 12'd915 : mem_out_dec = 6'b111111; + 12'd916 : mem_out_dec = 6'b000100; + 12'd917 : mem_out_dec = 6'b000101; + 12'd918 : mem_out_dec = 6'b000101; + 12'd919 : mem_out_dec = 6'b000110; + 12'd920 : mem_out_dec = 6'b000110; + 12'd921 : mem_out_dec = 6'b000111; + 12'd922 : mem_out_dec = 6'b001000; + 12'd923 : mem_out_dec = 6'b001000; + 12'd924 : mem_out_dec = 6'b001001; + 12'd925 : mem_out_dec = 6'b001010; + 12'd926 : mem_out_dec = 6'b001011; + 12'd927 : mem_out_dec = 6'b001011; + 12'd928 : mem_out_dec = 6'b001011; + 12'd929 : mem_out_dec = 6'b001100; + 12'd930 : mem_out_dec = 6'b001100; + 12'd931 : mem_out_dec = 6'b001101; + 12'd932 : mem_out_dec = 6'b001101; + 12'd933 : mem_out_dec = 6'b001110; + 12'd934 : mem_out_dec = 6'b001110; + 12'd935 : mem_out_dec = 6'b001111; + 12'd936 : mem_out_dec = 6'b001110; + 12'd937 : mem_out_dec = 6'b001110; + 12'd938 : mem_out_dec = 6'b001111; + 12'd939 : mem_out_dec = 6'b001111; + 12'd940 : mem_out_dec = 6'b010000; + 12'd941 : mem_out_dec = 6'b010000; + 12'd942 : mem_out_dec = 6'b010001; + 12'd943 : mem_out_dec = 6'b010001; + 12'd944 : mem_out_dec = 6'b010010; + 12'd945 : mem_out_dec = 6'b010010; + 12'd946 : mem_out_dec = 6'b010011; + 12'd947 : mem_out_dec = 6'b010011; + 12'd948 : mem_out_dec = 6'b010100; + 12'd949 : mem_out_dec = 6'b010100; + 12'd950 : mem_out_dec = 6'b010101; + 12'd951 : mem_out_dec = 6'b010110; + 12'd952 : mem_out_dec = 6'b010110; + 12'd953 : mem_out_dec = 6'b010111; + 12'd954 : mem_out_dec = 6'b010111; + 12'd955 : mem_out_dec = 6'b011000; + 12'd956 : mem_out_dec = 6'b011001; + 12'd957 : mem_out_dec = 6'b011010; + 12'd958 : mem_out_dec = 6'b011010; + 12'd959 : mem_out_dec = 6'b011011; + 12'd960 : mem_out_dec = 6'b111111; + 12'd961 : mem_out_dec = 6'b111111; + 12'd962 : mem_out_dec = 6'b111111; + 12'd963 : mem_out_dec = 6'b111111; + 12'd964 : mem_out_dec = 6'b111111; + 12'd965 : mem_out_dec = 6'b111111; + 12'd966 : mem_out_dec = 6'b111111; + 12'd967 : mem_out_dec = 6'b111111; + 12'd968 : mem_out_dec = 6'b111111; + 12'd969 : mem_out_dec = 6'b111111; + 12'd970 : mem_out_dec = 6'b111111; + 12'd971 : mem_out_dec = 6'b111111; + 12'd972 : mem_out_dec = 6'b111111; + 12'd973 : mem_out_dec = 6'b111111; + 12'd974 : mem_out_dec = 6'b111111; + 12'd975 : mem_out_dec = 6'b111111; + 12'd976 : mem_out_dec = 6'b111111; + 12'd977 : mem_out_dec = 6'b111111; + 12'd978 : mem_out_dec = 6'b111111; + 12'd979 : mem_out_dec = 6'b111111; + 12'd980 : mem_out_dec = 6'b111111; + 12'd981 : mem_out_dec = 6'b000100; + 12'd982 : mem_out_dec = 6'b000101; + 12'd983 : mem_out_dec = 6'b000110; + 12'd984 : mem_out_dec = 6'b000110; + 12'd985 : mem_out_dec = 6'b000111; + 12'd986 : mem_out_dec = 6'b000111; + 12'd987 : mem_out_dec = 6'b001000; + 12'd988 : mem_out_dec = 6'b001001; + 12'd989 : mem_out_dec = 6'b001010; + 12'd990 : mem_out_dec = 6'b001010; + 12'd991 : mem_out_dec = 6'b001011; + 12'd992 : mem_out_dec = 6'b001011; + 12'd993 : mem_out_dec = 6'b001011; + 12'd994 : mem_out_dec = 6'b001100; + 12'd995 : mem_out_dec = 6'b001100; + 12'd996 : mem_out_dec = 6'b001101; + 12'd997 : mem_out_dec = 6'b001110; + 12'd998 : mem_out_dec = 6'b001110; + 12'd999 : mem_out_dec = 6'b001110; + 12'd1000 : mem_out_dec = 6'b001101; + 12'd1001 : mem_out_dec = 6'b001110; + 12'd1002 : mem_out_dec = 6'b001110; + 12'd1003 : mem_out_dec = 6'b001111; + 12'd1004 : mem_out_dec = 6'b001111; + 12'd1005 : mem_out_dec = 6'b010000; + 12'd1006 : mem_out_dec = 6'b010000; + 12'd1007 : mem_out_dec = 6'b010001; + 12'd1008 : mem_out_dec = 6'b010001; + 12'd1009 : mem_out_dec = 6'b010010; + 12'd1010 : mem_out_dec = 6'b010011; + 12'd1011 : mem_out_dec = 6'b010011; + 12'd1012 : mem_out_dec = 6'b010100; + 12'd1013 : mem_out_dec = 6'b010100; + 12'd1014 : mem_out_dec = 6'b010101; + 12'd1015 : mem_out_dec = 6'b010110; + 12'd1016 : mem_out_dec = 6'b010110; + 12'd1017 : mem_out_dec = 6'b010110; + 12'd1018 : mem_out_dec = 6'b010111; + 12'd1019 : mem_out_dec = 6'b011000; + 12'd1020 : mem_out_dec = 6'b011001; + 12'd1021 : mem_out_dec = 6'b011001; + 12'd1022 : mem_out_dec = 6'b011010; + 12'd1023 : mem_out_dec = 6'b011011; + 12'd1024 : mem_out_dec = 6'b111111; + 12'd1025 : mem_out_dec = 6'b111111; + 12'd1026 : mem_out_dec = 6'b111111; + 12'd1027 : mem_out_dec = 6'b111111; + 12'd1028 : mem_out_dec = 6'b111111; + 12'd1029 : mem_out_dec = 6'b111111; + 12'd1030 : mem_out_dec = 6'b111111; + 12'd1031 : mem_out_dec = 6'b111111; + 12'd1032 : mem_out_dec = 6'b111111; + 12'd1033 : mem_out_dec = 6'b111111; + 12'd1034 : mem_out_dec = 6'b111111; + 12'd1035 : mem_out_dec = 6'b111111; + 12'd1036 : mem_out_dec = 6'b111111; + 12'd1037 : mem_out_dec = 6'b111111; + 12'd1038 : mem_out_dec = 6'b111111; + 12'd1039 : mem_out_dec = 6'b111111; + 12'd1040 : mem_out_dec = 6'b111111; + 12'd1041 : mem_out_dec = 6'b111111; + 12'd1042 : mem_out_dec = 6'b111111; + 12'd1043 : mem_out_dec = 6'b111111; + 12'd1044 : mem_out_dec = 6'b111111; + 12'd1045 : mem_out_dec = 6'b111111; + 12'd1046 : mem_out_dec = 6'b000100; + 12'd1047 : mem_out_dec = 6'b000101; + 12'd1048 : mem_out_dec = 6'b000101; + 12'd1049 : mem_out_dec = 6'b000110; + 12'd1050 : mem_out_dec = 6'b000110; + 12'd1051 : mem_out_dec = 6'b000111; + 12'd1052 : mem_out_dec = 6'b001000; + 12'd1053 : mem_out_dec = 6'b001001; + 12'd1054 : mem_out_dec = 6'b001001; + 12'd1055 : mem_out_dec = 6'b001010; + 12'd1056 : mem_out_dec = 6'b001010; + 12'd1057 : mem_out_dec = 6'b001011; + 12'd1058 : mem_out_dec = 6'b001011; + 12'd1059 : mem_out_dec = 6'b001100; + 12'd1060 : mem_out_dec = 6'b001100; + 12'd1061 : mem_out_dec = 6'b001100; + 12'd1062 : mem_out_dec = 6'b001100; + 12'd1063 : mem_out_dec = 6'b001100; + 12'd1064 : mem_out_dec = 6'b001100; + 12'd1065 : mem_out_dec = 6'b001100; + 12'd1066 : mem_out_dec = 6'b001101; + 12'd1067 : mem_out_dec = 6'b001101; + 12'd1068 : mem_out_dec = 6'b001110; + 12'd1069 : mem_out_dec = 6'b001111; + 12'd1070 : mem_out_dec = 6'b010000; + 12'd1071 : mem_out_dec = 6'b010000; + 12'd1072 : mem_out_dec = 6'b010001; + 12'd1073 : mem_out_dec = 6'b010001; + 12'd1074 : mem_out_dec = 6'b010010; + 12'd1075 : mem_out_dec = 6'b010010; + 12'd1076 : mem_out_dec = 6'b010011; + 12'd1077 : mem_out_dec = 6'b010011; + 12'd1078 : mem_out_dec = 6'b010100; + 12'd1079 : mem_out_dec = 6'b010101; + 12'd1080 : mem_out_dec = 6'b010101; + 12'd1081 : mem_out_dec = 6'b010110; + 12'd1082 : mem_out_dec = 6'b010110; + 12'd1083 : mem_out_dec = 6'b010111; + 12'd1084 : mem_out_dec = 6'b011000; + 12'd1085 : mem_out_dec = 6'b011000; + 12'd1086 : mem_out_dec = 6'b011001; + 12'd1087 : mem_out_dec = 6'b011010; + 12'd1088 : mem_out_dec = 6'b111111; + 12'd1089 : mem_out_dec = 6'b111111; + 12'd1090 : mem_out_dec = 6'b111111; + 12'd1091 : mem_out_dec = 6'b111111; + 12'd1092 : mem_out_dec = 6'b111111; + 12'd1093 : mem_out_dec = 6'b111111; + 12'd1094 : mem_out_dec = 6'b111111; + 12'd1095 : mem_out_dec = 6'b111111; + 12'd1096 : mem_out_dec = 6'b111111; + 12'd1097 : mem_out_dec = 6'b111111; + 12'd1098 : mem_out_dec = 6'b111111; + 12'd1099 : mem_out_dec = 6'b111111; + 12'd1100 : mem_out_dec = 6'b111111; + 12'd1101 : mem_out_dec = 6'b111111; + 12'd1102 : mem_out_dec = 6'b111111; + 12'd1103 : mem_out_dec = 6'b111111; + 12'd1104 : mem_out_dec = 6'b111111; + 12'd1105 : mem_out_dec = 6'b111111; + 12'd1106 : mem_out_dec = 6'b111111; + 12'd1107 : mem_out_dec = 6'b111111; + 12'd1108 : mem_out_dec = 6'b111111; + 12'd1109 : mem_out_dec = 6'b111111; + 12'd1110 : mem_out_dec = 6'b111111; + 12'd1111 : mem_out_dec = 6'b000100; + 12'd1112 : mem_out_dec = 6'b000100; + 12'd1113 : mem_out_dec = 6'b000101; + 12'd1114 : mem_out_dec = 6'b000110; + 12'd1115 : mem_out_dec = 6'b000111; + 12'd1116 : mem_out_dec = 6'b000111; + 12'd1117 : mem_out_dec = 6'b001000; + 12'd1118 : mem_out_dec = 6'b001001; + 12'd1119 : mem_out_dec = 6'b001001; + 12'd1120 : mem_out_dec = 6'b001010; + 12'd1121 : mem_out_dec = 6'b001010; + 12'd1122 : mem_out_dec = 6'b001011; + 12'd1123 : mem_out_dec = 6'b001011; + 12'd1124 : mem_out_dec = 6'b001011; + 12'd1125 : mem_out_dec = 6'b001011; + 12'd1126 : mem_out_dec = 6'b001011; + 12'd1127 : mem_out_dec = 6'b001011; + 12'd1128 : mem_out_dec = 6'b001011; + 12'd1129 : mem_out_dec = 6'b001011; + 12'd1130 : mem_out_dec = 6'b001100; + 12'd1131 : mem_out_dec = 6'b001101; + 12'd1132 : mem_out_dec = 6'b001110; + 12'd1133 : mem_out_dec = 6'b001110; + 12'd1134 : mem_out_dec = 6'b001111; + 12'd1135 : mem_out_dec = 6'b010000; + 12'd1136 : mem_out_dec = 6'b010000; + 12'd1137 : mem_out_dec = 6'b010001; + 12'd1138 : mem_out_dec = 6'b010001; + 12'd1139 : mem_out_dec = 6'b010010; + 12'd1140 : mem_out_dec = 6'b010010; + 12'd1141 : mem_out_dec = 6'b010011; + 12'd1142 : mem_out_dec = 6'b010100; + 12'd1143 : mem_out_dec = 6'b010100; + 12'd1144 : mem_out_dec = 6'b010100; + 12'd1145 : mem_out_dec = 6'b010101; + 12'd1146 : mem_out_dec = 6'b010110; + 12'd1147 : mem_out_dec = 6'b010110; + 12'd1148 : mem_out_dec = 6'b010111; + 12'd1149 : mem_out_dec = 6'b011000; + 12'd1150 : mem_out_dec = 6'b011000; + 12'd1151 : mem_out_dec = 6'b011001; + 12'd1152 : mem_out_dec = 6'b111111; + 12'd1153 : mem_out_dec = 6'b111111; + 12'd1154 : mem_out_dec = 6'b111111; + 12'd1155 : mem_out_dec = 6'b111111; + 12'd1156 : mem_out_dec = 6'b111111; + 12'd1157 : mem_out_dec = 6'b111111; + 12'd1158 : mem_out_dec = 6'b111111; + 12'd1159 : mem_out_dec = 6'b111111; + 12'd1160 : mem_out_dec = 6'b111111; + 12'd1161 : mem_out_dec = 6'b111111; + 12'd1162 : mem_out_dec = 6'b111111; + 12'd1163 : mem_out_dec = 6'b111111; + 12'd1164 : mem_out_dec = 6'b111111; + 12'd1165 : mem_out_dec = 6'b111111; + 12'd1166 : mem_out_dec = 6'b111111; + 12'd1167 : mem_out_dec = 6'b111111; + 12'd1168 : mem_out_dec = 6'b111111; + 12'd1169 : mem_out_dec = 6'b111111; + 12'd1170 : mem_out_dec = 6'b111111; + 12'd1171 : mem_out_dec = 6'b111111; + 12'd1172 : mem_out_dec = 6'b111111; + 12'd1173 : mem_out_dec = 6'b111111; + 12'd1174 : mem_out_dec = 6'b111111; + 12'd1175 : mem_out_dec = 6'b111111; + 12'd1176 : mem_out_dec = 6'b000100; + 12'd1177 : mem_out_dec = 6'b000101; + 12'd1178 : mem_out_dec = 6'b000101; + 12'd1179 : mem_out_dec = 6'b000110; + 12'd1180 : mem_out_dec = 6'b000111; + 12'd1181 : mem_out_dec = 6'b000111; + 12'd1182 : mem_out_dec = 6'b001000; + 12'd1183 : mem_out_dec = 6'b001001; + 12'd1184 : mem_out_dec = 6'b001001; + 12'd1185 : mem_out_dec = 6'b001010; + 12'd1186 : mem_out_dec = 6'b001010; + 12'd1187 : mem_out_dec = 6'b001010; + 12'd1188 : mem_out_dec = 6'b001010; + 12'd1189 : mem_out_dec = 6'b001010; + 12'd1190 : mem_out_dec = 6'b001010; + 12'd1191 : mem_out_dec = 6'b001010; + 12'd1192 : mem_out_dec = 6'b001010; + 12'd1193 : mem_out_dec = 6'b001011; + 12'd1194 : mem_out_dec = 6'b001100; + 12'd1195 : mem_out_dec = 6'b001100; + 12'd1196 : mem_out_dec = 6'b001101; + 12'd1197 : mem_out_dec = 6'b001110; + 12'd1198 : mem_out_dec = 6'b001111; + 12'd1199 : mem_out_dec = 6'b010000; + 12'd1200 : mem_out_dec = 6'b010000; + 12'd1201 : mem_out_dec = 6'b010000; + 12'd1202 : mem_out_dec = 6'b010001; + 12'd1203 : mem_out_dec = 6'b010001; + 12'd1204 : mem_out_dec = 6'b010010; + 12'd1205 : mem_out_dec = 6'b010011; + 12'd1206 : mem_out_dec = 6'b010011; + 12'd1207 : mem_out_dec = 6'b010100; + 12'd1208 : mem_out_dec = 6'b010100; + 12'd1209 : mem_out_dec = 6'b010100; + 12'd1210 : mem_out_dec = 6'b010101; + 12'd1211 : mem_out_dec = 6'b010110; + 12'd1212 : mem_out_dec = 6'b010110; + 12'd1213 : mem_out_dec = 6'b010111; + 12'd1214 : mem_out_dec = 6'b011000; + 12'd1215 : mem_out_dec = 6'b011001; + 12'd1216 : mem_out_dec = 6'b111111; + 12'd1217 : mem_out_dec = 6'b111111; + 12'd1218 : mem_out_dec = 6'b111111; + 12'd1219 : mem_out_dec = 6'b111111; + 12'd1220 : mem_out_dec = 6'b111111; + 12'd1221 : mem_out_dec = 6'b111111; + 12'd1222 : mem_out_dec = 6'b111111; + 12'd1223 : mem_out_dec = 6'b111111; + 12'd1224 : mem_out_dec = 6'b111111; + 12'd1225 : mem_out_dec = 6'b111111; + 12'd1226 : mem_out_dec = 6'b111111; + 12'd1227 : mem_out_dec = 6'b111111; + 12'd1228 : mem_out_dec = 6'b111111; + 12'd1229 : mem_out_dec = 6'b111111; + 12'd1230 : mem_out_dec = 6'b111111; + 12'd1231 : mem_out_dec = 6'b111111; + 12'd1232 : mem_out_dec = 6'b111111; + 12'd1233 : mem_out_dec = 6'b111111; + 12'd1234 : mem_out_dec = 6'b111111; + 12'd1235 : mem_out_dec = 6'b111111; + 12'd1236 : mem_out_dec = 6'b111111; + 12'd1237 : mem_out_dec = 6'b111111; + 12'd1238 : mem_out_dec = 6'b111111; + 12'd1239 : mem_out_dec = 6'b111111; + 12'd1240 : mem_out_dec = 6'b111111; + 12'd1241 : mem_out_dec = 6'b000100; + 12'd1242 : mem_out_dec = 6'b000100; + 12'd1243 : mem_out_dec = 6'b000101; + 12'd1244 : mem_out_dec = 6'b000110; + 12'd1245 : mem_out_dec = 6'b000111; + 12'd1246 : mem_out_dec = 6'b001000; + 12'd1247 : mem_out_dec = 6'b001000; + 12'd1248 : mem_out_dec = 6'b001001; + 12'd1249 : mem_out_dec = 6'b001001; + 12'd1250 : mem_out_dec = 6'b001001; + 12'd1251 : mem_out_dec = 6'b001001; + 12'd1252 : mem_out_dec = 6'b001001; + 12'd1253 : mem_out_dec = 6'b001001; + 12'd1254 : mem_out_dec = 6'b001001; + 12'd1255 : mem_out_dec = 6'b001001; + 12'd1256 : mem_out_dec = 6'b001010; + 12'd1257 : mem_out_dec = 6'b001010; + 12'd1258 : mem_out_dec = 6'b001011; + 12'd1259 : mem_out_dec = 6'b001100; + 12'd1260 : mem_out_dec = 6'b001101; + 12'd1261 : mem_out_dec = 6'b001110; + 12'd1262 : mem_out_dec = 6'b001110; + 12'd1263 : mem_out_dec = 6'b001111; + 12'd1264 : mem_out_dec = 6'b001111; + 12'd1265 : mem_out_dec = 6'b010000; + 12'd1266 : mem_out_dec = 6'b010000; + 12'd1267 : mem_out_dec = 6'b010001; + 12'd1268 : mem_out_dec = 6'b010001; + 12'd1269 : mem_out_dec = 6'b010010; + 12'd1270 : mem_out_dec = 6'b010011; + 12'd1271 : mem_out_dec = 6'b010011; + 12'd1272 : mem_out_dec = 6'b010011; + 12'd1273 : mem_out_dec = 6'b010100; + 12'd1274 : mem_out_dec = 6'b010100; + 12'd1275 : mem_out_dec = 6'b010101; + 12'd1276 : mem_out_dec = 6'b010110; + 12'd1277 : mem_out_dec = 6'b010111; + 12'd1278 : mem_out_dec = 6'b011000; + 12'd1279 : mem_out_dec = 6'b011000; + 12'd1280 : mem_out_dec = 6'b111111; + 12'd1281 : mem_out_dec = 6'b111111; + 12'd1282 : mem_out_dec = 6'b111111; + 12'd1283 : mem_out_dec = 6'b111111; + 12'd1284 : mem_out_dec = 6'b111111; + 12'd1285 : mem_out_dec = 6'b111111; + 12'd1286 : mem_out_dec = 6'b111111; + 12'd1287 : mem_out_dec = 6'b111111; + 12'd1288 : mem_out_dec = 6'b111111; + 12'd1289 : mem_out_dec = 6'b111111; + 12'd1290 : mem_out_dec = 6'b111111; + 12'd1291 : mem_out_dec = 6'b111111; + 12'd1292 : mem_out_dec = 6'b111111; + 12'd1293 : mem_out_dec = 6'b111111; + 12'd1294 : mem_out_dec = 6'b111111; + 12'd1295 : mem_out_dec = 6'b111111; + 12'd1296 : mem_out_dec = 6'b111111; + 12'd1297 : mem_out_dec = 6'b111111; + 12'd1298 : mem_out_dec = 6'b111111; + 12'd1299 : mem_out_dec = 6'b111111; + 12'd1300 : mem_out_dec = 6'b111111; + 12'd1301 : mem_out_dec = 6'b111111; + 12'd1302 : mem_out_dec = 6'b111111; + 12'd1303 : mem_out_dec = 6'b111111; + 12'd1304 : mem_out_dec = 6'b111111; + 12'd1305 : mem_out_dec = 6'b111111; + 12'd1306 : mem_out_dec = 6'b000100; + 12'd1307 : mem_out_dec = 6'b000101; + 12'd1308 : mem_out_dec = 6'b000110; + 12'd1309 : mem_out_dec = 6'b000110; + 12'd1310 : mem_out_dec = 6'b000111; + 12'd1311 : mem_out_dec = 6'b001000; + 12'd1312 : mem_out_dec = 6'b001000; + 12'd1313 : mem_out_dec = 6'b001000; + 12'd1314 : mem_out_dec = 6'b001000; + 12'd1315 : mem_out_dec = 6'b001000; + 12'd1316 : mem_out_dec = 6'b001000; + 12'd1317 : mem_out_dec = 6'b001000; + 12'd1318 : mem_out_dec = 6'b001000; + 12'd1319 : mem_out_dec = 6'b001001; + 12'd1320 : mem_out_dec = 6'b001001; + 12'd1321 : mem_out_dec = 6'b001010; + 12'd1322 : mem_out_dec = 6'b001011; + 12'd1323 : mem_out_dec = 6'b001100; + 12'd1324 : mem_out_dec = 6'b001100; + 12'd1325 : mem_out_dec = 6'b001101; + 12'd1326 : mem_out_dec = 6'b001110; + 12'd1327 : mem_out_dec = 6'b001111; + 12'd1328 : mem_out_dec = 6'b001111; + 12'd1329 : mem_out_dec = 6'b001111; + 12'd1330 : mem_out_dec = 6'b010000; + 12'd1331 : mem_out_dec = 6'b010000; + 12'd1332 : mem_out_dec = 6'b010001; + 12'd1333 : mem_out_dec = 6'b010001; + 12'd1334 : mem_out_dec = 6'b010010; + 12'd1335 : mem_out_dec = 6'b010011; + 12'd1336 : mem_out_dec = 6'b010010; + 12'd1337 : mem_out_dec = 6'b010011; + 12'd1338 : mem_out_dec = 6'b010100; + 12'd1339 : mem_out_dec = 6'b010101; + 12'd1340 : mem_out_dec = 6'b010110; + 12'd1341 : mem_out_dec = 6'b010110; + 12'd1342 : mem_out_dec = 6'b010111; + 12'd1343 : mem_out_dec = 6'b011000; + 12'd1344 : mem_out_dec = 6'b111111; + 12'd1345 : mem_out_dec = 6'b111111; + 12'd1346 : mem_out_dec = 6'b111111; + 12'd1347 : mem_out_dec = 6'b111111; + 12'd1348 : mem_out_dec = 6'b111111; + 12'd1349 : mem_out_dec = 6'b111111; + 12'd1350 : mem_out_dec = 6'b111111; + 12'd1351 : mem_out_dec = 6'b111111; + 12'd1352 : mem_out_dec = 6'b111111; + 12'd1353 : mem_out_dec = 6'b111111; + 12'd1354 : mem_out_dec = 6'b111111; + 12'd1355 : mem_out_dec = 6'b111111; + 12'd1356 : mem_out_dec = 6'b111111; + 12'd1357 : mem_out_dec = 6'b111111; + 12'd1358 : mem_out_dec = 6'b111111; + 12'd1359 : mem_out_dec = 6'b111111; + 12'd1360 : mem_out_dec = 6'b111111; + 12'd1361 : mem_out_dec = 6'b111111; + 12'd1362 : mem_out_dec = 6'b111111; + 12'd1363 : mem_out_dec = 6'b111111; + 12'd1364 : mem_out_dec = 6'b111111; + 12'd1365 : mem_out_dec = 6'b111111; + 12'd1366 : mem_out_dec = 6'b111111; + 12'd1367 : mem_out_dec = 6'b111111; + 12'd1368 : mem_out_dec = 6'b111111; + 12'd1369 : mem_out_dec = 6'b111111; + 12'd1370 : mem_out_dec = 6'b111111; + 12'd1371 : mem_out_dec = 6'b000101; + 12'd1372 : mem_out_dec = 6'b000101; + 12'd1373 : mem_out_dec = 6'b000110; + 12'd1374 : mem_out_dec = 6'b000111; + 12'd1375 : mem_out_dec = 6'b001000; + 12'd1376 : mem_out_dec = 6'b000111; + 12'd1377 : mem_out_dec = 6'b000111; + 12'd1378 : mem_out_dec = 6'b000111; + 12'd1379 : mem_out_dec = 6'b000111; + 12'd1380 : mem_out_dec = 6'b000111; + 12'd1381 : mem_out_dec = 6'b000111; + 12'd1382 : mem_out_dec = 6'b001000; + 12'd1383 : mem_out_dec = 6'b001001; + 12'd1384 : mem_out_dec = 6'b001001; + 12'd1385 : mem_out_dec = 6'b001010; + 12'd1386 : mem_out_dec = 6'b001010; + 12'd1387 : mem_out_dec = 6'b001011; + 12'd1388 : mem_out_dec = 6'b001100; + 12'd1389 : mem_out_dec = 6'b001101; + 12'd1390 : mem_out_dec = 6'b001110; + 12'd1391 : mem_out_dec = 6'b001110; + 12'd1392 : mem_out_dec = 6'b001111; + 12'd1393 : mem_out_dec = 6'b001111; + 12'd1394 : mem_out_dec = 6'b010000; + 12'd1395 : mem_out_dec = 6'b010000; + 12'd1396 : mem_out_dec = 6'b010001; + 12'd1397 : mem_out_dec = 6'b010001; + 12'd1398 : mem_out_dec = 6'b010010; + 12'd1399 : mem_out_dec = 6'b010010; + 12'd1400 : mem_out_dec = 6'b010010; + 12'd1401 : mem_out_dec = 6'b010011; + 12'd1402 : mem_out_dec = 6'b010100; + 12'd1403 : mem_out_dec = 6'b010100; + 12'd1404 : mem_out_dec = 6'b010101; + 12'd1405 : mem_out_dec = 6'b010110; + 12'd1406 : mem_out_dec = 6'b010111; + 12'd1407 : mem_out_dec = 6'b010111; + 12'd1408 : mem_out_dec = 6'b111111; + 12'd1409 : mem_out_dec = 6'b111111; + 12'd1410 : mem_out_dec = 6'b111111; + 12'd1411 : mem_out_dec = 6'b111111; + 12'd1412 : mem_out_dec = 6'b111111; + 12'd1413 : mem_out_dec = 6'b111111; + 12'd1414 : mem_out_dec = 6'b111111; + 12'd1415 : mem_out_dec = 6'b111111; + 12'd1416 : mem_out_dec = 6'b111111; + 12'd1417 : mem_out_dec = 6'b111111; + 12'd1418 : mem_out_dec = 6'b111111; + 12'd1419 : mem_out_dec = 6'b111111; + 12'd1420 : mem_out_dec = 6'b111111; + 12'd1421 : mem_out_dec = 6'b111111; + 12'd1422 : mem_out_dec = 6'b111111; + 12'd1423 : mem_out_dec = 6'b111111; + 12'd1424 : mem_out_dec = 6'b111111; + 12'd1425 : mem_out_dec = 6'b111111; + 12'd1426 : mem_out_dec = 6'b111111; + 12'd1427 : mem_out_dec = 6'b111111; + 12'd1428 : mem_out_dec = 6'b111111; + 12'd1429 : mem_out_dec = 6'b111111; + 12'd1430 : mem_out_dec = 6'b111111; + 12'd1431 : mem_out_dec = 6'b111111; + 12'd1432 : mem_out_dec = 6'b111111; + 12'd1433 : mem_out_dec = 6'b111111; + 12'd1434 : mem_out_dec = 6'b111111; + 12'd1435 : mem_out_dec = 6'b111111; + 12'd1436 : mem_out_dec = 6'b000101; + 12'd1437 : mem_out_dec = 6'b000110; + 12'd1438 : mem_out_dec = 6'b000111; + 12'd1439 : mem_out_dec = 6'b000111; + 12'd1440 : mem_out_dec = 6'b000110; + 12'd1441 : mem_out_dec = 6'b000110; + 12'd1442 : mem_out_dec = 6'b000110; + 12'd1443 : mem_out_dec = 6'b000110; + 12'd1444 : mem_out_dec = 6'b000110; + 12'd1445 : mem_out_dec = 6'b000111; + 12'd1446 : mem_out_dec = 6'b000111; + 12'd1447 : mem_out_dec = 6'b001000; + 12'd1448 : mem_out_dec = 6'b001001; + 12'd1449 : mem_out_dec = 6'b001001; + 12'd1450 : mem_out_dec = 6'b001010; + 12'd1451 : mem_out_dec = 6'b001011; + 12'd1452 : mem_out_dec = 6'b001100; + 12'd1453 : mem_out_dec = 6'b001100; + 12'd1454 : mem_out_dec = 6'b001101; + 12'd1455 : mem_out_dec = 6'b001110; + 12'd1456 : mem_out_dec = 6'b001110; + 12'd1457 : mem_out_dec = 6'b001111; + 12'd1458 : mem_out_dec = 6'b001111; + 12'd1459 : mem_out_dec = 6'b010000; + 12'd1460 : mem_out_dec = 6'b010000; + 12'd1461 : mem_out_dec = 6'b010001; + 12'd1462 : mem_out_dec = 6'b010001; + 12'd1463 : mem_out_dec = 6'b010010; + 12'd1464 : mem_out_dec = 6'b010010; + 12'd1465 : mem_out_dec = 6'b010011; + 12'd1466 : mem_out_dec = 6'b010011; + 12'd1467 : mem_out_dec = 6'b010100; + 12'd1468 : mem_out_dec = 6'b010101; + 12'd1469 : mem_out_dec = 6'b010110; + 12'd1470 : mem_out_dec = 6'b010110; + 12'd1471 : mem_out_dec = 6'b010111; + 12'd1472 : mem_out_dec = 6'b111111; + 12'd1473 : mem_out_dec = 6'b111111; + 12'd1474 : mem_out_dec = 6'b111111; + 12'd1475 : mem_out_dec = 6'b111111; + 12'd1476 : mem_out_dec = 6'b111111; + 12'd1477 : mem_out_dec = 6'b111111; + 12'd1478 : mem_out_dec = 6'b111111; + 12'd1479 : mem_out_dec = 6'b111111; + 12'd1480 : mem_out_dec = 6'b111111; + 12'd1481 : mem_out_dec = 6'b111111; + 12'd1482 : mem_out_dec = 6'b111111; + 12'd1483 : mem_out_dec = 6'b111111; + 12'd1484 : mem_out_dec = 6'b111111; + 12'd1485 : mem_out_dec = 6'b111111; + 12'd1486 : mem_out_dec = 6'b111111; + 12'd1487 : mem_out_dec = 6'b111111; + 12'd1488 : mem_out_dec = 6'b111111; + 12'd1489 : mem_out_dec = 6'b111111; + 12'd1490 : mem_out_dec = 6'b111111; + 12'd1491 : mem_out_dec = 6'b111111; + 12'd1492 : mem_out_dec = 6'b111111; + 12'd1493 : mem_out_dec = 6'b111111; + 12'd1494 : mem_out_dec = 6'b111111; + 12'd1495 : mem_out_dec = 6'b111111; + 12'd1496 : mem_out_dec = 6'b111111; + 12'd1497 : mem_out_dec = 6'b111111; + 12'd1498 : mem_out_dec = 6'b111111; + 12'd1499 : mem_out_dec = 6'b111111; + 12'd1500 : mem_out_dec = 6'b111111; + 12'd1501 : mem_out_dec = 6'b000101; + 12'd1502 : mem_out_dec = 6'b000110; + 12'd1503 : mem_out_dec = 6'b000110; + 12'd1504 : mem_out_dec = 6'b000110; + 12'd1505 : mem_out_dec = 6'b000110; + 12'd1506 : mem_out_dec = 6'b000101; + 12'd1507 : mem_out_dec = 6'b000101; + 12'd1508 : mem_out_dec = 6'b000110; + 12'd1509 : mem_out_dec = 6'b000111; + 12'd1510 : mem_out_dec = 6'b000111; + 12'd1511 : mem_out_dec = 6'b001000; + 12'd1512 : mem_out_dec = 6'b001000; + 12'd1513 : mem_out_dec = 6'b001001; + 12'd1514 : mem_out_dec = 6'b001010; + 12'd1515 : mem_out_dec = 6'b001011; + 12'd1516 : mem_out_dec = 6'b001011; + 12'd1517 : mem_out_dec = 6'b001100; + 12'd1518 : mem_out_dec = 6'b001101; + 12'd1519 : mem_out_dec = 6'b001110; + 12'd1520 : mem_out_dec = 6'b001110; + 12'd1521 : mem_out_dec = 6'b001110; + 12'd1522 : mem_out_dec = 6'b001111; + 12'd1523 : mem_out_dec = 6'b001111; + 12'd1524 : mem_out_dec = 6'b010000; + 12'd1525 : mem_out_dec = 6'b010000; + 12'd1526 : mem_out_dec = 6'b010001; + 12'd1527 : mem_out_dec = 6'b010001; + 12'd1528 : mem_out_dec = 6'b010001; + 12'd1529 : mem_out_dec = 6'b010010; + 12'd1530 : mem_out_dec = 6'b010011; + 12'd1531 : mem_out_dec = 6'b010100; + 12'd1532 : mem_out_dec = 6'b010101; + 12'd1533 : mem_out_dec = 6'b010101; + 12'd1534 : mem_out_dec = 6'b010110; + 12'd1535 : mem_out_dec = 6'b010110; + 12'd1536 : mem_out_dec = 6'b111111; + 12'd1537 : mem_out_dec = 6'b111111; + 12'd1538 : mem_out_dec = 6'b111111; + 12'd1539 : mem_out_dec = 6'b111111; + 12'd1540 : mem_out_dec = 6'b111111; + 12'd1541 : mem_out_dec = 6'b111111; + 12'd1542 : mem_out_dec = 6'b111111; + 12'd1543 : mem_out_dec = 6'b111111; + 12'd1544 : mem_out_dec = 6'b111111; + 12'd1545 : mem_out_dec = 6'b111111; + 12'd1546 : mem_out_dec = 6'b111111; + 12'd1547 : mem_out_dec = 6'b111111; + 12'd1548 : mem_out_dec = 6'b111111; + 12'd1549 : mem_out_dec = 6'b111111; + 12'd1550 : mem_out_dec = 6'b111111; + 12'd1551 : mem_out_dec = 6'b111111; + 12'd1552 : mem_out_dec = 6'b111111; + 12'd1553 : mem_out_dec = 6'b111111; + 12'd1554 : mem_out_dec = 6'b111111; + 12'd1555 : mem_out_dec = 6'b111111; + 12'd1556 : mem_out_dec = 6'b111111; + 12'd1557 : mem_out_dec = 6'b111111; + 12'd1558 : mem_out_dec = 6'b111111; + 12'd1559 : mem_out_dec = 6'b111111; + 12'd1560 : mem_out_dec = 6'b111111; + 12'd1561 : mem_out_dec = 6'b111111; + 12'd1562 : mem_out_dec = 6'b111111; + 12'd1563 : mem_out_dec = 6'b111111; + 12'd1564 : mem_out_dec = 6'b111111; + 12'd1565 : mem_out_dec = 6'b111111; + 12'd1566 : mem_out_dec = 6'b000100; + 12'd1567 : mem_out_dec = 6'b000100; + 12'd1568 : mem_out_dec = 6'b000100; + 12'd1569 : mem_out_dec = 6'b000100; + 12'd1570 : mem_out_dec = 6'b000100; + 12'd1571 : mem_out_dec = 6'b000101; + 12'd1572 : mem_out_dec = 6'b000101; + 12'd1573 : mem_out_dec = 6'b000110; + 12'd1574 : mem_out_dec = 6'b000111; + 12'd1575 : mem_out_dec = 6'b000111; + 12'd1576 : mem_out_dec = 6'b000111; + 12'd1577 : mem_out_dec = 6'b001000; + 12'd1578 : mem_out_dec = 6'b001001; + 12'd1579 : mem_out_dec = 6'b001010; + 12'd1580 : mem_out_dec = 6'b001010; + 12'd1581 : mem_out_dec = 6'b001011; + 12'd1582 : mem_out_dec = 6'b001100; + 12'd1583 : mem_out_dec = 6'b001101; + 12'd1584 : mem_out_dec = 6'b001101; + 12'd1585 : mem_out_dec = 6'b001101; + 12'd1586 : mem_out_dec = 6'b001110; + 12'd1587 : mem_out_dec = 6'b001110; + 12'd1588 : mem_out_dec = 6'b001111; + 12'd1589 : mem_out_dec = 6'b001111; + 12'd1590 : mem_out_dec = 6'b010000; + 12'd1591 : mem_out_dec = 6'b010001; + 12'd1592 : mem_out_dec = 6'b010001; + 12'd1593 : mem_out_dec = 6'b010001; + 12'd1594 : mem_out_dec = 6'b010010; + 12'd1595 : mem_out_dec = 6'b010010; + 12'd1596 : mem_out_dec = 6'b010011; + 12'd1597 : mem_out_dec = 6'b010011; + 12'd1598 : mem_out_dec = 6'b010100; + 12'd1599 : mem_out_dec = 6'b010100; + 12'd1600 : mem_out_dec = 6'b111111; + 12'd1601 : mem_out_dec = 6'b111111; + 12'd1602 : mem_out_dec = 6'b111111; + 12'd1603 : mem_out_dec = 6'b111111; + 12'd1604 : mem_out_dec = 6'b111111; + 12'd1605 : mem_out_dec = 6'b111111; + 12'd1606 : mem_out_dec = 6'b111111; + 12'd1607 : mem_out_dec = 6'b111111; + 12'd1608 : mem_out_dec = 6'b111111; + 12'd1609 : mem_out_dec = 6'b111111; + 12'd1610 : mem_out_dec = 6'b111111; + 12'd1611 : mem_out_dec = 6'b111111; + 12'd1612 : mem_out_dec = 6'b111111; + 12'd1613 : mem_out_dec = 6'b111111; + 12'd1614 : mem_out_dec = 6'b111111; + 12'd1615 : mem_out_dec = 6'b111111; + 12'd1616 : mem_out_dec = 6'b111111; + 12'd1617 : mem_out_dec = 6'b111111; + 12'd1618 : mem_out_dec = 6'b111111; + 12'd1619 : mem_out_dec = 6'b111111; + 12'd1620 : mem_out_dec = 6'b111111; + 12'd1621 : mem_out_dec = 6'b111111; + 12'd1622 : mem_out_dec = 6'b111111; + 12'd1623 : mem_out_dec = 6'b111111; + 12'd1624 : mem_out_dec = 6'b111111; + 12'd1625 : mem_out_dec = 6'b111111; + 12'd1626 : mem_out_dec = 6'b111111; + 12'd1627 : mem_out_dec = 6'b111111; + 12'd1628 : mem_out_dec = 6'b111111; + 12'd1629 : mem_out_dec = 6'b111111; + 12'd1630 : mem_out_dec = 6'b111111; + 12'd1631 : mem_out_dec = 6'b000100; + 12'd1632 : mem_out_dec = 6'b000011; + 12'd1633 : mem_out_dec = 6'b000011; + 12'd1634 : mem_out_dec = 6'b000100; + 12'd1635 : mem_out_dec = 6'b000100; + 12'd1636 : mem_out_dec = 6'b000101; + 12'd1637 : mem_out_dec = 6'b000110; + 12'd1638 : mem_out_dec = 6'b000110; + 12'd1639 : mem_out_dec = 6'b000111; + 12'd1640 : mem_out_dec = 6'b000111; + 12'd1641 : mem_out_dec = 6'b001000; + 12'd1642 : mem_out_dec = 6'b001001; + 12'd1643 : mem_out_dec = 6'b001001; + 12'd1644 : mem_out_dec = 6'b001010; + 12'd1645 : mem_out_dec = 6'b001011; + 12'd1646 : mem_out_dec = 6'b001100; + 12'd1647 : mem_out_dec = 6'b001101; + 12'd1648 : mem_out_dec = 6'b001101; + 12'd1649 : mem_out_dec = 6'b001101; + 12'd1650 : mem_out_dec = 6'b001110; + 12'd1651 : mem_out_dec = 6'b001110; + 12'd1652 : mem_out_dec = 6'b001110; + 12'd1653 : mem_out_dec = 6'b001111; + 12'd1654 : mem_out_dec = 6'b010000; + 12'd1655 : mem_out_dec = 6'b010000; + 12'd1656 : mem_out_dec = 6'b010001; + 12'd1657 : mem_out_dec = 6'b010001; + 12'd1658 : mem_out_dec = 6'b010001; + 12'd1659 : mem_out_dec = 6'b010010; + 12'd1660 : mem_out_dec = 6'b010010; + 12'd1661 : mem_out_dec = 6'b010011; + 12'd1662 : mem_out_dec = 6'b010011; + 12'd1663 : mem_out_dec = 6'b010100; + 12'd1664 : mem_out_dec = 6'b111111; + 12'd1665 : mem_out_dec = 6'b111111; + 12'd1666 : mem_out_dec = 6'b111111; + 12'd1667 : mem_out_dec = 6'b111111; + 12'd1668 : mem_out_dec = 6'b111111; + 12'd1669 : mem_out_dec = 6'b111111; + 12'd1670 : mem_out_dec = 6'b111111; + 12'd1671 : mem_out_dec = 6'b111111; + 12'd1672 : mem_out_dec = 6'b111111; + 12'd1673 : mem_out_dec = 6'b111111; + 12'd1674 : mem_out_dec = 6'b111111; + 12'd1675 : mem_out_dec = 6'b111111; + 12'd1676 : mem_out_dec = 6'b111111; + 12'd1677 : mem_out_dec = 6'b111111; + 12'd1678 : mem_out_dec = 6'b111111; + 12'd1679 : mem_out_dec = 6'b111111; + 12'd1680 : mem_out_dec = 6'b111111; + 12'd1681 : mem_out_dec = 6'b111111; + 12'd1682 : mem_out_dec = 6'b111111; + 12'd1683 : mem_out_dec = 6'b111111; + 12'd1684 : mem_out_dec = 6'b111111; + 12'd1685 : mem_out_dec = 6'b111111; + 12'd1686 : mem_out_dec = 6'b111111; + 12'd1687 : mem_out_dec = 6'b111111; + 12'd1688 : mem_out_dec = 6'b111111; + 12'd1689 : mem_out_dec = 6'b111111; + 12'd1690 : mem_out_dec = 6'b111111; + 12'd1691 : mem_out_dec = 6'b111111; + 12'd1692 : mem_out_dec = 6'b111111; + 12'd1693 : mem_out_dec = 6'b111111; + 12'd1694 : mem_out_dec = 6'b111111; + 12'd1695 : mem_out_dec = 6'b111111; + 12'd1696 : mem_out_dec = 6'b000011; + 12'd1697 : mem_out_dec = 6'b000011; + 12'd1698 : mem_out_dec = 6'b000100; + 12'd1699 : mem_out_dec = 6'b000100; + 12'd1700 : mem_out_dec = 6'b000101; + 12'd1701 : mem_out_dec = 6'b000101; + 12'd1702 : mem_out_dec = 6'b000110; + 12'd1703 : mem_out_dec = 6'b000111; + 12'd1704 : mem_out_dec = 6'b000111; + 12'd1705 : mem_out_dec = 6'b001000; + 12'd1706 : mem_out_dec = 6'b001000; + 12'd1707 : mem_out_dec = 6'b001001; + 12'd1708 : mem_out_dec = 6'b001010; + 12'd1709 : mem_out_dec = 6'b001011; + 12'd1710 : mem_out_dec = 6'b001100; + 12'd1711 : mem_out_dec = 6'b001100; + 12'd1712 : mem_out_dec = 6'b001100; + 12'd1713 : mem_out_dec = 6'b001101; + 12'd1714 : mem_out_dec = 6'b001101; + 12'd1715 : mem_out_dec = 6'b001110; + 12'd1716 : mem_out_dec = 6'b001110; + 12'd1717 : mem_out_dec = 6'b001111; + 12'd1718 : mem_out_dec = 6'b001111; + 12'd1719 : mem_out_dec = 6'b010000; + 12'd1720 : mem_out_dec = 6'b010000; + 12'd1721 : mem_out_dec = 6'b010000; + 12'd1722 : mem_out_dec = 6'b010001; + 12'd1723 : mem_out_dec = 6'b010001; + 12'd1724 : mem_out_dec = 6'b010010; + 12'd1725 : mem_out_dec = 6'b010010; + 12'd1726 : mem_out_dec = 6'b010011; + 12'd1727 : mem_out_dec = 6'b010011; + 12'd1728 : mem_out_dec = 6'b111111; + 12'd1729 : mem_out_dec = 6'b111111; + 12'd1730 : mem_out_dec = 6'b111111; + 12'd1731 : mem_out_dec = 6'b111111; + 12'd1732 : mem_out_dec = 6'b111111; + 12'd1733 : mem_out_dec = 6'b111111; + 12'd1734 : mem_out_dec = 6'b111111; + 12'd1735 : mem_out_dec = 6'b111111; + 12'd1736 : mem_out_dec = 6'b111111; + 12'd1737 : mem_out_dec = 6'b111111; + 12'd1738 : mem_out_dec = 6'b111111; + 12'd1739 : mem_out_dec = 6'b111111; + 12'd1740 : mem_out_dec = 6'b111111; + 12'd1741 : mem_out_dec = 6'b111111; + 12'd1742 : mem_out_dec = 6'b111111; + 12'd1743 : mem_out_dec = 6'b111111; + 12'd1744 : mem_out_dec = 6'b111111; + 12'd1745 : mem_out_dec = 6'b111111; + 12'd1746 : mem_out_dec = 6'b111111; + 12'd1747 : mem_out_dec = 6'b111111; + 12'd1748 : mem_out_dec = 6'b111111; + 12'd1749 : mem_out_dec = 6'b111111; + 12'd1750 : mem_out_dec = 6'b111111; + 12'd1751 : mem_out_dec = 6'b111111; + 12'd1752 : mem_out_dec = 6'b111111; + 12'd1753 : mem_out_dec = 6'b111111; + 12'd1754 : mem_out_dec = 6'b111111; + 12'd1755 : mem_out_dec = 6'b111111; + 12'd1756 : mem_out_dec = 6'b111111; + 12'd1757 : mem_out_dec = 6'b111111; + 12'd1758 : mem_out_dec = 6'b111111; + 12'd1759 : mem_out_dec = 6'b111111; + 12'd1760 : mem_out_dec = 6'b111111; + 12'd1761 : mem_out_dec = 6'b000011; + 12'd1762 : mem_out_dec = 6'b000011; + 12'd1763 : mem_out_dec = 6'b000100; + 12'd1764 : mem_out_dec = 6'b000101; + 12'd1765 : mem_out_dec = 6'b000101; + 12'd1766 : mem_out_dec = 6'b000110; + 12'd1767 : mem_out_dec = 6'b000111; + 12'd1768 : mem_out_dec = 6'b000111; + 12'd1769 : mem_out_dec = 6'b000111; + 12'd1770 : mem_out_dec = 6'b001000; + 12'd1771 : mem_out_dec = 6'b001001; + 12'd1772 : mem_out_dec = 6'b001010; + 12'd1773 : mem_out_dec = 6'b001011; + 12'd1774 : mem_out_dec = 6'b001011; + 12'd1775 : mem_out_dec = 6'b001100; + 12'd1776 : mem_out_dec = 6'b001100; + 12'd1777 : mem_out_dec = 6'b001101; + 12'd1778 : mem_out_dec = 6'b001101; + 12'd1779 : mem_out_dec = 6'b001101; + 12'd1780 : mem_out_dec = 6'b001110; + 12'd1781 : mem_out_dec = 6'b001111; + 12'd1782 : mem_out_dec = 6'b001111; + 12'd1783 : mem_out_dec = 6'b010000; + 12'd1784 : mem_out_dec = 6'b010000; + 12'd1785 : mem_out_dec = 6'b010000; + 12'd1786 : mem_out_dec = 6'b010000; + 12'd1787 : mem_out_dec = 6'b010001; + 12'd1788 : mem_out_dec = 6'b010001; + 12'd1789 : mem_out_dec = 6'b010010; + 12'd1790 : mem_out_dec = 6'b010010; + 12'd1791 : mem_out_dec = 6'b010011; + 12'd1792 : mem_out_dec = 6'b111111; + 12'd1793 : mem_out_dec = 6'b111111; + 12'd1794 : mem_out_dec = 6'b111111; + 12'd1795 : mem_out_dec = 6'b111111; + 12'd1796 : mem_out_dec = 6'b111111; + 12'd1797 : mem_out_dec = 6'b111111; + 12'd1798 : mem_out_dec = 6'b111111; + 12'd1799 : mem_out_dec = 6'b111111; + 12'd1800 : mem_out_dec = 6'b111111; + 12'd1801 : mem_out_dec = 6'b111111; + 12'd1802 : mem_out_dec = 6'b111111; + 12'd1803 : mem_out_dec = 6'b111111; + 12'd1804 : mem_out_dec = 6'b111111; + 12'd1805 : mem_out_dec = 6'b111111; + 12'd1806 : mem_out_dec = 6'b111111; + 12'd1807 : mem_out_dec = 6'b111111; + 12'd1808 : mem_out_dec = 6'b111111; + 12'd1809 : mem_out_dec = 6'b111111; + 12'd1810 : mem_out_dec = 6'b111111; + 12'd1811 : mem_out_dec = 6'b111111; + 12'd1812 : mem_out_dec = 6'b111111; + 12'd1813 : mem_out_dec = 6'b111111; + 12'd1814 : mem_out_dec = 6'b111111; + 12'd1815 : mem_out_dec = 6'b111111; + 12'd1816 : mem_out_dec = 6'b111111; + 12'd1817 : mem_out_dec = 6'b111111; + 12'd1818 : mem_out_dec = 6'b111111; + 12'd1819 : mem_out_dec = 6'b111111; + 12'd1820 : mem_out_dec = 6'b111111; + 12'd1821 : mem_out_dec = 6'b111111; + 12'd1822 : mem_out_dec = 6'b111111; + 12'd1823 : mem_out_dec = 6'b111111; + 12'd1824 : mem_out_dec = 6'b111111; + 12'd1825 : mem_out_dec = 6'b111111; + 12'd1826 : mem_out_dec = 6'b000011; + 12'd1827 : mem_out_dec = 6'b000100; + 12'd1828 : mem_out_dec = 6'b000100; + 12'd1829 : mem_out_dec = 6'b000101; + 12'd1830 : mem_out_dec = 6'b000110; + 12'd1831 : mem_out_dec = 6'b000110; + 12'd1832 : mem_out_dec = 6'b000110; + 12'd1833 : mem_out_dec = 6'b000111; + 12'd1834 : mem_out_dec = 6'b001000; + 12'd1835 : mem_out_dec = 6'b001001; + 12'd1836 : mem_out_dec = 6'b001010; + 12'd1837 : mem_out_dec = 6'b001010; + 12'd1838 : mem_out_dec = 6'b001011; + 12'd1839 : mem_out_dec = 6'b001100; + 12'd1840 : mem_out_dec = 6'b001100; + 12'd1841 : mem_out_dec = 6'b001100; + 12'd1842 : mem_out_dec = 6'b001101; + 12'd1843 : mem_out_dec = 6'b001101; + 12'd1844 : mem_out_dec = 6'b001110; + 12'd1845 : mem_out_dec = 6'b001110; + 12'd1846 : mem_out_dec = 6'b001111; + 12'd1847 : mem_out_dec = 6'b010000; + 12'd1848 : mem_out_dec = 6'b001111; + 12'd1849 : mem_out_dec = 6'b001111; + 12'd1850 : mem_out_dec = 6'b010000; + 12'd1851 : mem_out_dec = 6'b010000; + 12'd1852 : mem_out_dec = 6'b010001; + 12'd1853 : mem_out_dec = 6'b010001; + 12'd1854 : mem_out_dec = 6'b010010; + 12'd1855 : mem_out_dec = 6'b010010; + 12'd1856 : mem_out_dec = 6'b111111; + 12'd1857 : mem_out_dec = 6'b111111; + 12'd1858 : mem_out_dec = 6'b111111; + 12'd1859 : mem_out_dec = 6'b111111; + 12'd1860 : mem_out_dec = 6'b111111; + 12'd1861 : mem_out_dec = 6'b111111; + 12'd1862 : mem_out_dec = 6'b111111; + 12'd1863 : mem_out_dec = 6'b111111; + 12'd1864 : mem_out_dec = 6'b111111; + 12'd1865 : mem_out_dec = 6'b111111; + 12'd1866 : mem_out_dec = 6'b111111; + 12'd1867 : mem_out_dec = 6'b111111; + 12'd1868 : mem_out_dec = 6'b111111; + 12'd1869 : mem_out_dec = 6'b111111; + 12'd1870 : mem_out_dec = 6'b111111; + 12'd1871 : mem_out_dec = 6'b111111; + 12'd1872 : mem_out_dec = 6'b111111; + 12'd1873 : mem_out_dec = 6'b111111; + 12'd1874 : mem_out_dec = 6'b111111; + 12'd1875 : mem_out_dec = 6'b111111; + 12'd1876 : mem_out_dec = 6'b111111; + 12'd1877 : mem_out_dec = 6'b111111; + 12'd1878 : mem_out_dec = 6'b111111; + 12'd1879 : mem_out_dec = 6'b111111; + 12'd1880 : mem_out_dec = 6'b111111; + 12'd1881 : mem_out_dec = 6'b111111; + 12'd1882 : mem_out_dec = 6'b111111; + 12'd1883 : mem_out_dec = 6'b111111; + 12'd1884 : mem_out_dec = 6'b111111; + 12'd1885 : mem_out_dec = 6'b111111; + 12'd1886 : mem_out_dec = 6'b111111; + 12'd1887 : mem_out_dec = 6'b111111; + 12'd1888 : mem_out_dec = 6'b111111; + 12'd1889 : mem_out_dec = 6'b111111; + 12'd1890 : mem_out_dec = 6'b111111; + 12'd1891 : mem_out_dec = 6'b000100; + 12'd1892 : mem_out_dec = 6'b000100; + 12'd1893 : mem_out_dec = 6'b000101; + 12'd1894 : mem_out_dec = 6'b000101; + 12'd1895 : mem_out_dec = 6'b000110; + 12'd1896 : mem_out_dec = 6'b000110; + 12'd1897 : mem_out_dec = 6'b000111; + 12'd1898 : mem_out_dec = 6'b001000; + 12'd1899 : mem_out_dec = 6'b001001; + 12'd1900 : mem_out_dec = 6'b001001; + 12'd1901 : mem_out_dec = 6'b001010; + 12'd1902 : mem_out_dec = 6'b001011; + 12'd1903 : mem_out_dec = 6'b001100; + 12'd1904 : mem_out_dec = 6'b001100; + 12'd1905 : mem_out_dec = 6'b001100; + 12'd1906 : mem_out_dec = 6'b001100; + 12'd1907 : mem_out_dec = 6'b001101; + 12'd1908 : mem_out_dec = 6'b001110; + 12'd1909 : mem_out_dec = 6'b001110; + 12'd1910 : mem_out_dec = 6'b001111; + 12'd1911 : mem_out_dec = 6'b001111; + 12'd1912 : mem_out_dec = 6'b001111; + 12'd1913 : mem_out_dec = 6'b001111; + 12'd1914 : mem_out_dec = 6'b001111; + 12'd1915 : mem_out_dec = 6'b010000; + 12'd1916 : mem_out_dec = 6'b010000; + 12'd1917 : mem_out_dec = 6'b010001; + 12'd1918 : mem_out_dec = 6'b010001; + 12'd1919 : mem_out_dec = 6'b010010; + 12'd1920 : mem_out_dec = 6'b111111; + 12'd1921 : mem_out_dec = 6'b111111; + 12'd1922 : mem_out_dec = 6'b111111; + 12'd1923 : mem_out_dec = 6'b111111; + 12'd1924 : mem_out_dec = 6'b111111; + 12'd1925 : mem_out_dec = 6'b111111; + 12'd1926 : mem_out_dec = 6'b111111; + 12'd1927 : mem_out_dec = 6'b111111; + 12'd1928 : mem_out_dec = 6'b111111; + 12'd1929 : mem_out_dec = 6'b111111; + 12'd1930 : mem_out_dec = 6'b111111; + 12'd1931 : mem_out_dec = 6'b111111; + 12'd1932 : mem_out_dec = 6'b111111; + 12'd1933 : mem_out_dec = 6'b111111; + 12'd1934 : mem_out_dec = 6'b111111; + 12'd1935 : mem_out_dec = 6'b111111; + 12'd1936 : mem_out_dec = 6'b111111; + 12'd1937 : mem_out_dec = 6'b111111; + 12'd1938 : mem_out_dec = 6'b111111; + 12'd1939 : mem_out_dec = 6'b111111; + 12'd1940 : mem_out_dec = 6'b111111; + 12'd1941 : mem_out_dec = 6'b111111; + 12'd1942 : mem_out_dec = 6'b111111; + 12'd1943 : mem_out_dec = 6'b111111; + 12'd1944 : mem_out_dec = 6'b111111; + 12'd1945 : mem_out_dec = 6'b111111; + 12'd1946 : mem_out_dec = 6'b111111; + 12'd1947 : mem_out_dec = 6'b111111; + 12'd1948 : mem_out_dec = 6'b111111; + 12'd1949 : mem_out_dec = 6'b111111; + 12'd1950 : mem_out_dec = 6'b111111; + 12'd1951 : mem_out_dec = 6'b111111; + 12'd1952 : mem_out_dec = 6'b111111; + 12'd1953 : mem_out_dec = 6'b111111; + 12'd1954 : mem_out_dec = 6'b111111; + 12'd1955 : mem_out_dec = 6'b111111; + 12'd1956 : mem_out_dec = 6'b000100; + 12'd1957 : mem_out_dec = 6'b000101; + 12'd1958 : mem_out_dec = 6'b000101; + 12'd1959 : mem_out_dec = 6'b000110; + 12'd1960 : mem_out_dec = 6'b000110; + 12'd1961 : mem_out_dec = 6'b000111; + 12'd1962 : mem_out_dec = 6'b001000; + 12'd1963 : mem_out_dec = 6'b001000; + 12'd1964 : mem_out_dec = 6'b001001; + 12'd1965 : mem_out_dec = 6'b001010; + 12'd1966 : mem_out_dec = 6'b001011; + 12'd1967 : mem_out_dec = 6'b001011; + 12'd1968 : mem_out_dec = 6'b001011; + 12'd1969 : mem_out_dec = 6'b001100; + 12'd1970 : mem_out_dec = 6'b001100; + 12'd1971 : mem_out_dec = 6'b001101; + 12'd1972 : mem_out_dec = 6'b001101; + 12'd1973 : mem_out_dec = 6'b001110; + 12'd1974 : mem_out_dec = 6'b001111; + 12'd1975 : mem_out_dec = 6'b001111; + 12'd1976 : mem_out_dec = 6'b001110; + 12'd1977 : mem_out_dec = 6'b001110; + 12'd1978 : mem_out_dec = 6'b001111; + 12'd1979 : mem_out_dec = 6'b001111; + 12'd1980 : mem_out_dec = 6'b010000; + 12'd1981 : mem_out_dec = 6'b010000; + 12'd1982 : mem_out_dec = 6'b010001; + 12'd1983 : mem_out_dec = 6'b010001; + 12'd1984 : mem_out_dec = 6'b111111; + 12'd1985 : mem_out_dec = 6'b111111; + 12'd1986 : mem_out_dec = 6'b111111; + 12'd1987 : mem_out_dec = 6'b111111; + 12'd1988 : mem_out_dec = 6'b111111; + 12'd1989 : mem_out_dec = 6'b111111; + 12'd1990 : mem_out_dec = 6'b111111; + 12'd1991 : mem_out_dec = 6'b111111; + 12'd1992 : mem_out_dec = 6'b111111; + 12'd1993 : mem_out_dec = 6'b111111; + 12'd1994 : mem_out_dec = 6'b111111; + 12'd1995 : mem_out_dec = 6'b111111; + 12'd1996 : mem_out_dec = 6'b111111; + 12'd1997 : mem_out_dec = 6'b111111; + 12'd1998 : mem_out_dec = 6'b111111; + 12'd1999 : mem_out_dec = 6'b111111; + 12'd2000 : mem_out_dec = 6'b111111; + 12'd2001 : mem_out_dec = 6'b111111; + 12'd2002 : mem_out_dec = 6'b111111; + 12'd2003 : mem_out_dec = 6'b111111; + 12'd2004 : mem_out_dec = 6'b111111; + 12'd2005 : mem_out_dec = 6'b111111; + 12'd2006 : mem_out_dec = 6'b111111; + 12'd2007 : mem_out_dec = 6'b111111; + 12'd2008 : mem_out_dec = 6'b111111; + 12'd2009 : mem_out_dec = 6'b111111; + 12'd2010 : mem_out_dec = 6'b111111; + 12'd2011 : mem_out_dec = 6'b111111; + 12'd2012 : mem_out_dec = 6'b111111; + 12'd2013 : mem_out_dec = 6'b111111; + 12'd2014 : mem_out_dec = 6'b111111; + 12'd2015 : mem_out_dec = 6'b111111; + 12'd2016 : mem_out_dec = 6'b111111; + 12'd2017 : mem_out_dec = 6'b111111; + 12'd2018 : mem_out_dec = 6'b111111; + 12'd2019 : mem_out_dec = 6'b111111; + 12'd2020 : mem_out_dec = 6'b111111; + 12'd2021 : mem_out_dec = 6'b000100; + 12'd2022 : mem_out_dec = 6'b000101; + 12'd2023 : mem_out_dec = 6'b000110; + 12'd2024 : mem_out_dec = 6'b000110; + 12'd2025 : mem_out_dec = 6'b000111; + 12'd2026 : mem_out_dec = 6'b000111; + 12'd2027 : mem_out_dec = 6'b001000; + 12'd2028 : mem_out_dec = 6'b001001; + 12'd2029 : mem_out_dec = 6'b001010; + 12'd2030 : mem_out_dec = 6'b001010; + 12'd2031 : mem_out_dec = 6'b001011; + 12'd2032 : mem_out_dec = 6'b001011; + 12'd2033 : mem_out_dec = 6'b001011; + 12'd2034 : mem_out_dec = 6'b001100; + 12'd2035 : mem_out_dec = 6'b001101; + 12'd2036 : mem_out_dec = 6'b001101; + 12'd2037 : mem_out_dec = 6'b001110; + 12'd2038 : mem_out_dec = 6'b001110; + 12'd2039 : mem_out_dec = 6'b001110; + 12'd2040 : mem_out_dec = 6'b001101; + 12'd2041 : mem_out_dec = 6'b001110; + 12'd2042 : mem_out_dec = 6'b001110; + 12'd2043 : mem_out_dec = 6'b001111; + 12'd2044 : mem_out_dec = 6'b001111; + 12'd2045 : mem_out_dec = 6'b010000; + 12'd2046 : mem_out_dec = 6'b010000; + 12'd2047 : mem_out_dec = 6'b010001; + 12'd2048 : mem_out_dec = 6'b111111; + 12'd2049 : mem_out_dec = 6'b111111; + 12'd2050 : mem_out_dec = 6'b111111; + 12'd2051 : mem_out_dec = 6'b111111; + 12'd2052 : mem_out_dec = 6'b111111; + 12'd2053 : mem_out_dec = 6'b111111; + 12'd2054 : mem_out_dec = 6'b111111; + 12'd2055 : mem_out_dec = 6'b111111; + 12'd2056 : mem_out_dec = 6'b111111; + 12'd2057 : mem_out_dec = 6'b111111; + 12'd2058 : mem_out_dec = 6'b111111; + 12'd2059 : mem_out_dec = 6'b111111; + 12'd2060 : mem_out_dec = 6'b111111; + 12'd2061 : mem_out_dec = 6'b111111; + 12'd2062 : mem_out_dec = 6'b111111; + 12'd2063 : mem_out_dec = 6'b111111; + 12'd2064 : mem_out_dec = 6'b111111; + 12'd2065 : mem_out_dec = 6'b111111; + 12'd2066 : mem_out_dec = 6'b111111; + 12'd2067 : mem_out_dec = 6'b111111; + 12'd2068 : mem_out_dec = 6'b111111; + 12'd2069 : mem_out_dec = 6'b111111; + 12'd2070 : mem_out_dec = 6'b111111; + 12'd2071 : mem_out_dec = 6'b111111; + 12'd2072 : mem_out_dec = 6'b111111; + 12'd2073 : mem_out_dec = 6'b111111; + 12'd2074 : mem_out_dec = 6'b111111; + 12'd2075 : mem_out_dec = 6'b111111; + 12'd2076 : mem_out_dec = 6'b111111; + 12'd2077 : mem_out_dec = 6'b111111; + 12'd2078 : mem_out_dec = 6'b111111; + 12'd2079 : mem_out_dec = 6'b111111; + 12'd2080 : mem_out_dec = 6'b111111; + 12'd2081 : mem_out_dec = 6'b111111; + 12'd2082 : mem_out_dec = 6'b111111; + 12'd2083 : mem_out_dec = 6'b111111; + 12'd2084 : mem_out_dec = 6'b111111; + 12'd2085 : mem_out_dec = 6'b111111; + 12'd2086 : mem_out_dec = 6'b000100; + 12'd2087 : mem_out_dec = 6'b000101; + 12'd2088 : mem_out_dec = 6'b000101; + 12'd2089 : mem_out_dec = 6'b000110; + 12'd2090 : mem_out_dec = 6'b000110; + 12'd2091 : mem_out_dec = 6'b000111; + 12'd2092 : mem_out_dec = 6'b001000; + 12'd2093 : mem_out_dec = 6'b001001; + 12'd2094 : mem_out_dec = 6'b001001; + 12'd2095 : mem_out_dec = 6'b001010; + 12'd2096 : mem_out_dec = 6'b001010; + 12'd2097 : mem_out_dec = 6'b001011; + 12'd2098 : mem_out_dec = 6'b001011; + 12'd2099 : mem_out_dec = 6'b001100; + 12'd2100 : mem_out_dec = 6'b001100; + 12'd2101 : mem_out_dec = 6'b001100; + 12'd2102 : mem_out_dec = 6'b001100; + 12'd2103 : mem_out_dec = 6'b001101; + 12'd2104 : mem_out_dec = 6'b001100; + 12'd2105 : mem_out_dec = 6'b001100; + 12'd2106 : mem_out_dec = 6'b001101; + 12'd2107 : mem_out_dec = 6'b001101; + 12'd2108 : mem_out_dec = 6'b001110; + 12'd2109 : mem_out_dec = 6'b001111; + 12'd2110 : mem_out_dec = 6'b010000; + 12'd2111 : mem_out_dec = 6'b010000; + 12'd2112 : mem_out_dec = 6'b111111; + 12'd2113 : mem_out_dec = 6'b111111; + 12'd2114 : mem_out_dec = 6'b111111; + 12'd2115 : mem_out_dec = 6'b111111; + 12'd2116 : mem_out_dec = 6'b111111; + 12'd2117 : mem_out_dec = 6'b111111; + 12'd2118 : mem_out_dec = 6'b111111; + 12'd2119 : mem_out_dec = 6'b111111; + 12'd2120 : mem_out_dec = 6'b111111; + 12'd2121 : mem_out_dec = 6'b111111; + 12'd2122 : mem_out_dec = 6'b111111; + 12'd2123 : mem_out_dec = 6'b111111; + 12'd2124 : mem_out_dec = 6'b111111; + 12'd2125 : mem_out_dec = 6'b111111; + 12'd2126 : mem_out_dec = 6'b111111; + 12'd2127 : mem_out_dec = 6'b111111; + 12'd2128 : mem_out_dec = 6'b111111; + 12'd2129 : mem_out_dec = 6'b111111; + 12'd2130 : mem_out_dec = 6'b111111; + 12'd2131 : mem_out_dec = 6'b111111; + 12'd2132 : mem_out_dec = 6'b111111; + 12'd2133 : mem_out_dec = 6'b111111; + 12'd2134 : mem_out_dec = 6'b111111; + 12'd2135 : mem_out_dec = 6'b111111; + 12'd2136 : mem_out_dec = 6'b111111; + 12'd2137 : mem_out_dec = 6'b111111; + 12'd2138 : mem_out_dec = 6'b111111; + 12'd2139 : mem_out_dec = 6'b111111; + 12'd2140 : mem_out_dec = 6'b111111; + 12'd2141 : mem_out_dec = 6'b111111; + 12'd2142 : mem_out_dec = 6'b111111; + 12'd2143 : mem_out_dec = 6'b111111; + 12'd2144 : mem_out_dec = 6'b111111; + 12'd2145 : mem_out_dec = 6'b111111; + 12'd2146 : mem_out_dec = 6'b111111; + 12'd2147 : mem_out_dec = 6'b111111; + 12'd2148 : mem_out_dec = 6'b111111; + 12'd2149 : mem_out_dec = 6'b111111; + 12'd2150 : mem_out_dec = 6'b111111; + 12'd2151 : mem_out_dec = 6'b000100; + 12'd2152 : mem_out_dec = 6'b000100; + 12'd2153 : mem_out_dec = 6'b000101; + 12'd2154 : mem_out_dec = 6'b000110; + 12'd2155 : mem_out_dec = 6'b000111; + 12'd2156 : mem_out_dec = 6'b000111; + 12'd2157 : mem_out_dec = 6'b001000; + 12'd2158 : mem_out_dec = 6'b001001; + 12'd2159 : mem_out_dec = 6'b001001; + 12'd2160 : mem_out_dec = 6'b001010; + 12'd2161 : mem_out_dec = 6'b001010; + 12'd2162 : mem_out_dec = 6'b001011; + 12'd2163 : mem_out_dec = 6'b001011; + 12'd2164 : mem_out_dec = 6'b001011; + 12'd2165 : mem_out_dec = 6'b001011; + 12'd2166 : mem_out_dec = 6'b001011; + 12'd2167 : mem_out_dec = 6'b001100; + 12'd2168 : mem_out_dec = 6'b001011; + 12'd2169 : mem_out_dec = 6'b001011; + 12'd2170 : mem_out_dec = 6'b001100; + 12'd2171 : mem_out_dec = 6'b001101; + 12'd2172 : mem_out_dec = 6'b001110; + 12'd2173 : mem_out_dec = 6'b001110; + 12'd2174 : mem_out_dec = 6'b001111; + 12'd2175 : mem_out_dec = 6'b010000; + 12'd2176 : mem_out_dec = 6'b111111; + 12'd2177 : mem_out_dec = 6'b111111; + 12'd2178 : mem_out_dec = 6'b111111; + 12'd2179 : mem_out_dec = 6'b111111; + 12'd2180 : mem_out_dec = 6'b111111; + 12'd2181 : mem_out_dec = 6'b111111; + 12'd2182 : mem_out_dec = 6'b111111; + 12'd2183 : mem_out_dec = 6'b111111; + 12'd2184 : mem_out_dec = 6'b111111; + 12'd2185 : mem_out_dec = 6'b111111; + 12'd2186 : mem_out_dec = 6'b111111; + 12'd2187 : mem_out_dec = 6'b111111; + 12'd2188 : mem_out_dec = 6'b111111; + 12'd2189 : mem_out_dec = 6'b111111; + 12'd2190 : mem_out_dec = 6'b111111; + 12'd2191 : mem_out_dec = 6'b111111; + 12'd2192 : mem_out_dec = 6'b111111; + 12'd2193 : mem_out_dec = 6'b111111; + 12'd2194 : mem_out_dec = 6'b111111; + 12'd2195 : mem_out_dec = 6'b111111; + 12'd2196 : mem_out_dec = 6'b111111; + 12'd2197 : mem_out_dec = 6'b111111; + 12'd2198 : mem_out_dec = 6'b111111; + 12'd2199 : mem_out_dec = 6'b111111; + 12'd2200 : mem_out_dec = 6'b111111; + 12'd2201 : mem_out_dec = 6'b111111; + 12'd2202 : mem_out_dec = 6'b111111; + 12'd2203 : mem_out_dec = 6'b111111; + 12'd2204 : mem_out_dec = 6'b111111; + 12'd2205 : mem_out_dec = 6'b111111; + 12'd2206 : mem_out_dec = 6'b111111; + 12'd2207 : mem_out_dec = 6'b111111; + 12'd2208 : mem_out_dec = 6'b111111; + 12'd2209 : mem_out_dec = 6'b111111; + 12'd2210 : mem_out_dec = 6'b111111; + 12'd2211 : mem_out_dec = 6'b111111; + 12'd2212 : mem_out_dec = 6'b111111; + 12'd2213 : mem_out_dec = 6'b111111; + 12'd2214 : mem_out_dec = 6'b111111; + 12'd2215 : mem_out_dec = 6'b111111; + 12'd2216 : mem_out_dec = 6'b000100; + 12'd2217 : mem_out_dec = 6'b000101; + 12'd2218 : mem_out_dec = 6'b000101; + 12'd2219 : mem_out_dec = 6'b000110; + 12'd2220 : mem_out_dec = 6'b000111; + 12'd2221 : mem_out_dec = 6'b000111; + 12'd2222 : mem_out_dec = 6'b001000; + 12'd2223 : mem_out_dec = 6'b001001; + 12'd2224 : mem_out_dec = 6'b001001; + 12'd2225 : mem_out_dec = 6'b001010; + 12'd2226 : mem_out_dec = 6'b001010; + 12'd2227 : mem_out_dec = 6'b001010; + 12'd2228 : mem_out_dec = 6'b001010; + 12'd2229 : mem_out_dec = 6'b001010; + 12'd2230 : mem_out_dec = 6'b001010; + 12'd2231 : mem_out_dec = 6'b001010; + 12'd2232 : mem_out_dec = 6'b001010; + 12'd2233 : mem_out_dec = 6'b001011; + 12'd2234 : mem_out_dec = 6'b001100; + 12'd2235 : mem_out_dec = 6'b001100; + 12'd2236 : mem_out_dec = 6'b001101; + 12'd2237 : mem_out_dec = 6'b001110; + 12'd2238 : mem_out_dec = 6'b001111; + 12'd2239 : mem_out_dec = 6'b010000; + 12'd2240 : mem_out_dec = 6'b111111; + 12'd2241 : mem_out_dec = 6'b111111; + 12'd2242 : mem_out_dec = 6'b111111; + 12'd2243 : mem_out_dec = 6'b111111; + 12'd2244 : mem_out_dec = 6'b111111; + 12'd2245 : mem_out_dec = 6'b111111; + 12'd2246 : mem_out_dec = 6'b111111; + 12'd2247 : mem_out_dec = 6'b111111; + 12'd2248 : mem_out_dec = 6'b111111; + 12'd2249 : mem_out_dec = 6'b111111; + 12'd2250 : mem_out_dec = 6'b111111; + 12'd2251 : mem_out_dec = 6'b111111; + 12'd2252 : mem_out_dec = 6'b111111; + 12'd2253 : mem_out_dec = 6'b111111; + 12'd2254 : mem_out_dec = 6'b111111; + 12'd2255 : mem_out_dec = 6'b111111; + 12'd2256 : mem_out_dec = 6'b111111; + 12'd2257 : mem_out_dec = 6'b111111; + 12'd2258 : mem_out_dec = 6'b111111; + 12'd2259 : mem_out_dec = 6'b111111; + 12'd2260 : mem_out_dec = 6'b111111; + 12'd2261 : mem_out_dec = 6'b111111; + 12'd2262 : mem_out_dec = 6'b111111; + 12'd2263 : mem_out_dec = 6'b111111; + 12'd2264 : mem_out_dec = 6'b111111; + 12'd2265 : mem_out_dec = 6'b111111; + 12'd2266 : mem_out_dec = 6'b111111; + 12'd2267 : mem_out_dec = 6'b111111; + 12'd2268 : mem_out_dec = 6'b111111; + 12'd2269 : mem_out_dec = 6'b111111; + 12'd2270 : mem_out_dec = 6'b111111; + 12'd2271 : mem_out_dec = 6'b111111; + 12'd2272 : mem_out_dec = 6'b111111; + 12'd2273 : mem_out_dec = 6'b111111; + 12'd2274 : mem_out_dec = 6'b111111; + 12'd2275 : mem_out_dec = 6'b111111; + 12'd2276 : mem_out_dec = 6'b111111; + 12'd2277 : mem_out_dec = 6'b111111; + 12'd2278 : mem_out_dec = 6'b111111; + 12'd2279 : mem_out_dec = 6'b111111; + 12'd2280 : mem_out_dec = 6'b111111; + 12'd2281 : mem_out_dec = 6'b000100; + 12'd2282 : mem_out_dec = 6'b000101; + 12'd2283 : mem_out_dec = 6'b000101; + 12'd2284 : mem_out_dec = 6'b000110; + 12'd2285 : mem_out_dec = 6'b000111; + 12'd2286 : mem_out_dec = 6'b001000; + 12'd2287 : mem_out_dec = 6'b001001; + 12'd2288 : mem_out_dec = 6'b001001; + 12'd2289 : mem_out_dec = 6'b001001; + 12'd2290 : mem_out_dec = 6'b001001; + 12'd2291 : mem_out_dec = 6'b001001; + 12'd2292 : mem_out_dec = 6'b001001; + 12'd2293 : mem_out_dec = 6'b001001; + 12'd2294 : mem_out_dec = 6'b001001; + 12'd2295 : mem_out_dec = 6'b001001; + 12'd2296 : mem_out_dec = 6'b001010; + 12'd2297 : mem_out_dec = 6'b001010; + 12'd2298 : mem_out_dec = 6'b001011; + 12'd2299 : mem_out_dec = 6'b001100; + 12'd2300 : mem_out_dec = 6'b001101; + 12'd2301 : mem_out_dec = 6'b001110; + 12'd2302 : mem_out_dec = 6'b001110; + 12'd2303 : mem_out_dec = 6'b001111; + 12'd2304 : mem_out_dec = 6'b111111; + 12'd2305 : mem_out_dec = 6'b111111; + 12'd2306 : mem_out_dec = 6'b111111; + 12'd2307 : mem_out_dec = 6'b111111; + 12'd2308 : mem_out_dec = 6'b111111; + 12'd2309 : mem_out_dec = 6'b111111; + 12'd2310 : mem_out_dec = 6'b111111; + 12'd2311 : mem_out_dec = 6'b111111; + 12'd2312 : mem_out_dec = 6'b111111; + 12'd2313 : mem_out_dec = 6'b111111; + 12'd2314 : mem_out_dec = 6'b111111; + 12'd2315 : mem_out_dec = 6'b111111; + 12'd2316 : mem_out_dec = 6'b111111; + 12'd2317 : mem_out_dec = 6'b111111; + 12'd2318 : mem_out_dec = 6'b111111; + 12'd2319 : mem_out_dec = 6'b111111; + 12'd2320 : mem_out_dec = 6'b111111; + 12'd2321 : mem_out_dec = 6'b111111; + 12'd2322 : mem_out_dec = 6'b111111; + 12'd2323 : mem_out_dec = 6'b111111; + 12'd2324 : mem_out_dec = 6'b111111; + 12'd2325 : mem_out_dec = 6'b111111; + 12'd2326 : mem_out_dec = 6'b111111; + 12'd2327 : mem_out_dec = 6'b111111; + 12'd2328 : mem_out_dec = 6'b111111; + 12'd2329 : mem_out_dec = 6'b111111; + 12'd2330 : mem_out_dec = 6'b111111; + 12'd2331 : mem_out_dec = 6'b111111; + 12'd2332 : mem_out_dec = 6'b111111; + 12'd2333 : mem_out_dec = 6'b111111; + 12'd2334 : mem_out_dec = 6'b111111; + 12'd2335 : mem_out_dec = 6'b111111; + 12'd2336 : mem_out_dec = 6'b111111; + 12'd2337 : mem_out_dec = 6'b111111; + 12'd2338 : mem_out_dec = 6'b111111; + 12'd2339 : mem_out_dec = 6'b111111; + 12'd2340 : mem_out_dec = 6'b111111; + 12'd2341 : mem_out_dec = 6'b111111; + 12'd2342 : mem_out_dec = 6'b111111; + 12'd2343 : mem_out_dec = 6'b111111; + 12'd2344 : mem_out_dec = 6'b111111; + 12'd2345 : mem_out_dec = 6'b111111; + 12'd2346 : mem_out_dec = 6'b000100; + 12'd2347 : mem_out_dec = 6'b000101; + 12'd2348 : mem_out_dec = 6'b000110; + 12'd2349 : mem_out_dec = 6'b000111; + 12'd2350 : mem_out_dec = 6'b000111; + 12'd2351 : mem_out_dec = 6'b001000; + 12'd2352 : mem_out_dec = 6'b001000; + 12'd2353 : mem_out_dec = 6'b001000; + 12'd2354 : mem_out_dec = 6'b001000; + 12'd2355 : mem_out_dec = 6'b001000; + 12'd2356 : mem_out_dec = 6'b001000; + 12'd2357 : mem_out_dec = 6'b001000; + 12'd2358 : mem_out_dec = 6'b001000; + 12'd2359 : mem_out_dec = 6'b001001; + 12'd2360 : mem_out_dec = 6'b001001; + 12'd2361 : mem_out_dec = 6'b001010; + 12'd2362 : mem_out_dec = 6'b001011; + 12'd2363 : mem_out_dec = 6'b001100; + 12'd2364 : mem_out_dec = 6'b001100; + 12'd2365 : mem_out_dec = 6'b001101; + 12'd2366 : mem_out_dec = 6'b001110; + 12'd2367 : mem_out_dec = 6'b001111; + 12'd2368 : mem_out_dec = 6'b111111; + 12'd2369 : mem_out_dec = 6'b111111; + 12'd2370 : mem_out_dec = 6'b111111; + 12'd2371 : mem_out_dec = 6'b111111; + 12'd2372 : mem_out_dec = 6'b111111; + 12'd2373 : mem_out_dec = 6'b111111; + 12'd2374 : mem_out_dec = 6'b111111; + 12'd2375 : mem_out_dec = 6'b111111; + 12'd2376 : mem_out_dec = 6'b111111; + 12'd2377 : mem_out_dec = 6'b111111; + 12'd2378 : mem_out_dec = 6'b111111; + 12'd2379 : mem_out_dec = 6'b111111; + 12'd2380 : mem_out_dec = 6'b111111; + 12'd2381 : mem_out_dec = 6'b111111; + 12'd2382 : mem_out_dec = 6'b111111; + 12'd2383 : mem_out_dec = 6'b111111; + 12'd2384 : mem_out_dec = 6'b111111; + 12'd2385 : mem_out_dec = 6'b111111; + 12'd2386 : mem_out_dec = 6'b111111; + 12'd2387 : mem_out_dec = 6'b111111; + 12'd2388 : mem_out_dec = 6'b111111; + 12'd2389 : mem_out_dec = 6'b111111; + 12'd2390 : mem_out_dec = 6'b111111; + 12'd2391 : mem_out_dec = 6'b111111; + 12'd2392 : mem_out_dec = 6'b111111; + 12'd2393 : mem_out_dec = 6'b111111; + 12'd2394 : mem_out_dec = 6'b111111; + 12'd2395 : mem_out_dec = 6'b111111; + 12'd2396 : mem_out_dec = 6'b111111; + 12'd2397 : mem_out_dec = 6'b111111; + 12'd2398 : mem_out_dec = 6'b111111; + 12'd2399 : mem_out_dec = 6'b111111; + 12'd2400 : mem_out_dec = 6'b111111; + 12'd2401 : mem_out_dec = 6'b111111; + 12'd2402 : mem_out_dec = 6'b111111; + 12'd2403 : mem_out_dec = 6'b111111; + 12'd2404 : mem_out_dec = 6'b111111; + 12'd2405 : mem_out_dec = 6'b111111; + 12'd2406 : mem_out_dec = 6'b111111; + 12'd2407 : mem_out_dec = 6'b111111; + 12'd2408 : mem_out_dec = 6'b111111; + 12'd2409 : mem_out_dec = 6'b111111; + 12'd2410 : mem_out_dec = 6'b111111; + 12'd2411 : mem_out_dec = 6'b000101; + 12'd2412 : mem_out_dec = 6'b000101; + 12'd2413 : mem_out_dec = 6'b000110; + 12'd2414 : mem_out_dec = 6'b000111; + 12'd2415 : mem_out_dec = 6'b001000; + 12'd2416 : mem_out_dec = 6'b000111; + 12'd2417 : mem_out_dec = 6'b000111; + 12'd2418 : mem_out_dec = 6'b000111; + 12'd2419 : mem_out_dec = 6'b000111; + 12'd2420 : mem_out_dec = 6'b000111; + 12'd2421 : mem_out_dec = 6'b000111; + 12'd2422 : mem_out_dec = 6'b001000; + 12'd2423 : mem_out_dec = 6'b001001; + 12'd2424 : mem_out_dec = 6'b001001; + 12'd2425 : mem_out_dec = 6'b001010; + 12'd2426 : mem_out_dec = 6'b001010; + 12'd2427 : mem_out_dec = 6'b001011; + 12'd2428 : mem_out_dec = 6'b001100; + 12'd2429 : mem_out_dec = 6'b001101; + 12'd2430 : mem_out_dec = 6'b001101; + 12'd2431 : mem_out_dec = 6'b001110; + 12'd2432 : mem_out_dec = 6'b111111; + 12'd2433 : mem_out_dec = 6'b111111; + 12'd2434 : mem_out_dec = 6'b111111; + 12'd2435 : mem_out_dec = 6'b111111; + 12'd2436 : mem_out_dec = 6'b111111; + 12'd2437 : mem_out_dec = 6'b111111; + 12'd2438 : mem_out_dec = 6'b111111; + 12'd2439 : mem_out_dec = 6'b111111; + 12'd2440 : mem_out_dec = 6'b111111; + 12'd2441 : mem_out_dec = 6'b111111; + 12'd2442 : mem_out_dec = 6'b111111; + 12'd2443 : mem_out_dec = 6'b111111; + 12'd2444 : mem_out_dec = 6'b111111; + 12'd2445 : mem_out_dec = 6'b111111; + 12'd2446 : mem_out_dec = 6'b111111; + 12'd2447 : mem_out_dec = 6'b111111; + 12'd2448 : mem_out_dec = 6'b111111; + 12'd2449 : mem_out_dec = 6'b111111; + 12'd2450 : mem_out_dec = 6'b111111; + 12'd2451 : mem_out_dec = 6'b111111; + 12'd2452 : mem_out_dec = 6'b111111; + 12'd2453 : mem_out_dec = 6'b111111; + 12'd2454 : mem_out_dec = 6'b111111; + 12'd2455 : mem_out_dec = 6'b111111; + 12'd2456 : mem_out_dec = 6'b111111; + 12'd2457 : mem_out_dec = 6'b111111; + 12'd2458 : mem_out_dec = 6'b111111; + 12'd2459 : mem_out_dec = 6'b111111; + 12'd2460 : mem_out_dec = 6'b111111; + 12'd2461 : mem_out_dec = 6'b111111; + 12'd2462 : mem_out_dec = 6'b111111; + 12'd2463 : mem_out_dec = 6'b111111; + 12'd2464 : mem_out_dec = 6'b111111; + 12'd2465 : mem_out_dec = 6'b111111; + 12'd2466 : mem_out_dec = 6'b111111; + 12'd2467 : mem_out_dec = 6'b111111; + 12'd2468 : mem_out_dec = 6'b111111; + 12'd2469 : mem_out_dec = 6'b111111; + 12'd2470 : mem_out_dec = 6'b111111; + 12'd2471 : mem_out_dec = 6'b111111; + 12'd2472 : mem_out_dec = 6'b111111; + 12'd2473 : mem_out_dec = 6'b111111; + 12'd2474 : mem_out_dec = 6'b111111; + 12'd2475 : mem_out_dec = 6'b111111; + 12'd2476 : mem_out_dec = 6'b000101; + 12'd2477 : mem_out_dec = 6'b000110; + 12'd2478 : mem_out_dec = 6'b000111; + 12'd2479 : mem_out_dec = 6'b000111; + 12'd2480 : mem_out_dec = 6'b000110; + 12'd2481 : mem_out_dec = 6'b000110; + 12'd2482 : mem_out_dec = 6'b000110; + 12'd2483 : mem_out_dec = 6'b000110; + 12'd2484 : mem_out_dec = 6'b000110; + 12'd2485 : mem_out_dec = 6'b000111; + 12'd2486 : mem_out_dec = 6'b000111; + 12'd2487 : mem_out_dec = 6'b001000; + 12'd2488 : mem_out_dec = 6'b001001; + 12'd2489 : mem_out_dec = 6'b001001; + 12'd2490 : mem_out_dec = 6'b001010; + 12'd2491 : mem_out_dec = 6'b001011; + 12'd2492 : mem_out_dec = 6'b001011; + 12'd2493 : mem_out_dec = 6'b001100; + 12'd2494 : mem_out_dec = 6'b001101; + 12'd2495 : mem_out_dec = 6'b001110; + 12'd2496 : mem_out_dec = 6'b111111; + 12'd2497 : mem_out_dec = 6'b111111; + 12'd2498 : mem_out_dec = 6'b111111; + 12'd2499 : mem_out_dec = 6'b111111; + 12'd2500 : mem_out_dec = 6'b111111; + 12'd2501 : mem_out_dec = 6'b111111; + 12'd2502 : mem_out_dec = 6'b111111; + 12'd2503 : mem_out_dec = 6'b111111; + 12'd2504 : mem_out_dec = 6'b111111; + 12'd2505 : mem_out_dec = 6'b111111; + 12'd2506 : mem_out_dec = 6'b111111; + 12'd2507 : mem_out_dec = 6'b111111; + 12'd2508 : mem_out_dec = 6'b111111; + 12'd2509 : mem_out_dec = 6'b111111; + 12'd2510 : mem_out_dec = 6'b111111; + 12'd2511 : mem_out_dec = 6'b111111; + 12'd2512 : mem_out_dec = 6'b111111; + 12'd2513 : mem_out_dec = 6'b111111; + 12'd2514 : mem_out_dec = 6'b111111; + 12'd2515 : mem_out_dec = 6'b111111; + 12'd2516 : mem_out_dec = 6'b111111; + 12'd2517 : mem_out_dec = 6'b111111; + 12'd2518 : mem_out_dec = 6'b111111; + 12'd2519 : mem_out_dec = 6'b111111; + 12'd2520 : mem_out_dec = 6'b111111; + 12'd2521 : mem_out_dec = 6'b111111; + 12'd2522 : mem_out_dec = 6'b111111; + 12'd2523 : mem_out_dec = 6'b111111; + 12'd2524 : mem_out_dec = 6'b111111; + 12'd2525 : mem_out_dec = 6'b111111; + 12'd2526 : mem_out_dec = 6'b111111; + 12'd2527 : mem_out_dec = 6'b111111; + 12'd2528 : mem_out_dec = 6'b111111; + 12'd2529 : mem_out_dec = 6'b111111; + 12'd2530 : mem_out_dec = 6'b111111; + 12'd2531 : mem_out_dec = 6'b111111; + 12'd2532 : mem_out_dec = 6'b111111; + 12'd2533 : mem_out_dec = 6'b111111; + 12'd2534 : mem_out_dec = 6'b111111; + 12'd2535 : mem_out_dec = 6'b111111; + 12'd2536 : mem_out_dec = 6'b111111; + 12'd2537 : mem_out_dec = 6'b111111; + 12'd2538 : mem_out_dec = 6'b111111; + 12'd2539 : mem_out_dec = 6'b111111; + 12'd2540 : mem_out_dec = 6'b111111; + 12'd2541 : mem_out_dec = 6'b000101; + 12'd2542 : mem_out_dec = 6'b000110; + 12'd2543 : mem_out_dec = 6'b000110; + 12'd2544 : mem_out_dec = 6'b000110; + 12'd2545 : mem_out_dec = 6'b000110; + 12'd2546 : mem_out_dec = 6'b000101; + 12'd2547 : mem_out_dec = 6'b000101; + 12'd2548 : mem_out_dec = 6'b000110; + 12'd2549 : mem_out_dec = 6'b000111; + 12'd2550 : mem_out_dec = 6'b000111; + 12'd2551 : mem_out_dec = 6'b001000; + 12'd2552 : mem_out_dec = 6'b001000; + 12'd2553 : mem_out_dec = 6'b001001; + 12'd2554 : mem_out_dec = 6'b001010; + 12'd2555 : mem_out_dec = 6'b001010; + 12'd2556 : mem_out_dec = 6'b001011; + 12'd2557 : mem_out_dec = 6'b001100; + 12'd2558 : mem_out_dec = 6'b001101; + 12'd2559 : mem_out_dec = 6'b001101; + 12'd2560 : mem_out_dec = 6'b111111; + 12'd2561 : mem_out_dec = 6'b111111; + 12'd2562 : mem_out_dec = 6'b111111; + 12'd2563 : mem_out_dec = 6'b111111; + 12'd2564 : mem_out_dec = 6'b111111; + 12'd2565 : mem_out_dec = 6'b111111; + 12'd2566 : mem_out_dec = 6'b111111; + 12'd2567 : mem_out_dec = 6'b111111; + 12'd2568 : mem_out_dec = 6'b111111; + 12'd2569 : mem_out_dec = 6'b111111; + 12'd2570 : mem_out_dec = 6'b111111; + 12'd2571 : mem_out_dec = 6'b111111; + 12'd2572 : mem_out_dec = 6'b111111; + 12'd2573 : mem_out_dec = 6'b111111; + 12'd2574 : mem_out_dec = 6'b111111; + 12'd2575 : mem_out_dec = 6'b111111; + 12'd2576 : mem_out_dec = 6'b111111; + 12'd2577 : mem_out_dec = 6'b111111; + 12'd2578 : mem_out_dec = 6'b111111; + 12'd2579 : mem_out_dec = 6'b111111; + 12'd2580 : mem_out_dec = 6'b111111; + 12'd2581 : mem_out_dec = 6'b111111; + 12'd2582 : mem_out_dec = 6'b111111; + 12'd2583 : mem_out_dec = 6'b111111; + 12'd2584 : mem_out_dec = 6'b111111; + 12'd2585 : mem_out_dec = 6'b111111; + 12'd2586 : mem_out_dec = 6'b111111; + 12'd2587 : mem_out_dec = 6'b111111; + 12'd2588 : mem_out_dec = 6'b111111; + 12'd2589 : mem_out_dec = 6'b111111; + 12'd2590 : mem_out_dec = 6'b111111; + 12'd2591 : mem_out_dec = 6'b111111; + 12'd2592 : mem_out_dec = 6'b111111; + 12'd2593 : mem_out_dec = 6'b111111; + 12'd2594 : mem_out_dec = 6'b111111; + 12'd2595 : mem_out_dec = 6'b111111; + 12'd2596 : mem_out_dec = 6'b111111; + 12'd2597 : mem_out_dec = 6'b111111; + 12'd2598 : mem_out_dec = 6'b111111; + 12'd2599 : mem_out_dec = 6'b111111; + 12'd2600 : mem_out_dec = 6'b111111; + 12'd2601 : mem_out_dec = 6'b111111; + 12'd2602 : mem_out_dec = 6'b111111; + 12'd2603 : mem_out_dec = 6'b111111; + 12'd2604 : mem_out_dec = 6'b111111; + 12'd2605 : mem_out_dec = 6'b111111; + 12'd2606 : mem_out_dec = 6'b000100; + 12'd2607 : mem_out_dec = 6'b000101; + 12'd2608 : mem_out_dec = 6'b000100; + 12'd2609 : mem_out_dec = 6'b000100; + 12'd2610 : mem_out_dec = 6'b000100; + 12'd2611 : mem_out_dec = 6'b000101; + 12'd2612 : mem_out_dec = 6'b000101; + 12'd2613 : mem_out_dec = 6'b000110; + 12'd2614 : mem_out_dec = 6'b000111; + 12'd2615 : mem_out_dec = 6'b000111; + 12'd2616 : mem_out_dec = 6'b000111; + 12'd2617 : mem_out_dec = 6'b001000; + 12'd2618 : mem_out_dec = 6'b001001; + 12'd2619 : mem_out_dec = 6'b001010; + 12'd2620 : mem_out_dec = 6'b001010; + 12'd2621 : mem_out_dec = 6'b001011; + 12'd2622 : mem_out_dec = 6'b001100; + 12'd2623 : mem_out_dec = 6'b001101; + 12'd2624 : mem_out_dec = 6'b111111; + 12'd2625 : mem_out_dec = 6'b111111; + 12'd2626 : mem_out_dec = 6'b111111; + 12'd2627 : mem_out_dec = 6'b111111; + 12'd2628 : mem_out_dec = 6'b111111; + 12'd2629 : mem_out_dec = 6'b111111; + 12'd2630 : mem_out_dec = 6'b111111; + 12'd2631 : mem_out_dec = 6'b111111; + 12'd2632 : mem_out_dec = 6'b111111; + 12'd2633 : mem_out_dec = 6'b111111; + 12'd2634 : mem_out_dec = 6'b111111; + 12'd2635 : mem_out_dec = 6'b111111; + 12'd2636 : mem_out_dec = 6'b111111; + 12'd2637 : mem_out_dec = 6'b111111; + 12'd2638 : mem_out_dec = 6'b111111; + 12'd2639 : mem_out_dec = 6'b111111; + 12'd2640 : mem_out_dec = 6'b111111; + 12'd2641 : mem_out_dec = 6'b111111; + 12'd2642 : mem_out_dec = 6'b111111; + 12'd2643 : mem_out_dec = 6'b111111; + 12'd2644 : mem_out_dec = 6'b111111; + 12'd2645 : mem_out_dec = 6'b111111; + 12'd2646 : mem_out_dec = 6'b111111; + 12'd2647 : mem_out_dec = 6'b111111; + 12'd2648 : mem_out_dec = 6'b111111; + 12'd2649 : mem_out_dec = 6'b111111; + 12'd2650 : mem_out_dec = 6'b111111; + 12'd2651 : mem_out_dec = 6'b111111; + 12'd2652 : mem_out_dec = 6'b111111; + 12'd2653 : mem_out_dec = 6'b111111; + 12'd2654 : mem_out_dec = 6'b111111; + 12'd2655 : mem_out_dec = 6'b111111; + 12'd2656 : mem_out_dec = 6'b111111; + 12'd2657 : mem_out_dec = 6'b111111; + 12'd2658 : mem_out_dec = 6'b111111; + 12'd2659 : mem_out_dec = 6'b111111; + 12'd2660 : mem_out_dec = 6'b111111; + 12'd2661 : mem_out_dec = 6'b111111; + 12'd2662 : mem_out_dec = 6'b111111; + 12'd2663 : mem_out_dec = 6'b111111; + 12'd2664 : mem_out_dec = 6'b111111; + 12'd2665 : mem_out_dec = 6'b111111; + 12'd2666 : mem_out_dec = 6'b111111; + 12'd2667 : mem_out_dec = 6'b111111; + 12'd2668 : mem_out_dec = 6'b111111; + 12'd2669 : mem_out_dec = 6'b111111; + 12'd2670 : mem_out_dec = 6'b111111; + 12'd2671 : mem_out_dec = 6'b000100; + 12'd2672 : mem_out_dec = 6'b000011; + 12'd2673 : mem_out_dec = 6'b000011; + 12'd2674 : mem_out_dec = 6'b000100; + 12'd2675 : mem_out_dec = 6'b000100; + 12'd2676 : mem_out_dec = 6'b000101; + 12'd2677 : mem_out_dec = 6'b000110; + 12'd2678 : mem_out_dec = 6'b000110; + 12'd2679 : mem_out_dec = 6'b000111; + 12'd2680 : mem_out_dec = 6'b000111; + 12'd2681 : mem_out_dec = 6'b001000; + 12'd2682 : mem_out_dec = 6'b001001; + 12'd2683 : mem_out_dec = 6'b001001; + 12'd2684 : mem_out_dec = 6'b001010; + 12'd2685 : mem_out_dec = 6'b001011; + 12'd2686 : mem_out_dec = 6'b001100; + 12'd2687 : mem_out_dec = 6'b001100; + 12'd2688 : mem_out_dec = 6'b111111; + 12'd2689 : mem_out_dec = 6'b111111; + 12'd2690 : mem_out_dec = 6'b111111; + 12'd2691 : mem_out_dec = 6'b111111; + 12'd2692 : mem_out_dec = 6'b111111; + 12'd2693 : mem_out_dec = 6'b111111; + 12'd2694 : mem_out_dec = 6'b111111; + 12'd2695 : mem_out_dec = 6'b111111; + 12'd2696 : mem_out_dec = 6'b111111; + 12'd2697 : mem_out_dec = 6'b111111; + 12'd2698 : mem_out_dec = 6'b111111; + 12'd2699 : mem_out_dec = 6'b111111; + 12'd2700 : mem_out_dec = 6'b111111; + 12'd2701 : mem_out_dec = 6'b111111; + 12'd2702 : mem_out_dec = 6'b111111; + 12'd2703 : mem_out_dec = 6'b111111; + 12'd2704 : mem_out_dec = 6'b111111; + 12'd2705 : mem_out_dec = 6'b111111; + 12'd2706 : mem_out_dec = 6'b111111; + 12'd2707 : mem_out_dec = 6'b111111; + 12'd2708 : mem_out_dec = 6'b111111; + 12'd2709 : mem_out_dec = 6'b111111; + 12'd2710 : mem_out_dec = 6'b111111; + 12'd2711 : mem_out_dec = 6'b111111; + 12'd2712 : mem_out_dec = 6'b111111; + 12'd2713 : mem_out_dec = 6'b111111; + 12'd2714 : mem_out_dec = 6'b111111; + 12'd2715 : mem_out_dec = 6'b111111; + 12'd2716 : mem_out_dec = 6'b111111; + 12'd2717 : mem_out_dec = 6'b111111; + 12'd2718 : mem_out_dec = 6'b111111; + 12'd2719 : mem_out_dec = 6'b111111; + 12'd2720 : mem_out_dec = 6'b111111; + 12'd2721 : mem_out_dec = 6'b111111; + 12'd2722 : mem_out_dec = 6'b111111; + 12'd2723 : mem_out_dec = 6'b111111; + 12'd2724 : mem_out_dec = 6'b111111; + 12'd2725 : mem_out_dec = 6'b111111; + 12'd2726 : mem_out_dec = 6'b111111; + 12'd2727 : mem_out_dec = 6'b111111; + 12'd2728 : mem_out_dec = 6'b111111; + 12'd2729 : mem_out_dec = 6'b111111; + 12'd2730 : mem_out_dec = 6'b111111; + 12'd2731 : mem_out_dec = 6'b111111; + 12'd2732 : mem_out_dec = 6'b111111; + 12'd2733 : mem_out_dec = 6'b111111; + 12'd2734 : mem_out_dec = 6'b111111; + 12'd2735 : mem_out_dec = 6'b111111; + 12'd2736 : mem_out_dec = 6'b000011; + 12'd2737 : mem_out_dec = 6'b000011; + 12'd2738 : mem_out_dec = 6'b000100; + 12'd2739 : mem_out_dec = 6'b000100; + 12'd2740 : mem_out_dec = 6'b000101; + 12'd2741 : mem_out_dec = 6'b000101; + 12'd2742 : mem_out_dec = 6'b000110; + 12'd2743 : mem_out_dec = 6'b000111; + 12'd2744 : mem_out_dec = 6'b000111; + 12'd2745 : mem_out_dec = 6'b001000; + 12'd2746 : mem_out_dec = 6'b001000; + 12'd2747 : mem_out_dec = 6'b001001; + 12'd2748 : mem_out_dec = 6'b001010; + 12'd2749 : mem_out_dec = 6'b001011; + 12'd2750 : mem_out_dec = 6'b001011; + 12'd2751 : mem_out_dec = 6'b001100; + 12'd2752 : mem_out_dec = 6'b111111; + 12'd2753 : mem_out_dec = 6'b111111; + 12'd2754 : mem_out_dec = 6'b111111; + 12'd2755 : mem_out_dec = 6'b111111; + 12'd2756 : mem_out_dec = 6'b111111; + 12'd2757 : mem_out_dec = 6'b111111; + 12'd2758 : mem_out_dec = 6'b111111; + 12'd2759 : mem_out_dec = 6'b111111; + 12'd2760 : mem_out_dec = 6'b111111; + 12'd2761 : mem_out_dec = 6'b111111; + 12'd2762 : mem_out_dec = 6'b111111; + 12'd2763 : mem_out_dec = 6'b111111; + 12'd2764 : mem_out_dec = 6'b111111; + 12'd2765 : mem_out_dec = 6'b111111; + 12'd2766 : mem_out_dec = 6'b111111; + 12'd2767 : mem_out_dec = 6'b111111; + 12'd2768 : mem_out_dec = 6'b111111; + 12'd2769 : mem_out_dec = 6'b111111; + 12'd2770 : mem_out_dec = 6'b111111; + 12'd2771 : mem_out_dec = 6'b111111; + 12'd2772 : mem_out_dec = 6'b111111; + 12'd2773 : mem_out_dec = 6'b111111; + 12'd2774 : mem_out_dec = 6'b111111; + 12'd2775 : mem_out_dec = 6'b111111; + 12'd2776 : mem_out_dec = 6'b111111; + 12'd2777 : mem_out_dec = 6'b111111; + 12'd2778 : mem_out_dec = 6'b111111; + 12'd2779 : mem_out_dec = 6'b111111; + 12'd2780 : mem_out_dec = 6'b111111; + 12'd2781 : mem_out_dec = 6'b111111; + 12'd2782 : mem_out_dec = 6'b111111; + 12'd2783 : mem_out_dec = 6'b111111; + 12'd2784 : mem_out_dec = 6'b111111; + 12'd2785 : mem_out_dec = 6'b111111; + 12'd2786 : mem_out_dec = 6'b111111; + 12'd2787 : mem_out_dec = 6'b111111; + 12'd2788 : mem_out_dec = 6'b111111; + 12'd2789 : mem_out_dec = 6'b111111; + 12'd2790 : mem_out_dec = 6'b111111; + 12'd2791 : mem_out_dec = 6'b111111; + 12'd2792 : mem_out_dec = 6'b111111; + 12'd2793 : mem_out_dec = 6'b111111; + 12'd2794 : mem_out_dec = 6'b111111; + 12'd2795 : mem_out_dec = 6'b111111; + 12'd2796 : mem_out_dec = 6'b111111; + 12'd2797 : mem_out_dec = 6'b111111; + 12'd2798 : mem_out_dec = 6'b111111; + 12'd2799 : mem_out_dec = 6'b111111; + 12'd2800 : mem_out_dec = 6'b111111; + 12'd2801 : mem_out_dec = 6'b000011; + 12'd2802 : mem_out_dec = 6'b000011; + 12'd2803 : mem_out_dec = 6'b000100; + 12'd2804 : mem_out_dec = 6'b000101; + 12'd2805 : mem_out_dec = 6'b000101; + 12'd2806 : mem_out_dec = 6'b000110; + 12'd2807 : mem_out_dec = 6'b000111; + 12'd2808 : mem_out_dec = 6'b000111; + 12'd2809 : mem_out_dec = 6'b000111; + 12'd2810 : mem_out_dec = 6'b001000; + 12'd2811 : mem_out_dec = 6'b001001; + 12'd2812 : mem_out_dec = 6'b001010; + 12'd2813 : mem_out_dec = 6'b001010; + 12'd2814 : mem_out_dec = 6'b001011; + 12'd2815 : mem_out_dec = 6'b001100; + 12'd2816 : mem_out_dec = 6'b111111; + 12'd2817 : mem_out_dec = 6'b111111; + 12'd2818 : mem_out_dec = 6'b111111; + 12'd2819 : mem_out_dec = 6'b111111; + 12'd2820 : mem_out_dec = 6'b111111; + 12'd2821 : mem_out_dec = 6'b111111; + 12'd2822 : mem_out_dec = 6'b111111; + 12'd2823 : mem_out_dec = 6'b111111; + 12'd2824 : mem_out_dec = 6'b111111; + 12'd2825 : mem_out_dec = 6'b111111; + 12'd2826 : mem_out_dec = 6'b111111; + 12'd2827 : mem_out_dec = 6'b111111; + 12'd2828 : mem_out_dec = 6'b111111; + 12'd2829 : mem_out_dec = 6'b111111; + 12'd2830 : mem_out_dec = 6'b111111; + 12'd2831 : mem_out_dec = 6'b111111; + 12'd2832 : mem_out_dec = 6'b111111; + 12'd2833 : mem_out_dec = 6'b111111; + 12'd2834 : mem_out_dec = 6'b111111; + 12'd2835 : mem_out_dec = 6'b111111; + 12'd2836 : mem_out_dec = 6'b111111; + 12'd2837 : mem_out_dec = 6'b111111; + 12'd2838 : mem_out_dec = 6'b111111; + 12'd2839 : mem_out_dec = 6'b111111; + 12'd2840 : mem_out_dec = 6'b111111; + 12'd2841 : mem_out_dec = 6'b111111; + 12'd2842 : mem_out_dec = 6'b111111; + 12'd2843 : mem_out_dec = 6'b111111; + 12'd2844 : mem_out_dec = 6'b111111; + 12'd2845 : mem_out_dec = 6'b111111; + 12'd2846 : mem_out_dec = 6'b111111; + 12'd2847 : mem_out_dec = 6'b111111; + 12'd2848 : mem_out_dec = 6'b111111; + 12'd2849 : mem_out_dec = 6'b111111; + 12'd2850 : mem_out_dec = 6'b111111; + 12'd2851 : mem_out_dec = 6'b111111; + 12'd2852 : mem_out_dec = 6'b111111; + 12'd2853 : mem_out_dec = 6'b111111; + 12'd2854 : mem_out_dec = 6'b111111; + 12'd2855 : mem_out_dec = 6'b111111; + 12'd2856 : mem_out_dec = 6'b111111; + 12'd2857 : mem_out_dec = 6'b111111; + 12'd2858 : mem_out_dec = 6'b111111; + 12'd2859 : mem_out_dec = 6'b111111; + 12'd2860 : mem_out_dec = 6'b111111; + 12'd2861 : mem_out_dec = 6'b111111; + 12'd2862 : mem_out_dec = 6'b111111; + 12'd2863 : mem_out_dec = 6'b111111; + 12'd2864 : mem_out_dec = 6'b111111; + 12'd2865 : mem_out_dec = 6'b111111; + 12'd2866 : mem_out_dec = 6'b000011; + 12'd2867 : mem_out_dec = 6'b000100; + 12'd2868 : mem_out_dec = 6'b000100; + 12'd2869 : mem_out_dec = 6'b000101; + 12'd2870 : mem_out_dec = 6'b000110; + 12'd2871 : mem_out_dec = 6'b000110; + 12'd2872 : mem_out_dec = 6'b000110; + 12'd2873 : mem_out_dec = 6'b000111; + 12'd2874 : mem_out_dec = 6'b001000; + 12'd2875 : mem_out_dec = 6'b001001; + 12'd2876 : mem_out_dec = 6'b001001; + 12'd2877 : mem_out_dec = 6'b001010; + 12'd2878 : mem_out_dec = 6'b001011; + 12'd2879 : mem_out_dec = 6'b001100; + 12'd2880 : mem_out_dec = 6'b111111; + 12'd2881 : mem_out_dec = 6'b111111; + 12'd2882 : mem_out_dec = 6'b111111; + 12'd2883 : mem_out_dec = 6'b111111; + 12'd2884 : mem_out_dec = 6'b111111; + 12'd2885 : mem_out_dec = 6'b111111; + 12'd2886 : mem_out_dec = 6'b111111; + 12'd2887 : mem_out_dec = 6'b111111; + 12'd2888 : mem_out_dec = 6'b111111; + 12'd2889 : mem_out_dec = 6'b111111; + 12'd2890 : mem_out_dec = 6'b111111; + 12'd2891 : mem_out_dec = 6'b111111; + 12'd2892 : mem_out_dec = 6'b111111; + 12'd2893 : mem_out_dec = 6'b111111; + 12'd2894 : mem_out_dec = 6'b111111; + 12'd2895 : mem_out_dec = 6'b111111; + 12'd2896 : mem_out_dec = 6'b111111; + 12'd2897 : mem_out_dec = 6'b111111; + 12'd2898 : mem_out_dec = 6'b111111; + 12'd2899 : mem_out_dec = 6'b111111; + 12'd2900 : mem_out_dec = 6'b111111; + 12'd2901 : mem_out_dec = 6'b111111; + 12'd2902 : mem_out_dec = 6'b111111; + 12'd2903 : mem_out_dec = 6'b111111; + 12'd2904 : mem_out_dec = 6'b111111; + 12'd2905 : mem_out_dec = 6'b111111; + 12'd2906 : mem_out_dec = 6'b111111; + 12'd2907 : mem_out_dec = 6'b111111; + 12'd2908 : mem_out_dec = 6'b111111; + 12'd2909 : mem_out_dec = 6'b111111; + 12'd2910 : mem_out_dec = 6'b111111; + 12'd2911 : mem_out_dec = 6'b111111; + 12'd2912 : mem_out_dec = 6'b111111; + 12'd2913 : mem_out_dec = 6'b111111; + 12'd2914 : mem_out_dec = 6'b111111; + 12'd2915 : mem_out_dec = 6'b111111; + 12'd2916 : mem_out_dec = 6'b111111; + 12'd2917 : mem_out_dec = 6'b111111; + 12'd2918 : mem_out_dec = 6'b111111; + 12'd2919 : mem_out_dec = 6'b111111; + 12'd2920 : mem_out_dec = 6'b111111; + 12'd2921 : mem_out_dec = 6'b111111; + 12'd2922 : mem_out_dec = 6'b111111; + 12'd2923 : mem_out_dec = 6'b111111; + 12'd2924 : mem_out_dec = 6'b111111; + 12'd2925 : mem_out_dec = 6'b111111; + 12'd2926 : mem_out_dec = 6'b111111; + 12'd2927 : mem_out_dec = 6'b111111; + 12'd2928 : mem_out_dec = 6'b111111; + 12'd2929 : mem_out_dec = 6'b111111; + 12'd2930 : mem_out_dec = 6'b111111; + 12'd2931 : mem_out_dec = 6'b000100; + 12'd2932 : mem_out_dec = 6'b000100; + 12'd2933 : mem_out_dec = 6'b000101; + 12'd2934 : mem_out_dec = 6'b000101; + 12'd2935 : mem_out_dec = 6'b000110; + 12'd2936 : mem_out_dec = 6'b000110; + 12'd2937 : mem_out_dec = 6'b000111; + 12'd2938 : mem_out_dec = 6'b001000; + 12'd2939 : mem_out_dec = 6'b001000; + 12'd2940 : mem_out_dec = 6'b001001; + 12'd2941 : mem_out_dec = 6'b001010; + 12'd2942 : mem_out_dec = 6'b001011; + 12'd2943 : mem_out_dec = 6'b001011; + 12'd2944 : mem_out_dec = 6'b111111; + 12'd2945 : mem_out_dec = 6'b111111; + 12'd2946 : mem_out_dec = 6'b111111; + 12'd2947 : mem_out_dec = 6'b111111; + 12'd2948 : mem_out_dec = 6'b111111; + 12'd2949 : mem_out_dec = 6'b111111; + 12'd2950 : mem_out_dec = 6'b111111; + 12'd2951 : mem_out_dec = 6'b111111; + 12'd2952 : mem_out_dec = 6'b111111; + 12'd2953 : mem_out_dec = 6'b111111; + 12'd2954 : mem_out_dec = 6'b111111; + 12'd2955 : mem_out_dec = 6'b111111; + 12'd2956 : mem_out_dec = 6'b111111; + 12'd2957 : mem_out_dec = 6'b111111; + 12'd2958 : mem_out_dec = 6'b111111; + 12'd2959 : mem_out_dec = 6'b111111; + 12'd2960 : mem_out_dec = 6'b111111; + 12'd2961 : mem_out_dec = 6'b111111; + 12'd2962 : mem_out_dec = 6'b111111; + 12'd2963 : mem_out_dec = 6'b111111; + 12'd2964 : mem_out_dec = 6'b111111; + 12'd2965 : mem_out_dec = 6'b111111; + 12'd2966 : mem_out_dec = 6'b111111; + 12'd2967 : mem_out_dec = 6'b111111; + 12'd2968 : mem_out_dec = 6'b111111; + 12'd2969 : mem_out_dec = 6'b111111; + 12'd2970 : mem_out_dec = 6'b111111; + 12'd2971 : mem_out_dec = 6'b111111; + 12'd2972 : mem_out_dec = 6'b111111; + 12'd2973 : mem_out_dec = 6'b111111; + 12'd2974 : mem_out_dec = 6'b111111; + 12'd2975 : mem_out_dec = 6'b111111; + 12'd2976 : mem_out_dec = 6'b111111; + 12'd2977 : mem_out_dec = 6'b111111; + 12'd2978 : mem_out_dec = 6'b111111; + 12'd2979 : mem_out_dec = 6'b111111; + 12'd2980 : mem_out_dec = 6'b111111; + 12'd2981 : mem_out_dec = 6'b111111; + 12'd2982 : mem_out_dec = 6'b111111; + 12'd2983 : mem_out_dec = 6'b111111; + 12'd2984 : mem_out_dec = 6'b111111; + 12'd2985 : mem_out_dec = 6'b111111; + 12'd2986 : mem_out_dec = 6'b111111; + 12'd2987 : mem_out_dec = 6'b111111; + 12'd2988 : mem_out_dec = 6'b111111; + 12'd2989 : mem_out_dec = 6'b111111; + 12'd2990 : mem_out_dec = 6'b111111; + 12'd2991 : mem_out_dec = 6'b111111; + 12'd2992 : mem_out_dec = 6'b111111; + 12'd2993 : mem_out_dec = 6'b111111; + 12'd2994 : mem_out_dec = 6'b111111; + 12'd2995 : mem_out_dec = 6'b111111; + 12'd2996 : mem_out_dec = 6'b000100; + 12'd2997 : mem_out_dec = 6'b000101; + 12'd2998 : mem_out_dec = 6'b000101; + 12'd2999 : mem_out_dec = 6'b000110; + 12'd3000 : mem_out_dec = 6'b000110; + 12'd3001 : mem_out_dec = 6'b000111; + 12'd3002 : mem_out_dec = 6'b000111; + 12'd3003 : mem_out_dec = 6'b001000; + 12'd3004 : mem_out_dec = 6'b001001; + 12'd3005 : mem_out_dec = 6'b001010; + 12'd3006 : mem_out_dec = 6'b001010; + 12'd3007 : mem_out_dec = 6'b001011; + 12'd3008 : mem_out_dec = 6'b111111; + 12'd3009 : mem_out_dec = 6'b111111; + 12'd3010 : mem_out_dec = 6'b111111; + 12'd3011 : mem_out_dec = 6'b111111; + 12'd3012 : mem_out_dec = 6'b111111; + 12'd3013 : mem_out_dec = 6'b111111; + 12'd3014 : mem_out_dec = 6'b111111; + 12'd3015 : mem_out_dec = 6'b111111; + 12'd3016 : mem_out_dec = 6'b111111; + 12'd3017 : mem_out_dec = 6'b111111; + 12'd3018 : mem_out_dec = 6'b111111; + 12'd3019 : mem_out_dec = 6'b111111; + 12'd3020 : mem_out_dec = 6'b111111; + 12'd3021 : mem_out_dec = 6'b111111; + 12'd3022 : mem_out_dec = 6'b111111; + 12'd3023 : mem_out_dec = 6'b111111; + 12'd3024 : mem_out_dec = 6'b111111; + 12'd3025 : mem_out_dec = 6'b111111; + 12'd3026 : mem_out_dec = 6'b111111; + 12'd3027 : mem_out_dec = 6'b111111; + 12'd3028 : mem_out_dec = 6'b111111; + 12'd3029 : mem_out_dec = 6'b111111; + 12'd3030 : mem_out_dec = 6'b111111; + 12'd3031 : mem_out_dec = 6'b111111; + 12'd3032 : mem_out_dec = 6'b111111; + 12'd3033 : mem_out_dec = 6'b111111; + 12'd3034 : mem_out_dec = 6'b111111; + 12'd3035 : mem_out_dec = 6'b111111; + 12'd3036 : mem_out_dec = 6'b111111; + 12'd3037 : mem_out_dec = 6'b111111; + 12'd3038 : mem_out_dec = 6'b111111; + 12'd3039 : mem_out_dec = 6'b111111; + 12'd3040 : mem_out_dec = 6'b111111; + 12'd3041 : mem_out_dec = 6'b111111; + 12'd3042 : mem_out_dec = 6'b111111; + 12'd3043 : mem_out_dec = 6'b111111; + 12'd3044 : mem_out_dec = 6'b111111; + 12'd3045 : mem_out_dec = 6'b111111; + 12'd3046 : mem_out_dec = 6'b111111; + 12'd3047 : mem_out_dec = 6'b111111; + 12'd3048 : mem_out_dec = 6'b111111; + 12'd3049 : mem_out_dec = 6'b111111; + 12'd3050 : mem_out_dec = 6'b111111; + 12'd3051 : mem_out_dec = 6'b111111; + 12'd3052 : mem_out_dec = 6'b111111; + 12'd3053 : mem_out_dec = 6'b111111; + 12'd3054 : mem_out_dec = 6'b111111; + 12'd3055 : mem_out_dec = 6'b111111; + 12'd3056 : mem_out_dec = 6'b111111; + 12'd3057 : mem_out_dec = 6'b111111; + 12'd3058 : mem_out_dec = 6'b111111; + 12'd3059 : mem_out_dec = 6'b111111; + 12'd3060 : mem_out_dec = 6'b111111; + 12'd3061 : mem_out_dec = 6'b000100; + 12'd3062 : mem_out_dec = 6'b000101; + 12'd3063 : mem_out_dec = 6'b000110; + 12'd3064 : mem_out_dec = 6'b000110; + 12'd3065 : mem_out_dec = 6'b000111; + 12'd3066 : mem_out_dec = 6'b000111; + 12'd3067 : mem_out_dec = 6'b001000; + 12'd3068 : mem_out_dec = 6'b001001; + 12'd3069 : mem_out_dec = 6'b001001; + 12'd3070 : mem_out_dec = 6'b001010; + 12'd3071 : mem_out_dec = 6'b001011; + 12'd3072 : mem_out_dec = 6'b111111; + 12'd3073 : mem_out_dec = 6'b111111; + 12'd3074 : mem_out_dec = 6'b111111; + 12'd3075 : mem_out_dec = 6'b111111; + 12'd3076 : mem_out_dec = 6'b111111; + 12'd3077 : mem_out_dec = 6'b111111; + 12'd3078 : mem_out_dec = 6'b111111; + 12'd3079 : mem_out_dec = 6'b111111; + 12'd3080 : mem_out_dec = 6'b111111; + 12'd3081 : mem_out_dec = 6'b111111; + 12'd3082 : mem_out_dec = 6'b111111; + 12'd3083 : mem_out_dec = 6'b111111; + 12'd3084 : mem_out_dec = 6'b111111; + 12'd3085 : mem_out_dec = 6'b111111; + 12'd3086 : mem_out_dec = 6'b111111; + 12'd3087 : mem_out_dec = 6'b111111; + 12'd3088 : mem_out_dec = 6'b111111; + 12'd3089 : mem_out_dec = 6'b111111; + 12'd3090 : mem_out_dec = 6'b111111; + 12'd3091 : mem_out_dec = 6'b111111; + 12'd3092 : mem_out_dec = 6'b111111; + 12'd3093 : mem_out_dec = 6'b111111; + 12'd3094 : mem_out_dec = 6'b111111; + 12'd3095 : mem_out_dec = 6'b111111; + 12'd3096 : mem_out_dec = 6'b111111; + 12'd3097 : mem_out_dec = 6'b111111; + 12'd3098 : mem_out_dec = 6'b111111; + 12'd3099 : mem_out_dec = 6'b111111; + 12'd3100 : mem_out_dec = 6'b111111; + 12'd3101 : mem_out_dec = 6'b111111; + 12'd3102 : mem_out_dec = 6'b111111; + 12'd3103 : mem_out_dec = 6'b111111; + 12'd3104 : mem_out_dec = 6'b111111; + 12'd3105 : mem_out_dec = 6'b111111; + 12'd3106 : mem_out_dec = 6'b111111; + 12'd3107 : mem_out_dec = 6'b111111; + 12'd3108 : mem_out_dec = 6'b111111; + 12'd3109 : mem_out_dec = 6'b111111; + 12'd3110 : mem_out_dec = 6'b111111; + 12'd3111 : mem_out_dec = 6'b111111; + 12'd3112 : mem_out_dec = 6'b111111; + 12'd3113 : mem_out_dec = 6'b111111; + 12'd3114 : mem_out_dec = 6'b111111; + 12'd3115 : mem_out_dec = 6'b111111; + 12'd3116 : mem_out_dec = 6'b111111; + 12'd3117 : mem_out_dec = 6'b111111; + 12'd3118 : mem_out_dec = 6'b111111; + 12'd3119 : mem_out_dec = 6'b111111; + 12'd3120 : mem_out_dec = 6'b111111; + 12'd3121 : mem_out_dec = 6'b111111; + 12'd3122 : mem_out_dec = 6'b111111; + 12'd3123 : mem_out_dec = 6'b111111; + 12'd3124 : mem_out_dec = 6'b111111; + 12'd3125 : mem_out_dec = 6'b111111; + 12'd3126 : mem_out_dec = 6'b000100; + 12'd3127 : mem_out_dec = 6'b000101; + 12'd3128 : mem_out_dec = 6'b000101; + 12'd3129 : mem_out_dec = 6'b000110; + 12'd3130 : mem_out_dec = 6'b000110; + 12'd3131 : mem_out_dec = 6'b000111; + 12'd3132 : mem_out_dec = 6'b001000; + 12'd3133 : mem_out_dec = 6'b001000; + 12'd3134 : mem_out_dec = 6'b001001; + 12'd3135 : mem_out_dec = 6'b001010; + 12'd3136 : mem_out_dec = 6'b111111; + 12'd3137 : mem_out_dec = 6'b111111; + 12'd3138 : mem_out_dec = 6'b111111; + 12'd3139 : mem_out_dec = 6'b111111; + 12'd3140 : mem_out_dec = 6'b111111; + 12'd3141 : mem_out_dec = 6'b111111; + 12'd3142 : mem_out_dec = 6'b111111; + 12'd3143 : mem_out_dec = 6'b111111; + 12'd3144 : mem_out_dec = 6'b111111; + 12'd3145 : mem_out_dec = 6'b111111; + 12'd3146 : mem_out_dec = 6'b111111; + 12'd3147 : mem_out_dec = 6'b111111; + 12'd3148 : mem_out_dec = 6'b111111; + 12'd3149 : mem_out_dec = 6'b111111; + 12'd3150 : mem_out_dec = 6'b111111; + 12'd3151 : mem_out_dec = 6'b111111; + 12'd3152 : mem_out_dec = 6'b111111; + 12'd3153 : mem_out_dec = 6'b111111; + 12'd3154 : mem_out_dec = 6'b111111; + 12'd3155 : mem_out_dec = 6'b111111; + 12'd3156 : mem_out_dec = 6'b111111; + 12'd3157 : mem_out_dec = 6'b111111; + 12'd3158 : mem_out_dec = 6'b111111; + 12'd3159 : mem_out_dec = 6'b111111; + 12'd3160 : mem_out_dec = 6'b111111; + 12'd3161 : mem_out_dec = 6'b111111; + 12'd3162 : mem_out_dec = 6'b111111; + 12'd3163 : mem_out_dec = 6'b111111; + 12'd3164 : mem_out_dec = 6'b111111; + 12'd3165 : mem_out_dec = 6'b111111; + 12'd3166 : mem_out_dec = 6'b111111; + 12'd3167 : mem_out_dec = 6'b111111; + 12'd3168 : mem_out_dec = 6'b111111; + 12'd3169 : mem_out_dec = 6'b111111; + 12'd3170 : mem_out_dec = 6'b111111; + 12'd3171 : mem_out_dec = 6'b111111; + 12'd3172 : mem_out_dec = 6'b111111; + 12'd3173 : mem_out_dec = 6'b111111; + 12'd3174 : mem_out_dec = 6'b111111; + 12'd3175 : mem_out_dec = 6'b111111; + 12'd3176 : mem_out_dec = 6'b111111; + 12'd3177 : mem_out_dec = 6'b111111; + 12'd3178 : mem_out_dec = 6'b111111; + 12'd3179 : mem_out_dec = 6'b111111; + 12'd3180 : mem_out_dec = 6'b111111; + 12'd3181 : mem_out_dec = 6'b111111; + 12'd3182 : mem_out_dec = 6'b111111; + 12'd3183 : mem_out_dec = 6'b111111; + 12'd3184 : mem_out_dec = 6'b111111; + 12'd3185 : mem_out_dec = 6'b111111; + 12'd3186 : mem_out_dec = 6'b111111; + 12'd3187 : mem_out_dec = 6'b111111; + 12'd3188 : mem_out_dec = 6'b111111; + 12'd3189 : mem_out_dec = 6'b111111; + 12'd3190 : mem_out_dec = 6'b111111; + 12'd3191 : mem_out_dec = 6'b000100; + 12'd3192 : mem_out_dec = 6'b000100; + 12'd3193 : mem_out_dec = 6'b000101; + 12'd3194 : mem_out_dec = 6'b000110; + 12'd3195 : mem_out_dec = 6'b000110; + 12'd3196 : mem_out_dec = 6'b000111; + 12'd3197 : mem_out_dec = 6'b001000; + 12'd3198 : mem_out_dec = 6'b001000; + 12'd3199 : mem_out_dec = 6'b001001; + 12'd3200 : mem_out_dec = 6'b111111; + 12'd3201 : mem_out_dec = 6'b111111; + 12'd3202 : mem_out_dec = 6'b111111; + 12'd3203 : mem_out_dec = 6'b111111; + 12'd3204 : mem_out_dec = 6'b111111; + 12'd3205 : mem_out_dec = 6'b111111; + 12'd3206 : mem_out_dec = 6'b111111; + 12'd3207 : mem_out_dec = 6'b111111; + 12'd3208 : mem_out_dec = 6'b111111; + 12'd3209 : mem_out_dec = 6'b111111; + 12'd3210 : mem_out_dec = 6'b111111; + 12'd3211 : mem_out_dec = 6'b111111; + 12'd3212 : mem_out_dec = 6'b111111; + 12'd3213 : mem_out_dec = 6'b111111; + 12'd3214 : mem_out_dec = 6'b111111; + 12'd3215 : mem_out_dec = 6'b111111; + 12'd3216 : mem_out_dec = 6'b111111; + 12'd3217 : mem_out_dec = 6'b111111; + 12'd3218 : mem_out_dec = 6'b111111; + 12'd3219 : mem_out_dec = 6'b111111; + 12'd3220 : mem_out_dec = 6'b111111; + 12'd3221 : mem_out_dec = 6'b111111; + 12'd3222 : mem_out_dec = 6'b111111; + 12'd3223 : mem_out_dec = 6'b111111; + 12'd3224 : mem_out_dec = 6'b111111; + 12'd3225 : mem_out_dec = 6'b111111; + 12'd3226 : mem_out_dec = 6'b111111; + 12'd3227 : mem_out_dec = 6'b111111; + 12'd3228 : mem_out_dec = 6'b111111; + 12'd3229 : mem_out_dec = 6'b111111; + 12'd3230 : mem_out_dec = 6'b111111; + 12'd3231 : mem_out_dec = 6'b111111; + 12'd3232 : mem_out_dec = 6'b111111; + 12'd3233 : mem_out_dec = 6'b111111; + 12'd3234 : mem_out_dec = 6'b111111; + 12'd3235 : mem_out_dec = 6'b111111; + 12'd3236 : mem_out_dec = 6'b111111; + 12'd3237 : mem_out_dec = 6'b111111; + 12'd3238 : mem_out_dec = 6'b111111; + 12'd3239 : mem_out_dec = 6'b111111; + 12'd3240 : mem_out_dec = 6'b111111; + 12'd3241 : mem_out_dec = 6'b111111; + 12'd3242 : mem_out_dec = 6'b111111; + 12'd3243 : mem_out_dec = 6'b111111; + 12'd3244 : mem_out_dec = 6'b111111; + 12'd3245 : mem_out_dec = 6'b111111; + 12'd3246 : mem_out_dec = 6'b111111; + 12'd3247 : mem_out_dec = 6'b111111; + 12'd3248 : mem_out_dec = 6'b111111; + 12'd3249 : mem_out_dec = 6'b111111; + 12'd3250 : mem_out_dec = 6'b111111; + 12'd3251 : mem_out_dec = 6'b111111; + 12'd3252 : mem_out_dec = 6'b111111; + 12'd3253 : mem_out_dec = 6'b111111; + 12'd3254 : mem_out_dec = 6'b111111; + 12'd3255 : mem_out_dec = 6'b111111; + 12'd3256 : mem_out_dec = 6'b000100; + 12'd3257 : mem_out_dec = 6'b000100; + 12'd3258 : mem_out_dec = 6'b000101; + 12'd3259 : mem_out_dec = 6'b000110; + 12'd3260 : mem_out_dec = 6'b000110; + 12'd3261 : mem_out_dec = 6'b000111; + 12'd3262 : mem_out_dec = 6'b001000; + 12'd3263 : mem_out_dec = 6'b001001; + 12'd3264 : mem_out_dec = 6'b111111; + 12'd3265 : mem_out_dec = 6'b111111; + 12'd3266 : mem_out_dec = 6'b111111; + 12'd3267 : mem_out_dec = 6'b111111; + 12'd3268 : mem_out_dec = 6'b111111; + 12'd3269 : mem_out_dec = 6'b111111; + 12'd3270 : mem_out_dec = 6'b111111; + 12'd3271 : mem_out_dec = 6'b111111; + 12'd3272 : mem_out_dec = 6'b111111; + 12'd3273 : mem_out_dec = 6'b111111; + 12'd3274 : mem_out_dec = 6'b111111; + 12'd3275 : mem_out_dec = 6'b111111; + 12'd3276 : mem_out_dec = 6'b111111; + 12'd3277 : mem_out_dec = 6'b111111; + 12'd3278 : mem_out_dec = 6'b111111; + 12'd3279 : mem_out_dec = 6'b111111; + 12'd3280 : mem_out_dec = 6'b111111; + 12'd3281 : mem_out_dec = 6'b111111; + 12'd3282 : mem_out_dec = 6'b111111; + 12'd3283 : mem_out_dec = 6'b111111; + 12'd3284 : mem_out_dec = 6'b111111; + 12'd3285 : mem_out_dec = 6'b111111; + 12'd3286 : mem_out_dec = 6'b111111; + 12'd3287 : mem_out_dec = 6'b111111; + 12'd3288 : mem_out_dec = 6'b111111; + 12'd3289 : mem_out_dec = 6'b111111; + 12'd3290 : mem_out_dec = 6'b111111; + 12'd3291 : mem_out_dec = 6'b111111; + 12'd3292 : mem_out_dec = 6'b111111; + 12'd3293 : mem_out_dec = 6'b111111; + 12'd3294 : mem_out_dec = 6'b111111; + 12'd3295 : mem_out_dec = 6'b111111; + 12'd3296 : mem_out_dec = 6'b111111; + 12'd3297 : mem_out_dec = 6'b111111; + 12'd3298 : mem_out_dec = 6'b111111; + 12'd3299 : mem_out_dec = 6'b111111; + 12'd3300 : mem_out_dec = 6'b111111; + 12'd3301 : mem_out_dec = 6'b111111; + 12'd3302 : mem_out_dec = 6'b111111; + 12'd3303 : mem_out_dec = 6'b111111; + 12'd3304 : mem_out_dec = 6'b111111; + 12'd3305 : mem_out_dec = 6'b111111; + 12'd3306 : mem_out_dec = 6'b111111; + 12'd3307 : mem_out_dec = 6'b111111; + 12'd3308 : mem_out_dec = 6'b111111; + 12'd3309 : mem_out_dec = 6'b111111; + 12'd3310 : mem_out_dec = 6'b111111; + 12'd3311 : mem_out_dec = 6'b111111; + 12'd3312 : mem_out_dec = 6'b111111; + 12'd3313 : mem_out_dec = 6'b111111; + 12'd3314 : mem_out_dec = 6'b111111; + 12'd3315 : mem_out_dec = 6'b111111; + 12'd3316 : mem_out_dec = 6'b111111; + 12'd3317 : mem_out_dec = 6'b111111; + 12'd3318 : mem_out_dec = 6'b111111; + 12'd3319 : mem_out_dec = 6'b111111; + 12'd3320 : mem_out_dec = 6'b111111; + 12'd3321 : mem_out_dec = 6'b000100; + 12'd3322 : mem_out_dec = 6'b000100; + 12'd3323 : mem_out_dec = 6'b000101; + 12'd3324 : mem_out_dec = 6'b000110; + 12'd3325 : mem_out_dec = 6'b000111; + 12'd3326 : mem_out_dec = 6'b001000; + 12'd3327 : mem_out_dec = 6'b001000; + 12'd3328 : mem_out_dec = 6'b111111; + 12'd3329 : mem_out_dec = 6'b111111; + 12'd3330 : mem_out_dec = 6'b111111; + 12'd3331 : mem_out_dec = 6'b111111; + 12'd3332 : mem_out_dec = 6'b111111; + 12'd3333 : mem_out_dec = 6'b111111; + 12'd3334 : mem_out_dec = 6'b111111; + 12'd3335 : mem_out_dec = 6'b111111; + 12'd3336 : mem_out_dec = 6'b111111; + 12'd3337 : mem_out_dec = 6'b111111; + 12'd3338 : mem_out_dec = 6'b111111; + 12'd3339 : mem_out_dec = 6'b111111; + 12'd3340 : mem_out_dec = 6'b111111; + 12'd3341 : mem_out_dec = 6'b111111; + 12'd3342 : mem_out_dec = 6'b111111; + 12'd3343 : mem_out_dec = 6'b111111; + 12'd3344 : mem_out_dec = 6'b111111; + 12'd3345 : mem_out_dec = 6'b111111; + 12'd3346 : mem_out_dec = 6'b111111; + 12'd3347 : mem_out_dec = 6'b111111; + 12'd3348 : mem_out_dec = 6'b111111; + 12'd3349 : mem_out_dec = 6'b111111; + 12'd3350 : mem_out_dec = 6'b111111; + 12'd3351 : mem_out_dec = 6'b111111; + 12'd3352 : mem_out_dec = 6'b111111; + 12'd3353 : mem_out_dec = 6'b111111; + 12'd3354 : mem_out_dec = 6'b111111; + 12'd3355 : mem_out_dec = 6'b111111; + 12'd3356 : mem_out_dec = 6'b111111; + 12'd3357 : mem_out_dec = 6'b111111; + 12'd3358 : mem_out_dec = 6'b111111; + 12'd3359 : mem_out_dec = 6'b111111; + 12'd3360 : mem_out_dec = 6'b111111; + 12'd3361 : mem_out_dec = 6'b111111; + 12'd3362 : mem_out_dec = 6'b111111; + 12'd3363 : mem_out_dec = 6'b111111; + 12'd3364 : mem_out_dec = 6'b111111; + 12'd3365 : mem_out_dec = 6'b111111; + 12'd3366 : mem_out_dec = 6'b111111; + 12'd3367 : mem_out_dec = 6'b111111; + 12'd3368 : mem_out_dec = 6'b111111; + 12'd3369 : mem_out_dec = 6'b111111; + 12'd3370 : mem_out_dec = 6'b111111; + 12'd3371 : mem_out_dec = 6'b111111; + 12'd3372 : mem_out_dec = 6'b111111; + 12'd3373 : mem_out_dec = 6'b111111; + 12'd3374 : mem_out_dec = 6'b111111; + 12'd3375 : mem_out_dec = 6'b111111; + 12'd3376 : mem_out_dec = 6'b111111; + 12'd3377 : mem_out_dec = 6'b111111; + 12'd3378 : mem_out_dec = 6'b111111; + 12'd3379 : mem_out_dec = 6'b111111; + 12'd3380 : mem_out_dec = 6'b111111; + 12'd3381 : mem_out_dec = 6'b111111; + 12'd3382 : mem_out_dec = 6'b111111; + 12'd3383 : mem_out_dec = 6'b111111; + 12'd3384 : mem_out_dec = 6'b111111; + 12'd3385 : mem_out_dec = 6'b111111; + 12'd3386 : mem_out_dec = 6'b000100; + 12'd3387 : mem_out_dec = 6'b000101; + 12'd3388 : mem_out_dec = 6'b000110; + 12'd3389 : mem_out_dec = 6'b000110; + 12'd3390 : mem_out_dec = 6'b000111; + 12'd3391 : mem_out_dec = 6'b001000; + 12'd3392 : mem_out_dec = 6'b111111; + 12'd3393 : mem_out_dec = 6'b111111; + 12'd3394 : mem_out_dec = 6'b111111; + 12'd3395 : mem_out_dec = 6'b111111; + 12'd3396 : mem_out_dec = 6'b111111; + 12'd3397 : mem_out_dec = 6'b111111; + 12'd3398 : mem_out_dec = 6'b111111; + 12'd3399 : mem_out_dec = 6'b111111; + 12'd3400 : mem_out_dec = 6'b111111; + 12'd3401 : mem_out_dec = 6'b111111; + 12'd3402 : mem_out_dec = 6'b111111; + 12'd3403 : mem_out_dec = 6'b111111; + 12'd3404 : mem_out_dec = 6'b111111; + 12'd3405 : mem_out_dec = 6'b111111; + 12'd3406 : mem_out_dec = 6'b111111; + 12'd3407 : mem_out_dec = 6'b111111; + 12'd3408 : mem_out_dec = 6'b111111; + 12'd3409 : mem_out_dec = 6'b111111; + 12'd3410 : mem_out_dec = 6'b111111; + 12'd3411 : mem_out_dec = 6'b111111; + 12'd3412 : mem_out_dec = 6'b111111; + 12'd3413 : mem_out_dec = 6'b111111; + 12'd3414 : mem_out_dec = 6'b111111; + 12'd3415 : mem_out_dec = 6'b111111; + 12'd3416 : mem_out_dec = 6'b111111; + 12'd3417 : mem_out_dec = 6'b111111; + 12'd3418 : mem_out_dec = 6'b111111; + 12'd3419 : mem_out_dec = 6'b111111; + 12'd3420 : mem_out_dec = 6'b111111; + 12'd3421 : mem_out_dec = 6'b111111; + 12'd3422 : mem_out_dec = 6'b111111; + 12'd3423 : mem_out_dec = 6'b111111; + 12'd3424 : mem_out_dec = 6'b111111; + 12'd3425 : mem_out_dec = 6'b111111; + 12'd3426 : mem_out_dec = 6'b111111; + 12'd3427 : mem_out_dec = 6'b111111; + 12'd3428 : mem_out_dec = 6'b111111; + 12'd3429 : mem_out_dec = 6'b111111; + 12'd3430 : mem_out_dec = 6'b111111; + 12'd3431 : mem_out_dec = 6'b111111; + 12'd3432 : mem_out_dec = 6'b111111; + 12'd3433 : mem_out_dec = 6'b111111; + 12'd3434 : mem_out_dec = 6'b111111; + 12'd3435 : mem_out_dec = 6'b111111; + 12'd3436 : mem_out_dec = 6'b111111; + 12'd3437 : mem_out_dec = 6'b111111; + 12'd3438 : mem_out_dec = 6'b111111; + 12'd3439 : mem_out_dec = 6'b111111; + 12'd3440 : mem_out_dec = 6'b111111; + 12'd3441 : mem_out_dec = 6'b111111; + 12'd3442 : mem_out_dec = 6'b111111; + 12'd3443 : mem_out_dec = 6'b111111; + 12'd3444 : mem_out_dec = 6'b111111; + 12'd3445 : mem_out_dec = 6'b111111; + 12'd3446 : mem_out_dec = 6'b111111; + 12'd3447 : mem_out_dec = 6'b111111; + 12'd3448 : mem_out_dec = 6'b111111; + 12'd3449 : mem_out_dec = 6'b111111; + 12'd3450 : mem_out_dec = 6'b111111; + 12'd3451 : mem_out_dec = 6'b000100; + 12'd3452 : mem_out_dec = 6'b000101; + 12'd3453 : mem_out_dec = 6'b000110; + 12'd3454 : mem_out_dec = 6'b000111; + 12'd3455 : mem_out_dec = 6'b001000; + 12'd3456 : mem_out_dec = 6'b111111; + 12'd3457 : mem_out_dec = 6'b111111; + 12'd3458 : mem_out_dec = 6'b111111; + 12'd3459 : mem_out_dec = 6'b111111; + 12'd3460 : mem_out_dec = 6'b111111; + 12'd3461 : mem_out_dec = 6'b111111; + 12'd3462 : mem_out_dec = 6'b111111; + 12'd3463 : mem_out_dec = 6'b111111; + 12'd3464 : mem_out_dec = 6'b111111; + 12'd3465 : mem_out_dec = 6'b111111; + 12'd3466 : mem_out_dec = 6'b111111; + 12'd3467 : mem_out_dec = 6'b111111; + 12'd3468 : mem_out_dec = 6'b111111; + 12'd3469 : mem_out_dec = 6'b111111; + 12'd3470 : mem_out_dec = 6'b111111; + 12'd3471 : mem_out_dec = 6'b111111; + 12'd3472 : mem_out_dec = 6'b111111; + 12'd3473 : mem_out_dec = 6'b111111; + 12'd3474 : mem_out_dec = 6'b111111; + 12'd3475 : mem_out_dec = 6'b111111; + 12'd3476 : mem_out_dec = 6'b111111; + 12'd3477 : mem_out_dec = 6'b111111; + 12'd3478 : mem_out_dec = 6'b111111; + 12'd3479 : mem_out_dec = 6'b111111; + 12'd3480 : mem_out_dec = 6'b111111; + 12'd3481 : mem_out_dec = 6'b111111; + 12'd3482 : mem_out_dec = 6'b111111; + 12'd3483 : mem_out_dec = 6'b111111; + 12'd3484 : mem_out_dec = 6'b111111; + 12'd3485 : mem_out_dec = 6'b111111; + 12'd3486 : mem_out_dec = 6'b111111; + 12'd3487 : mem_out_dec = 6'b111111; + 12'd3488 : mem_out_dec = 6'b111111; + 12'd3489 : mem_out_dec = 6'b111111; + 12'd3490 : mem_out_dec = 6'b111111; + 12'd3491 : mem_out_dec = 6'b111111; + 12'd3492 : mem_out_dec = 6'b111111; + 12'd3493 : mem_out_dec = 6'b111111; + 12'd3494 : mem_out_dec = 6'b111111; + 12'd3495 : mem_out_dec = 6'b111111; + 12'd3496 : mem_out_dec = 6'b111111; + 12'd3497 : mem_out_dec = 6'b111111; + 12'd3498 : mem_out_dec = 6'b111111; + 12'd3499 : mem_out_dec = 6'b111111; + 12'd3500 : mem_out_dec = 6'b111111; + 12'd3501 : mem_out_dec = 6'b111111; + 12'd3502 : mem_out_dec = 6'b111111; + 12'd3503 : mem_out_dec = 6'b111111; + 12'd3504 : mem_out_dec = 6'b111111; + 12'd3505 : mem_out_dec = 6'b111111; + 12'd3506 : mem_out_dec = 6'b111111; + 12'd3507 : mem_out_dec = 6'b111111; + 12'd3508 : mem_out_dec = 6'b111111; + 12'd3509 : mem_out_dec = 6'b111111; + 12'd3510 : mem_out_dec = 6'b111111; + 12'd3511 : mem_out_dec = 6'b111111; + 12'd3512 : mem_out_dec = 6'b111111; + 12'd3513 : mem_out_dec = 6'b111111; + 12'd3514 : mem_out_dec = 6'b111111; + 12'd3515 : mem_out_dec = 6'b111111; + 12'd3516 : mem_out_dec = 6'b000101; + 12'd3517 : mem_out_dec = 6'b000110; + 12'd3518 : mem_out_dec = 6'b000110; + 12'd3519 : mem_out_dec = 6'b000111; + 12'd3520 : mem_out_dec = 6'b111111; + 12'd3521 : mem_out_dec = 6'b111111; + 12'd3522 : mem_out_dec = 6'b111111; + 12'd3523 : mem_out_dec = 6'b111111; + 12'd3524 : mem_out_dec = 6'b111111; + 12'd3525 : mem_out_dec = 6'b111111; + 12'd3526 : mem_out_dec = 6'b111111; + 12'd3527 : mem_out_dec = 6'b111111; + 12'd3528 : mem_out_dec = 6'b111111; + 12'd3529 : mem_out_dec = 6'b111111; + 12'd3530 : mem_out_dec = 6'b111111; + 12'd3531 : mem_out_dec = 6'b111111; + 12'd3532 : mem_out_dec = 6'b111111; + 12'd3533 : mem_out_dec = 6'b111111; + 12'd3534 : mem_out_dec = 6'b111111; + 12'd3535 : mem_out_dec = 6'b111111; + 12'd3536 : mem_out_dec = 6'b111111; + 12'd3537 : mem_out_dec = 6'b111111; + 12'd3538 : mem_out_dec = 6'b111111; + 12'd3539 : mem_out_dec = 6'b111111; + 12'd3540 : mem_out_dec = 6'b111111; + 12'd3541 : mem_out_dec = 6'b111111; + 12'd3542 : mem_out_dec = 6'b111111; + 12'd3543 : mem_out_dec = 6'b111111; + 12'd3544 : mem_out_dec = 6'b111111; + 12'd3545 : mem_out_dec = 6'b111111; + 12'd3546 : mem_out_dec = 6'b111111; + 12'd3547 : mem_out_dec = 6'b111111; + 12'd3548 : mem_out_dec = 6'b111111; + 12'd3549 : mem_out_dec = 6'b111111; + 12'd3550 : mem_out_dec = 6'b111111; + 12'd3551 : mem_out_dec = 6'b111111; + 12'd3552 : mem_out_dec = 6'b111111; + 12'd3553 : mem_out_dec = 6'b111111; + 12'd3554 : mem_out_dec = 6'b111111; + 12'd3555 : mem_out_dec = 6'b111111; + 12'd3556 : mem_out_dec = 6'b111111; + 12'd3557 : mem_out_dec = 6'b111111; + 12'd3558 : mem_out_dec = 6'b111111; + 12'd3559 : mem_out_dec = 6'b111111; + 12'd3560 : mem_out_dec = 6'b111111; + 12'd3561 : mem_out_dec = 6'b111111; + 12'd3562 : mem_out_dec = 6'b111111; + 12'd3563 : mem_out_dec = 6'b111111; + 12'd3564 : mem_out_dec = 6'b111111; + 12'd3565 : mem_out_dec = 6'b111111; + 12'd3566 : mem_out_dec = 6'b111111; + 12'd3567 : mem_out_dec = 6'b111111; + 12'd3568 : mem_out_dec = 6'b111111; + 12'd3569 : mem_out_dec = 6'b111111; + 12'd3570 : mem_out_dec = 6'b111111; + 12'd3571 : mem_out_dec = 6'b111111; + 12'd3572 : mem_out_dec = 6'b111111; + 12'd3573 : mem_out_dec = 6'b111111; + 12'd3574 : mem_out_dec = 6'b111111; + 12'd3575 : mem_out_dec = 6'b111111; + 12'd3576 : mem_out_dec = 6'b111111; + 12'd3577 : mem_out_dec = 6'b111111; + 12'd3578 : mem_out_dec = 6'b111111; + 12'd3579 : mem_out_dec = 6'b111111; + 12'd3580 : mem_out_dec = 6'b111111; + 12'd3581 : mem_out_dec = 6'b000101; + 12'd3582 : mem_out_dec = 6'b000110; + 12'd3583 : mem_out_dec = 6'b000110; + 12'd3584 : mem_out_dec = 6'b111111; + 12'd3585 : mem_out_dec = 6'b111111; + 12'd3586 : mem_out_dec = 6'b111111; + 12'd3587 : mem_out_dec = 6'b111111; + 12'd3588 : mem_out_dec = 6'b111111; + 12'd3589 : mem_out_dec = 6'b111111; + 12'd3590 : mem_out_dec = 6'b111111; + 12'd3591 : mem_out_dec = 6'b111111; + 12'd3592 : mem_out_dec = 6'b111111; + 12'd3593 : mem_out_dec = 6'b111111; + 12'd3594 : mem_out_dec = 6'b111111; + 12'd3595 : mem_out_dec = 6'b111111; + 12'd3596 : mem_out_dec = 6'b111111; + 12'd3597 : mem_out_dec = 6'b111111; + 12'd3598 : mem_out_dec = 6'b111111; + 12'd3599 : mem_out_dec = 6'b111111; + 12'd3600 : mem_out_dec = 6'b111111; + 12'd3601 : mem_out_dec = 6'b111111; + 12'd3602 : mem_out_dec = 6'b111111; + 12'd3603 : mem_out_dec = 6'b111111; + 12'd3604 : mem_out_dec = 6'b111111; + 12'd3605 : mem_out_dec = 6'b111111; + 12'd3606 : mem_out_dec = 6'b111111; + 12'd3607 : mem_out_dec = 6'b111111; + 12'd3608 : mem_out_dec = 6'b111111; + 12'd3609 : mem_out_dec = 6'b111111; + 12'd3610 : mem_out_dec = 6'b111111; + 12'd3611 : mem_out_dec = 6'b111111; + 12'd3612 : mem_out_dec = 6'b111111; + 12'd3613 : mem_out_dec = 6'b111111; + 12'd3614 : mem_out_dec = 6'b111111; + 12'd3615 : mem_out_dec = 6'b111111; + 12'd3616 : mem_out_dec = 6'b111111; + 12'd3617 : mem_out_dec = 6'b111111; + 12'd3618 : mem_out_dec = 6'b111111; + 12'd3619 : mem_out_dec = 6'b111111; + 12'd3620 : mem_out_dec = 6'b111111; + 12'd3621 : mem_out_dec = 6'b111111; + 12'd3622 : mem_out_dec = 6'b111111; + 12'd3623 : mem_out_dec = 6'b111111; + 12'd3624 : mem_out_dec = 6'b111111; + 12'd3625 : mem_out_dec = 6'b111111; + 12'd3626 : mem_out_dec = 6'b111111; + 12'd3627 : mem_out_dec = 6'b111111; + 12'd3628 : mem_out_dec = 6'b111111; + 12'd3629 : mem_out_dec = 6'b111111; + 12'd3630 : mem_out_dec = 6'b111111; + 12'd3631 : mem_out_dec = 6'b111111; + 12'd3632 : mem_out_dec = 6'b111111; + 12'd3633 : mem_out_dec = 6'b111111; + 12'd3634 : mem_out_dec = 6'b111111; + 12'd3635 : mem_out_dec = 6'b111111; + 12'd3636 : mem_out_dec = 6'b111111; + 12'd3637 : mem_out_dec = 6'b111111; + 12'd3638 : mem_out_dec = 6'b111111; + 12'd3639 : mem_out_dec = 6'b111111; + 12'd3640 : mem_out_dec = 6'b111111; + 12'd3641 : mem_out_dec = 6'b111111; + 12'd3642 : mem_out_dec = 6'b111111; + 12'd3643 : mem_out_dec = 6'b111111; + 12'd3644 : mem_out_dec = 6'b111111; + 12'd3645 : mem_out_dec = 6'b111111; + 12'd3646 : mem_out_dec = 6'b000100; + 12'd3647 : mem_out_dec = 6'b000101; + 12'd3648 : mem_out_dec = 6'b111111; + 12'd3649 : mem_out_dec = 6'b111111; + 12'd3650 : mem_out_dec = 6'b111111; + 12'd3651 : mem_out_dec = 6'b111111; + 12'd3652 : mem_out_dec = 6'b111111; + 12'd3653 : mem_out_dec = 6'b111111; + 12'd3654 : mem_out_dec = 6'b111111; + 12'd3655 : mem_out_dec = 6'b111111; + 12'd3656 : mem_out_dec = 6'b111111; + 12'd3657 : mem_out_dec = 6'b111111; + 12'd3658 : mem_out_dec = 6'b111111; + 12'd3659 : mem_out_dec = 6'b111111; + 12'd3660 : mem_out_dec = 6'b111111; + 12'd3661 : mem_out_dec = 6'b111111; + 12'd3662 : mem_out_dec = 6'b111111; + 12'd3663 : mem_out_dec = 6'b111111; + 12'd3664 : mem_out_dec = 6'b111111; + 12'd3665 : mem_out_dec = 6'b111111; + 12'd3666 : mem_out_dec = 6'b111111; + 12'd3667 : mem_out_dec = 6'b111111; + 12'd3668 : mem_out_dec = 6'b111111; + 12'd3669 : mem_out_dec = 6'b111111; + 12'd3670 : mem_out_dec = 6'b111111; + 12'd3671 : mem_out_dec = 6'b111111; + 12'd3672 : mem_out_dec = 6'b111111; + 12'd3673 : mem_out_dec = 6'b111111; + 12'd3674 : mem_out_dec = 6'b111111; + 12'd3675 : mem_out_dec = 6'b111111; + 12'd3676 : mem_out_dec = 6'b111111; + 12'd3677 : mem_out_dec = 6'b111111; + 12'd3678 : mem_out_dec = 6'b111111; + 12'd3679 : mem_out_dec = 6'b111111; + 12'd3680 : mem_out_dec = 6'b111111; + 12'd3681 : mem_out_dec = 6'b111111; + 12'd3682 : mem_out_dec = 6'b111111; + 12'd3683 : mem_out_dec = 6'b111111; + 12'd3684 : mem_out_dec = 6'b111111; + 12'd3685 : mem_out_dec = 6'b111111; + 12'd3686 : mem_out_dec = 6'b111111; + 12'd3687 : mem_out_dec = 6'b111111; + 12'd3688 : mem_out_dec = 6'b111111; + 12'd3689 : mem_out_dec = 6'b111111; + 12'd3690 : mem_out_dec = 6'b111111; + 12'd3691 : mem_out_dec = 6'b111111; + 12'd3692 : mem_out_dec = 6'b111111; + 12'd3693 : mem_out_dec = 6'b111111; + 12'd3694 : mem_out_dec = 6'b111111; + 12'd3695 : mem_out_dec = 6'b111111; + 12'd3696 : mem_out_dec = 6'b111111; + 12'd3697 : mem_out_dec = 6'b111111; + 12'd3698 : mem_out_dec = 6'b111111; + 12'd3699 : mem_out_dec = 6'b111111; + 12'd3700 : mem_out_dec = 6'b111111; + 12'd3701 : mem_out_dec = 6'b111111; + 12'd3702 : mem_out_dec = 6'b111111; + 12'd3703 : mem_out_dec = 6'b111111; + 12'd3704 : mem_out_dec = 6'b111111; + 12'd3705 : mem_out_dec = 6'b111111; + 12'd3706 : mem_out_dec = 6'b111111; + 12'd3707 : mem_out_dec = 6'b111111; + 12'd3708 : mem_out_dec = 6'b111111; + 12'd3709 : mem_out_dec = 6'b111111; + 12'd3710 : mem_out_dec = 6'b111111; + 12'd3711 : mem_out_dec = 6'b000100; + 12'd3712 : mem_out_dec = 6'b111111; + 12'd3713 : mem_out_dec = 6'b111111; + 12'd3714 : mem_out_dec = 6'b111111; + 12'd3715 : mem_out_dec = 6'b111111; + 12'd3716 : mem_out_dec = 6'b111111; + 12'd3717 : mem_out_dec = 6'b111111; + 12'd3718 : mem_out_dec = 6'b111111; + 12'd3719 : mem_out_dec = 6'b111111; + 12'd3720 : mem_out_dec = 6'b111111; + 12'd3721 : mem_out_dec = 6'b111111; + 12'd3722 : mem_out_dec = 6'b111111; + 12'd3723 : mem_out_dec = 6'b111111; + 12'd3724 : mem_out_dec = 6'b111111; + 12'd3725 : mem_out_dec = 6'b111111; + 12'd3726 : mem_out_dec = 6'b111111; + 12'd3727 : mem_out_dec = 6'b111111; + 12'd3728 : mem_out_dec = 6'b111111; + 12'd3729 : mem_out_dec = 6'b111111; + 12'd3730 : mem_out_dec = 6'b111111; + 12'd3731 : mem_out_dec = 6'b111111; + 12'd3732 : mem_out_dec = 6'b111111; + 12'd3733 : mem_out_dec = 6'b111111; + 12'd3734 : mem_out_dec = 6'b111111; + 12'd3735 : mem_out_dec = 6'b111111; + 12'd3736 : mem_out_dec = 6'b111111; + 12'd3737 : mem_out_dec = 6'b111111; + 12'd3738 : mem_out_dec = 6'b111111; + 12'd3739 : mem_out_dec = 6'b111111; + 12'd3740 : mem_out_dec = 6'b111111; + 12'd3741 : mem_out_dec = 6'b111111; + 12'd3742 : mem_out_dec = 6'b111111; + 12'd3743 : mem_out_dec = 6'b111111; + 12'd3744 : mem_out_dec = 6'b111111; + 12'd3745 : mem_out_dec = 6'b111111; + 12'd3746 : mem_out_dec = 6'b111111; + 12'd3747 : mem_out_dec = 6'b111111; + 12'd3748 : mem_out_dec = 6'b111111; + 12'd3749 : mem_out_dec = 6'b111111; + 12'd3750 : mem_out_dec = 6'b111111; + 12'd3751 : mem_out_dec = 6'b111111; + 12'd3752 : mem_out_dec = 6'b111111; + 12'd3753 : mem_out_dec = 6'b111111; + 12'd3754 : mem_out_dec = 6'b111111; + 12'd3755 : mem_out_dec = 6'b111111; + 12'd3756 : mem_out_dec = 6'b111111; + 12'd3757 : mem_out_dec = 6'b111111; + 12'd3758 : mem_out_dec = 6'b111111; + 12'd3759 : mem_out_dec = 6'b111111; + 12'd3760 : mem_out_dec = 6'b111111; + 12'd3761 : mem_out_dec = 6'b111111; + 12'd3762 : mem_out_dec = 6'b111111; + 12'd3763 : mem_out_dec = 6'b111111; + 12'd3764 : mem_out_dec = 6'b111111; + 12'd3765 : mem_out_dec = 6'b111111; + 12'd3766 : mem_out_dec = 6'b111111; + 12'd3767 : mem_out_dec = 6'b111111; + 12'd3768 : mem_out_dec = 6'b111111; + 12'd3769 : mem_out_dec = 6'b111111; + 12'd3770 : mem_out_dec = 6'b111111; + 12'd3771 : mem_out_dec = 6'b111111; + 12'd3772 : mem_out_dec = 6'b111111; + 12'd3773 : mem_out_dec = 6'b111111; + 12'd3774 : mem_out_dec = 6'b111111; + 12'd3775 : mem_out_dec = 6'b111111; + 12'd3776 : mem_out_dec = 6'b111111; + 12'd3777 : mem_out_dec = 6'b111111; + 12'd3778 : mem_out_dec = 6'b111111; + 12'd3779 : mem_out_dec = 6'b111111; + 12'd3780 : mem_out_dec = 6'b111111; + 12'd3781 : mem_out_dec = 6'b111111; + 12'd3782 : mem_out_dec = 6'b111111; + 12'd3783 : mem_out_dec = 6'b111111; + 12'd3784 : mem_out_dec = 6'b111111; + 12'd3785 : mem_out_dec = 6'b111111; + 12'd3786 : mem_out_dec = 6'b111111; + 12'd3787 : mem_out_dec = 6'b111111; + 12'd3788 : mem_out_dec = 6'b111111; + 12'd3789 : mem_out_dec = 6'b111111; + 12'd3790 : mem_out_dec = 6'b111111; + 12'd3791 : mem_out_dec = 6'b111111; + 12'd3792 : mem_out_dec = 6'b111111; + 12'd3793 : mem_out_dec = 6'b111111; + 12'd3794 : mem_out_dec = 6'b111111; + 12'd3795 : mem_out_dec = 6'b111111; + 12'd3796 : mem_out_dec = 6'b111111; + 12'd3797 : mem_out_dec = 6'b111111; + 12'd3798 : mem_out_dec = 6'b111111; + 12'd3799 : mem_out_dec = 6'b111111; + 12'd3800 : mem_out_dec = 6'b111111; + 12'd3801 : mem_out_dec = 6'b111111; + 12'd3802 : mem_out_dec = 6'b111111; + 12'd3803 : mem_out_dec = 6'b111111; + 12'd3804 : mem_out_dec = 6'b111111; + 12'd3805 : mem_out_dec = 6'b111111; + 12'd3806 : mem_out_dec = 6'b111111; + 12'd3807 : mem_out_dec = 6'b111111; + 12'd3808 : mem_out_dec = 6'b111111; + 12'd3809 : mem_out_dec = 6'b111111; + 12'd3810 : mem_out_dec = 6'b111111; + 12'd3811 : mem_out_dec = 6'b111111; + 12'd3812 : mem_out_dec = 6'b111111; + 12'd3813 : mem_out_dec = 6'b111111; + 12'd3814 : mem_out_dec = 6'b111111; + 12'd3815 : mem_out_dec = 6'b111111; + 12'd3816 : mem_out_dec = 6'b111111; + 12'd3817 : mem_out_dec = 6'b111111; + 12'd3818 : mem_out_dec = 6'b111111; + 12'd3819 : mem_out_dec = 6'b111111; + 12'd3820 : mem_out_dec = 6'b111111; + 12'd3821 : mem_out_dec = 6'b111111; + 12'd3822 : mem_out_dec = 6'b111111; + 12'd3823 : mem_out_dec = 6'b111111; + 12'd3824 : mem_out_dec = 6'b111111; + 12'd3825 : mem_out_dec = 6'b111111; + 12'd3826 : mem_out_dec = 6'b111111; + 12'd3827 : mem_out_dec = 6'b111111; + 12'd3828 : mem_out_dec = 6'b111111; + 12'd3829 : mem_out_dec = 6'b111111; + 12'd3830 : mem_out_dec = 6'b111111; + 12'd3831 : mem_out_dec = 6'b111111; + 12'd3832 : mem_out_dec = 6'b111111; + 12'd3833 : mem_out_dec = 6'b111111; + 12'd3834 : mem_out_dec = 6'b111111; + 12'd3835 : mem_out_dec = 6'b111111; + 12'd3836 : mem_out_dec = 6'b111111; + 12'd3837 : mem_out_dec = 6'b111111; + 12'd3838 : mem_out_dec = 6'b111111; + 12'd3839 : mem_out_dec = 6'b111111; + 12'd3840 : mem_out_dec = 6'b111111; + 12'd3841 : mem_out_dec = 6'b111111; + 12'd3842 : mem_out_dec = 6'b111111; + 12'd3843 : mem_out_dec = 6'b111111; + 12'd3844 : mem_out_dec = 6'b111111; + 12'd3845 : mem_out_dec = 6'b111111; + 12'd3846 : mem_out_dec = 6'b111111; + 12'd3847 : mem_out_dec = 6'b111111; + 12'd3848 : mem_out_dec = 6'b111111; + 12'd3849 : mem_out_dec = 6'b111111; + 12'd3850 : mem_out_dec = 6'b111111; + 12'd3851 : mem_out_dec = 6'b111111; + 12'd3852 : mem_out_dec = 6'b111111; + 12'd3853 : mem_out_dec = 6'b111111; + 12'd3854 : mem_out_dec = 6'b111111; + 12'd3855 : mem_out_dec = 6'b111111; + 12'd3856 : mem_out_dec = 6'b111111; + 12'd3857 : mem_out_dec = 6'b111111; + 12'd3858 : mem_out_dec = 6'b111111; + 12'd3859 : mem_out_dec = 6'b111111; + 12'd3860 : mem_out_dec = 6'b111111; + 12'd3861 : mem_out_dec = 6'b111111; + 12'd3862 : mem_out_dec = 6'b111111; + 12'd3863 : mem_out_dec = 6'b111111; + 12'd3864 : mem_out_dec = 6'b111111; + 12'd3865 : mem_out_dec = 6'b111111; + 12'd3866 : mem_out_dec = 6'b111111; + 12'd3867 : mem_out_dec = 6'b111111; + 12'd3868 : mem_out_dec = 6'b111111; + 12'd3869 : mem_out_dec = 6'b111111; + 12'd3870 : mem_out_dec = 6'b111111; + 12'd3871 : mem_out_dec = 6'b111111; + 12'd3872 : mem_out_dec = 6'b111111; + 12'd3873 : mem_out_dec = 6'b111111; + 12'd3874 : mem_out_dec = 6'b111111; + 12'd3875 : mem_out_dec = 6'b111111; + 12'd3876 : mem_out_dec = 6'b111111; + 12'd3877 : mem_out_dec = 6'b111111; + 12'd3878 : mem_out_dec = 6'b111111; + 12'd3879 : mem_out_dec = 6'b111111; + 12'd3880 : mem_out_dec = 6'b111111; + 12'd3881 : mem_out_dec = 6'b111111; + 12'd3882 : mem_out_dec = 6'b111111; + 12'd3883 : mem_out_dec = 6'b111111; + 12'd3884 : mem_out_dec = 6'b111111; + 12'd3885 : mem_out_dec = 6'b111111; + 12'd3886 : mem_out_dec = 6'b111111; + 12'd3887 : mem_out_dec = 6'b111111; + 12'd3888 : mem_out_dec = 6'b111111; + 12'd3889 : mem_out_dec = 6'b111111; + 12'd3890 : mem_out_dec = 6'b111111; + 12'd3891 : mem_out_dec = 6'b111111; + 12'd3892 : mem_out_dec = 6'b111111; + 12'd3893 : mem_out_dec = 6'b111111; + 12'd3894 : mem_out_dec = 6'b111111; + 12'd3895 : mem_out_dec = 6'b111111; + 12'd3896 : mem_out_dec = 6'b111111; + 12'd3897 : mem_out_dec = 6'b111111; + 12'd3898 : mem_out_dec = 6'b111111; + 12'd3899 : mem_out_dec = 6'b111111; + 12'd3900 : mem_out_dec = 6'b111111; + 12'd3901 : mem_out_dec = 6'b111111; + 12'd3902 : mem_out_dec = 6'b111111; + 12'd3903 : mem_out_dec = 6'b111111; + 12'd3904 : mem_out_dec = 6'b111111; + 12'd3905 : mem_out_dec = 6'b111111; + 12'd3906 : mem_out_dec = 6'b111111; + 12'd3907 : mem_out_dec = 6'b111111; + 12'd3908 : mem_out_dec = 6'b111111; + 12'd3909 : mem_out_dec = 6'b111111; + 12'd3910 : mem_out_dec = 6'b111111; + 12'd3911 : mem_out_dec = 6'b111111; + 12'd3912 : mem_out_dec = 6'b111111; + 12'd3913 : mem_out_dec = 6'b111111; + 12'd3914 : mem_out_dec = 6'b111111; + 12'd3915 : mem_out_dec = 6'b111111; + 12'd3916 : mem_out_dec = 6'b111111; + 12'd3917 : mem_out_dec = 6'b111111; + 12'd3918 : mem_out_dec = 6'b111111; + 12'd3919 : mem_out_dec = 6'b111111; + 12'd3920 : mem_out_dec = 6'b111111; + 12'd3921 : mem_out_dec = 6'b111111; + 12'd3922 : mem_out_dec = 6'b111111; + 12'd3923 : mem_out_dec = 6'b111111; + 12'd3924 : mem_out_dec = 6'b111111; + 12'd3925 : mem_out_dec = 6'b111111; + 12'd3926 : mem_out_dec = 6'b111111; + 12'd3927 : mem_out_dec = 6'b111111; + 12'd3928 : mem_out_dec = 6'b111111; + 12'd3929 : mem_out_dec = 6'b111111; + 12'd3930 : mem_out_dec = 6'b111111; + 12'd3931 : mem_out_dec = 6'b111111; + 12'd3932 : mem_out_dec = 6'b111111; + 12'd3933 : mem_out_dec = 6'b111111; + 12'd3934 : mem_out_dec = 6'b111111; + 12'd3935 : mem_out_dec = 6'b111111; + 12'd3936 : mem_out_dec = 6'b111111; + 12'd3937 : mem_out_dec = 6'b111111; + 12'd3938 : mem_out_dec = 6'b111111; + 12'd3939 : mem_out_dec = 6'b111111; + 12'd3940 : mem_out_dec = 6'b111111; + 12'd3941 : mem_out_dec = 6'b111111; + 12'd3942 : mem_out_dec = 6'b111111; + 12'd3943 : mem_out_dec = 6'b111111; + 12'd3944 : mem_out_dec = 6'b111111; + 12'd3945 : mem_out_dec = 6'b111111; + 12'd3946 : mem_out_dec = 6'b111111; + 12'd3947 : mem_out_dec = 6'b111111; + 12'd3948 : mem_out_dec = 6'b111111; + 12'd3949 : mem_out_dec = 6'b111111; + 12'd3950 : mem_out_dec = 6'b111111; + 12'd3951 : mem_out_dec = 6'b111111; + 12'd3952 : mem_out_dec = 6'b111111; + 12'd3953 : mem_out_dec = 6'b111111; + 12'd3954 : mem_out_dec = 6'b111111; + 12'd3955 : mem_out_dec = 6'b111111; + 12'd3956 : mem_out_dec = 6'b111111; + 12'd3957 : mem_out_dec = 6'b111111; + 12'd3958 : mem_out_dec = 6'b111111; + 12'd3959 : mem_out_dec = 6'b111111; + 12'd3960 : mem_out_dec = 6'b111111; + 12'd3961 : mem_out_dec = 6'b111111; + 12'd3962 : mem_out_dec = 6'b111111; + 12'd3963 : mem_out_dec = 6'b111111; + 12'd3964 : mem_out_dec = 6'b111111; + 12'd3965 : mem_out_dec = 6'b111111; + 12'd3966 : mem_out_dec = 6'b111111; + 12'd3967 : mem_out_dec = 6'b111111; + 12'd3968 : mem_out_dec = 6'b111111; + 12'd3969 : mem_out_dec = 6'b111111; + 12'd3970 : mem_out_dec = 6'b111111; + 12'd3971 : mem_out_dec = 6'b111111; + 12'd3972 : mem_out_dec = 6'b111111; + 12'd3973 : mem_out_dec = 6'b111111; + 12'd3974 : mem_out_dec = 6'b111111; + 12'd3975 : mem_out_dec = 6'b111111; + 12'd3976 : mem_out_dec = 6'b111111; + 12'd3977 : mem_out_dec = 6'b111111; + 12'd3978 : mem_out_dec = 6'b111111; + 12'd3979 : mem_out_dec = 6'b111111; + 12'd3980 : mem_out_dec = 6'b111111; + 12'd3981 : mem_out_dec = 6'b111111; + 12'd3982 : mem_out_dec = 6'b111111; + 12'd3983 : mem_out_dec = 6'b111111; + 12'd3984 : mem_out_dec = 6'b111111; + 12'd3985 : mem_out_dec = 6'b111111; + 12'd3986 : mem_out_dec = 6'b111111; + 12'd3987 : mem_out_dec = 6'b111111; + 12'd3988 : mem_out_dec = 6'b111111; + 12'd3989 : mem_out_dec = 6'b111111; + 12'd3990 : mem_out_dec = 6'b111111; + 12'd3991 : mem_out_dec = 6'b111111; + 12'd3992 : mem_out_dec = 6'b111111; + 12'd3993 : mem_out_dec = 6'b111111; + 12'd3994 : mem_out_dec = 6'b111111; + 12'd3995 : mem_out_dec = 6'b111111; + 12'd3996 : mem_out_dec = 6'b111111; + 12'd3997 : mem_out_dec = 6'b111111; + 12'd3998 : mem_out_dec = 6'b111111; + 12'd3999 : mem_out_dec = 6'b111111; + 12'd4000 : mem_out_dec = 6'b111111; + 12'd4001 : mem_out_dec = 6'b111111; + 12'd4002 : mem_out_dec = 6'b111111; + 12'd4003 : mem_out_dec = 6'b111111; + 12'd4004 : mem_out_dec = 6'b111111; + 12'd4005 : mem_out_dec = 6'b111111; + 12'd4006 : mem_out_dec = 6'b111111; + 12'd4007 : mem_out_dec = 6'b111111; + 12'd4008 : mem_out_dec = 6'b111111; + 12'd4009 : mem_out_dec = 6'b111111; + 12'd4010 : mem_out_dec = 6'b111111; + 12'd4011 : mem_out_dec = 6'b111111; + 12'd4012 : mem_out_dec = 6'b111111; + 12'd4013 : mem_out_dec = 6'b111111; + 12'd4014 : mem_out_dec = 6'b111111; + 12'd4015 : mem_out_dec = 6'b111111; + 12'd4016 : mem_out_dec = 6'b111111; + 12'd4017 : mem_out_dec = 6'b111111; + 12'd4018 : mem_out_dec = 6'b111111; + 12'd4019 : mem_out_dec = 6'b111111; + 12'd4020 : mem_out_dec = 6'b111111; + 12'd4021 : mem_out_dec = 6'b111111; + 12'd4022 : mem_out_dec = 6'b111111; + 12'd4023 : mem_out_dec = 6'b111111; + 12'd4024 : mem_out_dec = 6'b111111; + 12'd4025 : mem_out_dec = 6'b111111; + 12'd4026 : mem_out_dec = 6'b111111; + 12'd4027 : mem_out_dec = 6'b111111; + 12'd4028 : mem_out_dec = 6'b111111; + 12'd4029 : mem_out_dec = 6'b111111; + 12'd4030 : mem_out_dec = 6'b111111; + 12'd4031 : mem_out_dec = 6'b111111; + 12'd4032 : mem_out_dec = 6'b111111; + 12'd4033 : mem_out_dec = 6'b111111; + 12'd4034 : mem_out_dec = 6'b111111; + 12'd4035 : mem_out_dec = 6'b111111; + 12'd4036 : mem_out_dec = 6'b111111; + 12'd4037 : mem_out_dec = 6'b111111; + 12'd4038 : mem_out_dec = 6'b111111; + 12'd4039 : mem_out_dec = 6'b111111; + 12'd4040 : mem_out_dec = 6'b111111; + 12'd4041 : mem_out_dec = 6'b111111; + 12'd4042 : mem_out_dec = 6'b111111; + 12'd4043 : mem_out_dec = 6'b111111; + 12'd4044 : mem_out_dec = 6'b111111; + 12'd4045 : mem_out_dec = 6'b111111; + 12'd4046 : mem_out_dec = 6'b111111; + 12'd4047 : mem_out_dec = 6'b111111; + 12'd4048 : mem_out_dec = 6'b111111; + 12'd4049 : mem_out_dec = 6'b111111; + 12'd4050 : mem_out_dec = 6'b111111; + 12'd4051 : mem_out_dec = 6'b111111; + 12'd4052 : mem_out_dec = 6'b111111; + 12'd4053 : mem_out_dec = 6'b111111; + 12'd4054 : mem_out_dec = 6'b111111; + 12'd4055 : mem_out_dec = 6'b111111; + 12'd4056 : mem_out_dec = 6'b111111; + 12'd4057 : mem_out_dec = 6'b111111; + 12'd4058 : mem_out_dec = 6'b111111; + 12'd4059 : mem_out_dec = 6'b111111; + 12'd4060 : mem_out_dec = 6'b111111; + 12'd4061 : mem_out_dec = 6'b111111; + 12'd4062 : mem_out_dec = 6'b111111; + 12'd4063 : mem_out_dec = 6'b111111; + 12'd4064 : mem_out_dec = 6'b111111; + 12'd4065 : mem_out_dec = 6'b111111; + 12'd4066 : mem_out_dec = 6'b111111; + 12'd4067 : mem_out_dec = 6'b111111; + 12'd4068 : mem_out_dec = 6'b111111; + 12'd4069 : mem_out_dec = 6'b111111; + 12'd4070 : mem_out_dec = 6'b111111; + 12'd4071 : mem_out_dec = 6'b111111; + 12'd4072 : mem_out_dec = 6'b111111; + 12'd4073 : mem_out_dec = 6'b111111; + 12'd4074 : mem_out_dec = 6'b111111; + 12'd4075 : mem_out_dec = 6'b111111; + 12'd4076 : mem_out_dec = 6'b111111; + 12'd4077 : mem_out_dec = 6'b111111; + 12'd4078 : mem_out_dec = 6'b111111; + 12'd4079 : mem_out_dec = 6'b111111; + 12'd4080 : mem_out_dec = 6'b111111; + 12'd4081 : mem_out_dec = 6'b111111; + 12'd4082 : mem_out_dec = 6'b111111; + 12'd4083 : mem_out_dec = 6'b111111; + 12'd4084 : mem_out_dec = 6'b111111; + 12'd4085 : mem_out_dec = 6'b111111; + 12'd4086 : mem_out_dec = 6'b111111; + 12'd4087 : mem_out_dec = 6'b111111; + 12'd4088 : mem_out_dec = 6'b111111; + 12'd4089 : mem_out_dec = 6'b111111; + 12'd4090 : mem_out_dec = 6'b111111; + 12'd4091 : mem_out_dec = 6'b111111; + 12'd4092 : mem_out_dec = 6'b111111; + 12'd4093 : mem_out_dec = 6'b111111; + 12'd4094 : mem_out_dec = 6'b111111; + 12'd4095 : mem_out_dec = 6'b111111; + endcase + end + + always @ (posedge clk) begin + dec_cnt <= #TCQ mem_out_dec; + end +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v new file mode 100644 index 0000000..6942b00 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v @@ -0,0 +1,3381 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_rdlvl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Read leveling Stage1 calibration logic +// NOTES: +// 1. Window detection with PRBS pattern. +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ +**$Date: 2011/06/24 14:49:00 $ +**$Author: mgeorge $ +**$Revision: 1.2 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +(* use_dsp48 = "no" *) + +module mig_7series_v4_2_ddr_phy_rdlvl # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter CLK_PERIOD = 3333, // Internal clock period (in ps) + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter RANKS = 1, // # of DRAM ranks + parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew + parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps + parameter DEBUG_PORT = "OFF", // Enable debug port + parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" + parameter OCAL_EN = "ON", + parameter IDELAY_ADJ = "ON", + parameter PI_DIV2_INCDEC = "TRUE" + ) + ( + input clk, + input rst, + // Calibration status, control signals + input mpr_rdlvl_start, + output mpr_rdlvl_done, + output reg mpr_last_byte_done, + output mpr_rnk_done, + input rdlvl_stg1_start, + output rdlvl_stg1_done /* synthesis syn_maxfan = 30 */, + output rdlvl_stg1_rnk_done, + output reg rdlvl_stg1_err, + output mpr_rdlvl_err, + output rdlvl_err, + output reg rdlvl_prech_req, + output rdlvl_last_byte_done, + output reg rdlvl_assrt_common, + input prech_done, + input phy_if_empty, + input [4:0] idelaye2_init_val, + // Captured data in fabric clock domain + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + // Decrement initial Phaser_IN Fine tap delay + input dqs_po_dec_done, + input [5:0] pi_counter_read_val, + // Stage 1 calibration outputs + output reg pi_fine_dly_dec_done, + output reg pi_en_stg2_f, + output reg pi_stg2_f_incdec, + output reg pi_stg2_load, + output reg [5:0] pi_stg2_reg_l, + output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt, + // To DQ IDELAY required to find left edge of + // valid window + output idelay_ce, + output idelay_inc, + input idelay_ld, + input [DQS_CNT_WIDTH:0] wrcal_cnt, + // Only output if Per-bit de-skew enabled + output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, + //output to prevent read during PI movement + output reg rdlvl_pi_incdec, + // Debug Port + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, + output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, + + input dbg_idel_up_all, + input dbg_idel_down_all, + input dbg_idel_up_cpt, + input dbg_idel_down_cpt, + input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, + input dbg_sel_all_idel_cpt, + output [255:0] dbg_phy_rdlvl + ); + + // minimum time (in IDELAY taps) for which capture data must be stable for + // algorithm to consider a valid data eye to be found. The read leveling + // logic will ignore any window found smaller than this value. Limitations + // on how small this number can be is determined by: (1) the algorithmic + // limitation of how many taps wide the data eye can be (3 taps), and (2) + // how wide regions of "instability" that occur around the edges of the + // read valid window can be (i.e. need to be able to filter out "false" + // windows that occur for a short # of taps around the edges of the true + // data window, although with multi-sampling during read leveling, this is + // not as much a concern) - the larger the value, the more protection + // against "false" windows + localparam MIN_EYE_SIZE = 16; + + // Length of calibration sequence (in # of words) + localparam CAL_PAT_LEN = 8; + // Read data shift register length + localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK); + + // # of cycles required to perform read data shift register compare + // This is defined as from the cycle the new data is loaded until + // signal found_edge_r is valid + localparam RD_SHIFT_COMP_DELAY = 5; + + // worst-case # of cycles to wait to ensure that both the SR and + // PREV_SR shift registers have valid data, and that the comparison + // of the two shift register values is valid. The "+1" at the end of + // this equation is a fudge factor, I freely admit that + localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1; + + // # of clock cycles to wait after changing tap value or read data MUX + // to allow: (1) tap chain to settle, (2) for delayed input to propagate + // thru ISERDES, (3) for the read data comparison logic to have time to + // output the comparison of two consecutive samples of the settled read data + // The minimum delay is 16 cycles, which should be good enough to handle all + // three of the above conditions for the simulation-only case with a short + // training pattern. For H/W (or for simulation with longer training + // pattern), it will take longer to store and compare two consecutive + // samples, and the value of this parameter will reflect that + // put the maximum number for 2:1 mode + localparam PIPE_WAIT_CNT = (nCK_PER_CLK == 2) ? 31 : (SR_VALID_DELAY < 8) ? 16 + : (SR_VALID_DELAY + 8); + + // # of read data samples to examine when detecting whether an edge has + // occured during stage 1 calibration. Width of local param must be + // changed as appropriate. Note that there are two counters used, each + // counter can be changed independently of the other - they are used in + // cascade to create a larger counter + localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF; + localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0 + + localparam [5:0] CAL1_IDLE = 6'h00; + localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01; + localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02; + localparam [5:0] CAL1_PAT_DETECT = 6'h03; + localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04; + localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05; + localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06; + localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07; + localparam [5:0] CAL1_DETECT_EDGE = 6'h08; + localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09; + localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A; + localparam [5:0] CAL1_CALC_IDEL = 6'h0B; + localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C; + localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D; + localparam [5:0] CAL1_NEXT_DQS = 6'h0E; + localparam [5:0] CAL1_DONE = 6'h0F; + localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10; + localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11; + localparam [5:0] CAL1_PB_INC_CPT = 6'h12; + localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13; + localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14; + localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15; + localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16; + localparam [5:0] CAL1_PB_INC_DQ = 6'h17; + localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18; + localparam [5:0] CAL1_PB_DEC_CPT = 6'h19; + localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A; + localparam [5:0] CAL1_REGL_LOAD = 6'h1B; + localparam [5:0] CAL1_RDLVL_ERR = 6'h1C; + localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D; + localparam [5:0] CAL1_VALID_WAIT = 6'h1E; + localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F; + localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20; + localparam [5:0] CAL1_RD_STOP_FOR_PI_INC = 6'h21; + localparam [5:0] CAL1_CENTER_WAIT = 6'h22; + + integer a; + integer b; + integer d; + integer e; + integer f; + integer h; + integer g; + integer i; + integer j; + integer k; + integer l; + integer m; + integer n; + integer r; + integer p; + integer q; + integer s; + integer t; + integer u; + integer w; + integer ce_i; + integer ce_rnk_i; + integer aa; + integer bb; + integer cc; + integer dd; + genvar x; + genvar z; + + reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r; + wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing; + reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r; + reg cal1_dq_idel_ce; + reg cal1_dq_idel_inc; + reg cal1_dlyce_cpt_r; + reg cal1_dlyinc_cpt_r; + reg cal1_dlyce_dq_r; + reg cal1_dlyinc_dq_r; + reg cal1_wait_cnt_en_r; + reg [4:0] cal1_wait_cnt_r; + reg cal1_wait_r; + reg [DQ_WIDTH-1:0] dlyce_dq_r; + reg dlyinc_dq_r; + reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1]; + reg cal1_prech_req_r; + reg [5:0] cal1_state_r; + reg [5:0] cal1_state_r1; + reg [5:0] cal1_state_r2; + reg [5:0] cal1_state_r3; + reg [5:0] cnt_idel_dec_cpt_r; + reg [3:0] cnt_shift_r; + reg detect_edge_done_r; + reg [5:0] right_edge_taps_r; + reg [5:0] first_edge_taps_r; + reg found_edge_r; + reg found_first_edge_r; + reg found_second_edge_r; + reg found_stable_eye_r; + reg found_stable_eye_last_r; + reg found_edge_all_r; + reg [5:0] tap_cnt_cpt_r; + reg tap_limit_cpt_r; + reg [4:0] idel_tap_cnt_dq_pb_r; + reg idel_tap_limit_dq_pb_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; + reg mux_rd_valid_r; + reg new_cnt_cpt_r; + reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0]; + reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r; + reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r; + reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r; + reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r; + reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r; + reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0]; + reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r; + reg [DRAM_WIDTH-1:0] pb_found_edge_last_r; + reg [DRAM_WIDTH-1:0] pb_found_edge_r; + reg [DRAM_WIDTH-1:0] pb_found_first_edge_r; + reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r; + reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r; + reg pi_en_stg2_f_timing; + reg pi_stg2_f_incdec_timing; + reg pi_stg2_load_timing; + reg [5:0] pi_stg2_reg_l_timing; + reg [DRAM_WIDTH-1:0] prev_sr_diff_r; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0]; + reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r; + reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r; + wire [DQ_WIDTH-1:0] rd_data_rise0; + wire [DQ_WIDTH-1:0] rd_data_fall0; + wire [DQ_WIDTH-1:0] rd_data_rise1; + wire [DQ_WIDTH-1:0] rd_data_fall1; + wire [DQ_WIDTH-1:0] rd_data_rise2; + wire [DQ_WIDTH-1:0] rd_data_fall2; + wire [DQ_WIDTH-1:0] rd_data_rise3; + wire [DQ_WIDTH-1:0] rd_data_fall3; + reg samp_cnt_done_r; + reg samp_edge_cnt0_en_r; + reg [11:0] samp_edge_cnt0_r; + reg samp_edge_cnt1_en_r; + reg [11:0] samp_edge_cnt1_r; + reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; + reg [5:0] second_edge_taps_r; + reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; + reg store_sr_r; + reg store_sr_req_pulsed_r; + reg store_sr_req_r; + reg sr_valid_r; + reg sr_valid_r1; + reg sr_valid_r2; + reg [DRAM_WIDTH-1:0] old_sr_diff_r; + reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r; + reg pat0_data_match_r; + reg pat1_data_match_r; + wire pat_data_match_r; + wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0]; + reg [DRAM_WIDTH-1:0] pat0_match_fall0_r; + reg pat0_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_fall1_r; + reg pat0_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_fall2_r; + reg pat0_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_fall3_r; + reg pat0_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise0_r; + reg pat0_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise1_r; + reg pat0_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise2_r; + reg pat0_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] pat0_match_rise3_r; + reg pat0_match_rise3_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; + reg pat1_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; + reg pat1_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall2_r; + reg pat1_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall3_r; + reg pat1_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; + reg pat1_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; + reg pat1_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise2_r; + reg pat1_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise3_r; + reg pat1_match_rise3_and_r; + reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; + reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w; + reg [4:0] idelay_tap_cnt_slice_r; + reg idelay_tap_limit_r; + + wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0]; + + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0]; + + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r; + reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r; + + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r; + reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r; + + reg idel_pat0_match_rise0_and_r; + reg idel_pat0_match_fall0_and_r; + reg idel_pat0_match_rise1_and_r; + reg idel_pat0_match_fall1_and_r; + reg idel_pat0_match_rise2_and_r; + reg idel_pat0_match_fall2_and_r; + reg idel_pat0_match_rise3_and_r; + reg idel_pat0_match_fall3_and_r; + + reg idel_pat1_match_rise0_and_r; + reg idel_pat1_match_fall0_and_r; + reg idel_pat1_match_rise1_and_r; + reg idel_pat1_match_fall1_and_r; + reg idel_pat1_match_rise2_and_r; + reg idel_pat1_match_fall2_and_r; + reg idel_pat1_match_rise3_and_r; + reg idel_pat1_match_fall3_and_r; + + reg idel_pat0_data_match_r; + reg idel_pat1_data_match_r; + + reg idel_pat_data_match; + reg idel_pat_data_match_r; + + reg [4:0] idel_dec_cnt; + + reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1]; + reg [1:0] rnk_cnt_r; + reg rdlvl_rank_done_r; + + reg [3:0] done_cnt; + reg [1:0] regl_rank_cnt; + reg [DQS_CNT_WIDTH:0] regl_dqs_cnt; + reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r; + wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing; + reg regl_rank_done_r; + reg rdlvl_stg1_start_r; + + reg dqs_po_dec_done_r1; + reg dqs_po_dec_done_r2; + reg fine_dly_dec_done_r1; + reg fine_dly_dec_done_r2; + reg fine_dly_dec_done_r3; + reg fine_dly_dec_done_r4; + reg [3:0] wait_cnt_r; + reg [5:0] pi_rdval_cnt; + reg pi_cnt_dec; + + reg mpr_valid_r; + reg mpr_valid_r1; + reg mpr_valid_r2; + reg mpr_rd_rise0_prev_r; + reg mpr_rd_fall0_prev_r; + reg mpr_rd_rise1_prev_r; + reg mpr_rd_fall1_prev_r; + reg mpr_rd_rise2_prev_r; + reg mpr_rd_fall2_prev_r; + reg mpr_rd_rise3_prev_r; + reg mpr_rd_fall3_prev_r; + reg mpr_rdlvl_done_r; + reg mpr_rdlvl_done_r1; + reg mpr_rdlvl_done_r2; + reg mpr_rdlvl_start_r; + reg mpr_rank_done_r; + reg [2:0] stable_idel_cnt; + reg inhibit_edge_detect_r; + reg idel_pat_detect_valid_r; + reg idel_mpr_pat_detect_r; + reg mpr_pat_detect_r; + reg mpr_dec_cpt_r; + reg idel_adj_inc; //IDELAY adjustment + wire [1:0] idelay_adj; + wire pb_detect_edge_setup; + wire pb_detect_edge; + // Debug + reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps; + reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps; + reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w; + reg rdlvl_stg1_done_int; + reg rdlvl_stg1_done_int_r1, rdlvl_stg1_done_int_r2, rdlvl_stg1_done_int_r3; + reg rdlvl_last_byte_done_int; + reg rdlvl_last_byte_done_int_r1, rdlvl_last_byte_done_int_r2, rdlvl_last_byte_done_int_r3; + + + //IDELAY adjustment setting for -1 + //2'b10 : IDELAY - 1 + //2'b01 : IDELAY + 1 + //2'b00 : No IDELAY adjustment + assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00; + + //*************************************************************************** + // Debug + //*************************************************************************** + + always @(*) begin + for (d = 0; d < RANKS; d = d + 1) begin + for (e = 0; e < DQS_WIDTH; e = e + 1) begin + idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e]; + dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e]; + end + end + end + + assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done); + assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done); + + + assign dbg_phy_rdlvl[0] = rdlvl_stg1_start; + assign dbg_phy_rdlvl[1] = pat_data_match_r; + assign dbg_phy_rdlvl[2] = mux_rd_valid_r; + assign dbg_phy_rdlvl[3] = idelay_tap_limit_r; + assign dbg_phy_rdlvl[8:4] = 'b0; + assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0]; + assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r; + assign dbg_phy_rdlvl[21] = found_first_edge_r; + assign dbg_phy_rdlvl[22] = found_second_edge_r; + assign dbg_phy_rdlvl[23] = found_edge_r; + assign dbg_phy_rdlvl[24] = store_sr_r; + // [40:25] previously used for sr, old_sr shift registers. If connecting + // these signals again, don't forget to parameterize based on RD_SHIFT_LEN + assign dbg_phy_rdlvl[40:25] = 'b0; + assign dbg_phy_rdlvl[41] = sr_valid_r; + assign dbg_phy_rdlvl[42] = found_stable_eye_r; + assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r; + assign dbg_phy_rdlvl[54:49] = first_edge_taps_r; + assign dbg_phy_rdlvl[60:55] = second_edge_taps_r; + assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r; + assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r; + assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r; + assign dbg_phy_rdlvl[67] = found_edge_r; + assign dbg_phy_rdlvl[68] = found_first_edge_r; + assign dbg_phy_rdlvl[73:69] = 'b0; + assign dbg_phy_rdlvl[74] = idel_pat_data_match; + assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r; + assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r; + assign dbg_phy_rdlvl[77] = pat0_data_match_r; + assign dbg_phy_rdlvl[78] = pat1_data_match_r; + assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w; + assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r; + assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r; + assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r; + assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r; + assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r; + assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r; + assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r; + assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r; + + //*************************************************************************** + // Debug output + //*************************************************************************** + + // CPT taps + assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps; + assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps; + assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w; + assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w; + + // Record first and second edges found during CPT calibration + + generate + always @(posedge clk) + if (rst || (rdlvl_stg1_start && ~rdlvl_stg1_start_r)) begin + dbg_cpt_first_edge_taps <= #TCQ 'b0; + dbg_cpt_second_edge_taps <= #TCQ 'b0; + end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin + //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk + for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge + if (found_first_edge_r) + dbg_cpt_first_edge_taps[(6*ce_i)+:6] + <= #TCQ first_edge_taps_r; + if (found_second_edge_r) + dbg_cpt_second_edge_taps[(6*ce_i)+:6] + <= #TCQ second_edge_taps_r; + end + //end + end else if (cal1_state_r == CAL1_CALC_IDEL) begin + // Record tap counts of first and second edge edges during + // CPT calibration for each DQS group. If neither edge has + // been found, then those taps will remain 0 + if (found_first_edge_r) + dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] + <= #TCQ first_edge_taps_r; + if (found_second_edge_r) + dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6] + <= #TCQ second_edge_taps_r; + end + endgenerate + + assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r; + assign mpr_rnk_done = mpr_rank_done_r; + assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE") + mpr_rdlvl_done_r : 1'b1; + + //************************************************************************** + // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 + // coarse delay + //************************************************************************** + assign pi_stg2_rdlvl_cnt = (((PI_DIV2_INCDEC == "TRUE") && (cal1_state_r3 == CAL1_REGL_LOAD)) || ((PI_DIV2_INCDEC == "FALSE") && (cal1_state_r == CAL1_REGL_LOAD))) ? regl_dqs_cnt_r : cal1_cnt_cpt_r; + assign rdlvl_stg1_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_stg1_done_int_r3 : rdlvl_stg1_done_int; + assign rdlvl_last_byte_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_last_byte_done_int_r3 : rdlvl_last_byte_done_int; + + always @ (posedge clk) begin + rdlvl_stg1_done_int_r1 <= #TCQ rdlvl_stg1_done_int; + rdlvl_stg1_done_int_r2 <= #TCQ rdlvl_stg1_done_int_r1; + rdlvl_stg1_done_int_r3 <= #TCQ rdlvl_stg1_done_int_r2; + rdlvl_last_byte_done_int_r1 <= #TCQ rdlvl_last_byte_done_int; + rdlvl_last_byte_done_int_r2 <= #TCQ rdlvl_last_byte_done_int_r1; + rdlvl_last_byte_done_int_r3 <= #TCQ rdlvl_last_byte_done_int_r2; + end + + assign idelay_ce = cal1_dq_idel_ce; + assign idelay_inc = cal1_dq_idel_inc; + + //*************************************************************************** + // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all + // DQs simultaneously + //*************************************************************************** + + always @(posedge clk) begin + if (rst) + rdlvl_assrt_common <= #TCQ 1'b0; + else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start & + !rdlvl_stg1_start_r) + rdlvl_assrt_common <= #TCQ 1'b1; + else if (!idel_pat_data_match_r & idel_pat_data_match) + rdlvl_assrt_common <= #TCQ 1'b0; + end + + //*************************************************************************** + // Data mux to route appropriate bit to calibration logic - i.e. calibration + // is done sequentially, one bit (or DQS group) at a time + //*************************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + end else begin: rd_data_div2_logic_clk + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + end + endgenerate + + always @(posedge clk) begin + rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r; + end + + // Register outputs for improved timing. + // NOTE: Will need to change when per-bit DQ deskew is supported. + // Currenly all bits in DQS group are checked in aggregate + generate + genvar mux_i; + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + + mux_i]; + end + end + endgenerate + + //*************************************************************************** + // MPR Read Leveling + //*************************************************************************** + + // storing the previous read data for checking later. Only bit 0 is used + // since MPR contents (01010101) are available generally on DQ[0] per + // JEDEC spec. + always @(posedge clk)begin + if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || + ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin + mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0]; + mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0]; + mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0]; + mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0]; + mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0]; + mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0]; + mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0]; + mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0]; + end + end + + generate + if (nCK_PER_CLK == 4) begin: mpr_4to1 + // changed stable count of 2 IDELAY taps at 78 ps resolution + always @(posedge clk) begin + if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) | + //(cal1_state_r == CAL1_DETECT_EDGE) | + (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) | + (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) | + (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) | + (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) | + (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])) + stable_idel_cnt <= #TCQ 3'd0; + else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) & + ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idel_pat_detect_valid_r))) begin + if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & + (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & + (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & + (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & + (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) & + (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) & + (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) & + (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) & + (stable_idel_cnt < 3'd2)) + stable_idel_cnt <= #TCQ stable_idel_cnt + 1; + end + end + + always @(posedge clk) begin + if (rst | + (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & + mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & + mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r)) + inhibit_edge_detect_r <= 1'b1; + // Wait for settling time after idelay tap increment before + // de-asserting inhibit_edge_detect_r + else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & + (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & + ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & + ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r)) + inhibit_edge_detect_r <= 1'b0; + end + + //checking for transition from 01010101 to 10101010 + always @(posedge clk)begin + if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | + inhibit_edge_detect_r) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 10101010 is not the correct pattern + else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r & + mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r & + mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) || + ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) + && (idel_pat_detect_valid_r))) + //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 01010101 to 10101010 is the correct transition + else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r & + ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r & + ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) & + (stable_idel_cnt == 3'd2) & + ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) || + (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) || + (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) || + (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) || + (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))) + idel_mpr_pat_detect_r <= #TCQ 1'b1; + end + end else if (nCK_PER_CLK == 2) begin: mpr_2to1 + // changed stable count of 2 IDELAY taps at 78 ps resolution + always @(posedge clk) begin + if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | + (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) | + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) | + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) | + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])) + stable_idel_cnt <= #TCQ 3'd0; + else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) & + ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idel_pat_detect_valid_r))) begin + if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) & + (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) & + (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) & + (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) & + (stable_idel_cnt < 3'd2)) + stable_idel_cnt <= #TCQ stable_idel_cnt + 1; + end + end + + always @(posedge clk) begin + if (rst | + (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r)) + inhibit_edge_detect_r <= 1'b1; + else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) & + (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) & + (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r)) + inhibit_edge_detect_r <= 1'b0; + end + + //checking for transition from 01010101 to 10101010 + always @(posedge clk)begin + if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) | + inhibit_edge_detect_r) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 1010 is not the correct pattern + else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r & + mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) || + ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT) + & (idel_pat_detect_valid_r))) + // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2)) + idel_mpr_pat_detect_r <= #TCQ 1'b0; + // 0101 to 1010 is the correct transition + else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r & + ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) & + (stable_idel_cnt == 3'd2) & + ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) || + (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) || + (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) || + (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))) + idel_mpr_pat_detect_r <= #TCQ 1'b1; + end + end + endgenerate + + + + // Registered signal indicates when mux_rd_rise/fall_r is valid + always @(posedge clk) + mux_rd_valid_r <= #TCQ ~phy_if_empty; + + + //*************************************************************************** + // Decrement initial Phaser_IN fine delay value before proceeding with + // read calibration + //*************************************************************************** + + always @(posedge clk) begin + dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done; + dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; + fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; + fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2; + fine_dly_dec_done_r4 <= #TCQ fine_dly_dec_done_r3; + if (PI_DIV2_INCDEC == "TRUE") + pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r4; + else + pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2; + end + + always @(posedge clk) begin + if (rst || pi_cnt_dec) + wait_cnt_r <= #TCQ 'd8; + else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0)) + wait_cnt_r <= #TCQ wait_cnt_r - 1; + end + + always @(posedge clk) begin + if (rst) begin + pi_rdval_cnt <= #TCQ 'd0; + end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin + pi_rdval_cnt <= #TCQ pi_counter_read_val; + end else if (pi_rdval_cnt > 'd0) begin + if (pi_cnt_dec) + pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; + else + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end else if (pi_rdval_cnt == 'd0) begin + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (pi_rdval_cnt == 'd0)) + pi_cnt_dec <= #TCQ 1'b0; + else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) + && (wait_cnt_r == 'd1)) + pi_cnt_dec <= #TCQ 1'b1; + else + pi_cnt_dec <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst) begin + fine_dly_dec_done_r1 <= #TCQ 1'b0; + end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || + (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin + fine_dly_dec_done_r1 <= #TCQ 1'b1; + end + end + + //*************************************************************************** + // Demultiplexor to control Phaser_IN delay values + //*************************************************************************** + + // Read DQS + always @(posedge clk) begin + if (rst) begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end else if (pi_cnt_dec) begin + pi_en_stg2_f_timing <= #TCQ 'b1; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end else if (cal1_dlyce_cpt_r) begin + if ((SIM_CAL_OPTION == "NONE") || + (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin + // Change only specified DQS + pi_en_stg2_f_timing <= #TCQ 1'b1; + pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; + end else if (SIM_CAL_OPTION == "FAST_CAL") begin + // if simulating, and "shortcuts" for calibration enabled, apply + // results to all DQSs (i.e. assume same delay on all + // DQSs). + pi_en_stg2_f_timing <= #TCQ 1'b1; + pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r; + end + end else begin + pi_en_stg2_f_timing <= #TCQ 'b0; + pi_stg2_f_incdec_timing <= #TCQ 'b0; + end + end + + // registered for timing + always @(posedge clk) begin + pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; + pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; + end + + // This counter used to implement settling time between + // Phaser_IN rank register loads to different DQSs + always @(posedge clk) begin + if (rst) + done_cnt <= #TCQ 'b0; + else if (((cal1_state_r == CAL1_REGL_LOAD) && + (cal1_state_r1 == CAL1_NEXT_DQS)) || + ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE))) + done_cnt <= #TCQ 4'b1010; + else if (done_cnt > 'b0) + done_cnt <= #TCQ done_cnt - 1; + end + + // During rank register loading the rank count must be sent to + // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to + // issue NOPs during rank register loading with the appropriate + // rank count + always @(posedge clk) begin + if (rst || (regl_rank_done_r == 1'b1)) + regl_rank_done_r <= #TCQ 1'b0; + else if ((regl_dqs_cnt == DQS_WIDTH-1) && + (regl_rank_cnt != RANKS-1) && + (done_cnt == 4'd1)) + regl_rank_done_r <= #TCQ 1'b1; + end + + // Temp wire for timing. + // The following in the always block below causes timing issues + // due to DSP block inference + // 6*regl_dqs_cnt. + // replacing this with two left shifts + 1 left shift to avoid + // DSP multiplier. + assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt}; + + // Load Phaser_OUT rank register with rdlvl delay value + // for each DQS per rank. + always @(posedge clk) begin + if (rst || (done_cnt == 4'd0)) begin + pi_stg2_load_timing <= #TCQ 'b0; + pi_stg2_reg_l_timing <= #TCQ 'b0; + end else if ((cal1_state_r == CAL1_REGL_LOAD) && + (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin + pi_stg2_load_timing <= #TCQ 'b1; + pi_stg2_reg_l_timing <= #TCQ + rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt]; + end else begin + pi_stg2_load_timing <= #TCQ 'b0; + pi_stg2_reg_l_timing <= #TCQ 'b0; + end + end + + // registered for timing + always @(posedge clk) begin + pi_stg2_load <= #TCQ pi_stg2_load_timing; + pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing; + end + + always @(posedge clk) begin + if (rst || (done_cnt == 4'd0) || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + regl_rank_cnt <= #TCQ 2'b00; + else if ((cal1_state_r == CAL1_REGL_LOAD) && + (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin + if (regl_rank_cnt == RANKS-1) + regl_rank_cnt <= #TCQ regl_rank_cnt; + else + regl_rank_cnt <= #TCQ regl_rank_cnt + 1; + end + end + + always @(posedge clk) begin + if (rst || (done_cnt == 4'd0) || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; + else if ((cal1_state_r == CAL1_REGL_LOAD) && + (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin + if (regl_rank_cnt == RANKS-1) + regl_dqs_cnt <= #TCQ regl_dqs_cnt; + else + regl_dqs_cnt <= #TCQ 'b0; + end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1) + && (done_cnt == 4'd1)) + regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1; + else + regl_dqs_cnt <= #TCQ regl_dqs_cnt; + end + + + always @(posedge clk) + regl_dqs_cnt_r <= #TCQ regl_dqs_cnt; + //***************************************************************** + // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC: + // The actual IDELAY elements for each of the DQ bits is set via the + // DLYVAL parallel load port. However, the stage 1 calibration + // algorithm (well most of it) only needs to increment or decrement the DQ + // IDELAY value by 1 at any one time. + //***************************************************************** + + // Chip-select generation for each of the individual counters tracking + // IDELAY tap values for each DQ + generate + for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq + always @(posedge clk) + if (rst) + dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; + else + if (SIM_CAL_OPTION == "SKIP_CAL") + // If skipping calibration altogether (only for simulation), no + // need to set DQ IODELAY values - they are hardcoded + dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; + else if (SIM_CAL_OPTION == "FAST_CAL") begin + // If fast calibration option (simulation only) selected, DQ + // IODELAYs across all bytes are updated simultaneously + // (although per-bit deskew within DQS[0] is still supported) + for (h = 0; h < DRAM_WIDTH; h = h + 1) begin + dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r; + end + end else if ((SIM_CAL_OPTION == "NONE") || + (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin + if (cal1_cnt_cpt_r == z) begin + for (g = 0; g < DRAM_WIDTH; g = g + 1) begin + dlyce_dq_r[DRAM_WIDTH*z + g] + <= #TCQ cal1_dlyce_dq_r; + end + end else + dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0; + end + end + endgenerate + + // Also delay increment/decrement control to match delay on DLYCE + always @(posedge clk) + if (rst) + dlyinc_dq_r <= #TCQ 1'b0; + else + dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r; + + + // Each DQ has a counter associated with it to record current read-leveling + // delay value + always @(posedge clk) + // Reset or skipping calibration all together + if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin + for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r + for (bb = 0; bb < DQ_WIDTH; bb = bb + 1) + dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0; + end + end else if (SIM_CAL_OPTION == "FAST_CAL") begin + for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk + for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg + if (dlyce_dq_r[r]) begin + if (dlyinc_dq_r) + dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01; + else + dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01; + end + end + end + end else begin + if (dlyce_dq_r[cal1_cnt_cpt_r]) begin + if (dlyinc_dq_r) + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01; + else + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ + dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01; + end + end + + // Register for timing (help with logic placement) + always @(posedge clk) begin + for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn + for (dd = 0; dd < DQ_WIDTH; dd = dd + 1) + dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd]; + end + end + + //*************************************************************************** + // Generate signal used to delay calibration state machine - used when: + // (1) IDELAY value changed + // (2) RD_MUX_SEL value changed + // Use when a delay is necessary to give the change time to propagate + // through the data pipeline (through IDELAY and ISERDES, and fabric + // pipeline stages) + //*************************************************************************** + + + // List all the stage 1 calibration wait states here. + // verilint STARC-2.7.3.3b off + always @(posedge clk) + if ((cal1_state_r == CAL1_NEW_DQS_WAIT) || + (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) || + (cal1_state_r == CAL1_NEW_DQS_PREWAIT) || + (cal1_state_r == CAL1_VALID_WAIT) || + (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_PB_INC_CPT_WAIT) || + (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) || + (cal1_state_r == CAL1_PB_INC_DQ_WAIT) || + (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) || + (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) || + (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) || + (cal1_state_r == CAL1_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) || + (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT) || + (cal1_state_r == CAL1_CENTER_WAIT) || + (cal1_state_r == CAL1_RD_STOP_FOR_PI_INC)) + cal1_wait_cnt_en_r <= #TCQ 1'b1; + else + cal1_wait_cnt_en_r <= #TCQ 1'b0; +// verilint STARC-2.7.3.3b on + always @(posedge clk) + if (!cal1_wait_cnt_en_r) begin + cal1_wait_cnt_r <= #TCQ 5'b00000; + cal1_wait_r <= #TCQ 1'b1; + end else begin + if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin + cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1; + cal1_wait_r <= #TCQ 1'b1; + end else begin + // Need to reset to 0 to handle the case when there are two + // different WAIT states back-to-back + cal1_wait_cnt_r <= #TCQ 5'b00000; + cal1_wait_r <= #TCQ 1'b0; + end + end + + //*************************************************************************** + // generate request to PHY_INIT logic to issue precharged. Required when + // calibration can take a long time (during which there are only constant + // reads present on this bus). In this case need to issue perioidic + // precharges to avoid tRAS violation. This signal must meet the following + // requirements: (1) only transition from 0->1 when prech is first needed, + // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted + //*************************************************************************** + + always @(posedge clk) + if (rst) + rdlvl_prech_req <= #TCQ 1'b0; + else + rdlvl_prech_req <= #TCQ cal1_prech_req_r; + + //*************************************************************************** + // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of + // data from ISERDES. The value of this register is also stored, so that + // previous and current values of the ISERDES data can be compared while + // varying the IODELAY taps to see if an "edge" of the data valid window + // has been encountered since the last IODELAY tap adjustment + //*************************************************************************** + + //*************************************************************************** + // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES + // NOTE: Written using discrete flops, but SRL can be used if the matching + // logic does the comparison sequentially, rather than parallel + //*************************************************************************** + + generate + genvar rd_i; + if (nCK_PER_CLK == 4) begin: gen_sr_div4 + if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; + sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; + sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; + sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; + sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; + sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; + sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; + sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; + end + end + end + end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise0_r[rd_i]}; + sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall0_r[rd_i]}; + sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise1_r[rd_i]}; + sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall1_r[rd_i]}; + sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise2_r[rd_i]}; + sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall2_r[rd_i]}; + sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise3_r[rd_i]}; + sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall3_r[rd_i]}; + end + end + end + end + end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 + if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]}; + sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]}; + sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]}; + sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]}; + end + end + end + end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + if (mux_rd_valid_r) begin + sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise0_r[rd_i]}; + sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall0_r[rd_i]}; + sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_rise1_r[rd_i]}; + sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0], + mux_rd_fall1_r[rd_i]}; + end + end + end + end + end + endgenerate + + //*************************************************************************** + // Conversion to pattern calibration + //*************************************************************************** + + // Pattern for DQ IDELAY calibration + + //***************************************************************** + // Expected data pattern when DQ shifted to the right such that + // DQS before the left edge of the DVW: + // Based on pattern of ({rise,fall}) = + // 0x1, 0xB, 0x4, 0x4, 0xB, 0x9 + // Each nibble will look like: + // bit3: 0, 1, 0, 0, 1, 1 + // bit2: 0, 0, 1, 1, 0, 0 + // bit1: 0, 1, 0, 0, 1, 0 + // bit0: 1, 1, 0, 0, 1, 1 + // Or if the write is early it could look like: + // 0x4, 0x4, 0xB, 0x9, 0x6, 0xE + // bit3: 0, 0, 1, 1, 0, 1 + // bit2: 1, 1, 0, 0, 1, 1 + // bit1: 0, 0, 1, 0, 1, 1 + // bit0: 0, 0, 1, 1, 0, 0 + // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN + // and the actual training pattern contents change + //***************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: gen_pat_div4 + // Pattern for DQ IDELAY increment + + // Target pattern for "early write" + assign {idel_pat0_rise0[3], idel_pat0_rise0[2], + idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1; + assign {idel_pat0_fall0[3], idel_pat0_fall0[2], + idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7; + assign {idel_pat0_rise1[3], idel_pat0_rise1[2], + idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE; + assign {idel_pat0_fall1[3], idel_pat0_fall1[2], + idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC; + assign {idel_pat0_rise2[3], idel_pat0_rise2[2], + idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9; + assign {idel_pat0_fall2[3], idel_pat0_fall2[2], + idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2; + assign {idel_pat0_rise3[3], idel_pat0_rise3[2], + idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4; + assign {idel_pat0_fall3[3], idel_pat0_fall3[2], + idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB; + + // Target pattern for "on-time write" + assign {idel_pat1_rise0[3], idel_pat1_rise0[2], + idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4; + assign {idel_pat1_fall0[3], idel_pat1_fall0[2], + idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9; + assign {idel_pat1_rise1[3], idel_pat1_rise1[2], + idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3; + assign {idel_pat1_fall1[3], idel_pat1_fall1[2], + idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7; + assign {idel_pat1_rise2[3], idel_pat1_rise2[2], + idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE; + assign {idel_pat1_fall2[3], idel_pat1_fall2[2], + idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC; + assign {idel_pat1_rise3[3], idel_pat1_rise3[2], + idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9; + assign {idel_pat1_fall3[3], idel_pat1_fall3[2], + idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2; + + + // Correct data valid window for "early write" + assign {pat0_rise0[3], pat0_rise0[2], + pat0_rise0[1], pat0_rise0[0]} = 4'h7; + assign {pat0_fall0[3], pat0_fall0[2], + pat0_fall0[1], pat0_fall0[0]} = 4'hE; + assign {pat0_rise1[3], pat0_rise1[2], + pat0_rise1[1], pat0_rise1[0]} = 4'hC; + assign {pat0_fall1[3], pat0_fall1[2], + pat0_fall1[1], pat0_fall1[0]} = 4'h9; + assign {pat0_rise2[3], pat0_rise2[2], + pat0_rise2[1], pat0_rise2[0]} = 4'h2; + assign {pat0_fall2[3], pat0_fall2[2], + pat0_fall2[1], pat0_fall2[0]} = 4'h4; + assign {pat0_rise3[3], pat0_rise3[2], + pat0_rise3[1], pat0_rise3[0]} = 4'hB; + assign {pat0_fall3[3], pat0_fall3[2], + pat0_fall3[1], pat0_fall3[0]} = 4'h1; + + // Correct data valid window for "on-time write" + assign {pat1_rise0[3], pat1_rise0[2], + pat1_rise0[1], pat1_rise0[0]} = 4'h9; + assign {pat1_fall0[3], pat1_fall0[2], + pat1_fall0[1], pat1_fall0[0]} = 4'h3; + assign {pat1_rise1[3], pat1_rise1[2], + pat1_rise1[1], pat1_rise1[0]} = 4'h7; + assign {pat1_fall1[3], pat1_fall1[2], + pat1_fall1[1], pat1_fall1[0]} = 4'hE; + assign {pat1_rise2[3], pat1_rise2[2], + pat1_rise2[1], pat1_rise2[0]} = 4'hC; + assign {pat1_fall2[3], pat1_fall2[2], + pat1_fall2[1], pat1_fall2[0]} = 4'h9; + assign {pat1_rise3[3], pat1_rise3[2], + pat1_rise3[1], pat1_rise3[0]} = 4'h2; + assign {pat1_fall3[3], pat1_fall3[2], + pat1_fall3[1], pat1_fall3[0]} = 4'h4; + + end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 + + // Pattern for DQ IDELAY increment + + // Target pattern for "early write" + assign idel_pat0_rise0[3] = 2'b01; + assign idel_pat0_fall0[3] = 2'b00; + assign idel_pat0_rise1[3] = 2'b10; + assign idel_pat0_fall1[3] = 2'b11; + + assign idel_pat0_rise0[2] = 2'b00; + assign idel_pat0_fall0[2] = 2'b10; + assign idel_pat0_rise1[2] = 2'b11; + assign idel_pat0_fall1[2] = 2'b10; + + assign idel_pat0_rise0[1] = 2'b00; + assign idel_pat0_fall0[1] = 2'b11; + assign idel_pat0_rise1[1] = 2'b10; + assign idel_pat0_fall1[1] = 2'b01; + + assign idel_pat0_rise0[0] = 2'b11; + assign idel_pat0_fall0[0] = 2'b10; + assign idel_pat0_rise1[0] = 2'b00; + assign idel_pat0_fall1[0] = 2'b01; + + + // Target pattern for "on-time write" + assign idel_pat1_rise0[3] = 2'b01; + assign idel_pat1_fall0[3] = 2'b11; + assign idel_pat1_rise1[3] = 2'b01; + assign idel_pat1_fall1[3] = 2'b00; + + assign idel_pat1_rise0[2] = 2'b11; + assign idel_pat1_fall0[2] = 2'b01; + assign idel_pat1_rise1[2] = 2'b00; + assign idel_pat1_fall1[2] = 2'b10; + + assign idel_pat1_rise0[1] = 2'b01; + assign idel_pat1_fall0[1] = 2'b00; + assign idel_pat1_rise1[1] = 2'b10; + assign idel_pat1_fall1[1] = 2'b11; + + assign idel_pat1_rise0[0] = 2'b00; + assign idel_pat1_fall0[0] = 2'b10; + assign idel_pat1_rise1[0] = 2'b11; + assign idel_pat1_fall1[0] = 2'b10; + + + // Correct data valid window for "early write" + assign pat0_rise0[3] = 2'b00; + assign pat0_fall0[3] = 2'b10; + assign pat0_rise1[3] = 2'b11; + assign pat0_fall1[3] = 2'b10; + + assign pat0_rise0[2] = 2'b10; + assign pat0_fall0[2] = 2'b11; + assign pat0_rise1[2] = 2'b10; + assign pat0_fall1[2] = 2'b00; + + assign pat0_rise0[1] = 2'b11; + assign pat0_fall0[1] = 2'b10; + assign pat0_rise1[1] = 2'b01; + assign pat0_fall1[1] = 2'b00; + + assign pat0_rise0[0] = 2'b10; + assign pat0_fall0[0] = 2'b00; + assign pat0_rise1[0] = 2'b01; + assign pat0_fall1[0] = 2'b11; + + // Correct data valid window for "on-time write" + assign pat1_rise0[3] = 2'b11; + assign pat1_fall0[3] = 2'b01; + assign pat1_rise1[3] = 2'b00; + assign pat1_fall1[3] = 2'b10; + + assign pat1_rise0[2] = 2'b01; + assign pat1_fall0[2] = 2'b00; + assign pat1_rise1[2] = 2'b10; + assign pat1_fall1[2] = 2'b11; + + assign pat1_rise0[1] = 2'b00; + assign pat1_fall0[1] = 2'b10; + assign pat1_rise1[1] = 2'b11; + assign pat1_fall1[1] = 2'b10; + + assign pat1_rise0[0] = 2'b10; + assign pat1_fall0[0] = 2'b11; + assign pat1_rise1[0] = 2'b10; + assign pat1_fall1[0] = 2'b00; + end + endgenerate + + // Each bit of each byte is compared to expected pattern. + // This was done to prevent (and "drastically decrease") the chance that + // invalid data clocked in when the DQ bus is tri-state (along with a + // combination of the correct data) will resemble the expected data + // pattern. A better fix for this is to change the training pattern and/or + // make the pattern longer. + generate + genvar pt_i; + if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + + // DQ IDELAY pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4]) + idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4]) + idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4]) + idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4]) + idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4]) + idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4]) + idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4]) + idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4]) + idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + // DQS DVW pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) + pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) + pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) + pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) + pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4]) + pat0_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4]) + pat0_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4]) + pat0_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4]) + pat0_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) + pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) + pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) + pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) + pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4]) + pat1_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4]) + pat1_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4]) + pat1_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4]) + pat1_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + end + + // Combine pattern match "subterms" for DQ-IDELAY stage + always @(posedge clk) begin + idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; + idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; + idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; + idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; + idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r; + idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r; + idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r; + idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r; + idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && + idel_pat0_match_fall0_and_r && + idel_pat0_match_rise1_and_r && + idel_pat0_match_fall1_and_r && + idel_pat0_match_rise2_and_r && + idel_pat0_match_fall2_and_r && + idel_pat0_match_rise3_and_r && + idel_pat0_match_fall3_and_r); + end + + always @(posedge clk) begin + idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; + idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; + idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; + idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; + idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r; + idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r; + idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r; + idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r; + idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && + idel_pat1_match_fall0_and_r && + idel_pat1_match_rise1_and_r && + idel_pat1_match_fall1_and_r && + idel_pat1_match_rise2_and_r && + idel_pat1_match_fall2_and_r && + idel_pat1_match_rise3_and_r && + idel_pat1_match_fall3_and_r); + end + + always @(*) + idel_pat_data_match <= #TCQ idel_pat0_data_match_r | + idel_pat1_data_match_r; + + always @(posedge clk) + idel_pat_data_match_r <= #TCQ idel_pat_data_match; + + // Combine pattern match "subterms" for DQS-PHASER_IN stage + always @(posedge clk) begin + pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; + pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; + pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; + pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; + pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r; + pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r; + pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r; + pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r; + pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && + pat0_match_fall0_and_r && + pat0_match_rise1_and_r && + pat0_match_fall1_and_r && + pat0_match_rise2_and_r && + pat0_match_fall2_and_r && + pat0_match_rise3_and_r && + pat0_match_fall3_and_r); + end + + always @(posedge clk) begin + pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; + pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; + pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; + pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; + pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r; + pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r; + pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r; + pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r; + pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && + pat1_match_fall0_and_r && + pat1_match_rise1_and_r && + pat1_match_fall1_and_r && + pat1_match_rise2_and_r && + pat1_match_fall2_and_r && + pat1_match_rise3_and_r && + pat1_match_fall3_and_r); + end + + assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; + + end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + + // DQ IDELAY pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4]) + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4]) + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4]) + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4]) + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4]) + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4]) + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4]) + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4]) + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + // DQS DVW pattern detection + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4]) + pat0_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4]) + pat0_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4]) + pat0_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4]) + pat0_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat0_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) + pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) + pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) + pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) + pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + end + + // Combine pattern match "subterms" for DQ-IDELAY stage + always @(posedge clk) begin + idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r; + idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r; + idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r; + idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r; + idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r && + idel_pat0_match_fall0_and_r && + idel_pat0_match_rise1_and_r && + idel_pat0_match_fall1_and_r); + end + + always @(posedge clk) begin + idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r; + idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r; + idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r; + idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r; + idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r && + idel_pat1_match_fall0_and_r && + idel_pat1_match_rise1_and_r && + idel_pat1_match_fall1_and_r); + end + + always @(posedge clk) begin + if (sr_valid_r2) + idel_pat_data_match <= #TCQ idel_pat0_data_match_r | + idel_pat1_data_match_r; + end + + //assign idel_pat_data_match = idel_pat0_data_match_r | + // idel_pat1_data_match_r; + + always @(posedge clk) + idel_pat_data_match_r <= #TCQ idel_pat_data_match; + + // Combine pattern match "subterms" for DQS-PHASER_IN stage + always @(posedge clk) begin + pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r; + pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r; + pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r; + pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r; + pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r && + pat0_match_fall0_and_r && + pat0_match_rise1_and_r && + pat0_match_fall1_and_r); + end + + always @(posedge clk) begin + pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; + pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; + pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; + pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; + pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && + pat1_match_fall0_and_r && + pat1_match_rise1_and_r && + pat1_match_fall1_and_r); + end + + assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r; + + end + + endgenerate + + + always @(posedge clk) begin + rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start; + mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r; + mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1; + mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start; + end + + //*************************************************************************** + // First stage calibration: Capture clock + //*************************************************************************** + + //***************************************************************** + // Keep track of how many samples have been written to shift registers + // Every time RD_SHIFT_LEN samples have been written, then we have a + // full read training pattern loaded into the sr_* registers. Then assert + // sr_valid_r to indicate that: (1) comparison between the sr_* and + // old_sr_* and prev_sr_* registers can take place, (2) transfer of + // the contents of sr_* to old_sr_* and prev_sr_* registers can also + // take place + //***************************************************************** +// verilint STARC-2.2.3.3 off + always @(posedge clk) + if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin + cnt_shift_r <= #TCQ 'b1; + sr_valid_r <= #TCQ 1'b0; + mpr_valid_r <= #TCQ 1'b0; + end else begin + if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin + if (cnt_shift_r == 'b0) + mpr_valid_r <= #TCQ 1'b1; + else begin + mpr_valid_r <= #TCQ 1'b0; + cnt_shift_r <= #TCQ cnt_shift_r + 1; + end + end else + mpr_valid_r <= #TCQ 1'b0; + + if (mux_rd_valid_r && rdlvl_stg1_start) begin + if (cnt_shift_r == RD_SHIFT_LEN-1) begin + sr_valid_r <= #TCQ 1'b1; + cnt_shift_r <= #TCQ 'b0; + end else begin + sr_valid_r <= #TCQ 1'b0; + cnt_shift_r <= #TCQ cnt_shift_r + 1; + end + end else + // When the current mux_rd_* contents are not valid, then + // retain the current value of cnt_shift_r, and make sure + // that sr_valid_r = 0 to prevent any downstream loads or + // comparisons + sr_valid_r <= #TCQ 1'b0; + end +// verilint STARC-2.2.3.3 on + //***************************************************************** + // Logic to determine when either edge of the data eye encountered + // Pre- and post-IDELAY update data pattern is compared, if they + // differ, than an edge has been encountered. Currently no attempt + // made to determine if the data pattern itself is "correct", only + // whether it changes after incrementing the IDELAY (possible + // future enhancement) + //***************************************************************** + + // One-way control for ensuring that state machine request to store + // current read data into OLD SR shift register only occurs on a + // valid clock cycle. The FSM provides a one-cycle request pulse. + // It is the responsibility of the FSM to wait the worst-case time + // before relying on any downstream results of this load. + always @(posedge clk) + if (rst) + store_sr_r <= #TCQ 1'b0; + else begin + if (store_sr_req_r) + store_sr_r <= #TCQ 1'b1; + else if ((sr_valid_r || mpr_valid_r) && store_sr_r) + store_sr_r <= #TCQ 1'b0; + end + + // Transfer current data to old data, prior to incrementing delay + // Also store data from current sampling window - so that we can detect + // if the current delay tap yields data that is "jittery" + generate + if (nCK_PER_CLK == 4) begin: gen_old_sr_div4 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr + always @(posedge clk) begin + if (sr_valid_r || mpr_valid_r) begin + // Load last sample (i.e. from current sampling interval) + prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; + prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; + prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; + prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; + end + if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin + old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z]; + old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z]; + old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z]; + old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z]; + end + end + end + end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr + always @(posedge clk) begin + if (sr_valid_r || mpr_valid_r) begin + prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + end + if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin + old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z]; + old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z]; + old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z]; + old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z]; + end + end + end + end + endgenerate + + //******************************************************* + // Match determination occurs over 3 cycles - pipelined for better timing + //******************************************************* + + // Match valid with # of cycles of pipelining in match determination + always @(posedge clk) begin + sr_valid_r1 <= #TCQ sr_valid_r; + sr_valid_r2 <= #TCQ sr_valid_r1; + mpr_valid_r1 <= #TCQ mpr_valid_r; + mpr_valid_r2 <= #TCQ mpr_valid_r1; + end + + generate + if (nCK_PER_CLK == 4) begin: gen_sr_match_div4 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match + always @(posedge clk) begin + // CYCLE1: Compare all bits in DQS grp, generate separate term for + // each bit over four bit times. For example, if there are 8-bits + // per DQS group, 32 terms are generated on cycle 1 + // NOTE: Structure HDL such that X on data bus will result in a + // mismatch. This is required for memory models that can drive the + // bus with X's to model uncertainty regions (e.g. Denali) + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) + old_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; + else + old_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) + old_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; + else + old_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) + old_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; + else + old_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) + old_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; + else + old_sr_match_fall1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z])) + old_sr_match_rise2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z]; + else + old_sr_match_rise2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z])) + old_sr_match_fall2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z]; + else + old_sr_match_fall2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z])) + old_sr_match_rise3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z]; + else + old_sr_match_rise3_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z])) + old_sr_match_fall3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z]; + else + old_sr_match_fall3_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) + prev_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; + else + prev_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) + prev_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; + else + prev_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) + prev_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; + else + prev_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) + prev_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; + else + prev_sr_match_fall1_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z])) + prev_sr_match_rise2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z]; + else + prev_sr_match_rise2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z])) + prev_sr_match_fall2_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z]; + else + prev_sr_match_fall2_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z])) + prev_sr_match_rise3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z]; + else + prev_sr_match_rise3_r[z] <= #TCQ 1'b0; + + if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z])) + prev_sr_match_fall3_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z]; + else + prev_sr_match_fall3_r[z] <= #TCQ 1'b0; + + // CYCLE2: Combine all the comparisons for every 8 words (rise0, + // fall0,rise1, fall1) in the calibration sequence. Now we're down + // to DRAM_WIDTH terms + old_sr_match_cyc2_r[z] <= #TCQ + old_sr_match_rise0_r[z] & + old_sr_match_fall0_r[z] & + old_sr_match_rise1_r[z] & + old_sr_match_fall1_r[z] & + old_sr_match_rise2_r[z] & + old_sr_match_fall2_r[z] & + old_sr_match_rise3_r[z] & + old_sr_match_fall3_r[z]; + prev_sr_match_cyc2_r[z] <= #TCQ + prev_sr_match_rise0_r[z] & + prev_sr_match_fall0_r[z] & + prev_sr_match_rise1_r[z] & + prev_sr_match_fall1_r[z] & + prev_sr_match_rise2_r[z] & + prev_sr_match_fall2_r[z] & + prev_sr_match_rise3_r[z] & + prev_sr_match_fall3_r[z]; + + // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), + // and qualify with pipelined valid signal) - probably don't need + // a cycle just do do this.... + if (sr_valid_r2 || mpr_valid_r2) begin + old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; + prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; + end else begin + old_sr_diff_r[z] <= #TCQ 'b0; + prev_sr_diff_r[z] <= #TCQ 'b0; + end + end + end + end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2 + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match + always @(posedge clk) begin + if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z])) + old_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z]; + else + old_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z])) + old_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z]; + else + old_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z])) + old_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z]; + else + old_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z])) + old_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z]; + else + old_sr_match_fall1_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z])) + prev_sr_match_rise0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z]; + else + prev_sr_match_rise0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z])) + prev_sr_match_fall0_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z]; + else + prev_sr_match_fall0_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z])) + prev_sr_match_rise1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z]; + else + prev_sr_match_rise1_r[z] <= #TCQ 1'b0; + + if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z])) + prev_sr_match_fall1_r[z] <= #TCQ 1'b1; + else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r) + prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z]; + else + prev_sr_match_fall1_r[z] <= #TCQ 1'b0; + + old_sr_match_cyc2_r[z] <= #TCQ + old_sr_match_rise0_r[z] & + old_sr_match_fall0_r[z] & + old_sr_match_rise1_r[z] & + old_sr_match_fall1_r[z]; + prev_sr_match_cyc2_r[z] <= #TCQ + prev_sr_match_rise0_r[z] & + prev_sr_match_fall0_r[z] & + prev_sr_match_rise1_r[z] & + prev_sr_match_fall1_r[z]; + + // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen), + // and qualify with pipelined valid signal) - probably don't need + // a cycle just do do this.... + if (sr_valid_r2 || mpr_valid_r2) begin + old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z]; + prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z]; + end else begin + old_sr_diff_r[z] <= #TCQ 'b0; + prev_sr_diff_r[z] <= #TCQ 'b0; + end + end + end + end + endgenerate + + //*************************************************************************** + // First stage calibration: DQS Capture + //*************************************************************************** + + + //******************************************************* + // Counters for tracking # of samples compared + // For each comparision point (i.e. to determine if an edge has + // occurred after each IODELAY increment when read leveling), + // multiple samples are compared in order to average out the effects + // of jitter. If any one of these samples is different than the "old" + // sample corresponding to the previous IODELAY value, then an edge + // is declared to be detected. + //******************************************************* + + // Two cascaded counters are used to keep track of # of samples compared, + // in order to make it easier to meeting timing on these paths. Once + // optimal sampling interval is determined, it may be possible to remove + // the second counter + always @(posedge clk) + samp_edge_cnt0_en_r <= #TCQ + (cal1_state_r == CAL1_PAT_DETECT) || + (cal1_state_r == CAL1_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); + + // First counter counts # of samples compared + always @(posedge clk) + if (rst) + samp_edge_cnt0_r <= #TCQ 'b0; + else begin + if (!samp_edge_cnt0_en_r) + // Reset sample counter when not in any of the "sampling" states + samp_edge_cnt0_r <= #TCQ 'b0; + else if (sr_valid_r2 || mpr_valid_r2) + // Otherwise, count # of samples compared + samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1; + end + + // Counter #2 enable generation + always @(posedge clk) + if (rst) + samp_edge_cnt1_en_r <= #TCQ 1'b0; + else begin + // Assert pulse when correct number of samples compared + if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) && + (sr_valid_r2 || mpr_valid_r2)) + samp_edge_cnt1_en_r <= #TCQ 1'b1; + else + samp_edge_cnt1_en_r <= #TCQ 1'b0; + end + + // Counter #2 + always @(posedge clk) + if (rst) + samp_edge_cnt1_r <= #TCQ 'b0; + else + if (!samp_edge_cnt0_en_r) + samp_edge_cnt1_r <= #TCQ 'b0; + else if (samp_edge_cnt1_en_r) + samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1; + + always @(posedge clk) + if (rst) + samp_cnt_done_r <= #TCQ 1'b0; + else begin + if (!samp_edge_cnt0_en_r) + samp_cnt_done_r <= #TCQ 'b0; + else if ((SIM_CAL_OPTION == "FAST_CAL") || + (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin + if (samp_edge_cnt0_r == SR_VALID_DELAY-1) + // For simulation only, stay in edge detection mode a minimum + // amount of time - just enough for two data compares to finish + samp_cnt_done_r <= #TCQ 1'b1; + end else begin + if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1) + samp_cnt_done_r <= #TCQ 1'b1; + end + end + + //***************************************************************** + // Logic to keep track of (on per-bit basis): + // 1. When a region of stability preceded by a known edge occurs + // 2. If for the current tap, the read data jitters + // 3. If an edge occured between the current and previous tap + // 4. When the current edge detection/sampling interval can end + // Essentially, these are a series of status bits - the stage 1 + // calibration FSM monitors these to determine when an edge is + // found. Additional information is provided to help the FSM + // determine if a left or right edge has been found. + //**************************************************************** + + assign pb_detect_edge_setup + = (cal1_state_r == CAL1_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) || + (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT); + + assign pb_detect_edge + = (cal1_state_r == CAL1_PAT_DETECT) || + (cal1_state_r == CAL1_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE) || + (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ); + + generate + for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge + always @(posedge clk) begin + if (pb_detect_edge_setup) begin + // Reset eye size, stable eye marker, and jitter marker before + // starting new edge detection iteration + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_detect_edge_done_r[z] <= #TCQ 1'b0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_last_tap_jitter_r[z] <= #TCQ 1'b0; + pb_found_edge_last_r[z] <= #TCQ 1'b0; + pb_found_edge_r[z] <= #TCQ 1'b0; + pb_found_first_edge_r[z] <= #TCQ 1'b0; + end else if (pb_detect_edge) begin + // Save information on which DQ bits are already out of the + // data valid window - those DQ bits will later not have their + // IDELAY tap value incremented + pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z]; + + if (!pb_detect_edge_done_r[z]) begin + if (samp_cnt_done_r) begin + // If we've reached end of sampling interval, no jitter on + // current tap has been found (although an edge could have + // been found between the current and previous taps), and + // the sampling interval is complete. Increment the stable + // eye counter if no edge found, and always clear the jitter + // flag in preparation for the next tap. + pb_last_tap_jitter_r[z] <= #TCQ 1'b0; + pb_detect_edge_done_r[z] <= #TCQ 1'b1; + if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin + // If the data was completely stable during this tap and + // no edge was found between this and the previous tap + // then increment the stable eye counter "as appropriate" + if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1) + pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1; + else //if (pb_found_first_edge_r[z]) + // We've reached minimum stable eye width + pb_found_stable_eye_r[z] <= #TCQ 1'b1; + end else begin + // Otherwise, an edge was found, either because of a + // difference between this and the previous tap's read + // data, and/or because the previous tap's data jittered + // (but not the current tap's data), then just set the + // edge found flag, and enable the stable eye counter + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_found_edge_r[z] <= #TCQ 1'b1; + pb_detect_edge_done_r[z] <= #TCQ 1'b1; + end + end else if (prev_sr_diff_r[z]) begin + // If we find that the current tap read data jitters, then + // set edge and jitter found flags, "enable" the eye size + // counter, and stop sampling interval for this bit + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_last_tap_jitter_r[z] <= #TCQ 1'b1; + pb_found_edge_r[z] <= #TCQ 1'b1; + pb_found_first_edge_r[z] <= #TCQ 1'b1; + pb_detect_edge_done_r[z] <= #TCQ 1'b1; + end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin + // If either an edge was found (i.e. difference between + // current tap and previous tap read data), or the previous + // tap exhibited jitter (which means by definition that the + // current tap cannot match the previous tap because the + // previous tap gave unstable data), then set the edge found + // flag, and "enable" eye size counter. But do not stop + // sampling interval - we still need to check if the current + // tap exhibits jitter + pb_cnt_eye_size_r[z] <= #TCQ 5'd0; + pb_found_stable_eye_r[z] <= #TCQ 1'b0; + pb_found_edge_r[z] <= #TCQ 1'b1; + pb_found_first_edge_r[z] <= #TCQ 1'b1; + end + end + end else begin + // Before every edge detection interval, reset "intra-tap" flags + pb_found_edge_r[z] <= #TCQ 1'b0; + pb_detect_edge_done_r[z] <= #TCQ 1'b0; + end + end + end + endgenerate + + // Combine the above per-bit status flags into combined terms when + // performing deskew on the aggregate data window + always @(posedge clk) begin + detect_edge_done_r <= #TCQ &pb_detect_edge_done_r; + found_edge_r <= #TCQ |pb_found_edge_r; + found_edge_all_r <= #TCQ &pb_found_edge_r; + found_stable_eye_r <= #TCQ &pb_found_stable_eye_r; + end + + // last IODELAY "stable eye" indicator is updated only after + // detect_edge_done_r is asserted - so that when we do find the "right edge" + // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1 + // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates + // immediately, then it never possible to have found_stable_eye_r = 1 + // when we detect an edge - and we'll never know whether we've found + // a "right edge") + always @(posedge clk) + if (pb_detect_edge_setup) + found_stable_eye_last_r <= #TCQ 1'b0; + else if (detect_edge_done_r) + found_stable_eye_last_r <= #TCQ found_stable_eye_r; + + //***************************************************************** + // Keep track of DQ IDELAYE2 taps used + //***************************************************************** + + // Added additional register stage to improve timing + always @(posedge clk) + if (rst) + idelay_tap_cnt_slice_r <= 5'h0; + else + idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; + + always @(posedge clk) + if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r + for (s = 0; s < RANKS; s = s + 1) begin + for (t = 0; t < DQS_WIDTH; t = t + 1) begin + idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val; + end + end + end else if (SIM_CAL_OPTION == "FAST_CAL") begin + for (u = 0; u < RANKS; u = u + 1) begin + for (w = 0; w < DQS_WIDTH; w = w + 1) begin + if (cal1_dq_idel_ce) begin + if (cal1_dq_idel_inc) + idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1; + else + idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1; + end + end + end + end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) && + rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin + for (f = 0; f < DQS_WIDTH; f = f + 1) begin + idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f]; + end + end else if (cal1_dq_idel_ce) begin + if (cal1_dq_idel_inc) + idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1; + else + idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1; + end else if (idelay_ld) + idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000; + + always @(posedge clk) + if (rst || new_cnt_cpt_r) + idelay_tap_limit_r <= #TCQ 1'b0; + else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31) + idelay_tap_limit_r <= #TCQ 1'b1; + + //***************************************************************** + // keep track of edge tap counts found, and current capture clock + // tap count + //***************************************************************** + + always @(posedge clk) + if (rst || new_cnt_cpt_r || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + tap_cnt_cpt_r <= #TCQ 'b0; + else if (cal1_dlyce_cpt_r) begin + if (cal1_dlyinc_cpt_r) + tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1; + else if (tap_cnt_cpt_r != 'd0) + tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1; + end + + always @(posedge clk) + if (rst || new_cnt_cpt_r || + (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) || + (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2)) + tap_limit_cpt_r <= #TCQ 1'b0; + else if (tap_cnt_cpt_r == 6'd63) + tap_limit_cpt_r <= #TCQ 1'b1; + + always @(posedge clk) + cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r; + + assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r}; + + // Storing DQS tap values at the end of each DQS read leveling + always @(posedge clk) begin + if (rst) begin + for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop + for (b = 0; b < DQS_WIDTH; b = b + 1) + rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0; + end + end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin + for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt + for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt + rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r; + end + end + end else if (SIM_CAL_OPTION == "SKIP_CAL") begin + for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt + for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt + rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31; + end + end + end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin + rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r; + end + end + + + // Counter to track maximum DQ IODELAY tap usage during the per-bit + // deskew portion of stage 1 calibration + always @(posedge clk) + if (rst) begin + idel_tap_cnt_dq_pb_r <= #TCQ 'b0; + idel_tap_limit_dq_pb_r <= #TCQ 1'b0; + end else + if (new_cnt_cpt_r) begin + idel_tap_cnt_dq_pb_r <= #TCQ 'b0; + idel_tap_limit_dq_pb_r <= #TCQ 1'b0; + end else if (|cal1_dlyce_dq_r) begin + if (cal1_dlyinc_dq_r) + idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1; + else + idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1; + + if (idel_tap_cnt_dq_pb_r == 31) + idel_tap_limit_dq_pb_r <= #TCQ 1'b1; + else + idel_tap_limit_dq_pb_r <= #TCQ 1'b0; + end + + + //***************************************************************** + + always @(posedge clk) begin + cal1_state_r1 <= #TCQ cal1_state_r; + cal1_state_r2 <= #TCQ cal1_state_r1; + cal1_state_r3 <= #TCQ cal1_state_r2; + end + + always @(posedge clk) + if (rst) begin + cal1_cnt_cpt_r <= #TCQ 'b0; + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + cal1_prech_req_r <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_IDLE; + cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx; + found_first_edge_r <= #TCQ 1'b0; + found_second_edge_r <= #TCQ 1'b0; + right_edge_taps_r <= #TCQ 6'b000000; + first_edge_taps_r <= #TCQ 6'bxxxxxx; + new_cnt_cpt_r <= #TCQ 1'b0; + rdlvl_stg1_done_int <= #TCQ 1'b0; + rdlvl_stg1_err <= #TCQ 1'b0; + second_edge_taps_r <= #TCQ 6'bxxxxxx; + store_sr_req_pulsed_r <= #TCQ 1'b0; + store_sr_req_r <= #TCQ 1'b0; + rnk_cnt_r <= #TCQ 2'b00; + rdlvl_rank_done_r <= #TCQ 1'b0; + idel_dec_cnt <= #TCQ 'd0; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + idel_pat_detect_valid_r <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + idel_adj_inc <= #TCQ 1'b0; + if (OCAL_EN == "ON") + mpr_rdlvl_done_r <= #TCQ 1'b0; + else + mpr_rdlvl_done_r <= #TCQ 1'b1; + mpr_dec_cpt_r <= #TCQ 1'b0; + rdlvl_pi_incdec <= #TCQ 1'b0; + end else begin + // default (inactive) states for all "pulse" outputs + // verilint STARC-2.2.3.3 off + cal1_prech_req_r <= #TCQ 1'b0; + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + new_cnt_cpt_r <= #TCQ 1'b0; + store_sr_req_pulsed_r <= #TCQ 1'b0; + store_sr_req_r <= #TCQ 1'b0; + + case (cal1_state_r) + + CAL1_IDLE: begin + rdlvl_rank_done_r <= #TCQ 1'b0; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin + rdlvl_pi_incdec <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; + end else begin + rdlvl_pi_incdec <= #TCQ 1'b1; + if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin + if (SIM_CAL_OPTION == "SKIP_CAL") + cal1_state_r <= #TCQ CAL1_REGL_LOAD; + else if (SIM_CAL_OPTION == "FAST_CAL") + cal1_state_r <= #TCQ CAL1_NEXT_DQS; + else begin + new_cnt_cpt_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; + end + end + end + end + + CAL1_MPR_NEW_DQS_WAIT: begin + cal1_prech_req_r <= #TCQ 1'b0; + if (!cal1_wait_r && mpr_valid_r) + cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; + end + + // Wait for the new DQS group to change + // also gives time for the read data IN_FIFO to + // output the updated data for the new DQS group + CAL1_NEW_DQS_WAIT: begin + rdlvl_rank_done_r <= #TCQ 1'b0; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + cal1_prech_req_r <= #TCQ 1'b0; + if (|pi_counter_read_val) begin //VK_REVIEW + mpr_dec_cpt_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val; + rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed + end else if (!cal1_wait_r) begin + rdlvl_pi_incdec <= #TCQ 1'b0; + + // Store "previous tap" read data. Technically there is no + // "previous" read data, since we are starting a new DQS + // group, so we'll never find an edge at tap 0 unless the + // data is fluctuating/jittering + store_sr_req_r <= #TCQ 1'b1; + // If per-bit deskew is disabled, then skip the first + // portion of stage 1 calibration + if (PER_BIT_DESKEW == "OFF") + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + else if (PER_BIT_DESKEW == "ON") + cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT; + end else + rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed + end + //***************************************************************** + // Per-bit deskew states + //***************************************************************** + + // Wait state following storage of initial read data + CAL1_PB_STORE_FIRST_WAIT: + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; + + // Look for an edge on all DQ bits in current DQS group + CAL1_PB_DETECT_EDGE: + if (detect_edge_done_r) begin + if (found_stable_eye_r) begin + // If we've found the left edge for all bits (or more precisely, + // we've found the left edge, and then part of the stable + // window thereafter), then proceed to positioning the CPT clock + // right before the left margin + cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT; + end else begin + // If we've reached the end of the sampling time, and haven't + // yet found the left margin of all the DQ bits, then: + if (!tap_limit_cpt_r) begin + // If we still have taps left to use, then store current value + // of read data, increment the capture clock, and continue to + // look for (left) edges + store_sr_req_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_PB_INC_CPT; + end else begin + // If we ran out of taps moving the capture clock, and we + // haven't finished edge detection, then reset the capture + // clock taps to 0 (gradually, one tap at a time... + // then exit the per-bit portion of the algorithm - + // i.e. proceed to adjust the capture clock and DQ IODELAYs as + cnt_idel_dec_cpt_r <= #TCQ 6'd63; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; + end + end + end + + // Increment delay for DQS + CAL1_PB_INC_CPT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT; + end + + // Wait for IODELAY for both capture and internal nodes within + // ISERDES to settle, before checking again for an edge + CAL1_PB_INC_CPT_WAIT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) begin + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE; + + end + end + // We've found the left edges of the windows for all DQ bits + // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture + // clock IDELAY to position just outside left edge of data window + CAL1_PB_DEC_CPT_LEFT: + if (cnt_idel_dec_cpt_r == 6'b000000) + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT; + else begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; + end + + CAL1_PB_DEC_CPT_LEFT_WAIT: + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; + + // If there is skew between individual DQ bits, then after we've + // positioned the CPT clock, we will be "in the window" for some + // DQ bits ("early" DQ bits), and "out of the window" for others + // ("late" DQ bits). Increase DQ taps until we are out of the + // window for all DQ bits + CAL1_PB_DETECT_EDGE_DQ: + if (detect_edge_done_r) + if (found_edge_all_r) begin + // We're out of the window for all DQ bits in this DQS group + // We're done with per-bit deskew for this group - now decr + // capture clock IODELAY tap count back to 0, and proceed + // with the rest of stage 1 calibration for this DQS group + cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; + end else + if (!idel_tap_limit_dq_pb_r) + // If we still have DQ taps available for deskew, keep + // incrementing IODELAY tap count for the appropriate DQ bits + cal1_state_r <= #TCQ CAL1_PB_INC_DQ; + else begin + // Otherwise, stop immediately (we've done the best we can) + // and proceed with rest of stage 1 calibration + cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r; + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT; + end + + CAL1_PB_INC_DQ: begin + // Increment only those DQ for which an edge hasn't been found yet + cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r; + cal1_dlyinc_dq_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT; + end + + CAL1_PB_INC_DQ_WAIT: + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ; + + // Decrement capture clock taps back to initial value + CAL1_PB_DEC_CPT: + if (cnt_idel_dec_cpt_r == 6'b000000) + cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT; + else begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; + end + + // Wait for capture clock to settle, then proceed to rest of + // state 1 calibration for this DQS group + CAL1_PB_DEC_CPT_WAIT: + if (!cal1_wait_r) begin + store_sr_req_r <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + end + + // When first starting calibration for a DQS group, save the + // current value of the read data shift register, and use this + // as a reference. Note that for the first iteration of the + // edge detection loop, we will in effect be checking for an edge + // at IODELAY taps = 0 - normally, we are comparing the read data + // for IODELAY taps = N, with the read data for IODELAY taps = N-1 + // An edge can only be found at IODELAY taps = 0 if the read data + // is changing during this time (possible due to jitter) + CAL1_STORE_FIRST_WAIT: begin + mpr_dec_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_PAT_DETECT; + end + + CAL1_VALID_WAIT: begin + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; + end + + CAL1_MPR_PAT_DETECT: begin + rdlvl_pi_incdec <= #TCQ 1'b0; + // MPR read leveling for centering DQS in valid window before + // OCLKDELAYED calibration begins in order to eliminate read issues + if (idel_pat_detect_valid_r == 1'b0) begin + cal1_state_r <= #TCQ CAL1_VALID_WAIT; + idel_pat_detect_valid_r <= #TCQ 1'b1; + end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + idel_dec_cnt <= #TCQ 'd0; + end else if (!idelay_tap_limit_r) + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; + else + cal1_state_r <= #TCQ CAL1_RDLVL_ERR; + end + + CAL1_PAT_DETECT: begin + // All DQ bits associated with a DQS are pushed to the right one IDELAY + // tap at a time until first rising DQS is in the tri-state region + // before first rising edge window. + // The detect_edge_done_r condition included to support averaging + // during IDELAY tap increments + rdlvl_pi_incdec <= #TCQ 1'b0; + if (detect_edge_done_r) begin + if (idel_pat_data_match) begin + case (idelay_adj) + 2'b01: begin + cal1_state_r <= CAL1_DQ_IDEL_TAP_INC; + idel_dec_cnt <= #TCQ 5'd0; + idel_adj_inc <= #TCQ 1'b1; + end + 2'b10: begin //DEC by 1 + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ; + idel_dec_cnt <= #TCQ 5'd1; + idel_adj_inc <= #TCQ 1'b0; + end + default: begin + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + idel_dec_cnt <= #TCQ 5'd0; + idel_adj_inc <= #TCQ 1'b0; + end + endcase + end else if (!idelay_tap_limit_r) begin + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC; + end else begin + cal1_state_r <= #TCQ CAL1_RDLVL_ERR; + end + end + end + + // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated + // until left edge of valid window detected + CAL1_DQ_IDEL_TAP_INC: begin + cal1_dq_idel_ce <= #TCQ 1'b1; + cal1_dq_idel_inc <= #TCQ 1'b1; + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT; + idel_pat_detect_valid_r <= #TCQ 1'b0; + end + + CAL1_DQ_IDEL_TAP_INC_WAIT: begin + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + if (!cal1_wait_r) begin + idel_adj_inc <= #TCQ 1'b0; + if (idel_adj_inc) + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) + cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT; + else + cal1_state_r <= #TCQ CAL1_PAT_DETECT; + end + end + + // Decrement by 2 IDELAY taps once idel_pat_data_match detected + CAL1_DQ_IDEL_TAP_DEC: begin + cal1_dq_idel_inc <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT; + if (idel_dec_cnt >= 'd0) + cal1_dq_idel_ce <= #TCQ 1'b1; + else + cal1_dq_idel_ce <= #TCQ 1'b0; + if (idel_dec_cnt > 'd0) + idel_dec_cnt <= #TCQ idel_dec_cnt - 1; + else + idel_dec_cnt <= #TCQ idel_dec_cnt; + end + + CAL1_DQ_IDEL_TAP_DEC_WAIT: begin + cal1_dq_idel_ce <= #TCQ 1'b0; + cal1_dq_idel_inc <= #TCQ 1'b0; + if (!cal1_wait_r) begin + if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0)) + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; + else if (mpr_dec_cpt_r) + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + else + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + end + end + + // Check for presence of data eye edge. During this state, we + // sample the read data multiple times, and look for changes + // in the read data, specifically: + // 1. A change in the read data compared with the value of + // read data from the previous delay tap. This indicates + // that the most recent tap delay increment has moved us + // into either a new window, or moved/kept us in the + // transition/jitter region between windows. Note that this + // condition only needs to be checked for once, and for + // logistical purposes, we check this soon after entering + // this state (see comment in CAL1_DETECT_EDGE below for + // why this is done) + // 2. A change in the read data while we are in this state + // (i.e. in the absence of a tap delay increment). This + // indicates that we're close enough to a window edge that + // jitter will cause the read data to change even in the + // absence of a tap delay change + CAL1_DETECT_EDGE: begin + // Essentially wait for the first comparision to finish, then + // store current data into "old" data register. This store + // happens now, rather than later (e.g. when we've have already + // left this state) in order to avoid the situation the data that + // is stored as "old" data has not been used in an "active + // comparison" - i.e. data is stored after the last comparison + // of this state. In this case, we can miss an edge if the + // following sequence occurs: + // 1. Comparison completes in this state - no edge found + // 2. "Momentary jitter" occurs which "pushes" the data out the + // equivalent of one delay tap + // 3. We store this jittered data as the "old" data + // 4. "Jitter" no longer present + // 5. We increment the delay tap by one + // 6. Now we compare the current with the "old" data - they're + // the same, and no edge is detected + // NOTE: Given the large # of comparisons done in this state, it's + // highly unlikely the above sequence will occur in actual H/W + + // Wait for the first load of read data into the comparison + // shift register to finish, then load the current read data + // into the "old" data register. This allows us to do one + // initial comparision between the current read data, and + // stored data corresponding to the previous delay tap + idel_pat_detect_valid_r <= #TCQ 1'b0; + if (!store_sr_req_pulsed_r) begin + // Pulse store_sr_req_r only once in this state + store_sr_req_r <= #TCQ 1'b1; + store_sr_req_pulsed_r <= #TCQ 1'b1; + end else begin + store_sr_req_r <= #TCQ 1'b0; + store_sr_req_pulsed_r <= #TCQ 1'b1; + end + + // Continue to sample read data and look for edges until the + // appropriate time interval (shorter for simulation-only, + // much, much longer for actual h/w) has elapsed + if (detect_edge_done_r) begin + if (tap_limit_cpt_r) + // Only one edge detected and ran out of taps since only one + // bit time worth of taps available for window detection. This + // can happen if at tap 0 DQS is in previous window which results + // in only left edge being detected. Or at tap 0 DQS is in the + // current window resulting in only right edge being detected. + // Depending on the frequency this case can also happen if at + // tap 0 DQS is in the left noise region resulting in only left + // edge being detected. + cal1_state_r <= #TCQ CAL1_CALC_IDEL; + else if (found_edge_r) begin + // Sticky bit - asserted after we encounter an edge, although + // the current edge may not be considered the "first edge" this + // just means we found at least one edge + found_first_edge_r <= #TCQ 1'b1; + + // Only the right edge of the data valid window is found + // Record the inner right edge tap value + if (!found_first_edge_r && found_stable_eye_last_r) begin + if (tap_cnt_cpt_r == 'd0) + right_edge_taps_r <= #TCQ 'd0; + else + right_edge_taps_r <= #TCQ tap_cnt_cpt_r; + end + + // Both edges of data valid window found: + // If we've found a second edge after a region of stability + // then we must have just passed the second ("right" edge of + // the window. Record this second_edge_taps = current tap-1, + // because we're one past the actual second edge tap, where + // the edge taps represent the extremes of the data valid + // window (i.e. smallest & largest taps where data still valid + if (found_first_edge_r && found_stable_eye_last_r) begin + found_second_edge_r <= #TCQ 1'b1; + second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1; + cal1_state_r <= #TCQ CAL1_CALC_IDEL; + end else begin + // Otherwise, an edge was found (just not the "second" edge) + // Assuming DQS is in the correct window at tap 0 of Phaser IN + // fine tap. The first edge found is the right edge of the valid + // window and is the beginning of the jitter region hence done! + first_edge_taps_r <= #TCQ tap_cnt_cpt_r; + //wait for read stop before PI increament + cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC; + end + end else + // Otherwise, if we haven't found an edge.... + // If we still have taps left to use, then keep incrementing + //wait for read stop before PI increament + cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC; + end + end + + //before increment PI, read command sending should be stopped. + //Also need to wait existing read is finished + CAL1_RD_STOP_FOR_PI_INC: begin + rdlvl_pi_incdec <= #TCQ 1'b1; + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT; + end + + // Increment Phaser_IN delay for DQS + CAL1_IDEL_INC_CPT: begin + cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT; + if (~tap_limit_cpt_r) begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b1; + end else begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + end + end + + // Wait for Phaser_In to settle, before checking again for an edge + CAL1_IDEL_INC_CPT_WAIT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) begin + cal1_state_r <= #TCQ CAL1_DETECT_EDGE; + rdlvl_pi_incdec <= #TCQ 1'b0; //return to normal read + end + end + + // Calculate final value of Phaser_IN taps. At this point, one or both + // edges of data eye have been found, and/or all taps have been + // exhausted looking for the edges + // NOTE: We're calculating the amount to decrement by, not the + // absolute setting for DQS. + CAL1_CALC_IDEL: begin + // CASE1: If 2 edges found. + if (found_second_edge_r) + cnt_idel_dec_cpt_r + <= #TCQ ((second_edge_taps_r - + first_edge_taps_r)>>1) + 1; + else if (right_edge_taps_r > 6'd0) + // Only right edge detected + // right_edge_taps_r is the inner right edge tap value + // hence used for calculation + cnt_idel_dec_cpt_r + <= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1)); + else if (found_first_edge_r) + // Only left edge detected + cnt_idel_dec_cpt_r + <= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1); + else + cnt_idel_dec_cpt_r + <= #TCQ (tap_cnt_cpt_r>>1); + // Now use the value we just calculated to decrement CPT taps + // to the desired calibration point + //cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + cal1_state_r <= #TCQ CAL1_CENTER_WAIT; + rdlvl_pi_incdec <= #TCQ 1'b1; + end + + CAL1_CENTER_WAIT: begin + if(!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + end + // decrement capture clock for final adjustment - center + // capture clock in middle of data eye. This adjustment will occur + // only when both the edges are found usign CPT taps. Must do this + // incrementally to avoid clock glitching (since CPT drives clock + // divider within each ISERDES) + CAL1_IDEL_DEC_CPT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b1; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + // once adjustment is complete, we're done with calibration for + // this DQS, repeat for next DQS + cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1; + if (cnt_idel_dec_cpt_r == 6'b000001) begin + if (mpr_dec_cpt_r) begin + if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin + idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]; + cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC; + end else + cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT; + end else + cal1_state_r <= #TCQ CAL1_NEXT_DQS; + end else + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT; + end + + CAL1_IDEL_DEC_CPT_WAIT: begin + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + if (!cal1_wait_r) + cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT; + end + + // Determine whether we're done, or have more DQS's to calibrate + // Also request precharge after every byte, as appropriate + CAL1_NEXT_DQS: begin + //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2")) + cal1_prech_req_r <= #TCQ 1'b1; + //else + // cal1_prech_req_r <= #TCQ 1'b0; + cal1_dlyce_cpt_r <= #TCQ 1'b0; + cal1_dlyinc_cpt_r <= #TCQ 1'b0; + // Prepare for another iteration with next DQS group + found_first_edge_r <= #TCQ 1'b0; + found_second_edge_r <= #TCQ 1'b0; + first_edge_taps_r <= #TCQ 'd0; + second_edge_taps_r <= #TCQ 'd0; + right_edge_taps_r <= #TCQ 'd0; + if ((SIM_CAL_OPTION == "FAST_CAL") || + (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin + if (mpr_rdlvl_done_r) begin + rdlvl_last_byte_done_int <= #TCQ 1'b1; + mpr_last_byte_done <= #TCQ 1'b0; + end else begin + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b1; + end + end + + // Wait until precharge that occurs in between calibration of + // DQS groups is finished + if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + //rdlvl_rank_done_r <= #TCQ 1'b1; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD; + end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin + if (~mpr_rdlvl_done_r) begin + mpr_rank_done_r <= #TCQ 1'b1; + // if (rnk_cnt_r == RANKS-1) begin + // All DQS groups in all ranks done + cal1_state_r <= #TCQ CAL1_DONE; + cal1_cnt_cpt_r <= #TCQ 'b0; + // end else begin + // // Process DQS groups in next rank + // rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + // new_cnt_cpt_r <= #TCQ 1'b1; + // cal1_cnt_cpt_r <= #TCQ 'b0; + // cal1_state_r <= #TCQ CAL1_IDLE; + // end + end else begin + // All DQS groups in a rank done + rdlvl_rank_done_r <= #TCQ 1'b1; + if (rnk_cnt_r == RANKS-1) begin + // All DQS groups in all ranks done + cal1_state_r <= #TCQ CAL1_REGL_LOAD; + end else begin + // Process DQS groups in next rank + rnk_cnt_r <= #TCQ rnk_cnt_r + 1; + new_cnt_cpt_r <= #TCQ 1'b1; + cal1_cnt_cpt_r <= #TCQ 'b0; + cal1_state_r <= #TCQ CAL1_IDLE; + end + end + end else begin + // Process next DQS group + new_cnt_cpt_r <= #TCQ 1'b1; + cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1; + cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT; + end + end + end + + CAL1_NEW_DQS_PREWAIT: begin + if (!cal1_wait_r) begin + rdlvl_pi_incdec <= #TCQ 1'b0; + if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3")) + cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT; + else + cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT; + end + end + + // Load rank registers in Phaser_IN + CAL1_REGL_LOAD: begin + rdlvl_rank_done_r <= #TCQ 1'b0; + mpr_rank_done_r <= #TCQ 1'b0; + cal1_prech_req_r <= #TCQ 1'b0; + cal1_cnt_cpt_r <= #TCQ 'b0; + rnk_cnt_r <= #TCQ 2'b00; + if ((regl_rank_cnt == RANKS-1) && + ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin + cal1_state_r <= #TCQ CAL1_DONE; + rdlvl_last_byte_done_int <= #TCQ 1'b0; + mpr_last_byte_done <= #TCQ 1'b0; + end else + cal1_state_r <= #TCQ CAL1_REGL_LOAD; + end + + CAL1_RDLVL_ERR: begin + rdlvl_stg1_err <= #TCQ 1'b1; + end + + // Done with this stage of calibration + // if used, allow DEBUG_PORT to control taps + CAL1_DONE: begin + mpr_rdlvl_done_r <= #TCQ 1'b1; + cal1_prech_req_r <= #TCQ 1'b0; + if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin + rdlvl_stg1_done_int <= #TCQ 1'b0; + cal1_state_r <= #TCQ CAL1_IDLE; + end else + rdlvl_stg1_done_int <= #TCQ 1'b1; + end + + endcase + end +// verilint STARC-2.2.3.3 on + + + + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v new file mode 100644 index 0000000..165ab38 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v @@ -0,0 +1,560 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : mig_7series_v4_2_ddr_phy_tempmon.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Dec 20 2013 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Monitors chip temperature via the XADC and adjusts the +// stage 2 tap values as appropriate. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_ddr_phy_tempmon # +( + parameter SKIP_CALIB = "FALSE", + parameter TCQ = 100, // Register delay (simulation only) + // Temperature bands must be in order. To disable bands, set to extreme. + parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100) + parameter TEMP_HYST = 1, + parameter TEMP_MIN_LIMIT = 12'h8ac, + parameter TEMP_MAX_LIMIT = 12'hca4 +) +( + input clk, // Fabric clock + input rst, // System reset + input calib_complete, // Calibration complete + input tempmon_sample_en, // Signal to enable sampling + input [11:0] device_temp, // Current device temperature + input [11:0] calib_device_temp, // Calibration device temperature + output tempmon_pi_f_inc, // Increment PHASER_IN taps + output tempmon_pi_f_dec, // Decrement PHASER_IN taps + output tempmon_sel_pi_incdec, // Assume control of PHASER_IN taps + output tempmon_done_skip +); + + // translate hysteresis into XADC units + localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504; + + localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ; + + // Temperature sampler FSM encoding + localparam IDLE = 11'b000_0000_0001; + localparam INIT = 11'b000_0000_0010; + localparam FOUR_INC = 11'b000_0000_0100; + localparam THREE_INC = 11'b000_0000_1000; + localparam TWO_INC = 11'b000_0001_0000; + localparam ONE_INC = 11'b000_0010_0000; + localparam NEUTRAL = 11'b000_0100_0000; + localparam ONE_DEC = 11'b000_1000_0000; + localparam TWO_DEC = 11'b001_0000_0000; + localparam THREE_DEC = 11'b010_0000_0000; + localparam FOUR_DEC = 11'b100_0000_0000; + + + //=========================================================================== + // Reg declarations + //=========================================================================== + + // Output port flops. Inc and dec are mutex. + reg pi_f_dec; // Flop output + reg pi_f_inc; // Flop output + reg pi_f_dec_nxt; // FSM output + reg pi_f_inc_nxt; // FSM output + + // FSM state + reg [10:0] tempmon_state; + reg [10:0] tempmon_state_nxt; + + // FSM output used to capture the initial device termperature + reg tempmon_state_init; + + // Flag to indicate the initial device temperature is captured and normal operation can begin + reg tempmon_init_complete; + + // Temperature band/state boundaries + reg [11:0] four_inc_max_limit; + reg [11:0] three_inc_max_limit; + reg [11:0] two_inc_max_limit; + reg [11:0] one_inc_max_limit; + reg [11:0] neutral_max_limit; + reg [11:0] one_dec_max_limit; + reg [11:0] two_dec_max_limit; + reg [11:0] three_dec_max_limit; + reg [11:0] three_inc_min_limit; + reg [11:0] two_inc_min_limit; + reg [11:0] one_inc_min_limit; + reg [11:0] neutral_min_limit; + reg [11:0] one_dec_min_limit; + reg [11:0] two_dec_min_limit; + reg [11:0] three_dec_min_limit; + reg [11:0] four_dec_min_limit; + reg [11:0] device_temp_init; + + // Flops for capturing and storing the current device temperature + reg tempmon_sample_en_101; + reg tempmon_sample_en_102; + reg [11:0] device_temp_101; + reg [11:0] device_temp_capture_102; + reg update_temp_102; + + // Flops for comparing temperature to max limits + reg temp_cmp_four_inc_max_102; + reg temp_cmp_three_inc_max_102; + reg temp_cmp_two_inc_max_102; + reg temp_cmp_one_inc_max_102; + reg temp_cmp_neutral_max_102; + reg temp_cmp_one_dec_max_102; + reg temp_cmp_two_dec_max_102; + reg temp_cmp_three_dec_max_102; + + // Flops for comparing temperature to min limits + reg temp_cmp_three_inc_min_102; + reg temp_cmp_two_inc_min_102; + reg temp_cmp_one_inc_min_102; + reg temp_cmp_neutral_min_102; + reg temp_cmp_one_dec_min_102; + reg temp_cmp_two_dec_min_102; + reg temp_cmp_three_dec_min_102; + reg temp_cmp_four_dec_min_102; + + reg calib_complete_r; + reg tempmon_done; + reg [2:0] sample_en_cnt; + + always @ (posedge clk) + calib_complete_r <= #TCQ calib_complete; + + wire [11:0] device_temp_in = ((tempmon_state_init | ~calib_complete_r) & (SKIP_CALIB == "TRUE")) ? calib_device_temp : device_temp; + + always @ (posedge clk) begin + if (rst) + sample_en_cnt <= #TCQ 'd0; + else if ((tempmon_sample_en & ~tempmon_sample_en_101) & ((SKIP_CALIB == "TRUE")) & (sample_en_cnt < 'd5)) + sample_en_cnt <= #TCQ sample_en_cnt + 1; + end + + always @ (posedge clk) begin + if (rst) + tempmon_done <= #TCQ 1'b0; + else if ((sample_en_cnt == 'd5) & ((SKIP_CALIB == "TRUE"))) + tempmon_done <= #TCQ 1'b1; + end + + assign tempmon_done_skip = tempmon_done; + + //=========================================================================== + // Overview and temperature band limits + //=========================================================================== + + // The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM + // has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or + // decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are + // offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state + // and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when + // the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above + // 125C will never be entered. + + // Temperature lowest highest + // <------------------------------------------------------------------------------------------------------------------------------------------------> + // + // Temp four three two one neutral one two three four + // band/state inc inc inc inc dec dec dec dec + // + // Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| + // Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| | + // | | | | | | | + // | | | | | | | + // three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit | + // | device_temp_init | + // four_inc_max_limit three_dec_max_limit + + + + // Boundaries for moving from lower temp bands to higher temp bands. + // Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C, + // and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range. + wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band + wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET; + wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET; + wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET; + wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band + wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET; + wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET; + wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band + wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0]; + + + // Boundaries for moving from higher temp bands to lower temp bands + wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band + wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET; + wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET; + wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band + wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET; + wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET; + wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET; + wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band + + + + //=========================================================================== + // Capture device temperature + //=========================================================================== + + // There is a three stage pipeline used to capture temperature, calculate the next state + // of the FSM, and update the tempmon outputs. + // + // Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped. + // Input device_temp is compared to ADC codes for 0C and 125C and limited + // at the flop input if needed. + // + // Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries + // to determine if a state change is needed. State changes are only enabled on the + // rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser + // increment or decrement signal is generated and flopped. + // + // Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs. + + // Limit device_temp to 0C to 125C and assign it to flop input device_temp_100 + // temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15 + wire device_temp_high = device_temp_in > TEMP_MAX_LIMIT; + wire device_temp_low = device_temp_in < TEMP_MIN_LIMIT; + wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT ) + | ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT ) + | ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp_in ); + + // Capture/hold the initial temperature used in setting temperature bands and set init complete flag + // to enable normal sample operation. + wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init; + wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete; + + // Capture/hold the current temperature on the sample enable signal rising edge after init is complete. + // The captured current temp is not used functionaly. It is just useful for debug and waveform review. + wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101; + wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102; + + + //=========================================================================== + // Generate FSM arc signals + //=========================================================================== + + // Temperature comparisons for increasing temperature. + wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ; + wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ; + wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ; + wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ; + wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ; + wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ; + wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ; + wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ; + + // Temperature comparisons for decreasing temperature. + wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ; + wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ; + wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ; + wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ; + wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ; + wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ; + wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ; + wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ; + + // FSM arcs for increasing temperature. + wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102; + wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102; + wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102; + wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102; + wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102; + wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102; + wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102; + wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102; + + // FSM arcs for decreasing temperature. + wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102; + wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102; + wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102; + wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102; + wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102; + wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102; + wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102; + wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102; + + + //=========================================================================== + // Implement FSM + //=========================================================================== + + // In addition to the nine temperature states, there are also IDLE and INIT states. + // The INIT state triggers the calculation of the temperature boundaries between the + // other states. After INIT, the FSM will always go to the NEUTRAL state. There is + // no timing restriction required between calib_complete and tempmon_sample_en. + + always @(*) begin + + tempmon_state_nxt = tempmon_state; + tempmon_state_init = 1'b0; + pi_f_inc_nxt = 1'b0; + pi_f_dec_nxt = 1'b0; + + casez (tempmon_state) + IDLE: begin + if (calib_complete) tempmon_state_nxt = INIT; + end + INIT: begin + tempmon_state_nxt = NEUTRAL; + tempmon_state_init = 1'b1; + end + FOUR_INC: begin + if (temp_gte_four_inc_max) begin + tempmon_state_nxt = THREE_INC; + pi_f_dec_nxt = 1'b1; + end + end + THREE_INC: begin + if (temp_gte_three_inc_max) begin + tempmon_state_nxt = TWO_INC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_three_inc_min) begin + tempmon_state_nxt = FOUR_INC; + pi_f_inc_nxt = 1'b1; + end + end + TWO_INC: begin + if (temp_gte_two_inc_max) begin + tempmon_state_nxt = ONE_INC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_two_inc_min) begin + tempmon_state_nxt = THREE_INC; + pi_f_inc_nxt = 1'b1; + end + end + ONE_INC: begin + if (temp_gte_one_inc_max) begin + tempmon_state_nxt = NEUTRAL; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_one_inc_min) begin + tempmon_state_nxt = TWO_INC; + pi_f_inc_nxt = 1'b1; + end + end + NEUTRAL: begin + if (temp_gte_neutral_max) begin + tempmon_state_nxt = ONE_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_neutral_min) begin + tempmon_state_nxt = ONE_INC; + pi_f_inc_nxt = 1'b1; + end + end + ONE_DEC: begin + if (temp_gte_one_dec_max) begin + tempmon_state_nxt = TWO_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_one_dec_min) begin + tempmon_state_nxt = NEUTRAL; + pi_f_inc_nxt = 1'b1; + end + end + TWO_DEC: begin + if (temp_gte_two_dec_max) begin + tempmon_state_nxt = THREE_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_two_dec_min) begin + tempmon_state_nxt = ONE_DEC; + pi_f_inc_nxt = 1'b1; + end + end + THREE_DEC: begin + if (temp_gte_three_dec_max) begin + tempmon_state_nxt = FOUR_DEC; + pi_f_dec_nxt = 1'b1; + end + else if (temp_lte_three_dec_min) begin + tempmon_state_nxt = TWO_DEC; + pi_f_inc_nxt = 1'b1; + end + end + FOUR_DEC: begin + if (temp_lte_four_dec_min) begin + tempmon_state_nxt = THREE_DEC; + pi_f_inc_nxt = 1'b1; + end + end + default: begin + tempmon_state_nxt = IDLE; + end + endcase + + end //always + +//synopsys translate_off +reg [71:0] tempmon_state_name; +always @(*) casez (tempmon_state) + IDLE : tempmon_state_name = "IDLE"; + INIT : tempmon_state_name = "INIT"; + FOUR_INC : tempmon_state_name = "FOUR_INC"; + THREE_INC : tempmon_state_name = "THREE_INC"; + TWO_INC : tempmon_state_name = "TWO_INC"; + ONE_INC : tempmon_state_name = "ONE_INC"; + NEUTRAL : tempmon_state_name = "NEUTRAL"; + ONE_DEC : tempmon_state_name = "ONE_DEC"; + TWO_DEC : tempmon_state_name = "TWO_DEC"; + THREE_DEC : tempmon_state_name = "THREE_DEC"; + FOUR_DEC : tempmon_state_name = "FOUR_DEC"; + default : tempmon_state_name = "BAD_STATE"; +endcase +//synopsys translate_on + + //=========================================================================== + // Generate final output and implement flops + //=========================================================================== + + // Generate output + assign tempmon_pi_f_inc = pi_f_inc; + assign tempmon_pi_f_dec = pi_f_dec; + assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec; + + + // Implement reset flops + always @(posedge clk) begin + if(rst) begin + tempmon_state <= #TCQ 11'b000_0000_0001; + pi_f_inc <= #TCQ 1'b0; + pi_f_dec <= #TCQ 1'b0; + four_inc_max_limit <= #TCQ 12'b0; + three_inc_max_limit <= #TCQ 12'b0; + two_inc_max_limit <= #TCQ 12'b0; + one_inc_max_limit <= #TCQ 12'b0; + neutral_max_limit <= #TCQ 12'b0; + one_dec_max_limit <= #TCQ 12'b0; + two_dec_max_limit <= #TCQ 12'b0; + three_dec_max_limit <= #TCQ 12'b0; + three_inc_min_limit <= #TCQ 12'b0; + two_inc_min_limit <= #TCQ 12'b0; + one_inc_min_limit <= #TCQ 12'b0; + neutral_min_limit <= #TCQ 12'b0; + one_dec_min_limit <= #TCQ 12'b0; + two_dec_min_limit <= #TCQ 12'b0; + three_dec_min_limit <= #TCQ 12'b0; + four_dec_min_limit <= #TCQ 12'b0; + device_temp_init <= #TCQ 12'b0; + tempmon_init_complete <= #TCQ 1'b0; + tempmon_sample_en_101 <= #TCQ 1'b0; + tempmon_sample_en_102 <= #TCQ 1'b0; + device_temp_101 <= #TCQ 12'b0; + device_temp_capture_102 <= #TCQ 12'b0; + end + else begin + tempmon_state <= #TCQ tempmon_state_nxt; + pi_f_inc <= #TCQ pi_f_inc_nxt; + pi_f_dec <= #TCQ pi_f_dec_nxt; + four_inc_max_limit <= #TCQ four_inc_max_limit_nxt; + three_inc_max_limit <= #TCQ three_inc_max_limit_nxt; + two_inc_max_limit <= #TCQ two_inc_max_limit_nxt; + one_inc_max_limit <= #TCQ one_inc_max_limit_nxt; + neutral_max_limit <= #TCQ neutral_max_limit_nxt; + one_dec_max_limit <= #TCQ one_dec_max_limit_nxt; + two_dec_max_limit <= #TCQ two_dec_max_limit_nxt; + three_dec_max_limit <= #TCQ three_dec_max_limit_nxt; + three_inc_min_limit <= #TCQ three_inc_min_limit_nxt; + two_inc_min_limit <= #TCQ two_inc_min_limit_nxt; + one_inc_min_limit <= #TCQ one_inc_min_limit_nxt; + neutral_min_limit <= #TCQ neutral_min_limit_nxt; + one_dec_min_limit <= #TCQ one_dec_min_limit_nxt; + two_dec_min_limit <= #TCQ two_dec_min_limit_nxt; + three_dec_min_limit <= #TCQ three_dec_min_limit_nxt; + four_dec_min_limit <= #TCQ four_dec_min_limit_nxt; + device_temp_init <= #TCQ device_temp_init_nxt; + tempmon_init_complete <= #TCQ tempmon_init_complete_nxt; + tempmon_sample_en_101 <= #TCQ tempmon_sample_en; + tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101; + device_temp_101 <= #TCQ device_temp_100; + device_temp_capture_102 <= #TCQ device_temp_capture_101; + end + end + + // Implement non-reset flops + always @(posedge clk) begin + temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101; + temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101; + temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101; + temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101; + temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101; + temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101; + temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101; + temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101; + temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101; + temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101; + temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101; + temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101; + temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101; + temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101; + temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101; + temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101; + update_temp_102 <= #TCQ update_temp_101; + end + + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v new file mode 100644 index 0000000..4e8793c --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v @@ -0,0 +1,1445 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 4.2 +// \ \ Application : MIG +// / / Filename : ddr_phy_top.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Aug 03 2009 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Top level memory interface block. Instantiates a clock +// and reset generator, the memory controller, the phy and +// the user interface blocks. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_ddr_phy_top # + ( + parameter TCQ = 100, // Register delay (simulation only) + parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3 + parameter AL = "0", // Additive Latency option + parameter BANK_WIDTH = 3, // # of bank bits + parameter BURST_MODE = "8", // Burst length + parameter BURST_TYPE = "SEQ", // Burst type + parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank + parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory + parameter CL = 5, + parameter COL_WIDTH = 12, // column address width + parameter CS_WIDTH = 1, // # of unique CS outputs + parameter CKE_WIDTH = 1, // # of cke outputs + parameter CWL = 5, + parameter DM_WIDTH = 8, // # of DM (data mask) + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_TYPE = "DDR3", + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides + parameter LP_DDR_CK_WIDTH = 2, + + // Hard PHY parameters + parameter PHYCTL_CMD_FIFO = "FALSE", + // five fields, one per possible I/O bank, 4 bits in each field, + // 1 per lane data=1/ctl=0 + parameter DATA_CTL_B0 = 4'hc, + parameter DATA_CTL_B1 = 4'hf, + parameter DATA_CTL_B2 = 4'hf, + parameter DATA_CTL_B3 = 4'hf, + parameter DATA_CTL_B4 = 4'hf, + // defines the byte lanes in I/O banks being used in the interface + // 1- Used, 0- Unused + parameter BYTE_LANES_B0 = 4'b1111, + parameter BYTE_LANES_B1 = 4'b0000, + parameter BYTE_LANES_B2 = 4'b0000, + parameter BYTE_LANES_B3 = 4'b0000, + parameter BYTE_LANES_B4 = 4'b0000, + // defines the bit lanes in I/O banks being used in the interface. Each + // parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused + parameter PHY_0_BITLANES = 48'h0000_0000_0000, + parameter PHY_1_BITLANES = 48'h0000_0000_0000, + parameter PHY_2_BITLANES = 48'h0000_0000_0000, + + // control/address/data pin mapping parameters + parameter CK_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter ADDR_MAP + = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, + parameter BANK_MAP = 36'h000_000_000, + parameter CAS_MAP = 12'h000, + parameter CKE_ODT_BYTE_MAP = 8'h00, + parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, + parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, + parameter CKE_ODT_AUX = "FALSE", + parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, + parameter PARITY_MAP = 12'h000, + parameter RAS_MAP = 12'h000, + parameter WE_MAP = 12'h000, + parameter DQS_BYTE_MAP + = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, + parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, + parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, + parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, + parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, + + // This parameter must be set based on memory clock frequency + // It must be set to 4 for frequencies above 533 MHz?? (undecided) + // and set to 2 for 533 MHz and below + parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly + parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK + parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank + parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" + parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" + parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" + parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" + parameter IODELAY_GRP = "IODELAY_MIG", + parameter FPGA_SPEED_GRADE = 1, + parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option + parameter OUTPUT_DRV = "HIGH", // to calib_top + parameter REG_CTRL = "OFF", // to calib_top + parameter RTT_NOM = "60", // to calib_top + parameter RTT_WR = "120", // to calib_top + parameter tCK = 2500, // pS + parameter tRFC = 110000, // pS + parameter tREFI = 7800000, // pS + parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 + parameter WRLVL = "OFF", // to calib_top + parameter DEBUG_PORT = "OFF", // to calib_top + parameter RANKS = 4, + parameter ODT_WIDTH = 1, + parameter ROW_WIDTH = 16, // DRAM address bus width + parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, + // calibration Address. The address given below will be used for calibration + // read and write operations. + parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address + parameter CALIB_COL_ADD = 12'h000, // Calibration column address + parameter CALIB_BA_ADD = 3'h0, // Calibration bank address + // Simulation /debug options + parameter SIM_BYPASS_INIT_CAL = "OFF", + // Parameter used to force skipping + // or abbreviation of initialization + // and calibration. Overrides + // SIM_INIT_OPTION, SIM_CAL_OPTION, + // and disables various other blocks + //parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps + //parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps + parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz) + parameter USE_CS_PORT = 1, // Support chip select output + parameter USE_DM_PORT = 1, // Support data mask output + parameter USE_ODT_PORT = 1, // Support ODT output + parameter RD_PATH_REG = 0, // optional registers in the read path + // to MC for timing improvement. + // =1 enabled, = 0 disabled + parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change + parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl + parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation + parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering + parameter TAPSPERKCLK = 56, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter SKIP_CALIB = "FALSE", + parameter FPGA_VOLT_TYPE = "N" + ) + ( + input clk, // Fabric logic clock + // To MC, calib_top, hard PHY + input clk_div2, // mem_refclk divided by 2 for PI incdec + input rst_div2, // reset in clk_div2 domain + input clk_ref, // Idelay_ctrl reference clock + // To hard PHY (external source) + input freq_refclk, // To hard PHY for Phasers + input mem_refclk, // Memory clock to hard PHY + input pll_lock, // System PLL lock signal + input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS + input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering + input poc_sample_pd, // Tell POC how to avoid metastability. + + input error, // Support for TG error detect + output rst_tg_mc, // Support for TG error detect + + input [11:0] device_temp, + input tempmon_sample_en, + + input dbg_sel_pi_incdec, + input dbg_sel_po_incdec, + input [DQS_CNT_WIDTH:0] dbg_byte_sel, + input dbg_pi_f_inc, + input dbg_pi_f_dec, + input dbg_po_f_inc, + input dbg_po_f_stg23_sel, + input dbg_po_f_dec, + input dbg_idel_down_all, + input dbg_idel_down_cpt, + input dbg_idel_up_all, + input dbg_idel_up_cpt, + input dbg_sel_all_idel_cpt, + input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, + input rst, + input iddr_rst, + input [7:0] slot_0_present, + input [7:0] slot_1_present, + // From MC + input [nCK_PER_CLK-1:0] mc_ras_n, + input [nCK_PER_CLK-1:0] mc_cas_n, + input [nCK_PER_CLK-1:0] mc_we_n, + input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, + input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, + input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, + input mc_reset_n, + input [1:0] mc_odt, + input [nCK_PER_CLK-1:0] mc_cke, + // AUX - For ODT and CKE assertion during reads and writes + input [3:0] mc_aux_out0, + input [3:0] mc_aux_out1, + input mc_cmd_wren, + input mc_ctl_wren, + input [2:0] mc_cmd, + input [1:0] mc_cas_slot, + input [5:0] mc_data_offset, + input [5:0] mc_data_offset_1, + input [5:0] mc_data_offset_2, + input [1:0] mc_rank_cnt, + // Write + input mc_wrdata_en, + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, + input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask, + input idle, + // DDR bus signals + output [ROW_WIDTH-1:0] ddr_addr, + output [BANK_WIDTH-1:0] ddr_ba, + output ddr_cas_n, + output [CK_WIDTH-1:0] ddr_ck_n, + output [CK_WIDTH-1:0] ddr_ck, + output [CKE_WIDTH-1:0] ddr_cke, + output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, + output [DM_WIDTH-1:0] ddr_dm, + output [ODT_WIDTH-1:0] ddr_odt, + output ddr_ras_n, + output ddr_reset_n, + output ddr_parity, + output ddr_we_n, + inout [DQ_WIDTH-1:0] ddr_dq, + inout [DQS_WIDTH-1:0] ddr_dqs_n, + inout [DQS_WIDTH-1:0] ddr_dqs, + + // Ports to be used when SKIP_CALIB="TRUE" + output calib_tap_req, + input [6:0] calib_tap_addr, + input calib_tap_load, + input [7:0] calib_tap_val, + input calib_tap_load_done, + + //phase shift clock control + output psen, + output psincdec, + input psdone, + // Debug Port Outputs + output [255:0] dbg_calib_top, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, + output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, + output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, + output [255:0] dbg_phy_rdlvl, + output [99:0] dbg_phy_wrcal, + output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, + output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata, + output dbg_rddata_valid, + output [1:0] dbg_rdlvl_done, + output [1:0] dbg_rdlvl_err, + output [1:0] dbg_rdlvl_start, + output [5:0] dbg_tap_cnt_during_wrlvl, + output dbg_wl_edge_detect_valid, + output dbg_wrlvl_done, + output dbg_wrlvl_err, + output dbg_wrlvl_start, + output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, + output [255:0] dbg_phy_wrlvl, + output dbg_pi_phaselock_start, + output dbg_pi_phaselocked_done, + output dbg_pi_phaselock_err, + output [11:0] dbg_pi_phase_locked_phy4lanes, + output dbg_pi_dqsfound_start, + output dbg_pi_dqsfound_done, + output dbg_pi_dqsfound_err, + output [11:0] dbg_pi_dqs_found_lanes_phy4lanes, + output dbg_wrcal_start, + output dbg_wrcal_done, + output dbg_wrcal_err, + output [1023:0] dbg_poc, + // FIFO status flags + output phy_mc_ctl_full, + output phy_mc_cmd_full, + output phy_mc_data_full, + // Calibration status and resultant outputs + output init_calib_complete, + output init_wrcal_complete, + output [6*RANKS-1:0] calib_rd_data_offset_0, + output [6*RANKS-1:0] calib_rd_data_offset_1, + output [6*RANKS-1:0] calib_rd_data_offset_2, + output phy_rddata_valid, + output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, + + output ref_dll_lock, + input rst_phaser_ref, + output [6*RANKS-1:0] dbg_rd_data_offset, + output [255:0] dbg_phy_init, + output [255:0] dbg_prbs_rdlvl, + output [255:0] dbg_dqs_found_cal, + output [5:0] dbg_pi_counter_read_val, + output [8:0] dbg_po_counter_read_val, + output dbg_oclkdelay_calib_start, + output dbg_oclkdelay_calib_done, + output [255:0] dbg_phy_oclkdelay_cal, + output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, + output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, + output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps + ); + + // Calculate number of slots in the system + localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); + localparam CLK_PERIOD = tCK * nCK_PER_CLK; + + // Parameter used to force skipping or abbreviation of initialization + // and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and + // disables various other blocks depending on the option selected + // This option should only be used during simulation. In the case of + // the "SKIP" option, the testbench used should also not be modeling + // propagation delays. + // Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"} + // "NONE" = options determined by the individual parameter settings + // "SIM_FULL" = skip power-up delay. FULL calibration performed without + // averaging algorithm turned ON during window detection. + // "SKIP" = skip power-up delay. Skip calibration not yet supported. + // "FAST" = skip power-up delay, and calibrate (read leveling, write + // leveling, and phase detector) only using one DQS group, and + // apply the results to all other DQS groups. + localparam SIM_INIT_OPTION + = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" : + ((SIM_BYPASS_INIT_CAL == "FAST") || + (SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" : + "NONE"); + localparam SIM_CAL_OPTION + = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" : + (SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" : + ((SIM_BYPASS_INIT_CAL == "SIM_FULL") || + (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" : + "NONE"); + localparam WRLVL_W + = (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL; + + localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : + (BYTE_LANES_B2 != 0 ? 3 : + (BYTE_LANES_B1 != 0 ? 2 : 1)))); + + localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : + BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : + 0; + localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : + BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : + 0; + localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : + BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : + 0; + localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 : + BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 : + 0; + localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 : + BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 : + 0; + localparam HIGHEST_LANE = + (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : + ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : + ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : + ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : + HIGHEST_LANE_B0))); + + localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) + + (0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) + + (0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) + + (0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) + + ((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) + + (0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) + + (0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) + + (0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) + + ((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) + + (0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) + + (0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) + + (0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) + + ((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) + + (0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) + + (0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) + + (0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) + + ((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) + + (0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) + + (0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) + + (0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])); + + // Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank + // This should be the case since the PLL should be placed adjacent + // to the same IO Bank as Ck/Addr/Cmd and Control + localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) | + ((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | + ((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ? + 3'b000 : + (((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | + ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ? + 3'b001 : + (((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | + ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ? + 3'b010 : + (((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | + ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ? + 3'b011 : + (((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) | + ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) | + ((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ? + 3'b100 : 3'b000; + + localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? + 8'b00_10_01_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_11_01_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_11_10_00 : + ((N_CTL_LANES == 3) & + (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_11_10_01 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ? + 8'b00_00_01_00 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_00_11_00 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_00_11_10 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? + 8'b00_00_10_01 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] & + (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) | + ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] & + (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) | + ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] & + (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) | + ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] & + (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) | + ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] & + (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ? + 8'b00_00_11_01 : + ((N_CTL_LANES == 2) & + (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] & + (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) | + ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] & + (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) | + ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] & + (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) | + ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] & + (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) | + ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] & + (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ? + 8'b00_00_10_00 : 8'b11_10_01_00; + + localparam PI_DIV2_INCDEC = (DRAM_TYPE == "DDR2") ? "FALSE" : (((FPGA_VOLT_TYPE == "L") && (nCK_PER_CLK == 4)) ? "TRUE" : "FALSE"); + + wire [HIGHEST_LANE*80-1:0] phy_din; + wire [HIGHEST_LANE*80-1:0] phy_dout; + wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data; + wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out; + wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk; + wire phy_mc_go; + wire phy_ctl_full; + wire phy_cmd_full; + wire phy_data_full; + wire phy_pre_data_a_full; + wire if_empty /* synthesis syn_maxfan = 3 */; + wire phy_write_calib; + wire phy_read_calib; + wire [HIGHEST_BANK-1:0] rst_stg1_cal; + wire [5:0] calib_sel; + wire calib_in_common /* synthesis syn_maxfan = 10 */; + wire [HIGHEST_BANK-1:0] calib_zero_inputs; + wire [HIGHEST_BANK-1:0] calib_zero_ctrl; + wire pi_phase_locked; + wire pi_phase_locked_all; + wire pi_found_dqs; + wire pi_dqs_found_all; + wire pi_dqs_out_of_range; + wire pi_enstg2_f; + wire pi_stg2_fincdec; + wire pi_stg2_load; + wire [5:0] pi_stg2_reg_l; + wire idelay_ce; + wire idelay_inc; + wire idelay_ld; + wire [2:0] po_sel_stg2stg3; + wire [2:0] po_stg2_cincdec; + wire [2:0] po_enstg2_c; + wire [2:0] po_stg2_fincdec; + wire [2:0] po_enstg2_f; + wire [8:0] po_counter_read_val; + wire [5:0] pi_counter_read_val; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata; + reg [nCK_PER_CLK-1:0] parity; + wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address; + wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank; + wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n; + wire [nCK_PER_CLK-1:0] phy_ras_n; + wire [nCK_PER_CLK-1:0] phy_cas_n; + wire [nCK_PER_CLK-1:0] phy_we_n; + wire phy_reset_n; + wire [3:0] calib_aux_out; + wire [nCK_PER_CLK-1:0] calib_cke; + wire [1:0] calib_odt; + wire calib_ctl_wren; + wire calib_cmd_wren; + wire calib_wrdata_en; + wire [2:0] calib_cmd; + wire [1:0] calib_seq; + wire [5:0] calib_data_offset_0; + wire [5:0] calib_data_offset_1; + wire [5:0] calib_data_offset_2; + wire [1:0] calib_rank_cnt; + wire [1:0] calib_cas_slot; + wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address; + wire [3:0] mux_aux_out; + wire [3:0] aux_out_map; + wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank; + wire [2:0] mux_cmd; + wire mux_cmd_wren; + wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n; + wire mux_ctl_wren; + wire [1:0] mux_cas_slot; + wire [5:0] mux_data_offset; + wire [5:0] mux_data_offset_1; + wire [5:0] mux_data_offset_2; + wire [nCK_PER_CLK-1:0] mux_ras_n; + wire [nCK_PER_CLK-1:0] mux_cas_n; + wire [1:0] mux_rank_cnt; + wire mux_reset_n; + wire [nCK_PER_CLK-1:0] mux_we_n; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata; + wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask; + wire mux_wrdata_en; + wire [nCK_PER_CLK-1:0] mux_cke ; + wire [1:0] mux_odt ; + wire phy_if_empty_def; + wire phy_if_reset; + wire phy_init_data_sel; + wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map; + wire phy_rddata_valid_w; + reg rddata_valid_reg; + reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg; + wire [4:0] idelaye2_init_val; + wire [5:0] oclkdelay_init_val; + wire po_counter_load_en; + wire [DQS_CNT_WIDTH:0] byte_sel_cnt; + wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb; + wire fine_delay_sel; + wire pd_out; + + //*************************************************************************** + + assign dbg_rddata_valid = rddata_valid_reg; + assign dbg_rddata = rd_data_reg; + + assign dbg_rd_data_offset = calib_rd_data_offset_0; + assign dbg_pi_phaselocked_done = pi_phase_locked_all; + + assign dbg_po_counter_read_val = po_counter_read_val; + assign dbg_pi_counter_read_val = pi_counter_read_val; + + //*************************************************************************** + + //*************************************************************************** + // Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec + //*************************************************************************** + //localparam PI_DIV2_INCDEC = "TRUE"; + + wire pi_fine_enable; + wire pi_fine_inc; + wire pi_counter_load_en; + wire [5:0] pi_counter_load_val; + wire [HIGHEST_BANK-1:0] pi_rst_dqs_find; + + generate + if (PI_DIV2_INCDEC == "TRUE") begin: div2_incdec + // 3-stage synchronizer registers + (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r2; + (* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r3; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r2; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r3; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r1; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r2; + (* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r3; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r1; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r2; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r1; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r2; + (* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r3; + + reg pi_stg2_fine_enable, pi_stg2_fine_enable_r1; + reg pi_stg2_fine_inc, pi_stg2_fine_inc_r1; + reg pi_stg2_load_en, pi_stg2_load_en_r1; + reg [5:0] pi_stg2_load_val; + (* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] pi_dqs_find_rst; + + // 3-stage synchronizer + always @(posedge clk_div2) begin + //Phaser_In fine enable + pi_enstg2_f_div2r1 <= #TCQ pi_enstg2_f; + pi_enstg2_f_div2r2 <= #TCQ pi_enstg2_f_div2r1; + pi_enstg2_f_div2r3 <= #TCQ pi_enstg2_f_div2r2; + //Phaser_In fine incdec + pi_stg2_fincdec_div2r1 <= #TCQ pi_stg2_fincdec; + pi_stg2_fincdec_div2r2 <= #TCQ pi_stg2_fincdec_div2r1; + pi_stg2_fincdec_div2r3 <= #TCQ pi_stg2_fincdec_div2r2; + //Phaser_In stage2 load + pi_stg2_load_div2r1 <= #TCQ pi_stg2_load; + pi_stg2_load_div2r2 <= #TCQ pi_stg2_load_div2r1; + pi_stg2_load_div2r3 <= #TCQ pi_stg2_load_div2r2; + //Phaser_In stage2 load value + pi_stg2_reg_l_div2r1 <= #TCQ pi_stg2_reg_l; + pi_stg2_reg_l_div2r2 <= #TCQ pi_stg2_reg_l_div2r1; + pi_stg2_reg_l_div2r3 <= #TCQ pi_stg2_reg_l_div2r2; + //Phaser_In reset DQSFOUND + rst_stg1_cal_div2r1 <= #TCQ rst_stg1_cal; + rst_stg1_cal_div2r2 <= #TCQ rst_stg1_cal_div2r1; + pi_dqs_find_rst <= #TCQ rst_stg1_cal_div2r2; + end + + always @(posedge clk_div2) begin + pi_stg2_fine_enable_r1 <= #TCQ pi_stg2_fine_enable; + pi_stg2_fine_inc_r1 <= #TCQ pi_stg2_fine_inc; + pi_stg2_load_en_r1 <= #TCQ pi_stg2_load_en; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_fine_enable || pi_stg2_fine_enable_r1) + pi_stg2_fine_enable <= #TCQ 1'b0; + else if (pi_enstg2_f_div2r3) + pi_stg2_fine_enable <= #TCQ 1'b1; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_fine_inc || pi_stg2_fine_inc_r1) + pi_stg2_fine_inc <= #TCQ 1'b0; + else if (pi_stg2_fincdec_div2r3) + pi_stg2_fine_inc <= #TCQ 1'b1; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1) + pi_stg2_load_en <= #TCQ 1'b0; + else if (pi_stg2_load_div2r3) + pi_stg2_load_en <= #TCQ 1'b1; + end + + always @(posedge clk_div2) begin + if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1) + pi_stg2_load_val <= #TCQ 6'd0; + else if (pi_stg2_load_div2r3) + pi_stg2_load_val <= #TCQ pi_stg2_reg_l_div2r3; + end + + + assign pi_fine_enable = pi_stg2_fine_enable; + assign pi_fine_inc = pi_stg2_fine_inc; + assign pi_counter_load_en = pi_stg2_load_en; + assign pi_counter_load_val = pi_stg2_load_val; + assign pi_rst_dqs_find = pi_dqs_find_rst; + + end else begin: div4_incdec + assign pi_fine_enable = pi_enstg2_f; + assign pi_fine_inc = pi_stg2_fincdec; + assign pi_counter_load_en = pi_stg2_load; + assign pi_counter_load_val = pi_stg2_reg_l; + assign pi_rst_dqs_find = rst_stg1_cal; + + end + endgenerate + + genvar i; + generate + for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen + assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i]; + assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1]; + end + endgenerate + + //*************************************************************************** + // During memory initialization and calibration the calibration logic drives + // the memory signals. After calibration is complete the memory controller + // drives the memory signals. + // Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps + //*************************************************************************** + + wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ; + genvar v ; + + generate + if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm + for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin + if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin + assign mc_cs_n_temp[v] = mc_cs_n[v] ; + end else begin + assign mc_cs_n_temp[v] = 'b1 ; + end + end + end else begin + assign mc_cs_n_temp = mc_cs_n ; + end + endgenerate + + assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata; + assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0; + assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address; + assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank; + assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n; + assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n; + assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n; + assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n; + assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n; + assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out; + assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ; + assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ; + assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren : + calib_cmd_wren; + assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren : + calib_ctl_wren; + assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en : + calib_wrdata_en; + assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd; + assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot; + assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset : + calib_data_offset_0; + assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 : + calib_data_offset_1; + assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 : + calib_data_offset_2; + // Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601 + assign mux_rank_cnt = 2'b00; + + + // Assigning cke & odt for DDR2 & DDR3 + // No changes for DDR3 & DDR2 dual rank + // DDR2 single rank systems might potentially need 3 odt signals. + // Aux_out[2] will have the odt toggled by phy and controller + // wiring aux_out[2] to 0 & 3. Depending upon the odt parameter + // all of the three odt bits or some of them might be used. + // mapping done in mc_phy_wrapper module + generate + if(CKE_ODT_AUX == "TRUE") begin + assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ? + {mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} : + mux_aux_out; + end else begin + assign aux_out_map = 4'b0000 ; + end + endgenerate + + assign init_calib_complete = phy_init_data_sel; + + assign phy_mc_ctl_full = phy_ctl_full; + assign phy_mc_cmd_full = phy_cmd_full; + assign phy_mc_data_full = phy_pre_data_a_full; + + //*************************************************************************** + // Generate parity for DDR3 RDIMM. + //*************************************************************************** + + generate + if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity + if (nCK_PER_CLK == 4) begin + always @(posedge clk) begin + parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3], + mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3], + mux_cas_n[3], mux_ras_n[3], mux_we_n[3]}); + end + always @(*) begin + parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0], + mux_cas_n[0],mux_ras_n[0], mux_we_n[0]}); + parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], + mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], + mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); + parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2], + mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2], + mux_cas_n[2],mux_ras_n[2], mux_we_n[2]}); + end + end else begin + always @(posedge clk) begin + parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH], + mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH], + mux_cas_n[1], mux_ras_n[1], mux_we_n[1]}); + end + always @(*) begin + parity[1] = (^{mux_address[ROW_WIDTH-1:0], + mux_bank[BANK_WIDTH-1:0], + mux_cas_n[0], mux_ras_n[0], mux_we_n[0]}); + end + end + end else begin: gen_ddr3_noparity + if (nCK_PER_CLK == 4) begin + always @(posedge clk) begin + parity[0] <= #TCQ 1'b0; + parity[1] <= #TCQ 1'b0; + parity[2] <= #TCQ 1'b0; + parity[3] <= #TCQ 1'b0; + end + end else begin + always @(posedge clk) begin + parity[0] <= #TCQ 1'b0; + parity[1] <= #TCQ 1'b0; + end + end + end + endgenerate + + //*************************************************************************** + // Code for optional register stage in read path to MC for timing + //*************************************************************************** + generate + if(RD_PATH_REG == 1)begin:RD_REG_TIMING + always @(posedge clk)begin + rddata_valid_reg <= #TCQ phy_rddata_valid_w; + rd_data_reg <= #TCQ rd_data_map; + end // always @ (posedge clk) + end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING + always @(phy_rddata_valid_w or rd_data_map)begin + rddata_valid_reg = phy_rddata_valid_w; + rd_data_reg = rd_data_map; + end + end + endgenerate + + assign phy_rddata_valid = rddata_valid_reg; + assign phy_rd_data = rd_data_reg; + + //*************************************************************************** + // Hard PHY and accompanying bit mapping logic + //*************************************************************************** + + mig_7series_v4_2_ddr_mc_phy_wrapper # + ( + .TCQ (TCQ), + .tCK (tCK), + .BANK_TYPE (BANK_TYPE), + .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), + .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN), + .IODELAY_GRP (IODELAY_GRP), + .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), + .nCK_PER_CLK (nCK_PER_CLK), + .nCS_PER_RANK (nCS_PER_RANK), + .BANK_WIDTH (BANK_WIDTH), + .CKE_WIDTH (CKE_WIDTH), + .CS_WIDTH (CS_WIDTH), + .CK_WIDTH (CK_WIDTH), + .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), + .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), + .CWL (CWL), + .DM_WIDTH (DM_WIDTH), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_TYPE (DRAM_TYPE), + .RANKS (RANKS), + .ODT_WIDTH (ODT_WIDTH), + .REG_CTRL (REG_CTRL), + .ROW_WIDTH (ROW_WIDTH), + .USE_CS_PORT (USE_CS_PORT), + .USE_DM_PORT (USE_DM_PORT), + .USE_ODT_PORT (USE_ODT_PORT), + .IBUF_LPWR_MODE (IBUF_LPWR_MODE), + .PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .PHY_0_BITLANES (PHY_0_BITLANES), + .PHY_1_BITLANES (PHY_1_BITLANES), + .PHY_2_BITLANES (PHY_2_BITLANES), + .HIGHEST_BANK (HIGHEST_BANK), + .HIGHEST_LANE (HIGHEST_LANE), + .CK_BYTE_MAP (CK_BYTE_MAP), + .ADDR_MAP (ADDR_MAP), + .BANK_MAP (BANK_MAP), + .CAS_MAP (CAS_MAP), + .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), + .CKE_MAP (CKE_MAP), + .ODT_MAP (ODT_MAP), + .CKE_ODT_AUX (CKE_ODT_AUX), + .CS_MAP (CS_MAP), + .PARITY_MAP (PARITY_MAP), + .RAS_MAP (RAS_MAP), + .WE_MAP (WE_MAP), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .DATA0_MAP (DATA0_MAP), + .DATA1_MAP (DATA1_MAP), + .DATA2_MAP (DATA2_MAP), + .DATA3_MAP (DATA3_MAP), + .DATA4_MAP (DATA4_MAP), + .DATA5_MAP (DATA5_MAP), + .DATA6_MAP (DATA6_MAP), + .DATA7_MAP (DATA7_MAP), + .DATA8_MAP (DATA8_MAP), + .DATA9_MAP (DATA9_MAP), + .DATA10_MAP (DATA10_MAP), + .DATA11_MAP (DATA11_MAP), + .DATA12_MAP (DATA12_MAP), + .DATA13_MAP (DATA13_MAP), + .DATA14_MAP (DATA14_MAP), + .DATA15_MAP (DATA15_MAP), + .DATA16_MAP (DATA16_MAP), + .DATA17_MAP (DATA17_MAP), + .MASK0_MAP (MASK0_MAP), + .MASK1_MAP (MASK1_MAP), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .MASTER_PHY_CTL (MASTER_PHY_CTL), + .DRAM_WIDTH (DRAM_WIDTH), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_mc_phy_wrapper + ( + .rst (rst), + .iddr_rst (iddr_rst), + .clk (clk), + .clk_div2 (clk_div2), + // For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk + // For memory frequencies below 400 MHz mem_refclk = mem_refclk and + // freq_refclk = 2x or 4x mem_refclk such that it remains in the + // 400~1066 MHz range + .freq_refclk (freq_refclk), + .mem_refclk (mem_refclk), + .mmcm_ps_clk (mmcm_ps_clk), + .pll_lock (pll_lock), + .sync_pulse (sync_pulse), + .idelayctrl_refclk (clk_ref), + .phy_cmd_wr_en (mux_cmd_wren), + .phy_data_wr_en (mux_wrdata_en), + // phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23], + // DataOffset[22:17],HiIndex[16:15],LowIndex[14:12], + // AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]} + // The fields ACTPRE, and BankCount are only used + // when the hard PHY counters are used by the MC. + .phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset, + mux_rank_cnt, 3'd0, aux_out_map, + 5'd0, mux_cmd}), + .phy_ctl_wr (mux_ctl_wren), + .phy_if_empty_def (phy_if_empty_def), + .phy_if_reset (phy_if_reset), + .data_offset_1 (mux_data_offset_1), + .data_offset_2 (mux_data_offset_2), + .aux_in_1 (aux_out_map), + .aux_in_2 (aux_out_map), + .idelaye2_init_val (idelaye2_init_val), + .oclkdelay_init_val (oclkdelay_init_val), + .if_empty (if_empty), + .phy_ctl_full (phy_ctl_full), + .phy_cmd_full (phy_cmd_full), + .phy_data_full (phy_data_full), + .phy_pre_data_a_full (phy_pre_data_a_full), + .ddr_clk (ddr_clk), + .phy_mc_go (phy_mc_go), + .phy_write_calib (phy_write_calib), + .phy_read_calib (phy_read_calib), + .po_fine_enable (po_enstg2_f), + .po_coarse_enable (po_enstg2_c), + .po_fine_inc (po_stg2_fincdec), + .po_coarse_inc (po_stg2_cincdec), + .po_counter_load_en (po_counter_load_en), + .po_counter_read_en (1'b1), + .po_sel_fine_oclk_delay (po_sel_stg2stg3), + .po_counter_load_val (), + .po_counter_read_val (po_counter_read_val), + .pi_rst_dqs_find (pi_rst_dqs_find), + .pi_fine_enable (pi_fine_enable), + .pi_fine_inc (pi_fine_inc), + .pi_counter_load_en (pi_counter_load_en), + .pi_counter_load_val (pi_counter_load_val), + .pi_counter_read_val (pi_counter_read_val), + .idelay_ce (idelay_ce), + .idelay_inc (idelay_inc), + .idelay_ld (idelay_ld), + .pi_phase_locked (pi_phase_locked), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_dqs_found (pi_found_dqs), + .pi_dqs_found_all (pi_dqs_found_all), + // Currently not being used. May be used in future if periodic reads + // become a requirement. This output could also be used to signal a + // catastrophic failure in read capture and the need for re-cal + .pi_dqs_out_of_range (pi_dqs_out_of_range), + .phy_init_data_sel (phy_init_data_sel), + .calib_sel (calib_sel), + .calib_in_common (calib_in_common), + .calib_zero_inputs (calib_zero_inputs), + .calib_zero_ctrl (calib_zero_ctrl), + .mux_address (mux_address), + .mux_bank (mux_bank), + .mux_cs_n (mux_cs_n), + .mux_ras_n (mux_ras_n), + .mux_cas_n (mux_cas_n), + .mux_we_n (mux_we_n), + .mux_reset_n (mux_reset_n), + .parity_in (parity), + .mux_wrdata (mux_wrdata), + .mux_wrdata_mask (mux_wrdata_mask), + .mux_odt (mux_odt), + .mux_cke (mux_cke), + .idle (idle), + .rd_data (rd_data_map), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_odt (ddr_odt), + .ddr_parity (ddr_parity), + .ddr_ras_n (ddr_ras_n), + .ddr_we_n (ddr_we_n), + .ddr_dq (ddr_dq), + .ddr_dqs (ddr_dqs), + .ddr_dqs_n (ddr_dqs_n), + .ddr_reset_n (ddr_reset_n), + .dbg_pi_counter_read_en (1'b1), + .ref_dll_lock (ref_dll_lock), + .rst_phaser_ref (rst_phaser_ref), + .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), + .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .byte_sel_cnt (byte_sel_cnt), + .pd_out (pd_out), + .fine_delay_incdec_pb (fine_delay_incdec_pb), + .fine_delay_sel (fine_delay_sel) + ); + + //*************************************************************************** + // Soft memory initialization and calibration logic + //*************************************************************************** + + mig_7series_v4_2_ddr_calib_top # + ( + .TCQ (TCQ), + .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), + .nCK_PER_CLK (nCK_PER_CLK), + .PRE_REV3ES (PRE_REV3ES), + .tCK (tCK), + .CLK_PERIOD (CLK_PERIOD), + .N_CTL_LANES (N_CTL_LANES), + .CTL_BYTE_LANE (CTL_BYTE_LANE), + .CTL_BANK (CTL_BANK), + .DRAM_TYPE (DRAM_TYPE), + .PRBS_WIDTH (8), + .DQS_BYTE_MAP (DQS_BYTE_MAP), + .HIGHEST_BANK (HIGHEST_BANK), + .BANK_TYPE (BANK_TYPE), + .HIGHEST_LANE (HIGHEST_LANE), + .BYTE_LANES_B0 (BYTE_LANES_B0), + .BYTE_LANES_B1 (BYTE_LANES_B1), + .BYTE_LANES_B2 (BYTE_LANES_B2), + .BYTE_LANES_B3 (BYTE_LANES_B3), + .BYTE_LANES_B4 (BYTE_LANES_B4), + .DATA_CTL_B0 (DATA_CTL_B0), + .DATA_CTL_B1 (DATA_CTL_B1), + .DATA_CTL_B2 (DATA_CTL_B2), + .DATA_CTL_B3 (DATA_CTL_B3), + .DATA_CTL_B4 (DATA_CTL_B4), + .SLOT_1_CONFIG (SLOT_1_CONFIG), + .BANK_WIDTH (BANK_WIDTH), + .CA_MIRROR (CA_MIRROR), + .COL_WIDTH (COL_WIDTH), + .CKE_ODT_AUX (CKE_ODT_AUX), + .nCS_PER_RANK (nCS_PER_RANK), + .DQ_WIDTH (DQ_WIDTH), + .DQS_CNT_WIDTH (DQS_CNT_WIDTH), + .DQS_WIDTH (DQS_WIDTH), + .DRAM_WIDTH (DRAM_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .RANKS (RANKS), + .CS_WIDTH (CS_WIDTH), + .CKE_WIDTH (CKE_WIDTH), + .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), + .PER_BIT_DESKEW ("OFF"), + .CALIB_ROW_ADD (CALIB_ROW_ADD), + .CALIB_COL_ADD (CALIB_COL_ADD), + .CALIB_BA_ADD (CALIB_BA_ADD), + .AL (AL), + .BURST_MODE (BURST_MODE), + .BURST_TYPE (BURST_TYPE), + .nCL (CL), + .nCWL (CWL), + .tRFC (tRFC), + .tREFI (tREFI), + .OUTPUT_DRV (OUTPUT_DRV), + .REG_CTRL (REG_CTRL), + .ADDR_CMD_MODE (ADDR_CMD_MODE), + .RTT_NOM (RTT_NOM), + .RTT_WR (RTT_WR), + .WRLVL (WRLVL_W), + .USE_ODT_PORT (USE_ODT_PORT), + .SIM_INIT_OPTION (SIM_INIT_OPTION), + .SIM_CAL_OPTION (SIM_CAL_OPTION), + .DEBUG_PORT (DEBUG_PORT), + .IDELAY_ADJ (IDELAY_ADJ), + .FINE_PER_BIT (FINE_PER_BIT), + .CENTER_COMP_MODE (CENTER_COMP_MODE), + .PI_VAL_ADJ (PI_VAL_ADJ), + .TAPSPERKCLK (TAPSPERKCLK), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SKIP_CALIB (SKIP_CALIB), + .PI_DIV2_INCDEC (PI_DIV2_INCDEC) + ) + u_ddr_calib_top + ( + .clk (clk), + .rst (rst), + + .tg_err (error), + .rst_tg_mc (rst_tg_mc), + + .slot_0_present (slot_0_present), + .slot_1_present (slot_1_present), + // PHY Control Block and IN_FIFO status + .phy_ctl_ready (phy_mc_go), + .phy_ctl_full (1'b0), + .phy_cmd_full (1'b0), + .phy_data_full (1'b0), + .phy_if_empty (if_empty), + .idelaye2_init_val (idelaye2_init_val), + .oclkdelay_init_val (oclkdelay_init_val), + // From calib logic To data IN_FIFO + // DQ IDELAY tap value from Calib logic + // port to be added to mc_phy by Gary + .dlyval_dq (), + // hard PHY calibration modes + .write_calib (phy_write_calib), + .read_calib (phy_read_calib), + // DQS count and ck/addr/cmd to be mapped to calib_sel + // based on parameter that defines placement of ctl lanes + // and DQS byte groups in each bank. When phy_write_calib + // is de-asserted calib_sel should select CK/addr/cmd/ctl. + .calib_sel (calib_sel), + .calib_in_common (calib_in_common), + .calib_zero_inputs (calib_zero_inputs), + .calib_zero_ctrl (calib_zero_ctrl), + .phy_if_empty_def (phy_if_empty_def), + .phy_if_reset (phy_if_reset), + // Signals from calib logic to be MUXED with MC + // signals before sending to hard PHY + .calib_ctl_wren (calib_ctl_wren), + .calib_cmd_wren (calib_cmd_wren), + .calib_seq (calib_seq), + .calib_aux_out (calib_aux_out), + .calib_odt (calib_odt), + .calib_cke (calib_cke), + .calib_cmd (calib_cmd), + .calib_wrdata_en (calib_wrdata_en), + .calib_rank_cnt (calib_rank_cnt), + .calib_cas_slot (calib_cas_slot), + .calib_data_offset_0 (calib_data_offset_0), + .calib_data_offset_1 (calib_data_offset_1), + .calib_data_offset_2 (calib_data_offset_2), + .phy_reset_n (phy_reset_n), + .phy_address (phy_address), + .phy_bank (phy_bank), + .phy_cs_n (phy_cs_n), + .phy_ras_n (phy_ras_n), + .phy_cas_n (phy_cas_n), + .phy_we_n (phy_we_n), + .phy_wrdata (phy_wrdata), + // DQS Phaser_IN calibration/status signals + .pi_phaselocked (pi_phase_locked), + .pi_phase_locked_all (pi_phase_locked_all), + .pi_found_dqs (pi_found_dqs), + .pi_dqs_found_all (pi_dqs_found_all), + .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), + .pi_rst_stg1_cal (rst_stg1_cal), + .pi_en_stg2_f (pi_enstg2_f), + .pi_stg2_f_incdec (pi_stg2_fincdec), + .pi_stg2_load (pi_stg2_load), + .pi_stg2_reg_l (pi_stg2_reg_l), + .pi_counter_read_val (pi_counter_read_val), + .device_temp (device_temp), + .tempmon_sample_en (tempmon_sample_en), + // IDELAY tap enable and inc signals + .idelay_ce (idelay_ce), + .idelay_inc (idelay_inc), + .idelay_ld (idelay_ld), + // DQS Phaser_OUT calibration/status signals + .po_sel_stg2stg3 (po_sel_stg2stg3), + .po_stg2_c_incdec (po_stg2_cincdec), + .po_en_stg2_c (po_enstg2_c), + .po_stg2_f_incdec (po_stg2_fincdec), + .po_en_stg2_f (po_enstg2_f), + .po_counter_load_en (po_counter_load_en), + .po_counter_read_val (po_counter_read_val), + // From data IN_FIFO To Calib logic and MC/UI + .phy_rddata (rd_data_map), + // From calib logic To MC + .phy_rddata_valid (phy_rddata_valid_w), + .calib_rd_data_offset_0 (calib_rd_data_offset_0), + .calib_rd_data_offset_1 (calib_rd_data_offset_1), + .calib_rd_data_offset_2 (calib_rd_data_offset_2), + .calib_writes (), + // Mem Init and Calibration status To MC + .init_calib_complete (phy_init_data_sel), + .init_wrcal_complete (init_wrcal_complete), + // Debug Error signals + .pi_phase_locked_err (dbg_pi_phaselock_err), + .pi_dqsfound_err (dbg_pi_dqsfound_err), + .wrcal_err (dbg_wrcal_err), + //used for oclk stg3 centering + .pd_out (pd_out), + .psen (psen), + .psincdec (psincdec), + .psdone (psdone), + .poc_sample_pd (poc_sample_pd), + .calib_tap_req (calib_tap_req), + .calib_tap_addr (calib_tap_addr), + .calib_tap_load (calib_tap_load), + .calib_tap_val (calib_tap_val), + .calib_tap_load_done (calib_tap_load_done), + // Debug Signals + .dbg_pi_phaselock_start (dbg_pi_phaselock_start), + .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), + .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), + .dbg_wrlvl_start (dbg_wrlvl_start), + .dbg_wrlvl_done (dbg_wrlvl_done), + .dbg_wrlvl_err (dbg_wrlvl_err), + .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), + .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), + .dbg_phy_wrlvl (dbg_phy_wrlvl), + .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), + .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), + .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), + .dbg_wrcal_start (dbg_wrcal_start), + .dbg_wrcal_done (dbg_wrcal_done), + .dbg_phy_wrcal (dbg_phy_wrcal), + .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), + .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), + .dbg_rdlvl_start (dbg_rdlvl_start), + .dbg_rdlvl_done (dbg_rdlvl_done), + .dbg_rdlvl_err (dbg_rdlvl_err), + .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), + .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), + .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), + .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), + .dbg_sel_pi_incdec (dbg_sel_pi_incdec), + .dbg_sel_po_incdec (dbg_sel_po_incdec), + .dbg_byte_sel (dbg_byte_sel), + .dbg_pi_f_inc (dbg_pi_f_inc), + .dbg_pi_f_dec (dbg_pi_f_dec), + .dbg_po_f_inc (dbg_po_f_inc), + .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), + .dbg_po_f_dec (dbg_po_f_dec), + .dbg_idel_up_all (dbg_idel_up_all), + .dbg_idel_down_all (dbg_idel_down_all), + .dbg_idel_up_cpt (dbg_idel_up_cpt), + .dbg_idel_down_cpt (dbg_idel_down_cpt), + .dbg_sel_idel_cpt (dbg_sel_idel_cpt), + .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), + .dbg_phy_rdlvl (dbg_phy_rdlvl), + .dbg_calib_top (dbg_calib_top), + .dbg_phy_init (dbg_phy_init), + .dbg_prbs_rdlvl (dbg_prbs_rdlvl), + .dbg_dqs_found_cal (dbg_dqs_found_cal), + .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), + .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), + .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), + .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), + .dbg_poc (dbg_poc[1023:0]), + .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), + .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), + .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), + .byte_sel_cnt (byte_sel_cnt), + .fine_delay_incdec_pb (fine_delay_incdec_pb), + .fine_delay_sel (fine_delay_sel) + ); + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v new file mode 100644 index 0000000..a700da2 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v @@ -0,0 +1,1332 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: +// \ \ Application: MIG +// / / Filename: ddr_phy_wrcal.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Write calibration logic to align DQS to correct CK edge +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ +**$Date: 2011/06/02 08:35:09 $ +**$Author: +**$Revision: +**$Source: +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_wrcal # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter nCK_PER_CLK = 2, // # of memory clocks per CLK + parameter CLK_PERIOD = 2500, + parameter DQ_WIDTH = 64, // # of DQ (data) + parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) + parameter DQS_WIDTH = 8, // # of DQS (strobe) + parameter DRAM_WIDTH = 8, // # of DQ per DQS + parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly + parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps + ) + ( + input clk, + input rst, + // Calibration status, control signals + input wrcal_start, + input wrcal_rd_wait, + input wrcal_sanity_chk, + input dqsfound_retry_done, + input phy_rddata_en, + output dqsfound_retry, + output wrcal_read_req, + output reg wrcal_act_req, + output reg wrcal_done, + output reg wrcal_pat_err, + output reg wrcal_prech_req, + output reg temp_wrcal_done, + output reg wrcal_sanity_chk_done, + input prech_done, + // Captured data in resync clock domain + input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, + // Write level values of Phaser_Out coarse and fine + // delay taps required to load Phaser_Out register + input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, + input [6*DQS_WIDTH-1:0] wl_po_fine_cnt, + input wrlvl_byte_done, + output reg wrlvl_byte_redo, + output reg early1_data, + output reg early2_data, + // DQ IDELAY + output reg idelay_ld, + output reg wrcal_pat_resume, // to phy_init for write + output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt, + output phy_if_reset, + + // Debug Port + output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, + output [99:0] dbg_phy_wrcal + ); + + // Length of calibration sequence (in # of words) + //localparam CAL_PAT_LEN = 8; + + // Read data shift register length + localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2; + + // # of reads for reliable read capture + localparam NUM_READS = 2; + + // # of cycles to wait after changing RDEN count value + localparam RDEN_WAIT_CNT = 12; + + localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6; + localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44; + + + localparam CAL2_IDLE = 4'h0; + localparam CAL2_READ_WAIT = 4'h1; + localparam CAL2_NEXT_DQS = 4'h2; + localparam CAL2_WRLVL_WAIT = 4'h3; + localparam CAL2_IFIFO_RESET = 4'h4; + localparam CAL2_DQ_IDEL_DEC = 4'h5; + localparam CAL2_DONE = 4'h6; + localparam CAL2_SANITY_WAIT = 4'h7; + localparam CAL2_ERR = 4'h8; + + integer i,j,k,l,m,p,q,d; + + reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1]; + reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w; + reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1]; + reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w; + reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */; + reg [4:0] not_empty_wait_cnt; + reg [3:0] tap_inc_wait_cnt; + reg cal2_done_r; + reg cal2_done_r1; + reg cal2_prech_req_r; + reg [3:0] cal2_state_r; + reg [3:0] cal2_state_r1; + reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1]; + reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1]; + reg cal2_if_reset; + reg wrcal_pat_resume_r; + reg wrcal_pat_resume_r1; + reg wrcal_pat_resume_r2; + reg wrcal_pat_resume_r3; + reg [DRAM_WIDTH-1:0] mux_rd_fall0_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall1_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise0_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise1_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall2_r; + reg [DRAM_WIDTH-1:0] mux_rd_fall3_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise2_r; + reg [DRAM_WIDTH-1:0] mux_rd_rise3_r; + reg pat_data_match_r; + reg pat1_data_match_r; + reg pat1_data_match_r1; + reg pat2_data_match_r; + reg pat_data_match_valid_r; + wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0]; + reg [DRAM_WIDTH-1:0] pat_match_fall0_r; + reg pat_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] pat_match_fall1_r; + reg pat_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] pat_match_fall2_r; + reg pat_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] pat_match_fall3_r; + reg pat_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise0_r; + reg pat_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise1_r; + reg pat_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise2_r; + reg pat_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] pat_match_rise3_r; + reg pat_match_rise3_and_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise0_r; + reg [DRAM_WIDTH-1:0] pat1_match_rise1_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall0_r; + reg [DRAM_WIDTH-1:0] pat1_match_fall1_r; + reg [DRAM_WIDTH-1:0] pat2_match_rise0_r; + reg [DRAM_WIDTH-1:0] pat2_match_rise1_r; + reg [DRAM_WIDTH-1:0] pat2_match_fall0_r; + reg [DRAM_WIDTH-1:0] pat2_match_fall1_r; + reg pat1_match_rise0_and_r; + reg pat1_match_rise1_and_r; + reg pat1_match_fall0_and_r; + reg pat1_match_fall1_and_r; + reg pat2_match_rise0_and_r; + reg pat2_match_rise1_and_r; + reg pat2_match_fall0_and_r; + reg pat2_match_fall1_and_r; + reg early1_data_match_r; + reg early1_data_match_r1; + reg [DRAM_WIDTH-1:0] early1_match_fall0_r; + reg early1_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] early1_match_fall1_r; + reg early1_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] early1_match_fall2_r; + reg early1_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] early1_match_fall3_r; + reg early1_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise0_r; + reg early1_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise1_r; + reg early1_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise2_r; + reg early1_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] early1_match_rise3_r; + reg early1_match_rise3_and_r; + reg early2_data_match_r; + reg [DRAM_WIDTH-1:0] early2_match_fall0_r; + reg early2_match_fall0_and_r; + reg [DRAM_WIDTH-1:0] early2_match_fall1_r; + reg early2_match_fall1_and_r; + reg [DRAM_WIDTH-1:0] early2_match_fall2_r; + reg early2_match_fall2_and_r; + reg [DRAM_WIDTH-1:0] early2_match_fall3_r; + reg early2_match_fall3_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise0_r; + reg early2_match_rise0_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise1_r; + reg early2_match_rise1_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise2_r; + reg early2_match_rise2_and_r; + reg [DRAM_WIDTH-1:0] early2_match_rise3_r; + reg early2_match_rise3_and_r; + wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0]; + wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0]; + wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0]; + wire [DQ_WIDTH-1:0] rd_data_rise0; + wire [DQ_WIDTH-1:0] rd_data_fall0; + wire [DQ_WIDTH-1:0] rd_data_rise1; + wire [DQ_WIDTH-1:0] rd_data_fall1; + wire [DQ_WIDTH-1:0] rd_data_rise2; + wire [DQ_WIDTH-1:0] rd_data_fall2; + wire [DQ_WIDTH-1:0] rd_data_rise3; + wire [DQ_WIDTH-1:0] rd_data_fall3; + reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; + reg rd_active_posedge_r; + reg rd_active_r; + reg rd_active_r1; + reg rd_active_r2; + reg rd_active_r3; + reg rd_active_r4; + reg rd_active_r5; + reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0]; + reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0]; + reg wrlvl_byte_done_r; + reg idelay_ld_done; + reg pat1_detect; + reg early1_detect; + reg wrcal_sanity_chk_r; + reg wrcal_sanity_chk_err; + + + //*************************************************************************** + // Debug + //*************************************************************************** + + always @(*) begin + for (d = 0; d < DQS_WIDTH; d = d + 1) begin + po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d]; + po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d]; + end + end + + assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w; + assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w; + + generate + if (nCK_PER_CLK == 4) begin: match_data_4 + assign dbg_phy_wrcal[0] = pat_data_match_r; + end else begin:match_data_2 + assign dbg_phy_wrcal[0] = 1'b0; + end + endgenerate + assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0]; + assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err; + assign dbg_phy_wrcal[6] = wrcal_start; + assign dbg_phy_wrcal[7] = wrcal_done; + assign dbg_phy_wrcal[8] = pat_data_match_valid_r; + assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r; + assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt; + assign dbg_phy_wrcal[22] = early1_data; + assign dbg_phy_wrcal[23] = early2_data; + assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r; + assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r; + assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r; + assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r; + generate + if (nCK_PER_CLK == 4) begin: mux_data_4 + assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r; + assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r; + assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r; + assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r; + end else begin: mux_data_2 + assign dbg_phy_wrcal[56+:8] = {8{1'b0}}; + assign dbg_phy_wrcal[64+:8] = {8{1'b0}}; + assign dbg_phy_wrcal[72+:8] = {8{1'b0}}; + assign dbg_phy_wrcal[80+:8] = {8{1'b0}}; + end + endgenerate + assign dbg_phy_wrcal[88] = early1_data_match_r; + assign dbg_phy_wrcal[89] = early2_data_match_r; + assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r; + assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r; + assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done; + + assign dqsfound_retry = 1'b0; + assign wrcal_read_req = 1'b0; + assign phy_if_reset = cal2_if_reset; + + //************************************************************************** + // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 + // coarse delay + //************************************************************************** + + always @(posedge clk) begin + po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r; + wrlvl_byte_done_r <= #TCQ wrlvl_byte_done; + wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk; + end + + //*************************************************************************** + // Data mux to route appropriate byte to calibration logic - i.e. calibration + // is done sequentially, one byte (or DQS group) at a time + //*************************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: gen_rd_data_div4 + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; + assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; + assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; + assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; + end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2 + assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; + assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; + assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; + assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; + end + endgenerate + + //************************************************************************** + // Final Phaser OUT coarse and fine delay taps after write calibration + // Sum of taps used during write leveling taps and write calibration + //************************************************************************** + + always @(*) begin + for (m = 0; m < DQS_WIDTH; m = m + 1) begin + wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3]; + wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6]; + end + end + + always @(posedge clk) begin + if (rst) begin + for (p = 0; p < DQS_WIDTH; p = p + 1) begin + po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}}; + po_fine_tap_cnt[p] <= #TCQ {6{1'b0}}; + end + end else if (cal2_done_r && ~cal2_done_r1) begin + for (q = 0; q < DQS_WIDTH; q = q + 1) begin + po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i]; + po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i]; + end + end + end + + always @(posedge clk) begin + rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r; + end + + // Register outputs for improved timing. + // NOTE: Will need to change when per-bit DQ deskew is supported. + // Currenly all bits in DQS group are checked in aggregate + generate + genvar mux_i; + if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4 + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + end + end + end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2 + for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd + always @(posedge clk) begin + mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; + end + end + end + endgenerate + + //*************************************************************************** + // generate request to PHY_INIT logic to issue precharged. Required when + // calibration can take a long time (during which there are only constant + // reads present on this bus). In this case need to issue perioidic + // precharges to avoid tRAS violation. This signal must meet the following + // requirements: (1) only transition from 0->1 when prech is first needed, + // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted + //*************************************************************************** + + always @(posedge clk) + if (rst) + wrcal_prech_req <= #TCQ 1'b0; + else + // Combine requests from all stages here + wrcal_prech_req <= #TCQ cal2_prech_req_r; + + //*************************************************************************** + // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES + // NOTE: Written using discrete flops, but SRL can be used if the matching + // logic does the comparison sequentially, rather than parallel + //*************************************************************************** + + generate + genvar rd_i; + if (nCK_PER_CLK == 4) begin: gen_sr_div4 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; + sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; + sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; + sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; + sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i]; + sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i]; + sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i]; + sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i]; + end + end + end else if (nCK_PER_CLK == 2) begin: gen_sr_div2 + for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr + always @(posedge clk) begin + sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i]; + sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i]; + sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i]; + sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i]; + end + end + end + endgenerate + + //*************************************************************************** + // Write calibration: + // During write leveling DQS is aligned to the nearest CK edge that may not + // be the correct CK edge. Write calibration is required to align the DQS to + // the correct CK edge that clocks the write command. + // The Phaser_Out coarse delay line is adjusted if required to add a memory + // clock cycle of delay in order to read back the expected pattern. + //*************************************************************************** + + always @(posedge clk) begin + rd_active_r <= #TCQ phy_rddata_en; + rd_active_r1 <= #TCQ rd_active_r; + rd_active_r2 <= #TCQ rd_active_r1; + rd_active_r3 <= #TCQ rd_active_r2; + rd_active_r4 <= #TCQ rd_active_r3; + rd_active_r5 <= #TCQ rd_active_r4; + end + + //***************************************************************** + // Expected data pattern when properly received by read capture + // logic: + // Based on pattern of ({rise,fall}) = + // 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 + // Each nibble will look like: + // bit3: 1, 0, 1, 0, 0, 1, 1, 0 + // bit2: 1, 0, 0, 1, 1, 0, 0, 1 + // bit1: 1, 0, 1, 0, 0, 1, 0, 1 + // bit0: 1, 0, 0, 1, 1, 0, 1, 0 + // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN + // and the actual training pattern contents change + //***************************************************************** + + generate + if (nCK_PER_CLK == 4) begin: gen_pat_div4 + // FF00AA5555AA9966 + assign pat_rise0[3] = 1'b1; + assign pat_fall0[3] = 1'b0; + assign pat_rise1[3] = 1'b1; + assign pat_fall1[3] = 1'b0; + assign pat_rise2[3] = 1'b0; + assign pat_fall2[3] = 1'b1; + assign pat_rise3[3] = 1'b1; + assign pat_fall3[3] = 1'b0; + + assign pat_rise0[2] = 1'b1; + assign pat_fall0[2] = 1'b0; + assign pat_rise1[2] = 1'b0; + assign pat_fall1[2] = 1'b1; + assign pat_rise2[2] = 1'b1; + assign pat_fall2[2] = 1'b0; + assign pat_rise3[2] = 1'b0; + assign pat_fall3[2] = 1'b1; + + assign pat_rise0[1] = 1'b1; + assign pat_fall0[1] = 1'b0; + assign pat_rise1[1] = 1'b1; + assign pat_fall1[1] = 1'b0; + assign pat_rise2[1] = 1'b0; + assign pat_fall2[1] = 1'b1; + assign pat_rise3[1] = 1'b0; + assign pat_fall3[1] = 1'b1; + + assign pat_rise0[0] = 1'b1; + assign pat_fall0[0] = 1'b0; + assign pat_rise1[0] = 1'b0; + assign pat_fall1[0] = 1'b1; + assign pat_rise2[0] = 1'b1; + assign pat_fall2[0] = 1'b0; + assign pat_rise3[0] = 1'b1; + assign pat_fall3[0] = 1'b0; + + // Pattern to distinguish between early write and incorrect read + // BB11EE4444EEDD88 + assign early_rise0[3] = 1'b1; + assign early_fall0[3] = 1'b0; + assign early_rise1[3] = 1'b1; + assign early_fall1[3] = 1'b0; + assign early_rise2[3] = 1'b0; + assign early_fall2[3] = 1'b1; + assign early_rise3[3] = 1'b1; + assign early_fall3[3] = 1'b1; + + assign early_rise0[2] = 1'b0; + assign early_fall0[2] = 1'b0; + assign early_rise1[2] = 1'b1; + assign early_fall1[2] = 1'b1; + assign early_rise2[2] = 1'b1; + assign early_fall2[2] = 1'b1; + assign early_rise3[2] = 1'b1; + assign early_fall3[2] = 1'b0; + + assign early_rise0[1] = 1'b1; + assign early_fall0[1] = 1'b0; + assign early_rise1[1] = 1'b1; + assign early_fall1[1] = 1'b0; + assign early_rise2[1] = 1'b0; + assign early_fall2[1] = 1'b1; + assign early_rise3[1] = 1'b0; + assign early_fall3[1] = 1'b0; + + assign early_rise0[0] = 1'b1; + assign early_fall0[0] = 1'b1; + assign early_rise1[0] = 1'b0; + assign early_fall1[0] = 1'b0; + assign early_rise2[0] = 1'b0; + assign early_fall2[0] = 1'b0; + assign early_rise3[0] = 1'b1; + assign early_fall3[0] = 1'b0; + + end else if (nCK_PER_CLK == 2) begin: gen_pat_div2 + // First cycle pattern FF00AA55 + assign pat1_rise0[3] = 1'b1; + assign pat1_fall0[3] = 1'b0; + assign pat1_rise1[3] = 1'b1; + assign pat1_fall1[3] = 1'b0; + + assign pat1_rise0[2] = 1'b1; + assign pat1_fall0[2] = 1'b0; + assign pat1_rise1[2] = 1'b0; + assign pat1_fall1[2] = 1'b1; + + assign pat1_rise0[1] = 1'b1; + assign pat1_fall0[1] = 1'b0; + assign pat1_rise1[1] = 1'b1; + assign pat1_fall1[1] = 1'b0; + + assign pat1_rise0[0] = 1'b1; + assign pat1_fall0[0] = 1'b0; + assign pat1_rise1[0] = 1'b0; + assign pat1_fall1[0] = 1'b1; + + // Second cycle pattern 55AA9966 + assign pat2_rise0[3] = 1'b0; + assign pat2_fall0[3] = 1'b1; + assign pat2_rise1[3] = 1'b1; + assign pat2_fall1[3] = 1'b0; + + assign pat2_rise0[2] = 1'b1; + assign pat2_fall0[2] = 1'b0; + assign pat2_rise1[2] = 1'b0; + assign pat2_fall1[2] = 1'b1; + + assign pat2_rise0[1] = 1'b0; + assign pat2_fall0[1] = 1'b1; + assign pat2_rise1[1] = 1'b0; + assign pat2_fall1[1] = 1'b1; + + assign pat2_rise0[0] = 1'b1; + assign pat2_fall0[0] = 1'b0; + assign pat2_rise1[0] = 1'b1; + assign pat2_fall1[0] = 1'b0; + + //Pattern to distinguish between early write and incorrect read + // First cycle pattern AA5555AA + assign early1_rise0[3] = 2'b1; + assign early1_fall0[3] = 2'b0; + assign early1_rise1[3] = 2'b0; + assign early1_fall1[3] = 2'b1; + + assign early1_rise0[2] = 2'b0; + assign early1_fall0[2] = 2'b1; + assign early1_rise1[2] = 2'b1; + assign early1_fall1[2] = 2'b0; + + assign early1_rise0[1] = 2'b1; + assign early1_fall0[1] = 2'b0; + assign early1_rise1[1] = 2'b0; + assign early1_fall1[1] = 2'b1; + + assign early1_rise0[0] = 2'b0; + assign early1_fall0[0] = 2'b1; + assign early1_rise1[0] = 2'b1; + assign early1_fall1[0] = 2'b0; + + // Second cycle pattern 9966BB11 + assign early2_rise0[3] = 2'b1; + assign early2_fall0[3] = 2'b0; + assign early2_rise1[3] = 2'b1; + assign early2_fall1[3] = 2'b0; + + assign early2_rise0[2] = 2'b0; + assign early2_fall0[2] = 2'b1; + assign early2_rise1[2] = 2'b0; + assign early2_fall1[2] = 2'b0; + + assign early2_rise0[1] = 2'b0; + assign early2_fall0[1] = 2'b1; + assign early2_rise1[1] = 2'b1; + assign early2_fall1[1] = 2'b0; + + assign early2_rise0[0] = 2'b1; + assign early2_fall0[0] = 2'b0; + assign early2_rise1[0] = 2'b1; + assign early2_fall1[0] = 2'b1; + end + endgenerate + + // Each bit of each byte is compared to expected pattern. + // This was done to prevent (and "drastically decrease") the chance that + // invalid data clocked in when the DQ bus is tri-state (along with a + // combination of the correct data) will resemble the expected data + // pattern. A better fix for this is to change the training pattern and/or + // make the pattern longer. + generate + genvar pt_i; + if (nCK_PER_CLK == 4) begin: gen_pat_match_div4 + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4]) + pat_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4]) + pat_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4]) + pat_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4]) + pat_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4]) + pat_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4]) + pat_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4]) + pat_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + pat_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4]) + pat_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + pat_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4]) + early1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4]) + early1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4]) + early1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4]) + early1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4]) + early1_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4]) + early1_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == early_rise0[pt_i%4]) + early1_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == early_fall0[pt_i%4]) + early1_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4]) + early2_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4]) + early2_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4]) + early2_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4]) + early2_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall1_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise2_r[pt_i] == early_rise0[pt_i%4]) + early2_match_rise2_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise2_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall2_r[pt_i] == early_fall0[pt_i%4]) + early2_match_fall2_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall2_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise3_r[pt_i] == early_rise1[pt_i%4]) + early2_match_rise3_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise3_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall3_r[pt_i] == early_fall1[pt_i%4]) + early2_match_fall3_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall3_r[pt_i] <= #TCQ 1'b0; + end + end + + + always @(posedge clk) begin + pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r; + pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r; + pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r; + pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r; + pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r; + pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r; + pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r; + pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r; + pat_data_match_r <= #TCQ (pat_match_rise0_and_r && + pat_match_fall0_and_r && + pat_match_rise1_and_r && + pat_match_fall1_and_r && + pat_match_rise2_and_r && + pat_match_fall2_and_r && + pat_match_rise3_and_r && + pat_match_fall3_and_r); + pat_data_match_valid_r <= #TCQ rd_active_r3; + end + + always @(posedge clk) begin + early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; + early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; + early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; + early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; + early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r; + early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r; + early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r; + early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r; + early1_data_match_r <= #TCQ (early1_match_rise0_and_r && + early1_match_fall0_and_r && + early1_match_rise1_and_r && + early1_match_fall1_and_r && + early1_match_rise2_and_r && + early1_match_fall2_and_r && + early1_match_rise3_and_r && + early1_match_fall3_and_r); + end + + always @(posedge clk) begin + early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r; + early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r; + early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r; + early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r; + early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r; + early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r; + early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r; + early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r; + early2_data_match_r <= #TCQ (early2_match_rise0_and_r && + early2_match_fall0_and_r && + early2_match_rise1_and_r && + early2_match_fall1_and_r && + early2_match_rise2_and_r && + early2_match_fall2_and_r && + early2_match_rise3_and_r && + early2_match_fall3_and_r); + end + + end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2 + + for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4]) + pat1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4]) + pat1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4]) + pat1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4]) + pat1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4]) + pat2_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4]) + pat2_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4]) + pat2_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4]) + pat2_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + pat2_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4]) + early1_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4]) + early1_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4]) + early1_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4]) + early1_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early1_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + + // early2 in this case does not mean 2 cycles early but + // the second cycle of read data in 2:1 mode + always @(posedge clk) begin + if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4]) + early2_match_rise0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise0_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4]) + early2_match_fall0_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall0_r[pt_i] <= #TCQ 1'b0; + + if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4]) + early2_match_rise1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_rise1_r[pt_i] <= #TCQ 1'b0; + + if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4]) + early2_match_fall1_r[pt_i] <= #TCQ 1'b1; + else + early2_match_fall1_r[pt_i] <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r; + pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r; + pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r; + pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r; + pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r && + pat1_match_fall0_and_r && + pat1_match_rise1_and_r && + pat1_match_fall1_and_r); + pat1_data_match_r1 <= #TCQ pat1_data_match_r; + + pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3; + pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3; + pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3; + pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3; + pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r && + pat2_match_fall0_and_r && + pat2_match_rise1_and_r && + pat2_match_fall1_and_r); + + // For 2:1 mode, read valid is asserted for 2 clock cycles - + // here we generate a "match valid" pulse that is only 1 clock + // cycle wide that is simulatenous when the match calculation + // is complete + pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5; + end + + always @(posedge clk) begin + early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r; + early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r; + early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r; + early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r; + early1_data_match_r <= #TCQ (early1_match_rise0_and_r && + early1_match_fall0_and_r && + early1_match_rise1_and_r && + early1_match_fall1_and_r); + early1_data_match_r1 <= #TCQ early1_data_match_r; + + early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3; + early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3; + early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3; + early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3; + early2_data_match_r <= #TCQ (early2_match_rise0_and_r && + early2_match_fall0_and_r && + early2_match_rise1_and_r && + early2_match_fall1_and_r); + end + + end + endgenerate + + // Need to delay it by 3 cycles in order to wait for Phaser_Out + // coarse delay to take effect before issuing a write command + always @(posedge clk) begin + wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r; + wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1; + wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2; + end + + always @(posedge clk) begin + if (rst) + tap_inc_wait_cnt <= #TCQ 'd0; + else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) || + (cal2_state_r == CAL2_IFIFO_RESET) || + (cal2_state_r == CAL2_SANITY_WAIT)) + tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1; + else + tap_inc_wait_cnt <= #TCQ 'd0; + end + + always @(posedge clk) begin + if (rst) + not_empty_wait_cnt <= #TCQ 'd0; + else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait) + not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1; + else + not_empty_wait_cnt <= #TCQ 'd0; + end + + always @(posedge clk) + cal2_state_r1 <= #TCQ cal2_state_r; + + //***************************************************************** + // Write Calibration state machine + //***************************************************************** + + // when calibrating, check to see if the expected pattern is received. + // Otherwise delay DQS to align to correct CK edge. + // NOTES: + // 1. An error condition can occur due to two reasons: + // a. If the matching logic does not receive the expected data + // pattern. However, the error may be "recoverable" because + // the write calibration is still in progress. If an error is + // found the write calibration logic delays DQS by an additional + // clock cycle and restarts the pattern detection process. + // By design, if the write path timing is incorrect, the correct + // data pattern will never be detected. + // b. Valid data not found even after incrementing Phaser_Out + // coarse delay line. + + + always @(posedge clk) begin + if (rst) begin + wrcal_dqs_cnt_r <= #TCQ 'b0; + cal2_done_r <= #TCQ 1'b0; + cal2_prech_req_r <= #TCQ 1'b0; + cal2_state_r <= #TCQ CAL2_IDLE; + wrcal_pat_err <= #TCQ 1'b0; + wrcal_pat_resume_r <= #TCQ 1'b0; + wrcal_act_req <= #TCQ 1'b0; + cal2_if_reset <= #TCQ 1'b0; + temp_wrcal_done <= #TCQ 1'b0; + wrlvl_byte_redo <= #TCQ 1'b0; + early1_data <= #TCQ 1'b0; + early2_data <= #TCQ 1'b0; + idelay_ld <= #TCQ 1'b0; + idelay_ld_done <= #TCQ 1'b0; + pat1_detect <= #TCQ 1'b0; + early1_detect <= #TCQ 1'b0; + wrcal_sanity_chk_done <= #TCQ 1'b0; + wrcal_sanity_chk_err <= #TCQ 1'b0; + end else begin + cal2_prech_req_r <= #TCQ 1'b0; + case (cal2_state_r) + CAL2_IDLE: begin + wrcal_pat_err <= #TCQ 1'b0; + if (wrcal_start) begin + cal2_if_reset <= #TCQ 1'b0; + if (SIM_CAL_OPTION == "SKIP_CAL") + // If skip write calibration, then proceed to end. + cal2_state_r <= #TCQ CAL2_DONE; + else + cal2_state_r <= #TCQ CAL2_READ_WAIT; + end + end + + // General wait state to wait for read data to be output by the + // IN_FIFO + CAL2_READ_WAIT: begin + wrcal_pat_resume_r <= #TCQ 1'b0; + cal2_if_reset <= #TCQ 1'b0; + // Wait until read data is received, and pattern matching + // calculation is complete. NOTE: Need to add a timeout here + // in case for some reason data is never received (or rather + // the PHASER_IN and IN_FIFO think they never receives data) + if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin + if (pat_data_match_r) + // If found data match, then move on to next DQS group + cal2_state_r <= #TCQ CAL2_NEXT_DQS; + else begin + if (wrcal_sanity_chk_r) + cal2_state_r <= #TCQ CAL2_ERR; + // If writes are one or two cycles early then redo + // write leveling for the byte + else if (early1_data_match_r) begin + early1_data <= #TCQ 1'b1; + early2_data <= #TCQ 1'b0; + wrlvl_byte_redo <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; + end else if (early2_data_match_r) begin + early1_data <= #TCQ 1'b0; + early2_data <= #TCQ 1'b1; + wrlvl_byte_redo <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; + // Read late due to incorrect MPR idelay value + // Decrement Idelay to '0'for the current byte + end else if (~idelay_ld_done) begin + cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; + idelay_ld <= #TCQ 1'b1; + end else + cal2_state_r <= #TCQ CAL2_ERR; + end + end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin + if ((pat1_data_match_r1 && pat2_data_match_r) || + (pat1_detect && pat2_data_match_r)) + // If found data match, then move on to next DQS group + cal2_state_r <= #TCQ CAL2_NEXT_DQS; + else if (pat1_data_match_r1 && ~pat2_data_match_r) begin + cal2_state_r <= #TCQ CAL2_READ_WAIT; + pat1_detect <= #TCQ 1'b1; + end else begin + // If writes are one or two cycles early then redo + // write leveling for the byte + if (wrcal_sanity_chk_r) + cal2_state_r <= #TCQ CAL2_ERR; + else if ((early1_data_match_r1 && early2_data_match_r) || + (early1_detect && early2_data_match_r)) begin + early1_data <= #TCQ 1'b1; + early2_data <= #TCQ 1'b0; + wrlvl_byte_redo <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_WRLVL_WAIT; + end else if (early1_data_match_r1 && ~early2_data_match_r) begin + early1_detect <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_READ_WAIT; + // Read late due to incorrect MPR idelay value + // Decrement Idelay to '0'for the current byte + end else if (~idelay_ld_done) begin + cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC; + idelay_ld <= #TCQ 1'b1; + end else + cal2_state_r <= #TCQ CAL2_ERR; + end + end else if (not_empty_wait_cnt == 'd31) + cal2_state_r <= #TCQ CAL2_ERR; + end + + CAL2_WRLVL_WAIT: begin + early1_detect <= #TCQ 1'b0; + if (wrlvl_byte_done && ~wrlvl_byte_done_r) + wrlvl_byte_redo <= #TCQ 1'b0; + if (wrlvl_byte_done) begin + if (rd_active_r1 && ~rd_active_r) begin + cal2_state_r <= #TCQ CAL2_IFIFO_RESET; + cal2_if_reset <= #TCQ 1'b1; + early1_data <= #TCQ 1'b0; + early2_data <= #TCQ 1'b0; + end + end + end + + CAL2_DQ_IDEL_DEC: begin + if (tap_inc_wait_cnt == 'd4) begin + idelay_ld <= #TCQ 1'b0; + cal2_state_r <= #TCQ CAL2_IFIFO_RESET; + cal2_if_reset <= #TCQ 1'b1; + idelay_ld_done <= #TCQ 1'b1; + end + end + + CAL2_IFIFO_RESET: begin + if (tap_inc_wait_cnt == 'd15) begin + cal2_if_reset <= #TCQ 1'b0; + if (wrcal_sanity_chk_r) + cal2_state_r <= #TCQ CAL2_DONE; + else if (idelay_ld_done) begin + wrcal_pat_resume_r <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_READ_WAIT; + end else + cal2_state_r <= #TCQ CAL2_IDLE; + end + end + + // Final processing for current DQS group. Move on to next group + CAL2_NEXT_DQS: begin + // At this point, we've just found the correct pattern for the + // current DQS group. + + // Request bank/row precharge, and wait for its completion. Always + // precharge after each DQS group to avoid tRAS(max) violation + //verilint STARC-2.2.3.3 off + if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin + cal2_prech_req_r <= #TCQ 1'b0; + wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; + cal2_state_r <= #TCQ CAL2_SANITY_WAIT; + end else + cal2_prech_req_r <= #TCQ 1'b1; + idelay_ld_done <= #TCQ 1'b0; + pat1_detect <= #TCQ 1'b0; + if (prech_done) + if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) || + (wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin + // If either FAST_CAL is enabled and first DQS group is + // finished, or if the last DQS group was just finished, + // then end of write calibration + if (wrcal_sanity_chk_r) begin + cal2_if_reset <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_IFIFO_RESET; + end else + cal2_state_r <= #TCQ CAL2_DONE; + end else begin + // Continue to next DQS group + wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1; + cal2_state_r <= #TCQ CAL2_READ_WAIT; + end + end + //verilint STARC-2.2.3.3 on + CAL2_SANITY_WAIT: begin + if (tap_inc_wait_cnt == 'd15) begin + cal2_state_r <= #TCQ CAL2_READ_WAIT; + wrcal_pat_resume_r <= #TCQ 1'b1; + end + end + + // Finished with read enable calibration + CAL2_DONE: begin + if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin + cal2_done_r <= #TCQ 1'b0; + wrcal_dqs_cnt_r <= #TCQ 'd0; + cal2_state_r <= #TCQ CAL2_IDLE; + end else + cal2_done_r <= #TCQ 1'b1; + cal2_prech_req_r <= #TCQ 1'b0; + cal2_if_reset <= #TCQ 1'b0; + if (wrcal_sanity_chk_r) + wrcal_sanity_chk_done <= #TCQ 1'b1; + end + + // Assert error signal indicating that writes timing is incorrect + CAL2_ERR: begin + wrcal_pat_resume_r <= #TCQ 1'b0; + if (wrcal_sanity_chk_r) + wrcal_sanity_chk_err <= #TCQ 1'b1; + else + wrcal_pat_err <= #TCQ 1'b1; + cal2_state_r <= #TCQ CAL2_ERR; + end + endcase + end + end + + // Delay assertion of wrcal_done for write calibration by a few cycles after + // we've reached CAL2_DONE + always @(posedge clk) + if (rst) + cal2_done_r1 <= #TCQ 1'b0; + else + cal2_done_r1 <= #TCQ cal2_done_r; + + always @(posedge clk) + if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r)) + wrcal_done <= #TCQ 1'b0; + else if (cal2_done_r) + wrcal_done <= #TCQ 1'b1; + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v new file mode 100644 index 0000000..931dc32 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v @@ -0,0 +1,1219 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_wrlvl.v +// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ +// \ \ / \ Date Created: Mon Jun 23 2008 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: +// Memory initialization and overall master state control during +// initialization and calibration. Specifically, the following functions +// are performed: +// 1. Memory initialization (initial AR, mode register programming, etc.) +// 2. Initiating write leveling +// 3. Generate training pattern writes for read leveling. Generate +// memory readback for read leveling. +// This module has a DFI interface for providing control/address and write +// data to the rest of the PHY datapath during initialization/calibration. +// Once initialization is complete, control is passed to the MC. +// NOTES: +// 1. Multiple CS (multi-rank) not supported +// 2. DDR2 not supported +// 3. ODT not supported +//Reference: +//Revision History: +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $ +**$Date: 2011/06/24 14:49:00 $ +**$Author: mgeorge $ +**$Revision: 1.3 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $ +******************************************************************************/ + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_wrlvl # + ( + parameter TCQ = 100, + parameter DQS_CNT_WIDTH = 3, + parameter DQ_WIDTH = 64, + parameter DQS_WIDTH = 2, + parameter DRAM_WIDTH = 8, + parameter RANKS = 1, + parameter nCK_PER_CLK = 4, + parameter CLK_PERIOD = 4, + parameter SIM_CAL_OPTION = "NONE" + ) + ( + input clk, + input rst, + input phy_ctl_ready, + input wr_level_start, + input wl_sm_start, + input wrlvl_final, + input wrlvl_byte_redo, + input [DQS_CNT_WIDTH:0] wrcal_cnt, + input early1_data, + input early2_data, + input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt, + input oclkdelay_calib_done, + input [(DQ_WIDTH)-1:0] rd_data_rise0, + output reg wrlvl_byte_done, + output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */, + output phy_ctl_rdy_dly, + output reg wr_level_done /* synthesis syn_maxfan = 2 */, + // to phy_init for cs logic + output wrlvl_rank_done, + output done_dqs_tap_inc, + output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt, + // Fine delay line used only during write leveling + // Inc/dec Phaser_Out fine delay line + output reg dqs_po_stg2_f_incdec, + // Enable Phaser_Out fine delay inc/dec + output reg dqs_po_en_stg2_f, + // Coarse delay line used during write leveling + // only if 64 taps of fine delay line were not + // sufficient to detect a 0->1 transition + // Inc Phaser_Out coarse delay line + output reg dqs_wl_po_stg2_c_incdec, + // Enable Phaser_Out coarse delay inc/dec + output reg dqs_wl_po_en_stg2_c, + // Read Phaser_Out delay value + input [8:0] po_counter_read_val, +// output reg dqs_wl_po_stg2_load, +// output reg [8:0] dqs_wl_po_stg2_reg_l, + // CK edge undetected + output reg wrlvl_err, + output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt, + output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt, + // Debug ports + output [5:0] dbg_wl_tap_cnt, + output dbg_wl_edge_detect_valid, + output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect, + output [DQS_CNT_WIDTH:0] dbg_dqs_count, + output [4:0] dbg_wl_state, + output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, + output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, + output [255:0] dbg_phy_wrlvl + ); + + + localparam WL_IDLE = 5'h0; + localparam WL_INIT = 5'h1; + localparam WL_INIT_FINE_INC = 5'h2; + localparam WL_INIT_FINE_INC_WAIT1= 5'h3; + localparam WL_INIT_FINE_INC_WAIT = 5'h4; + localparam WL_INIT_FINE_DEC = 5'h5; + localparam WL_INIT_FINE_DEC_WAIT = 5'h6; + localparam WL_FINE_INC = 5'h7; + localparam WL_WAIT = 5'h8; + localparam WL_EDGE_CHECK = 5'h9; + localparam WL_DQS_CHECK = 5'hA; + localparam WL_DQS_CNT = 5'hB; + localparam WL_2RANK_TAP_DEC = 5'hC; + localparam WL_2RANK_DQS_CNT = 5'hD; + localparam WL_FINE_DEC = 5'hE; + localparam WL_FINE_DEC_WAIT = 5'hF; + localparam WL_CORSE_INC = 5'h10; + localparam WL_CORSE_INC_WAIT = 5'h11; + localparam WL_CORSE_INC_WAIT1 = 5'h12; + localparam WL_CORSE_INC_WAIT2 = 5'h13; + localparam WL_CORSE_DEC = 5'h14; + localparam WL_CORSE_DEC_WAIT = 5'h15; + localparam WL_CORSE_DEC_WAIT1 = 5'h16; + localparam WL_FINE_INC_WAIT = 5'h17; + localparam WL_2RANK_FINAL_TAP = 5'h18; + localparam WL_INIT_FINE_DEC_WAIT1= 5'h19; + localparam WL_FINE_DEC_WAIT1 = 5'h1A; + localparam WL_CORSE_INC_WAIT_TMP = 5'h1B; + + localparam COARSE_TAPS = 7; + + localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48; + localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2; + localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5; + + + integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y; + + reg phy_ctl_ready_r1; + reg phy_ctl_ready_r2; + reg phy_ctl_ready_r3; + reg phy_ctl_ready_r4; + reg phy_ctl_ready_r5; + reg phy_ctl_ready_r6; + (* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r; + reg [1:0] rank_cnt_r; + reg [DQS_WIDTH-1:0] rd_data_rise_wl_r; + reg [DQS_WIDTH-1:0] rd_data_previous_r; + reg [DQS_WIDTH-1:0] rd_data_edge_detect_r; + reg wr_level_done_r; + reg wrlvl_rank_done_r; + reg wr_level_start_r; + reg [4:0] wl_state_r, wl_state_r1; + reg inhibit_edge_detect_r; + reg wl_edge_detect_valid_r; + reg [5:0] wl_tap_count_r; + reg [5:0] fine_dec_cnt; + reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each + reg [2:0] corse_dec[0:DQS_WIDTH-1]; + reg [2:0] corse_inc[0:DQS_WIDTH-1]; + reg dq_cnt_inc; + reg [3:0] stable_cnt; + reg flag_ck_negedge; + //reg past_negedge; + reg flag_init; + reg [2:0] corse_cnt[0:DQS_WIDTH-1]; + reg [3*DQS_WIDTH-1:0] corse_cnt_dbg; + reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1]; + //reg [3*DQS_WIDTH-1:0] coarse_tap_inc; + reg [2:0] final_coarse_tap[0:DQS_WIDTH-1]; + reg [5:0] add_smallest[0:DQS_WIDTH-1]; + reg [5:0] add_largest[0:DQS_WIDTH-1]; + //reg [6*DQS_WIDTH-1:0] fine_tap_inc; + //reg [6*DQS_WIDTH-1:0] fine_tap_dec; + reg wr_level_done_r1; + reg wr_level_done_r2; + reg wr_level_done_r3; + reg wr_level_done_r4; + reg wr_level_done_r5; + reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1]; + reg [5:0] smallest[0:DQS_WIDTH-1]; + reg [5:0] largest[0:DQS_WIDTH-1]; + reg [5:0] final_val[0:DQS_WIDTH-1]; + reg [5:0] po_dec_cnt[0:DQS_WIDTH-1]; + reg done_dqs_dec; + reg [8:0] po_rdval_cnt; + reg po_cnt_dec; + reg po_dec_done; + reg dual_rnk_dec; + wire [DQS_CNT_WIDTH+2:0] dqs_count_w; + reg [5:0] fast_cal_fine_cnt; + reg [2:0] fast_cal_coarse_cnt; + reg wrlvl_byte_redo_r; + reg [2:0] wrlvl_redo_corse_inc; + reg wrlvl_final_r; + reg final_corse_dec; + wire [DQS_CNT_WIDTH+2:0] oclk_count_w; + reg wrlvl_tap_done_r ; + reg [3:0] wait_cnt; + reg [3:0] incdec_wait_cnt; + + + + // Debug ports + assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r; + assign dbg_rd_data_edge_detect = rd_data_edge_detect_r; + assign dbg_wl_tap_cnt = wl_tap_count_r; + assign dbg_dqs_count = dqs_count_r; + assign dbg_wl_state = wl_state_r; + assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt; + assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt; + + always @(*) begin + for (v = 0; v < DQS_WIDTH; v = v + 1) + corse_cnt_dbg[3*v+:3] = corse_cnt[v]; + end + + assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg; + assign dbg_phy_wrlvl[27+:5] = wl_state_r; + assign dbg_phy_wrlvl[32+:4] = dqs_count_r; + assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r; + assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r; + assign dbg_phy_wrlvl[54+:4] = stable_cnt; + assign dbg_phy_wrlvl[58] = 'd0; + assign dbg_phy_wrlvl[59] = flag_ck_negedge; + + assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r; + assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r; + assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r; + assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt; + assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt; + + + + //************************************************************************** + // DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay + //************************************************************************** + assign po_stg2_wl_cnt = dqs_count_r; + + assign wrlvl_rank_done = wrlvl_rank_done_r; + + assign done_dqs_tap_inc = done_dqs_dec; + + assign phy_ctl_rdy_dly = phy_ctl_ready_r6; + + always @(posedge clk) begin + phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; + phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; + phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; + phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; + phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; + phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; + wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo; + wrlvl_final_r <= #TCQ wrlvl_final; + if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) || + (wrlvl_final && ~wrlvl_final_r)) + wr_level_done <= #TCQ 1'b0; + else + wr_level_done <= #TCQ done_dqs_dec; + end + +// Status signal that will be asserted once the first +// pass of write leveling is done. + always @(posedge clk) begin + if(rst) begin + wrlvl_tap_done_r <= #TCQ 1'b0 ; + end else begin + if(wrlvl_tap_done_r == 1'b0) begin + if(oclkdelay_calib_done) begin + wrlvl_tap_done_r <= #TCQ 1'b1 ; + end + end + end + end + + always @(posedge clk) begin + if (rst || po_cnt_dec) + wait_cnt <= #TCQ 'd8; + else if (phy_ctl_ready_r6 && (wait_cnt > 'd0)) + wait_cnt <= #TCQ wait_cnt - 1; + end + + always @(posedge clk) begin + if (rst) begin + po_rdval_cnt <= #TCQ 'd0; + end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin + po_rdval_cnt <= #TCQ po_counter_read_val; + end else if (po_rdval_cnt > 'd0) begin + if (po_cnt_dec) + po_rdval_cnt <= #TCQ po_rdval_cnt - 1; + else + po_rdval_cnt <= #TCQ po_rdval_cnt; + end else if (po_rdval_cnt == 'd0) begin + po_rdval_cnt <= #TCQ po_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (po_rdval_cnt == 'd0)) + po_cnt_dec <= #TCQ 1'b0; + else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1)) + po_cnt_dec <= #TCQ 1'b1; + else + po_cnt_dec <= #TCQ 1'b0; + end + + always @(posedge clk) begin + if (rst) + po_dec_done <= #TCQ 1'b0; + else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || + (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin + po_dec_done <= #TCQ 1'b1; + end + end + + + always @(posedge clk) begin + dqs_po_dec_done <= #TCQ po_dec_done; + wr_level_done_r1 <= #TCQ wr_level_done_r; + wr_level_done_r2 <= #TCQ wr_level_done_r1; + wr_level_done_r3 <= #TCQ wr_level_done_r2; + wr_level_done_r4 <= #TCQ wr_level_done_r3; + wr_level_done_r5 <= #TCQ wr_level_done_r4; + for (l = 0; l < DQS_WIDTH; l = l + 1) begin + wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l]; + if ((RANKS == 1) || ~oclkdelay_calib_done) + wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l]; + else + wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l]; + end + end + + generate + if (RANKS == 2) begin: dual_rank + always @(posedge clk) begin + if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || + (wrlvl_final && ~wrlvl_final_r)) + done_dqs_dec <= #TCQ 1'b0; + else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done) + done_dqs_dec <= #TCQ wr_level_done_r; + else if (wr_level_done_r5 && (wl_state_r == WL_IDLE)) + done_dqs_dec <= #TCQ 1'b1; + end + end else begin: single_rank + always @(posedge clk) begin + if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) || + (wrlvl_final && ~wrlvl_final_r)) + done_dqs_dec <= #TCQ 1'b0; + else if (~oclkdelay_calib_done) + done_dqs_dec <= #TCQ wr_level_done_r; + else if (wr_level_done_r3 && ~wr_level_done_r4) + done_dqs_dec <= #TCQ 1'b1; + end + end + endgenerate + + always @(posedge clk) + if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r)) + wrlvl_byte_done <= #TCQ 1'b0; + else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4) + wrlvl_byte_done <= #TCQ 1'b1; + + // Storing DQS tap values at the end of each DQS write leveling + always @(posedge clk) begin + if (rst) begin + for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop + for (n = 0; n < DQS_WIDTH; n = n + 1) begin + wl_corse_cnt[k][n] <= #TCQ 'b0; + wl_dqs_tap_count_r[k][n] <= #TCQ 'b0; + end + end + end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) | + (wl_state_r == WL_FINE_DEC_WAIT1) | + (wl_state_r == WL_2RANK_TAP_DEC)) begin + wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r; + wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r]; + end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin + for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt + for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt + wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r; + wl_corse_cnt[p][q] <= #TCQ corse_cnt[0]; + end + end + end + end + + // Convert coarse delay to fine taps in case of unequal number of coarse + // taps between ranks. Assuming a difference of 1 coarse tap counts + // between ranks. A common fine and coarse tap value must be used for both ranks + // because Phaser_Out has only one rank register. + // Coarse tap1 = period(ps)*93/360 = 34 fine taps + // Other coarse taps = period(ps)*103/360 = 38 fine taps + + generate + genvar cnt; + if (RANKS == 2) begin // Dual rank + for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt + always @(posedge clk) begin + if (rst) begin + //coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0; + add_smallest[cnt] <= #TCQ 'd0; + add_largest[cnt] <= #TCQ 'd0; + final_coarse_tap[cnt] <= #TCQ 'd0; + end else if (wr_level_done_r1 & ~wr_level_done_r2) begin + if (~oclkdelay_calib_done) begin + for(y = 0 ; y < DQS_WIDTH; y = y+1) begin + final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y]; + add_smallest[y] <= #TCQ 'd0; + add_largest[y] <= #TCQ 'd0; + end + end else + if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin + // Both ranks have use the same number of coarse delay taps. + // No conversion of coarse tap to fine taps required. + //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3]; + final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; + add_smallest[cnt] <= #TCQ 'd0; + add_largest[cnt] <= #TCQ 'd0; + end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin + // Rank 0 uses fewer coarse delay taps than rank1. + // conversion of coarse tap to fine taps required for rank1. + // The final coarse count will the smaller value. + //coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1; + final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1; + if (|wl_corse_cnt[0][cnt]) + // Coarse tap 2 or higher being converted to fine taps + // This will be added to 'largest' value in final_val + // computation + add_largest[cnt] <= #TCQ 'd38; + else + // Coarse tap 1 being converted to fine taps + // This will be added to 'largest' value in final_val + // computation + add_largest[cnt] <= #TCQ 'd34; + end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin + // This may be an unlikely scenario in a real system. + // Rank 0 uses more coarse delay taps than rank1. + // conversion of coarse tap to fine taps required. + //coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0; + final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt]; + if (|wl_corse_cnt[1][cnt]) + // Coarse tap 2 or higher being converted to fine taps + // This will be added to 'smallest' value in final_val + // computation + add_smallest[cnt] <= #TCQ 'd38; + else + // Coarse tap 1 being converted to fine taps + // This will be added to 'smallest' value in + // final_val computation + add_smallest[cnt] <= #TCQ 'd34; + end + end + end + end + end else begin + // Single rank + always @(posedge clk) begin + //coarse_tap_inc <= #TCQ 'd0; + for(w = 0; w < DQS_WIDTH; w = w + 1) begin + final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w]; + add_smallest[w] <= #TCQ 'd0; + add_largest[w] <= #TCQ 'd0; + end + end + end + endgenerate + + + // Determine delay value for DQS in multirank system + // Assuming delay value is the smallest for rank 0 DQS + // and largest delay value for rank 4 DQS + // Set to smallest + ((largest-smallest)/2) + always @(posedge clk) begin + if (rst) begin + for(x = 0; x < DQS_WIDTH; x = x +1) begin + smallest[x] <= #TCQ 'b0; + largest[x] <= #TCQ 'b0; + end + end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin + smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; + largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; + end else if ((wl_state_r == WL_DQS_CNT) | + (wl_state_r == WL_2RANK_TAP_DEC)) begin + smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r]; + largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r]; + end else if (((SIM_CAL_OPTION == "FAST_CAL") | + (~oclkdelay_calib_done & ~wrlvl_byte_redo)) & + wr_level_done_r1 & ~wr_level_done_r2) begin + for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs + smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; + largest[i] <= #TCQ wl_dqs_tap_count_r[0][i]; + end + end + end + + +// final_val to be used for all DQSs in all ranks + genvar wr_i; + generate + for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap + always @(posedge clk) begin + if (rst) + final_val[wr_i] <= #TCQ 'b0; + else if (wr_level_done_r2 && ~wr_level_done_r3) begin + if (~oclkdelay_calib_done) + final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]); + else if ((smallest[wr_i] + add_smallest[wr_i]) < + (largest[wr_i] + add_largest[wr_i])) + final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) + + (((largest[wr_i] + add_largest[wr_i]) - + (smallest[wr_i] + add_smallest[wr_i]))/2)); + else if ((smallest[wr_i] + add_smallest[wr_i]) > + (largest[wr_i] + add_largest[wr_i])) + final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) + + (((smallest[wr_i] + add_smallest[wr_i]) - + (largest[wr_i] + add_largest[wr_i]))/2)); + else if ((smallest[wr_i] + add_smallest[wr_i]) == + (largest[wr_i] + add_largest[wr_i])) + final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]); + end + end + end + endgenerate + +// // fine tap inc/dec value for all DQSs in all ranks +// genvar dqs_i; +// generate +// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap +// always @(posedge clk) begin +// if (rst) +// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0; +// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; +// else if (wr_level_done_r3 && ~wr_level_done_r4) begin +// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6]; +// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0; +// end +// end +// endgenerate + + + // Inc/Dec Phaser_Out stage 2 fine delay line + always @(posedge clk) begin + if (rst) begin + // Fine delay line used only during write leveling + dqs_po_stg2_f_incdec <= #TCQ 1'b0; + dqs_po_en_stg2_f <= #TCQ 1'b0; + // Dec Phaser_Out fine delay (1)before write leveling, + // (2)if no 0 to 1 transition detected with 63 fine delay taps, or + // (3)dual rank case where fine taps for the first rank need to be 0 + end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) || + (wl_state_r == WL_FINE_DEC)) begin + dqs_po_stg2_f_incdec <= #TCQ 1'b0; + dqs_po_en_stg2_f <= #TCQ 1'b1; + // Inc Phaser_Out fine delay during write leveling + end else if ((wl_state_r == WL_INIT_FINE_INC) || + (wl_state_r == WL_FINE_INC)) begin + dqs_po_stg2_f_incdec <= #TCQ 1'b1; + dqs_po_en_stg2_f <= #TCQ 1'b1; + end else begin + dqs_po_stg2_f_incdec <= #TCQ 1'b0; + dqs_po_en_stg2_f <= #TCQ 1'b0; + end + end + + + // Inc Phaser_Out stage 2 Coarse delay line + always @(posedge clk) begin + if (rst) begin + // Coarse delay line used during write leveling + // only if no 0->1 transition undetected with 64 + // fine delay line taps + dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; + dqs_wl_po_en_stg2_c <= #TCQ 1'b0; + end else if (wl_state_r == WL_CORSE_INC) begin + // Inc Phaser_Out coarse delay during write leveling + dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1; + dqs_wl_po_en_stg2_c <= #TCQ 1'b1; + end else begin + dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0; + dqs_wl_po_en_stg2_c <= #TCQ 1'b0; + end + end + + + // only storing the rise data for checking. The data comming back during + // write leveling will be a static value. Just checking for rise data is + // enough. + +genvar rd_i; +generate + for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd + always @(posedge clk) + rd_data_rise_wl_r[rd_i] <= + #TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH]; + end +endgenerate + + + // storing the previous data for checking later. + always @(posedge clk)begin + if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) || + //(wl_state_r == WL_INIT_FINE_INC_WAIT1) || + ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) || + (wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) || + (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || + (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) || + ((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r))) + rd_data_previous_r <= #TCQ rd_data_rise_wl_r; + end + + // changed stable count from 3 to 7 because of fine tap resolution + always @(posedge clk)begin + if (rst | (wl_state_r == WL_DQS_CNT) | + (wl_state_r == WL_2RANK_TAP_DEC) | + (wl_state_r == WL_FINE_DEC) | + (rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) | + (wl_state_r1 == WL_INIT_FINE_DEC)) + stable_cnt <= #TCQ 'd0; + else if ((wl_tap_count_r > 6'd0) & + (((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) | + ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin + if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r]) + & (stable_cnt < 'd14)) + stable_cnt <= #TCQ stable_cnt + 1; + end + end + + // Signal to ensure that flag_ck_negedge does not incorrectly assert + // when DQS is very close to CK rising edge + //always @(posedge clk) begin + // if (rst | (wl_state_r == WL_DQS_CNT) | + // (wl_state_r == WL_DQS_CHECK) | wr_level_done_r) + // past_negedge <= #TCQ 1'b0; + // else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] && + // (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) | + // (wl_state_r == WL_CORSE_INC_WAIT2))) + // past_negedge <= #TCQ 1'b1; + //end + + // Flag to indicate negedge of CK detected and ignore 0->1 transitions + // in this region + always @(posedge clk)begin + if (rst | (wl_state_r == WL_DQS_CNT) | + (wl_state_r == WL_DQS_CHECK) | wr_level_done_r | + (wl_state_r1 == WL_INIT_FINE_DEC)) + flag_ck_negedge <= #TCQ 1'd0; + else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) | + (wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) | + (wl_state_r == WL_CORSE_INC)) + flag_ck_negedge <= #TCQ 1'd1; + else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14)) + //&& flag_ck_negedge) + flag_ck_negedge <= #TCQ 1'd0; + end + + // Flag to inhibit rd_data_edge_detect_r before stable DQ + always @(posedge clk) begin + if (rst) + flag_init <= #TCQ 1'b1; + else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) || + (wl_state_r1 == WL_INIT_FINE_DEC_WAIT))) + flag_init <= #TCQ 1'b0; + end + + //checking for transition from 0 to 1 + always @(posedge clk)begin + if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) | + inhibit_edge_detect_r) + rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; + else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin + if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) || + (wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) || + (wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2)) + rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; + else + rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r; + end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14)) + rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}}; + else + rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r); + end + + + + // registring the write level start signal + always@(posedge clk) begin + wr_level_start_r <= #TCQ wr_level_start; + end + + // Assign dqs_count_r to dqs_count_w to perform the shift operation + // instead of multiply operation + assign dqs_count_w = {2'b00, dqs_count_r}; + + assign oclk_count_w = {2'b00, oclkdelay_calib_cnt}; + + always @(posedge clk) begin + if (rst) + incdec_wait_cnt <= #TCQ 'd0; + else if ((wl_state_r == WL_FINE_DEC_WAIT1) || + (wl_state_r == WL_INIT_FINE_DEC_WAIT1) || + (wl_state_r == WL_CORSE_INC_WAIT_TMP)) + incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1; + else + incdec_wait_cnt <= #TCQ 'd0; + end + + + // state machine to initiate the write leveling sequence + // The state machine operates on one byte at a time. + // It will increment the delays to the DQS OSERDES + // and sample the DQ from the memory. When it detects + // a transition from 1 to 0 then the write leveling is considered + // done. + always @(posedge clk) begin + if(rst)begin + wrlvl_err <= #TCQ 1'b0; + wr_level_done_r <= #TCQ 1'b0; + wrlvl_rank_done_r <= #TCQ 1'b0; + dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}}; + dq_cnt_inc <= #TCQ 1'b1; + rank_cnt_r <= #TCQ 2'b00; + wl_state_r <= #TCQ WL_IDLE; + wl_state_r1 <= #TCQ WL_IDLE; + inhibit_edge_detect_r <= #TCQ 1'b1; + wl_edge_detect_valid_r <= #TCQ 1'b0; + wl_tap_count_r <= #TCQ 6'd0; + fine_dec_cnt <= #TCQ 6'd0; + for (r = 0; r < DQS_WIDTH; r = r + 1) begin + fine_inc[r] <= #TCQ 6'b0; + corse_dec[r] <= #TCQ 3'b0; + corse_inc[r] <= #TCQ 3'b0; + corse_cnt[r] <= #TCQ 3'b0; + end + dual_rnk_dec <= #TCQ 1'b0; + fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE; + fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE; + final_corse_dec <= #TCQ 1'b0; + //zero_tran_r <= #TCQ 1'b0; + wrlvl_redo_corse_inc <= #TCQ 'd0; + end else begin + wl_state_r1 <= #TCQ wl_state_r; + case (wl_state_r) + + WL_IDLE: begin + wrlvl_rank_done_r <= #TCQ 1'd0; + inhibit_edge_detect_r <= #TCQ 1'b1; + if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin + wr_level_done_r <= #TCQ 1'b0; + dqs_count_r <= #TCQ wrcal_cnt; + corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt]; + wl_tap_count_r <= #TCQ smallest[wrcal_cnt]; + if (early1_data && + (((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) || + ((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500)))) + wrlvl_redo_corse_inc <= #TCQ REDO_COARSE; + else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2)) + wrlvl_redo_corse_inc <= #TCQ 3'd6; + else begin + wl_state_r <= #TCQ WL_IDLE; + wrlvl_err <= #TCQ 1'b1; + end + end else if (wrlvl_final && ~wrlvl_final_r) begin + wr_level_done_r <= #TCQ 1'b0; + dqs_count_r <= #TCQ 'd0; + end + // verilint STARC-2.2.3.3 off + if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin + if (SIM_CAL_OPTION == "FAST_CAL") + wl_state_r <= #TCQ WL_FINE_INC; + else + wl_state_r <= #TCQ WL_INIT; + end + end + // verilint STARC-2.2.3.3 on + WL_INIT: begin + wl_edge_detect_valid_r <= #TCQ 1'b0; + inhibit_edge_detect_r <= #TCQ 1'b1; + wrlvl_rank_done_r <= #TCQ 1'd0; + //zero_tran_r <= #TCQ 1'b0; + if (wrlvl_final) + corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ]; + if (wrlvl_byte_redo) begin + if (|wl_tap_count_r) begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) + wl_state_r <= #TCQ WL_CORSE_INC; + else begin + wl_state_r <= #TCQ WL_IDLE; + wrlvl_err <= #TCQ 1'b1; + end + end else if(wl_sm_start) + wl_state_r <= #TCQ WL_INIT_FINE_INC; + end + + // Initially Phaser_Out fine delay taps incremented + // until stable_cnt=14. A stable_cnt of 14 indicates + // that rd_data_rise_wl_r=rd_data_previous_r for 14 fine + // tap increments. This is done to inhibit false 0->1 + // edge detection when DQS is initially aligned to the + // negedge of CK + WL_INIT_FINE_INC: begin + wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1; + wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; + final_corse_dec <= #TCQ 1'b0; + end + + WL_INIT_FINE_INC_WAIT1: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT; + end + + // Case1: stable value of rd_data_previous_r=0 then + // proceed to 0->1 edge detection. + // Case2: stable value of rd_data_previous_r=1 then + // decrement fine taps to '0' and proceed to 0->1 + // edge detection. Need to decrement in this case to + // make sure a valid 0->1 transition was not left + // undetected. + WL_INIT_FINE_INC_WAIT: begin + if (wl_sm_start) begin + if (stable_cnt < 'd14) + wl_state_r <= #TCQ WL_INIT_FINE_INC; + else if (~rd_data_previous_r[dqs_count_r]) begin + wl_state_r <= #TCQ WL_WAIT; + inhibit_edge_detect_r <= #TCQ 1'b0; + end else begin + wl_state_r <= #TCQ WL_INIT_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end + end + end + + // Case2: stable value of rd_data_previous_r=1 then + // decrement fine taps to '0' and proceed to 0->1 + // edge detection. Need to decrement in this case to + // make sure a valid 0->1 transition was not left + // undetected. + WL_INIT_FINE_DEC: begin + wl_tap_count_r <= #TCQ 'd0; + wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1; + if (fine_dec_cnt > 6'd0) + fine_dec_cnt <= #TCQ fine_dec_cnt - 1; + else + fine_dec_cnt <= #TCQ fine_dec_cnt; + end + + WL_INIT_FINE_DEC_WAIT1: begin + if (incdec_wait_cnt == 'd8) + wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT; + end + + WL_INIT_FINE_DEC_WAIT: begin + if (fine_dec_cnt > 6'd0) begin + wl_state_r <= #TCQ WL_INIT_FINE_DEC; + inhibit_edge_detect_r <= #TCQ 1'b1; + end else begin + wl_state_r <= #TCQ WL_WAIT; + inhibit_edge_detect_r <= #TCQ 1'b0; + end + end + + // Inc DQS Phaser_Out Stage2 Fine Delay line + WL_FINE_INC: begin + wl_edge_detect_valid_r <= #TCQ 1'b0; + if (SIM_CAL_OPTION == "FAST_CAL") begin + wl_state_r <= #TCQ WL_FINE_INC_WAIT; + if (fast_cal_fine_cnt > 'd0) + fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1; + else + fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt; + end else if (wr_level_done_r5) begin + wl_tap_count_r <= #TCQ 'd0; + wl_state_r <= #TCQ WL_FINE_INC_WAIT; + if (|fine_inc[dqs_count_w]) + fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1; + end else begin + wl_state_r <= #TCQ WL_WAIT; + wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1; + end + end + + WL_FINE_INC_WAIT: begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + if (fast_cal_fine_cnt > 'd0) + wl_state_r <= #TCQ WL_FINE_INC; + else if (fast_cal_coarse_cnt > 'd0) + wl_state_r <= #TCQ WL_CORSE_INC; + else + wl_state_r <= #TCQ WL_DQS_CNT; + end else if (|fine_inc[dqs_count_w]) + wl_state_r <= #TCQ WL_FINE_INC; + else if (dqs_count_r == (DQS_WIDTH-1)) + wl_state_r <= #TCQ WL_IDLE; + else begin + wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; + dqs_count_r <= #TCQ dqs_count_r + 1; + end + end + + WL_FINE_DEC: begin + wl_edge_detect_valid_r <= #TCQ 1'b0; + wl_tap_count_r <= #TCQ 'd0; + wl_state_r <= #TCQ WL_FINE_DEC_WAIT1; + if (fine_dec_cnt > 6'd0) + fine_dec_cnt <= #TCQ fine_dec_cnt - 1; + else + fine_dec_cnt <= #TCQ fine_dec_cnt; + end + + WL_FINE_DEC_WAIT1: begin + if (incdec_wait_cnt == 'd8) + wl_state_r <= #TCQ WL_FINE_DEC_WAIT; + end + + WL_FINE_DEC_WAIT: begin + if (fine_dec_cnt > 6'd0) + wl_state_r <= #TCQ WL_FINE_DEC; + //else if (zero_tran_r) + // wl_state_r <= #TCQ WL_DQS_CNT; + else if (dual_rnk_dec) begin + if (|corse_dec[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_DEC; + else + wl_state_r <= #TCQ WL_2RANK_DQS_CNT; + end else if (wrlvl_byte_redo) begin + if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7) + wl_state_r <= #TCQ WL_CORSE_INC; + else begin + wl_state_r <= #TCQ WL_IDLE; + wrlvl_err <= #TCQ 1'b1; + end + end else + wl_state_r <= #TCQ WL_CORSE_INC; + end + + WL_CORSE_DEC: begin + wl_state_r <= #TCQ WL_CORSE_DEC_WAIT; + dual_rnk_dec <= #TCQ 1'b0; + if (|corse_dec[dqs_count_r]) + corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1; + else + corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r]; + end + + WL_CORSE_DEC_WAIT: begin + if (wl_sm_start) begin + //if (|corse_dec[dqs_count_r]) + // wl_state_r <= #TCQ WL_CORSE_DEC; + if (|corse_dec[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1; + else + wl_state_r <= #TCQ WL_2RANK_DQS_CNT; + end + end + + WL_CORSE_DEC_WAIT1: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_CORSE_DEC; + end + + WL_CORSE_INC: begin + wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP; + if (SIM_CAL_OPTION == "FAST_CAL") begin + if (fast_cal_coarse_cnt > 'd0) + fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1; + else + fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt; + end else if (wrlvl_byte_redo) begin + corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1; + if (|wrlvl_redo_corse_inc) + wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1; + end else if (~wr_level_done_r5) + corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1; + else if (|corse_inc[dqs_count_w]) + corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1; + end + + WL_CORSE_INC_WAIT_TMP: begin + if (incdec_wait_cnt == 'd8) + wl_state_r <= #TCQ WL_CORSE_INC_WAIT; + end + + WL_CORSE_INC_WAIT: begin + if (SIM_CAL_OPTION == "FAST_CAL") begin + if (fast_cal_coarse_cnt > 'd0) + wl_state_r <= #TCQ WL_CORSE_INC; + else + wl_state_r <= #TCQ WL_DQS_CNT; + end else if (wrlvl_byte_redo) begin + if (|wrlvl_redo_corse_inc) + wl_state_r <= #TCQ WL_CORSE_INC; + else begin + wl_state_r <= #TCQ WL_INIT_FINE_INC; + inhibit_edge_detect_r <= #TCQ 1'b1; + end + end else if (~wr_level_done_r5 && wl_sm_start) + wl_state_r <= #TCQ WL_CORSE_INC_WAIT1; + else if (wr_level_done_r5) begin + if (|corse_inc[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_INC; + else if (|fine_inc[dqs_count_w]) + wl_state_r <= #TCQ WL_FINE_INC; + else if (dqs_count_r == (DQS_WIDTH-1)) + wl_state_r <= #TCQ WL_IDLE; + else begin + wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; + dqs_count_r <= #TCQ dqs_count_r + 1; + end + end + end + + WL_CORSE_INC_WAIT1: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_CORSE_INC_WAIT2; + end + + WL_CORSE_INC_WAIT2: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_WAIT; + end + + WL_WAIT: begin + if (wl_sm_start) + wl_state_r <= #TCQ WL_EDGE_CHECK; + end + + WL_EDGE_CHECK: begin // Look for the edge + if (wl_edge_detect_valid_r == 1'b0) begin + wl_state_r <= #TCQ WL_WAIT; + wl_edge_detect_valid_r <= #TCQ 1'b1; + end + // 0->1 transition detected with DQS + else if(rd_data_edge_detect_r[dqs_count_r] && + wl_edge_detect_valid_r) + begin + wl_tap_count_r <= #TCQ wl_tap_count_r; + if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || + ~oclkdelay_calib_done) + wl_state_r <= #TCQ WL_DQS_CNT; + else + wl_state_r <= #TCQ WL_2RANK_TAP_DEC; + end + // For initial writes check only upto 56 taps. Reserving the + // remaining taps for OCLK calibration. + else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin + if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end else begin + wrlvl_err <= #TCQ 1'b1; + wl_state_r <= #TCQ WL_IDLE; + end + end else begin + if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal + wl_state_r <= #TCQ WL_FINE_INC; + else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + end else begin + wrlvl_err <= #TCQ 1'b1; + wl_state_r <= #TCQ WL_IDLE; + end + end + end + + WL_2RANK_TAP_DEC: begin + wl_state_r <= #TCQ WL_FINE_DEC; + fine_dec_cnt <= #TCQ wl_tap_count_r; + for (m = 0; m < DQS_WIDTH; m = m + 1) + corse_dec[m] <= #TCQ corse_cnt[m]; + wl_edge_detect_valid_r <= #TCQ 1'b0; + dual_rnk_dec <= #TCQ 1'b1; + end + + WL_DQS_CNT: begin + if ((SIM_CAL_OPTION == "FAST_CAL") || + (dqs_count_r == (DQS_WIDTH-1)) || + wrlvl_byte_redo) begin + dqs_count_r <= #TCQ dqs_count_r; + dq_cnt_inc <= #TCQ 1'b0; + end else begin + dqs_count_r <= #TCQ dqs_count_r + 1'b1; + dq_cnt_inc <= #TCQ 1'b1; + end + wl_state_r <= #TCQ WL_DQS_CHECK; + wl_edge_detect_valid_r <= #TCQ 1'b0; + end + + WL_2RANK_DQS_CNT: begin + if ((SIM_CAL_OPTION == "FAST_CAL") || + (dqs_count_r == (DQS_WIDTH-1))) begin + dqs_count_r <= #TCQ dqs_count_r; + dq_cnt_inc <= #TCQ 1'b0; + end else begin + dqs_count_r <= #TCQ dqs_count_r + 1'b1; + dq_cnt_inc <= #TCQ 1'b1; + end + wl_state_r <= #TCQ WL_DQS_CHECK; + wl_edge_detect_valid_r <= #TCQ 1'b0; + dual_rnk_dec <= #TCQ 1'b0; + end + + WL_DQS_CHECK: begin // check if all DQS have been calibrated + wl_tap_count_r <= #TCQ 'd0; + if (dq_cnt_inc == 1'b0)begin + wrlvl_rank_done_r <= #TCQ 1'd1; + for (t = 0; t < DQS_WIDTH; t = t + 1) + corse_cnt[t] <= #TCQ 3'b0; + if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin + wl_state_r <= #TCQ WL_IDLE; + if (wrlvl_byte_redo) + dqs_count_r <= #TCQ dqs_count_r; + else + dqs_count_r <= #TCQ 'd0; + end else if (rank_cnt_r == RANKS-1) begin + dqs_count_r <= #TCQ dqs_count_r; + if (RANKS > 1) + wl_state_r <= #TCQ WL_2RANK_FINAL_TAP; + else + wl_state_r <= #TCQ WL_IDLE; + end else begin + wl_state_r <= #TCQ WL_INIT; + dqs_count_r <= #TCQ 'd0; + end + if ((SIM_CAL_OPTION == "FAST_CAL") || + (rank_cnt_r == RANKS-1)) begin + wr_level_done_r <= #TCQ 1'd1; + rank_cnt_r <= #TCQ 2'b00; + end else begin + wr_level_done_r <= #TCQ 1'd0; + rank_cnt_r <= #TCQ rank_cnt_r + 1'b1; + end + end else + wl_state_r <= #TCQ WL_INIT; + end + + WL_2RANK_FINAL_TAP: begin + if (wr_level_done_r4 && ~wr_level_done_r5) begin + for(u = 0; u < DQS_WIDTH; u = u + 1) begin + corse_inc[u] <= #TCQ final_coarse_tap[u]; + fine_inc[u] <= #TCQ final_val[u]; + end + dqs_count_r <= #TCQ 'd0; + end else if (wr_level_done_r5) begin + if (|corse_inc[dqs_count_r]) + wl_state_r <= #TCQ WL_CORSE_INC; + else if (|fine_inc[dqs_count_w]) + wl_state_r <= #TCQ WL_FINE_INC; + end + end + endcase + end + end // always @ (posedge clk) + +endmodule + + + + + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v new file mode 100644 index 0000000..c65a458 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v @@ -0,0 +1,248 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_phy_ck_addr_cmd_delay.v +// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ +// \ \ / \ Date Created: Aug 03 2009 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_phy_wrlvl_off_delay # + ( + parameter TCQ = 100, + parameter tCK = 3636, + parameter nCK_PER_CLK = 2, + parameter CLK_PERIOD = 4, + parameter PO_INITIAL_DLY= 46, + parameter DQS_CNT_WIDTH = 3, + parameter DQS_WIDTH = 8, + parameter N_CTL_LANES = 3 + ) + ( + input clk, + input rst, + input pi_fine_dly_dec_done, + input cmd_delay_start, + // Control lane being shifted using Phaser_Out fine delay taps + output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt, + // Inc/dec Phaser_Out fine delay line + output reg po_s2_incdec_f, + output reg po_en_s2_f, + // Inc/dec Phaser_Out coarse delay line + output reg po_s2_incdec_c, + output reg po_en_s2_c, + // Completed adjusting delays for dq, dqs for tdqss + output po_ck_addr_cmd_delay_done, + // completed decrementing initialPO delays + output po_dec_done, + output phy_ctl_rdy_dly + ); + + + localparam TAP_LIMIT = 63; + + + +// PO fine delay tap resolution change by frequency. tCK > 2500, need +// twice the amount of taps +// localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY; + + // coarse delay tap is added DQ/DQS to meet the TDQSS specification. + //localparam TDQSS_DLY = (tCK > 2500 )? 2: 1; + localparam TDQSS_DLY = 2; // DIV2 change + + reg delay_done; + reg delay_done_r1; + reg delay_done_r2; + reg delay_done_r3; + reg delay_done_r4; + reg [5:0] po_delay_cnt_r; + reg po_cnt_inc; + reg cmd_delay_start_r1; + reg cmd_delay_start_r2; + reg cmd_delay_start_r3; + reg cmd_delay_start_r4; + reg cmd_delay_start_r5; + reg cmd_delay_start_r6; + reg po_delay_done; + reg po_delay_done_r1; + reg po_delay_done_r2; + reg po_delay_done_r3; + reg po_delay_done_r4; + reg pi_fine_dly_dec_done_r; + reg po_en_stg2_c; + reg po_en_stg2_f; + reg po_stg2_incdec_c; + reg po_stg2_f_incdec; + reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r; + reg [DQS_CNT_WIDTH:0] lane_cnt_po_r; + reg [5:0] delay_cnt_r; + + always @(posedge clk) begin + cmd_delay_start_r1 <= #TCQ cmd_delay_start; + cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1; + cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2; + cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3; + cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4; + cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5; + pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done; + end + + assign phy_ctl_rdy_dly = cmd_delay_start_r6; + + + // logic for decrementing initial fine delay taps for all PO + // Decrement done for add, ctrl and data phaser outs + + assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4; + + + always @(posedge clk) + if (rst || ~cmd_delay_start_r6 || po_delay_done) begin + po_stg2_f_incdec <= #TCQ 1'b0; + po_en_stg2_f <= #TCQ 1'b0; + end else if (po_delay_cnt_r > 6'd0) begin + po_en_stg2_f <= #TCQ ~po_en_stg2_f; + end + + always @(posedge clk) + if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0)) + // set all the PO delays to 31. Decrement from 46 to 31. + // Requirement comes from dqs_found logic + po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31); + else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0)) + po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1; + + always @(posedge clk) + if (rst) + lane_cnt_po_r <= #TCQ 'd0; + else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1)) + lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1; + + always @(posedge clk) + if (rst || ~cmd_delay_start_r6 ) + po_delay_done <= #TCQ 1'b0; + else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0)) + po_delay_done <= #TCQ 1'b1; + + always @(posedge clk) begin + po_delay_done_r1 <= #TCQ po_delay_done; + po_delay_done_r2 <= #TCQ po_delay_done_r1; + po_delay_done_r3 <= #TCQ po_delay_done_r2; + po_delay_done_r4 <= #TCQ po_delay_done_r3; + end + + // logic to select between all PO delays and data path delay. + always @(posedge clk) begin + po_s2_incdec_f <= #TCQ po_stg2_f_incdec; + po_en_s2_f <= #TCQ po_en_stg2_f; + end + +// Logic to add 1/4 taps amount of delay to data path for tdqss. +// After all the initial PO delays are decremented the 1/4 delay will +// be added. Coarse delay taps will be added here . +// Delay added only to data path + + assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r + : delay_done_r4; + + always @(posedge clk) + if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin + po_stg2_incdec_c <= #TCQ 1'b1; + po_en_stg2_c <= #TCQ 1'b0; + end else if (delay_cnt_r > 6'd0) begin + po_en_stg2_c <= #TCQ ~po_en_stg2_c; + end + + always @(posedge clk) + if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0)) + delay_cnt_r <= #TCQ TDQSS_DLY; + else if ( po_en_stg2_c && (delay_cnt_r > 6'd0)) + delay_cnt_r <= #TCQ delay_cnt_r - 1; + + always @(posedge clk) + if (rst) + lane_cnt_dqs_c_r <= #TCQ 'd0; + else if ( po_en_stg2_c && (delay_cnt_r == 6'd1)) + lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1; + + always @(posedge clk) + if (rst || ~pi_fine_dly_dec_done_r) + delay_done <= #TCQ 1'b0; + else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0)) + delay_done <= #TCQ 1'b1; + + + always @(posedge clk) begin + delay_done_r1 <= #TCQ delay_done; + delay_done_r2 <= #TCQ delay_done_r1; + delay_done_r3 <= #TCQ delay_done_r2; + delay_done_r4 <= #TCQ delay_done_r3; + end + + always @(posedge clk) begin + po_s2_incdec_c <= #TCQ po_stg2_incdec_c; + po_en_s2_c <= #TCQ po_en_stg2_c; + ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r; + end + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v new file mode 100644 index 0000000..50c270a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v @@ -0,0 +1,581 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_prbs_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $ +// \ \ / \ Date Created: 05/12/10 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: ddr_prbs_gen +// Overview: +// Implements a "pseudo-PRBS" generator. Basically this is a standard +// PRBS generator (using an linear feedback shift register) along with +// logic to force the repetition of the sequence after 2^PRBS_WIDTH +// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design +// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains +// are supported in this code +// Parameter Requirements: +// 1. PRBS_WIDTH = 8 or 10 +// 2. PRBS_WIDTH >= 2*nCK_PER_CLK +// Output notes: +// The output of this module consists of 2*nCK_PER_CLK bits, these contain +// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note +// that prbs_o[0] contains the bit value for the "earliest" bit time. +// +//Reference: +//Revision History: +// +//***************************************************************************** + +/****************************************************************************** +**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $ +**$Date: 2011/06/02 08:35:10 $ +**$Author: mishra $ +**$Revision: 1.1 $ +**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $ +******************************************************************************/ + + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_prbs_gen # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter PRBS_WIDTH = 64, // LFSR shift register length + parameter DQS_CNT_WIDTH = 5, + parameter DQ_WIDTH = 72, + parameter VCCO_PAT_EN = 1, + parameter VCCAUX_PAT_EN = 1, + parameter ISI_PAT_EN = 1, + parameter FIXED_VICTIM = "TRUE" + ) + ( + input clk_i, // input clock + input clk_en_i, // clock enable + input rst_i, // synchronous reset + input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed + input phy_if_empty, // IN_FIFO empty flag + input prbs_rdlvl_start, // PRBS read lveling start + input prbs_rdlvl_done, + input complex_wr_done, + input [2:0] victim_sel, + input [DQS_CNT_WIDTH:0] byte_cnt, + //output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data + output [8*DQ_WIDTH-1:0] prbs_o, + output [9:0] dbg_prbs_gen, + input reset_rd_addr, + output prbs_ignore_first_byte, + output prbs_ignore_last_bytes + ); + + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + + // Number of internal clock cycles before the PRBS sequence will repeat + localparam PRBS_SEQ_LEN_CYCLES = 128; + localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES); + + reg phy_if_empty_r; + reg reseed_prbs_r; + reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r; + reg [PRBS_WIDTH - 1 :0] prbs; + reg [PRBS_WIDTH :1] lfsr_q; + + + //*************************************************************************** + always @(posedge clk_i) begin + phy_if_empty_r <= #TCQ phy_if_empty; + end + + //*************************************************************************** + // Generate PRBS reset signal to ensure that PRBS sequence repeats after + // every 2**PRBS_WIDTH samples. Basically what happens is that we let the + // LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1 + // samples have past. Once that extra cycle is finished, we reseed the LFSR + always @(posedge clk_i) + begin + if (rst_i || ~clk_en_i) begin + sample_cnt_r <= #TCQ 'b0; + reseed_prbs_r <= #TCQ 1'b0; + end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin + // The rollver count should always be [(power of 2) - 1] + sample_cnt_r <= #TCQ sample_cnt_r + 1; + // Assert PRBS reset signal so that it is simultaneously with the + // last sample of the sequence + if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2) + reseed_prbs_r <= #TCQ 1'b1; + else + reseed_prbs_r <= #TCQ 1'b0; + end + end + + always @ (posedge clk_i) + begin +//reset it to a known good state to prevent it locks up + if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin + lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; + lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4]; + end + else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin + lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30]; + lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1]; + lfsr_q[29:9] <= #TCQ lfsr_q[28:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + end + end + + always @ (lfsr_q[PRBS_WIDTH:1]) begin + prbs = lfsr_q[PRBS_WIDTH:1]; + end + +//****************************************************************************** +// Complex pattern BRAM +//****************************************************************************** + +localparam BRAM_ADDR_WIDTH = 8; +localparam BRAM_DATA_WIDTH = 18; +localparam BRAM_DEPTH = 256; + +integer i,j; +(* RAM_STYLE = "distributed" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr; +//reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1]; +(* RAM_STYLE = "distributed" *) reg [BRAM_DATA_WIDTH - 1:0] mem_out; +reg [BRAM_DATA_WIDTH - 3:0] dout_o; +reg [DQ_WIDTH-1:0] sel; +reg [DQ_WIDTH-1:0] dout_rise0; +reg [DQ_WIDTH-1:0] dout_fall0; +reg [DQ_WIDTH-1:0] dout_rise1; +reg [DQ_WIDTH-1:0] dout_fall1; +reg [DQ_WIDTH-1:0] dout_rise2; +reg [DQ_WIDTH-1:0] dout_fall2; +reg [DQ_WIDTH-1:0] dout_rise3; +reg [DQ_WIDTH-1:0] dout_fall3; + +// VCCO noise injection pattern with matching victim (reads with gaps) +// content format +// {aggressor pattern, victim pattern} +always @ (rd_addr) begin + case (rd_addr) + 8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read + 8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads + 8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads + 8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads + 8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads + 8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads + 8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads + 8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads + 8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads + 8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads + 8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads + 8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads + 8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads + 8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads + 8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads + 8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads + 8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads + 8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads + 8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads + 8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads + 8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads + // VCCO noise injection pattern with non-matching victim (reads with gaps) + // content format + // {aggressor pattern, victim pattern} + 8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read + 8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads + 8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads + 8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads + 8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads + 8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads + 8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads + 8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads + 8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads + 8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads + 8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads + 8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads + 8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads + 8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads + 8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads + 8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads + 8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads + 8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads + 8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads + 8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads + 8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads + // VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps) + // content format + // {aggressor pattern, victim pattern} + 8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads + 8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads + 8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads + 8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads + 8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads + 8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads + 8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads + 8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads + 8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads + 8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads + 8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads + 8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads + 8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads + 8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads + 8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads + 8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads + 8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads + 8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads + 8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads + 8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads + 8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads + 8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads + 8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads + 8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads + 8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads + 8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads + 8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads + 8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads + 8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads + 8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads + 8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads + 8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads + 8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads + 8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads + 8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads + 8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads + 8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads + 8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads + 8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads + 8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads + 8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads + 8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads + 8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads + 8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads + 8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads + 8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads + 8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads + 8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads + 8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads + 8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads + 8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads + 8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads + 8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads + 8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads + 8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads + 8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads + 8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads + 8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads + 8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads + 8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads + 8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads + 8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads + 8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads + 8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads + 8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads + 8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads + 8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads + 8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads + 8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads + 8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads + 8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads + 8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads + 8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads + 8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads + 8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads + 8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads + 8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads + 8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads + 8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads + 8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads + 8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads + 8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads + 8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads + 8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads + 8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads + // ISI pattern (Back-to-back reads) + // content format + // {aggressor pattern, victim pattern} + 8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111}; + 8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111}; + 8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000}; + 8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100}; + 8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001}; + 8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111}; + 8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101}; + 8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011}; + 8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101}; + 8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101}; + 8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000}; + 8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100}; + 8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101}; + 8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011}; + 8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111}; + 8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000}; + 8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011}; + 8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100}; + 8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011}; + 8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100}; + 8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101}; + 8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000}; + //Additional for ISI + 8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000}; + 8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101}; + 8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101}; + 8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000}; + 8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000}; + 8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010}; + 8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010}; + 8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000}; + //Available + 8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + 8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001}; + endcase +end + + + +always @ (posedge clk_i) begin + if (rst_i | reset_rd_addr) + rd_addr <= #TCQ 'b0; + //rd_addr for complex oclkdelay calib + else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin + if (rd_addr == 'd156) rd_addr <= #TCQ 'b0; + else rd_addr <= #TCQ rd_addr + 1; + end + //rd_addr for complex rdlvl + else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin + if (rd_addr == 'd148) rd_addr <= #TCQ 'b0; + else rd_addr <= #TCQ rd_addr+1; + end + +end + +// Each pattern can be disabled independently +// When disabled zeros are written to and read from the DRAM +always @ (posedge clk_i) begin + if ((rd_addr < 42) && VCCO_PAT_EN) + dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; + else if ((rd_addr < 127) && VCCAUX_PAT_EN) + dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; + else if (ISI_PAT_EN && (rd_addr > 126)) + dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0]; + else + dout_o <= #TCQ 'd0; +end + +reg prbs_ignore_first_byte_r; +always @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16]; +assign prbs_ignore_first_byte = prbs_ignore_first_byte_r; + +reg prbs_ignore_last_bytes_r; +always @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17]; +assign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r; + + + +generate + if (FIXED_VICTIM == "TRUE") begin: victim_sel_fixed + // Fixed victim bit 3 + always @(posedge clk_i) + sel <= #TCQ {DQ_WIDTH/8{8'h08}}; + end else begin: victim_sel_rotate + // One-hot victim select + always @(posedge clk_i) + if (rst_i) + sel <= #TCQ 'd0; + else begin + for (i = 0; i < DQ_WIDTH/8; i = i+1) begin + for (j=0; j <8 ; j = j+1) begin + if (j == victim_sel) + sel[i*8+j] <= #TCQ 1'b1; + else + sel[i*8+j] <= #TCQ 1'b0; + end + end + end + end +endgenerate + + + +// construct 8 X DATA_WIDTH output bus +always @(*) + for (i = 0; i < DQ_WIDTH; i = i+1) begin + dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]); + dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]); + dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]); + dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]); + dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]); + dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]); + dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]); + dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]); + end + + + assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0}; + + assign dbg_prbs_gen[9] = phy_if_empty_r; + assign dbg_prbs_gen[8] = clk_en_i; + assign dbg_prbs_gen[7:0] = rd_addr[7:0]; + +endmodule + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v new file mode 100644 index 0000000..816bb57 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v @@ -0,0 +1,838 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: ddr_skip_calib_tap.v +// /___/ /\ Date Last Modified: $Date: 2015/05/06 02:07:40 $ +// \ \ / \ Date Created: May 06 2015 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: DDR3 SDRAM +//Purpose: Phaser_Out, Phaser_In, and IDELAY tap adjustments to match +// calibration values when SKIP_CALIB=="TRUE" +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_ddr_skip_calib_tap # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter DQS_WIDTH = 8 // number of bytes + ) + ( + input clk, + input rst, + input phy_ctl_ready, + // Completed loading calib tap values into registers + input load_done, + // Tap adjustment status + input calib_tap_inc_start, + output calib_tap_inc_done, + // Calibration tap values + input [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt, + input [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt, + input [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt, + input [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt, + input [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt, + // Phaser_Out and Phaser_In tap count + input [8:0] po_counter_read_val, + input [5:0] pi_counter_read_val, + // Phaser_Out and Phaser_In tap inc/dec control signals + output [5:0] calib_tap_inc_byte_cnt, + output calib_po_f_en, + output calib_po_f_incdec, + output calib_po_sel_stg2stg3, + output calib_po_c_en, + output calib_po_c_inc, + output calib_pi_f_en, + output calib_pi_f_incdec, + output calib_idelay_ce, + output calib_idelay_inc, + output skip_cal_po_pi_dec_done, + output reg coarse_dec_err, + output [127:0] dbg_skip_cal + ); + + //*************************************************************************** + // Decrement initial Phaser_OUT fine delay value before proceeding with + // calibration + //*************************************************************************** + + + reg phy_ctl_ready_r1, phy_ctl_ready_r2, phy_ctl_ready_r3, phy_ctl_ready_r4, phy_ctl_ready_r5, phy_ctl_ready_r6; + reg po_cnt_dec; + reg [3:0] dec_wait_cnt; + reg [8:0] po_rdval_cnt; + reg po_dec_done; + reg dec_po_f_en_r; + reg dec_po_f_incdec_r; + reg dqs_po_dec_done_r1, dqs_po_dec_done_r2; + reg fine_dly_dec_done_r1, fine_dly_dec_done_r2, fine_dly_dec_done_r3; + reg [5:0] pi_rdval_cnt; + reg pi_cnt_dec; + reg dec_pi_f_en_r; + reg dec_pi_f_incdec_r; + + always @(posedge clk) begin + phy_ctl_ready_r1 <= #TCQ phy_ctl_ready; + phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1; + phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2; + phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3; + phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4; + phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5; + end + + always @(posedge clk) begin + if (rst || po_cnt_dec || pi_cnt_dec) + dec_wait_cnt <= #TCQ 'd8; + else if (phy_ctl_ready_r6 && (dec_wait_cnt > 'd0)) + dec_wait_cnt <= #TCQ dec_wait_cnt - 1; + end + + always @(posedge clk) begin + if (rst) begin + po_rdval_cnt <= #TCQ 'd0; + end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin + po_rdval_cnt <= #TCQ po_counter_read_val; + end else if (po_rdval_cnt > 'd0) begin + if (po_cnt_dec) + po_rdval_cnt <= #TCQ po_rdval_cnt - 1; + else + po_rdval_cnt <= #TCQ po_rdval_cnt; + end else if (po_rdval_cnt == 'd0) begin + po_rdval_cnt <= #TCQ po_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (po_rdval_cnt == 'd0)) + po_cnt_dec <= #TCQ 1'b0; + else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (dec_wait_cnt == 'd1)) + po_cnt_dec <= #TCQ 1'b1; + else + po_cnt_dec <= #TCQ 1'b0; + end + + // Inc/Dec Phaser_Out stage 2 fine delay line + always @(posedge clk) begin + if (rst) begin + dec_po_f_incdec_r <= #TCQ 1'b0; + dec_po_f_en_r <= #TCQ 1'b0; + end else if (po_cnt_dec) begin + dec_po_f_incdec_r <= #TCQ 1'b0; + dec_po_f_en_r <= #TCQ 1'b1; + end else begin + dec_po_f_incdec_r <= #TCQ 1'b0; + dec_po_f_en_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst) + po_dec_done <= #TCQ 1'b0; + else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) || + (phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin + po_dec_done <= #TCQ 1'b1; + end + end + + //*************************************************************************** + // Decrement initial Phaser_IN fine delay value before proceeding with + // calibration + //*************************************************************************** + + always @(posedge clk) begin + dqs_po_dec_done_r1 <= #TCQ po_dec_done; + dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1; + fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1; + fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2; + end + + always @(posedge clk) begin + if (rst) begin + pi_rdval_cnt <= #TCQ 'd0; + end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin + pi_rdval_cnt <= #TCQ pi_counter_read_val; + end else if (pi_rdval_cnt > 'd0) begin + if (pi_cnt_dec) + pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1; + else + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end else if (pi_rdval_cnt == 'd0) begin + pi_rdval_cnt <= #TCQ pi_rdval_cnt; + end + end + + always @(posedge clk) begin + if (rst || (pi_rdval_cnt == 'd0)) + pi_cnt_dec <= #TCQ 1'b0; + else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0) + && (dec_wait_cnt == 'd1)) + pi_cnt_dec <= #TCQ 1'b1; + else + pi_cnt_dec <= #TCQ 1'b0; + end + + // Inc/Dec Phaser_In stage 2 fine delay line + always @(posedge clk) begin + if (rst) begin + dec_pi_f_incdec_r <= #TCQ 1'b0; + dec_pi_f_en_r <= #TCQ 1'b0; + end else if (pi_cnt_dec) begin + dec_pi_f_incdec_r <= #TCQ 1'b0; + dec_pi_f_en_r <= #TCQ 1'b1; + end else begin + dec_pi_f_incdec_r <= #TCQ 1'b0; + dec_pi_f_en_r <= #TCQ 1'b0; + end + end + + always @(posedge clk) begin + if (rst) begin + fine_dly_dec_done_r1 <= #TCQ 1'b0; + end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) || + (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin + fine_dly_dec_done_r1 <= #TCQ 1'b1; + end + end + + assign skip_cal_po_pi_dec_done = fine_dly_dec_done_r3; + +//*************************end Phaser_Out and Phaser_In decrement to zero******* + + + + localparam WAIT_CNT = 15; + + // State Machine + localparam [4:0] IDLE = 5'h00; + localparam [4:0] READ_PO_PI_COUNTER_VAL = 5'h01; + localparam [4:0] CALC_INC_DEC_CNT_VAL = 5'h02; + localparam [4:0] WAIT_STG3_SEL = 5'h03; + localparam [4:0] PO_COARSE_CNT_CHECK = 5'h04; + localparam [4:0] PO_COARSE_INC = 5'h05; + localparam [4:0] PO_STG3_SEL = 5'h06; + localparam [4:0] PO_STG3_INC_CNT_CHECK = 5'h07; + localparam [4:0] PO_STG3_INC = 5'h08; + localparam [4:0] PO_STG3_DEC_CNT_CHECK = 5'h09; + localparam [4:0] PO_STG3_DEC = 5'h0A; + localparam [4:0] PO_STG2_INC_CNT_CHECK = 5'h0B; + localparam [4:0] PO_STG2_INC = 5'h0C; + localparam [4:0] PO_STG2_DEC_CNT_CHECK = 5'h0D; + localparam [4:0] PO_STG2_DEC = 5'h0E; + localparam [4:0] PI_STG2_INC_CNT_CHECK = 5'h0F; + localparam [4:0] PI_STG2_INC = 5'h10; + localparam [4:0] PI_STG2_DEC_CNT_CHECK = 5'h11; + localparam [4:0] PI_STG2_DEC = 5'h12; + localparam [4:0] IDELAY_CNT_CHECK = 5'h13; + localparam [4:0] IDELAY_TAP_INC = 5'h14; + localparam [4:0] WAIT_TAP_INC_DEC = 5'h15; + localparam [4:0] NEXT_BYTE = 5'h16; + localparam [4:0] WAIT_PO_PI_COUNTER_VAL = 5'h17; + localparam [4:0] PO_PI_TAP_ADJ_DONE = 5'h18; + + + reg calib_tap_inc_start_r; + reg [4:0] skip_state_r; + reg wait_cnt_en_r; + reg wait_cnt_done; + reg [3:0] wait_cnt_r; + reg po_sel_stg23_r; + reg po_f_en_r; + reg po_f_incdec_r; + reg po_c_en_r; + reg po_c_inc_r; + reg pi_f_en_r; + reg pi_f_incdec_r; + reg idelay_ce_r; + reg idelay_inc_r; + reg [2:0] po_c_inc_cnt; + reg [5:0] po_stg3_inc_cnt; + reg [5:0] po_stg3_dec_cnt; + reg [5:0] po_stg2_inc_cnt; + reg [5:0] po_stg2_dec_cnt; + reg [5:0] pi_stg2_inc_cnt; + reg [5:0] pi_stg2_dec_cnt; + reg [4:0] idelay_inc_cnt; + reg po_stg3_cnt_load_r; + reg po_c_inc_active_r; + reg po_stg3_inc_active_r; + reg po_stg3_dec_active_r; + reg po_stg2_inc_active_r; + reg po_stg2_dec_active_r; + reg pi_stg2_inc_active_r; + reg pi_stg2_dec_active_r; + reg idelay_inc_active_r; + reg [5:0] byte_cnt_r; + reg tap_adj_done_r; + reg [2:0] calib_byte_po_c_cnt; + reg [5:0] calib_byte_po_stg2_cnt; + reg [5:0] calib_byte_po_stg3_cnt; + reg [5:0] calib_byte_pi_stg2_cnt; + reg [4:0] calib_byte_idelay_cnt; + + reg [4:0] skip_next_state; + reg [5:0] byte_cnt; + reg tap_adj_done; + reg po_sel_stg23; + reg po_f_en; + reg po_f_incdec; + reg po_c_en; + reg po_c_inc; + reg pi_f_en; + reg pi_f_incdec; + reg idelay_ce; + reg idelay_inc; + reg po_stg3_cnt_load; + reg po_c_inc_active; + reg po_stg3_inc_active; + reg po_stg3_dec_active; + reg po_stg2_inc_active; + reg po_stg2_dec_active; + reg pi_stg2_inc_active; + reg pi_stg2_dec_active; + reg idelay_inc_active; + + + +// Output assignments + assign calib_tap_inc_byte_cnt = byte_cnt_r; + assign calib_po_f_en = fine_dly_dec_done_r3 ? po_f_en_r : dec_po_f_en_r; + assign calib_po_f_incdec = fine_dly_dec_done_r3 ? po_f_incdec_r : dec_po_f_incdec_r; + assign calib_po_sel_stg2stg3 = po_sel_stg23_r; + assign calib_po_c_en = po_c_en_r; + assign calib_po_c_inc = po_c_inc_r; + assign calib_pi_f_en = fine_dly_dec_done_r3 ? pi_f_en_r : dec_pi_f_en_r; + assign calib_pi_f_incdec = fine_dly_dec_done_r3 ? pi_f_incdec_r : dec_pi_f_incdec_r; + assign calib_idelay_ce = idelay_ce_r; + assign calib_idelay_inc = idelay_inc_r; + assign calib_tap_inc_done = tap_adj_done_r; + +// Register input calib_tap_inc_start + always @(posedge clk) + calib_tap_inc_start_r <= #TCQ calib_tap_inc_start; + + +/**************************Wait Counter Start*********************************/ +// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and +// WAIT_PO_PI_COUNTER_VAL + always @(posedge clk) begin + if ((skip_state_r == WAIT_STG3_SEL) || + (skip_state_r == WAIT_TAP_INC_DEC) || + (skip_state_r == WAIT_PO_PI_COUNTER_VAL)) + wait_cnt_en_r <= #TCQ 1'b1; + else + wait_cnt_en_r <= #TCQ 1'b0; + end + +// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and +// WAIT_PO_PI_COUNTER_VAL + always @(posedge clk) begin + if (!wait_cnt_en_r) begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b0; + end else begin + if (wait_cnt_r != WAIT_CNT - 1) begin + wait_cnt_r <= #TCQ wait_cnt_r + 1; + wait_cnt_done <= #TCQ 1'b0; + end else begin + wait_cnt_r <= #TCQ 'b0; + wait_cnt_done <= #TCQ 1'b1; + end + end + end +/**************************Wait Counter End***********************************/ + +// Calibration tap values for current byte being adjusted + always @(posedge clk) begin + if (rst) begin + calib_byte_po_c_cnt <= #TCQ 'd0; + calib_byte_po_stg2_cnt <= #TCQ 'd0; + calib_byte_po_stg3_cnt <= #TCQ 'd0; + calib_byte_pi_stg2_cnt <= #TCQ 'd0; + calib_byte_idelay_cnt <= #TCQ 'd0; + end else begin + calib_byte_po_c_cnt <= #TCQ calib_po_coarse_tap_cnt[3*byte_cnt_r+:3]; + calib_byte_po_stg2_cnt <= #TCQ calib_po_stage2_tap_cnt[6*byte_cnt_r+:6]; + calib_byte_po_stg3_cnt <= #TCQ calib_po_stage3_tap_cnt[6*byte_cnt_r+:6]; + calib_byte_pi_stg2_cnt <= #TCQ calib_pi_stage2_tap_cnt[6*byte_cnt_r+:6]; + calib_byte_idelay_cnt <= #TCQ calib_idelay_tap_cnt[5*byte_cnt_r+:5]; + end + end + +// Phaser_Out, Phaser_In, and IDELAY inc/dec counters + always @(posedge clk) begin + if (rst) begin + po_c_inc_cnt <= #TCQ 'd0; + po_stg2_inc_cnt <= #TCQ 'd0; + po_stg2_dec_cnt <= #TCQ 'd0; + pi_stg2_inc_cnt <= #TCQ 'd0; + pi_stg2_dec_cnt <= #TCQ 'd0; + idelay_inc_cnt <= #TCQ 'd0; + end else if (skip_state_r == READ_PO_PI_COUNTER_VAL) begin + // IDELAY tap count setting + idelay_inc_cnt <= #TCQ calib_byte_idelay_cnt; + // Phaser_Out coarse tap setting + if (po_counter_read_val[8:6] == 'd0) begin + coarse_dec_err <= #TCQ 1'b0; + po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt; + end else if (po_counter_read_val[8:6] < calib_byte_po_c_cnt) begin + coarse_dec_err <= #TCQ 1'b0; + po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt - po_counter_read_val[8:6]; + end else begin + // Phaser_Out coarse taps cannot be decremented + coarse_dec_err <= #TCQ 1'b1; + po_c_inc_cnt <= #TCQ 'd0; + end + // Phaser_Out stage2 tap count setting when po_sel_stg23_r=0 + if (po_counter_read_val[5:0] == 'd0) begin + po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt; + po_stg2_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] > calib_byte_po_stg2_cnt) begin + po_stg2_inc_cnt <= #TCQ 'd0; + po_stg2_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg2_cnt; + end else if (po_counter_read_val[5:0] < calib_byte_po_stg2_cnt) begin + po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt - po_counter_read_val[5:0]; + po_stg2_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] == calib_byte_po_stg2_cnt) begin + po_stg2_inc_cnt <= #TCQ 'd0; + po_stg2_dec_cnt <= #TCQ 'd0; + end + //Phaser_In stgae2 tap count setting + if (pi_counter_read_val == 'd0) begin + pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt; + pi_stg2_dec_cnt <= #TCQ 'd0; + end else if (pi_counter_read_val > calib_byte_pi_stg2_cnt) begin + pi_stg2_inc_cnt <= #TCQ 'd0; + pi_stg2_dec_cnt <= #TCQ pi_counter_read_val - calib_byte_pi_stg2_cnt; + end else if (pi_counter_read_val < calib_byte_pi_stg2_cnt) begin + pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt - pi_counter_read_val; + pi_stg2_dec_cnt <= #TCQ 'd0; + end else if (pi_counter_read_val == calib_byte_pi_stg2_cnt) begin + pi_stg2_inc_cnt <= #TCQ 'd0; + pi_stg2_dec_cnt <= #TCQ 'd0; + end + end else begin + if (skip_state_r == IDELAY_TAP_INC) + idelay_inc_cnt <= #TCQ idelay_inc_cnt - 1; + if (skip_state_r == PO_COARSE_INC) + po_c_inc_cnt <= #TCQ po_c_inc_cnt - 1; + if (skip_state_r == PO_STG2_INC) + po_stg2_inc_cnt <= #TCQ po_stg2_inc_cnt - 1; + if (skip_state_r == PO_STG2_DEC) + po_stg2_dec_cnt <= #TCQ po_stg2_dec_cnt - 1; + if (skip_state_r == PI_STG2_INC) + pi_stg2_inc_cnt <= #TCQ pi_stg2_inc_cnt - 1; + if (skip_state_r == PI_STG2_DEC) + pi_stg2_dec_cnt <= #TCQ pi_stg2_dec_cnt - 1; + end + end + + // Phaser_Out stage 3 tap count setting when po_sel_stg23_r=1 + always @(posedge clk) begin + if (rst) begin + po_stg3_inc_cnt <= #TCQ 'd0; + po_stg3_dec_cnt <= #TCQ 'd0; + end else if ((skip_state_r == WAIT_STG3_SEL) && wait_cnt_done && po_stg3_cnt_load_r) begin + if (po_counter_read_val[5:0] == 'd0) begin + po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt; + po_stg3_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] > calib_byte_po_stg3_cnt) begin + po_stg3_inc_cnt <= #TCQ 'd0; + po_stg3_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg3_cnt; + end else if (po_counter_read_val[5:0] < calib_byte_po_stg3_cnt) begin + po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt - po_counter_read_val[5:0]; + po_stg3_dec_cnt <= #TCQ 'd0; + end else if (po_counter_read_val[5:0] == calib_byte_po_stg3_cnt) begin + po_stg3_inc_cnt <= #TCQ 'd0; + po_stg3_dec_cnt <= #TCQ 'd0; + end + end else begin + if (skip_state_r == PO_STG3_INC) + po_stg3_inc_cnt <= #TCQ po_stg3_inc_cnt - 1; + if (skip_state_r == PO_STG3_DEC) + po_stg3_dec_cnt <= #TCQ po_stg3_dec_cnt - 1; + end + end + + always @(posedge clk) begin + if (rst) begin + skip_state_r <= #TCQ IDLE; + byte_cnt_r <= #TCQ 'd0; + tap_adj_done_r <= #TCQ 1'b0; + po_sel_stg23_r <= #TCQ 1'b0; + po_f_en_r <= #TCQ 1'b0; + po_f_incdec_r <= #TCQ 1'b0; + po_c_en_r <= #TCQ 1'b0; + po_c_inc_r <= #TCQ 1'b0; + pi_f_en_r <= #TCQ 1'b0; + pi_f_incdec_r <= #TCQ 1'b0; + idelay_ce_r <= #TCQ 1'b0; + idelay_inc_r <= #TCQ 1'b0; + po_stg3_cnt_load_r <= #TCQ 1'b0; + po_c_inc_active_r <= #TCQ 1'b0; + po_stg3_inc_active_r <= #TCQ 1'b0; + po_stg3_dec_active_r <= #TCQ 1'b0; + po_stg2_inc_active_r <= #TCQ 1'b0; + po_stg2_dec_active_r <= #TCQ 1'b0; + pi_stg2_inc_active_r <= #TCQ 1'b0; + pi_stg2_dec_active_r <= #TCQ 1'b0; + idelay_inc_active_r <= #TCQ 1'b0; + end else begin + skip_state_r <= #TCQ skip_next_state; + byte_cnt_r <= #TCQ byte_cnt; + tap_adj_done_r <= #TCQ tap_adj_done; + po_sel_stg23_r <= #TCQ po_sel_stg23; + po_f_en_r <= #TCQ po_f_en; + po_f_incdec_r <= #TCQ po_f_incdec; + po_c_en_r <= #TCQ po_c_en; + po_c_inc_r <= #TCQ po_c_inc; + pi_f_en_r <= #TCQ pi_f_en; + pi_f_incdec_r <= #TCQ pi_f_incdec; + idelay_ce_r <= #TCQ idelay_ce; + idelay_inc_r <= #TCQ idelay_inc; + po_stg3_cnt_load_r <= #TCQ po_stg3_cnt_load; + po_c_inc_active_r <= #TCQ po_c_inc_active; + po_stg3_inc_active_r <= #TCQ po_stg3_inc_active; + po_stg3_dec_active_r <= #TCQ po_stg3_dec_active; + po_stg2_inc_active_r <= #TCQ po_stg2_inc_active; + po_stg2_dec_active_r <= #TCQ po_stg2_dec_active; + pi_stg2_inc_active_r <= #TCQ pi_stg2_inc_active; + pi_stg2_dec_active_r <= #TCQ pi_stg2_dec_active; + idelay_inc_active_r <= #TCQ idelay_inc_active; + end + end + +// State Machine + always @(*) begin + skip_next_state = skip_state_r; + byte_cnt = byte_cnt_r; + tap_adj_done = tap_adj_done_r; + po_sel_stg23 = po_sel_stg23_r; + po_f_en = po_f_en_r; + po_f_incdec = po_f_incdec_r; + po_c_en = po_c_en_r; + po_c_inc = po_c_inc_r; + pi_f_en = pi_f_en_r; + pi_f_incdec = pi_f_incdec_r; + idelay_ce = idelay_ce_r; + idelay_inc = idelay_inc_r; + po_stg3_cnt_load = po_stg3_cnt_load_r; + po_c_inc_active = po_c_inc_active_r; + po_stg3_inc_active = po_stg3_inc_active_r; + po_stg3_dec_active = po_stg3_dec_active_r; + po_stg2_inc_active = po_stg2_inc_active_r; + po_stg2_dec_active = po_stg2_dec_active_r; + pi_stg2_inc_active = pi_stg2_inc_active_r; + pi_stg2_dec_active = pi_stg2_dec_active_r; + idelay_inc_active = idelay_inc_active_r; + + + case(skip_state_r) + IDLE: begin + // Begin tap adjustment on the rising edge of calib_tap_inc_start + // This logic assumes that load_done is asserted before calib_tap_inc_start + // If this is not the case this logic will have to change + if (calib_tap_inc_start && ~calib_tap_inc_start_r && load_done) begin + skip_next_state = READ_PO_PI_COUNTER_VAL; + end + end + + READ_PO_PI_COUNTER_VAL: begin + skip_next_state = CALC_INC_DEC_CNT_VAL; + end + + CALC_INC_DEC_CNT_VAL: begin + skip_next_state = WAIT_STG3_SEL; + po_sel_stg23 = 1'b1; + po_stg3_cnt_load = 1'b1; + end + + WAIT_STG3_SEL: begin + if (wait_cnt_done) begin + if (po_stg3_cnt_load) + skip_next_state = PO_STG3_SEL; + else + skip_next_state = PO_COARSE_CNT_CHECK; + end + end + + PO_COARSE_CNT_CHECK: begin + if (po_c_inc_cnt > 'd0) begin + po_c_inc_active = 1'b1; + skip_next_state = PO_COARSE_INC; + end else begin + po_c_inc_active = 1'b0; + skip_next_state = PO_STG2_DEC_CNT_CHECK; + end + end + + PO_COARSE_INC: begin + po_c_en = 1'b1; + po_c_inc = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG3_SEL: begin + po_stg3_cnt_load = 1'b0; + if (po_stg3_inc_cnt > 'd0) begin + po_stg3_inc_active = 1'b1; + skip_next_state = PO_STG3_INC; + end else if (po_stg3_dec_cnt > 'd0) begin + po_stg3_dec_active = 1'b1; + skip_next_state = PO_STG3_DEC; + end else begin + po_sel_stg23 = 1'b0; + skip_next_state = WAIT_STG3_SEL; + + end + end + + PO_STG3_INC_CNT_CHECK: begin + if (po_stg3_inc_cnt > 'd0) begin + po_stg3_inc_active = 1'b1; + skip_next_state = PO_STG3_INC; + end else begin + po_stg3_inc_active = 1'b0; + po_sel_stg23 = 1'b0; + skip_next_state = WAIT_STG3_SEL; + end + end + + PO_STG3_INC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG3_DEC_CNT_CHECK: begin + if (po_stg3_dec_cnt > 'd0) begin + po_stg3_dec_active = 1'b1; + skip_next_state = PO_STG3_DEC; + end else begin + po_stg3_dec_active = 1'b0; + po_sel_stg23 = 1'b0; + skip_next_state = WAIT_STG3_SEL; + end + end + + PO_STG3_DEC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b0; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG2_DEC_CNT_CHECK: begin + if (po_stg2_dec_cnt > 'd0) begin + po_stg2_dec_active = 1'b1; + skip_next_state = PO_STG2_DEC; + end else if (po_stg2_inc_cnt > 'd0) begin + po_stg2_dec_active = 1'b0; + skip_next_state = PO_STG2_INC_CNT_CHECK; + end else begin + po_stg2_dec_active = 1'b0; + skip_next_state = PI_STG2_DEC_CNT_CHECK; + end + end + + PO_STG2_DEC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b0; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PO_STG2_INC_CNT_CHECK: begin + if (po_stg2_inc_cnt > 'd0) begin + po_stg2_inc_active = 1'b1; + skip_next_state = PO_STG2_INC; + end else begin + po_stg2_inc_active = 1'b0; + skip_next_state = PI_STG2_DEC_CNT_CHECK; + end + end + + PO_STG2_INC: begin + po_f_en = 1'b1; + po_f_incdec = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PI_STG2_DEC_CNT_CHECK: begin + if (pi_stg2_dec_cnt > 'd0) begin + pi_stg2_dec_active = 1'b1; + skip_next_state = PI_STG2_DEC; + end else if (pi_stg2_inc_cnt > 'd0) begin + pi_stg2_dec_active = 1'b0; + skip_next_state = PI_STG2_INC_CNT_CHECK; + end else begin + pi_stg2_dec_active = 1'b0; + skip_next_state = IDELAY_CNT_CHECK; + end + end + + PI_STG2_DEC: begin + pi_f_en = 1'b1; + pi_f_incdec = 1'b0; + skip_next_state = WAIT_TAP_INC_DEC; + end + + PI_STG2_INC_CNT_CHECK: begin + if (pi_stg2_inc_cnt > 'd0) begin + pi_stg2_inc_active = 1'b1; + skip_next_state = PI_STG2_INC; + end else begin + pi_stg2_inc_active = 1'b0; + skip_next_state = IDELAY_CNT_CHECK; + end + end + + PI_STG2_INC: begin + pi_f_en = 1'b1; + pi_f_incdec = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + IDELAY_CNT_CHECK: begin + if (idelay_inc_cnt > 'd0) begin + idelay_inc_active = 1'b1; + skip_next_state = IDELAY_TAP_INC; + end else begin + idelay_inc_active = 1'b0; + skip_next_state = NEXT_BYTE; + end + end + + IDELAY_TAP_INC: begin + idelay_ce = 1'b1; + idelay_inc = 1'b1; + skip_next_state = WAIT_TAP_INC_DEC; + end + + WAIT_TAP_INC_DEC: begin + po_c_en = 1'b0; + po_c_inc = 1'b0; + po_f_en = 1'b0; + po_f_incdec = 1'b0; + pi_f_en = 1'b0; + pi_f_incdec = 1'b0; + idelay_ce = 1'b0; + idelay_inc = 1'b0; + if (wait_cnt_done) begin + if (po_c_inc_active_r) + skip_next_state = PO_COARSE_CNT_CHECK; + else if (po_stg3_inc_active_r) + skip_next_state = PO_STG3_INC_CNT_CHECK; + else if (po_stg3_dec_active_r) + skip_next_state = PO_STG3_DEC_CNT_CHECK; + else if (po_stg2_dec_active_r) + skip_next_state = PO_STG2_DEC_CNT_CHECK; + else if (po_stg2_inc_active_r) + skip_next_state = PO_STG2_INC_CNT_CHECK; + else if (pi_stg2_dec_active_r) + skip_next_state = PI_STG2_DEC_CNT_CHECK; + else if (pi_stg2_inc_active_r) + skip_next_state = PI_STG2_INC_CNT_CHECK; + else if (idelay_inc_active_r) + skip_next_state = IDELAY_CNT_CHECK; + end + end + + NEXT_BYTE: begin + if (byte_cnt_r >= DQS_WIDTH-1) begin + skip_next_state = PO_PI_TAP_ADJ_DONE; + end else begin + byte_cnt = byte_cnt + 1; + skip_next_state = WAIT_PO_PI_COUNTER_VAL; + end + end + + WAIT_PO_PI_COUNTER_VAL: begin + if (wait_cnt_done) + skip_next_state = READ_PO_PI_COUNTER_VAL; + end + + PO_PI_TAP_ADJ_DONE: begin + tap_adj_done = 1'b1; + end + + default: begin + skip_next_state = IDLE; + end + + endcase + end + + //Debug + assign dbg_skip_cal[4:0] = skip_state_r; + assign dbg_skip_cal[7:5] = po_c_inc_cnt; + assign dbg_skip_cal[13:8] = po_stg3_inc_cnt; + assign dbg_skip_cal[19:14] = po_stg3_dec_cnt; + assign dbg_skip_cal[25:20] = po_stg2_inc_cnt; + assign dbg_skip_cal[31:26] = po_stg2_dec_cnt; + assign dbg_skip_cal[37:32] = pi_stg2_inc_cnt; + assign dbg_skip_cal[43:38] = pi_stg2_dec_cnt; + assign dbg_skip_cal[48:44] = idelay_inc_cnt; + assign dbg_skip_cal[54:49] = byte_cnt_r; + assign dbg_skip_cal[55] = po_c_inc_active; + assign dbg_skip_cal[56] = po_stg3_inc_active; + assign dbg_skip_cal[57] = po_stg3_dec_active; + assign dbg_skip_cal[58] = po_stg2_inc_active; + assign dbg_skip_cal[59] = po_stg2_dec_active; + assign dbg_skip_cal[60] = pi_stg2_inc_active; + assign dbg_skip_cal[61] = pi_stg2_dec_active; + assign dbg_skip_cal[62] = idelay_inc_active; + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v new file mode 100644 index 0000000..0539005 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v @@ -0,0 +1,204 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_2_poc_cc.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 20 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser out characterization and control. Logic to interface with +// Chipscope and control. Intended to support real time observation. Largely +// not generated for production implementations. +// +// Also generates debug bus. Concept is a dynamic portion that can be used +// to examine the POC while it is operating, and a logging portion that +// stores per lane results. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_poc_cc # + (parameter TCQ = 100, + parameter CCENABLE = 0, + parameter LANE_CNT_WIDTH = 2, + parameter PCT_SAMPS_SOLID = 95, + parameter SAMPCNTRWIDTH = 8, + parameter SAMPLES = 128, + parameter SMWIDTH = 2, + parameter TAPCNTRWIDTH = 7) + (/*AUTOARG*/ + // Outputs + samples, samps_solid_thresh, poc_error, dbg_poc, + // Inputs + psen, clk, rst, ktap_at_right_edge, ktap_at_left_edge, + mmcm_lbclk_edge_aligned, mmcm_edge_detect_done, fall_lead_right, + fall_trail_right, rise_lead_right, rise_trail_right, fall_lead_left, + fall_trail_left, rise_lead_left, rise_trail_left, fall_lead_center, + fall_trail_center, rise_lead_center, rise_trail_center, lane, + mmcm_edge_detect_rdy, poc_backup, sm, tap, run, run_end, + run_polarity, run_too_small, samp_cntr, samps_hi, samps_hi_held, + samps_zero, samps_one, run_ends, diff, left, right, window_center, + edge_center + ); + + // Remember SAMPLES is whole number counting. Zero corresponds to one sample. + localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01; + + output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; + input psen; + + input clk, rst; + input ktap_at_right_edge, ktap_at_left_edge; + + input mmcm_lbclk_edge_aligned; + wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned; + + input mmcm_edge_detect_done; + reg mmcm_edge_detect_done_r; + always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done; + wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r; + + + reg [6:0] aligned_cnt_r; + wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done}; + always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns; + + reg poc_error_r; + wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r); + always @(posedge clk) poc_error_r <= #TCQ poc_error_ns; + output poc_error; + assign poc_error = poc_error_r; + + input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right; + input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left; + input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center; + + + generate if (CCENABLE == 0) begin : no_characterization + assign samples = SAMPLES[SAMPCNTRWIDTH:0]; + assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0]; + end else begin : characterization + end endgenerate + + reg [1023:0] dbg_poc_r; + output [1023:0] dbg_poc; + assign dbg_poc = dbg_poc_r; + input [LANE_CNT_WIDTH-1:0] lane; + + input mmcm_edge_detect_rdy; + input poc_backup; + input [SMWIDTH-1:0] sm; + input [TAPCNTRWIDTH-1:0] tap; + input [TAPCNTRWIDTH-1:0] run; + input run_end; + input run_polarity; + input run_too_small; + input [SAMPCNTRWIDTH-1:0] samp_cntr; + input [SAMPCNTRWIDTH:0] samps_hi; + input [SAMPCNTRWIDTH:0] samps_hi_held; + input samps_zero, samps_one; + input [1:0] run_ends; + input [TAPCNTRWIDTH+1:0] diff; + + always @(*) begin + dbg_poc_r[99:0] = 'b0; + dbg_poc_r[1023:900] = 'b0; + dbg_poc_r[0] = mmcm_edge_detect_rdy; + dbg_poc_r[1] = mmcm_edge_detect_done; + dbg_poc_r[2] = ktap_at_right_edge; + dbg_poc_r[3] = ktap_at_left_edge; + dbg_poc_r[4] = mmcm_lbclk_edge_aligned; + dbg_poc_r[5] = poc_backup; + dbg_poc_r[6+:SMWIDTH] = sm; + dbg_poc_r[10+:TAPCNTRWIDTH] = tap; + dbg_poc_r[20+:TAPCNTRWIDTH] = run; + dbg_poc_r[30] = run_end; + dbg_poc_r[31] = run_polarity; + dbg_poc_r[32] = run_too_small; + dbg_poc_r[33+:SAMPCNTRWIDTH] = samp_cntr; + dbg_poc_r[49+:SAMPCNTRWIDTH+1] = samps_hi; + dbg_poc_r[66+:SAMPCNTRWIDTH+1] = samps_hi_held; + dbg_poc_r[83] = samps_zero; + dbg_poc_r[84] = samps_one; + dbg_poc_r[86:85] = run_ends; + dbg_poc_r[87+:TAPCNTRWIDTH+2] = diff; + end // always @ (*) + + input [TAPCNTRWIDTH-1:0] left, right; + input [TAPCNTRWIDTH:0] window_center, edge_center; + + reg [899:100] dbg_poc_ns; + always @(posedge clk) dbg_poc_r[899:100] <= #TCQ dbg_poc_ns; + + always @(*) begin + if (rst) dbg_poc_ns = 'b0; + else begin + dbg_poc_ns = dbg_poc_r[899:100]; + if (mmcm_edge_detect_rdy && lane < 8) begin + dbg_poc_ns[(lane+1)*100] = poc_backup; + dbg_poc_ns[(lane+1)*100+1] = dbg_poc_ns[(lane+1)*100+1] || run_too_small; + dbg_poc_ns[(lane+1)*100+10+:TAPCNTRWIDTH] = left; + dbg_poc_ns[(lane+1)*100+20+:TAPCNTRWIDTH] = right; + dbg_poc_ns[(lane+1)*100+30+:TAPCNTRWIDTH+1] = window_center; + dbg_poc_ns[(lane+1)*100+41+:TAPCNTRWIDTH+1] = edge_center; + end + end + end + +endmodule // mig_7series_v4_2_poc_cc + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v new file mode 100644 index 0000000..290e066 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v @@ -0,0 +1,118 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_2_poc_meta.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Fri 24 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser output calibration edge store. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_poc_edge_store # + (parameter TCQ = 100, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 112) + (/*AUTOARG*/ + // Outputs + fall_lead, fall_trail, rise_lead, rise_trail, + // Inputs + clk, run_polarity, run_end, select0, select1, tap, run + ); + + input clk; + + input run_polarity; + input run_end; + input select0; + input select1; + input [TAPCNTRWIDTH-1:0] tap; + input [TAPCNTRWIDTH-1:0] run; + + wire [TAPCNTRWIDTH:0] trailing_edge = run > tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run + : tap - run; + + wire run_end_this = run_end && select0 && select1; + + reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r; + output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail; + assign fall_lead = fall_lead_r; + assign fall_trail = fall_trail_r; + assign rise_lead = rise_lead_r; + assign rise_trail = rise_trail_r; + + wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r; + wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] + : rise_trail_r; + wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r; + wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] + : fall_trail_r; + + always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns; + always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns; + always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns; + always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns; + +endmodule // mig_7series_v4_2_poc_edge_store + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v new file mode 100644 index 0000000..d030e88 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v @@ -0,0 +1,303 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_2_poc_meta.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser output calibration meta controller. +// +// Compute center of the window set up with with the ktap_left, +// ktap_right dance (hereafter "the window"). Also compute center of the +// edge (hereafter "the edge") to be aligned in the center +// of this window. +// +// Following the ktap_left/right dance, the to be centered edge is +// always left at the right edge of the window +// if SCANFROMRIGHT == 1, and the left edge otherwise. +// +// An assumption is the rise(0) case has a window wider than the noise on the +// edge. The noise case with the possibly narrow window +// will always be shifted by 90. And the fall(180) case is shifted by +// 90 twice. Hence when we start, we can assume the center of the +// edge is to the right/left of the the window center. +// +// The actual hardware does not necessarily monotonically appear to +// move the window centers. Because of noise, it is possible for the +// centered edge to move opposite the expected direction with a tap increment. +// +// This problem is solved by computing the absolute difference between +// the centers and the circular distance between the centers. These will +// be the same until the difference transits through zero. Then the circular +// difference will jump to almost the value of TAPSPERKCLK. +// +// The window center computation is done at 1/2 tap increments to maintain +// resolution through the divide by 2 for centering. +// +// There is a corner case of when the shift is greater than 180 degress. In +// this case the absolute difference and the circular difference will be +// unequal at the beginning of the alignment. This is solved by latching +// if they are equal at the end of each cycle. The completion must see +// that they were equal in the previous cycle, but are not equal in this cycle. +// +// Since the phaser out steps are of unknown size, it is possible to overshoot +// the center. The previous difference is recorded and if its less than the current +// difference, poc_backup is driven high. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_poc_meta # + (parameter SCANFROMRIGHT = 0, + parameter TCQ = 100, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 112) + (/*AUTOARG*/ + // Outputs + run_ends, mmcm_edge_detect_done, edge_center, left, right, + window_center, diff, poc_backup, mmcm_lbclk_edge_aligned, + // Inputs + rst, clk, mmcm_edge_detect_rdy, run_too_small, run, run_end, + run_polarity, rise_lead_right, rise_trail_left, rise_lead_center, + rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets, + use_noise_window, ktap_at_right_edge, ktap_at_left_edge + ); + + localparam NINETY = TAPSPERKCLK/4; + + function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a, + input [1:0] b, + input integer base); + integer offset_ii; + begin + offset_ii = (a + b * NINETY) < base + ? (a + b * NINETY) + : (a + b * NINETY - base); + offset = offset_ii[TAPCNTRWIDTH-1:0]; + end + endfunction // offset + + function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a, + input [TAPCNTRWIDTH-1:0] b, + input integer base); + begin + mod_sub = (a>=b) ? a-b : a+base-b; + end + endfunction // mod_sub + + function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left, + input [TAPCNTRWIDTH-1:0] diff, + input integer base); + integer center_ii; + begin + center_ii = ({left, 1'b0} + diff < base * 2) + ? {left, 1'b0} + diff + 32'h0 + : {left, 1'b0} + diff - base * 2; + center = center_ii[TAPCNTRWIDTH:0]; + end + endfunction // center + + input rst; + input clk; + + + input mmcm_edge_detect_rdy; + + reg [1:0] run_ends_r; + + input run_too_small; + reg run_too_small_r1, run_too_small_r2, run_too_small_r3; + + always @ (posedge clk) run_too_small_r1 <= #TCQ run_too_small & (run_ends_r == 'd1); //align with run_end_r1; + always @ (posedge clk) run_too_small_r2 <= #TCQ run_too_small_r1; + always @ (posedge clk) run_too_small_r3 <= #TCQ run_too_small_r2; + + wire reset_run_ends = rst || ~mmcm_edge_detect_rdy || run_too_small_r3 ; + + // This input used only for the SVA. + input [TAPCNTRWIDTH-1:0] run; + + input run_end; + reg run_end_r, run_end_r1, run_end_r2, run_end_r3; + always @(posedge clk) run_end_r <= #TCQ run_end; + always @(posedge clk) run_end_r1 <= #TCQ run_end_r; + always @(posedge clk) run_end_r2 <= #TCQ run_end_r1; + always @(posedge clk) run_end_r3 <= #TCQ run_end_r2; + + input run_polarity; + reg run_polarity_held_ns, run_polarity_held_r; + always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns; + always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r; + + reg [1:0] run_ends_ns; + always @(posedge clk) run_ends_r <= #TCQ run_ends_ns; + always @(*) begin + run_ends_ns = run_ends_r; + if (reset_run_ends) run_ends_ns = 2'b0; + else case (run_ends_r) + 2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r}; + 2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3}; + endcase // case (run_ends_r) + end // always @ begin + output [1:0] run_ends; + assign run_ends = run_ends_r; + + reg done_r; + wire done_ns = mmcm_edge_detect_rdy && &run_ends_r; + always @(posedge clk) done_r <= #TCQ done_ns; + output mmcm_edge_detect_done; + assign mmcm_edge_detect_done = done_r; + + input [TAPCNTRWIDTH-1:0] rise_lead_right; + input [TAPCNTRWIDTH-1:0] rise_trail_left; + input [TAPCNTRWIDTH-1:0] rise_lead_center; + input [TAPCNTRWIDTH-1:0] rise_trail_center; + input [TAPCNTRWIDTH-1:0] rise_trail_right; + input [TAPCNTRWIDTH-1:0] rise_lead_left; + + input [1:0] ninety_offsets; + wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets; + + wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK); + wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK); + reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r; + always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns; + always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns; + + wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK); + reg [TAPCNTRWIDTH-1:0] edge_diff_r; + always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns; + + wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK); + reg [TAPCNTRWIDTH:0] edge_center_r; + always @(posedge clk) edge_center_r <= #TCQ edge_center_ns; + output [TAPCNTRWIDTH:0] edge_center; + assign edge_center = edge_center_r; + + input use_noise_window; + output [TAPCNTRWIDTH-1:0] left, right; + assign left = use_noise_window ? rise_lead_left : rise_trail_left; + assign right = use_noise_window ? rise_trail_right : rise_lead_right; + + wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK); + reg [TAPCNTRWIDTH-1:0] center_diff_r; + always @(posedge clk) center_diff_r <= #TCQ center_diff_ns; + + wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK); + reg [TAPCNTRWIDTH:0] window_center_r; + always @(posedge clk) window_center_r <= #TCQ window_center_ns; + output [TAPCNTRWIDTH:0] window_center; + assign window_center = window_center_r; + + localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2; + + wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r}; + wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r}; + + wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center + ? right_center - left_center + : right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center; + + reg [TAPCNTRWIDTH+1:0] diff_r; + always @(posedge clk) diff_r <= #TCQ diff_ns; + output [TAPCNTRWIDTH+1:0] diff; + assign diff = diff_r; + + wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2 + ? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r + : diff_r; + + reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r; + always @(posedge clk) prev_r <= #TCQ prev_ns; + always @(*) prev_ns = done_ns ? diff_r : prev_r; + + input ktap_at_right_edge; + input ktap_at_left_edge; + + wire centering = !(ktap_at_right_edge || ktap_at_left_edge); + wire diffs_eq = abs_diff == diff_r; + reg diffs_eq_ns, diffs_eq_r; + always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r); + always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns; + + reg edge_aligned_r; + reg prev_valid_ns, prev_valid_r; + always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns; + always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns; + + wire indicate_alignment = ~rst && centering && done_ns; + wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r); + always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns; + + reg poc_backup_r; + wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r; + always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns; + output poc_backup; + assign poc_backup = poc_backup_r; + + output mmcm_lbclk_edge_aligned; + assign mmcm_lbclk_edge_aligned = edge_aligned_r; + +endmodule // mig_7series_v4_2_poc_meta + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v new file mode 100644 index 0000000..cf065df --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v @@ -0,0 +1,132 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_2_poc_pd.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff +// prevents any noise that could happen when the phase shift clock is very +// nearly aligned to the fabric clock. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_poc_pd # + (parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter SIM_CAL_OPTION = "NONE", + parameter TCQ = 100) + (/*AUTOARG*/ + // Outputs + pd_out, + // Inputs + iddr_rst, clk, kclk, mmcm_ps_clk + ); + + input iddr_rst; + input clk; + input kclk; + input mmcm_ps_clk; + + wire q1; + IDDR # + (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .SRTYPE ("SYNC")) + u_phase_detector + (.Q1 (q1), + .Q2 (), + .C (mmcm_ps_clk), + .CE (1'b1), + .D (kclk), + .R (iddr_rst), + .S (1'b0)); + + // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME + + reg pos_edge_samp; + + generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes + always @(posedge clk) pos_edge_samp <= #TCQ q1; + end else begin : eXes + reg q1_delayed; + reg rising_clk_seen; + always @(posedge mmcm_ps_clk) begin + rising_clk_seen <= 1'b0; + q1_delayed <= 1'bx; + end + always @(posedge clk) begin + rising_clk_seen = 1'b1; + if (rising_clk_seen) q1_delayed <= q1; + end + always @(posedge clk) begin + pos_edge_samp <= q1_delayed; + end + end endgenerate + + reg pd_out_r; + always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; + + output pd_out; + assign pd_out = pd_out_r; + + +endmodule // mic_7series_v4_0_poc_pd + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v new file mode 100644 index 0000000..b7cc705 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v @@ -0,0 +1,302 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_2_poc_tap_base.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: All your taps are belong to us. +// +//In general, this block should be able to start up with a random initialization of +//the various counters. But its probably easier, more normative and quicker time to solution +//to just initialize to zero with rst. +// +// Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For +// each MMCM tap it samples the phase detector output a programmable number of times. +// When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM +// tap begins. +// +// Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround +// for a bug in the MMCM where its output may have noise for a period following +// the PSEN. +// +// Samples are taken every other fabric clock. This is because the MMCM phase shift +// clock operates at half the fabric clock. The reason for this is unknown. +// +// At the end of the sampling period, a filtering step is implemented. samps_solid_thresh +// is the minumum number of samples that must be seen to declare a solid zero or one. If +// neithr the one and zero samples cross this threshold, then the sampple is declared fuzz. +// +// A "run_polarity" bit is maintained. It is set appropriately whenever a solid sample +// is observed. +// +// A "run" counter is maintained. If the current sample is fuzz, or opposite polarity +// from a previous sample, then the run counter is reset. If the current sample is the +// same polarity run_polarity, then the run counter is incremented. +// +// If a run_polarity reversal or fuzz is observed and the run counter is not zero +// then the run_end strobe is pulsed. +// +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_poc_tap_base # + (parameter MMCM_SAMP_WAIT = 10, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter TCQ = 100, + parameter SAMPCNTRWIDTH = 8, + parameter SMWIDTH = 2, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK = 112) + (/*AUTOARG*/ + // Outputs + psincdec, psen, run, run_end, run_too_small, run_polarity, + samp_cntr, samps_hi, samps_hi_held, tap, sm, samps_zero, samps_one, + // Inputs + pd_out, clk, samples, samps_solid_thresh, psdone, rst, + poc_sample_pd + ); + + + function integer clogb2 (input integer size); // ceiling logb2 + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction // clogb2 + + input pd_out; + input clk; + input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; + input psdone; + input rst; + + localparam ONE = 1; + + localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT); + reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r; + always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns; + + reg pd_out_r; + always @(posedge clk) pd_out_r <= #TCQ pd_out; + wire pd_out_sel = POC_USE_METASTABLE_SAMP == "TRUE" ? pd_out_r : pd_out; + + output psincdec; + assign psincdec = 1'b1; + output psen; + reg psen_int; + assign psen = psen_int; + + reg [TAPCNTRWIDTH-1:0] run_r; + reg [TAPCNTRWIDTH-1:0] run_ns; + always @(posedge clk) run_r <= #TCQ run_ns; + output [TAPCNTRWIDTH-1:0] run; + assign run = run_r; + + output run_end; + reg run_end_int; + assign run_end = run_end_int; + + output run_too_small; + reg run_too_small_r, run_too_small_ns; + always @(*) run_too_small_ns = run_end && (run < TAPSPERKCLK/4); + always @(posedge clk) run_too_small_r <= #TCQ run_too_small_ns; + assign run_too_small = run_too_small_r; + + reg run_polarity_r; + reg run_polarity_ns; + always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns; + output run_polarity; + assign run_polarity = run_polarity_r; + + reg [SAMPCNTRWIDTH-1:0] samp_cntr_r; + reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns; + always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns; + output [SAMPCNTRWIDTH-1:0] samp_cntr; + assign samp_cntr = samp_cntr_r; + + reg [SAMPCNTRWIDTH:0] samps_hi_r; + reg [SAMPCNTRWIDTH:0] samps_hi_ns; + always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns; + output [SAMPCNTRWIDTH:0] samps_hi; + assign samps_hi = samps_hi_r; + + reg [SAMPCNTRWIDTH:0] samps_hi_held_r; + reg [SAMPCNTRWIDTH:0] samps_hi_held_ns; + always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns; + output [SAMPCNTRWIDTH:0] samps_hi_held; + assign samps_hi_held = samps_hi_held_r; + + reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r; + always @(posedge clk) tap_r <= #TCQ tap_ns; + output [TAPCNTRWIDTH-1:0] tap; + assign tap = tap_r; + + reg [SMWIDTH-1:0] sm_ns; + reg [SMWIDTH-1:0] sm_r; + always @(posedge clk) sm_r <= #TCQ sm_ns; + output [SMWIDTH-1:0] sm; + assign sm = sm_r; + + reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r; + always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns; + always @(posedge clk) samps_one_r <= #TCQ samps_one_ns; + output samps_zero, samps_one; + assign samps_zero = samps_zero_r; + assign samps_one = samps_one_r; + + // Interesting corner case... what if both samps_zero and samps_one are + // hi? Could happen for small sample counts and reasonable values of + // PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment + // consistently breaks tie with samps_one_r. + wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r; + always @(*) begin + samps_zero_ns = samps_zero_r; + samps_one_ns = samps_one_r; + samps_zero_ns = samps_lo >= samps_solid_thresh; + samps_one_ns = samps_hi_r >= samps_solid_thresh; + end // always @ begin + wire new_polarity = run_polarity_ns ^ run_polarity_r; + + input poc_sample_pd; + + always @(*) begin + + if (rst == 1'b1) begin + + // RESET next states + psen_int = 1'b0; + sm_ns = /*AUTOLINK("SAMPLE")*/2'd0; + run_polarity_ns = 1'b0; + run_ns = {TAPCNTRWIDTH{1'b0}}; + run_end_int = 1'b0; + samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; + samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; + tap_ns = {TAPCNTRWIDTH{1'b0}}; + samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0]; + samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}}; + end else begin + + // Default next states; + psen_int = 1'b0; + sm_ns = sm_r; + run_polarity_ns = run_polarity_r; + run_ns = run_r; + run_end_int = 1'b0; + samp_cntr_ns = samp_cntr_r; + samps_hi_ns = samps_hi_r; + tap_ns = tap_r; + samp_wait_ns = samp_wait_r; + if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0]; + samps_hi_held_ns = samps_hi_held_r; + +// State based actions and next states. + case (sm_r) + /*AL("SAMPLE")*/2'd0: begin + if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == "TRUE") begin + if (POC_USE_METASTABLE_SAMP == "TRUE") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0]; + if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK("COMPUTE")*/2'd1; + samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel}; + samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0]; + end + end + + /*AL("COMPUTE")*/2'd1:begin + sm_ns = /*AK("PSEN")*/2'd2; + end + + /*AL("PSEN")*/2'd2:begin + sm_ns = /*AK("PSDONE_WAIT")*/2'd3; + psen_int = 1'b1; + samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; + samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; + samps_hi_held_ns = samps_hi_r; + tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0]) + ? tap_r + ONE[TAPCNTRWIDTH-1:0] + : {TAPCNTRWIDTH{1'b0}}; + + if (run_polarity_r) begin + if (samps_zero_r) run_polarity_ns = 1'b0; + end else begin + if (samps_one_r) run_polarity_ns = 1'b1; + end + if (new_polarity) begin + run_ns ={TAPCNTRWIDTH{1'b0}}; + run_end_int = 1'b1; + end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0]; + end + + /*AL("PSDONE_WAIT")*/2'd3:begin + samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0]; + if (psdone) sm_ns = /*AK("SAMPLE")*/2'd0; + end + + endcase // case (sm_r) + end // else: !if(rst == 1'b1) + end // always @ (*) + +endmodule // mig_7series_v4_2_poc_tap_base + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// verilog-autolabel-prefix: "2'd" +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v new file mode 100644 index 0000000..cbb6d0a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v @@ -0,0 +1,371 @@ +//***************************************************************************** +// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version:%version +// \ \ Application: MIG +// / / Filename: mig_7series_v4_2_poc_top.v +// /___/ /\ Date Last Modified: $$ +// \ \ / \ Date Created:Tue 15 Jan 2014 +// \___\/\___\ +// +//Device: Virtex-7 +//Design Name: DDR3 SDRAM +//Purpose: Phaser out calibration top. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_poc_top # + (parameter LANE_CNT_WIDTH = 2, + parameter MMCM_SAMP_WAIT = 10, + parameter PCT_SAMPS_SOLID = 95, + parameter POC_USE_METASTABLE_SAMP = "FALSE", + parameter TCQ = 100, + parameter CCENABLE = 0, + parameter SCANFROMRIGHT = 0, + parameter SAMPCNTRWIDTH = 8, + parameter SAMPLES = 128, + parameter TAPCNTRWIDTH = 7, + parameter TAPSPERKCLK =112) + (/*AUTOARG*/ + // Outputs + psincdec, poc_error, dbg_poc, psen, rise_lead_right, + rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned, + poc_backup, + // Inputs + use_noise_window, rst, psdone, poc_sample_pd, pd_out, + ninety_offsets, mmcm_edge_detect_rdy, lane, ktap_at_right_edge, + ktap_at_left_edge, clk + ); + + localparam SMWIDTH = 2; + + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input clk; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v, ... + input ktap_at_left_edge; // To u_poc_meta of mig_7series_v4_2_poc_meta.v, ... + input ktap_at_right_edge; // To u_poc_meta of mig_7series_v4_2_poc_meta.v, ... + input [LANE_CNT_WIDTH-1:0] lane; // To u_poc_cc of mig_7series_v4_2_poc_cc.v + input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v4_2_poc_meta.v, ... + input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v4_2_poc_meta.v + input pd_out; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + input poc_sample_pd; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + input psdone; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + input rst; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v, ... + input use_noise_window; // To u_poc_meta of mig_7series_v4_2_poc_meta.v + // End of automatics + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [1023:0] dbg_poc; // From u_poc_cc of mig_7series_v4_2_poc_cc.v + output poc_error; // From u_poc_cc of mig_7series_v4_2_poc_cc.v + output psincdec; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + // End of automatics + /*AUTOwire*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [TAPCNTRWIDTH+1:0] diff; // From u_poc_meta of mig_7series_v4_2_poc_meta.v + wire [TAPCNTRWIDTH:0] edge_center; // From u_poc_meta of mig_7series_v4_2_poc_meta.v + wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] left; // From u_poc_meta of mig_7series_v4_2_poc_meta.v + wire [TAPCNTRWIDTH-1:0] right; // From u_poc_meta of mig_7series_v4_2_poc_meta.v + wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v + wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire run_end; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [1:0] run_ends; // From u_poc_meta of mig_7series_v4_2_poc_meta.v + wire run_polarity; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire run_too_small; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [SAMPCNTRWIDTH-1:0] samp_cntr; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v4_2_poc_cc.v + wire [SAMPCNTRWIDTH:0] samps_hi; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire samps_one; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v4_2_poc_cc.v + wire samps_zero; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [SMWIDTH-1:0] sm; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v + wire [TAPCNTRWIDTH:0] window_center; // From u_poc_meta of mig_7series_v4_2_poc_meta.v + // End of automatics + + output psen; + output [TAPCNTRWIDTH-1:0] rise_lead_right; + output [TAPCNTRWIDTH-1:0] rise_trail_right; + output mmcm_edge_detect_done; + output mmcm_lbclk_edge_aligned; + output poc_backup; + + mig_7series_v4_2_poc_tap_base # + (/*AUTOINSTPARAM*/ + // Parameters + .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), + .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SMWIDTH (SMWIDTH), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_poc_tap_base + (/*AUTOINST*/ + // Outputs + .psen (psen), + .psincdec (psincdec), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .run_too_small (run_too_small), + .samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]), + .samps_hi (samps_hi[SAMPCNTRWIDTH:0]), + .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), + .samps_one (samps_one), + .samps_zero (samps_zero), + .sm (sm[SMWIDTH-1:0]), + .tap (tap[TAPCNTRWIDTH-1:0]), + // Inputs + .clk (clk), + .pd_out (pd_out), + .poc_sample_pd (poc_sample_pd), + .psdone (psdone), + .rst (rst), + .samples (samples[SAMPCNTRWIDTH:0]), + .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0])); + + mig_7series_v4_2_poc_meta # + (/*AUTOINSTPARAM*/ + // Parameters + .SCANFROMRIGHT (SCANFROMRIGHT), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_poc_meta + (/*AUTOINST*/ + // Outputs + .diff (diff[TAPCNTRWIDTH+1:0]), + .edge_center (edge_center[TAPCNTRWIDTH:0]), + .left (left[TAPCNTRWIDTH-1:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .poc_backup (poc_backup), + .right (right[TAPCNTRWIDTH-1:0]), + .run_ends (run_ends[1:0]), + .window_center (window_center[TAPCNTRWIDTH:0]), + // Inputs + .clk (clk), + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .ninety_offsets (ninety_offsets[1:0]), + .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), + .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), + .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), + .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), + .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), + .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), + .rst (rst), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .run_too_small (run_too_small), + .use_noise_window (use_noise_window)); + + /*mig_7series_v4_2_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( + .\(.*\)lead (\1lead_@@"vl-bits"), + .\(.*\)trail (\1trail_@@"vl-bits"), + .select0 (ktap_at_@_edge), + .select1 (1'b1),)*/ + + mig_7series_v4_2_poc_edge_store # + (/*AUTOINSTPARAM*/ + // Parameters + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_edge_right + (/*AUTOINST*/ + // Outputs + .fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated + .fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated + .rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated + .rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .select0 (ktap_at_right_edge), // Templated + .select1 (1'b1), // Templated + .tap (tap[TAPCNTRWIDTH-1:0])); + + mig_7series_v4_2_poc_edge_store # + (/*AUTOINSTPARAM*/ + // Parameters + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_edge_left + (/*AUTOINST*/ + // Outputs + .fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated + .fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated + .rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated + .rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .select0 (ktap_at_left_edge), // Templated + .select1 (1'b1), // Templated + .tap (tap[TAPCNTRWIDTH-1:0])); + + wire not_ktap_at_right_edge = ~ktap_at_right_edge; + wire not_ktap_at_left_edge = ~ktap_at_left_edge; + /*mig_7series_v4_2_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" ( + .\(.*\)lead (\1lead_@@"vl-bits"), + .\(.*\)trail (\1trail_@@"vl-bits"), + .select0 (not_ktap_at_right_edge), + .select1 (not_ktap_at_left_edge),)*/ + + mig_7series_v4_2_poc_edge_store # + (/*AUTOINSTPARAM*/ + // Parameters + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TAPSPERKCLK (TAPSPERKCLK), + .TCQ (TCQ)) + u_edge_center + (/*AUTOINST*/ + // Outputs + .fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated + .fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated + .rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated + .rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated + // Inputs + .clk (clk), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_polarity (run_polarity), + .select0 (not_ktap_at_right_edge), // Templated + .select1 (not_ktap_at_left_edge), // Templated + .tap (tap[TAPCNTRWIDTH-1:0])); + + mig_7series_v4_2_poc_cc # + (/*AUTOINSTPARAM*/ + // Parameters + .CCENABLE (CCENABLE), + .LANE_CNT_WIDTH (LANE_CNT_WIDTH), + .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), + .SAMPCNTRWIDTH (SAMPCNTRWIDTH), + .SAMPLES (SAMPLES), + .SMWIDTH (SMWIDTH), + .TAPCNTRWIDTH (TAPCNTRWIDTH), + .TCQ (TCQ)) + u_poc_cc + (/*AUTOINST*/ + // Outputs + .dbg_poc (dbg_poc[1023:0]), + .poc_error (poc_error), + .samples (samples[SAMPCNTRWIDTH:0]), + .samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]), + // Inputs + .clk (clk), + .diff (diff[TAPCNTRWIDTH+1:0]), + .edge_center (edge_center[TAPCNTRWIDTH:0]), + .fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]), + .fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]), + .fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]), + .fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]), + .fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]), + .fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]), + .ktap_at_left_edge (ktap_at_left_edge), + .ktap_at_right_edge (ktap_at_right_edge), + .lane (lane[LANE_CNT_WIDTH-1:0]), + .left (left[TAPCNTRWIDTH-1:0]), + .mmcm_edge_detect_done (mmcm_edge_detect_done), + .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), + .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), + .poc_backup (poc_backup), + .psen (psen), + .right (right[TAPCNTRWIDTH-1:0]), + .rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]), + .rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]), + .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), + .rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]), + .rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]), + .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), + .rst (rst), + .run (run[TAPCNTRWIDTH-1:0]), + .run_end (run_end), + .run_ends (run_ends[1:0]), + .run_polarity (run_polarity), + .run_too_small (run_too_small), + .samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]), + .samps_hi (samps_hi[SAMPCNTRWIDTH:0]), + .samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]), + .samps_one (samps_one), + .samps_zero (samps_zero), + .sm (sm[SMWIDTH-1:0]), + .tap (tap[TAPCNTRWIDTH-1:0]), + .window_center (window_center[TAPCNTRWIDTH:0])); + +endmodule // mig_7series_v4_2_poc_top + +// Local Variables: +// verilog-library-directories:(".") +// verilog-library-extensions:(".v") +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v new file mode 100644 index 0000000..ae4b53c --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v @@ -0,0 +1,293 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ui_cmd.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +// User interface command port. + +module mig_7series_v4_2_ui_cmd # + ( + parameter TCQ = 100, + parameter ADDR_WIDTH = 33, + parameter BANK_WIDTH = 3, + parameter COL_WIDTH = 12, + parameter DATA_BUF_ADDR_WIDTH = 5, + parameter RANK_WIDTH = 2, + parameter ROW_WIDTH = 16, + parameter RANKS = 4, + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN" + ) + (/*AUTOARG*/ + // Outputs + app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority, + rd_accepted, wr_accepted, data_buf_addr, + // Inputs + rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd, + app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r + ); + + input rst; + input clk; + + input accept_ns; + input rd_buf_full; + input wr_req_16; + wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16; + reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 */; + always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns; + output wire app_rdy; + assign app_rdy = app_rdy_r; + + input [ADDR_WIDTH-1:0] app_addr; + input [2:0] app_cmd; + input app_sz; + input app_hi_pri; + input app_en; + + reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}}; + reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}}; + reg [2:0] app_cmd_r1; + reg [2:0] app_cmd_r2; + reg app_sz_r1; + reg app_sz_r2; + reg app_hi_pri_r1; + reg app_hi_pri_r2; + reg app_en_r1; + reg app_en_r2; + + wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1; + wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2; + wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1; + wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2; + wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1; + wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2; + wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1; + wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2; + wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1); + wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2); + + always @(posedge clk) begin + if (rst) begin + app_addr_r1 <= #TCQ {ADDR_WIDTH{1'b0}}; + app_addr_r2 <= #TCQ {ADDR_WIDTH{1'b0}}; + end else begin + app_addr_r1 <= #TCQ app_addr_ns1; + app_addr_r2 <= #TCQ app_addr_ns2; + end + app_cmd_r1 <= #TCQ app_cmd_ns1; + app_cmd_r2 <= #TCQ app_cmd_ns2; + app_sz_r1 <= #TCQ app_sz_ns1; + app_sz_r2 <= #TCQ app_sz_ns2; + app_hi_pri_r1 <= #TCQ app_hi_pri_ns1; + app_hi_pri_r2 <= #TCQ app_hi_pri_ns2; + app_en_r1 <= #TCQ app_en_ns1; + app_en_r2 <= #TCQ app_en_ns2; + end // always @ (posedge clk) + + wire use_addr_lcl = app_en_r2 && app_rdy_r; + output wire use_addr; + assign use_addr = use_addr_lcl; + + output wire [RANK_WIDTH-1:0] rank; + output wire [BANK_WIDTH-1:0] bank; + output wire [ROW_WIDTH-1:0] row; + output wire [COL_WIDTH-1:0] col; + output wire size; + output wire [2:0] cmd; + output wire hi_priority; + +/* assign col = app_rdy_r + ? app_addr_r1[0+:COL_WIDTH] + : app_addr_r2[0+:COL_WIDTH];*/ + generate + begin + if (MEM_ADDR_ORDER == "TG_TEST") + begin + assign col[4:0] = app_rdy_r + ? app_addr_r1[0+:5] + : app_addr_r2[0+:5]; + + if (RANKS==1) + begin + assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+:2] + : app_addr_r2[5+3+BANK_WIDTH+:2]; + assign col[COL_WIDTH-3:5] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7] + : app_addr_r2[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7]; + end + else + begin + assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+:2] + : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+:2]; + assign col[COL_WIDTH-3:5] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7] + : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7]; + end + assign row[2:0] = app_rdy_r + ? app_addr_r1[5+:3] + : app_addr_r2[5+:3]; + if (RANKS==1) + begin + assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+2+:2] + : app_addr_r2[5+3+BANK_WIDTH+2+:2]; + assign row[ROW_WIDTH-3:3] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5] + : app_addr_r2[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]; + end + else + begin + assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+:2] + : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+:2]; + assign row[ROW_WIDTH-3:3] = app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5] + : app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]; + end + assign bank = app_rdy_r + ? app_addr_r1[5+3+:BANK_WIDTH] + : app_addr_r2[5+3+:BANK_WIDTH]; + assign rank = (RANKS == 1) + ? 1'b0 + : app_rdy_r + ? app_addr_r1[5+3+BANK_WIDTH+:RANK_WIDTH] + : app_addr_r2[5+3+BANK_WIDTH+:RANK_WIDTH]; + end + else if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN") + begin + assign col = app_rdy_r + ? app_addr_r1[0+:COL_WIDTH] + : app_addr_r2[0+:COL_WIDTH]; + assign row = app_rdy_r + ? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH] + : app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]; + assign bank = app_rdy_r + ? app_addr_r1[COL_WIDTH+:BANK_WIDTH] + : app_addr_r2[COL_WIDTH+:BANK_WIDTH]; + assign rank = (RANKS == 1) + ? 1'b0 + : app_rdy_r + ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH] + : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]; + end + else + begin + assign col = app_rdy_r + ? app_addr_r1[0+:COL_WIDTH] + : app_addr_r2[0+:COL_WIDTH]; + assign row = app_rdy_r + ? app_addr_r1[COL_WIDTH+:ROW_WIDTH] + : app_addr_r2[COL_WIDTH+:ROW_WIDTH]; + assign bank = app_rdy_r + ? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH] + : app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]; + assign rank = (RANKS == 1) + ? 1'b0 + : app_rdy_r + ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH] + : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]; + end + end + endgenerate + +/* assign rank = (RANKS == 1) + ? 1'b0 + : app_rdy_r + ? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH] + : app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];*/ + assign size = app_rdy_r + ? app_sz_r1 + : app_sz_r2; + assign cmd = app_rdy_r + ? app_cmd_r1 + : app_cmd_r2; + assign hi_priority = app_rdy_r + ? app_hi_pri_r1 + : app_hi_pri_r2; + + wire request_accepted = use_addr_lcl && app_rdy_r; + wire rd = app_cmd_r2[1:0] == 2'b01; + wire wr = app_cmd_r2[1:0] == 2'b00; + wire wr_bytes = app_cmd_r2[1:0] == 2'b11; + wire write = wr || wr_bytes; + output wire rd_accepted; + assign rd_accepted = request_accepted && rd; + output wire wr_accepted; + assign wr_accepted = request_accepted && write; + + input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr; + input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r; + output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr; + + assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr; + +endmodule // ui_cmd + +// Local Variables: +// verilog-library-directories:(".") +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v new file mode 100644 index 0000000..65d079f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v @@ -0,0 +1,449 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ui_rd_data.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// User interface read buffer. Re orders read data returned from the +// memory controller back to the request order. +// +// Consists of a large buffer for the data, a status RAM and two counters. +// +// The large buffer is implemented with distributed RAM in 6 bit wide, +// 1 read, 1 write mode. The status RAM is implemented with a distributed +// RAM configured as 2 bits wide 1 read/write, 1 read mode. +// +// As read requests are received from the application, the data_buf_addr +// counter supplies the data_buf_addr sent into the memory controller. +// With each read request, the counter is incremented, eventually rolling +// over. This mechanism labels each read request with an incrementing number. +// +// When the memory controller returns read data, it echos the original +// data_buf_addr with the read data. +// +// The status RAM is indexed with the same address as the data buffer +// RAM. Each word of the data buffer RAM has an associated status bit +// and "end" bit. Requests of size 1 return a data burst on two consecutive +// states. Requests of size zero return with a single assertion of rd_data_en. +// +// Upon returning data, the status and end bits are updated for each +// corresponding location in the status RAM indexed by the data_buf_addr +// echoed on the rd_data_addr field. +// +// The other side of the status and data RAMs is indexed by the rd_buf_indx. +// The rd_buf_indx constantly monitors the status bit it is currently +// pointing to. When the status becomes set to the proper state (more on +// this later) read data is returned to the application, and the rd_buf_indx +// is incremented. +// +// At rst the rd_buf_indx is initialized to zero. Data will not have been +// returned from the memory controller yet, so there is nothing to return +// to the application. Evenutally, read requests will be made, and the +// memory controller will return the corresponding data. The memory +// controller may not return this data in the request order. In which +// case, the status bit at location zero, will not indicate +// the data for request zero is ready. Eventually, the memory controller +// will return data for request zero. The data is forwarded on to the +// application, and rd_buf_indx is incremented to point to the next status +// bits and data in the buffers. The status bit will be examined, and if +// data is valid, this data will be returned as well. This process +// continues until the status bit indexed by rd_buf_indx indicates data +// is not ready. This may be because the rd_data_buf +// is empty, or that some data was returned out of order. Since rd_buf_indx +// always increments sequentially, data is always returned to the application +// in request order. +// +// Some further discussion of the status bit is in order. The rd_data_buf +// is a circular buffer. The status bit is a single bit. Distributed RAM +// supports only a single write port. The write port is consumed by +// memory controller read data updates. If a simple '1' were used to +// indicate the status, when rd_data_indx rolled over it would immediately +// encounter a one for a request that may not be ready. +// +// This problem is solved by causing read data returns to flip the +// status bit, and adding hi order bit beyond the size required to +// index the rd_data_buf. Data is considered ready when the status bit +// and this hi order bit are equal. +// +// The status RAM needs to be initialized to zero after reset. This is +// accomplished by cycling through all rd_buf_indx valus and writing a +// zero to the status bits directly following deassertion of reset. This +// mechanism is used for similar purposes +// for the wr_data_buf. +// +// When ORDERING == "STRICT", read data reordering is unnecessary. For thi +// case, most of the logic in the block is not generated. + +`timescale 1 ps / 1 ps + +// User interface read data. + +module mig_7series_v4_2_ui_rd_data # + ( + parameter TCQ = 100, + parameter APP_DATA_WIDTH = 256, + parameter DATA_BUF_ADDR_WIDTH = 5, + parameter ECC = "OFF", + parameter nCK_PER_CLK = 2 , + parameter ORDERING = "NORM" + ) + (/*AUTOARG*/ + // Outputs + ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end, + app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r, + app_ecc_single_err, + // Inputs + rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end, + rd_data, ecc_multiple, ecc_single, rd_accepted + ); + + input rst; + input clk; + + output wire ram_init_done_r; + output wire [3:0] ram_init_addr; + +// rd_buf_indx points to the status and data storage rams for +// reading data out to the app. + reg [5:0] rd_buf_indx_r; + reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */; + assign ram_init_done_r = ram_init_done_r_lcl; + wire app_rd_data_valid_ns; + wire single_data; + reg [5:0] rd_buf_indx_ns; + generate begin : rd_buf_indx + wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns; +// Loop through all status write addresses once after rst. Initializes +// the status and pointer RAMs. + wire ram_init_done_ns = + ~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f)); + always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns; + + always @(/*AS*/rd_buf_indx_r or rst or single_data + or upd_rd_buf_indx) begin + rd_buf_indx_ns = rd_buf_indx_r; + if (rst) rd_buf_indx_ns = 6'b0; + else if (upd_rd_buf_indx) rd_buf_indx_ns = + // need to use every slot of RAMB32 if all address bits are used + rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data); + end + always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns; + end + endgenerate + assign ram_init_addr = rd_buf_indx_r[3:0]; + + input rd_data_en; + input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; + input rd_data_offset; + input rd_data_end; + input [APP_DATA_WIDTH-1:0] rd_data; + output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */; + output reg app_rd_data_end; + output reg [APP_DATA_WIDTH-1:0] app_rd_data; + input [(2*nCK_PER_CLK)-1:0] ecc_multiple; + input [(2*nCK_PER_CLK)-1:0] ecc_single; + reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0; + reg [2*nCK_PER_CLK-1:0] app_ecc_single_err_r = 'b0; + output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; + output wire [2*nCK_PER_CLK-1:0] app_ecc_single_err; + assign app_ecc_multiple_err = app_ecc_multiple_err_r; + assign app_ecc_single_err = app_ecc_single_err_r; + input rd_accepted; + output wire rd_buf_full; + output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r; + +// Compute dimensions of read data buffer. Depending on width of +// DQ bus and DRAM CK +// to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in +// single write, single read, 6 bit wide mode. + localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*2*nCK_PER_CLK); + localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6); + localparam REMAINDER = RD_BUF_WIDTH % 6; + localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); + localparam RAM_WIDTH = (RAM_CNT*6); + generate + if (ORDERING == "STRICT") begin : strict_mode + assign app_rd_data_valid_ns = 1'b0; + assign single_data = 1'b0; + assign rd_buf_full = 1'b0; + reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; + wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns = + rst + ? 0 + : rd_data_buf_addr_r_lcl + rd_accepted; + always @(posedge clk) rd_data_buf_addr_r_lcl <= + #TCQ rd_data_buf_addr_ns; + assign rd_data_buf_addr_r = rd_data_buf_addr_ns; +// app_* signals required to be registered. + if (ECC == "OFF") begin : ecc_off + always @(/*AS*/rd_data) app_rd_data = rd_data; + always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en; + always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end; + end + else begin : ecc_on + always @(posedge clk) app_rd_data <= #TCQ rd_data; + always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en; + always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end; + always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple; + always @(posedge clk) app_ecc_single_err_r <= #TCQ ecc_single; + end + end + else begin : not_strict_mode + wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */; + // In configurations where read data is returned in a single fabric cycle + // the offset is always zero and we can use the bit to get a deeper + // FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH + // is set to use them all, discard the offset. Otherwise, include the + // offset. + wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ? + rd_data_addr : + {rd_data_addr, rd_data_offset}; + wire [1:0] rd_status; +// Instantiate status RAM. One bit for status and one for "end". + begin : status_ram +// Turns out read to write back status is a timing path. Update +// the status in the ram on the state following the read. Bypass +// the write data into the status read path. + wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl + ? rd_buf_wr_addr + : rd_buf_indx_r[4:0]; + reg [4:0] status_ram_wr_addr_r; + always @(posedge clk) status_ram_wr_addr_r <= + #TCQ status_ram_wr_addr_ns; + wire [1:0] wr_status; +// Not guaranteed to write second status bit. If it is written, always +// copy in the first status bit. + reg wr_status_r1; + always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0]; + wire [1:0] status_ram_wr_data_ns = + ram_init_done_r_lcl + ? {rd_data_end, ~(rd_data_offset + ? wr_status_r1 + : wr_status[0])} + : 2'b0; + reg [1:0] status_ram_wr_data_r; + always @(posedge clk) status_ram_wr_data_r <= + #TCQ status_ram_wr_data_ns; + reg rd_buf_we_r1; + always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we; + RAM32M + #(.INIT_A(64'h0000000000000000), + .INIT_B(64'h0000000000000000), + .INIT_C(64'h0000000000000000), + .INIT_D(64'h0000000000000000) + ) RAM32M0 ( + .DOA(rd_status), + .DOB(), + .DOC(wr_status), + .DOD(), + .DIA(status_ram_wr_data_r), + .DIB(2'b0), + .DIC(status_ram_wr_data_r), + .DID(status_ram_wr_data_r), + .ADDRA(rd_buf_indx_r[4:0]), + .ADDRB(5'b0), + .ADDRC(status_ram_wr_addr_ns), + .ADDRD(status_ram_wr_addr_r), + .WE(rd_buf_we_r1), + .WCLK(clk) + ); + end // block: status_ram + + wire [RAM_WIDTH-1:0] rd_buf_out_data; + begin : rd_buf + wire [RAM_WIDTH-1:0] rd_buf_in_data; + if (REMAINDER == 0) + if (ECC == "OFF") + assign rd_buf_in_data = rd_data; + else + assign rd_buf_in_data = {ecc_single, ecc_multiple, rd_data}; + else + if (ECC == "OFF") + assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data}; + else + assign rd_buf_in_data = + {{6-REMAINDER{1'b0}}, ecc_single, ecc_multiple, rd_data}; + + // Dedicated copy for driving distributed RAM. + (* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */; + always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0]; + + genvar i; + for (i=0; i 4) begin + assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0; + end + endgenerate + + mig_7series_v4_2_ui_cmd # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ), + .ADDR_WIDTH (ADDR_WIDTH), + .BANK_WIDTH (BANK_WIDTH), + .COL_WIDTH (COL_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .RANK_WIDTH (RANK_WIDTH), + .ROW_WIDTH (ROW_WIDTH), + .RANKS (RANKS), + .MEM_ADDR_ORDER (MEM_ADDR_ORDER)) + ui_cmd0 + (/*AUTOINST*/ + // Outputs + .app_rdy (app_rdy), + .use_addr (use_addr), + .rank (rank[RANK_WIDTH-1:0]), + .bank (bank[BANK_WIDTH-1:0]), + .row (row[ROW_WIDTH-1:0]), + .col (col[COL_WIDTH-1:0]), + .size (size), + .cmd (cmd[2:0]), + .hi_priority (hi_priority), + .rd_accepted (rd_accepted), + .wr_accepted (wr_accepted), + .data_buf_addr (data_buf_addr), + // Inputs + .rst (rst), + .clk (clk), + .accept_ns (accept_ns), + .rd_buf_full (rd_buf_full), + .wr_req_16 (wr_req_16), + .app_addr (app_addr[ADDR_WIDTH-1:0]), + .app_cmd (app_cmd[2:0]), + .app_sz (app_sz), + .app_hi_pri (app_hi_pri), + .app_en (app_en), + .wr_data_buf_addr (wr_data_buf_addr), + .rd_data_buf_addr_r (rd_data_buf_addr_r)); + + mig_7series_v4_2_ui_wr_data # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ), + .APP_DATA_WIDTH (APP_DATA_WIDTH), + .APP_MASK_WIDTH (APP_MASK_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + .ECC (ECC), + .ECC_TEST (ECC_TEST), + .CWL (CWL_M)) + ui_wr_data0 + (/*AUTOINST*/ + // Outputs + .app_wdf_rdy (app_wdf_rdy), + .wr_req_16 (wr_req_16), + .wr_data_buf_addr (wr_data_buf_addr[3:0]), + .wr_data (wr_data[APP_DATA_WIDTH-1:0]), + .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), + .raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]), + // Inputs + .rst (rst), + .clk (clk), + .app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]), + .app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]), + .app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]), + .app_wdf_wren (app_wdf_wren), + .app_wdf_end (app_wdf_end), + .wr_data_offset (wr_data_offset), + .wr_data_addr (wr_data_addr[3:0]), + .wr_data_en (wr_data_en), + .wr_accepted (wr_accepted), + .ram_init_done_r (ram_init_done_r), + .ram_init_addr (ram_init_addr)); + + mig_7series_v4_2_ui_rd_data # + (/*AUTOINSTPARAM*/ + // Parameters + .TCQ (TCQ), + .APP_DATA_WIDTH (APP_DATA_WIDTH), + .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + .ECC (ECC), + .ORDERING (ORDERING)) + ui_rd_data0 + (/*AUTOINST*/ + // Outputs + .ram_init_done_r (ram_init_done_r), + .ram_init_addr (ram_init_addr), + .app_rd_data_valid (app_rd_data_valid), + .app_rd_data_end (app_rd_data_end), + .app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]), + .app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]), + .app_ecc_single_err (app_ecc_single_err[2*nCK_PER_CLK-1:0]), + .rd_buf_full (rd_buf_full), + .rd_data_buf_addr_r (rd_data_buf_addr_r), + // Inputs + .rst (rst), + .clk (clk), + .rd_data_en (rd_data_en), + .rd_data_addr (rd_data_addr), + .rd_data_offset (rd_data_offset), + .rd_data_end (rd_data_end), + .rd_data (rd_data[APP_DATA_WIDTH-1:0]), + .ecc_multiple (ecc_multiple), + .ecc_single (ecc_single), + .rd_accepted (rd_accepted)); + + +endmodule // ui_top + +// Local Variables: +// verilog-library-directories:("." "../mc") +// End: + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v new file mode 100644 index 0000000..dd2d365 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v @@ -0,0 +1,516 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : ui_wr_data.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Tue Jun 30 2009 +// \___\/\___\ +// +//Device : 7-Series +//Design Name : DDR3 SDRAM +//Purpose : +//Reference : +//Revision History : +//***************************************************************************** + +// User interface write data buffer. Consists of four counters, +// a pointer RAM and the write data storage RAM. +// +// All RAMs are implemented with distributed RAM. +// +// Whe ordering is set to STRICT or NORM, data moves through +// the write data buffer in strictly FIFO order. In RELAXED +// mode, data may be retired from the write data RAM in any +// order relative to the input order. This implementation +// supports all ordering modes. +// +// The pointer RAM stores a list of pointers to the write data storage RAM. +// This is a list of vacant entries. As data is written into the RAM, a +// pointer is pulled from the pointer RAM and used to index the write +// operation. In a semi autonomously manner, pointers are also pulled, in +// the same order, and provided to the command port as the data_buf_addr. +// +// When the MC reads data from the write data buffer, it uses the +// data_buf_addr provided with the command to extract the data from the +// write data buffer. It also writes this pointer into the end +// of the pointer RAM. +// +// The occupancy counter keeps track of how many entries are valid +// in the write data storage RAM. app_wdf_rdy and app_rdy will be +// de-asserted when there is no more storage in the write data buffer. +// +// Three sequentially incrementing counters/indexes are used to maintain +// and use the contents of the pointer RAM. +// +// The write buffer write data address index generates the pointer +// used to extract the write data address from the pointer RAM. It +// is incremented with each buffer write. The counter is actually one +// ahead of the current write address so that the actual data buffer +// write address can be registered to give a full state to propagate to +// the write data distributed RAMs. +// +// The data_buf_addr counter is used to extract the data_buf_addr for +// the command port. It is incremented as each command is written +// into the MC. +// +// The read data index points to the end of the list of free +// buffers. When the MC fetches data from the write data buffer, it +// provides the buffer address. The buffer address is used to fetch +// the data, but is also written into the pointer at the location indicated +// by the read data index. +// +// Enter and exiting a buffer full condition generates corner cases. Upon +// entering a full condition, incrementing the write buffer write data +// address index must be inhibited. When exiting the full condition, +// the just arrived pointer must propagate through the pointer RAM, then +// indexed by the current value of the write buffer write data +// address counter, the value is registered in the write buffer write +// data address register, then the counter can be advanced. +// +// The pointer RAM must be initialized with valid data after reset. This is +// accomplished by stepping through each pointer RAM entry and writing +// the locations address into the pointer RAM. For the FIFO modes, this means +// that buffer address will always proceed in a sequential order. In the +// RELAXED mode, the original write traversal will be in sequential +// order, but once the MC begins to retire out of order, the entries in +// the pointer RAM will become randomized. The ui_rd_data module provides +// the control information for the initialization process. + +`timescale 1 ps / 1 ps + +module mig_7series_v4_2_ui_wr_data # + ( + parameter TCQ = 100, + parameter APP_DATA_WIDTH = 256, + parameter APP_MASK_WIDTH = 32, + parameter ECC = "OFF", + parameter nCK_PER_CLK = 2 , + parameter ECC_TEST = "OFF", + parameter CWL = 5 + ) + (/*AUTOARG*/ + // Outputs + app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask, + raw_not_ecc, + // Inputs + rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren, + app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted, + ram_init_done_r, ram_init_addr + ); + + input rst; + input clk; + + input [APP_DATA_WIDTH-1:0] app_wdf_data; + input [APP_MASK_WIDTH-1:0] app_wdf_mask; + input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; + input app_wdf_wren; + input app_wdf_end; + + reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1; + reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1; + reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0; + reg app_wdf_wren_r1; + reg app_wdf_end_r1; + + reg app_wdf_rdy_r; + + //Adding few copies of the app_wdf_rdy_r signal in order to meet + //timing. This is signal has a very high fanout. So grouped into + //few functional groups and alloted one copy per group. + (* equivalent_register_removal = "no" *) + reg app_wdf_rdy_r_copy1; + (* equivalent_register_removal = "no" *) + reg app_wdf_rdy_r_copy2; + (* equivalent_register_removal = "no" *) + reg app_wdf_rdy_r_copy3; + (* equivalent_register_removal = "no" *) + reg app_wdf_rdy_r_copy4; + + wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 = + ~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data; + wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 = + ~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask; + wire app_wdf_wren_ns1 = + ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren); + wire app_wdf_end_ns1 = + ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end); + + generate + if (ECC_TEST != "OFF") begin : ecc_on + always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc; + end + endgenerate + +// Be explicit about the latch enable on these registers. + always @(posedge clk) begin + app_wdf_data_r1 <= #TCQ app_wdf_data_ns1; + app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1; + app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1; + app_wdf_end_r1 <= #TCQ app_wdf_end_ns1; + end + +// The signals wr_data_addr and wr_data_offset come at different +// times depending on ECC and the value of CWL. The data portion +// always needs to look a the raw wires, the control portion needs +// to look at a delayed version when ECC is on and CWL != 8. The +// currently supported write data delays do not require this +// functionality, but preserve for future use. + input wr_data_offset; + input [3:0] wr_data_addr; + reg wr_data_offset_r; + reg [3:0] wr_data_addr_r; + generate + if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr + always @(wr_data_offset) wr_data_offset_r = wr_data_offset; + always @(wr_data_addr) wr_data_addr_r = wr_data_addr; + end + else begin : delay_wr_addr + always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset; + always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr; + end + endgenerate + +// rd_data_cnt is the pointer RAM index for data read from the write data +// buffer. Ie, its the data on its way out to the DRAM. + input wr_data_en; + wire new_rd_data = wr_data_en && ~wr_data_offset_r; + reg [3:0] rd_data_indx_r; + reg rd_data_upd_indx_r; + generate begin : read_data_indx + reg [3:0] rd_data_indx_ns; + always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin + rd_data_indx_ns = rd_data_indx_r; + if (rst) rd_data_indx_ns = 5'b0; + else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1; + end + always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns; + always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data; + end + endgenerate + +// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf +// of data buf address that comes with the wr_data_en. +// The data buf address is written into the memory +// controller along with the command and address. + input wr_accepted; + reg [3:0] data_buf_addr_cnt_r; + generate begin : data_buf_address_counter + + reg [3:0] data_buf_addr_cnt_ns; + always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin + data_buf_addr_cnt_ns = data_buf_addr_cnt_r; + if (rst) data_buf_addr_cnt_ns = 4'b0; + else if (wr_accepted) data_buf_addr_cnt_ns = + data_buf_addr_cnt_r + 4'h1; + end + always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns; + + end + endgenerate + +// Control writing data into the write data buffer. + wire wdf_rdy_ns; + always @( posedge clk ) begin + app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns; + app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns; + app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns; + app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns; + end + wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1; + wire [3:0] wr_data_pntr; + wire [4:0] wb_wr_data_addr; + wire [4:0] wb_wr_data_addr_w; + reg [3:0] wr_data_indx_r; + generate begin : write_data_control + + wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) || + (rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1); + +// For pointer RAM. Initialize to one since this is one ahead of +// what's being registered in wb_wr_data_addr. Assumes pointer RAM +// has been initialized such that address equals contents. + reg [3:0] wr_data_indx_ns; + always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin + wr_data_indx_ns = wr_data_indx_r; + if (rst) wr_data_indx_ns = 4'b1; + else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1; + end + always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns; + +// Take pointer from pointer RAM and set into the write data address. +// Needs to be split into zeroth bit and everything else because synthesis +// tools don't always allow assigning bit vectors seperately. Bit zero of the +// address is computed via an entirely different algorithm. + reg [4:1] wb_wr_data_addr_ns; + reg [4:1] wb_wr_data_addr_r; + always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le + or wr_data_pntr) begin + wb_wr_data_addr_ns = wb_wr_data_addr_r; + if (rst) wb_wr_data_addr_ns = 4'b0; + else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr; + end + always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns; + +// If we see the first getting accepted, then +// second half is unconditionally accepted. + reg wb_wr_data_addr0_r; + wire wb_wr_data_addr0_ns = ~rst && + ((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) || + (wb_wr_data_addr0_r && ~app_wdf_wren_r1)); + always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns; + + assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r}; + assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns}; + + end + endgenerate + +// Keep track of how many entries in the queue hold data. + input ram_init_done_r; + output wire app_wdf_rdy; + generate begin : occupied_counter + //reg [4:0] occ_cnt_ns; + //reg [4:0] occ_cnt_r; + //always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst + // or wr_data_end) begin + // occ_cnt_ns = occ_cnt_r; + // if (rst) occ_cnt_ns = 5'b0; + // else case ({wr_data_end, rd_data_upd_indx_r}) + // 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1; + // 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1; + // endcase // case ({wr_data_end, rd_data_upd_indx_r}) + //end + //always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns; + //assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]); + //always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; + //assign app_wdf_rdy = app_wdf_rdy_r; + reg [15:0] occ_cnt; + always @(posedge clk) begin + if ( rst ) + occ_cnt <= #TCQ 16'h0000; + else case ({wr_data_end, rd_data_upd_indx_r}) + 2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]}; + 2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1}; + endcase // case ({wr_data_end, rd_data_upd_indx_r}) + end + assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r)); + always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; + assign app_wdf_rdy = app_wdf_rdy_r; + +`ifdef MC_SVA + wr_data_buffer_full: cover property (@(posedge clk) + (~rst && ~app_wdf_rdy_r)); +// wr_data_buffer_inc_dec_15: cover property (@(posedge clk) +// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf))); +// wr_data_underflow: assert property (@(posedge clk) +// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f)))); +// wr_data_overflow: assert property (@(posedge clk) +// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11)))); +`endif + end // block: occupied_counter + endgenerate + +// Keep track of how many write requests are in the memory controller. We +// must limit this to 16 because we only have that many data_buf_addrs to +// hand out. Since the memory controller queue and the write data buffer +// queue are distinct, the number of valid entries can be different. +// Throttle request acceptance once there are sixteen write requests in +// the memory controller. Note that there is still a requirement +// for a write reqeusts corresponding write data to be written into the +// write data queue with two states of the request. + output wire wr_req_16; + generate begin : wr_req_counter + reg [4:0] wr_req_cnt_ns; + reg [4:0] wr_req_cnt_r; + always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted + or wr_req_cnt_r) begin + wr_req_cnt_ns = wr_req_cnt_r; + if (rst) wr_req_cnt_ns = 5'b0; + else case ({wr_accepted, rd_data_upd_indx_r}) + 2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1; + 2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1; + endcase // case ({wr_accepted, rd_data_upd_indx_r}) + end + always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns; + assign wr_req_16 = (wr_req_cnt_ns == 5'h10); + +`ifdef MC_SVA + wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16)); + wr_req_mc_full_inc_dec_15: cover property (@(posedge clk) + (~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf))); + wr_req_underflow: assert property (@(posedge clk) + (rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f)))); + wr_req_overflow: assert property (@(posedge clk) + (rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11)))); +`endif + end // block: wr_req_counter + endgenerate + + + +// Instantiate pointer RAM. Made up of RAM32M in single write, two read +// port mode, 2 bit wide mode. + input [3:0] ram_init_addr; + output wire [3:0] wr_data_buf_addr; + localparam PNTR_RAM_CNT = 2; + generate begin : pointer_ram + wire pointer_we = new_rd_data || ~ram_init_done_r; + wire [3:0] pointer_wr_data = ram_init_done_r + ? wr_data_addr_r + : ram_init_addr; + wire [3:0] pointer_wr_addr = ram_init_done_r + ? rd_data_indx_r + : ram_init_addr; + genvar i; + for (i=0; i CLK, + CE => '1', + D => I120(0), + Q => cke_r, + S => SR(0) + ); +\col_mux.col_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_data_buf_addr(0), + Q => \col_mux.col_data_buf_addr_r\(0), + R => '0' + ); +\col_mux.col_periodic_rd_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => DIC(0), + Q => \col_mux.col_periodic_rd_r\, + R => '0' + ); +\col_mux.col_rd_wr_r_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \col_mux.col_rd_wr_r_reg_0\, + Q => col_rd_wr_r, + R => '0' + ); +\mc_data_offset1_inferred__0/i__carry\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \mc_data_offset1_inferred__0/i__carry_n_0\, + CO(2) => \mc_data_offset1_inferred__0/i__carry_n_1\, + CO(1) => \mc_data_offset1_inferred__0/i__carry_n_2\, + CO(0) => \mc_data_offset1_inferred__0/i__carry_n_3\, + CYINIT => \cmd_pipe_plus.mc_data_offset_reg[5]\(0), + DI(3 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(4 downto 1), + O(3) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2), + O(2) => O(0), + O(1 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1 downto 0), + S(3 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(4 downto 1) + ); +\mc_data_offset1_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => \mc_data_offset1_inferred__0/i__carry_n_0\, + CO(3 downto 0) => \NLW_mc_data_offset1_inferred__0/i__carry__0_CO_UNCONNECTED\(3 downto 0), + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 1) => \NLW_mc_data_offset1_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 1), + O(0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3), + S(3 downto 1) => B"000", + S(0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5) + ); +\rnk_config_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rnk_config_0, + Q => rnk_config_r, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_common is + port ( + periodic_rd_ack_r_lcl_reg_0 : out STD_LOGIC; + accept_ns : out STD_LOGIC; + was_wr : out STD_LOGIC; + \generate_maint_cmds.insert_maint_r_lcl_reg_0\ : out STD_LOGIC; + \maint_controller.maint_wip_r_lcl_reg_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC; + periodic_rd_cntr_r_reg_0 : out STD_LOGIC; + was_priority : out STD_LOGIC; + was_priority_reg_0 : out STD_LOGIC; + req_wr_r_lcl_reg : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_1 : out STD_LOGIC; + idle_r_lcl_reg : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_2 : out STD_LOGIC; + app_rdy_r_reg : out STD_LOGIC; + app_rdy_r_reg_0 : out STD_LOGIC; + \maint_controller.maint_wip_r_lcl_reg_1\ : out STD_LOGIC; + clear_periodic_rd_request : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_3 : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_4 : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_5 : out STD_LOGIC; + periodic_rd_insert : out STD_LOGIC; + app_rdy_r_reg_1 : out STD_LOGIC; + app_rdy_r_reg_2 : out STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p_9_in : in STD_LOGIC; + CLK : in STD_LOGIC; + was_wr0 : in STD_LOGIC; + maint_srx_r : in STD_LOGIC; + \maint_controller.maint_rdy\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + periodic_rd_cntr_r_reg_1 : in STD_LOGIC; + req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + was_priority_reg_1 : in STD_LOGIC; + app_en_r2 : in STD_LOGIC; + rb_hit_busy_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \maint_controller.maint_wip_r_lcl_reg_2\ : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ : in STD_LOGIC; + maint_zq_r : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0\ : in STD_LOGIC; + \periodic_read_request.periodic_rd_grant_r\ : in STD_LOGIC; + head_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + D : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_common : entity is "mig_7series_v4_2_bank_common"; +end ddr3_mig_7series_v4_2_bank_common; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_common is + signal accept_internal_r : STD_LOGIC; + signal \^accept_ns\ : STD_LOGIC; + signal accept_r_reg_n_0 : STD_LOGIC; + signal \generate_maint_cmds.insert_maint_ns\ : STD_LOGIC; + signal \^generate_maint_cmds.insert_maint_r_lcl_reg_0\ : STD_LOGIC; + signal \maint_controller.maint_rdy_r1\ : STD_LOGIC; + signal \maint_controller.maint_srx_r1\ : STD_LOGIC; + signal \maint_controller.maint_wip_r_lcl_i_1_n_0\ : STD_LOGIC; + signal \^maint_controller.maint_wip_r_lcl_reg_0\ : STD_LOGIC; + signal periodic_rd_ack_ns : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg_0\ : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg_1\ : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg_2\ : STD_LOGIC; + signal periodic_rd_cntr_r_i_1_n_0 : STD_LOGIC; + signal \^periodic_rd_cntr_r_reg_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\ : STD_LOGIC_VECTOR ( 4 to 4 ); + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\ : STD_LOGIC; + signal \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\ : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__13\ : STD_LOGIC; + signal \^was_priority\ : STD_LOGIC; + signal \^was_priority_reg_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of accept_r_i_1 : label is "soft_lutpair538"; + attribute SOFT_HLUTNM of \maint_controller.maint_rdy_r1_i_2\ : label is "soft_lutpair540"; + attribute SOFT_HLUTNM of \pass_open_bank_r_lcl_i_3__1\ : label is "soft_lutpair536"; + attribute SOFT_HLUTNM of periodic_rd_ack_r_lcl_i_1 : label is "soft_lutpair538"; + attribute SOFT_HLUTNM of periodic_rd_cntr_r_i_1 : label is "soft_lutpair540"; + attribute SOFT_HLUTNM of \periodic_rd_generation.periodic_rd_request_r_i_3\ : label is "soft_lutpair541"; + attribute SOFT_HLUTNM of q_has_rd_r_i_3 : label is "soft_lutpair536"; + attribute SOFT_HLUTNM of req_periodic_rd_r_lcl_i_1 : label is "soft_lutpair541"; + attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1\ : label is "soft_lutpair539"; + attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2\ : label is "soft_lutpair539"; + attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2\ : label is "soft_lutpair537"; + attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4\ : label is "soft_lutpair537"; +begin + accept_ns <= \^accept_ns\; + \generate_maint_cmds.insert_maint_r_lcl_reg_0\ <= \^generate_maint_cmds.insert_maint_r_lcl_reg_0\; + \maint_controller.maint_wip_r_lcl_reg_0\ <= \^maint_controller.maint_wip_r_lcl_reg_0\; + periodic_rd_ack_r_lcl_reg_0 <= \^periodic_rd_ack_r_lcl_reg_0\; + periodic_rd_ack_r_lcl_reg_1 <= \^periodic_rd_ack_r_lcl_reg_1\; + periodic_rd_ack_r_lcl_reg_2 <= \^periodic_rd_ack_r_lcl_reg_2\; + periodic_rd_cntr_r_reg_0 <= \^periodic_rd_cntr_r_reg_0\; + \rstdiv0_sync_r1_reg_rep__13\ <= \^rstdiv0_sync_r1_reg_rep__13\; + was_priority <= \^was_priority\; + was_priority_reg_0 <= \^was_priority_reg_0\; +accept_internal_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_9_in, + Q => accept_internal_r, + R => '0' + ); +accept_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"80AA" + ) + port map ( + I0 => p_9_in, + I1 => \^periodic_rd_ack_r_lcl_reg_0\, + I2 => \^periodic_rd_cntr_r_reg_0\, + I3 => periodic_rd_cntr_r_reg_1, + O => \^accept_ns\ + ); +accept_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^accept_ns\, + Q => accept_r_reg_n_0, + R => '0' + ); +\generate_maint_cmds.insert_maint_r_lcl_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4F44" + ) + port map ( + I0 => \maint_controller.maint_srx_r1\, + I1 => maint_srx_r, + I2 => \maint_controller.maint_rdy_r1\, + I3 => \maint_controller.maint_rdy\, + O => \generate_maint_cmds.insert_maint_ns\ + ); +\generate_maint_cmds.insert_maint_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \generate_maint_cmds.insert_maint_ns\, + Q => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\, + R => '0' + ); +\maint_controller.maint_hit_busies_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(0), + Q => Q(0), + R => '0' + ); +\maint_controller.maint_hit_busies_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(1), + Q => Q(1), + R => '0' + ); +\maint_controller.maint_hit_busies_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(2), + Q => Q(2), + R => '0' + ); +\maint_controller.maint_hit_busies_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(3), + Q => Q(3), + R => '0' + ); +\maint_controller.maint_rdy_r1_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"45" + ) + port map ( + I0 => \^maint_controller.maint_wip_r_lcl_reg_0\, + I1 => \^periodic_rd_cntr_r_reg_0\, + I2 => maint_req_r, + O => \maint_controller.maint_wip_r_lcl_reg_1\ + ); +\maint_controller.maint_rdy_r1_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maint_controller.maint_rdy\, + Q => \maint_controller.maint_rdy_r1\, + R => '0' + ); +\maint_controller.maint_srx_r1_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => maint_srx_r, + Q => \maint_controller.maint_srx_r1\, + R => '0' + ); +\maint_controller.maint_wip_r_lcl_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7FF" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\, + O => \maint_controller.maint_wip_r_lcl_i_1_n_0\ + ); +\maint_controller.maint_wip_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maint_controller.maint_wip_r_lcl_i_1_n_0\, + Q => \^maint_controller.maint_wip_r_lcl_reg_0\, + R => \^rstdiv0_sync_r1_reg_rep__13\ + ); +\order_q_r[1]_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_1\, + I1 => req_wr_r(0), + O => req_wr_r_lcl_reg + ); +pass_open_bank_r_lcl_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"007FFFFF" + ) + port map ( + I0 => was_priority_reg_1, + I1 => app_en_r2, + I2 => accept_r_reg_n_0, + I3 => \^periodic_rd_ack_r_lcl_reg_0\, + I4 => rb_hit_busy_r(3), + O => app_rdy_r_reg_1 + ); +\pass_open_bank_r_lcl_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"007FFFFF" + ) + port map ( + I0 => was_priority_reg_1, + I1 => app_en_r2, + I2 => accept_r_reg_n_0, + I3 => \^periodic_rd_ack_r_lcl_reg_0\, + I4 => rb_hit_busy_r(2), + O => app_rdy_r_reg_2 + ); +\pass_open_bank_r_lcl_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"007FFFFF" + ) + port map ( + I0 => was_priority_reg_1, + I1 => app_en_r2, + I2 => accept_r_reg_n_0, + I3 => \^periodic_rd_ack_r_lcl_reg_0\, + I4 => rb_hit_busy_r(1), + O => app_rdy_r_reg + ); +\pass_open_bank_r_lcl_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"007FFFFF" + ) + port map ( + I0 => was_priority_reg_1, + I1 => app_en_r2, + I2 => accept_r_reg_n_0, + I3 => \^periodic_rd_ack_r_lcl_reg_0\, + I4 => rb_hit_busy_r(0), + O => app_rdy_r_reg_0 + ); +periodic_rd_ack_r_lcl_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"7000" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_0\, + I1 => \^periodic_rd_cntr_r_reg_0\, + I2 => periodic_rd_cntr_r_reg_1, + I3 => p_9_in, + O => periodic_rd_ack_ns + ); +periodic_rd_ack_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => periodic_rd_ack_ns, + Q => \^periodic_rd_ack_r_lcl_reg_0\, + R => '0' + ); +periodic_rd_cntr_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => periodic_rd_cntr_r_reg_1, + I1 => \^periodic_rd_ack_r_lcl_reg_0\, + I2 => \^periodic_rd_cntr_r_reg_0\, + O => periodic_rd_cntr_r_i_1_n_0 + ); +periodic_rd_cntr_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => periodic_rd_cntr_r_i_1_n_0, + Q => \^periodic_rd_cntr_r_reg_0\, + R => SR(0) + ); +\periodic_rd_generation.periodic_rd_request_r_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_0\, + I1 => \periodic_read_request.periodic_rd_grant_r\, + O => clear_periodic_rd_request + ); +\q_entry_r[0]_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"69969669" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_2\, + I1 => E(0), + I2 => \q_entry_r_reg[0]\(0), + I3 => \q_entry_r_reg[0]_0\(0), + I4 => \q_entry_r_reg[0]_1\(0), + O => idle_r_lcl_reg + ); +\q_entry_r[0]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00000000000000" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_0\, + I1 => was_priority_reg_1, + I2 => app_en_r2, + I3 => accept_internal_r, + I4 => head_r(0), + I5 => \q_entry_r_reg[0]_1\(0), + O => periodic_rd_ack_r_lcl_reg_3 + ); +q_has_rd_r_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"1555" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_0\, + I1 => accept_r_reg_n_0, + I2 => app_en_r2, + I3 => was_priority_reg_1, + O => \^periodic_rd_ack_r_lcl_reg_2\ + ); +req_periodic_rd_r_lcl_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => periodic_rd_cntr_r_reg_1, + I1 => \^periodic_rd_cntr_r_reg_0\, + I2 => \^periodic_rd_ack_r_lcl_reg_0\, + O => periodic_rd_insert + ); +req_priority_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^was_priority\, + I1 => was_priority_reg_1, + O => \^was_priority_reg_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1001100110015445" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\, + I1 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\, + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\, + I5 => maint_zq_r, + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000540155555555" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\, + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2), + I4 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\, + I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0\, + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FF990F99" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\, + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\, + I3 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\, + I4 => maint_zq_r, + I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\, + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4) + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAA9" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + I5 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4), + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\, + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4), + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFD" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\, + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2), + I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\, + I5 => \^generate_maint_cmds.insert_maint_r_lcl_reg_0\, + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3), + I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6), + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55555556" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7), + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4), + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5), + I3 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_2_n_0\, + I4 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6), + O => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1_n_0\, + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(0), + R => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1_n_0\, + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(1), + R => '0' + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1_n_0\, + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(2), + R => '0' + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1_n_0\, + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(3), + R => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns\(4), + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(4), + R => '0' + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1_n_0\, + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(5), + R => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0\, + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(6), + R => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0\, + D => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\(0), + Q => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r\(7), + R => '0' + ); +\wait_for_maint_r_lcl_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAFB" + ) + port map ( + I0 => \maint_controller.maint_wip_r_lcl_reg_2\, + I1 => maint_req_r, + I2 => \^periodic_rd_cntr_r_reg_0\, + I3 => \^maint_controller.maint_wip_r_lcl_reg_0\, + O => \^rstdiv0_sync_r1_reg_rep__13\ + ); +wait_for_maint_r_lcl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00000000000000" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_0\, + I1 => was_priority_reg_1, + I2 => app_en_r2, + I3 => accept_internal_r, + I4 => head_r(3), + I5 => E(0), + O => periodic_rd_ack_r_lcl_reg_4 + ); +\wait_for_maint_r_lcl_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00000000000000" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_0\, + I1 => was_priority_reg_1, + I2 => app_en_r2, + I3 => accept_internal_r, + I4 => head_r(2), + I5 => \q_entry_r_reg[0]\(0), + O => \^periodic_rd_ack_r_lcl_reg_1\ + ); +\wait_for_maint_r_lcl_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EA00000000000000" + ) + port map ( + I0 => \^periodic_rd_ack_r_lcl_reg_0\, + I1 => was_priority_reg_1, + I2 => app_en_r2, + I3 => accept_internal_r, + I4 => head_r(1), + I5 => \q_entry_r_reg[0]_0\(0), + O => periodic_rd_ack_r_lcl_reg_5 + ); +was_priority_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^was_priority_reg_0\, + Q => \^was_priority\, + R => '0' + ); +was_wr_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => was_wr0, + Q => was_wr, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_compare is + port ( + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg_0 : out STD_LOGIC; + req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rb_hit_busy_r_reg_0 : out STD_LOGIC; + req_priority_r : out STD_LOGIC; + row_hit_r : out STD_LOGIC; + ordered_r_lcl_reg : out STD_LOGIC; + req_wr_r_lcl_reg_0 : out STD_LOGIC; + ordered_r_lcl_reg_0 : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + \order_q_r_reg[1]\ : out STD_LOGIC; + req_bank_rdy_ns : out STD_LOGIC; + rd_wr_r_lcl_reg_1 : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__12\ : out STD_LOGIC; + set_order_q : out STD_LOGIC; + pass_open_bank_ns : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC; + start_wtp_timer0 : out STD_LOGIC; + \req_row_r_lcl_reg[14]_0\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_data_buf_addr_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + periodic_rd_insert : in STD_LOGIC; + CLK : in STD_LOGIC; + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + req_priority_r_reg_0 : in STD_LOGIC; + ordered_r_lcl_reg_1 : in STD_LOGIC; + \order_q_r_reg[1]_0\ : in STD_LOGIC; + ordered_r_lcl : in STD_LOGIC; + ordered_r : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + order_q_r : in STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + req_bank_rdy_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_bank_rdy_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_bank_rdy_r_reg_2 : in STD_LOGIC; + ordered_r_lcl_reg_2 : in STD_LOGIC; + ordered_r_lcl_reg_3 : in STD_LOGIC; + rd_wr_r_lcl_reg_2 : in STD_LOGIC; + rd_wr_r_lcl_reg_3 : in STD_LOGIC; + pass_open_bank_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + tail_r : in STD_LOGIC; + pre_wait_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + pre_bm_end_r : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_2 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_3 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_4 : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_data_buf_addr_r_reg[4]_1\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_compare : entity is "mig_7series_v4_2_bank_compare"; +end ddr3_mig_7series_v4_2_bank_compare; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_compare is + signal \^order_q_r_reg[1]\ : STD_LOGIC; + signal pass_open_bank_r_lcl_i_4_n_0 : STD_LOGIC; + signal rd_wr_ns : STD_LOGIC; + signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC; + signal \^rd_wr_r_lcl_reg_1\ : STD_LOGIC; + signal \^req_row_r_lcl_reg[14]_0\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC; + signal \row_hit_ns_carry__0_i_1__2_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry__0_n_3\ : STD_LOGIC; + signal \row_hit_ns_carry_i_1__2_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_2__2_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_3__2_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_4__2_n_0\ : STD_LOGIC; + signal row_hit_ns_carry_n_0 : STD_LOGIC; + signal row_hit_ns_carry_n_1 : STD_LOGIC; + signal row_hit_ns_carry_n_2 : STD_LOGIC; + signal row_hit_ns_carry_n_3 : STD_LOGIC; + signal \^row_hit_r\ : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__13\ : STD_LOGIC; + signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of demand_priority_r_i_2 : label is "soft_lutpair530"; + attribute SOFT_HLUTNM of \order_q_r[0]_i_2\ : label is "soft_lutpair529"; + attribute SOFT_HLUTNM of \order_q_r[1]_i_2\ : label is "soft_lutpair529"; + attribute SOFT_HLUTNM of ras_timer_zero_r_i_3 : label is "soft_lutpair531"; + attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__0\ : label is "soft_lutpair531"; + attribute SOFT_HLUTNM of req_bank_rdy_r_i_1 : label is "soft_lutpair530"; +begin + \order_q_r_reg[1]\ <= \^order_q_r_reg[1]\; + rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\; + rd_wr_r_lcl_reg_1 <= \^rd_wr_r_lcl_reg_1\; + \req_row_r_lcl_reg[14]_0\(14 downto 0) <= \^req_row_r_lcl_reg[14]_0\(14 downto 0); + req_wr_r(0) <= \^req_wr_r\(0); + req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\; + row_hit_r <= \^row_hit_r\; + \rstdiv0_sync_r1_reg_rep__13\ <= \^rstdiv0_sync_r1_reg_rep__13\; +demand_priority_r_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EC" + ) + port map ( + I0 => \^req_wr_r_lcl_reg_0\, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => \^rd_wr_r_lcl_reg_0\, + O => \^order_q_r_reg[1]\ + ); +\grant_r[3]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^order_q_r_reg[1]\, + I1 => req_bank_rdy_r_reg, + I2 => \rnk_config_strobe_r_reg[0]\, + I3 => \rnk_config_strobe_r_reg[0]_0\, + O => col_wait_r_reg + ); +\order_q_r[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => \^req_wr_r_lcl_reg_0\, + I1 => ordered_r_lcl_reg_1, + I2 => \order_q_r_reg[1]_0\, + I3 => ordered_r_lcl, + I4 => ordered_r, + O => ordered_r_lcl_reg + ); +\order_q_r[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7EE8E881" + ) + port map ( + I0 => \^req_wr_r_lcl_reg_0\, + I1 => ordered_r, + I2 => ordered_r_lcl, + I3 => \order_q_r_reg[1]_0\, + I4 => ordered_r_lcl_reg_1, + O => ordered_r_lcl_reg_0 + ); +\order_q_r[1]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^req_wr_r\(0), + I1 => ordered_r_lcl_reg_3, + O => set_order_q + ); +\ordered_r_lcl_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5400545450505050" + ) + port map ( + I0 => ordered_r_lcl_reg_2, + I1 => ordered_r_lcl_reg_3, + I2 => ordered_r_lcl_reg_1, + I3 => \^rd_wr_r_lcl_reg_0\, + I4 => Q(1), + I5 => \^req_wr_r\(0), + O => \rstdiv0_sync_r1_reg_rep__12\ + ); +\pass_open_bank_r_lcl_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444454444444444" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__13\, + I1 => pass_open_bank_r, + I2 => pass_open_bank_r_lcl_reg, + I3 => tail_r, + I4 => pre_wait_r, + I5 => pass_open_bank_r_lcl_i_4_n_0, + O => pass_open_bank_ns + ); +\pass_open_bank_r_lcl_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBFAAAAAA" + ) + port map ( + I0 => pass_open_bank_r_lcl_reg_0, + I1 => \^req_wr_r\(0), + I2 => \^rd_wr_r_lcl_reg_0\, + I3 => pass_open_bank_r, + I4 => Q(1), + I5 => pre_bm_end_r, + O => \^rstdiv0_sync_r1_reg_rep__13\ + ); +pass_open_bank_r_lcl_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAA00A2" + ) + port map ( + I0 => \^row_hit_r\, + I1 => maint_req_r, + I2 => pass_open_bank_r_lcl_reg_1, + I3 => pass_open_bank_r_lcl_reg_2, + I4 => pass_open_bank_r_lcl_reg_3, + I5 => pass_open_bank_r_lcl_reg_4, + O => pass_open_bank_r_lcl_i_4_n_0 + ); +ras_timer_zero_r_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(1), + O => \^rd_wr_r_lcl_reg_1\ + ); +rb_hit_busy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rb_hit_busy_r_reg_1, + Q => rb_hit_busy_r_reg_0, + R => '0' + ); +\rd_wr_r_lcl_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(1), + I2 => rd_wr_r_lcl_reg_2, + I3 => rd_wr_r_lcl_reg_3, + O => rd_wr_ns + ); +rd_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_wr_ns, + Q => \^rd_wr_r_lcl_reg_0\, + R => '0' + ); +\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(0), + Q => \req_bank_r_lcl_reg[2]_0\(0), + R => '0' + ); +\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(1), + Q => \req_bank_r_lcl_reg[2]_0\(1), + R => '0' + ); +\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(2), + Q => \req_bank_r_lcl_reg[2]_0\(2), + R => '0' + ); +req_bank_rdy_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"888A88AA" + ) + port map ( + I0 => req_bank_rdy_r_reg, + I1 => \^rd_wr_r_lcl_reg_0\, + I2 => order_q_r(0), + I3 => order_q_r(1), + I4 => \^req_wr_r_lcl_reg_0\, + O => req_bank_rdy_ns + ); +req_bank_rdy_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000DD0DDDDD" + ) + port map ( + I0 => \^req_wr_r\(0), + I1 => \^rd_wr_r_lcl_reg_1\, + I2 => Q(0), + I3 => req_bank_rdy_r_reg_0(0), + I4 => req_bank_rdy_r_reg_1(0), + I5 => req_bank_rdy_r_reg_2, + O => \^req_wr_r_lcl_reg_0\ + ); +\req_col_r_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(0), + Q => \req_col_r_reg[9]_0\(0), + R => '0' + ); +\req_col_r_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(1), + Q => \req_col_r_reg[9]_0\(1), + R => '0' + ); +\req_col_r_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(2), + Q => \req_col_r_reg[9]_0\(2), + R => '0' + ); +\req_col_r_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(3), + Q => \req_col_r_reg[9]_0\(3), + R => '0' + ); +\req_col_r_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(4), + Q => \req_col_r_reg[9]_0\(4), + R => '0' + ); +\req_col_r_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(5), + Q => \req_col_r_reg[9]_0\(5), + R => '0' + ); +\req_col_r_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(6), + Q => \req_col_r_reg[9]_0\(6), + R => '0' + ); +\req_col_r_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(7), + Q => \req_col_r_reg[9]_0\(7), + R => '0' + ); +\req_col_r_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(8), + Q => \req_col_r_reg[9]_0\(8), + R => '0' + ); +\req_col_r_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(9), + Q => \req_col_r_reg[9]_0\(9), + R => '0' + ); +\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(0), + Q => \req_data_buf_addr_r_reg[4]_0\(0), + R => '0' + ); +\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(1), + Q => \req_data_buf_addr_r_reg[4]_0\(1), + R => '0' + ); +\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(2), + Q => \req_data_buf_addr_r_reg[4]_0\(2), + R => '0' + ); +\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(3), + Q => \req_data_buf_addr_r_reg[4]_0\(3), + R => '0' + ); +\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(4), + Q => \req_data_buf_addr_r_reg[4]_0\(4), + R => '0' + ); +req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => periodic_rd_insert, + Q => req_periodic_rd_r(0), + R => '0' + ); +req_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_priority_r_reg_0, + Q => req_priority_r, + R => '0' + ); +\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(0), + Q => \^req_row_r_lcl_reg[14]_0\(0), + R => '0' + ); +\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(10), + Q => \^req_row_r_lcl_reg[14]_0\(10), + R => '0' + ); +\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(11), + Q => \^req_row_r_lcl_reg[14]_0\(11), + R => '0' + ); +\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(12), + Q => \^req_row_r_lcl_reg[14]_0\(12), + R => '0' + ); +\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(13), + Q => \^req_row_r_lcl_reg[14]_0\(13), + R => '0' + ); +\req_row_r_lcl_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(14), + Q => \^req_row_r_lcl_reg[14]_0\(14), + R => '0' + ); +\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(1), + Q => \^req_row_r_lcl_reg[14]_0\(1), + R => '0' + ); +\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(2), + Q => \^req_row_r_lcl_reg[14]_0\(2), + R => '0' + ); +\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(3), + Q => \^req_row_r_lcl_reg[14]_0\(3), + R => '0' + ); +\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(4), + Q => \^req_row_r_lcl_reg[14]_0\(4), + R => '0' + ); +\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(5), + Q => \^req_row_r_lcl_reg[14]_0\(5), + R => '0' + ); +\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(6), + Q => \^req_row_r_lcl_reg[14]_0\(6), + R => '0' + ); +\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(7), + Q => \^req_row_r_lcl_reg[14]_0\(7), + R => '0' + ); +\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(8), + Q => \^req_row_r_lcl_reg[14]_0\(8), + R => '0' + ); +\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(9), + Q => \^req_row_r_lcl_reg[14]_0\(9), + R => '0' + ); +req_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_wr_r_lcl0, + Q => \^req_wr_r\(0), + R => '0' + ); +row_hit_ns_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => row_hit_ns_carry_n_0, + CO(2) => row_hit_ns_carry_n_1, + CO(1) => row_hit_ns_carry_n_2, + CO(0) => row_hit_ns_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0), + S(3) => \row_hit_ns_carry_i_1__2_n_0\, + S(2) => \row_hit_ns_carry_i_2__2_n_0\, + S(1) => \row_hit_ns_carry_i_3__2_n_0\, + S(0) => \row_hit_ns_carry_i_4__2_n_0\ + ); +\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => row_hit_ns_carry_n_0, + CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \row_hit_ns_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \row_hit_ns_carry__0_i_1__2_n_0\ + ); +\row_hit_ns_carry__0_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(14), + I1 => row(14), + I2 => \^req_row_r_lcl_reg[14]_0\(13), + I3 => row(13), + I4 => row(12), + I5 => \^req_row_r_lcl_reg[14]_0\(12), + O => \row_hit_ns_carry__0_i_1__2_n_0\ + ); +\row_hit_ns_carry_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(11), + I1 => row(11), + I2 => \^req_row_r_lcl_reg[14]_0\(10), + I3 => row(10), + I4 => row(9), + I5 => \^req_row_r_lcl_reg[14]_0\(9), + O => \row_hit_ns_carry_i_1__2_n_0\ + ); +\row_hit_ns_carry_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(8), + I1 => row(8), + I2 => \^req_row_r_lcl_reg[14]_0\(7), + I3 => row(7), + I4 => row(6), + I5 => \^req_row_r_lcl_reg[14]_0\(6), + O => \row_hit_ns_carry_i_2__2_n_0\ + ); +\row_hit_ns_carry_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(5), + I1 => row(5), + I2 => \^req_row_r_lcl_reg[14]_0\(4), + I3 => row(4), + I4 => row(3), + I5 => \^req_row_r_lcl_reg[14]_0\(3), + O => \row_hit_ns_carry_i_3__2_n_0\ + ); +\row_hit_ns_carry_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(2), + I1 => row(2), + I2 => \^req_row_r_lcl_reg[14]_0\(1), + I3 => row(1), + I4 => row(0), + I5 => \^req_row_r_lcl_reg[14]_0\(0), + O => \row_hit_ns_carry_i_4__2_n_0\ + ); +row_hit_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \row_hit_ns_carry__0_n_3\, + Q => \^row_hit_r\, + R => '0' + ); +\wr_this_rank_r[0]_i_1__2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + O => start_wtp_timer0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_compare_0 is + port ( + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg_0 : out STD_LOGIC; + req_wr_r_lcl_reg_0 : out STD_LOGIC; + rb_hit_busy_r_reg_0 : out STD_LOGIC; + req_priority_r : out STD_LOGIC; + row_hit_r : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC; + rd_wr_r_lcl_reg_1 : out STD_LOGIC; + rd_wr_r_lcl_reg_2 : out STD_LOGIC; + pass_open_bank_ns : out STD_LOGIC; + bm_end : out STD_LOGIC_VECTOR ( 0 to 0 ); + start_wtp_timer0 : out STD_LOGIC; + \req_row_r_lcl_reg[14]_0\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_data_buf_addr_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + periodic_rd_insert : in STD_LOGIC; + CLK : in STD_LOGIC; + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + req_priority_r_reg_0 : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + pass_open_bank_r : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + pre_bm_end_r : in STD_LOGIC; + ordered_r_lcl_reg : in STD_LOGIC; + ordered_r_lcl_reg_0 : in STD_LOGIC; + ordered_r_lcl_reg_1 : in STD_LOGIC; + rd_wr_r_lcl_reg_3 : in STD_LOGIC; + rd_wr_r_lcl_reg_4 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + tail_r : in STD_LOGIC; + pre_wait_r : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_2 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_3 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_4 : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_data_buf_addr_r_reg[4]_1\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_compare_0 : entity is "mig_7series_v4_2_bank_compare"; +end ddr3_mig_7series_v4_2_bank_compare_0; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_compare_0 is + signal \pass_open_bank_r_lcl_i_4__0_n_0\ : STD_LOGIC; + signal rd_wr_ns : STD_LOGIC; + signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC; + signal \^req_row_r_lcl_reg[14]_0\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC; + signal \row_hit_ns_carry__0_i_1__1_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry__0_n_3\ : STD_LOGIC; + signal \row_hit_ns_carry_i_1__1_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_2__1_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_3__1_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_4__1_n_0\ : STD_LOGIC; + signal row_hit_ns_carry_n_0 : STD_LOGIC; + signal row_hit_ns_carry_n_1 : STD_LOGIC; + signal row_hit_ns_carry_n_2 : STD_LOGIC; + signal row_hit_ns_carry_n_3 : STD_LOGIC; + signal \^row_hit_r\ : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__13\ : STD_LOGIC; + signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \bm_end_r1_i_1__0\ : label is "soft_lutpair522"; + attribute SOFT_HLUTNM of \ras_timer_r[0]_i_4\ : label is "soft_lutpair522"; + attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__1\ : label is "soft_lutpair523"; + attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1__1\ : label is "soft_lutpair523"; +begin + rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\; + \req_row_r_lcl_reg[14]_0\(14 downto 0) <= \^req_row_r_lcl_reg[14]_0\(14 downto 0); + req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\; + row_hit_r <= \^row_hit_r\; + \rstdiv0_sync_r1_reg_rep__13\ <= \^rstdiv0_sync_r1_reg_rep__13\; +\bm_end_r1_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7000" + ) + port map ( + I0 => \^req_wr_r_lcl_reg_0\, + I1 => \^rd_wr_r_lcl_reg_0\, + I2 => pass_open_bank_r, + I3 => Q(0), + I4 => pre_bm_end_r, + O => bm_end(0) + ); +ordered_r_lcl_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BFBFB000" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(0), + I2 => \^req_wr_r_lcl_reg_0\, + I3 => ordered_r_lcl_reg, + I4 => ordered_r_lcl_reg_0, + I5 => ordered_r_lcl_reg_1, + O => rd_wr_r_lcl_reg_1 + ); +\pass_open_bank_r_lcl_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444454444444444" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__13\, + I1 => pass_open_bank_r, + I2 => pass_open_bank_r_lcl_reg_0, + I3 => tail_r, + I4 => pre_wait_r, + I5 => \pass_open_bank_r_lcl_i_4__0_n_0\, + O => pass_open_bank_ns + ); +\pass_open_bank_r_lcl_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBFAAAAAA" + ) + port map ( + I0 => pass_open_bank_r_lcl_reg, + I1 => \^req_wr_r_lcl_reg_0\, + I2 => \^rd_wr_r_lcl_reg_0\, + I3 => pass_open_bank_r, + I4 => Q(0), + I5 => pre_bm_end_r, + O => \^rstdiv0_sync_r1_reg_rep__13\ + ); +\pass_open_bank_r_lcl_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAA00A2" + ) + port map ( + I0 => \^row_hit_r\, + I1 => maint_req_r, + I2 => pass_open_bank_r_lcl_reg_1, + I3 => pass_open_bank_r_lcl_reg_2, + I4 => pass_open_bank_r_lcl_reg_3, + I5 => pass_open_bank_r_lcl_reg_4, + O => \pass_open_bank_r_lcl_i_4__0_n_0\ + ); +\ras_timer_r[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(0), + O => rd_wr_r_lcl_reg_2 + ); +rb_hit_busy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rb_hit_busy_r_reg_1, + Q => rb_hit_busy_r_reg_0, + R => '0' + ); +\rd_wr_r_lcl_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(0), + I2 => rd_wr_r_lcl_reg_3, + I3 => rd_wr_r_lcl_reg_4, + O => rd_wr_ns + ); +rd_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_wr_ns, + Q => \^rd_wr_r_lcl_reg_0\, + R => '0' + ); +\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(0), + Q => \req_bank_r_lcl_reg[2]_0\(0), + R => '0' + ); +\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(1), + Q => \req_bank_r_lcl_reg[2]_0\(1), + R => '0' + ); +\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(2), + Q => \req_bank_r_lcl_reg[2]_0\(2), + R => '0' + ); +\req_col_r_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(0), + Q => \req_col_r_reg[9]_0\(0), + R => '0' + ); +\req_col_r_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(1), + Q => \req_col_r_reg[9]_0\(1), + R => '0' + ); +\req_col_r_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(2), + Q => \req_col_r_reg[9]_0\(2), + R => '0' + ); +\req_col_r_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(3), + Q => \req_col_r_reg[9]_0\(3), + R => '0' + ); +\req_col_r_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(4), + Q => \req_col_r_reg[9]_0\(4), + R => '0' + ); +\req_col_r_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(5), + Q => \req_col_r_reg[9]_0\(5), + R => '0' + ); +\req_col_r_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(6), + Q => \req_col_r_reg[9]_0\(6), + R => '0' + ); +\req_col_r_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(7), + Q => \req_col_r_reg[9]_0\(7), + R => '0' + ); +\req_col_r_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(8), + Q => \req_col_r_reg[9]_0\(8), + R => '0' + ); +\req_col_r_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(9), + Q => \req_col_r_reg[9]_0\(9), + R => '0' + ); +\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(0), + Q => \req_data_buf_addr_r_reg[4]_0\(0), + R => '0' + ); +\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(1), + Q => \req_data_buf_addr_r_reg[4]_0\(1), + R => '0' + ); +\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(2), + Q => \req_data_buf_addr_r_reg[4]_0\(2), + R => '0' + ); +\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(3), + Q => \req_data_buf_addr_r_reg[4]_0\(3), + R => '0' + ); +\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(4), + Q => \req_data_buf_addr_r_reg[4]_0\(4), + R => '0' + ); +req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => periodic_rd_insert, + Q => req_periodic_rd_r(0), + R => '0' + ); +req_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_priority_r_reg_0, + Q => req_priority_r, + R => '0' + ); +\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(0), + Q => \^req_row_r_lcl_reg[14]_0\(0), + R => '0' + ); +\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(10), + Q => \^req_row_r_lcl_reg[14]_0\(10), + R => '0' + ); +\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(11), + Q => \^req_row_r_lcl_reg[14]_0\(11), + R => '0' + ); +\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(12), + Q => \^req_row_r_lcl_reg[14]_0\(12), + R => '0' + ); +\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(13), + Q => \^req_row_r_lcl_reg[14]_0\(13), + R => '0' + ); +\req_row_r_lcl_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(14), + Q => \^req_row_r_lcl_reg[14]_0\(14), + R => '0' + ); +\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(1), + Q => \^req_row_r_lcl_reg[14]_0\(1), + R => '0' + ); +\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(2), + Q => \^req_row_r_lcl_reg[14]_0\(2), + R => '0' + ); +\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(3), + Q => \^req_row_r_lcl_reg[14]_0\(3), + R => '0' + ); +\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(4), + Q => \^req_row_r_lcl_reg[14]_0\(4), + R => '0' + ); +\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(5), + Q => \^req_row_r_lcl_reg[14]_0\(5), + R => '0' + ); +\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(6), + Q => \^req_row_r_lcl_reg[14]_0\(6), + R => '0' + ); +\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(7), + Q => \^req_row_r_lcl_reg[14]_0\(7), + R => '0' + ); +\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(8), + Q => \^req_row_r_lcl_reg[14]_0\(8), + R => '0' + ); +\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(9), + Q => \^req_row_r_lcl_reg[14]_0\(9), + R => '0' + ); +req_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_wr_r_lcl0, + Q => \^req_wr_r_lcl_reg_0\, + R => '0' + ); +row_hit_ns_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => row_hit_ns_carry_n_0, + CO(2) => row_hit_ns_carry_n_1, + CO(1) => row_hit_ns_carry_n_2, + CO(0) => row_hit_ns_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0), + S(3) => \row_hit_ns_carry_i_1__1_n_0\, + S(2) => \row_hit_ns_carry_i_2__1_n_0\, + S(1) => \row_hit_ns_carry_i_3__1_n_0\, + S(0) => \row_hit_ns_carry_i_4__1_n_0\ + ); +\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => row_hit_ns_carry_n_0, + CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \row_hit_ns_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \row_hit_ns_carry__0_i_1__1_n_0\ + ); +\row_hit_ns_carry__0_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(14), + I1 => row(14), + I2 => \^req_row_r_lcl_reg[14]_0\(12), + I3 => row(12), + I4 => row(13), + I5 => \^req_row_r_lcl_reg[14]_0\(13), + O => \row_hit_ns_carry__0_i_1__1_n_0\ + ); +\row_hit_ns_carry_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(11), + I1 => row(11), + I2 => \^req_row_r_lcl_reg[14]_0\(10), + I3 => row(10), + I4 => row(9), + I5 => \^req_row_r_lcl_reg[14]_0\(9), + O => \row_hit_ns_carry_i_1__1_n_0\ + ); +\row_hit_ns_carry_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(8), + I1 => row(8), + I2 => \^req_row_r_lcl_reg[14]_0\(7), + I3 => row(7), + I4 => row(6), + I5 => \^req_row_r_lcl_reg[14]_0\(6), + O => \row_hit_ns_carry_i_2__1_n_0\ + ); +\row_hit_ns_carry_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(5), + I1 => row(5), + I2 => \^req_row_r_lcl_reg[14]_0\(4), + I3 => row(4), + I4 => row(3), + I5 => \^req_row_r_lcl_reg[14]_0\(3), + O => \row_hit_ns_carry_i_3__1_n_0\ + ); +\row_hit_ns_carry_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(2), + I1 => row(2), + I2 => \^req_row_r_lcl_reg[14]_0\(1), + I3 => row(1), + I4 => row(0), + I5 => \^req_row_r_lcl_reg[14]_0\(0), + O => \row_hit_ns_carry_i_4__1_n_0\ + ); +row_hit_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \row_hit_ns_carry__0_n_3\, + Q => \^row_hit_r\, + R => '0' + ); +\wr_this_rank_r[0]_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + O => start_wtp_timer0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_compare_1 is + port ( + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg_0 : out STD_LOGIC; + req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rb_hit_busy_r_reg_0 : out STD_LOGIC; + req_priority_r : out STD_LOGIC; + row_hit_r : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC; + req_wr_r_lcl_reg_0 : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13_0\ : out STD_LOGIC; + set_order_q : out STD_LOGIC; + rd_wr_r_lcl_reg_1 : out STD_LOGIC; + rd_wr_r_lcl_reg_2 : out STD_LOGIC; + pass_open_bank_ns : out STD_LOGIC; + bm_end : out STD_LOGIC_VECTOR ( 0 to 0 ); + start_wtp_timer0 : out STD_LOGIC; + \req_row_r_lcl_reg[14]_0\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_row_r_lcl_reg[10]_0\ : out STD_LOGIC; + \req_data_buf_addr_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + periodic_rd_insert : in STD_LOGIC; + CLK : in STD_LOGIC; + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + req_priority_r_reg_0 : in STD_LOGIC; + ordered_r_lcl_reg : in STD_LOGIC; + pass_open_bank_r : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pre_bm_end_r : in STD_LOGIC; + head_r_lcl_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg_3 : in STD_LOGIC; + rd_wr_r_lcl_reg_4 : in STD_LOGIC; + ordered_r_lcl_reg_0 : in STD_LOGIC; + ordered_r_lcl : in STD_LOGIC; + rd_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_bank_rdy_r_i_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + pass_open_bank_r_lcl_reg : in STD_LOGIC; + tail_r : in STD_LOGIC; + pre_wait_r : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_2 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_3 : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[10]_0\ : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[10]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_address_reg[10]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_address_reg[10]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \req_data_buf_addr_r_reg[4]_1\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_compare_1 : entity is "mig_7series_v4_2_bank_compare"; +end ddr3_mig_7series_v4_2_bank_compare_1; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_compare_1 is + signal \pass_open_bank_r_lcl_i_4__1_n_0\ : STD_LOGIC; + signal rd_wr_ns : STD_LOGIC; + signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC; + signal \^req_row_r_lcl_reg[14]_0\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \row_hit_ns_carry__0_i_1__0_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry__0_n_3\ : STD_LOGIC; + signal \row_hit_ns_carry_i_1__0_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_2__0_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_3__0_n_0\ : STD_LOGIC; + signal \row_hit_ns_carry_i_4__0_n_0\ : STD_LOGIC; + signal row_hit_ns_carry_n_0 : STD_LOGIC; + signal row_hit_ns_carry_n_1 : STD_LOGIC; + signal row_hit_ns_carry_n_2 : STD_LOGIC; + signal row_hit_ns_carry_n_3 : STD_LOGIC; + signal \^row_hit_r\ : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__13\ : STD_LOGIC; + signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \bm_end_r1_i_1__1\ : label is "soft_lutpair514"; + attribute SOFT_HLUTNM of \ras_timer_r[0]_i_4__1\ : label is "soft_lutpair514"; + attribute SOFT_HLUTNM of \rd_wr_r_lcl_i_1__2\ : label is "soft_lutpair515"; + attribute SOFT_HLUTNM of \wr_this_rank_r[0]_i_1__0\ : label is "soft_lutpair515"; +begin + rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\; + \req_row_r_lcl_reg[14]_0\(14 downto 0) <= \^req_row_r_lcl_reg[14]_0\(14 downto 0); + req_wr_r(0) <= \^req_wr_r\(0); + row_hit_r <= \^row_hit_r\; + \rstdiv0_sync_r1_reg_rep__13\ <= \^rstdiv0_sync_r1_reg_rep__13\; +\bm_end_r1_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7000" + ) + port map ( + I0 => \^req_wr_r\(0), + I1 => \^rd_wr_r_lcl_reg_0\, + I2 => pass_open_bank_r, + I3 => Q(1), + I4 => pre_bm_end_r, + O => bm_end(0) + ); +\cmd_pipe_plus.mc_address[10]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80808080808080" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(10), + I1 => \cmd_pipe_plus.mc_address_reg[10]\, + I2 => \cmd_pipe_plus.mc_address_reg[10]_0\, + I3 => \cmd_pipe_plus.mc_address_reg[10]_1\(0), + I4 => \cmd_pipe_plus.mc_address_reg[10]_2\(0), + I5 => \cmd_pipe_plus.mc_address_reg[10]_3\(0), + O => \req_row_r_lcl_reg[10]_0\ + ); +\head_r_lcl_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000008FFF" + ) + port map ( + I0 => \^req_wr_r\(0), + I1 => \^rd_wr_r_lcl_reg_0\, + I2 => pass_open_bank_r, + I3 => Q(1), + I4 => pre_bm_end_r, + I5 => head_r_lcl_reg(0), + O => req_wr_r_lcl_reg_0 + ); +\order_q_r[1]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^req_wr_r\(0), + I1 => ordered_r_lcl_reg_0, + O => set_order_q + ); +\ordered_r_lcl_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5400545450505050" + ) + port map ( + I0 => ordered_r_lcl_reg, + I1 => ordered_r_lcl_reg_0, + I2 => ordered_r_lcl, + I3 => \^rd_wr_r_lcl_reg_0\, + I4 => Q(1), + I5 => \^req_wr_r\(0), + O => \rstdiv0_sync_r1_reg_rep__13_0\ + ); +\pass_open_bank_r_lcl_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444454444444444" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__13\, + I1 => pass_open_bank_r, + I2 => pass_open_bank_r_lcl_reg, + I3 => tail_r, + I4 => pre_wait_r, + I5 => \pass_open_bank_r_lcl_i_4__1_n_0\, + O => pass_open_bank_ns + ); +\pass_open_bank_r_lcl_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBFAAAAAA" + ) + port map ( + I0 => ordered_r_lcl_reg, + I1 => \^req_wr_r\(0), + I2 => \^rd_wr_r_lcl_reg_0\, + I3 => pass_open_bank_r, + I4 => Q(1), + I5 => pre_bm_end_r, + O => \^rstdiv0_sync_r1_reg_rep__13\ + ); +\pass_open_bank_r_lcl_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAA00A2" + ) + port map ( + I0 => \^row_hit_r\, + I1 => maint_req_r, + I2 => pass_open_bank_r_lcl_reg_0, + I3 => pass_open_bank_r_lcl_reg_1, + I4 => pass_open_bank_r_lcl_reg_2, + I5 => pass_open_bank_r_lcl_reg_3, + O => \pass_open_bank_r_lcl_i_4__1_n_0\ + ); +\ras_timer_r[0]_i_4__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(1), + O => rd_wr_r_lcl_reg_2 + ); +rb_hit_busy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rb_hit_busy_r_reg_1, + Q => rb_hit_busy_r_reg_0, + R => '0' + ); +\rd_wr_r_lcl_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(1), + I2 => rd_wr_r_lcl_reg_3, + I3 => rd_wr_r_lcl_reg_4, + O => rd_wr_ns + ); +rd_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_wr_ns, + Q => \^rd_wr_r_lcl_reg_0\, + R => '0' + ); +\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(0), + Q => \req_bank_r_lcl_reg[2]_0\(0), + R => '0' + ); +\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(1), + Q => \req_bank_r_lcl_reg[2]_0\(1), + R => '0' + ); +\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(2), + Q => \req_bank_r_lcl_reg[2]_0\(2), + R => '0' + ); +req_bank_rdy_r_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"40FF404040404040" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => Q(1), + I2 => \^req_wr_r\(0), + I3 => rd_wr_r(0), + I4 => Q(0), + I5 => req_bank_rdy_r_i_2(0), + O => rd_wr_r_lcl_reg_1 + ); +\req_col_r_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(0), + Q => \req_col_r_reg[9]_0\(0), + R => '0' + ); +\req_col_r_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(1), + Q => \req_col_r_reg[9]_0\(1), + R => '0' + ); +\req_col_r_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(2), + Q => \req_col_r_reg[9]_0\(2), + R => '0' + ); +\req_col_r_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(3), + Q => \req_col_r_reg[9]_0\(3), + R => '0' + ); +\req_col_r_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(4), + Q => \req_col_r_reg[9]_0\(4), + R => '0' + ); +\req_col_r_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(5), + Q => \req_col_r_reg[9]_0\(5), + R => '0' + ); +\req_col_r_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(6), + Q => \req_col_r_reg[9]_0\(6), + R => '0' + ); +\req_col_r_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(7), + Q => \req_col_r_reg[9]_0\(7), + R => '0' + ); +\req_col_r_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(8), + Q => \req_col_r_reg[9]_0\(8), + R => '0' + ); +\req_col_r_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(9), + Q => \req_col_r_reg[9]_0\(9), + R => '0' + ); +\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(0), + Q => \req_data_buf_addr_r_reg[4]_0\(0), + R => '0' + ); +\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(1), + Q => \req_data_buf_addr_r_reg[4]_0\(1), + R => '0' + ); +\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(2), + Q => \req_data_buf_addr_r_reg[4]_0\(2), + R => '0' + ); +\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(3), + Q => \req_data_buf_addr_r_reg[4]_0\(3), + R => '0' + ); +\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(4), + Q => \req_data_buf_addr_r_reg[4]_0\(4), + R => '0' + ); +req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => periodic_rd_insert, + Q => req_periodic_rd_r(0), + R => '0' + ); +req_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_priority_r_reg_0, + Q => req_priority_r, + R => '0' + ); +\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(0), + Q => \^req_row_r_lcl_reg[14]_0\(0), + R => '0' + ); +\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(10), + Q => \^req_row_r_lcl_reg[14]_0\(10), + R => '0' + ); +\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(11), + Q => \^req_row_r_lcl_reg[14]_0\(11), + R => '0' + ); +\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(12), + Q => \^req_row_r_lcl_reg[14]_0\(12), + R => '0' + ); +\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(13), + Q => \^req_row_r_lcl_reg[14]_0\(13), + R => '0' + ); +\req_row_r_lcl_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(14), + Q => \^req_row_r_lcl_reg[14]_0\(14), + R => '0' + ); +\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(1), + Q => \^req_row_r_lcl_reg[14]_0\(1), + R => '0' + ); +\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(2), + Q => \^req_row_r_lcl_reg[14]_0\(2), + R => '0' + ); +\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(3), + Q => \^req_row_r_lcl_reg[14]_0\(3), + R => '0' + ); +\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(4), + Q => \^req_row_r_lcl_reg[14]_0\(4), + R => '0' + ); +\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(5), + Q => \^req_row_r_lcl_reg[14]_0\(5), + R => '0' + ); +\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(6), + Q => \^req_row_r_lcl_reg[14]_0\(6), + R => '0' + ); +\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(7), + Q => \^req_row_r_lcl_reg[14]_0\(7), + R => '0' + ); +\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(8), + Q => \^req_row_r_lcl_reg[14]_0\(8), + R => '0' + ); +\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(9), + Q => \^req_row_r_lcl_reg[14]_0\(9), + R => '0' + ); +req_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_wr_r_lcl0, + Q => \^req_wr_r\(0), + R => '0' + ); +row_hit_ns_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => row_hit_ns_carry_n_0, + CO(2) => row_hit_ns_carry_n_1, + CO(1) => row_hit_ns_carry_n_2, + CO(0) => row_hit_ns_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0), + S(3) => \row_hit_ns_carry_i_1__0_n_0\, + S(2) => \row_hit_ns_carry_i_2__0_n_0\, + S(1) => \row_hit_ns_carry_i_3__0_n_0\, + S(0) => \row_hit_ns_carry_i_4__0_n_0\ + ); +\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => row_hit_ns_carry_n_0, + CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => \row_hit_ns_carry__0_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => \row_hit_ns_carry__0_i_1__0_n_0\ + ); +\row_hit_ns_carry__0_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(14), + I1 => row(14), + I2 => \^req_row_r_lcl_reg[14]_0\(13), + I3 => row(13), + I4 => row(12), + I5 => \^req_row_r_lcl_reg[14]_0\(12), + O => \row_hit_ns_carry__0_i_1__0_n_0\ + ); +\row_hit_ns_carry_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(11), + I1 => row(11), + I2 => \^req_row_r_lcl_reg[14]_0\(9), + I3 => row(9), + I4 => row(10), + I5 => \^req_row_r_lcl_reg[14]_0\(10), + O => \row_hit_ns_carry_i_1__0_n_0\ + ); +\row_hit_ns_carry_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(8), + I1 => row(8), + I2 => \^req_row_r_lcl_reg[14]_0\(6), + I3 => row(6), + I4 => row(7), + I5 => \^req_row_r_lcl_reg[14]_0\(7), + O => \row_hit_ns_carry_i_2__0_n_0\ + ); +\row_hit_ns_carry_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(5), + I1 => row(5), + I2 => \^req_row_r_lcl_reg[14]_0\(4), + I3 => row(4), + I4 => row(3), + I5 => \^req_row_r_lcl_reg[14]_0\(3), + O => \row_hit_ns_carry_i_3__0_n_0\ + ); +\row_hit_ns_carry_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^req_row_r_lcl_reg[14]_0\(2), + I1 => row(2), + I2 => \^req_row_r_lcl_reg[14]_0\(1), + I3 => row(1), + I4 => row(0), + I5 => \^req_row_r_lcl_reg[14]_0\(0), + O => \row_hit_ns_carry_i_4__0_n_0\ + ); +row_hit_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \row_hit_ns_carry__0_n_3\, + Q => \^row_hit_r\, + R => '0' + ); +\wr_this_rank_r[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + O => start_wtp_timer0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_compare_2 is + port ( + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg_0 : out STD_LOGIC; + req_wr_r_lcl_reg_0 : out STD_LOGIC; + req_priority_r : out STD_LOGIC; + rb_hit_busy_r_reg_0 : out STD_LOGIC; + row_hit_r : out STD_LOGIC; + pass_open_bank_ns : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13_0\ : out STD_LOGIC; + set_order_q : out STD_LOGIC; + start_wtp_timer0 : out STD_LOGIC; + rd_wr_r_lcl_reg_1 : out STD_LOGIC; + rb_hit_busy_r_reg_1 : out STD_LOGIC; + rb_hit_busy_r_reg_2 : out STD_LOGIC; + \req_data_buf_addr_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_row_r_lcl_reg[14]_0\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_col_r_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + periodic_rd_insert : in STD_LOGIC; + CLK : in STD_LOGIC; + req_wr_r_lcl0 : in STD_LOGIC; + req_priority_r_reg_0 : in STD_LOGIC; + rb_hit_busy_r_reg_3 : in STD_LOGIC; + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + row_hit_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + pass_open_bank_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + tail_r : in STD_LOGIC; + pre_wait_r : in STD_LOGIC; + rd_wr_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg_3 : in STD_LOGIC; + rd_wr_r_lcl_reg_4 : in STD_LOGIC; + ordered_r_lcl_reg : in STD_LOGIC; + pre_bm_end_r : in STD_LOGIC; + ordered_r_lcl_reg_0 : in STD_LOGIC; + ordered_r : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_2 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_3 : in STD_LOGIC; + \q_entry_r[1]_i_4__0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_data_buf_addr_r_reg[4]_1\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_2\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_col_r_reg[9]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_compare_2 : entity is "mig_7series_v4_2_bank_compare"; +end ddr3_mig_7series_v4_2_bank_compare_2; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_compare_2 is + signal \pass_open_bank_r_lcl_i_4__2_n_0\ : STD_LOGIC; + signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC; + signal rd_wr_ns : STD_LOGIC; + signal \^rd_wr_r_lcl_reg_0\ : STD_LOGIC; + signal \^req_wr_r_lcl_reg_0\ : STD_LOGIC; + signal row_hit_ns : STD_LOGIC; + signal row_hit_ns_carry_n_0 : STD_LOGIC; + signal row_hit_ns_carry_n_1 : STD_LOGIC; + signal row_hit_ns_carry_n_2 : STD_LOGIC; + signal row_hit_ns_carry_n_3 : STD_LOGIC; + signal \^row_hit_r\ : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__13\ : STD_LOGIC; + signal NLW_row_hit_ns_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_row_hit_ns_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_5__1\ : label is "soft_lutpair503"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_7__1\ : label is "soft_lutpair503"; + attribute SOFT_HLUTNM of \ras_timer_r[0]_i_4__0\ : label is "soft_lutpair502"; + attribute SOFT_HLUTNM of rd_wr_r_lcl_i_1 : label is "soft_lutpair502"; +begin + rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\; + rd_wr_r_lcl_reg_0 <= \^rd_wr_r_lcl_reg_0\; + req_wr_r_lcl_reg_0 <= \^req_wr_r_lcl_reg_0\; + row_hit_r <= \^row_hit_r\; + \rstdiv0_sync_r1_reg_rep__13\ <= \^rstdiv0_sync_r1_reg_rep__13\; +\order_q_r[1]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^req_wr_r_lcl_reg_0\, + I1 => ordered_r_lcl_reg_0, + O => set_order_q + ); +\ordered_r_lcl_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5400545450505050" + ) + port map ( + I0 => ordered_r_lcl_reg, + I1 => ordered_r_lcl_reg_0, + I2 => ordered_r, + I3 => \^rd_wr_r_lcl_reg_0\, + I4 => rd_wr_r_lcl_reg_2(0), + I5 => \^req_wr_r_lcl_reg_0\, + O => \rstdiv0_sync_r1_reg_rep__13_0\ + ); +pass_open_bank_r_lcl_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444454444444444" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__13\, + I1 => pass_open_bank_r, + I2 => pass_open_bank_r_lcl_reg, + I3 => tail_r, + I4 => pre_wait_r, + I5 => \pass_open_bank_r_lcl_i_4__2_n_0\, + O => pass_open_bank_ns + ); +pass_open_bank_r_lcl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBFAAAAAA" + ) + port map ( + I0 => ordered_r_lcl_reg, + I1 => \^req_wr_r_lcl_reg_0\, + I2 => \^rd_wr_r_lcl_reg_0\, + I3 => pass_open_bank_r, + I4 => rd_wr_r_lcl_reg_2(0), + I5 => pre_bm_end_r, + O => \^rstdiv0_sync_r1_reg_rep__13\ + ); +\pass_open_bank_r_lcl_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAA00A2" + ) + port map ( + I0 => \^row_hit_r\, + I1 => maint_req_r, + I2 => pass_open_bank_r_lcl_reg_0, + I3 => pass_open_bank_r_lcl_reg_1, + I4 => pass_open_bank_r_lcl_reg_2, + I5 => pass_open_bank_r_lcl_reg_3, + O => \pass_open_bank_r_lcl_i_4__2_n_0\ + ); +\q_entry_r[1]_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6996" + ) + port map ( + I0 => \^rb_hit_busy_r_reg_0\, + I1 => \q_entry_r[1]_i_4__0\(0), + I2 => \q_entry_r[1]_i_4__0\(1), + I3 => \q_entry_r[1]_i_4__0\(2), + O => rb_hit_busy_r_reg_2 + ); +\q_entry_r[1]_i_7__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7EE8" + ) + port map ( + I0 => \^rb_hit_busy_r_reg_0\, + I1 => \q_entry_r[1]_i_4__0\(2), + I2 => \q_entry_r[1]_i_4__0\(1), + I3 => \q_entry_r[1]_i_4__0\(0), + O => rb_hit_busy_r_reg_1 + ); +\ras_timer_r[0]_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => rd_wr_r_lcl_reg_2(0), + O => rd_wr_r_lcl_reg_1 + ); +rb_hit_busy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rb_hit_busy_r_reg_3, + Q => \^rb_hit_busy_r_reg_0\, + R => '0' + ); +rd_wr_r_lcl_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + I1 => rd_wr_r_lcl_reg_2(0), + I2 => rd_wr_r_lcl_reg_3, + I3 => rd_wr_r_lcl_reg_4, + O => rd_wr_ns + ); +rd_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_wr_ns, + Q => \^rd_wr_r_lcl_reg_0\, + R => '0' + ); +\req_bank_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(0), + Q => \req_bank_r_lcl_reg[2]_0\(0), + R => '0' + ); +\req_bank_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(1), + Q => \req_bank_r_lcl_reg[2]_0\(1), + R => '0' + ); +\req_bank_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \req_bank_r_lcl_reg[2]_1\(2), + Q => \req_bank_r_lcl_reg[2]_0\(2), + R => '0' + ); +\req_col_r_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(0), + Q => \req_col_r_reg[9]_0\(0), + R => '0' + ); +\req_col_r_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(1), + Q => \req_col_r_reg[9]_0\(1), + R => '0' + ); +\req_col_r_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(2), + Q => \req_col_r_reg[9]_0\(2), + R => '0' + ); +\req_col_r_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(3), + Q => \req_col_r_reg[9]_0\(3), + R => '0' + ); +\req_col_r_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(4), + Q => \req_col_r_reg[9]_0\(4), + R => '0' + ); +\req_col_r_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(5), + Q => \req_col_r_reg[9]_0\(5), + R => '0' + ); +\req_col_r_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(6), + Q => \req_col_r_reg[9]_0\(6), + R => '0' + ); +\req_col_r_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(7), + Q => \req_col_r_reg[9]_0\(7), + R => '0' + ); +\req_col_r_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(8), + Q => \req_col_r_reg[9]_0\(8), + R => '0' + ); +\req_col_r_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => E(0), + D => \req_col_r_reg[9]_1\(9), + Q => \req_col_r_reg[9]_0\(9), + R => '0' + ); +\req_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(0), + Q => \req_data_buf_addr_r_reg[4]_0\(0), + R => '0' + ); +\req_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(1), + Q => \req_data_buf_addr_r_reg[4]_0\(1), + R => '0' + ); +\req_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(2), + Q => \req_data_buf_addr_r_reg[4]_0\(2), + R => '0' + ); +\req_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(3), + Q => \req_data_buf_addr_r_reg[4]_0\(3), + R => '0' + ); +\req_data_buf_addr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \req_data_buf_addr_r_reg[4]_1\, + D => \req_data_buf_addr_r_reg[4]_2\(4), + Q => \req_data_buf_addr_r_reg[4]_0\(4), + R => '0' + ); +req_periodic_rd_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => periodic_rd_insert, + Q => req_periodic_rd_r(0), + R => '0' + ); +req_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_priority_r_reg_0, + Q => req_priority_r, + R => '0' + ); +\req_row_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(0), + Q => \req_row_r_lcl_reg[14]_0\(0), + R => '0' + ); +\req_row_r_lcl_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(10), + Q => \req_row_r_lcl_reg[14]_0\(10), + R => '0' + ); +\req_row_r_lcl_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(11), + Q => \req_row_r_lcl_reg[14]_0\(11), + R => '0' + ); +\req_row_r_lcl_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(12), + Q => \req_row_r_lcl_reg[14]_0\(12), + R => '0' + ); +\req_row_r_lcl_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(13), + Q => \req_row_r_lcl_reg[14]_0\(13), + R => '0' + ); +\req_row_r_lcl_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(14), + Q => \req_row_r_lcl_reg[14]_0\(14), + R => '0' + ); +\req_row_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(1), + Q => \req_row_r_lcl_reg[14]_0\(1), + R => '0' + ); +\req_row_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(2), + Q => \req_row_r_lcl_reg[14]_0\(2), + R => '0' + ); +\req_row_r_lcl_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(3), + Q => \req_row_r_lcl_reg[14]_0\(3), + R => '0' + ); +\req_row_r_lcl_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(4), + Q => \req_row_r_lcl_reg[14]_0\(4), + R => '0' + ); +\req_row_r_lcl_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(5), + Q => \req_row_r_lcl_reg[14]_0\(5), + R => '0' + ); +\req_row_r_lcl_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(6), + Q => \req_row_r_lcl_reg[14]_0\(6), + R => '0' + ); +\req_row_r_lcl_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(7), + Q => \req_row_r_lcl_reg[14]_0\(7), + R => '0' + ); +\req_row_r_lcl_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(8), + Q => \req_row_r_lcl_reg[14]_0\(8), + R => '0' + ); +\req_row_r_lcl_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => row(9), + Q => \req_row_r_lcl_reg[14]_0\(9), + R => '0' + ); +req_wr_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => req_wr_r_lcl0, + Q => \^req_wr_r_lcl_reg_0\, + R => '0' + ); +row_hit_ns_carry: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => row_hit_ns_carry_n_0, + CO(2) => row_hit_ns_carry_n_1, + CO(1) => row_hit_ns_carry_n_2, + CO(0) => row_hit_ns_carry_n_3, + CYINIT => '1', + DI(3 downto 0) => B"0000", + O(3 downto 0) => NLW_row_hit_ns_carry_O_UNCONNECTED(3 downto 0), + S(3 downto 0) => S(3 downto 0) + ); +\row_hit_ns_carry__0\: unisim.vcomponents.CARRY4 + port map ( + CI => row_hit_ns_carry_n_0, + CO(3 downto 1) => \NLW_row_hit_ns_carry__0_CO_UNCONNECTED\(3 downto 1), + CO(0) => row_hit_ns, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3 downto 0) => \NLW_row_hit_ns_carry__0_O_UNCONNECTED\(3 downto 0), + S(3 downto 1) => B"000", + S(0) => row_hit_r_reg_0(0) + ); +row_hit_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => row_hit_ns, + Q => \^row_hit_r\, + R => '0' + ); +\wr_this_rank_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rd_wr_r_lcl_reg_0\, + O => start_wtp_timer0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_queue is + port ( + idle_r_lcl_reg_0 : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + pass_open_bank_r : out STD_LOGIC; + pre_bm_end_r : out STD_LOGIC; + q_has_rd : out STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : out STD_LOGIC; + tail_r : out STD_LOGIC; + head_r_lcl_reg_0 : out STD_LOGIC; + auto_pre_r_lcl_reg_0 : out STD_LOGIC; + ordered_r : out STD_LOGIC; + pre_bm_end_r_reg_0 : out STD_LOGIC; + idle_r_lcl_reg_1 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg_2 : out STD_LOGIC; + pre_bm_end_r_reg_1 : out STD_LOGIC; + idle_r_lcl_reg_3 : out STD_LOGIC; + \q_entry_r_reg[1]_0\ : out STD_LOGIC; + \q_entry_r_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + demand_priority_ns : out STD_LOGIC; + \order_q_r_reg[1]_0\ : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + req_bank_rdy_ns : out STD_LOGIC; + pre_passing_open_bank_r_reg_0 : out STD_LOGIC; + idle_r_lcl_reg_4 : out STD_LOGIC; + act_wait_ns : out STD_LOGIC; + p_9_in : out STD_LOGIC; + idle_r_lcl_reg_5 : out STD_LOGIC; + idle_r_lcl_reg_6 : out STD_LOGIC; + pre_bm_end_r_reg_2 : out STD_LOGIC; + pre_bm_end_r_reg_3 : out STD_LOGIC; + idle_r_lcl_reg_7 : out STD_LOGIC; + act_wait_r_lcl_reg : out STD_LOGIC; + CLK : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + pre_bm_end_ns : in STD_LOGIC; + pre_passing_open_bank_ns : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_2 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ordered_r_lcl_reg_0 : in STD_LOGIC; + \q_entry_r_reg[0]_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC; + q_has_priority_r_reg_0 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[0]\ : in STD_LOGIC; + q_has_rd_r_reg_0 : in STD_LOGIC; + was_wr : in STD_LOGIC; + q_has_priority_r_reg_1 : in STD_LOGIC; + q_has_priority_r_reg_2 : in STD_LOGIC; + was_priority : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC; + \q_entry_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + act_wait_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + act_wait_r_lcl_reg_1 : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + demand_priority_r_reg : in STD_LOGIC; + req_priority_r : in STD_LOGIC; + demand_priority_r_reg_0 : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + bm_end_r1_reg : in STD_LOGIC; + req_bank_rdy_r_reg_0 : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]_2\ : in STD_LOGIC; + bm_end_r1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + bm_end_r1_reg_1 : in STD_LOGIC; + \q_entry_r_reg[1]_5\ : in STD_LOGIC; + bm_end_r1 : in STD_LOGIC; + auto_pre_r_lcl_reg_1 : in STD_LOGIC; + auto_pre_r_lcl_reg_2 : in STD_LOGIC; + row_hit_r : in STD_LOGIC; + auto_pre_r_lcl_reg_3 : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + accept_internal_r_reg : in STD_LOGIC; + accept_internal_r_reg_0 : in STD_LOGIC; + accept_internal_r_reg_1 : in STD_LOGIC; + accept_internal_r_reg_2 : in STD_LOGIC; + head_r_lcl_reg_1 : in STD_LOGIC; + head_r_lcl_reg_2 : in STD_LOGIC; + ras_timer_zero_r : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \ras_timer_r_reg[0]_5\ : in STD_LOGIC; + \q_entry_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \q_entry_r_reg[0]_2\ : in STD_LOGIC; + \q_entry_r_reg[1]_6\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]_1\ : in STD_LOGIC; + set_order_q : in STD_LOGIC; + \order_q_r_reg[0]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_queue : entity is "mig_7series_v4_2_bank_queue"; +end ddr3_mig_7series_v4_2_bank_queue; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_queue is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal auto_pre_r_lcl_i_1_n_0 : STD_LOGIC; + signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC; + signal \compute_tail.tail_r_lcl_i_1_n_0\ : STD_LOGIC; + signal head_r_lcl_i_1_n_0 : STD_LOGIC; + signal \head_r_lcl_i_3__1_n_0\ : STD_LOGIC; + signal \head_r_lcl_i_4__1_n_0\ : STD_LOGIC; + signal \^head_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_1\ : STD_LOGIC; + signal \^idle_r_lcl_reg_2\ : STD_LOGIC; + signal \^idle_r_lcl_reg_3\ : STD_LOGIC; + signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC; + signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC; + signal \^order_q_r_reg[1]_0\ : STD_LOGIC; + signal \^pass_open_bank_r\ : STD_LOGIC; + signal \^pre_bm_end_r\ : STD_LOGIC; + signal \^pre_bm_end_r_reg_0\ : STD_LOGIC; + signal pre_passing_open_bank_r : STD_LOGIC; + signal q_entry_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[0]_i_4_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_2__2_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_3_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_4__1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_6__0_n_0\ : STD_LOGIC; + signal \^q_entry_r_reg[1]_0\ : STD_LOGIC; + signal q_has_priority : STD_LOGIC; + signal q_has_priority_r_i_1_n_0 : STD_LOGIC; + signal q_has_rd_r_i_1_n_0 : STD_LOGIC; + signal \ras_timer_r[0]_i_2__1_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_2__2_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_3__1_n_0\ : STD_LOGIC; + signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \^tail_r\ : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \demand_priority_r_i_2__2\ : label is "soft_lutpair507"; + attribute SOFT_HLUTNM of \head_r_lcl_i_3__2\ : label is "soft_lutpair509"; + attribute SOFT_HLUTNM of \head_r_lcl_i_4__1\ : label is "soft_lutpair506"; + attribute SOFT_HLUTNM of idle_r_lcl_i_1 : label is "soft_lutpair504"; + attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[0]_i_1\ : label is "soft_lutpair504"; + attribute SOFT_HLUTNM of \q_entry_r[0]_i_3\ : label is "soft_lutpair509"; + attribute SOFT_HLUTNM of \q_entry_r[0]_i_3__0\ : label is "soft_lutpair508"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_2__0\ : label is "soft_lutpair505"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_4__1\ : label is "soft_lutpair506"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_5__0\ : label is "soft_lutpair505"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_6__2\ : label is "soft_lutpair508"; + attribute SOFT_HLUTNM of \req_bank_rdy_r_i_1__2\ : label is "soft_lutpair507"; +begin + E(0) <= \^e\(0); + auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\; + head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\; + idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\; + idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\; + idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\; + idle_r_lcl_reg_3 <= \^idle_r_lcl_reg_3\; + \order_q_r_reg[1]_0\ <= \^order_q_r_reg[1]_0\; + pass_open_bank_r <= \^pass_open_bank_r\; + pre_bm_end_r <= \^pre_bm_end_r\; + pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\; + \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\; + tail_r <= \^tail_r\; + wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\; +accept_internal_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"2AAAAAAA" + ) + port map ( + I0 => accept_internal_r_reg, + I1 => \^idle_r_lcl_reg_2\, + I2 => accept_internal_r_reg_0, + I3 => accept_internal_r_reg_1, + I4 => accept_internal_r_reg_2, + O => p_9_in + ); +\act_wait_r_lcl_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF444" + ) + port map ( + I0 => \^q_entry_r_reg[1]_0\, + I1 => act_wait_r_lcl_reg_1, + I2 => \^pass_open_bank_r\, + I3 => \^pre_bm_end_r_reg_0\, + I4 => q_has_priority_r_reg_0, + I5 => bm_end_r1, + O => act_wait_ns + ); +\act_wait_r_lcl_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF002000200020" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__2_n_0\, + I1 => q_entry_r(1), + I2 => q_entry_r(0), + I3 => \^idle_r_lcl_reg_0\, + I4 => act_wait_r_lcl_reg_0(0), + I5 => act_wait_r_lcl_reg_1, + O => \^q_entry_r_reg[1]_0\ + ); +auto_pre_r_lcl_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAEEEEE" + ) + port map ( + I0 => \^auto_pre_r_lcl_reg_0\, + I1 => auto_pre_r_lcl_reg_1, + I2 => \^wait_for_maint_r_lcl_reg_0\, + I3 => auto_pre_r_lcl_reg_2, + I4 => row_hit_r, + I5 => auto_pre_r_lcl_reg_3, + O => auto_pre_r_lcl_i_1_n_0 + ); +auto_pre_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => auto_pre_r_lcl_i_1_n_0, + Q => \^auto_pre_r_lcl_reg_0\, + R => '0' + ); +bm_end_r1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAEAEAEA" + ) + port map ( + I0 => \^pre_bm_end_r\, + I1 => bm_end_r1_reg_0(0), + I2 => \^pass_open_bank_r\, + I3 => bm_end_r1_reg, + I4 => bm_end_r1_reg_1, + O => \^pre_bm_end_r_reg_0\ + ); +\compute_tail.tail_r_lcl_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCFFECECECECECEC" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \q_entry_r_reg[0]_0\, + I2 => \compute_tail.tail_r_lcl_reg_0\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \compute_tail.tail_r_lcl_reg_1\, + I5 => \^tail_r\, + O => \compute_tail.tail_r_lcl_i_1_n_0\ + ); +\compute_tail.tail_r_lcl_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0), + O => pre_bm_end_r_reg_2 + ); +\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \compute_tail.tail_r_lcl_i_1_n_0\, + Q => \^tail_r\, + R => SR(0) + ); +\demand_priority_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888800008880" + ) + port map ( + I0 => demand_priority_r_reg, + I1 => \^idle_r_lcl_reg_2\, + I2 => req_priority_r, + I3 => q_has_priority, + I4 => \^order_q_r_reg[1]_0\, + I5 => demand_priority_r_reg_0, + O => demand_priority_ns + ); +\demand_priority_r_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EC" + ) + port map ( + I0 => req_bank_rdy_r_reg_0, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => bm_end_r1_reg, + O => \^order_q_r_reg[1]_0\ + ); +\grant_r[2]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^order_q_r_reg[1]_0\, + I1 => req_bank_rdy_r_reg, + I2 => \rnk_config_strobe_r_reg[0]\, + I3 => \rnk_config_strobe_r_reg[0]_0\, + O => col_wait_r_reg + ); +\grant_r[2]_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFDFFFFF" + ) + port map ( + I0 => act_wait_r_lcl_reg_1, + I1 => \^idle_r_lcl_reg_0\, + I2 => \^head_r_lcl_reg_0\, + I3 => \^wait_for_maint_r_lcl_reg_0\, + I4 => ras_timer_zero_r, + O => act_wait_r_lcl_reg + ); +head_r_lcl_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8FFB800" + ) + port map ( + I0 => \^idle_r_lcl_reg_1\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => \head_r_lcl_i_3__1_n_0\, + I3 => \q_entry_r[1]_i_4__1_n_0\, + I4 => \^head_r_lcl_reg_0\, + O => head_r_lcl_i_1_n_0 + ); +\head_r_lcl_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80010116" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \q_entry_r_reg[1]_2\(0), + I2 => \q_entry_r_reg[1]_3\(0), + I3 => \q_entry_r_reg[1]_4\(0), + I4 => q_has_priority_r_reg_2, + O => \^idle_r_lcl_reg_1\ + ); +\head_r_lcl_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FF000006060606" + ) + port map ( + I0 => head_r_lcl_reg_1, + I1 => \q_entry_r[1]_i_6__0_n_0\, + I2 => head_r_lcl_reg_2, + I3 => q_entry_r(1), + I4 => q_entry_r(0), + I5 => \head_r_lcl_i_4__1_n_0\, + O => \head_r_lcl_i_3__1_n_0\ + ); +\head_r_lcl_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + O => pre_bm_end_r_reg_1 + ); +\head_r_lcl_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0535" + ) + port map ( + I0 => \q_entry_r[1]_i_6__0_n_0\, + I1 => \q_entry_r_reg[0]_0\, + I2 => \^idle_r_lcl_reg_0\, + I3 => q_has_priority_r_reg_2, + O => \head_r_lcl_i_4__1_n_0\ + ); +head_r_lcl_reg: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => head_r_lcl_i_1_n_0, + Q => \^head_r_lcl_reg_0\, + S => SR(0) + ); +idle_r_lcl_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^idle_r_lcl_reg_2\, + O => \^e\(0) + ); +idle_r_lcl_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"000D" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \q_entry_r_reg[0]_0\, + I2 => \^pre_bm_end_r_reg_0\, + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\, + O => \^idle_r_lcl_reg_2\ + ); +idle_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^e\(0), + Q => \^idle_r_lcl_reg_0\, + R => '0' + ); +\maint_controller.maint_hit_busies_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10111010" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_0, + I2 => Q(0), + I3 => \maint_controller.maint_hit_busies_r_reg[0]\, + I4 => \^idle_r_lcl_reg_2\, + O => D(0) + ); +\order_q_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"550D000C550DF00C" + ) + port map ( + I0 => \order_q_r_reg[0]_0\, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg_0, + I4 => set_order_q, + I5 => q_has_priority_r_reg_0, + O => \order_q_r[0]_i_1_n_0\ + ); +\order_q_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAC200C0AAC2CCC0" + ) + port map ( + I0 => \order_q_r_reg[1]_1\, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg_0, + I4 => set_order_q, + I5 => q_has_priority_r_reg_0, + O => \order_q_r[1]_i_1_n_0\ + ); +\order_q_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[0]_i_1_n_0\, + Q => order_q_r(0), + R => '0' + ); +\order_q_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[1]_i_1_n_0\, + Q => order_q_r(1), + R => '0' + ); +ordered_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ordered_r_lcl_reg_0, + Q => ordered_r, + R => '0' + ); +pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pass_open_bank_ns, + Q => \^pass_open_bank_r\, + R => '0' + ); +pre_bm_end_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_bm_end_ns, + Q => \^pre_bm_end_r\, + R => '0' + ); +pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_passing_open_bank_ns, + Q => pre_passing_open_bank_r, + R => '0' + ); +\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88B8FFFF8BBB0000" + ) + port map ( + I0 => \q_entry_r_reg[0]_2\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => \q_entry_r_reg[0]_0\, + I3 => \q_entry_r[0]_i_4_n_0\, + I4 => \q_entry_r[1]_i_4__1_n_0\, + I5 => q_entry_r(0), + O => \q_entry_r[0]_i_1_n_0\ + ); +\q_entry_r[0]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9669" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + I2 => \^idle_r_lcl_reg_3\, + I3 => \^pre_bm_end_r_reg_0\, + O => pre_bm_end_r_reg_3 + ); +\q_entry_r[0]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \q_entry_r_reg[1]_4\(0), + I2 => \q_entry_r_reg[1]_3\(0), + I3 => \q_entry_r_reg[1]_2\(0), + I4 => \^idle_r_lcl_reg_0\, + O => idle_r_lcl_reg_7 + ); +\q_entry_r[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"96696996" + ) + port map ( + I0 => \q_entry_r[1]_i_6__0_n_0\, + I1 => \q_entry_r_reg[0]_1\(2), + I2 => \q_entry_r_reg[0]_1\(1), + I3 => \q_entry_r_reg[0]_1\(0), + I4 => q_has_priority_r_reg_1, + O => \q_entry_r[0]_i_4_n_0\ + ); +\q_entry_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F1FFF100" + ) + port map ( + I0 => \q_entry_r[1]_i_2__2_n_0\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => \q_entry_r[1]_i_3_n_0\, + I3 => \q_entry_r[1]_i_4__1_n_0\, + I4 => q_entry_r(1), + O => \q_entry_r[1]_i_1_n_0\ + ); +\q_entry_r[1]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A96A6A56" + ) + port map ( + I0 => \q_entry_r_reg[1]_5\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => \^idle_r_lcl_reg_3\, + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + O => idle_r_lcl_reg_4 + ); +\q_entry_r[1]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4DDBDBB2DBB2B224" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + I2 => \q_entry_r_reg[1]_4\(0), + I3 => \q_entry_r_reg[1]_3\(0), + I4 => \q_entry_r_reg[1]_2\(0), + I5 => \^idle_r_lcl_reg_0\, + O => idle_r_lcl_reg_6 + ); +\q_entry_r[1]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1E001EFF1EFF1E00" + ) + port map ( + I0 => head_r_lcl_reg_1, + I1 => \q_entry_r[1]_i_6__0_n_0\, + I2 => head_r_lcl_reg_2, + I3 => \q_entry_r_reg[0]_0\, + I4 => q_entry_r(1), + I5 => q_entry_r(0), + O => \q_entry_r[1]_i_2__2_n_0\ + ); +\q_entry_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7EE80000E8810000" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \q_entry_r_reg[1]_2\(0), + I2 => \q_entry_r_reg[1]_3\(0), + I3 => \q_entry_r_reg[1]_4\(0), + I4 => \^pre_bm_end_r_reg_0\, + I5 => q_has_priority_r_reg_2, + O => \q_entry_r[1]_i_3_n_0\ + ); +\q_entry_r[1]_i_4__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCFDFFFD" + ) + port map ( + I0 => \q_entry_r[1]_i_6__0_n_0\, + I1 => \q_entry_r_reg[0]_0\, + I2 => \^pre_bm_end_r_reg_0\, + I3 => \^idle_r_lcl_reg_0\, + I4 => q_has_priority_r_reg_2, + O => \q_entry_r[1]_i_4__1_n_0\ + ); +\q_entry_r[1]_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"9C39C69C" + ) + port map ( + I0 => \^idle_r_lcl_reg_3\, + I1 => \q_entry_r_reg[1]_5\, + I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + I3 => \^pre_bm_end_r_reg_0\, + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + O => idle_r_lcl_reg_5 + ); +\q_entry_r[1]_i_6__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7707770700007707" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0), + I1 => rb_hit_busies_r(3), + I2 => rb_hit_busies_r(2), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + I4 => rb_hit_busies_r(1), + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + O => \q_entry_r[1]_i_6__0_n_0\ + ); +\q_entry_r[1]_i_6__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6996" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \q_entry_r_reg[1]_2\(0), + I2 => \q_entry_r_reg[1]_3\(0), + I3 => \q_entry_r_reg[1]_4\(0), + O => \^idle_r_lcl_reg_3\ + ); +\q_entry_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[0]_i_1_n_0\, + Q => q_entry_r(0), + R => \q_entry_r_reg[1]_6\(0) + ); +\q_entry_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[1]_i_1_n_0\, + Q => q_entry_r(1), + R => \q_entry_r_reg[1]_6\(0) + ); +q_has_priority_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"1010111010101010" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_0, + I2 => q_has_priority, + I3 => q_has_priority_r_reg_1, + I4 => q_has_priority_r_reg_2, + I5 => was_priority, + O => q_has_priority_r_i_1_n_0 + ); +q_has_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => q_has_priority_r_i_1_n_0, + Q => q_has_priority, + R => '0' + ); +q_has_rd_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"1010101010111010" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_0, + I2 => q_has_rd_r_reg_0, + I3 => was_wr, + I4 => q_has_priority_r_reg_1, + I5 => q_has_priority_r_reg_2, + O => q_has_rd_r_i_1_n_0 + ); +q_has_rd_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => q_has_rd_r_i_1_n_0, + Q => q_has_rd, + R => '0' + ); +\ras_timer_r[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__2_n_0\, + I1 => q_entry_r(1), + I2 => q_entry_r(0), + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[0]_i_2__1_n_0\, + I5 => \ras_timer_r_reg[0]\, + O => \q_entry_r_reg[1]_1\(0) + ); +\ras_timer_r[0]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBB8888B888B888" + ) + port map ( + I0 => \ras_timer_r_reg[0]_0\, + I1 => rb_hit_busies_r(3), + I2 => rb_hit_busies_r(1), + I3 => \ras_timer_r_reg[0]_1\, + I4 => \ras_timer_r_reg[0]_2\, + I5 => rb_hit_busies_r(2), + O => \ras_timer_r[0]_i_2__1_n_0\ + ); +\ras_timer_r[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__2_n_0\, + I1 => q_entry_r(1), + I2 => q_entry_r(0), + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[1]_i_3__1_n_0\, + I5 => \ras_timer_r_reg[1]\, + O => \q_entry_r_reg[1]_1\(1) + ); +\ras_timer_r[1]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \ras_timer_r_reg[0]_3\, + I1 => rb_hit_busies_r(1), + I2 => rb_hit_busies_r(2), + I3 => \ras_timer_r_reg[0]_4\, + I4 => rb_hit_busies_r(3), + I5 => \ras_timer_r_reg[0]_5\, + O => \ras_timer_r[1]_i_2__2_n_0\ + ); +\ras_timer_r[1]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBB8888B888B888" + ) + port map ( + I0 => \ras_timer_r_reg[1]_0\, + I1 => rb_hit_busies_r(3), + I2 => rb_hit_busies_r(1), + I3 => \ras_timer_r_reg[1]_1\, + I4 => \ras_timer_r_reg[1]_2\, + I5 => rb_hit_busies_r(2), + O => \ras_timer_r[1]_i_3__1_n_0\ + ); +\ras_timer_r[1]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55151515" + ) + port map ( + I0 => pre_passing_open_bank_r, + I1 => bm_end_r1_reg_0(0), + I2 => \^pass_open_bank_r\, + I3 => bm_end_r1_reg, + I4 => bm_end_r1_reg_1, + O => pre_passing_open_bank_r_reg_0 + ); +\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E200" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\, + I1 => \^idle_r_lcl_reg_2\, + I2 => rb_hit_busies_r(1), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\, + O => \rb_hit_busies.rb_hit_busies_ns\(1) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E200" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\, + I1 => \^idle_r_lcl_reg_2\, + I2 => rb_hit_busies_r(2), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\, + O => \rb_hit_busies.rb_hit_busies_ns\(2) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\, + I1 => \^idle_r_lcl_reg_2\, + I2 => rb_hit_busies_r(3), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0), + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\, + O => \rb_hit_busies.rb_hit_busies_ns\(3) + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(1), + Q => rb_hit_busies_r(1), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(2), + Q => rb_hit_busies_r(2), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(3), + Q => rb_hit_busies_r(3), + R => '0' + ); +\req_bank_rdy_r_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"888A88AA" + ) + port map ( + I0 => req_bank_rdy_r_reg, + I1 => bm_end_r1_reg, + I2 => order_q_r(0), + I3 => order_q_r(1), + I4 => req_bank_rdy_r_reg_0, + O => req_bank_rdy_ns + ); +wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wait_for_maint_r_lcl_reg_2, + Q => \^wait_for_maint_r_lcl_reg_0\, + R => wait_for_maint_r_lcl_reg_1 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_queue__parameterized0\ is + port ( + idle_r_lcl_reg_0 : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + pass_open_bank_r : out STD_LOGIC; + pre_bm_end_r : out STD_LOGIC; + q_has_rd_0 : out STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : out STD_LOGIC; + head_r_lcl_reg_0 : out STD_LOGIC; + ordered_r_lcl : out STD_LOGIC; + tail_r : out STD_LOGIC; + auto_pre_r_lcl_reg_0 : out STD_LOGIC; + pre_bm_end_r_reg_0 : out STD_LOGIC; + idle_r_lcl_reg_1 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg_2 : out STD_LOGIC; + rnk_config_valid_r_lcl_reg : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + rnk_config_strobe_ns : out STD_LOGIC; + \q_entry_r_reg[1]_0\ : out STD_LOGIC; + \q_entry_r_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + demand_priority_ns : out STD_LOGIC; + \order_q_r_reg[1]_0\ : out STD_LOGIC; + req_bank_rdy_ns : out STD_LOGIC; + act_wait_ns : out STD_LOGIC; + pre_passing_open_bank_r_reg_0 : out STD_LOGIC; + act_wait_r_lcl_reg : out STD_LOGIC; + CLK : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + pre_bm_end_ns : in STD_LOGIC; + pre_passing_open_bank_ns : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_2 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ordered_r_lcl_reg_0 : in STD_LOGIC; + head_r_lcl_reg_1 : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_2\ : in STD_LOGIC; + q_has_priority_r_reg_0 : in STD_LOGIC; + \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + q_has_priority_r_reg_1 : in STD_LOGIC; + \maint_controller.maint_hit_busies_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[1]_0\ : in STD_LOGIC; + q_has_rd_r_reg_0 : in STD_LOGIC; + was_wr : in STD_LOGIC; + q_has_priority_r_reg_2 : in STD_LOGIC; + was_priority : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC; + rnk_config_valid_r : in STD_LOGIC; + act_wait_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + act_wait_r_lcl_reg_1 : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + demand_priority_r_reg : in STD_LOGIC; + req_priority_r : in STD_LOGIC; + demand_priority_r_reg_0 : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_2\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_3\ : in STD_LOGIC; + req_bank_rdy_r_reg_0 : in STD_LOGIC; + req_bank_rdy_r_reg_1 : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]_2\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC; + bm_end_r1 : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \ras_timer_r_reg[0]_5\ : in STD_LOGIC; + \q_entry_r_reg[1]_2\ : in STD_LOGIC; + \q_entry_r_reg[1]_3\ : in STD_LOGIC; + head_r_lcl_reg_2 : in STD_LOGIC; + \q_entry_r_reg[0]_3\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + auto_pre_r_lcl_reg_1 : in STD_LOGIC; + auto_pre_r_lcl_reg_2 : in STD_LOGIC; + row_hit_r : in STD_LOGIC; + auto_pre_r_lcl_reg_3 : in STD_LOGIC; + ras_timer_zero_r : in STD_LOGIC; + \q_entry_r_reg[0]_4\ : in STD_LOGIC; + \q_entry_r_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]_1\ : in STD_LOGIC; + set_order_q : in STD_LOGIC; + \order_q_r_reg[0]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_queue__parameterized0\ : entity is "mig_7series_v4_2_bank_queue"; +end \ddr3_mig_7series_v4_2_bank_queue__parameterized0\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_queue__parameterized0\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \auto_pre_r_lcl_i_1__1_n_0\ : STD_LOGIC; + signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC; + signal \^col_wait_r_reg\ : STD_LOGIC; + signal \compute_tail.tail_r_lcl_i_1__0_n_0\ : STD_LOGIC; + signal \head_r_lcl_i_1__0_n_0\ : STD_LOGIC; + signal \head_r_lcl_i_2__1_n_0\ : STD_LOGIC; + signal head_r_lcl_i_3_n_0 : STD_LOGIC; + signal \^head_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_2\ : STD_LOGIC; + signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC; + signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC; + signal \^order_q_r_reg[1]_0\ : STD_LOGIC; + signal \^pass_open_bank_r\ : STD_LOGIC; + signal \^pre_bm_end_r\ : STD_LOGIC; + signal \^pre_bm_end_r_reg_0\ : STD_LOGIC; + signal pre_passing_open_bank_r : STD_LOGIC; + signal q_entry_ns : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[0]_i_2__1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_3__2_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_4__0_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_7__0_n_0\ : STD_LOGIC; + signal \^q_entry_r_reg[1]_0\ : STD_LOGIC; + signal \q_entry_r_reg_n_0_[0]\ : STD_LOGIC; + signal \q_entry_r_reg_n_0_[1]\ : STD_LOGIC; + signal q_has_priority : STD_LOGIC; + signal \q_has_priority_r_i_1__1_n_0\ : STD_LOGIC; + signal \q_has_rd_r_i_1__1_n_0\ : STD_LOGIC; + signal \ras_timer_r[0]_i_2__0_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_2__1_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_3__0_n_0\ : STD_LOGIC; + signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 4 downto 2 ); + signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 4 downto 2 ); + signal \^tail_r\ : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \demand_priority_r_i_2__1\ : label is "soft_lutpair519"; + attribute SOFT_HLUTNM of head_r_lcl_i_3 : label is "soft_lutpair518"; + attribute SOFT_HLUTNM of \idle_r_lcl_i_1__2\ : label is "soft_lutpair516"; + attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[1]_i_1\ : label is "soft_lutpair516"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_3__2\ : label is "soft_lutpair518"; + attribute SOFT_HLUTNM of \req_bank_rdy_r_i_1__1\ : label is "soft_lutpair519"; + attribute SOFT_HLUTNM of \rnk_config_strobe_r[0]_i_1\ : label is "soft_lutpair517"; + attribute SOFT_HLUTNM of rnk_config_valid_r_lcl_i_1 : label is "soft_lutpair517"; +begin + E(0) <= \^e\(0); + auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\; + col_wait_r_reg <= \^col_wait_r_reg\; + head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\; + idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\; + idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\; + \order_q_r_reg[1]_0\ <= \^order_q_r_reg[1]_0\; + pass_open_bank_r <= \^pass_open_bank_r\; + pre_bm_end_r <= \^pre_bm_end_r\; + pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\; + \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\; + tail_r <= \^tail_r\; + wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\; +\act_wait_r_lcl_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF44F4" + ) + port map ( + I0 => \^q_entry_r_reg[1]_0\, + I1 => act_wait_r_lcl_reg_1, + I2 => \^pass_open_bank_r\, + I3 => \^pre_bm_end_r_reg_0\, + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + I5 => bm_end_r1, + O => act_wait_ns + ); +\act_wait_r_lcl_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF002000200020" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__1_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => act_wait_r_lcl_reg_0(0), + I5 => act_wait_r_lcl_reg_1, + O => \^q_entry_r_reg[1]_0\ + ); +\act_wait_r_lcl_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55151515" + ) + port map ( + I0 => \^pre_bm_end_r\, + I1 => Q(0), + I2 => \^pass_open_bank_r\, + I3 => req_bank_rdy_r_reg_0, + I4 => req_wr_r(0), + O => \^pre_bm_end_r_reg_0\ + ); +\auto_pre_r_lcl_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAEEEEE" + ) + port map ( + I0 => \^auto_pre_r_lcl_reg_0\, + I1 => auto_pre_r_lcl_reg_1, + I2 => \^wait_for_maint_r_lcl_reg_0\, + I3 => auto_pre_r_lcl_reg_2, + I4 => row_hit_r, + I5 => auto_pre_r_lcl_reg_3, + O => \auto_pre_r_lcl_i_1__1_n_0\ + ); +auto_pre_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \auto_pre_r_lcl_i_1__1_n_0\, + Q => \^auto_pre_r_lcl_reg_0\, + R => '0' + ); +\compute_tail.tail_r_lcl_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FDCCFDFCDDCCDDCC" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \compute_tail.tail_r_lcl_reg_1\, + I3 => \compute_tail.tail_r_lcl_reg_2\, + I4 => \^idle_r_lcl_reg_0\, + I5 => \^tail_r\, + O => \compute_tail.tail_r_lcl_i_1__0_n_0\ + ); +\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \compute_tail.tail_r_lcl_i_1__0_n_0\, + Q => \^tail_r\, + R => SR(0) + ); +\demand_priority_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888800008880" + ) + port map ( + I0 => demand_priority_r_reg, + I1 => \^idle_r_lcl_reg_2\, + I2 => req_priority_r, + I3 => q_has_priority, + I4 => \^order_q_r_reg[1]_0\, + I5 => demand_priority_r_reg_0, + O => demand_priority_ns + ); +\demand_priority_r_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EC" + ) + port map ( + I0 => req_bank_rdy_r_reg_1, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg_0, + O => \^order_q_r_reg[1]_0\ + ); +\grant_r[3]_i_12__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFDFFFFF" + ) + port map ( + I0 => act_wait_r_lcl_reg_1, + I1 => \^idle_r_lcl_reg_0\, + I2 => \^head_r_lcl_reg_0\, + I3 => \^wait_for_maint_r_lcl_reg_0\, + I4 => ras_timer_zero_r, + O => act_wait_r_lcl_reg + ); +\grant_r[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^order_q_r_reg[1]_0\, + I1 => req_bank_rdy_r_reg, + I2 => \rnk_config_strobe_r_reg[0]_2\, + I3 => \rnk_config_strobe_r_reg[0]_3\, + O => \^col_wait_r_reg\ + ); +\head_r_lcl_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88B8FFFF88B80000" + ) + port map ( + I0 => \head_r_lcl_i_2__1_n_0\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => head_r_lcl_reg_1, + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + I4 => \q_entry_r[1]_i_3__2_n_0\, + I5 => \^head_r_lcl_reg_0\, + O => \head_r_lcl_i_1__0_n_0\ + ); +\head_r_lcl_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FF000014141414" + ) + port map ( + I0 => head_r_lcl_reg_2, + I1 => \q_entry_r[1]_i_7__0_n_0\, + I2 => \q_entry_r_reg[0]_3\, + I3 => \q_entry_r_reg_n_0_[1]\, + I4 => \q_entry_r_reg_n_0_[0]\, + I5 => head_r_lcl_i_3_n_0, + O => \head_r_lcl_i_2__1_n_0\ + ); +head_r_lcl_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"0535" + ) + port map ( + I0 => \q_entry_r[1]_i_7__0_n_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \^idle_r_lcl_reg_0\, + I3 => q_has_priority_r_reg_0, + O => head_r_lcl_i_3_n_0 + ); +head_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \head_r_lcl_i_1__0_n_0\, + Q => \^head_r_lcl_reg_0\, + R => SR(0) + ); +\idle_r_lcl_i_1__2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^idle_r_lcl_reg_2\, + O => \^e\(0) + ); +\idle_r_lcl_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00D0" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \^pre_bm_end_r_reg_0\, + I3 => q_has_priority_r_reg_1, + O => \^idle_r_lcl_reg_2\ + ); +idle_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^e\(0), + Q => \^idle_r_lcl_reg_0\, + R => '0' + ); +\maint_controller.maint_hit_busies_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20222020" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => \maint_controller.maint_hit_busies_r_reg[1]\(0), + I3 => \maint_controller.maint_hit_busies_r_reg[1]_0\, + I4 => \^idle_r_lcl_reg_2\, + O => D(0) + ); +\order_q_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"550D000C550DF00C" + ) + port map ( + I0 => \order_q_r_reg[0]_0\, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg_1, + I4 => set_order_q, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \order_q_r[0]_i_1_n_0\ + ); +\order_q_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAC200C0AAC2CCC0" + ) + port map ( + I0 => \order_q_r_reg[1]_1\, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg_1, + I4 => set_order_q, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \order_q_r[1]_i_1_n_0\ + ); +\order_q_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[0]_i_1_n_0\, + Q => order_q_r(0), + R => '0' + ); +\order_q_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[1]_i_1_n_0\, + Q => order_q_r(1), + R => '0' + ); +ordered_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ordered_r_lcl_reg_0, + Q => ordered_r_lcl, + R => '0' + ); +pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pass_open_bank_ns, + Q => \^pass_open_bank_r\, + R => '0' + ); +pre_bm_end_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_bm_end_ns, + Q => \^pre_bm_end_r\, + R => '0' + ); +pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_passing_open_bank_ns, + Q => pre_passing_open_bank_r, + R => '0' + ); +\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B88BFFFFB88B0000" + ) + port map ( + I0 => \q_entry_r[0]_i_2__1_n_0\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => \q_entry_r_reg[0]_4\, + I3 => q_has_priority_r_reg_0, + I4 => \q_entry_r[1]_i_3__2_n_0\, + I5 => \q_entry_r_reg_n_0_[0]\, + O => \q_entry_r[0]_i_1_n_0\ + ); +\q_entry_r[0]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"909F" + ) + port map ( + I0 => \q_entry_r_reg[0]_3\, + I1 => \q_entry_r[1]_i_7__0_n_0\, + I2 => \compute_tail.tail_r_lcl_reg_0\, + I3 => \q_entry_r_reg_n_0_[0]\, + O => \q_entry_r[0]_i_2__1_n_0\ + ); +\q_entry_r[0]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9669699669969669" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \q_entry_r_reg[0]_0\(0), + I2 => \^idle_r_lcl_reg_0\, + I3 => \q_entry_r_reg[0]_1\(0), + I4 => \q_entry_r_reg[0]_2\(0), + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + O => idle_r_lcl_reg_1 + ); +\q_entry_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => q_entry_ns(1), + I1 => \q_entry_r[1]_i_3__2_n_0\, + I2 => \q_entry_r_reg_n_0_[1]\, + O => \q_entry_r[1]_i_1_n_0\ + ); +\q_entry_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8BB8BB88BB88B88B" + ) + port map ( + I0 => \q_entry_r[1]_i_4__0_n_0\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => q_has_priority_r_reg_0, + I3 => \q_entry_r_reg[1]_2\, + I4 => \q_entry_r_reg[1]_3\, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + O => q_entry_ns(1) + ); +\q_entry_r[1]_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CDFDFFFF" + ) + port map ( + I0 => \q_entry_r[1]_i_7__0_n_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \^idle_r_lcl_reg_0\, + I3 => q_has_priority_r_reg_0, + I4 => \^pre_bm_end_r_reg_0\, + O => \q_entry_r[1]_i_3__2_n_0\ + ); +\q_entry_r[1]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A9FFA900A900A9FF" + ) + port map ( + I0 => head_r_lcl_reg_2, + I1 => \q_entry_r[1]_i_7__0_n_0\, + I2 => \q_entry_r_reg[0]_3\, + I3 => \compute_tail.tail_r_lcl_reg_0\, + I4 => \q_entry_r_reg_n_0_[1]\, + I5 => \q_entry_r_reg_n_0_[0]\, + O => \q_entry_r[1]_i_4__0_n_0\ + ); +\q_entry_r[1]_i_7__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000DDD0DDD0DDD" + ) + port map ( + I0 => rb_hit_busies_r(2), + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + I2 => rb_hit_busies_r(4), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + I4 => rb_hit_busies_r(3), + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1), + O => \q_entry_r[1]_i_7__0_n_0\ + ); +\q_entry_r_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[0]_i_1_n_0\, + Q => \q_entry_r_reg_n_0_[0]\, + S => \q_entry_r_reg[1]_4\(0) + ); +\q_entry_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[1]_i_1_n_0\, + Q => \q_entry_r_reg_n_0_[1]\, + R => \q_entry_r_reg[1]_4\(0) + ); +\q_has_priority_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020222020202020" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => q_has_priority, + I3 => q_has_priority_r_reg_2, + I4 => q_has_priority_r_reg_0, + I5 => was_priority, + O => \q_has_priority_r_i_1__1_n_0\ + ); +q_has_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_has_priority_r_i_1__1_n_0\, + Q => q_has_priority, + R => '0' + ); +\q_has_rd_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020202020222020" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => q_has_rd_r_reg_0, + I3 => was_wr, + I4 => q_has_priority_r_reg_2, + I5 => q_has_priority_r_reg_0, + O => \q_has_rd_r_i_1__1_n_0\ + ); +q_has_rd_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_has_rd_r_i_1__1_n_0\, + Q => q_has_rd_0, + R => '0' + ); +\ras_timer_r[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__1_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[0]_i_2__0_n_0\, + I5 => \ras_timer_r_reg[0]\, + O => \q_entry_r_reg[1]_1\(0) + ); +\ras_timer_r[0]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8BBB888B888B888" + ) + port map ( + I0 => \ras_timer_r_reg[0]_0\, + I1 => rb_hit_busies_r(4), + I2 => \ras_timer_r_reg[0]_1\, + I3 => rb_hit_busies_r(3), + I4 => rb_hit_busies_r(2), + I5 => \ras_timer_r_reg[0]_2\, + O => \ras_timer_r[0]_i_2__0_n_0\ + ); +\ras_timer_r[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__1_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[1]_i_3__0_n_0\, + I5 => \ras_timer_r_reg[1]\, + O => \q_entry_r_reg[1]_1\(1) + ); +\ras_timer_r[1]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \ras_timer_r_reg[0]_3\, + I1 => rb_hit_busies_r(2), + I2 => rb_hit_busies_r(4), + I3 => \ras_timer_r_reg[0]_4\, + I4 => rb_hit_busies_r(3), + I5 => \ras_timer_r_reg[0]_5\, + O => \ras_timer_r[1]_i_2__1_n_0\ + ); +\ras_timer_r[1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBB8888B888B888" + ) + port map ( + I0 => \ras_timer_r_reg[1]_0\, + I1 => rb_hit_busies_r(4), + I2 => rb_hit_busies_r(2), + I3 => \ras_timer_r_reg[1]_1\, + I4 => \ras_timer_r_reg[1]_2\, + I5 => rb_hit_busies_r(3), + O => \ras_timer_r[1]_i_3__0_n_0\ + ); +\ras_timer_r[1]_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55151515" + ) + port map ( + I0 => pre_passing_open_bank_r, + I1 => Q(0), + I2 => \^pass_open_bank_r\, + I3 => req_bank_rdy_r_reg_0, + I4 => req_wr_r(0), + O => pre_passing_open_bank_r_reg_0 + ); +\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E200" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\, + I1 => \^idle_r_lcl_reg_2\, + I2 => rb_hit_busies_r(2), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + I4 => q_has_priority_r_reg_1, + O => \rb_hit_busies.rb_hit_busies_ns\(2) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\, + I1 => \^idle_r_lcl_reg_2\, + I2 => rb_hit_busies_r(3), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1), + I4 => q_has_priority_r_reg_1, + O => \rb_hit_busies.rb_hit_busies_ns\(3) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\, + I1 => \^idle_r_lcl_reg_2\, + I2 => rb_hit_busies_r(4), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \rb_hit_busies.rb_hit_busies_ns\(4) + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(2), + Q => rb_hit_busies_r(2), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(3), + Q => rb_hit_busies_r(3), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(4), + Q => rb_hit_busies_r(4), + R => '0' + ); +\req_bank_rdy_r_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"888A88AA" + ) + port map ( + I0 => req_bank_rdy_r_reg, + I1 => req_bank_rdy_r_reg_0, + I2 => order_q_r(0), + I3 => order_q_r(1), + I4 => req_bank_rdy_r_reg_1, + O => req_bank_rdy_ns + ); +\rnk_config_strobe_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFB" + ) + port map ( + I0 => \^col_wait_r_reg\, + I1 => \rnk_config_strobe_r_reg[0]\, + I2 => \rnk_config_strobe_r_reg[0]_0\, + I3 => \rnk_config_strobe_r_reg[0]_1\, + O => rnk_config_strobe_ns + ); +rnk_config_valid_r_lcl_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFB" + ) + port map ( + I0 => \^col_wait_r_reg\, + I1 => \rnk_config_strobe_r_reg[0]\, + I2 => \rnk_config_strobe_r_reg[0]_0\, + I3 => \rnk_config_strobe_r_reg[0]_1\, + I4 => rnk_config_valid_r, + O => rnk_config_valid_r_lcl_reg + ); +wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wait_for_maint_r_lcl_reg_2, + Q => \^wait_for_maint_r_lcl_reg_0\, + R => wait_for_maint_r_lcl_reg_1 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_queue__parameterized1\ is + port ( + idle_r_lcl_reg_0 : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + pass_open_bank_r : out STD_LOGIC; + pre_bm_end_r : out STD_LOGIC; + q_has_rd_1 : out STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : out STD_LOGIC; + head_r_lcl_reg_0 : out STD_LOGIC; + ordered_r_lcl_reg_0 : out STD_LOGIC; + tail_r : out STD_LOGIC; + auto_pre_r_lcl_reg_0 : out STD_LOGIC; + pre_bm_end_r_reg_0 : out STD_LOGIC; + pre_bm_end_r_reg_1 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg_1 : out STD_LOGIC; + \q_entry_r_reg[1]_0\ : out STD_LOGIC; + \q_entry_r_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + demand_priority_ns : out STD_LOGIC; + \order_q_r_reg[1]_0\ : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + req_bank_rdy_ns : out STD_LOGIC; + act_wait_ns : out STD_LOGIC; + \maint_controller.maint_rdy\ : out STD_LOGIC; + pre_passing_open_bank_r_reg_0 : out STD_LOGIC; + act_wait_r_lcl_reg : out STD_LOGIC; + CLK : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + pre_bm_end_ns : in STD_LOGIC; + pre_passing_open_bank_ns : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_2 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ordered_r_lcl_reg_1 : in STD_LOGIC; + head_r_lcl_reg_1 : in STD_LOGIC; + head_r_lcl_reg_2 : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_2\ : in STD_LOGIC; + q_has_priority_r_reg_0 : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + q_has_priority_r_reg_1 : in STD_LOGIC; + \maint_controller.maint_hit_busies_r_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[2]_0\ : in STD_LOGIC; + q_has_rd_r_reg_0 : in STD_LOGIC; + was_wr : in STD_LOGIC; + q_has_priority_r_reg_2 : in STD_LOGIC; + was_priority : in STD_LOGIC; + act_wait_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + act_wait_r_lcl_reg_1 : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + demand_priority_r_reg : in STD_LOGIC; + req_priority_r : in STD_LOGIC; + demand_priority_r_reg_0 : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + col_wait_r : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC; + req_bank_rdy_r_reg_0 : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]_2\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC; + bm_end_r1 : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \ras_timer_r_reg[0]_5\ : in STD_LOGIC; + \q_entry_r_reg[1]_2\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC; + \q_entry_r_reg[1]_3\ : in STD_LOGIC; + head_r_lcl_reg_3 : in STD_LOGIC; + \q_entry_r_reg[0]_0\ : in STD_LOGIC; + \maint_controller.maint_rdy_r1_reg\ : in STD_LOGIC; + \maint_controller.maint_rdy_r1_reg_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + q_has_priority_r_reg_3 : in STD_LOGIC; + auto_pre_r_lcl_reg_1 : in STD_LOGIC; + auto_pre_r_lcl_reg_2 : in STD_LOGIC; + row_hit_r : in STD_LOGIC; + auto_pre_r_lcl_reg_3 : in STD_LOGIC; + ras_timer_zero_r : in STD_LOGIC; + \q_entry_r_reg[1]_4\ : in STD_LOGIC; + \q_entry_r_reg[0]_1\ : in STD_LOGIC; + \q_entry_r_reg[1]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]_1\ : in STD_LOGIC; + \order_q_r_reg[0]_0\ : in STD_LOGIC; + \order_q_r_reg[0]_1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_queue__parameterized1\ : entity is "mig_7series_v4_2_bank_queue"; +end \ddr3_mig_7series_v4_2_bank_queue__parameterized1\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_queue__parameterized1\ is + signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \auto_pre_r_lcl_i_1__0_n_0\ : STD_LOGIC; + signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC; + signal \compute_tail.tail_r_lcl_i_1__1_n_0\ : STD_LOGIC; + signal \head_r_lcl_i_1__1_n_0\ : STD_LOGIC; + signal \head_r_lcl_i_2__0_n_0\ : STD_LOGIC; + signal \head_r_lcl_i_4__0_n_0\ : STD_LOGIC; + signal \^head_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_1\ : STD_LOGIC; + signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC; + signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC; + signal \^order_q_r_reg[1]_0\ : STD_LOGIC; + signal \^pass_open_bank_r\ : STD_LOGIC; + signal \^pre_bm_end_r\ : STD_LOGIC; + signal \^pre_bm_end_r_reg_0\ : STD_LOGIC; + signal pre_passing_open_bank_r : STD_LOGIC; + signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[0]_i_2__0_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_3__1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_4__2_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_5_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_6_n_0\ : STD_LOGIC; + signal \^q_entry_r_reg[1]_0\ : STD_LOGIC; + signal \q_entry_r_reg_n_0_[0]\ : STD_LOGIC; + signal \q_entry_r_reg_n_0_[1]\ : STD_LOGIC; + signal q_has_priority : STD_LOGIC; + signal \q_has_priority_r_i_1__0_n_0\ : STD_LOGIC; + signal \q_has_rd_r_i_1__0_n_0\ : STD_LOGIC; + signal \ras_timer_r[0]_i_2__2_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_2__0_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_3__2_n_0\ : STD_LOGIC; + signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 5 downto 3 ); + signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 5 downto 3 ); + signal \^tail_r\ : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \demand_priority_r_i_2__0\ : label is "soft_lutpair526"; + attribute SOFT_HLUTNM of \head_r_lcl_i_4__0\ : label is "soft_lutpair525"; + attribute SOFT_HLUTNM of \idle_r_lcl_i_1__1\ : label is "soft_lutpair524"; + attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[2]_i_1\ : label is "soft_lutpair524"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_4__2\ : label is "soft_lutpair525"; + attribute SOFT_HLUTNM of \req_bank_rdy_r_i_1__0\ : label is "soft_lutpair526"; +begin + D(0) <= \^d\(0); + E(0) <= \^e\(0); + auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\; + head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\; + idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\; + idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\; + \order_q_r_reg[1]_0\ <= \^order_q_r_reg[1]_0\; + pass_open_bank_r <= \^pass_open_bank_r\; + pre_bm_end_r <= \^pre_bm_end_r\; + pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\; + \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\; + tail_r <= \^tail_r\; + wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\; +\act_wait_r_lcl_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF44F4" + ) + port map ( + I0 => \^q_entry_r_reg[1]_0\, + I1 => act_wait_r_lcl_reg_1, + I2 => \^pass_open_bank_r\, + I3 => \^pre_bm_end_r_reg_0\, + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + I5 => bm_end_r1, + O => act_wait_ns + ); +\act_wait_r_lcl_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF002000200020" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__0_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => act_wait_r_lcl_reg_0(0), + I5 => act_wait_r_lcl_reg_1, + O => \^q_entry_r_reg[1]_0\ + ); +act_wait_r_lcl_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"55151515" + ) + port map ( + I0 => \^pre_bm_end_r\, + I1 => Q(0), + I2 => \^pass_open_bank_r\, + I3 => req_bank_rdy_r_reg, + I4 => q_has_priority_r_reg_3, + O => \^pre_bm_end_r_reg_0\ + ); +\auto_pre_r_lcl_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAEEEEE" + ) + port map ( + I0 => \^auto_pre_r_lcl_reg_0\, + I1 => auto_pre_r_lcl_reg_1, + I2 => \^wait_for_maint_r_lcl_reg_0\, + I3 => auto_pre_r_lcl_reg_2, + I4 => row_hit_r, + I5 => auto_pre_r_lcl_reg_3, + O => \auto_pre_r_lcl_i_1__0_n_0\ + ); +auto_pre_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \auto_pre_r_lcl_i_1__0_n_0\, + Q => \^auto_pre_r_lcl_reg_0\, + R => '0' + ); +\compute_tail.tail_r_lcl_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCFFDCDCDCDCDCDC" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \compute_tail.tail_r_lcl_reg_1\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \compute_tail.tail_r_lcl_reg_2\, + I5 => \^tail_r\, + O => \compute_tail.tail_r_lcl_i_1__1_n_0\ + ); +\compute_tail.tail_r_lcl_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1), + I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + O => pre_bm_end_r_reg_1 + ); +\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \compute_tail.tail_r_lcl_i_1__1_n_0\, + Q => \^tail_r\, + R => SR(0) + ); +\demand_priority_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888800008880" + ) + port map ( + I0 => demand_priority_r_reg, + I1 => \^idle_r_lcl_reg_1\, + I2 => req_priority_r, + I3 => q_has_priority, + I4 => \^order_q_r_reg[1]_0\, + I5 => demand_priority_r_reg_0, + O => demand_priority_ns + ); +\demand_priority_r_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00EC" + ) + port map ( + I0 => req_bank_rdy_r_reg_0, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg, + O => \^order_q_r_reg[1]_0\ + ); +\grant_r[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FDFF" + ) + port map ( + I0 => \rnk_config_strobe_r_reg[0]\, + I1 => \rnk_config_strobe_r_reg[0]_0\, + I2 => \^order_q_r_reg[1]_0\, + I3 => col_wait_r, + O => col_wait_r_reg + ); +\grant_r[3]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFDFFFFF" + ) + port map ( + I0 => act_wait_r_lcl_reg_1, + I1 => \^idle_r_lcl_reg_0\, + I2 => \^head_r_lcl_reg_0\, + I3 => \^wait_for_maint_r_lcl_reg_0\, + I4 => ras_timer_zero_r, + O => act_wait_r_lcl_reg + ); +\head_r_lcl_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B888FFFFB8880000" + ) + port map ( + I0 => \head_r_lcl_i_2__0_n_0\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => head_r_lcl_reg_1, + I3 => head_r_lcl_reg_2, + I4 => \q_entry_r[1]_i_4__2_n_0\, + I5 => \^head_r_lcl_reg_0\, + O => \head_r_lcl_i_1__1_n_0\ + ); +\head_r_lcl_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FF000014141414" + ) + port map ( + I0 => head_r_lcl_reg_3, + I1 => \q_entry_r[1]_i_6_n_0\, + I2 => \q_entry_r_reg[0]_0\, + I3 => \q_entry_r_reg_n_0_[1]\, + I4 => \q_entry_r_reg_n_0_[0]\, + I5 => \head_r_lcl_i_4__0_n_0\, + O => \head_r_lcl_i_2__0_n_0\ + ); +\head_r_lcl_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0535" + ) + port map ( + I0 => \q_entry_r[1]_i_6_n_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \^idle_r_lcl_reg_0\, + I3 => q_has_priority_r_reg_0, + O => \head_r_lcl_i_4__0_n_0\ + ); +head_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \head_r_lcl_i_1__1_n_0\, + Q => \^head_r_lcl_reg_0\, + R => SR(0) + ); +\idle_r_lcl_i_1__1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^idle_r_lcl_reg_1\, + O => \^e\(0) + ); +\idle_r_lcl_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00D0" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \^pre_bm_end_r_reg_0\, + I3 => q_has_priority_r_reg_1, + O => \^idle_r_lcl_reg_1\ + ); +idle_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^e\(0), + Q => \^idle_r_lcl_reg_0\, + R => '0' + ); +\maint_controller.maint_hit_busies_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20222020" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => \maint_controller.maint_hit_busies_r_reg[2]\(0), + I3 => \maint_controller.maint_hit_busies_r_reg[2]_0\, + I4 => \^idle_r_lcl_reg_1\, + O => \^d\(0) + ); +\maint_controller.maint_rdy_r1_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \^d\(0), + I1 => \maint_controller.maint_rdy_r1_reg\, + I2 => \maint_controller.maint_rdy_r1_reg_0\(0), + I3 => \maint_controller.maint_rdy_r1_reg_0\(2), + I4 => \maint_controller.maint_rdy_r1_reg_0\(1), + O => \maint_controller.maint_rdy\ + ); +\order_q_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"550D000C550DF00C" + ) + port map ( + I0 => \order_q_r_reg[0]_1\, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg_0, + I4 => \order_q_r_reg[0]_0\, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \order_q_r[0]_i_1_n_0\ + ); +\order_q_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAC200C0AAC2CCC0" + ) + port map ( + I0 => \order_q_r_reg[1]_1\, + I1 => order_q_r(1), + I2 => order_q_r(0), + I3 => req_bank_rdy_r_reg_0, + I4 => \order_q_r_reg[0]_0\, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \order_q_r[1]_i_1_n_0\ + ); +\order_q_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[0]_i_1_n_0\, + Q => order_q_r(0), + R => '0' + ); +\order_q_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[1]_i_1_n_0\, + Q => order_q_r(1), + R => '0' + ); +ordered_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ordered_r_lcl_reg_1, + Q => ordered_r_lcl_reg_0, + R => '0' + ); +pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pass_open_bank_ns, + Q => \^pass_open_bank_r\, + R => '0' + ); +pre_bm_end_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_bm_end_ns, + Q => \^pre_bm_end_r\, + R => '0' + ); +pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_passing_open_bank_ns, + Q => pre_passing_open_bank_r, + R => '0' + ); +\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B88BFFFFB88B0000" + ) + port map ( + I0 => \q_entry_r[0]_i_2__0_n_0\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => q_has_priority_r_reg_0, + I3 => \q_entry_r_reg[0]_1\, + I4 => \q_entry_r[1]_i_4__2_n_0\, + I5 => \q_entry_r_reg_n_0_[0]\, + O => \q_entry_r[0]_i_1_n_0\ + ); +\q_entry_r[0]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"909F" + ) + port map ( + I0 => \q_entry_r_reg[0]_0\, + I1 => \q_entry_r[1]_i_6_n_0\, + I2 => \compute_tail.tail_r_lcl_reg_0\, + I3 => \q_entry_r_reg_n_0_[0]\, + O => \q_entry_r[0]_i_2__0_n_0\ + ); +\q_entry_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FE02FFFFFE020000" + ) + port map ( + I0 => \q_entry_r_reg[1]_4\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => q_has_priority_r_reg_0, + I3 => \q_entry_r[1]_i_3__1_n_0\, + I4 => \q_entry_r[1]_i_4__2_n_0\, + I5 => \q_entry_r_reg_n_0_[1]\, + O => \q_entry_r[1]_i_1_n_0\ + ); +\q_entry_r[1]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8B8BB88BB88BB8B8" + ) + port map ( + I0 => \q_entry_r[1]_i_5_n_0\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => \q_entry_r_reg[1]_2\, + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + I4 => \q_entry_r_reg[1]_3\, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + O => \q_entry_r[1]_i_3__1_n_0\ + ); +\q_entry_r[1]_i_4__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CDFDFFFF" + ) + port map ( + I0 => \q_entry_r[1]_i_6_n_0\, + I1 => \compute_tail.tail_r_lcl_reg_0\, + I2 => \^idle_r_lcl_reg_0\, + I3 => q_has_priority_r_reg_0, + I4 => \^pre_bm_end_r_reg_0\, + O => \q_entry_r[1]_i_4__2_n_0\ + ); +\q_entry_r[1]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A9FFA900A900A9FF" + ) + port map ( + I0 => head_r_lcl_reg_3, + I1 => \q_entry_r[1]_i_6_n_0\, + I2 => \q_entry_r_reg[0]_0\, + I3 => \compute_tail.tail_r_lcl_reg_0\, + I4 => \q_entry_r_reg_n_0_[1]\, + I5 => \q_entry_r_reg_n_0_[0]\, + O => \q_entry_r[1]_i_5_n_0\ + ); +\q_entry_r[1]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000770777077707" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1), + I1 => rb_hit_busies_r(3), + I2 => rb_hit_busies_r(5), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + I4 => rb_hit_busies_r(4), + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + O => \q_entry_r[1]_i_6_n_0\ + ); +\q_entry_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[0]_i_1_n_0\, + Q => \q_entry_r_reg_n_0_[0]\, + R => \q_entry_r_reg[1]_5\(0) + ); +\q_entry_r_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[1]_i_1_n_0\, + Q => \q_entry_r_reg_n_0_[1]\, + S => \q_entry_r_reg[1]_5\(0) + ); +\q_has_priority_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020222020202020" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => q_has_priority, + I3 => q_has_priority_r_reg_2, + I4 => q_has_priority_r_reg_0, + I5 => was_priority, + O => \q_has_priority_r_i_1__0_n_0\ + ); +q_has_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_has_priority_r_i_1__0_n_0\, + Q => q_has_priority, + R => '0' + ); +\q_has_rd_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020202020222020" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => q_has_rd_r_reg_0, + I3 => was_wr, + I4 => q_has_priority_r_reg_2, + I5 => q_has_priority_r_reg_0, + O => \q_has_rd_r_i_1__0_n_0\ + ); +q_has_rd_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_has_rd_r_i_1__0_n_0\, + Q => q_has_rd_1, + R => '0' + ); +\ras_timer_r[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__0_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[0]_i_2__2_n_0\, + I5 => \ras_timer_r_reg[0]\, + O => \q_entry_r_reg[1]_1\(0) + ); +\ras_timer_r[0]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8BBB888B888B888" + ) + port map ( + I0 => \ras_timer_r_reg[0]_0\, + I1 => rb_hit_busies_r(5), + I2 => \ras_timer_r_reg[0]_1\, + I3 => rb_hit_busies_r(4), + I4 => rb_hit_busies_r(3), + I5 => \ras_timer_r_reg[0]_2\, + O => \ras_timer_r[0]_i_2__2_n_0\ + ); +\ras_timer_r[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2__0_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[1]_i_3__2_n_0\, + I5 => \ras_timer_r_reg[1]\, + O => \q_entry_r_reg[1]_1\(1) + ); +\ras_timer_r[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \ras_timer_r_reg[0]_3\, + I1 => rb_hit_busies_r(5), + I2 => rb_hit_busies_r(4), + I3 => \ras_timer_r_reg[0]_4\, + I4 => rb_hit_busies_r(3), + I5 => \ras_timer_r_reg[0]_5\, + O => \ras_timer_r[1]_i_2__0_n_0\ + ); +\ras_timer_r[1]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBB8888B888B888" + ) + port map ( + I0 => \ras_timer_r_reg[1]_0\, + I1 => rb_hit_busies_r(5), + I2 => rb_hit_busies_r(3), + I3 => \ras_timer_r_reg[1]_1\, + I4 => \ras_timer_r_reg[1]_2\, + I5 => rb_hit_busies_r(4), + O => \ras_timer_r[1]_i_3__2_n_0\ + ); +\ras_timer_r[1]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55151515" + ) + port map ( + I0 => pre_passing_open_bank_r, + I1 => Q(0), + I2 => \^pass_open_bank_r\, + I3 => req_bank_rdy_r_reg, + I4 => q_has_priority_r_reg_3, + O => pre_passing_open_bank_r_reg_0 + ); +\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\, + I1 => \^idle_r_lcl_reg_1\, + I2 => rb_hit_busies_r(3), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1), + I4 => q_has_priority_r_reg_1, + O => \rb_hit_busies.rb_hit_busies_ns\(3) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\, + I1 => \^idle_r_lcl_reg_1\, + I2 => rb_hit_busies_r(4), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \rb_hit_busies.rb_hit_busies_ns\(4) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E200" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\, + I1 => \^idle_r_lcl_reg_1\, + I2 => rb_hit_busies_r(5), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + I4 => q_has_priority_r_reg_1, + O => \rb_hit_busies.rb_hit_busies_ns\(5) + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(3), + Q => rb_hit_busies_r(3), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(4), + Q => rb_hit_busies_r(4), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(5), + Q => rb_hit_busies_r(5), + R => '0' + ); +\req_bank_rdy_r_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"888A88AA" + ) + port map ( + I0 => col_wait_r, + I1 => req_bank_rdy_r_reg, + I2 => order_q_r(0), + I3 => order_q_r(1), + I4 => req_bank_rdy_r_reg_0, + O => req_bank_rdy_ns + ); +wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wait_for_maint_r_lcl_reg_2, + Q => \^wait_for_maint_r_lcl_reg_0\, + R => wait_for_maint_r_lcl_reg_1 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_queue__parameterized2\ is + port ( + idle_r_lcl_reg_0 : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + pass_open_bank_r : out STD_LOGIC; + pre_bm_end_r : out STD_LOGIC; + q_has_rd_2 : out STD_LOGIC; + q_has_priority : out STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : out STD_LOGIC; + head_r_lcl_reg_0 : out STD_LOGIC; + ordered_r_lcl_reg_0 : out STD_LOGIC; + tail_r : out STD_LOGIC; + auto_pre_r_lcl_reg_0 : out STD_LOGIC; + pre_bm_end_r_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg_1 : out STD_LOGIC; + pre_bm_end_r_reg_1 : out STD_LOGIC; + \q_entry_r_reg[1]_0\ : out STD_LOGIC; + \q_entry_r_reg[1]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + col_wait_r_reg : out STD_LOGIC; + act_wait_ns : out STD_LOGIC; + pre_passing_open_bank_r_reg_0 : out STD_LOGIC; + act_wait_r_lcl_reg : out STD_LOGIC; + idle_r_lcl_reg_2 : out STD_LOGIC; + order_q_r : out STD_LOGIC_VECTOR ( 1 downto 0 ); + CLK : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + pre_bm_end_ns : in STD_LOGIC; + pre_passing_open_bank_ns : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_2 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ordered_r_lcl_reg_1 : in STD_LOGIC; + head_r_lcl_reg_1 : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_2\ : in STD_LOGIC; + rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 ); + q_has_priority_r_reg_0 : in STD_LOGIC; + q_has_priority_r_reg_1 : in STD_LOGIC; + \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[3]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC; + q_has_rd_r_reg_0 : in STD_LOGIC; + was_wr : in STD_LOGIC; + q_has_priority_r_reg_2 : in STD_LOGIC; + was_priority : in STD_LOGIC; + act_wait_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + act_wait_r_lcl_reg_1 : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + \grant_r_reg[1]\ : in STD_LOGIC; + \grant_r_reg[1]_0\ : in STD_LOGIC; + bm_end_r1_reg : in STD_LOGIC; + \grant_r_reg[1]_1\ : in STD_LOGIC; + \grant_r_reg[1]_2\ : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]_2\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ : in STD_LOGIC; + bm_end_r1 : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \ras_timer_r_reg[0]_5\ : in STD_LOGIC; + \q_entry_r_reg[1]_2\ : in STD_LOGIC; + head_r_lcl_reg_2 : in STD_LOGIC; + head_r_lcl_reg_3 : in STD_LOGIC; + bm_end : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + auto_pre_r_lcl_reg_1 : in STD_LOGIC; + auto_pre_r_lcl_reg_2 : in STD_LOGIC; + row_hit_r : in STD_LOGIC; + auto_pre_r_lcl_reg_3 : in STD_LOGIC; + ras_timer_zero_r : in STD_LOGIC; + \q_entry_r[1]_i_2__0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r[1]_i_2__0_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r[1]_i_2__0_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[1]_3\ : in STD_LOGIC; + \q_entry_r_reg[0]_0\ : in STD_LOGIC; + \q_entry_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]_0\ : in STD_LOGIC; + \order_q_r_reg[0]_0\ : in STD_LOGIC; + set_order_q : in STD_LOGIC; + \order_q_r_reg[0]_1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_queue__parameterized2\ : entity is "mig_7series_v4_2_bank_queue"; +end \ddr3_mig_7series_v4_2_bank_queue__parameterized2\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_queue__parameterized2\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \auto_pre_r_lcl_i_1__2_n_0\ : STD_LOGIC; + signal \^auto_pre_r_lcl_reg_0\ : STD_LOGIC; + signal \compute_tail.tail_r_lcl_i_1__2_n_0\ : STD_LOGIC; + signal \head_r_lcl_i_1__2_n_0\ : STD_LOGIC; + signal head_r_lcl_i_2_n_0 : STD_LOGIC; + signal head_r_lcl_i_4_n_0 : STD_LOGIC; + signal \^head_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_1\ : STD_LOGIC; + signal \^order_q_r\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \order_q_r[0]_i_1_n_0\ : STD_LOGIC; + signal \order_q_r[1]_i_1_n_0\ : STD_LOGIC; + signal \^pass_open_bank_r\ : STD_LOGIC; + signal \^pre_bm_end_r\ : STD_LOGIC; + signal \^pre_bm_end_r_reg_0\ : STD_LOGIC; + signal pre_passing_open_bank_r : STD_LOGIC; + signal \q_entry_r[0]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[0]_i_2_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_3__0_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_4_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_6__1_n_0\ : STD_LOGIC; + signal \q_entry_r[1]_i_7_n_0\ : STD_LOGIC; + signal \^q_entry_r_reg[1]_0\ : STD_LOGIC; + signal \q_entry_r_reg_n_0_[0]\ : STD_LOGIC; + signal \q_entry_r_reg_n_0_[1]\ : STD_LOGIC; + signal \^q_has_priority\ : STD_LOGIC; + signal \q_has_priority_r_i_1__2_n_0\ : STD_LOGIC; + signal \q_has_rd_r_i_1__2_n_0\ : STD_LOGIC; + signal \ras_timer_r[0]_i_2_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_2_n_0\ : STD_LOGIC; + signal \ras_timer_r[1]_i_3_n_0\ : STD_LOGIC; + signal \rb_hit_busies.rb_hit_busies_ns\ : STD_LOGIC_VECTOR ( 6 downto 4 ); + signal rb_hit_busies_r : STD_LOGIC_VECTOR ( 6 downto 4 ); + signal \^tail_r\ : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of head_r_lcl_i_4 : label is "soft_lutpair533"; + attribute SOFT_HLUTNM of \idle_r_lcl_i_1__0\ : label is "soft_lutpair532"; + attribute SOFT_HLUTNM of \maint_controller.maint_hit_busies_r[3]_i_1\ : label is "soft_lutpair532"; + attribute SOFT_HLUTNM of \q_entry_r[1]_i_4\ : label is "soft_lutpair533"; +begin + E(0) <= \^e\(0); + auto_pre_r_lcl_reg_0 <= \^auto_pre_r_lcl_reg_0\; + head_r_lcl_reg_0 <= \^head_r_lcl_reg_0\; + idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\; + idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\; + order_q_r(1 downto 0) <= \^order_q_r\(1 downto 0); + pass_open_bank_r <= \^pass_open_bank_r\; + pre_bm_end_r <= \^pre_bm_end_r\; + pre_bm_end_r_reg_0 <= \^pre_bm_end_r_reg_0\; + \q_entry_r_reg[1]_0\ <= \^q_entry_r_reg[1]_0\; + q_has_priority <= \^q_has_priority\; + tail_r <= \^tail_r\; + wait_for_maint_r_lcl_reg_0 <= \^wait_for_maint_r_lcl_reg_0\; +act_wait_r_lcl_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFF444" + ) + port map ( + I0 => \^q_entry_r_reg[1]_0\, + I1 => act_wait_r_lcl_reg_1, + I2 => \^pass_open_bank_r\, + I3 => \^pre_bm_end_r_reg_0\, + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + I5 => bm_end_r1, + O => act_wait_ns + ); +act_wait_r_lcl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF002000200020" + ) + port map ( + I0 => \ras_timer_r[1]_i_2_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => act_wait_r_lcl_reg_0(0), + I5 => act_wait_r_lcl_reg_1, + O => \^q_entry_r_reg[1]_0\ + ); +\auto_pre_r_lcl_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAEEEEE" + ) + port map ( + I0 => \^auto_pre_r_lcl_reg_0\, + I1 => auto_pre_r_lcl_reg_1, + I2 => \^wait_for_maint_r_lcl_reg_0\, + I3 => auto_pre_r_lcl_reg_2, + I4 => row_hit_r, + I5 => auto_pre_r_lcl_reg_3, + O => \auto_pre_r_lcl_i_1__2_n_0\ + ); +auto_pre_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \auto_pre_r_lcl_i_1__2_n_0\, + Q => \^auto_pre_r_lcl_reg_0\, + R => '0' + ); +\bm_end_r1_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAEAEAEA" + ) + port map ( + I0 => \^pre_bm_end_r\, + I1 => Q(0), + I2 => \^pass_open_bank_r\, + I3 => bm_end_r1_reg, + I4 => req_wr_r(0), + O => \^pre_bm_end_r_reg_0\ + ); +\compute_tail.tail_r_lcl_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCFFECECECECECEC" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \compute_tail.tail_r_lcl_reg_1\, + I2 => \compute_tail.tail_r_lcl_reg_0\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \compute_tail.tail_r_lcl_reg_2\, + I5 => \^tail_r\, + O => \compute_tail.tail_r_lcl_i_1__2_n_0\ + ); +\compute_tail.tail_r_lcl_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\, + I2 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + O => pre_bm_end_r_reg_1 + ); +\compute_tail.tail_r_lcl_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \compute_tail.tail_r_lcl_i_1__2_n_0\, + Q => \^tail_r\, + R => SR(0) + ); +\grant_r[3]_i_15\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFDFFFFF" + ) + port map ( + I0 => act_wait_r_lcl_reg_1, + I1 => \^idle_r_lcl_reg_0\, + I2 => \^head_r_lcl_reg_0\, + I3 => \^wait_for_maint_r_lcl_reg_0\, + I4 => ras_timer_zero_r, + O => act_wait_r_lcl_reg + ); +\grant_r[3]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000E000EEE" + ) + port map ( + I0 => \^q_entry_r_reg[1]_0\, + I1 => \grant_r_reg[1]\, + I2 => \grant_r_reg[1]_0\, + I3 => bm_end_r1_reg, + I4 => \grant_r_reg[1]_1\, + I5 => \grant_r_reg[1]_2\, + O => col_wait_r_reg + ); +\head_r_lcl_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C055FFFFC0550000" + ) + port map ( + I0 => head_r_lcl_i_2_n_0, + I1 => head_r_lcl_reg_1, + I2 => \compute_tail.tail_r_lcl_reg_0\, + I3 => \^pre_bm_end_r_reg_0\, + I4 => \q_entry_r[1]_i_4_n_0\, + I5 => \^head_r_lcl_reg_0\, + O => \head_r_lcl_i_1__2_n_0\ + ); +head_r_lcl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFBFBFB0BFB0BFBF" + ) + port map ( + I0 => \q_entry_r_reg_n_0_[1]\, + I1 => \q_entry_r_reg_n_0_[0]\, + I2 => head_r_lcl_i_4_n_0, + I3 => head_r_lcl_reg_3, + I4 => \q_entry_r[1]_i_7_n_0\, + I5 => head_r_lcl_reg_2, + O => head_r_lcl_i_2_n_0 + ); +head_r_lcl_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"0535" + ) + port map ( + I0 => \q_entry_r[1]_i_7_n_0\, + I1 => \compute_tail.tail_r_lcl_reg_1\, + I2 => \^idle_r_lcl_reg_0\, + I3 => q_has_priority_r_reg_2, + O => head_r_lcl_i_4_n_0 + ); +head_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \head_r_lcl_i_1__2_n_0\, + Q => \^head_r_lcl_reg_0\, + R => SR(0) + ); +\idle_r_lcl_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^idle_r_lcl_reg_1\, + O => \^e\(0) + ); +\idle_r_lcl_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"000D" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \compute_tail.tail_r_lcl_reg_1\, + I2 => \^pre_bm_end_r_reg_0\, + I3 => q_has_priority_r_reg_1, + O => \^idle_r_lcl_reg_1\ + ); +idle_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^e\(0), + Q => \^idle_r_lcl_reg_0\, + R => '0' + ); +\maint_controller.maint_hit_busies_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10111010" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => \maint_controller.maint_hit_busies_r_reg[3]\(0), + I3 => \maint_controller.maint_hit_busies_r_reg[3]_0\, + I4 => \^idle_r_lcl_reg_1\, + O => D(0) + ); +\order_q_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"550D000C550DF00C" + ) + port map ( + I0 => \order_q_r_reg[0]_1\, + I1 => \^order_q_r\(1), + I2 => \^order_q_r\(0), + I3 => \order_q_r_reg[0]_0\, + I4 => set_order_q, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \order_q_r[0]_i_1_n_0\ + ); +\order_q_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAC200C0AAC2CCC0" + ) + port map ( + I0 => \order_q_r_reg[1]_0\, + I1 => \^order_q_r\(1), + I2 => \^order_q_r\(0), + I3 => \order_q_r_reg[0]_0\, + I4 => set_order_q, + I5 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \order_q_r[1]_i_1_n_0\ + ); +\order_q_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[0]_i_1_n_0\, + Q => \^order_q_r\(0), + R => '0' + ); +\order_q_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \order_q_r[1]_i_1_n_0\, + Q => \^order_q_r\(1), + R => '0' + ); +ordered_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ordered_r_lcl_reg_1, + Q => ordered_r_lcl_reg_0, + R => '0' + ); +pass_open_bank_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pass_open_bank_ns, + Q => \^pass_open_bank_r\, + R => '0' + ); +pre_bm_end_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_bm_end_ns, + Q => \^pre_bm_end_r\, + R => '0' + ); +pre_passing_open_bank_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_passing_open_bank_ns, + Q => pre_passing_open_bank_r, + R => '0' + ); +\q_entry_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F2D8FFFFF2D80000" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_2, + I2 => \q_entry_r[0]_i_2_n_0\, + I3 => \q_entry_r_reg[0]_0\, + I4 => \q_entry_r[1]_i_4_n_0\, + I5 => \q_entry_r_reg_n_0_[0]\, + O => \q_entry_r[0]_i_1_n_0\ + ); +\q_entry_r[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000990F" + ) + port map ( + I0 => head_r_lcl_reg_2, + I1 => \q_entry_r[1]_i_7_n_0\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \compute_tail.tail_r_lcl_reg_1\, + I4 => \^pre_bm_end_r_reg_0\, + O => \q_entry_r[0]_i_2_n_0\ + ); +\q_entry_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FB08FFFFFB080000" + ) + port map ( + I0 => \q_entry_r_reg[1]_3\, + I1 => \^pre_bm_end_r_reg_0\, + I2 => q_has_priority_r_reg_2, + I3 => \q_entry_r[1]_i_3__0_n_0\, + I4 => \q_entry_r[1]_i_4_n_0\, + I5 => \q_entry_r_reg_n_0_[1]\, + O => \q_entry_r[1]_i_1_n_0\ + ); +\q_entry_r[1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"555555553F30303F" + ) + port map ( + I0 => \q_entry_r_reg[1]_2\, + I1 => \q_entry_r[1]_i_6__1_n_0\, + I2 => \compute_tail.tail_r_lcl_reg_1\, + I3 => \q_entry_r_reg_n_0_[1]\, + I4 => \q_entry_r_reg_n_0_[0]\, + I5 => \^pre_bm_end_r_reg_0\, + O => \q_entry_r[1]_i_3__0_n_0\ + ); +\q_entry_r[1]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FAFBFFFB" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => \q_entry_r[1]_i_7_n_0\, + I2 => \compute_tail.tail_r_lcl_reg_1\, + I3 => \^idle_r_lcl_reg_0\, + I4 => q_has_priority_r_reg_2, + O => \q_entry_r[1]_i_4_n_0\ + ); +\q_entry_r[1]_i_5__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7EE8" + ) + port map ( + I0 => \^idle_r_lcl_reg_0\, + I1 => \q_entry_r[1]_i_2__0\(0), + I2 => \q_entry_r[1]_i_2__0_0\(0), + I3 => \q_entry_r[1]_i_2__0_1\(0), + O => idle_r_lcl_reg_2 + ); +\q_entry_r[1]_i_6__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8117177E" + ) + port map ( + I0 => \q_entry_r[1]_i_7_n_0\, + I1 => rb_hit_busy_r(0), + I2 => rb_hit_busy_r(1), + I3 => rb_hit_busy_r(2), + I4 => q_has_priority_r_reg_0, + O => \q_entry_r[1]_i_6__1_n_0\ + ); +\q_entry_r[1]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000DD0DDD0DDD0D" + ) + port map ( + I0 => rb_hit_busies_r(5), + I1 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + I2 => rb_hit_busies_r(6), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\, + I4 => rb_hit_busies_r(4), + I5 => bm_end(0), + O => \q_entry_r[1]_i_7_n_0\ + ); +\q_entry_r_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[0]_i_1_n_0\, + Q => \q_entry_r_reg_n_0_[0]\, + S => \q_entry_r_reg[0]_1\(0) + ); +\q_entry_r_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \q_entry_r[1]_i_1_n_0\, + Q => \q_entry_r_reg_n_0_[1]\, + S => \q_entry_r_reg[0]_1\(0) + ); +\q_has_priority_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1010111010101010" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => \^q_has_priority\, + I3 => q_has_priority_r_reg_0, + I4 => q_has_priority_r_reg_2, + I5 => was_priority, + O => \q_has_priority_r_i_1__2_n_0\ + ); +q_has_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_has_priority_r_i_1__2_n_0\, + Q => \^q_has_priority\, + R => '0' + ); +\q_has_rd_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1010101010111010" + ) + port map ( + I0 => \^pre_bm_end_r_reg_0\, + I1 => q_has_priority_r_reg_1, + I2 => q_has_rd_r_reg_0, + I3 => was_wr, + I4 => q_has_priority_r_reg_0, + I5 => q_has_priority_r_reg_2, + O => \q_has_rd_r_i_1__2_n_0\ + ); +q_has_rd_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \q_has_rd_r_i_1__2_n_0\, + Q => q_has_rd_2, + R => '0' + ); +\ras_timer_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[0]_i_2_n_0\, + I5 => \ras_timer_r_reg[0]\, + O => \q_entry_r_reg[1]_1\(0) + ); +\ras_timer_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8BBB888B888B888" + ) + port map ( + I0 => \ras_timer_r_reg[0]_0\, + I1 => rb_hit_busies_r(6), + I2 => \ras_timer_r_reg[0]_1\, + I3 => rb_hit_busies_r(5), + I4 => rb_hit_busies_r(4), + I5 => \ras_timer_r_reg[0]_2\, + O => \ras_timer_r[0]_i_2_n_0\ + ); +\ras_timer_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDF00200000" + ) + port map ( + I0 => \ras_timer_r[1]_i_2_n_0\, + I1 => \q_entry_r_reg_n_0_[1]\, + I2 => \q_entry_r_reg_n_0_[0]\, + I3 => \^idle_r_lcl_reg_0\, + I4 => \ras_timer_r[1]_i_3_n_0\, + I5 => \ras_timer_r_reg[1]\, + O => \q_entry_r_reg[1]_1\(1) + ); +\ras_timer_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F444F4FFFF44F4" + ) + port map ( + I0 => \ras_timer_r_reg[0]_3\, + I1 => rb_hit_busies_r(4), + I2 => rb_hit_busies_r(6), + I3 => \ras_timer_r_reg[0]_4\, + I4 => rb_hit_busies_r(5), + I5 => \ras_timer_r_reg[0]_5\, + O => \ras_timer_r[1]_i_2_n_0\ + ); +\ras_timer_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBB8888888B888" + ) + port map ( + I0 => \ras_timer_r_reg[1]_0\, + I1 => rb_hit_busies_r(6), + I2 => rb_hit_busies_r(4), + I3 => \ras_timer_r_reg[1]_1\, + I4 => rb_hit_busies_r(5), + I5 => \ras_timer_r_reg[1]_2\, + O => \ras_timer_r[1]_i_3_n_0\ + ); +\ras_timer_r[1]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55151515" + ) + port map ( + I0 => pre_passing_open_bank_r, + I1 => Q(0), + I2 => \^pass_open_bank_r\, + I3 => bm_end_r1_reg, + I4 => req_wr_r(0), + O => pre_passing_open_bank_r_reg_0 + ); +\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000E2" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\, + I1 => \^idle_r_lcl_reg_1\, + I2 => rb_hit_busies_r(4), + I3 => bm_end(0), + I4 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\, + O => \rb_hit_busies.rb_hit_busies_ns\(4) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E200" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\, + I1 => \^idle_r_lcl_reg_1\, + I2 => rb_hit_busies_r(5), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + I4 => q_has_priority_r_reg_1, + O => \rb_hit_busies.rb_hit_busies_ns\(5) + ); +\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E200" + ) + port map ( + I0 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\, + I1 => \^idle_r_lcl_reg_1\, + I2 => rb_hit_busies_r(6), + I3 => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\, + I4 => q_has_priority_r_reg_1, + O => \rb_hit_busies.rb_hit_busies_ns\(6) + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(4), + Q => rb_hit_busies_r(4), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(5), + Q => rb_hit_busies_r(5), + R => '0' + ); +\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \rb_hit_busies.rb_hit_busies_ns\(6), + Q => rb_hit_busies_r(6), + R => '0' + ); +wait_for_maint_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wait_for_maint_r_lcl_reg_2, + Q => \^wait_for_maint_r_lcl_reg_0\, + R => wait_for_maint_r_lcl_reg_1 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_state is + port ( + bm_end_r1 : out STD_LOGIC; + act_wait_r_lcl_reg_0 : out STD_LOGIC; + ras_timer_zero_r : out STD_LOGIC; + pre_wait_r : out STD_LOGIC; + col_wait_r_reg_0 : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC; + demand_act_priority_r : out STD_LOGIC; + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + demand_priority_r_reg_0 : out STD_LOGIC; + demanded_prior_r_reg_0 : out STD_LOGIC; + ofs_rdy_r : out STD_LOGIC; + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + override_demand_r_reg : out STD_LOGIC; + pre_bm_end_ns : out STD_LOGIC; + pre_passing_open_bank_ns : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + bm_end_r1_reg_1 : out STD_LOGIC; + act_wait_r_lcl_reg_1 : out STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + demand_priority_r_reg_1 : out STD_LOGIC; + demand_priority_r_reg_2 : out STD_LOGIC; + ofs_rdy_r0 : out STD_LOGIC; + ofs_rdy_r0_0 : out STD_LOGIC; + ofs_rdy_r0_1 : out STD_LOGIC; + bm_end : in STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + act_wait_ns : in STD_LOGIC; + req_bank_rdy_ns : in STD_LOGIC; + demand_priority_ns : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_mc_ctl_full : in STD_LOGIC; + phy_mc_cmd_full : in STD_LOGIC; + start_wtp_timer0 : in STD_LOGIC; + \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC; + col_wait_r_reg_1 : in STD_LOGIC; + demanded_prior_r_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + col_wait_r_reg_2 : in STD_LOGIC; + override_demand_r : in STD_LOGIC; + demanded_prior_r_reg_2 : in STD_LOGIC; + demand_priority_r_2 : in STD_LOGIC; + pass_open_bank_r : in STD_LOGIC; + pre_wait_r_reg_0 : in STD_LOGIC; + pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + pre_bm_end_r_reg_0 : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + demand_act_priority_r_reg_0 : in STD_LOGIC; + head_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + ras_timer_zero_r_reg_0 : in STD_LOGIC; + tail_r : in STD_LOGIC; + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + rb_hit_busy_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r[3]_i_3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \starve_limit_cntr_r_reg[0]_0\ : in STD_LOGIC; + q_has_rd : in STD_LOGIC; + req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + demanded_prior_r_3 : in STD_LOGIC; + phy_mc_data_full : in STD_LOGIC; + ofs_rdy_r_reg_0 : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rtp_timer_r_reg[0]_0\ : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_state : entity is "mig_7series_v4_2_bank_state"; +end ddr3_mig_7series_v4_2_bank_state; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_state is + signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC; + signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC; + signal \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\ : STD_LOGIC; + signal \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\ : STD_LOGIC; + signal \^bm_end_r1\ : STD_LOGIC; + signal \^bm_end_r1_reg_0\ : STD_LOGIC; + signal \^bm_end_r1_reg_1\ : STD_LOGIC; + signal \^col_wait_r_reg_0\ : STD_LOGIC; + signal demand_act_priority_ns : STD_LOGIC; + signal \^demand_act_priority_r\ : STD_LOGIC; + signal demand_priority_r_i_4_n_0 : STD_LOGIC; + signal \^demand_priority_r_reg_0\ : STD_LOGIC; + signal demanded_prior_ns : STD_LOGIC; + signal \^demanded_prior_r_reg_0\ : STD_LOGIC; + signal ofs_rdy_r0_2 : STD_LOGIC; + signal \^pre_passing_open_bank_ns\ : STD_LOGIC; + signal pre_wait_ns : STD_LOGIC; + signal \^pre_wait_r\ : STD_LOGIC; + signal pre_wait_r_i_2_n_0 : STD_LOGIC; + signal ras_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ras_timer_zero_ns : STD_LOGIC; + signal \^ras_timer_zero_r\ : STD_LOGIC; + signal req_bank_rdy_r : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__13\ : STD_LOGIC; + signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \rtp_timer_r[0]_i_1_n_0\ : STD_LOGIC; + signal \rtp_timer_r[1]_i_1_n_0\ : STD_LOGIC; + signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal starve_limit_cntr_r0 : STD_LOGIC; + signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \grant_r[2]_i_3__2\ : label is "soft_lutpair510"; + attribute SOFT_HLUTNM of ofs_rdy_r_i_1 : label is "soft_lutpair512"; + attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__0\ : label is "soft_lutpair512"; + attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__1\ : label is "soft_lutpair513"; + attribute SOFT_HLUTNM of \ofs_rdy_r_i_1__2\ : label is "soft_lutpair513"; + attribute SOFT_HLUTNM of pre_bm_end_r_i_1 : label is "soft_lutpair510"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair511"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair511"; +begin + act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\; + act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\; + bm_end_r1 <= \^bm_end_r1\; + bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\; + bm_end_r1_reg_1 <= \^bm_end_r1_reg_1\; + col_wait_r_reg_0 <= \^col_wait_r_reg_0\; + demand_act_priority_r <= \^demand_act_priority_r\; + demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\; + demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\; + pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\; + pre_wait_r <= \^pre_wait_r\; + ras_timer_zero_r <= \^ras_timer_zero_r\; + \rstdiv0_sync_r1_reg_rep__13\ <= \^rstdiv0_sync_r1_reg_rep__13\; +\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^act_wait_r_lcl_reg_0\, + Q => act_this_rank_r(0), + R => '0' + ); +act_wait_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => act_wait_ns, + Q => \^act_wait_r_lcl_reg_0\, + R => '0' + ); +\auto_pre_r_lcl_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020202000002000" + ) + port map ( + I0 => tail_r, + I1 => auto_pre_r_lcl_reg_0, + I2 => rb_hit_busy_r(0), + I3 => \^col_wait_r_reg_0\, + I4 => demanded_prior_r_reg_1(0), + I5 => \^act_wait_r_lcl_reg_0\, + O => \compute_tail.tail_r_lcl_reg\ + ); +bm_end_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bm_end(0), + Q => \^bm_end_r1\, + R => '0' + ); +\col_wait_r_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => col_wait_r_reg_1, + I1 => \^col_wait_r_reg_0\, + I2 => demanded_prior_r_reg_1(0), + I3 => col_wait_r_reg_2, + O => \^rstdiv0_sync_r1_reg_rep__13\ + ); +col_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^rstdiv0_sync_r1_reg_rep__13\, + Q => \^col_wait_r_reg_0\, + R => '0' + ); +demand_act_priority_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080000000000" + ) + port map ( + I0 => \^demand_act_priority_r\, + I1 => \^ras_timer_zero_r\, + I2 => demand_act_priority_r_reg_0, + I3 => head_r(0), + I4 => E(0), + I5 => \^act_wait_r_lcl_reg_0\, + O => demand_act_priority_ns + ); +demand_act_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_act_priority_ns, + Q => \^demand_act_priority_r\, + R => '0' + ); +demand_priority_r_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"BAAAAAAA" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => demand_priority_r_i_4_n_0, + I2 => starve_limit_cntr_r(2), + I3 => starve_limit_cntr_r(1), + I4 => starve_limit_cntr_r(0), + O => demand_priority_r_reg_1 + ); +demand_priority_r_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"DFFFDFDF" + ) + port map ( + I0 => \starve_limit_cntr_r_reg[0]_0\, + I1 => demanded_prior_r_reg_1(0), + I2 => req_bank_rdy_r, + I3 => q_has_rd, + I4 => req_wr_r(0), + O => demand_priority_r_i_4_n_0 + ); +demand_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_priority_ns, + Q => \^demand_priority_r_reg_0\, + R => '0' + ); +demanded_prior_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000D00DDDDDDDD" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => \^demanded_prior_r_reg_0\, + I2 => demanded_prior_r_reg_1(1), + I3 => demand_priority_r_2, + I4 => demanded_prior_r_3, + I5 => demanded_prior_r_reg_2, + O => demanded_prior_ns + ); +demanded_prior_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demanded_prior_ns, + Q => \^demanded_prior_r_reg_0\, + R => '0' + ); +\grant_r[2]_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => pre_bm_end_r_reg_0, + I1 => pre_bm_end_r_reg(0), + I2 => \^pre_wait_r\, + I3 => \^ras_timer_zero_r\, + O => auto_pre_r_lcl_reg + ); +\grant_r[3]_i_11__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^act_wait_r_lcl_reg_0\, + I1 => \grant_r[3]_i_3__1\(0), + O => \^act_wait_r_lcl_reg_1\ + ); +\grant_r[3]_i_18\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000011111511" + ) + port map ( + I0 => override_demand_r, + I1 => demanded_prior_r_reg_2, + I2 => \^demanded_prior_r_reg_0\, + I3 => \^demand_priority_r_reg_0\, + I4 => demanded_prior_r_reg_1(0), + I5 => demand_priority_r_2, + O => override_demand_r_reg + ); +\grant_r[3]_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEFAAAA" + ) + port map ( + I0 => demand_priority_r_2, + I1 => demanded_prior_r_reg_1(0), + I2 => \^demand_priority_r_reg_0\, + I3 => \^demanded_prior_r_reg_0\, + I4 => demanded_prior_r_reg_2, + O => demand_priority_r_reg_2 + ); +ofs_rdy_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"1011" + ) + port map ( + I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\, + I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\, + I2 => \rd_this_rank_r_reg[0]_0\, + I3 => phy_mc_data_full, + O => ofs_rdy_r0_2 + ); +\ofs_rdy_r_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1011" + ) + port map ( + I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\, + I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\, + I2 => ofs_rdy_r_reg_0(2), + I3 => phy_mc_data_full, + O => ofs_rdy_r0 + ); +\ofs_rdy_r_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1011" + ) + port map ( + I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\, + I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\, + I2 => ofs_rdy_r_reg_0(1), + I3 => phy_mc_data_full, + O => ofs_rdy_r0_0 + ); +\ofs_rdy_r_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1011" + ) + port map ( + I0 => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\, + I1 => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\, + I2 => ofs_rdy_r_reg_0(0), + I3 => phy_mc_data_full, + O => ofs_rdy_r0_1 + ); +ofs_rdy_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => ofs_rdy_r0_2, + Q => ofs_rdy_r, + R => SR(0) + ); +phy_mc_cmd_full_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => phy_mc_cmd_full, + Q => \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r\, + R => SR(0) + ); +phy_mc_ctl_full_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => phy_mc_ctl_full, + Q => \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r\, + R => SR(0) + ); +pre_bm_end_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAEAEAAA" + ) + port map ( + I0 => \^pre_passing_open_bank_ns\, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => pre_bm_end_r_reg(0), + I4 => pre_bm_end_r_reg_0, + O => pre_bm_end_ns + ); +pre_passing_open_bank_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAA8AAAAAAA8AAA8" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => demanded_prior_r_reg_1(0), + I2 => rtp_timer_r(0), + I3 => rtp_timer_r(1), + I4 => \^ras_timer_zero_r\, + I5 => \^pre_wait_r\, + O => \^pre_passing_open_bank_ns\ + ); +pre_wait_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444444454444" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => pre_wait_r_i_2_n_0, + I2 => pass_open_bank_r, + I3 => pre_wait_r_reg_0, + I4 => rtp_timer_r(0), + I5 => rtp_timer_r(1), + O => pre_wait_ns + ); +pre_wait_r_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"10101050" + ) + port map ( + I0 => col_wait_r_reg_1, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => pre_bm_end_r_reg(0), + I4 => pre_bm_end_r_reg_0, + O => pre_wait_r_i_2_n_0 + ); +pre_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_wait_ns, + Q => \^pre_wait_r\, + R => '0' + ); +\ras_timer_r[0]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000111011111111" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => col_wait_r_reg_1, + I2 => \^act_wait_r_lcl_reg_1\, + I3 => ras_timer_r(1), + I4 => ras_timer_r(0), + I5 => ras_timer_zero_r_reg_0, + O => \^bm_end_r1_reg_0\ + ); +\ras_timer_r[1]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000111110001000" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => col_wait_r_reg_1, + I2 => ras_timer_r(1), + I3 => ras_timer_r(0), + I4 => \rd_this_rank_r_reg[0]_0\, + I5 => demanded_prior_r_reg_1(0), + O => \^bm_end_r1_reg_1\ + ); +\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(0), + Q => ras_timer_r(0), + R => '0' + ); +\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(1), + Q => ras_timer_r(1), + R => '0' + ); +\ras_timer_zero_r_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^bm_end_r1_reg_0\, + I1 => \^bm_end_r1_reg_1\, + O => ras_timer_zero_ns + ); +ras_timer_zero_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ras_timer_zero_ns, + Q => \^ras_timer_zero_r\, + R => '0' + ); +\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_this_rank_r_reg[0]_0\, + Q => rd_this_rank_r(0), + R => '0' + ); +req_bank_rdy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => req_bank_rdy_ns, + Q => req_bank_rdy_r, + R => '0' + ); +\rtp_timer_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \rtp_timer_r_reg[0]_0\, + I1 => pass_open_bank_r, + I2 => rtp_timer_r(1), + I3 => rtp_timer_r(0), + O => \rtp_timer_r[0]_i_1_n_0\ + ); +\rtp_timer_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000C2" + ) + port map ( + I0 => demanded_prior_r_reg_1(0), + I1 => rtp_timer_r(0), + I2 => rtp_timer_r(1), + I3 => pass_open_bank_r, + I4 => pre_wait_r_reg_0, + O => \rtp_timer_r[1]_i_1_n_0\ + ); +\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[0]_i_1_n_0\, + Q => rtp_timer_r(0), + R => '0' + ); +\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[1]_i_1_n_0\, + Q => rtp_timer_r(1), + R => '0' + ); +\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r0, + I2 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[0]_i_1_n_0\ + ); +\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6A00" + ) + port map ( + I0 => starve_limit_cntr_r(1), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[1]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAA0000" + ) + port map ( + I0 => starve_limit_cntr_r(2), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => starve_limit_cntr_r(1), + I4 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[2]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00007F0000000000" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r(1), + I2 => starve_limit_cntr_r(2), + I3 => \starve_limit_cntr_r_reg[0]_0\, + I4 => demanded_prior_r_reg_1(0), + I5 => req_bank_rdy_r, + O => starve_limit_cntr_r0 + ); +\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[0]_i_1_n_0\, + Q => starve_limit_cntr_r(0), + R => '0' + ); +\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[1]_i_1_n_0\, + Q => starve_limit_cntr_r(1), + R => '0' + ); +\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[2]_i_1_n_0\, + Q => starve_limit_cntr_r(2), + R => '0' + ); +\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => start_wtp_timer0, + Q => wr_this_rank_r(0), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_state__parameterized0\ is + port ( + act_wait_r_lcl_reg_0 : out STD_LOGIC; + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + bm_end_r1 : out STD_LOGIC; + ras_timer_zero_r : out STD_LOGIC; + pre_wait_r : out STD_LOGIC; + col_wait_r_reg_0 : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__12\ : out STD_LOGIC; + demand_act_priority_r : out STD_LOGIC; + demand_priority_r_reg_0 : out STD_LOGIC; + demanded_prior_r_reg_0 : out STD_LOGIC; + ofs_rdy_r : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + bm_end_r1_reg_1 : out STD_LOGIC; + act_wait_r_lcl_reg_1 : out STD_LOGIC; + pre_bm_end_ns : out STD_LOGIC; + pre_passing_open_bank_ns : out STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + demand_priority_r_reg_1 : out STD_LOGIC; + demanded_prior_r_reg_1 : out STD_LOGIC; + demand_priority_r_reg_2 : out STD_LOGIC; + act_wait_ns : in STD_LOGIC; + CLK : in STD_LOGIC; + start_wtp_timer0 : in STD_LOGIC; + \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC; + bm_end : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_bank_rdy_ns : in STD_LOGIC; + demand_priority_ns : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ofs_rdy_r0 : in STD_LOGIC; + col_wait_r_reg_1 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + col_wait_r_reg_2 : in STD_LOGIC; + pass_open_bank_r : in STD_LOGIC; + pre_wait_r_reg_0 : in STD_LOGIC; + ras_timer_zero_r_reg_0 : in STD_LOGIC; + pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + pre_bm_end_r_reg_0 : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + tail_r : in STD_LOGIC; + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + auto_pre_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + demand_act_priority_r_reg_0 : in STD_LOGIC; + head_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r[2]_i_3__1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + demand_priority_r_0 : in STD_LOGIC; + demanded_prior_r_reg_2 : in STD_LOGIC; + demanded_prior_r_1 : in STD_LOGIC; + \starve_limit_cntr_r_reg[0]_0\ : in STD_LOGIC; + q_has_rd_0 : in STD_LOGIC; + req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rtp_timer_r_reg[0]_0\ : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_state__parameterized0\ : entity is "mig_7series_v4_2_bank_state"; +end \ddr3_mig_7series_v4_2_bank_state__parameterized0\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_state__parameterized0\ is + signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC; + signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC; + signal \^bm_end_r1\ : STD_LOGIC; + signal \^bm_end_r1_reg_0\ : STD_LOGIC; + signal \^bm_end_r1_reg_1\ : STD_LOGIC; + signal \^col_wait_r_reg_0\ : STD_LOGIC; + signal demand_act_priority_ns : STD_LOGIC; + signal \^demand_act_priority_r\ : STD_LOGIC; + signal \demand_priority_r_i_4__0_n_0\ : STD_LOGIC; + signal \^demand_priority_r_reg_0\ : STD_LOGIC; + signal demanded_prior_ns : STD_LOGIC; + signal \^demanded_prior_r_reg_0\ : STD_LOGIC; + signal \^pre_passing_open_bank_ns\ : STD_LOGIC; + signal pre_wait_ns : STD_LOGIC; + signal \^pre_wait_r\ : STD_LOGIC; + signal \pre_wait_r_i_2__0_n_0\ : STD_LOGIC; + signal \ras_timer_r_reg_n_0_[0]\ : STD_LOGIC; + signal \ras_timer_r_reg_n_0_[1]\ : STD_LOGIC; + signal \^ras_timer_zero_r\ : STD_LOGIC; + signal \ras_timer_zero_r_i_1__2_n_0\ : STD_LOGIC; + signal req_bank_rdy_r : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__12\ : STD_LOGIC; + signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \rtp_timer_r[0]_i_1__0_n_0\ : STD_LOGIC; + signal \rtp_timer_r[1]_i_1__0_n_0\ : STD_LOGIC; + signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal starve_limit_cntr_r0 : STD_LOGIC; + signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \grant_r[3]_i_4__2\ : label is "soft_lutpair520"; + attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__1\ : label is "soft_lutpair520"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair521"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair521"; +begin + act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\; + act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\; + bm_end_r1 <= \^bm_end_r1\; + bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\; + bm_end_r1_reg_1 <= \^bm_end_r1_reg_1\; + col_wait_r_reg_0 <= \^col_wait_r_reg_0\; + demand_act_priority_r <= \^demand_act_priority_r\; + demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\; + demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\; + pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\; + pre_wait_r <= \^pre_wait_r\; + ras_timer_zero_r <= \^ras_timer_zero_r\; + \rstdiv0_sync_r1_reg_rep__12\ <= \^rstdiv0_sync_r1_reg_rep__12\; +\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^act_wait_r_lcl_reg_0\, + Q => act_this_rank_r(0), + R => '0' + ); +act_wait_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => act_wait_ns, + Q => \^act_wait_r_lcl_reg_0\, + R => '0' + ); +auto_pre_r_lcl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020202000002000" + ) + port map ( + I0 => tail_r, + I1 => auto_pre_r_lcl_reg_0, + I2 => auto_pre_r_lcl_reg_1(0), + I3 => \^col_wait_r_reg_0\, + I4 => Q(0), + I5 => \^act_wait_r_lcl_reg_0\, + O => \compute_tail.tail_r_lcl_reg\ + ); +bm_end_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bm_end(0), + Q => \^bm_end_r1\, + R => '0' + ); +\col_wait_r_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => col_wait_r_reg_1, + I1 => \^col_wait_r_reg_0\, + I2 => Q(0), + I3 => col_wait_r_reg_2, + O => \^rstdiv0_sync_r1_reg_rep__12\ + ); +col_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^rstdiv0_sync_r1_reg_rep__12\, + Q => \^col_wait_r_reg_0\, + R => '0' + ); +\demand_act_priority_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080000000000" + ) + port map ( + I0 => \^demand_act_priority_r\, + I1 => \^ras_timer_zero_r\, + I2 => demand_act_priority_r_reg_0, + I3 => head_r(0), + I4 => E(0), + I5 => \^act_wait_r_lcl_reg_0\, + O => demand_act_priority_ns + ); +demand_act_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_act_priority_ns, + Q => \^demand_act_priority_r\, + R => '0' + ); +\demand_priority_r_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BAAAAAAA" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => \demand_priority_r_i_4__0_n_0\, + I2 => starve_limit_cntr_r(2), + I3 => starve_limit_cntr_r(1), + I4 => starve_limit_cntr_r(0), + O => demand_priority_r_reg_2 + ); +\demand_priority_r_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DFFFDFDF" + ) + port map ( + I0 => \starve_limit_cntr_r_reg[0]_0\, + I1 => Q(0), + I2 => req_bank_rdy_r, + I3 => q_has_rd_0, + I4 => req_wr_r(0), + O => \demand_priority_r_i_4__0_n_0\ + ); +demand_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_priority_ns, + Q => \^demand_priority_r_reg_0\, + R => '0' + ); +\demanded_prior_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D0D0D0D0D0DDD0D0" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => \^demanded_prior_r_reg_0\, + I2 => demanded_prior_r_reg_2, + I3 => Q(1), + I4 => demand_priority_r_0, + I5 => demanded_prior_r_1, + O => demanded_prior_ns + ); +\demanded_prior_r_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFBFBFBFB00FBFB" + ) + port map ( + I0 => \^demanded_prior_r_reg_0\, + I1 => \^demand_priority_r_reg_0\, + I2 => Q(0), + I3 => demanded_prior_r_1, + I4 => demand_priority_r_0, + I5 => Q(1), + O => demanded_prior_r_reg_1 + ); +demanded_prior_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demanded_prior_ns, + Q => \^demanded_prior_r_reg_0\, + R => '0' + ); +\grant_r[2]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^act_wait_r_lcl_reg_0\, + I1 => \grant_r[2]_i_3__1\(0), + O => \^act_wait_r_lcl_reg_1\ + ); +\grant_r[3]_i_4__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => pre_bm_end_r_reg_0, + I1 => pre_bm_end_r_reg(0), + I2 => \^pre_wait_r\, + I3 => \^ras_timer_zero_r\, + O => auto_pre_r_lcl_reg + ); +\grant_r[3]_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBBBBABB" + ) + port map ( + I0 => demand_priority_r_0, + I1 => demanded_prior_r_reg_2, + I2 => Q(0), + I3 => \^demand_priority_r_reg_0\, + I4 => \^demanded_prior_r_reg_0\, + O => demand_priority_r_reg_1 + ); +ofs_rdy_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => ofs_rdy_r0, + Q => ofs_rdy_r, + R => SR(0) + ); +\pre_bm_end_r_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAEAEAAA" + ) + port map ( + I0 => \^pre_passing_open_bank_ns\, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => pre_bm_end_r_reg(0), + I4 => pre_bm_end_r_reg_0, + O => pre_bm_end_ns + ); +\pre_passing_open_bank_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAA8AAAAAAA8AAA8" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => Q(0), + I2 => rtp_timer_r(0), + I3 => rtp_timer_r(1), + I4 => \^ras_timer_zero_r\, + I5 => \^pre_wait_r\, + O => \^pre_passing_open_bank_ns\ + ); +\pre_wait_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444444454444" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => \pre_wait_r_i_2__0_n_0\, + I2 => pass_open_bank_r, + I3 => pre_wait_r_reg_0, + I4 => rtp_timer_r(0), + I5 => rtp_timer_r(1), + O => pre_wait_ns + ); +\pre_wait_r_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10101050" + ) + port map ( + I0 => pre_wait_r_reg_0, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => pre_bm_end_r_reg(0), + I4 => pre_bm_end_r_reg_0, + O => \pre_wait_r_i_2__0_n_0\ + ); +pre_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_wait_ns, + Q => \^pre_wait_r\, + R => '0' + ); +\ras_timer_r[0]_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000111011111111" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => pre_wait_r_reg_0, + I2 => \^act_wait_r_lcl_reg_1\, + I3 => \ras_timer_r_reg_n_0_[1]\, + I4 => \ras_timer_r_reg_n_0_[0]\, + I5 => ras_timer_zero_r_reg_0, + O => \^bm_end_r1_reg_0\ + ); +\ras_timer_r[1]_i_4__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000111110001000" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => pre_wait_r_reg_0, + I2 => \ras_timer_r_reg_n_0_[1]\, + I3 => \ras_timer_r_reg_n_0_[0]\, + I4 => \rd_this_rank_r_reg[0]_0\, + I5 => Q(0), + O => \^bm_end_r1_reg_1\ + ); +\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(0), + Q => \ras_timer_r_reg_n_0_[0]\, + R => '0' + ); +\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(1), + Q => \ras_timer_r_reg_n_0_[1]\, + R => '0' + ); +\ras_timer_zero_r_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^bm_end_r1_reg_0\, + I1 => \^bm_end_r1_reg_1\, + O => \ras_timer_zero_r_i_1__2_n_0\ + ); +ras_timer_zero_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ras_timer_zero_r_i_1__2_n_0\, + Q => \^ras_timer_zero_r\, + R => '0' + ); +\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_this_rank_r_reg[0]_0\, + Q => rd_this_rank_r(0), + R => '0' + ); +req_bank_rdy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => req_bank_rdy_ns, + Q => req_bank_rdy_r, + R => '0' + ); +\rtp_timer_r[0]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \rtp_timer_r_reg[0]_0\, + I1 => pass_open_bank_r, + I2 => rtp_timer_r(1), + I3 => rtp_timer_r(0), + O => \rtp_timer_r[0]_i_1__0_n_0\ + ); +\rtp_timer_r[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000C2" + ) + port map ( + I0 => Q(0), + I1 => rtp_timer_r(0), + I2 => rtp_timer_r(1), + I3 => pass_open_bank_r, + I4 => col_wait_r_reg_1, + O => \rtp_timer_r[1]_i_1__0_n_0\ + ); +\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[0]_i_1__0_n_0\, + Q => rtp_timer_r(0), + R => '0' + ); +\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[1]_i_1__0_n_0\, + Q => rtp_timer_r(1), + R => '0' + ); +\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r0, + I2 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[0]_i_1_n_0\ + ); +\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6A00" + ) + port map ( + I0 => starve_limit_cntr_r(1), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[1]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAA0000" + ) + port map ( + I0 => starve_limit_cntr_r(2), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => starve_limit_cntr_r(1), + I4 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[2]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00007F0000000000" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r(1), + I2 => starve_limit_cntr_r(2), + I3 => \starve_limit_cntr_r_reg[0]_0\, + I4 => Q(0), + I5 => req_bank_rdy_r, + O => starve_limit_cntr_r0 + ); +\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[0]_i_1_n_0\, + Q => starve_limit_cntr_r(0), + R => '0' + ); +\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[1]_i_1_n_0\, + Q => starve_limit_cntr_r(1), + R => '0' + ); +\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[2]_i_1_n_0\, + Q => starve_limit_cntr_r(2), + R => '0' + ); +\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => start_wtp_timer0, + Q => wr_this_rank_r(0), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_state__parameterized1\ is + port ( + act_wait_r_lcl_reg_0 : out STD_LOGIC; + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + bm_end_r1 : out STD_LOGIC; + ras_timer_zero_r : out STD_LOGIC; + pre_wait_r : out STD_LOGIC; + col_wait_r : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__12\ : out STD_LOGIC; + demand_act_priority_r : out STD_LOGIC; + demand_priority_r_reg_0 : out STD_LOGIC; + demanded_prior_r_reg_0 : out STD_LOGIC; + override_demand_r : out STD_LOGIC; + override_demand_r_reg_0 : out STD_LOGIC; + col_wait_r_reg_0 : out STD_LOGIC; + rd_wr_r_lcl_reg : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + bm_end_r1_reg_1 : out STD_LOGIC; + act_wait_r_lcl_reg_1 : out STD_LOGIC; + pre_bm_end_ns : out STD_LOGIC; + pre_passing_open_bank_ns : out STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC; + ras_timer_zero_r_reg_0 : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + demand_priority_r_reg_1 : out STD_LOGIC; + demand_priority_r_reg_2 : out STD_LOGIC; + act_wait_r_lcl_reg_2 : out STD_LOGIC; + act_wait_ns : in STD_LOGIC; + CLK : in STD_LOGIC; + start_wtp_timer0 : in STD_LOGIC; + \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC; + bm_end : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_bank_rdy_ns : in STD_LOGIC; + demand_priority_ns : in STD_LOGIC; + override_demand_ns : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ofs_rdy_r0 : in STD_LOGIC; + col_wait_r_reg_1 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + col_wait_r_reg_2 : in STD_LOGIC; + demanded_prior_r_0 : in STD_LOGIC; + demand_priority_r_1 : in STD_LOGIC; + demanded_prior_r_reg_1 : in STD_LOGIC; + pass_open_bank_r : in STD_LOGIC; + \grant_r_reg[1]\ : in STD_LOGIC; + \grant_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + granted_col_r_reg : in STD_LOGIC; + granted_col_r_reg_0 : in STD_LOGIC; + \grant_r[1]_i_2_0\ : in STD_LOGIC; + \grant_r[1]_i_2_1\ : in STD_LOGIC; + ras_timer_zero_r_reg_1 : in STD_LOGIC; + pre_bm_end_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pre_bm_end_r_reg_0 : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + pre_wait_r_reg_0 : in STD_LOGIC; + tail_r : in STD_LOGIC; + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + auto_pre_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC; + demand_act_priority_r_reg_0 : in STD_LOGIC; + head_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r[3]_i_5__2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \starve_limit_cntr_r_reg[0]_0\ : in STD_LOGIC; + q_has_rd_1 : in STD_LOGIC; + req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_address_reg[40]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_address_reg[40]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_address_reg[40]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rtp_timer_r_reg[0]_0\ : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_state__parameterized1\ : entity is "mig_7series_v4_2_bank_state"; +end \ddr3_mig_7series_v4_2_bank_state__parameterized1\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_state__parameterized1\ is + signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC; + signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC; + signal \^bm_end_r1\ : STD_LOGIC; + signal \^bm_end_r1_reg_0\ : STD_LOGIC; + signal \^bm_end_r1_reg_1\ : STD_LOGIC; + signal \^col_wait_r\ : STD_LOGIC; + signal demand_act_priority_ns : STD_LOGIC; + signal \^demand_act_priority_r\ : STD_LOGIC; + signal \demand_priority_r_i_4__1_n_0\ : STD_LOGIC; + signal \^demand_priority_r_reg_0\ : STD_LOGIC; + signal demanded_prior_ns : STD_LOGIC; + signal \^demanded_prior_r_reg_0\ : STD_LOGIC; + signal \grant_r[3]_i_10_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_15__0_n_0\ : STD_LOGIC; + signal ofs_rdy_r : STD_LOGIC; + signal \^override_demand_r\ : STD_LOGIC; + signal \^pre_passing_open_bank_ns\ : STD_LOGIC; + signal pre_wait_ns : STD_LOGIC; + signal \^pre_wait_r\ : STD_LOGIC; + signal \pre_wait_r_i_2__1_n_0\ : STD_LOGIC; + signal \ras_timer_r_reg_n_0_[0]\ : STD_LOGIC; + signal \ras_timer_r_reg_n_0_[1]\ : STD_LOGIC; + signal \^ras_timer_zero_r\ : STD_LOGIC; + signal ras_timer_zero_r_i_1_n_0 : STD_LOGIC; + signal req_bank_rdy_r : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__12\ : STD_LOGIC; + signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \rtp_timer_r[0]_i_1__1_n_0\ : STD_LOGIC; + signal \rtp_timer_r[1]_i_1__1_n_0\ : STD_LOGIC; + signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal starve_limit_cntr_r0 : STD_LOGIC; + signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \grant_r[3]_i_3__2\ : label is "soft_lutpair527"; + attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__0\ : label is "soft_lutpair527"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair528"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair528"; +begin + act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\; + act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\; + bm_end_r1 <= \^bm_end_r1\; + bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\; + bm_end_r1_reg_1 <= \^bm_end_r1_reg_1\; + col_wait_r <= \^col_wait_r\; + demand_act_priority_r <= \^demand_act_priority_r\; + demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\; + demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\; + override_demand_r <= \^override_demand_r\; + pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\; + pre_wait_r <= \^pre_wait_r\; + ras_timer_zero_r <= \^ras_timer_zero_r\; + \rstdiv0_sync_r1_reg_rep__12\ <= \^rstdiv0_sync_r1_reg_rep__12\; +\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^act_wait_r_lcl_reg_0\, + Q => act_this_rank_r(0), + R => '0' + ); +act_wait_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => act_wait_ns, + Q => \^act_wait_r_lcl_reg_0\, + R => '0' + ); +\auto_pre_r_lcl_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020202000002000" + ) + port map ( + I0 => tail_r, + I1 => auto_pre_r_lcl_reg_0, + I2 => auto_pre_r_lcl_reg_1(0), + I3 => \^col_wait_r\, + I4 => Q(1), + I5 => \^act_wait_r_lcl_reg_0\, + O => \compute_tail.tail_r_lcl_reg\ + ); +bm_end_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bm_end(0), + Q => \^bm_end_r1\, + R => '0' + ); +\cmd_pipe_plus.mc_address[40]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888F00088880000" + ) + port map ( + I0 => \^act_wait_r_lcl_reg_0\, + I1 => \cmd_pipe_plus.mc_address_reg[40]\(0), + I2 => \cmd_pipe_plus.mc_address_reg[40]_0\(0), + I3 => pre_bm_end_r_reg(0), + I4 => pre_bm_end_r_reg(1), + I5 => \cmd_pipe_plus.mc_address_reg[40]_1\(0), + O => act_wait_r_lcl_reg_2 + ); +\col_wait_r_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => col_wait_r_reg_1, + I1 => \^col_wait_r\, + I2 => Q(1), + I3 => col_wait_r_reg_2, + O => \^rstdiv0_sync_r1_reg_rep__12\ + ); +col_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^rstdiv0_sync_r1_reg_rep__12\, + Q => \^col_wait_r\, + R => '0' + ); +\demand_act_priority_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080000000000" + ) + port map ( + I0 => \^demand_act_priority_r\, + I1 => \^ras_timer_zero_r\, + I2 => demand_act_priority_r_reg_0, + I3 => head_r(0), + I4 => E(0), + I5 => \^act_wait_r_lcl_reg_0\, + O => demand_act_priority_ns + ); +demand_act_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_act_priority_ns, + Q => \^demand_act_priority_r\, + R => '0' + ); +\demand_priority_r_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BAAAAAAA" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => \demand_priority_r_i_4__1_n_0\, + I2 => starve_limit_cntr_r(2), + I3 => starve_limit_cntr_r(1), + I4 => starve_limit_cntr_r(0), + O => demand_priority_r_reg_2 + ); +\demand_priority_r_i_4__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DFFFDFDF" + ) + port map ( + I0 => \starve_limit_cntr_r_reg[0]_0\, + I1 => Q(1), + I2 => req_bank_rdy_r, + I3 => q_has_rd_1, + I4 => req_wr_r(0), + O => \demand_priority_r_i_4__1_n_0\ + ); +demand_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_priority_ns, + Q => \^demand_priority_r_reg_0\, + R => '0' + ); +\demanded_prior_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D0D0D0D0D0DDD0D0" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => \^demanded_prior_r_reg_0\, + I2 => demanded_prior_r_reg_1, + I3 => Q(0), + I4 => demand_priority_r_1, + I5 => demanded_prior_r_0, + O => demanded_prior_ns + ); +demanded_prior_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demanded_prior_ns, + Q => \^demanded_prior_r_reg_0\, + R => '0' + ); +\grant_r[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFF1FFFF" + ) + port map ( + I0 => \^col_wait_r\, + I1 => col_wait_r_reg_2, + I2 => \grant_r_reg[1]\, + I3 => \grant_r[3]_i_10_n_0\, + I4 => \grant_r_reg[1]_0\(0), + O => col_wait_r_reg_0 + ); +\grant_r[3]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEFF" + ) + port map ( + I0 => \grant_r[3]_i_15__0_n_0\, + I1 => \grant_r[1]_i_2_0\, + I2 => override_demand_ns, + I3 => ofs_rdy_r, + I4 => Q(1), + I5 => \grant_r[1]_i_2_1\, + O => \grant_r[3]_i_10_n_0\ + ); +\grant_r[3]_i_14\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^act_wait_r_lcl_reg_0\, + I1 => \grant_r[3]_i_5__2\(0), + O => \^act_wait_r_lcl_reg_1\ + ); +\grant_r[3]_i_14__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055550010" + ) + port map ( + I0 => \^override_demand_r\, + I1 => \^demanded_prior_r_reg_0\, + I2 => \^demand_priority_r_reg_0\, + I3 => Q(1), + I4 => demanded_prior_r_reg_1, + I5 => demand_priority_r_1, + O => override_demand_r_reg_0 + ); +\grant_r[3]_i_15__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055550010" + ) + port map ( + I0 => \^override_demand_r\, + I1 => demanded_prior_r_0, + I2 => demand_priority_r_1, + I3 => Q(0), + I4 => demanded_prior_r_reg_1, + I5 => \^demand_priority_r_reg_0\, + O => \grant_r[3]_i_15__0_n_0\ + ); +\grant_r[3]_i_3__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => pre_bm_end_r_reg_0, + I1 => pre_bm_end_r_reg(1), + I2 => \^pre_wait_r\, + I3 => \^ras_timer_zero_r\, + O => auto_pre_r_lcl_reg + ); +\grant_r[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEAEFEAEFEAFFFF" + ) + port map ( + I0 => \grant_r[3]_i_10_n_0\, + I1 => granted_col_r_reg, + I2 => \rd_this_rank_r_reg[0]_0\, + I3 => granted_col_r_reg_0, + I4 => col_wait_r_reg_2, + I5 => \^col_wait_r\, + O => rd_wr_r_lcl_reg + ); +\grant_r[3]_i_6__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBBBBABB" + ) + port map ( + I0 => demand_priority_r_1, + I1 => demanded_prior_r_reg_1, + I2 => Q(1), + I3 => \^demand_priority_r_reg_0\, + I4 => \^demanded_prior_r_reg_0\, + O => demand_priority_r_reg_1 + ); +ofs_rdy_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => ofs_rdy_r0, + Q => ofs_rdy_r, + R => SR(0) + ); +override_demand_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => override_demand_ns, + Q => \^override_demand_r\, + R => '0' + ); +\pre_4_1_1T_arb.granted_pre_r_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000FFF7" + ) + port map ( + I0 => \^ras_timer_zero_r\, + I1 => \^pre_wait_r\, + I2 => pre_bm_end_r_reg(1), + I3 => pre_bm_end_r_reg_0, + I4 => \pre_4_1_1T_arb.granted_pre_r_reg\, + O => ras_timer_zero_r_reg_0 + ); +\pre_bm_end_r_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAEAEAAA" + ) + port map ( + I0 => \^pre_passing_open_bank_ns\, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => pre_bm_end_r_reg(1), + I4 => pre_bm_end_r_reg_0, + O => pre_bm_end_ns + ); +\pre_passing_open_bank_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAA8AAAAAAA8AAA8" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => Q(1), + I2 => rtp_timer_r(0), + I3 => rtp_timer_r(1), + I4 => \^ras_timer_zero_r\, + I5 => \^pre_wait_r\, + O => \^pre_passing_open_bank_ns\ + ); +\pre_wait_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444444454444" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => \pre_wait_r_i_2__1_n_0\, + I2 => pass_open_bank_r, + I3 => pre_wait_r_reg_0, + I4 => rtp_timer_r(0), + I5 => rtp_timer_r(1), + O => pre_wait_ns + ); +\pre_wait_r_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10101050" + ) + port map ( + I0 => pre_wait_r_reg_0, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => pre_bm_end_r_reg(1), + I4 => pre_bm_end_r_reg_0, + O => \pre_wait_r_i_2__1_n_0\ + ); +pre_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_wait_ns, + Q => \^pre_wait_r\, + R => '0' + ); +\ras_timer_r[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000111011111111" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => col_wait_r_reg_1, + I2 => \^act_wait_r_lcl_reg_1\, + I3 => \ras_timer_r_reg_n_0_[1]\, + I4 => \ras_timer_r_reg_n_0_[0]\, + I5 => ras_timer_zero_r_reg_1, + O => \^bm_end_r1_reg_0\ + ); +\ras_timer_r[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000111110001000" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => col_wait_r_reg_1, + I2 => \ras_timer_r_reg_n_0_[1]\, + I3 => \ras_timer_r_reg_n_0_[0]\, + I4 => \rd_this_rank_r_reg[0]_0\, + I5 => Q(1), + O => \^bm_end_r1_reg_1\ + ); +\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(0), + Q => \ras_timer_r_reg_n_0_[0]\, + R => '0' + ); +\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(1), + Q => \ras_timer_r_reg_n_0_[1]\, + R => '0' + ); +ras_timer_zero_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^bm_end_r1_reg_0\, + I1 => \^bm_end_r1_reg_1\, + O => ras_timer_zero_r_i_1_n_0 + ); +ras_timer_zero_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ras_timer_zero_r_i_1_n_0, + Q => \^ras_timer_zero_r\, + R => '0' + ); +\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_this_rank_r_reg[0]_0\, + Q => rd_this_rank_r(0), + R => '0' + ); +req_bank_rdy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => req_bank_rdy_ns, + Q => req_bank_rdy_r, + R => '0' + ); +\rtp_timer_r[0]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \rtp_timer_r_reg[0]_0\, + I1 => pass_open_bank_r, + I2 => rtp_timer_r(1), + I3 => rtp_timer_r(0), + O => \rtp_timer_r[0]_i_1__1_n_0\ + ); +\rtp_timer_r[1]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000C2" + ) + port map ( + I0 => Q(1), + I1 => rtp_timer_r(0), + I2 => rtp_timer_r(1), + I3 => pass_open_bank_r, + I4 => col_wait_r_reg_1, + O => \rtp_timer_r[1]_i_1__1_n_0\ + ); +\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[0]_i_1__1_n_0\, + Q => rtp_timer_r(0), + R => '0' + ); +\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[1]_i_1__1_n_0\, + Q => rtp_timer_r(1), + R => '0' + ); +\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r0, + I2 => \^col_wait_r\, + O => \starve_limit_cntr_r[0]_i_1_n_0\ + ); +\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6A00" + ) + port map ( + I0 => starve_limit_cntr_r(1), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => \^col_wait_r\, + O => \starve_limit_cntr_r[1]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAA0000" + ) + port map ( + I0 => starve_limit_cntr_r(2), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => starve_limit_cntr_r(1), + I4 => \^col_wait_r\, + O => \starve_limit_cntr_r[2]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00007F0000000000" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r(1), + I2 => starve_limit_cntr_r(2), + I3 => \starve_limit_cntr_r_reg[0]_0\, + I4 => Q(1), + I5 => req_bank_rdy_r, + O => starve_limit_cntr_r0 + ); +\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[0]_i_1_n_0\, + Q => starve_limit_cntr_r(0), + R => '0' + ); +\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[1]_i_1_n_0\, + Q => starve_limit_cntr_r(1), + R => '0' + ); +\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[2]_i_1_n_0\, + Q => starve_limit_cntr_r(2), + R => '0' + ); +\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => start_wtp_timer0, + Q => wr_this_rank_r(0), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_state__parameterized2\ is + port ( + act_wait_r_lcl_reg_0 : out STD_LOGIC; + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + bm_end_r1 : out STD_LOGIC; + ras_timer_zero_r : out STD_LOGIC; + pre_wait_r : out STD_LOGIC; + col_wait_r_reg_0 : out STD_LOGIC; + demand_act_priority_r : out STD_LOGIC; + demand_priority_r_reg_0 : out STD_LOGIC; + demanded_prior_r_reg_0 : out STD_LOGIC; + ofs_rdy_r : out STD_LOGIC; + override_demand_r_reg : out STD_LOGIC; + act_wait_r_lcl_reg_1 : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + bm_end_r1_reg_1 : out STD_LOGIC; + pre_bm_end_ns : out STD_LOGIC; + pre_passing_open_bank_ns : out STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : out STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_ns\ : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + demand_priority_r_reg_1 : out STD_LOGIC; + demanded_prior_r_reg_1 : out STD_LOGIC; + act_wait_ns : in STD_LOGIC; + CLK : in STD_LOGIC; + start_wtp_timer0 : in STD_LOGIC; + \rd_this_rank_r_reg[0]_0\ : in STD_LOGIC; + bm_end_r1_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_bank_rdy_ns : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ofs_rdy_r0 : in STD_LOGIC; + col_wait_r_reg_1 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + col_wait_r_reg_2 : in STD_LOGIC; + override_demand_r : in STD_LOGIC; + demanded_prior_r_reg_2 : in STD_LOGIC; + demand_priority_r_0 : in STD_LOGIC; + pass_open_bank_r : in STD_LOGIC; + demand_priority_r_reg_2 : in STD_LOGIC; + req_priority_r : in STD_LOGIC; + q_has_priority : in STD_LOGIC; + demand_priority_r_reg_3 : in STD_LOGIC; + ras_timer_zero_r_reg_0 : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pre_4_1_1T_arb.granted_pre_r_reg_0\ : in STD_LOGIC; + pass_open_bank_ns : in STD_LOGIC; + pre_wait_r_reg_0 : in STD_LOGIC; + tail_r : in STD_LOGIC; + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + auto_pre_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pre_4_1_1T_arb.granted_pre_r_reg_1\ : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg_2\ : in STD_LOGIC; + demand_act_priority_r_reg_0 : in STD_LOGIC; + head_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + ras_timer_zero_r_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + demanded_prior_r_1 : in STD_LOGIC; + \starve_limit_cntr_r_reg[0]_0\ : in STD_LOGIC; + q_has_rd_2 : in STD_LOGIC; + req_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rtp_timer_r_reg[0]_0\ : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_state__parameterized2\ : entity is "mig_7series_v4_2_bank_state"; +end \ddr3_mig_7series_v4_2_bank_state__parameterized2\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_state__parameterized2\ is + signal \^act_wait_r_lcl_reg_0\ : STD_LOGIC; + signal \^act_wait_r_lcl_reg_1\ : STD_LOGIC; + signal \^bm_end_r1\ : STD_LOGIC; + signal col_wait_r_i_1_n_0 : STD_LOGIC; + signal \^col_wait_r_reg_0\ : STD_LOGIC; + signal demand_act_priority_ns : STD_LOGIC; + signal \^demand_act_priority_r\ : STD_LOGIC; + signal demand_priority_ns : STD_LOGIC; + signal \demand_priority_r_i_3__2_n_0\ : STD_LOGIC; + signal \demand_priority_r_i_4__2_n_0\ : STD_LOGIC; + signal \^demand_priority_r_reg_0\ : STD_LOGIC; + signal demanded_prior_ns : STD_LOGIC; + signal \^demanded_prior_r_reg_0\ : STD_LOGIC; + signal \^pre_passing_open_bank_ns\ : STD_LOGIC; + signal pre_wait_ns : STD_LOGIC; + signal \^pre_wait_r\ : STD_LOGIC; + signal \pre_wait_r_i_2__2_n_0\ : STD_LOGIC; + signal \ras_timer_r_reg_n_0_[0]\ : STD_LOGIC; + signal \ras_timer_r_reg_n_0_[1]\ : STD_LOGIC; + signal \^ras_timer_zero_r\ : STD_LOGIC; + signal \ras_timer_zero_r_i_1__0_n_0\ : STD_LOGIC; + signal req_bank_rdy_r : STD_LOGIC; + signal rtp_timer_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \rtp_timer_r[0]_i_1__2_n_0\ : STD_LOGIC; + signal \rtp_timer_r[1]_i_1__2_n_0\ : STD_LOGIC; + signal starve_limit_cntr_r : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal starve_limit_cntr_r0 : STD_LOGIC; + signal \starve_limit_cntr_r[0]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[1]_i_1_n_0\ : STD_LOGIC; + signal \starve_limit_cntr_r[2]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \grant_r[3]_i_6__0\ : label is "soft_lutpair534"; + attribute SOFT_HLUTNM of \pre_bm_end_r_i_1__2\ : label is "soft_lutpair534"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[1]_i_1\ : label is "soft_lutpair535"; + attribute SOFT_HLUTNM of \starve_limit_cntr_r[2]_i_1\ : label is "soft_lutpair535"; +begin + act_wait_r_lcl_reg_0 <= \^act_wait_r_lcl_reg_0\; + act_wait_r_lcl_reg_1 <= \^act_wait_r_lcl_reg_1\; + bm_end_r1 <= \^bm_end_r1\; + col_wait_r_reg_0 <= \^col_wait_r_reg_0\; + demand_act_priority_r <= \^demand_act_priority_r\; + demand_priority_r_reg_0 <= \^demand_priority_r_reg_0\; + demanded_prior_r_reg_0 <= \^demanded_prior_r_reg_0\; + pre_passing_open_bank_ns <= \^pre_passing_open_bank_ns\; + pre_wait_r <= \^pre_wait_r\; + ras_timer_zero_r <= \^ras_timer_zero_r\; +\act_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^act_wait_r_lcl_reg_0\, + Q => act_this_rank_r(0), + R => '0' + ); +act_wait_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => act_wait_ns, + Q => \^act_wait_r_lcl_reg_0\, + R => '0' + ); +\auto_pre_r_lcl_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020202000002000" + ) + port map ( + I0 => tail_r, + I1 => auto_pre_r_lcl_reg_0, + I2 => auto_pre_r_lcl_reg_1(0), + I3 => \^col_wait_r_reg_0\, + I4 => Q(1), + I5 => \^act_wait_r_lcl_reg_0\, + O => \compute_tail.tail_r_lcl_reg\ + ); +bm_end_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bm_end_r1_reg_2(0), + Q => \^bm_end_r1\, + R => '0' + ); +col_wait_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"5504" + ) + port map ( + I0 => col_wait_r_reg_1, + I1 => \^col_wait_r_reg_0\, + I2 => Q(1), + I3 => col_wait_r_reg_2, + O => col_wait_r_i_1_n_0 + ); +col_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_wait_r_i_1_n_0, + Q => \^col_wait_r_reg_0\, + R => '0' + ); +\demand_act_priority_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000080000000000" + ) + port map ( + I0 => \^demand_act_priority_r\, + I1 => \^ras_timer_zero_r\, + I2 => demand_act_priority_r_reg_0, + I3 => head_r(0), + I4 => E(0), + I5 => \^act_wait_r_lcl_reg_0\, + O => demand_act_priority_ns + ); +demand_act_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_act_priority_ns, + Q => \^demand_act_priority_r\, + R => '0' + ); +demand_priority_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888800008880" + ) + port map ( + I0 => col_wait_r_i_1_n_0, + I1 => demand_priority_r_reg_2, + I2 => req_priority_r, + I3 => q_has_priority, + I4 => demand_priority_r_reg_3, + I5 => \demand_priority_r_i_3__2_n_0\, + O => demand_priority_ns + ); +\demand_priority_r_i_3__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BAAAAAAA" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => \demand_priority_r_i_4__2_n_0\, + I2 => starve_limit_cntr_r(2), + I3 => starve_limit_cntr_r(1), + I4 => starve_limit_cntr_r(0), + O => \demand_priority_r_i_3__2_n_0\ + ); +\demand_priority_r_i_4__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DFFFDFDF" + ) + port map ( + I0 => \starve_limit_cntr_r_reg[0]_0\, + I1 => Q(1), + I2 => req_bank_rdy_r, + I3 => q_has_rd_2, + I4 => req_wr_r(0), + O => \demand_priority_r_i_4__2_n_0\ + ); +demand_priority_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demand_priority_ns, + Q => \^demand_priority_r_reg_0\, + R => '0' + ); +\demanded_prior_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000D00DDDDDDDD" + ) + port map ( + I0 => \^demand_priority_r_reg_0\, + I1 => \^demanded_prior_r_reg_0\, + I2 => Q(0), + I3 => demand_priority_r_0, + I4 => demanded_prior_r_1, + I5 => demanded_prior_r_reg_2, + O => demanded_prior_ns + ); +demanded_prior_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0404040404FF0404" + ) + port map ( + I0 => \^demanded_prior_r_reg_0\, + I1 => \^demand_priority_r_reg_0\, + I2 => Q(1), + I3 => demanded_prior_r_1, + I4 => demand_priority_r_0, + I5 => Q(0), + O => demanded_prior_r_reg_1 + ); +demanded_prior_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => demanded_prior_ns, + Q => \^demanded_prior_r_reg_0\, + R => '0' + ); +\grant_r[2]_i_5__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEFAAAA" + ) + port map ( + I0 => demand_priority_r_0, + I1 => Q(1), + I2 => \^demand_priority_r_reg_0\, + I3 => \^demanded_prior_r_reg_0\, + I4 => demanded_prior_r_reg_2, + O => demand_priority_r_reg_1 + ); +\grant_r[3]_i_17\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000011111511" + ) + port map ( + I0 => override_demand_r, + I1 => demanded_prior_r_reg_2, + I2 => \^demanded_prior_r_reg_0\, + I3 => \^demand_priority_r_reg_0\, + I4 => Q(1), + I5 => demand_priority_r_0, + O => override_demand_r_reg + ); +\grant_r[3]_i_6__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => \pre_4_1_1T_arb.granted_pre_r_reg_0\, + I1 => \pre_4_1_1T_arb.granted_pre_r_reg\(0), + I2 => \^pre_wait_r\, + I3 => \^ras_timer_zero_r\, + O => auto_pre_r_lcl_reg + ); +ofs_rdy_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => ofs_rdy_r0, + Q => ofs_rdy_r, + R => SR(0) + ); +\pre_4_1_1T_arb.granted_pre_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABAAAAAAFFFFFFFF" + ) + port map ( + I0 => \pre_4_1_1T_arb.granted_pre_r_reg_1\, + I1 => \pre_4_1_1T_arb.granted_pre_r_reg_0\, + I2 => \pre_4_1_1T_arb.granted_pre_r_reg\(0), + I3 => \^pre_wait_r\, + I4 => \^ras_timer_zero_r\, + I5 => \pre_4_1_1T_arb.granted_pre_r_reg_2\, + O => \pre_4_1_1T_arb.granted_pre_ns\ + ); +\pre_bm_end_r_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAEAEAAA" + ) + port map ( + I0 => \^pre_passing_open_bank_ns\, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => \pre_4_1_1T_arb.granted_pre_r_reg\(0), + I4 => \pre_4_1_1T_arb.granted_pre_r_reg_0\, + O => pre_bm_end_ns + ); +\pre_passing_open_bank_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAA8AAAAAAA8AAA8" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => Q(1), + I2 => rtp_timer_r(0), + I3 => rtp_timer_r(1), + I4 => \^ras_timer_zero_r\, + I5 => \^pre_wait_r\, + O => \^pre_passing_open_bank_ns\ + ); +\pre_wait_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4444444444454444" + ) + port map ( + I0 => pass_open_bank_ns, + I1 => \pre_wait_r_i_2__2_n_0\, + I2 => pass_open_bank_r, + I3 => pre_wait_r_reg_0, + I4 => rtp_timer_r(0), + I5 => rtp_timer_r(1), + O => pre_wait_ns + ); +\pre_wait_r_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10101050" + ) + port map ( + I0 => pre_wait_r_reg_0, + I1 => \^ras_timer_zero_r\, + I2 => \^pre_wait_r\, + I3 => \pre_4_1_1T_arb.granted_pre_r_reg\(0), + I4 => \pre_4_1_1T_arb.granted_pre_r_reg_0\, + O => \pre_wait_r_i_2__2_n_0\ + ); +pre_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pre_wait_ns, + Q => \^pre_wait_r\, + R => '0' + ); +\ras_timer_r[0]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000111011111111" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => col_wait_r_reg_1, + I2 => \^act_wait_r_lcl_reg_1\, + I3 => \ras_timer_r_reg_n_0_[1]\, + I4 => \ras_timer_r_reg_n_0_[0]\, + I5 => ras_timer_zero_r_reg_0, + O => bm_end_r1_reg_0 + ); +\ras_timer_r[1]_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1000111110001000" + ) + port map ( + I0 => \^bm_end_r1\, + I1 => col_wait_r_reg_1, + I2 => \ras_timer_r_reg_n_0_[1]\, + I3 => \ras_timer_r_reg_n_0_[0]\, + I4 => \rd_this_rank_r_reg[0]_0\, + I5 => Q(1), + O => bm_end_r1_reg_1 + ); +\ras_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(0), + Q => \ras_timer_r_reg_n_0_[0]\, + R => '0' + ); +\ras_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(1), + Q => \ras_timer_r_reg_n_0_[1]\, + R => '0' + ); +\ras_timer_zero_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF00C4" + ) + port map ( + I0 => \^act_wait_r_lcl_reg_1\, + I1 => ras_timer_zero_r_reg_0, + I2 => \ras_timer_r_reg_n_0_[0]\, + I3 => \ras_timer_r_reg_n_0_[1]\, + I4 => col_wait_r_reg_1, + I5 => \^bm_end_r1\, + O => \ras_timer_zero_r_i_1__0_n_0\ + ); +ras_timer_zero_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^act_wait_r_lcl_reg_0\, + I1 => ras_timer_zero_r_reg_1(0), + O => \^act_wait_r_lcl_reg_1\ + ); +ras_timer_zero_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ras_timer_zero_r_i_1__0_n_0\, + Q => \^ras_timer_zero_r\, + R => '0' + ); +\rd_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_this_rank_r_reg[0]_0\, + Q => rd_this_rank_r(0), + R => '0' + ); +req_bank_rdy_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => req_bank_rdy_ns, + Q => req_bank_rdy_r, + R => '0' + ); +\rtp_timer_r[0]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \rtp_timer_r_reg[0]_0\, + I1 => pass_open_bank_r, + I2 => rtp_timer_r(1), + I3 => rtp_timer_r(0), + O => \rtp_timer_r[0]_i_1__2_n_0\ + ); +\rtp_timer_r[1]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000C2" + ) + port map ( + I0 => Q(1), + I1 => rtp_timer_r(0), + I2 => rtp_timer_r(1), + I3 => pass_open_bank_r, + I4 => col_wait_r_reg_1, + O => \rtp_timer_r[1]_i_1__2_n_0\ + ); +\rtp_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[0]_i_1__2_n_0\, + Q => rtp_timer_r(0), + R => '0' + ); +\rtp_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rtp_timer_r[1]_i_1__2_n_0\, + Q => rtp_timer_r(1), + R => '0' + ); +\starve_limit_cntr_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"60" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r0, + I2 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[0]_i_1_n_0\ + ); +\starve_limit_cntr_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6A00" + ) + port map ( + I0 => starve_limit_cntr_r(1), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[1]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAA0000" + ) + port map ( + I0 => starve_limit_cntr_r(2), + I1 => starve_limit_cntr_r0, + I2 => starve_limit_cntr_r(0), + I3 => starve_limit_cntr_r(1), + I4 => \^col_wait_r_reg_0\, + O => \starve_limit_cntr_r[2]_i_1_n_0\ + ); +\starve_limit_cntr_r[2]_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00007F0000000000" + ) + port map ( + I0 => starve_limit_cntr_r(0), + I1 => starve_limit_cntr_r(1), + I2 => starve_limit_cntr_r(2), + I3 => \starve_limit_cntr_r_reg[0]_0\, + I4 => Q(1), + I5 => req_bank_rdy_r, + O => starve_limit_cntr_r0 + ); +\starve_limit_cntr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[0]_i_1_n_0\, + Q => starve_limit_cntr_r(0), + R => '0' + ); +\starve_limit_cntr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[1]_i_1_n_0\, + Q => starve_limit_cntr_r(1), + R => '0' + ); +\starve_limit_cntr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \starve_limit_cntr_r[2]_i_1_n_0\, + Q => starve_limit_cntr_r(2), + R => '0' + ); +\wr_this_rank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => start_wtp_timer0, + Q => wr_this_rank_r(0), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_clk_ibuf is + port ( + mmcm_clk : out STD_LOGIC; + sys_clk_i : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_clk_ibuf : entity is "mig_7series_v4_2_clk_ibuf"; +end ddr3_mig_7series_v4_2_clk_ibuf; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_clk_ibuf is + signal sys_clk_ibufg : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sys_clk_ibufg : signal is "true"; + attribute syn_keep : string; + attribute syn_keep of sys_clk_ibufg : signal is "true"; +begin + mmcm_clk <= sys_clk_ibufg; + sys_clk_ibufg <= sys_clk_i; +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_col_mach is + port ( + D : out STD_LOGIC_VECTOR ( 3 downto 0 ); + mc_wrdata_en_ns : out STD_LOGIC; + wr_data_en_ns : out STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[6]_0\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \read_fifo.tail_r_reg[0]_0\ : out STD_LOGIC; + \read_fifo.tail_r_reg[4]_0\ : out STD_LOGIC; + mc_ref_zq_wip_ns : out STD_LOGIC; + \not_strict_mode.app_rd_data_end_ns\ : out STD_LOGIC; + \not_strict_mode.bypass__0\ : out STD_LOGIC; + CLK : in STD_LOGIC; + col_data_buf_addr : in STD_LOGIC_VECTOR ( 4 downto 0 ); + DIC : in STD_LOGIC_VECTOR ( 0 to 0 ); + col_rd_wr : in STD_LOGIC; + mc_cmd : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg[1]_0\ : in STD_LOGIC; + ram_init_done_r : in STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[5]_0\ : in STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[5]_1\ : in STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[7]_0\ : in STD_LOGIC; + maint_ref_zq_wip : in STD_LOGIC; + \not_strict_mode.app_rd_data_end_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_data_en : in STD_LOGIC; + \not_strict_mode.app_rd_data_end_reg_0\ : in STD_LOGIC; + ram_init_addr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \read_fifo.head_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + I121 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg[1]_1\ : in STD_LOGIC; + \read_fifo.tail_r_reg[0]_1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_col_mach : entity is "mig_7series_v4_2_col_mach"; +end ddr3_mig_7series_v4_2_col_mach; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_col_mach is + signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal col_rd_wr_r1 : STD_LOGIC; + signal col_rd_wr_r2 : STD_LOGIC; + signal mc_ref_zq_wip_r_i_2_n_0 : STD_LOGIC; + signal \not_strict_mode.app_rd_data[127]_i_4_n_0\ : STD_LOGIC; + signal \^not_strict_mode.bypass__0\ : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \read_fifo.fifo_out_data_ns\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\ : STD_LOGIC; + signal \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\ : STD_LOGIC; + signal \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\ : STD_LOGIC; + signal \read_fifo.head_r_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \read_fifo.tail_ns\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \read_fifo.tail_r[1]_i_1_n_0\ : STD_LOGIC; + signal \read_fifo.tail_r[2]_i_1_n_0\ : STD_LOGIC; + signal \read_fifo.tail_r[3]_i_1_n_0\ : STD_LOGIC; + signal \read_fifo.tail_r[4]_i_1_n_0\ : STD_LOGIC; + signal \read_fifo.tail_r_reg\ : STD_LOGIC_VECTOR ( 4 downto 1 ); + signal \^read_fifo.tail_r_reg[0]_0\ : STD_LOGIC; + signal sent_col_r2 : STD_LOGIC; + signal \NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of \read_fifo.fifo_ram[0].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \read_fifo.fifo_ram[1].RAM32M0\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \read_fifo.head_r[1]_i_1\ : label is "soft_lutpair544"; + attribute SOFT_HLUTNM of \read_fifo.head_r[2]_i_1\ : label is "soft_lutpair544"; + attribute SOFT_HLUTNM of \read_fifo.head_r[3]_i_1\ : label is "soft_lutpair543"; + attribute SOFT_HLUTNM of \read_fifo.head_r[4]_i_1\ : label is "soft_lutpair543"; + attribute SOFT_HLUTNM of \read_fifo.tail_r[2]_i_1\ : label is "soft_lutpair542"; + attribute SOFT_HLUTNM of \read_fifo.tail_r[3]_i_1\ : label is "soft_lutpair542"; +begin + Q(7 downto 0) <= \^q\(7 downto 0); + \not_strict_mode.bypass__0\ <= \^not_strict_mode.bypass__0\; + \read_fifo.tail_r_reg[0]_0\ <= \^read_fifo.tail_r_reg[0]_0\; +\cmd_pipe_plus.mc_wrdata_en_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => sent_col_r2, + I1 => col_rd_wr_r2, + O => mc_wrdata_en_ns + ); +\cmd_pipe_plus.wr_data_en_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => mc_cmd(0), + I1 => col_rd_wr_r1, + O => wr_data_en_ns + ); +\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_data_buf_addr(0), + Q => D(0), + R => '0' + ); +\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_data_buf_addr(1), + Q => D(1), + R => '0' + ); +\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_data_buf_addr(2), + Q => D(2), + R => '0' + ); +\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_data_buf_addr(3), + Q => D(3), + R => '0' + ); +mc_read_idle_r_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"09000009" + ) + port map ( + I0 => \read_fifo.tail_r_reg\(4), + I1 => \read_fifo.head_r_reg\(4), + I2 => mc_ref_zq_wip_r_i_2_n_0, + I3 => \read_fifo.head_r_reg\(3), + I4 => \read_fifo.tail_r_reg\(3), + O => \read_fifo.tail_r_reg[4]_0\ + ); +mc_ref_zq_wip_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0082000000000082" + ) + port map ( + I0 => maint_ref_zq_wip, + I1 => \read_fifo.tail_r_reg\(4), + I2 => \read_fifo.head_r_reg\(4), + I3 => mc_ref_zq_wip_r_i_2_n_0, + I4 => \read_fifo.head_r_reg\(3), + I5 => \read_fifo.tail_r_reg\(3), + O => mc_ref_zq_wip_ns + ); +mc_ref_zq_wip_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"6FF6FFFFFFFF6FF6" + ) + port map ( + I0 => \read_fifo.head_r_reg\(1), + I1 => \read_fifo.tail_r_reg\(1), + I2 => \read_fifo.head_r_reg\(2), + I3 => \read_fifo.tail_r_reg\(2), + I4 => \^read_fifo.tail_r_reg[0]_0\, + I5 => \read_fifo.head_r_reg\(0), + O => mc_ref_zq_wip_r_i_2_n_0 + ); +\not_strict_mode.app_rd_data[127]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8200000000008200" + ) + port map ( + I0 => rd_data_en, + I1 => \^q\(5), + I2 => \not_strict_mode.app_rd_data_end_reg_0\, + I3 => \not_strict_mode.app_rd_data[127]_i_4_n_0\, + I4 => ram_init_addr(3), + I5 => \^q\(4), + O => \^not_strict_mode.bypass__0\ + ); +\not_strict_mode.app_rd_data[127]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^q\(1), + I1 => ram_init_addr(0), + I2 => ram_init_addr(2), + I3 => \^q\(3), + I4 => ram_init_addr(1), + I5 => \^q\(2), + O => \not_strict_mode.app_rd_data[127]_i_4_n_0\ + ); +\not_strict_mode.app_rd_data_end_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \^q\(7), + I1 => \^not_strict_mode.bypass__0\, + I2 => \not_strict_mode.app_rd_data_end_reg\(0), + O => \not_strict_mode.app_rd_data_end_ns\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \^q\(6), + I1 => \read_fifo.tail_r_reg[1]_0\, + I2 => ram_init_done_r, + O => \read_fifo.fifo_out_data_r_reg[6]_0\ + ); +\offset_pipe_0.col_rd_wr_r1_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_rd_wr, + Q => col_rd_wr_r1, + R => '0' + ); +\offset_pipe_1.col_rd_wr_r2_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_rd_wr_r1, + Q => col_rd_wr_r2, + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(0), + Q => \^q\(0), + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(1), + Q => \^q\(1), + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(2), + Q => \^q\(2), + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(3), + Q => \^q\(3), + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(4), + Q => \^q\(4), + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(5), + Q => \^q\(5), + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(6), + Q => \^q\(6), + R => '0' + ); +\read_fifo.fifo_out_data_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.fifo_out_data_ns\(7), + Q => \^q\(7), + R => '0' + ); +\read_fifo.fifo_ram[0].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4) => \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\, + ADDRA(3) => \read_fifo.tail_ns\(3), + ADDRA(2) => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\, + ADDRA(1) => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\, + ADDRA(0) => \read_fifo.tail_ns\(0), + ADDRB(4) => \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\, + ADDRB(3) => \read_fifo.tail_ns\(3), + ADDRB(2) => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\, + ADDRB(1) => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\, + ADDRB(0) => \read_fifo.tail_ns\(0), + ADDRC(4) => \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\, + ADDRC(3) => \read_fifo.tail_ns\(3), + ADDRC(2) => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\, + ADDRC(1) => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\, + ADDRC(0) => \read_fifo.tail_ns\(0), + ADDRD(4 downto 0) => \read_fifo.head_r_reg\(4 downto 0), + DIA(1 downto 0) => col_data_buf_addr(4 downto 3), + DIB(1 downto 0) => col_data_buf_addr(2 downto 1), + DIC(1) => col_data_buf_addr(0), + DIC(0) => '0', + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \read_fifo.fifo_out_data_ns\(5 downto 4), + DOB(1 downto 0) => \read_fifo.fifo_out_data_ns\(3 downto 2), + DOC(1 downto 0) => \read_fifo.fifo_out_data_ns\(1 downto 0), + DOD(1 downto 0) => \NLW_read_fifo.fifo_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => '1' + ); +\read_fifo.fifo_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1555555540000000" + ) + port map ( + I0 => \read_fifo.fifo_out_data_r_reg[5]_0\, + I1 => \read_fifo.tail_r_reg\(3), + I2 => \read_fifo.tail_r_reg\(2), + I3 => \read_fifo.fifo_out_data_r_reg[5]_1\, + I4 => \read_fifo.tail_r_reg\(1), + I5 => \read_fifo.tail_r_reg\(4), + O => \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000007FFF8000" + ) + port map ( + I0 => \read_fifo.tail_r_reg\(1), + I1 => \read_fifo.tail_r_reg[1]_0\, + I2 => \^read_fifo.tail_r_reg[0]_0\, + I3 => \read_fifo.tail_r_reg\(2), + I4 => \read_fifo.tail_r_reg\(3), + I5 => \read_fifo.fifo_out_data_r_reg[7]_0\, + O => \read_fifo.tail_ns\(3) + ); +\read_fifo.fifo_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"15554000" + ) + port map ( + I0 => \read_fifo.fifo_out_data_r_reg[5]_0\, + I1 => \^read_fifo.tail_r_reg[0]_0\, + I2 => \read_fifo.tail_r_reg[1]_0\, + I3 => \read_fifo.tail_r_reg\(1), + I4 => \read_fifo.tail_r_reg\(2), + O => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1540" + ) + port map ( + I0 => \read_fifo.fifo_out_data_r_reg[7]_0\, + I1 => \read_fifo.tail_r_reg[1]_0\, + I2 => \^read_fifo.tail_r_reg[0]_0\, + I3 => \read_fifo.tail_r_reg\(1), + O => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => \^read_fifo.tail_r_reg[0]_0\, + I1 => \read_fifo.tail_r_reg[1]_0\, + I2 => \read_fifo.fifo_out_data_r_reg[7]_0\, + O => \read_fifo.tail_ns\(0) + ); +\read_fifo.fifo_ram[1].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4) => \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\, + ADDRA(3) => \read_fifo.tail_ns\(3), + ADDRA(2) => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\, + ADDRA(1) => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\, + ADDRA(0) => \read_fifo.tail_ns\(0), + ADDRB(4) => \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\, + ADDRB(3) => \read_fifo.tail_ns\(3), + ADDRB(2) => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\, + ADDRB(1) => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\, + ADDRB(0) => \read_fifo.tail_ns\(0), + ADDRC(4) => \read_fifo.fifo_ram[0].RAM32M0_i_5_n_0\, + ADDRC(3) => \read_fifo.tail_ns\(3), + ADDRC(2) => \read_fifo.fifo_ram[0].RAM32M0_i_7_n_0\, + ADDRC(1) => \read_fifo.fifo_ram[0].RAM32M0_i_8_n_0\, + ADDRC(0) => \read_fifo.tail_ns\(0), + ADDRD(4 downto 0) => \read_fifo.head_r_reg\(4 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1) => '1', + DIC(0) => DIC(0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \read_fifo.fifo_out_data_ns\(7 downto 6), + DOD(1 downto 0) => \NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => '1' + ); +\read_fifo.head_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \read_fifo.head_r_reg\(0), + O => p_0_in(0) + ); +\read_fifo.head_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \read_fifo.head_r_reg\(0), + I1 => \read_fifo.head_r_reg\(1), + O => p_0_in(1) + ); +\read_fifo.head_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \read_fifo.head_r_reg\(2), + I1 => \read_fifo.head_r_reg\(1), + I2 => \read_fifo.head_r_reg\(0), + O => p_0_in(2) + ); +\read_fifo.head_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \read_fifo.head_r_reg\(3), + I1 => \read_fifo.head_r_reg\(0), + I2 => \read_fifo.head_r_reg\(1), + I3 => \read_fifo.head_r_reg\(2), + O => p_0_in(3) + ); +\read_fifo.head_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \read_fifo.head_r_reg\(4), + I1 => \read_fifo.head_r_reg\(2), + I2 => \read_fifo.head_r_reg\(1), + I3 => \read_fifo.head_r_reg\(0), + I4 => \read_fifo.head_r_reg\(3), + O => p_0_in(4) + ); +\read_fifo.head_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => I121(0), + D => p_0_in(0), + Q => \read_fifo.head_r_reg\(0), + R => \read_fifo.head_r_reg[0]_0\(0) + ); +\read_fifo.head_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => I121(0), + D => p_0_in(1), + Q => \read_fifo.head_r_reg\(1), + R => \read_fifo.head_r_reg[0]_0\(0) + ); +\read_fifo.head_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => I121(0), + D => p_0_in(2), + Q => \read_fifo.head_r_reg\(2), + R => \read_fifo.head_r_reg[0]_0\(0) + ); +\read_fifo.head_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => I121(0), + D => p_0_in(3), + Q => \read_fifo.head_r_reg\(3), + R => \read_fifo.head_r_reg[0]_0\(0) + ); +\read_fifo.head_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => I121(0), + D => p_0_in(4), + Q => \read_fifo.head_r_reg\(4), + R => \read_fifo.head_r_reg[0]_0\(0) + ); +\read_fifo.tail_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \read_fifo.tail_r_reg[1]_0\, + I1 => \^read_fifo.tail_r_reg[0]_0\, + I2 => \read_fifo.tail_r_reg\(1), + O => \read_fifo.tail_r[1]_i_1_n_0\ + ); +\read_fifo.tail_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^read_fifo.tail_r_reg[0]_0\, + I1 => \read_fifo.tail_r_reg[1]_0\, + I2 => \read_fifo.tail_r_reg\(1), + I3 => \read_fifo.tail_r_reg\(2), + O => \read_fifo.tail_r[2]_i_1_n_0\ + ); +\read_fifo.tail_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \read_fifo.tail_r_reg\(3), + I1 => \read_fifo.tail_r_reg\(2), + I2 => \^read_fifo.tail_r_reg[0]_0\, + I3 => \read_fifo.tail_r_reg[1]_0\, + I4 => \read_fifo.tail_r_reg\(1), + O => \read_fifo.tail_r[3]_i_1_n_0\ + ); +\read_fifo.tail_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \read_fifo.tail_r_reg\(3), + I1 => \read_fifo.tail_r_reg\(2), + I2 => \^read_fifo.tail_r_reg[0]_0\, + I3 => \read_fifo.tail_r_reg[1]_0\, + I4 => \read_fifo.tail_r_reg\(1), + I5 => \read_fifo.tail_r_reg\(4), + O => \read_fifo.tail_r[4]_i_1_n_0\ + ); +\read_fifo.tail_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.tail_r_reg[0]_1\, + Q => \^read_fifo.tail_r_reg[0]_0\, + R => \read_fifo.tail_r_reg[1]_1\ + ); +\read_fifo.tail_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.tail_r[1]_i_1_n_0\, + Q => \read_fifo.tail_r_reg\(1), + R => \read_fifo.tail_r_reg[1]_1\ + ); +\read_fifo.tail_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.tail_r[2]_i_1_n_0\, + Q => \read_fifo.tail_r_reg\(2), + R => \read_fifo.tail_r_reg[1]_1\ + ); +\read_fifo.tail_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.tail_r[3]_i_1_n_0\, + Q => \read_fifo.tail_r_reg\(3), + R => \read_fifo.tail_r_reg[1]_1\ + ); +\read_fifo.tail_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \read_fifo.tail_r[4]_i_1_n_0\, + Q => \read_fifo.tail_r_reg\(4), + R => \read_fifo.tail_r_reg[1]_1\ + ); +sent_col_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_cmd(0), + Q => sent_col_r2, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_byte_group_io is + port ( + mem_dq_out : out STD_LOGIC_VECTOR ( 10 downto 0 ); + oserdes_clk : in STD_LOGIC; + oserdes_clkdiv : in STD_LOGIC; + oserdes_dq : in STD_LOGIC_VECTOR ( 43 downto 0 ); + po_oserdes_rst : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_byte_group_io : entity is "mig_7series_v4_2_ddr_byte_group_io"; +end ddr3_mig_7series_v4_2_ddr_byte_group_io; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_byte_group_io is + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \output_[0].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[1].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[6].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[7].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[8].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[9].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; +begin +\output_[0].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(0), + D2 => oserdes_dq(1), + D3 => oserdes_dq(2), + D4 => oserdes_dq(3), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(0), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(40), + D2 => oserdes_dq(41), + D3 => oserdes_dq(42), + D4 => oserdes_dq(43), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(10), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[1].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(4), + D2 => oserdes_dq(5), + D3 => oserdes_dq(6), + D4 => oserdes_dq(7), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(1), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(8), + D2 => oserdes_dq(9), + D3 => oserdes_dq(10), + D4 => oserdes_dq(11), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(2), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(12), + D2 => oserdes_dq(13), + D3 => oserdes_dq(14), + D4 => oserdes_dq(15), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(3), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(16), + D2 => oserdes_dq(17), + D3 => oserdes_dq(18), + D4 => oserdes_dq(19), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(4), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(20), + D2 => oserdes_dq(21), + D3 => oserdes_dq(22), + D4 => oserdes_dq(23), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(5), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[6].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(24), + D2 => oserdes_dq(25), + D3 => oserdes_dq(26), + D4 => oserdes_dq(27), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(6), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[7].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(28), + D2 => oserdes_dq(29), + D3 => oserdes_dq(30), + D4 => oserdes_dq(31), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(7), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[8].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(32), + D2 => oserdes_dq(33), + D3 => oserdes_dq(34), + D4 => oserdes_dq(35), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(8), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[9].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(36), + D2 => oserdes_dq(37), + D3 => oserdes_dq(38), + D4 => oserdes_dq(39), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(9), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ is + port ( + mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 ); + oserdes_clk : in STD_LOGIC; + oserdes_clkdiv : in STD_LOGIC; + oserdes_dq : in STD_LOGIC_VECTOR ( 47 downto 0 ); + po_oserdes_rst : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ : entity is "mig_7series_v4_2_ddr_byte_group_io"; +end \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized0\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ is + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \output_[0].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[10].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[11].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[1].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[2].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[3].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[4].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[5].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[6].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[7].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[8].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[9].oserdes_dq_.sdr.oserdes_dq_i\ : label is "PRIMITIVE"; +begin +\output_[0].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(0), + D2 => oserdes_dq(1), + D3 => oserdes_dq(2), + D4 => oserdes_dq(3), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(0), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[10].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(40), + D2 => oserdes_dq(41), + D3 => oserdes_dq(42), + D4 => oserdes_dq(43), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(10), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[11].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(44), + D2 => oserdes_dq(45), + D3 => oserdes_dq(46), + D4 => oserdes_dq(47), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(11), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[1].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(4), + D2 => oserdes_dq(5), + D3 => oserdes_dq(6), + D4 => oserdes_dq(7), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(1), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[2].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(8), + D2 => oserdes_dq(9), + D3 => oserdes_dq(10), + D4 => oserdes_dq(11), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(2), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[3].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(12), + D2 => oserdes_dq(13), + D3 => oserdes_dq(14), + D4 => oserdes_dq(15), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(3), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[4].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(16), + D2 => oserdes_dq(17), + D3 => oserdes_dq(18), + D4 => oserdes_dq(19), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(4), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[5].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(20), + D2 => oserdes_dq(21), + D3 => oserdes_dq(22), + D4 => oserdes_dq(23), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(5), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[6].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(24), + D2 => oserdes_dq(25), + D3 => oserdes_dq(26), + D4 => oserdes_dq(27), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(6), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[7].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(28), + D2 => oserdes_dq(29), + D3 => oserdes_dq(30), + D4 => oserdes_dq(31), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(7), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[8].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(32), + D2 => oserdes_dq(33), + D3 => oserdes_dq(34), + D4 => oserdes_dq(35), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(8), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +\output_[9].oserdes_dq_.sdr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "SDR", + DATA_RATE_TQ => "SDR", + DATA_WIDTH => 4, + INIT_OQ => '0', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '0', + SRVAL_TQ => '1', + TBYTE_CTL => "FALSE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 1 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => oserdes_dq(36), + D2 => oserdes_dq(37), + D3 => oserdes_dq(38), + D4 => oserdes_dq(39), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(9), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED\, + TBYTEOUT => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ is + port ( + D1 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D3 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D8 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D9 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); + mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 ); + out_dqs_0 : out STD_LOGIC; + ts_dqs_0 : out STD_LOGIC; + idelay_ld_rst : out STD_LOGIC; + CLK : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC; + mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); + idelay_inc : in STD_LOGIC; + LD0 : in STD_LOGIC; + idelay_ld_rst_reg_0 : in STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + iserdes_clkdiv : in STD_LOGIC; + oserdes_clk : in STD_LOGIC; + oserdes_clkdiv : in STD_LOGIC; + po_oserdes_rst : in STD_LOGIC; + DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 ); + of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 ); + oserdes_clk_delayed : in STD_LOGIC; + DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 ); + CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ : entity is "mig_7series_v4_2_ddr_byte_group_io"; +end \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized1\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ is + signal data_in_dly_1 : STD_LOGIC; + signal data_in_dly_2 : STD_LOGIC; + signal data_in_dly_3 : STD_LOGIC; + signal data_in_dly_5 : STD_LOGIC; + signal data_in_dly_6 : STD_LOGIC; + signal data_in_dly_7 : STD_LOGIC; + signal data_in_dly_8 : STD_LOGIC; + signal data_in_dly_9 : STD_LOGIC; + signal \^idelay_ld_rst\ : STD_LOGIC; + signal idelay_ld_rst_i_1_n_0 : STD_LOGIC; + signal rst_r3_reg_srl3_n_0 : STD_LOGIC; + signal rst_r4 : STD_LOGIC; + signal tbyte_out : STD_LOGIC; + signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC; + signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE"; + attribute \__SRVAL\ : string; + attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE"; + attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE"; + attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE"; + attribute BOX_TYPE of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D : integer; + attribute SIM_DELAY_D of \input_[1].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[1].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED : string; + attribute OPT_MODIFIED of \input_[1].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[3].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[3].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[3].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[3].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute srl_name : string; + attribute srl_name of rst_r3_reg_srl3 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/rst_r3_reg_srl3 "; + attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE"; +begin + idelay_ld_rst <= \^idelay_ld_rst\; +\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR + generic map( + DDR_CLK_EDGE => "SAME_EDGE", + INIT => '0', + IS_C_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + SRTYPE => "SYNC" + ) + port map ( + C => oserdes_clk_delayed, + CE => '1', + D1 => DQSBUS(0), + D2 => DQSBUS(1), + Q => out_dqs_0, + R => '0', + S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ + ); +\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR + generic map( + DDR_CLK_EDGE => "SAME_EDGE", + INIT => '0', + IS_C_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + SRTYPE => "SYNC" + ) + port map ( + C => oserdes_clk_delayed, + CE => '1', + D1 => CTSBUS(0), + D2 => CTSBUS(0), + Q => ts_dqs_0, + R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\, + S => '0' + ); +idelay_ld_rst_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => rst_r4, + I1 => \^idelay_ld_rst\, + I2 => idelay_ld_rst_reg_0, + O => idelay_ld_rst_i_1_n_0 + ); +idelay_ld_rst_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_ld_rst_i_1_n_0, + Q => \^idelay_ld_rst\, + R => '0' + ); +\input_[1].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_1, + IDATAIN => mem_dq_in(0), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[1].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(0), + DDLY => data_in_dly_1, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D1(3), + Q2 => D1(2), + Q3 => D1(1), + Q4 => D1(0), + Q5 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_2, + IDATAIN => mem_dq_in(1), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(1), + DDLY => data_in_dly_2, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D2(3), + Q2 => D2(2), + Q3 => D2(1), + Q4 => D2(0), + Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[3].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_3, + IDATAIN => mem_dq_in(2), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[3].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(2), + DDLY => data_in_dly_3, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D3(3), + Q2 => D3(2), + Q3 => D3(1), + Q4 => D3(0), + Q5 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_5, + IDATAIN => mem_dq_in(3), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(3), + DDLY => data_in_dly_5, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D5(3), + Q2 => D5(2), + Q3 => D5(1), + Q4 => D5(0), + Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_6, + IDATAIN => mem_dq_in(4), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(4), + DDLY => data_in_dly_6, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D6(3), + Q2 => D6(2), + Q3 => D6(1), + Q4 => D6(0), + Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_7, + IDATAIN => mem_dq_in(5), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(5), + DDLY => data_in_dly_7, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D7(3), + Q2 => D7(2), + Q3 => D7(1), + Q4 => D7(0), + Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_8, + IDATAIN => mem_dq_in(6), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(6), + DDLY => data_in_dly_8, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D8(3), + Q2 => D8(2), + Q3 => D8(1), + Q4 => D8(0), + Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_9, + IDATAIN => mem_dq_in(7), + INC => idelay_inc, + LD => LD0, + LDPIPEEN => '0', + REGRST => idelay_ld_rst_reg_0 + ); +\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0, + CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(7), + DDLY => data_in_dly_9, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D9(3), + Q2 => D9(2), + Q3 => D9(1), + Q4 => D9(0), + Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(0), + D2 => of_dqbus(1), + D3 => of_dqbus(2), + D4 => of_dqbus(3), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(0), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(0) + ); +\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(4), + D2 => of_dqbus(5), + D3 => of_dqbus(6), + D4 => of_dqbus(7), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(1), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(1) + ); +\output_[3].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(8), + D2 => of_dqbus(9), + D3 => of_dqbus(10), + D4 => of_dqbus(11), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(2), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(2) + ); +\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(12), + D2 => of_dqbus(13), + D3 => of_dqbus(14), + D4 => of_dqbus(15), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(3), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(3) + ); +\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(16), + D2 => of_dqbus(17), + D3 => of_dqbus(18), + D4 => of_dqbus(19), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(4), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(4) + ); +\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(20), + D2 => of_dqbus(21), + D3 => of_dqbus(22), + D4 => of_dqbus(23), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(5), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(5) + ); +\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(24), + D2 => of_dqbus(25), + D3 => of_dqbus(26), + D4 => of_dqbus(27), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(6), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(6) + ); +\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(28), + D2 => of_dqbus(29), + D3 => of_dqbus(30), + D4 => of_dqbus(31), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(7), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(7) + ); +\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(32), + D2 => of_dqbus(33), + D3 => of_dqbus(34), + D4 => of_dqbus(35), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(8), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(8) + ); +rst_r3_reg_srl3: unisim.vcomponents.SRL16E + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => idelay_ld_rst_reg_0, + Q => rst_r3_reg_srl3_n_0 + ); +rst_r4_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rst_r3_reg_srl3_n_0, + Q => rst_r4, + R => '0' + ); +\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "TRUE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => '0', + D2 => '0', + D3 => '0', + D4 => '0', + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\, + OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\, + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\, + T1 => DTSBUS(0), + T2 => DTSBUS(0), + T3 => DTSBUS(1), + T4 => DTSBUS(1), + TBYTEIN => tbyte_out, + TBYTEOUT => tbyte_out, + TCE => '1', + TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\, + TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ is + port ( + D0 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D5 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D7 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D8 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D9 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); + mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 ); + out_dqs_1 : out STD_LOGIC; + ts_dqs_1 : out STD_LOGIC; + CLK : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC; + mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); + idelay_inc : in STD_LOGIC; + LD0_0 : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq_1\ : in STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + iserdes_clkdiv : in STD_LOGIC; + oserdes_clk : in STD_LOGIC; + oserdes_clkdiv : in STD_LOGIC; + po_oserdes_rst : in STD_LOGIC; + DTSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 ); + of_dqbus : in STD_LOGIC_VECTOR ( 35 downto 0 ); + oserdes_clk_delayed : in STD_LOGIC; + DQSBUS : in STD_LOGIC_VECTOR ( 1 downto 0 ); + CTSBUS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ : entity is "mig_7series_v4_2_ddr_byte_group_io"; +end \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized2\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ is + signal data_in_dly_0 : STD_LOGIC; + signal data_in_dly_2 : STD_LOGIC; + signal data_in_dly_4 : STD_LOGIC; + signal data_in_dly_5 : STD_LOGIC; + signal data_in_dly_6 : STD_LOGIC; + signal data_in_dly_7 : STD_LOGIC; + signal data_in_dly_8 : STD_LOGIC; + signal data_in_dly_9 : STD_LOGIC; + signal tbyte_out : STD_LOGIC; + signal \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ : STD_LOGIC; + signal \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\ : STD_LOGIC; + signal \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \dqs_gen.oddr_dqs\ : label is "PRIMITIVE"; + attribute \__SRVAL\ : string; + attribute \__SRVAL\ of \dqs_gen.oddr_dqs\ : label is "FALSE"; + attribute BOX_TYPE of \dqs_gen.oddr_dqsts\ : label is "PRIMITIVE"; + attribute \__SRVAL\ of \dqs_gen.oddr_dqsts\ : label is "TRUE"; + attribute BOX_TYPE of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D : integer; + attribute SIM_DELAY_D of \input_[0].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[0].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED : string; + attribute OPT_MODIFIED of \input_[0].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[2].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[2].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[2].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[4].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[4].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[4].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[5].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[5].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[5].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[6].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[6].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[6].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[7].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[7].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[7].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[8].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[8].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[8].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "PRIMITIVE"; + attribute IODELAY_GROUP of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is "DDR3_IODELAY_MIG0"; + attribute SIM_DELAY_D of \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : label is 0; + attribute BOX_TYPE of \input_[9].iserdes_dq_.iserdesdq\ : label is "PRIMITIVE"; + attribute OPT_MODIFIED of \input_[9].iserdes_dq_.iserdesdq\ : label is "MLO"; + attribute BOX_TYPE of \output_[0].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[1].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[2].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[4].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[5].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[6].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[7].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[8].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \output_[9].oserdes_dq_.ddr.oserdes_dq_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \slave_ts.oserdes_slave_ts\ : label is "PRIMITIVE"; +begin +\dqs_gen.oddr_dqs\: unisim.vcomponents.ODDR + generic map( + DDR_CLK_EDGE => "SAME_EDGE", + INIT => '0', + IS_C_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + SRTYPE => "SYNC" + ) + port map ( + C => oserdes_clk_delayed, + CE => '1', + D1 => DQSBUS(0), + D2 => DQSBUS(1), + Q => out_dqs_1, + R => '0', + S => \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED\ + ); +\dqs_gen.oddr_dqsts\: unisim.vcomponents.ODDR + generic map( + DDR_CLK_EDGE => "SAME_EDGE", + INIT => '0', + IS_C_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + SRTYPE => "SYNC" + ) + port map ( + C => oserdes_clk_delayed, + CE => '1', + D1 => CTSBUS(0), + D2 => CTSBUS(0), + Q => ts_dqs_1, + R => \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED\, + S => '0' + ); +\input_[0].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_0, + IDATAIN => mem_dq_in(0), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[0].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(0), + DDLY => data_in_dly_0, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D0(3), + Q2 => D0(2), + Q3 => D0(1), + Q4 => D0(0), + Q5 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[2].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_2, + IDATAIN => mem_dq_in(1), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[2].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(1), + DDLY => data_in_dly_2, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D2(3), + Q2 => D2(2), + Q3 => D2(1), + Q4 => D2(0), + Q5 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[4].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_4, + IDATAIN => mem_dq_in(2), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[4].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(2), + DDLY => data_in_dly_4, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D4(3), + Q2 => D4(2), + Q3 => D4(1), + Q4 => D4(0), + Q5 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[5].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_5, + IDATAIN => mem_dq_in(3), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[5].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(3), + DDLY => data_in_dly_5, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D5(3), + Q2 => D5(2), + Q3 => D5(1), + Q4 => D5(0), + Q5 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[6].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_6, + IDATAIN => mem_dq_in(4), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[6].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(4), + DDLY => data_in_dly_6, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D6(3), + Q2 => D6(2), + Q3 => D6(1), + Q4 => D6(0), + Q5 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[7].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_7, + IDATAIN => mem_dq_in(5), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[7].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(5), + DDLY => data_in_dly_7, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D7(3), + Q2 => D7(2), + Q3 => D7(1), + Q4 => D7(0), + Q5 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[8].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_8, + IDATAIN => mem_dq_in(6), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[8].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(6), + DDLY => data_in_dly_8, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D8(3), + Q2 => D8(2), + Q3 => D8(1), + Q4 => D8(0), + Q5 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\input_[9].iserdes_dq_.idelay_dq.idelaye2\: unisim.vcomponents.IDELAYE2 + generic map( + CINVCTRL_SEL => "FALSE", + DELAY_SRC => "IDATAIN", + HIGH_PERFORMANCE_MODE => "TRUE", + IDELAY_TYPE => "VARIABLE", + IDELAY_VALUE => 0, + IS_C_INVERTED => '0', + IS_DATAIN_INVERTED => '0', + IS_IDATAIN_INVERTED => '0', + PIPE_SEL => "FALSE", + REFCLK_FREQUENCY => 200.000000, + SIGNAL_PATTERN => "DATA" + ) + port map ( + C => CLK, + CE => \input_[9].iserdes_dq_.iserdesdq_0\, + CINVCTRL => '0', + CNTVALUEIN(4 downto 0) => B"00000", + CNTVALUEOUT(4 downto 0) => \NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED\(4 downto 0), + DATAIN => '0', + DATAOUT => data_in_dly_9, + IDATAIN => mem_dq_in(7), + INC => idelay_inc, + LD => LD0_0, + LDPIPEEN => '0', + REGRST => \input_[9].iserdes_dq_.iserdesdq_1\ + ); +\input_[9].iserdes_dq_.iserdesdq\: unisim.vcomponents.ISERDESE2 + generic map( + DATA_RATE => "DDR", + DATA_WIDTH => 4, + DYN_CLKDIV_INV_EN => "FALSE", + DYN_CLK_INV_EN => "FALSE", + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "MEMORY_DDR3", + IOBDELAY => "IFD", + IS_CLKB_INVERTED => '1', + IS_CLKDIVP_INVERTED => '0', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D_INVERTED => '0', + IS_OCLKB_INVERTED => '0', + IS_OCLK_INVERTED => '0', + NUM_CE => 2, + OFB_USED => "FALSE", + SERDES_MODE => "MASTER", + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' + ) + port map ( + BITSLIP => '0', + CE1 => '1', + CE2 => '1', + CLK => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + CLKB => CLKB0_4, + CLKDIV => \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED\, + CLKDIVP => iserdes_clkdiv, + D => mem_dq_in(7), + DDLY => data_in_dly_9, + DYNCLKDIVSEL => '0', + DYNCLKSEL => '0', + O => \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED\, + OCLK => oserdes_clk, + OCLKB => \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED\, + OFB => \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED\, + Q1 => D9(3), + Q2 => D9(2), + Q3 => D9(1), + Q4 => D9(0), + Q5 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED\, + Q6 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED\, + Q7 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED\, + Q8 => \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED\, + RST => '0', + SHIFTIN1 => '0', + SHIFTIN2 => '0', + SHIFTOUT1 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED\ + ); +\output_[0].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(0), + D2 => of_dqbus(1), + D3 => of_dqbus(2), + D4 => of_dqbus(3), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(0), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(0) + ); +\output_[1].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(4), + D2 => of_dqbus(5), + D3 => of_dqbus(6), + D4 => of_dqbus(7), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(1), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(1) + ); +\output_[2].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(8), + D2 => of_dqbus(9), + D3 => of_dqbus(10), + D4 => of_dqbus(11), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(2), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(2) + ); +\output_[4].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(12), + D2 => of_dqbus(13), + D3 => of_dqbus(14), + D4 => of_dqbus(15), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(3), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(3) + ); +\output_[5].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(16), + D2 => of_dqbus(17), + D3 => of_dqbus(18), + D4 => of_dqbus(19), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(4), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(4) + ); +\output_[6].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(20), + D2 => of_dqbus(21), + D3 => of_dqbus(22), + D4 => of_dqbus(23), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(5), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(5) + ); +\output_[7].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(24), + D2 => of_dqbus(25), + D3 => of_dqbus(26), + D4 => of_dqbus(27), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(6), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(6) + ); +\output_[8].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(28), + D2 => of_dqbus(29), + D3 => of_dqbus(30), + D4 => of_dqbus(31), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(7), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(7) + ); +\output_[9].oserdes_dq_.ddr.oserdes_dq_i\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "FALSE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => of_dqbus(32), + D2 => of_dqbus(33), + D3 => of_dqbus(34), + D4 => of_dqbus(35), + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED\, + OQ => mem_dq_out(8), + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED\, + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TBYTEIN => tbyte_out, + TBYTEOUT => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED\, + TCE => '1', + TFB => \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED\, + TQ => mem_dq_ts(8) + ); +\slave_ts.oserdes_slave_ts\: unisim.vcomponents.OSERDESE2 + generic map( + DATA_RATE_OQ => "DDR", + DATA_RATE_TQ => "DDR", + DATA_WIDTH => 4, + INIT_OQ => '1', + INIT_TQ => '1', + IS_CLKDIV_INVERTED => '0', + IS_CLK_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + IS_D3_INVERTED => '0', + IS_D4_INVERTED => '0', + IS_D5_INVERTED => '0', + IS_D6_INVERTED => '0', + IS_D7_INVERTED => '0', + IS_D8_INVERTED => '0', + IS_T1_INVERTED => '0', + IS_T2_INVERTED => '0', + IS_T3_INVERTED => '0', + IS_T4_INVERTED => '0', + SERDES_MODE => "MASTER", + SRVAL_OQ => '1', + SRVAL_TQ => '1', + TBYTE_CTL => "TRUE", + TBYTE_SRC => "TRUE", + TRISTATE_WIDTH => 4 + ) + port map ( + CLK => oserdes_clk, + CLKDIV => oserdes_clkdiv, + D1 => '0', + D2 => '0', + D3 => '0', + D4 => '0', + D5 => '0', + D6 => '0', + D7 => '0', + D8 => '0', + OCE => '1', + OFB => \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED\, + OQ => \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED\, + RST => po_oserdes_rst, + SHIFTIN1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED\, + SHIFTIN2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED\, + SHIFTOUT1 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED\, + SHIFTOUT2 => \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED\, + T1 => DTSBUS(0), + T2 => DTSBUS(0), + T3 => DTSBUS(1), + T4 => DTSBUS(1), + TBYTEIN => tbyte_out, + TBYTEOUT => tbyte_out, + TCE => '1', + TFB => \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED\, + TQ => \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_if_post_fifo is + port ( + \rd_ptr_timing_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \my_empty_reg[4]_rep__1_0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + rd_data_en : out STD_LOGIC; + \my_empty_reg[0]_0\ : out STD_LOGIC; + \my_empty_reg[0]_1\ : out STD_LOGIC; + \my_empty_reg[0]_2\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \my_empty_reg[3]_0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + p_1_in : out STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC; + DIC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[4]_rep__2_0\ : in STD_LOGIC; + \my_empty_reg[4]_rep__2_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg_0_sp_1\ : in STD_LOGIC; + \not_strict_mode.app_rd_data[127]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[8]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[73]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[75]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[79]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[91]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[93]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[105]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[109]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[111]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[121]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[123]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + ififo_rst : in STD_LOGIC; + CLK : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_if_post_fifo : entity is "mig_7series_v4_2_ddr_if_post_fifo"; +end ddr3_mig_7series_v4_2_ddr_if_post_fifo; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_if_post_fifo is + signal my_empty : STD_LOGIC_VECTOR ( 4 downto 1 ); + signal my_empty1 : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \my_empty[0]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[1]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[1]_i_2_n_0\ : STD_LOGIC; + signal \my_empty[2]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[3]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[4]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[4]_i_2__0_n_0\ : STD_LOGIC; + signal \^my_empty_reg[0]_0\ : STD_LOGIC; + signal \^my_empty_reg[3]_0\ : STD_LOGIC; + signal \my_empty_reg[4]_rep__0_n_0\ : STD_LOGIC; + signal \^my_empty_reg[4]_rep__1_0\ : STD_LOGIC; + signal \my_empty_reg[4]_rep__2_n_0\ : STD_LOGIC; + signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC; + signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \my_full[0]_i_1_n_0\ : STD_LOGIC; + signal \my_full[0]_i_2__0_n_0\ : STD_LOGIC; + signal \my_full[1]_i_1_n_0\ : STD_LOGIC; + signal \my_full[1]_i_2_n_0\ : STD_LOGIC; + signal \my_full[1]_i_3_n_0\ : STD_LOGIC; + signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \rd_ptr[0]_i_1__0_n_0\ : STD_LOGIC; + signal \rd_ptr[1]_i_1__0_n_0\ : STD_LOGIC; + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of rd_ptr_timing : signal is "true"; + attribute syn_maxfan : string; + attribute syn_maxfan of rd_ptr_timing : signal is "10"; + signal \rd_ptr_timing[0]_i_1__1_n_0\ : STD_LOGIC; + signal \rd_ptr_timing[1]_i_1__1_n_0\ : STD_LOGIC; + signal \read_fifo.tail_r_reg_0_sn_1\ : STD_LOGIC; + signal \wr_ptr[0]_i_1__1_n_0\ : STD_LOGIC; + signal \wr_ptr[1]_i_1__1_n_0\ : STD_LOGIC; + signal \wr_ptr[1]_i_2_n_0\ : STD_LOGIC; + signal \^wr_ptr_reg[0]_0\ : STD_LOGIC; + signal \^wr_ptr_reg[1]_0\ : STD_LOGIC; + attribute ORIG_CELL_NAME : string; + attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED : integer; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__0\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__1\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__1\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__2\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__2\ : label is "my_empty_reg[4]"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \my_full[0]_i_2__0\ : label is "soft_lutpair481"; + attribute SOFT_HLUTNM of \rd_ptr[0]_i_1__0\ : label is "soft_lutpair482"; + attribute SOFT_HLUTNM of \rd_ptr[1]_i_1__0\ : label is "soft_lutpair482"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2__0\ : label is "soft_lutpair481"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; +begin + \my_empty_reg[0]_0\ <= \^my_empty_reg[0]_0\; + \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\; + \my_empty_reg[4]_rep__1_0\ <= \^my_empty_reg[4]_rep__1_0\; + \rd_ptr_timing_reg[1]_0\(1 downto 0) <= rd_ptr_timing(1 downto 0); + \read_fifo.tail_r_reg_0_sn_1\ <= \read_fifo.tail_r_reg_0_sp_1\; + \wr_ptr_reg[0]_0\ <= \^wr_ptr_reg[0]_0\; + \wr_ptr_reg[1]_0\ <= \^wr_ptr_reg[1]_0\; +\gen_mux_rd[0].mux_rd_fall0_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(1), + I1 => \not_strict_mode.app_rd_data_reg[127]\(1), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => DIA(0), + O => \gen_mux_rd[0].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[0].mux_rd_fall1_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(3), + I1 => \not_strict_mode.app_rd_data_reg[127]\(3), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(0), + O => \gen_mux_rd[0].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[0].mux_rd_fall2_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(5), + I1 => \not_strict_mode.app_rd_data_reg[127]\(5), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(0), + O => \gen_mux_rd[0].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[0].mux_rd_fall3_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(7), + I1 => \not_strict_mode.app_rd_data_reg[127]\(7), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(0), + O => \gen_mux_rd[0].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[0].mux_rd_rise0_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(0), + I1 => \not_strict_mode.app_rd_data_reg[127]\(0), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => DIC(0), + O => \gen_mux_rd[0].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[0].mux_rd_rise1_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(2), + I1 => \not_strict_mode.app_rd_data_reg[127]\(2), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => DIB(0), + O => \gen_mux_rd[0].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[0].mux_rd_rise2_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(4), + I1 => \not_strict_mode.app_rd_data_reg[127]\(4), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(0), + O => \gen_mux_rd[0].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[0].mux_rd_rise3_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(6), + I1 => \not_strict_mode.app_rd_data_reg[127]\(6), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(0), + O => \gen_mux_rd[0].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_fall0_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(41), + I1 => \not_strict_mode.app_rd_data_reg[127]\(41), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => DIA(1), + O => \gen_mux_rd[1].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_fall1_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(43), + I1 => \not_strict_mode.app_rd_data_reg[127]\(43), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1), + O => \gen_mux_rd[1].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_fall2_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(45), + I1 => \not_strict_mode.app_rd_data_reg[127]\(45), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1), + O => \gen_mux_rd[1].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_fall3_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(47), + I1 => \not_strict_mode.app_rd_data_reg[127]\(47), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1), + O => \gen_mux_rd[1].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_rise0_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(40), + I1 => \not_strict_mode.app_rd_data_reg[127]\(40), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => DIC(1), + O => \gen_mux_rd[1].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_rise1_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(42), + I1 => \not_strict_mode.app_rd_data_reg[127]\(42), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => DIB(1), + O => \gen_mux_rd[1].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_rise2_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(44), + I1 => \not_strict_mode.app_rd_data_reg[127]\(44), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1), + O => \gen_mux_rd[1].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[1].mux_rd_rise3_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(46), + I1 => \not_strict_mode.app_rd_data_reg[127]\(46), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1), + O => \gen_mux_rd[1].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_fall0_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(9), + I1 => \not_strict_mode.app_rd_data_reg[127]\(9), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_fall1_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(11), + I1 => \not_strict_mode.app_rd_data_reg[127]\(11), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_fall2_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(13), + I1 => \not_strict_mode.app_rd_data_reg[127]\(13), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_fall3_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(15), + I1 => \not_strict_mode.app_rd_data_reg[127]\(15), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_rise0_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(8), + I1 => \not_strict_mode.app_rd_data_reg[127]\(8), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_rise1_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(10), + I1 => \not_strict_mode.app_rd_data_reg[127]\(10), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_rise2_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(12), + I1 => \not_strict_mode.app_rd_data_reg[127]\(12), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[2].mux_rd_rise3_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(14), + I1 => \not_strict_mode.app_rd_data_reg[127]\(14), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\(0), + O => \gen_mux_rd[2].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_fall0_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(17), + I1 => \not_strict_mode.app_rd_data_reg[127]\(17), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_fall1_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(19), + I1 => \not_strict_mode.app_rd_data_reg[127]\(19), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_fall2_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(21), + I1 => \not_strict_mode.app_rd_data_reg[127]\(21), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_fall3_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(23), + I1 => \not_strict_mode.app_rd_data_reg[127]\(23), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_rise0_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(16), + I1 => \not_strict_mode.app_rd_data_reg[127]\(16), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_rise1_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(18), + I1 => \not_strict_mode.app_rd_data_reg[127]\(18), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_rise2_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(20), + I1 => \not_strict_mode.app_rd_data_reg[127]\(20), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[3].mux_rd_rise3_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(22), + I1 => \not_strict_mode.app_rd_data_reg[127]\(22), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\(1), + O => \gen_mux_rd[3].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_fall0_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(33), + I1 => \not_strict_mode.app_rd_data_reg[127]\(33), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_fall1_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(35), + I1 => \not_strict_mode.app_rd_data_reg[127]\(35), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_fall2_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(37), + I1 => \not_strict_mode.app_rd_data_reg[127]\(37), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_fall3_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(39), + I1 => \not_strict_mode.app_rd_data_reg[127]\(39), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_rise0_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(32), + I1 => \not_strict_mode.app_rd_data_reg[127]\(32), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_rise1_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(34), + I1 => \not_strict_mode.app_rd_data_reg[127]\(34), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_rise2_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(36), + I1 => \not_strict_mode.app_rd_data_reg[127]\(36), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[4].mux_rd_rise3_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(38), + I1 => \not_strict_mode.app_rd_data_reg[127]\(38), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(0), + O => \gen_mux_rd[4].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_fall0_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(49), + I1 => \not_strict_mode.app_rd_data_reg[127]\(49), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_fall1_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(51), + I1 => \not_strict_mode.app_rd_data_reg[127]\(51), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_fall2_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(53), + I1 => \not_strict_mode.app_rd_data_reg[127]\(53), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_fall3_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(55), + I1 => \not_strict_mode.app_rd_data_reg[127]\(55), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_rise0_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(48), + I1 => \not_strict_mode.app_rd_data_reg[127]\(48), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_rise1_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(50), + I1 => \not_strict_mode.app_rd_data_reg[127]\(50), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_rise2_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(52), + I1 => \not_strict_mode.app_rd_data_reg[127]\(52), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[5].mux_rd_rise3_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(54), + I1 => \not_strict_mode.app_rd_data_reg[127]\(54), + I2 => \^my_empty_reg[4]_rep__1_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1), + O => \gen_mux_rd[5].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_fall0_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(25), + I1 => \not_strict_mode.app_rd_data_reg[127]\(25), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_fall1_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(27), + I1 => \not_strict_mode.app_rd_data_reg[127]\(27), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_fall2_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(29), + I1 => \not_strict_mode.app_rd_data_reg[127]\(29), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_fall3_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(31), + I1 => \not_strict_mode.app_rd_data_reg[127]\(31), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_rise0_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(24), + I1 => \not_strict_mode.app_rd_data_reg[127]\(24), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_rise1_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(26), + I1 => \not_strict_mode.app_rd_data_reg[127]\(26), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_rise2_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(28), + I1 => \not_strict_mode.app_rd_data_reg[127]\(28), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[6].mux_rd_rise3_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(30), + I1 => \not_strict_mode.app_rd_data_reg[127]\(30), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\(0), + O => \gen_mux_rd[6].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_fall0_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(57), + I1 => \not_strict_mode.app_rd_data_reg[127]\(57), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_fall1_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(59), + I1 => \not_strict_mode.app_rd_data_reg[127]\(59), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_fall2_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(61), + I1 => \not_strict_mode.app_rd_data_reg[127]\(61), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_fall3_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(63), + I1 => \not_strict_mode.app_rd_data_reg[127]\(63), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_rise0_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(56), + I1 => \not_strict_mode.app_rd_data_reg[127]\(56), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_rise1_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(58), + I1 => \not_strict_mode.app_rd_data_reg[127]\(58), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_rise2_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(60), + I1 => \not_strict_mode.app_rd_data_reg[127]\(60), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd[7].mux_rd_rise3_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACFFAC00" + ) + port map ( + I0 => Q(62), + I1 => \not_strict_mode.app_rd_data_reg[127]\(62), + I2 => \my_empty_reg[4]_rep__0_n_0\, + I3 => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + I4 => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\(1), + O => \gen_mux_rd[7].mux_rd_rise3_r_reg0\ + ); +mem_reg_0_3_0_5_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000078F" + ) + port map ( + I0 => if_empty_r_0(0), + I1 => \my_empty_reg[4]_rep__2_1\(1), + I2 => my_empty(2), + I3 => my_full(0), + I4 => \my_empty_reg[4]_rep__2_0\, + O => p_1_in + ); +\my_empty[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => \^my_empty_reg[0]_0\, + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2_n_0\, + I4 => my_empty(1), + I5 => \my_empty[4]_i_2__0_n_0\, + O => \my_empty[0]_i_1_n_0\ + ); +\my_empty[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA00411400" + ) + port map ( + I0 => \my_empty[1]_i_2_n_0\, + I1 => \^wr_ptr_reg[1]_0\, + I2 => rd_ptr(1), + I3 => rd_ptr(0), + I4 => \^wr_ptr_reg[0]_0\, + I5 => my_empty(1), + O => \my_empty[1]_i_1_n_0\ + ); +\my_empty[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFBFFFBFFFFFEAFF" + ) + port map ( + I0 => my_full(1), + I1 => if_empty_r_0(0), + I2 => \my_empty_reg[4]_rep__2_1\(1), + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => \^my_empty_reg[3]_0\, + I5 => my_empty(1), + O => \my_empty[1]_i_2_n_0\ + ); +\my_empty[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => my_empty(2), + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2_n_0\, + I4 => my_empty(1), + I5 => \my_empty[4]_i_2__0_n_0\, + O => \my_empty[2]_i_1_n_0\ + ); +\my_empty[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => \^my_empty_reg[3]_0\, + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2_n_0\, + I4 => my_empty(1), + I5 => \my_empty[4]_i_2__0_n_0\, + O => \my_empty[3]_i_1_n_0\ + ); +\my_empty[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => \my_empty_reg[4]_rep_n_0\, + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2_n_0\, + I4 => my_empty(1), + I5 => \my_empty[4]_i_2__0_n_0\, + O => \my_empty[4]_i_1_n_0\ + ); +\my_empty[4]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000960" + ) + port map ( + I0 => \^wr_ptr_reg[1]_0\, + I1 => rd_ptr(1), + I2 => rd_ptr(0), + I3 => \^wr_ptr_reg[0]_0\, + I4 => my_empty(1), + O => \my_empty[4]_i_2__0_n_0\ + ); +\my_empty_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[0]_i_1_n_0\, + Q => \^my_empty_reg[0]_0\, + S => ififo_rst + ); +\my_empty_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[1]_i_1_n_0\, + Q => my_empty(1), + S => ififo_rst + ); +\my_empty_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[2]_i_1_n_0\, + Q => my_empty(2), + S => ififo_rst + ); +\my_empty_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[3]_i_1_n_0\, + Q => \^my_empty_reg[3]_0\, + S => ififo_rst + ); +\my_empty_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[4]_i_1_n_0\, + Q => my_empty(4), + S => ififo_rst + ); +\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[4]_i_1_n_0\, + Q => \my_empty_reg[4]_rep_n_0\, + S => ififo_rst + ); +\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[4]_i_1_n_0\, + Q => \my_empty_reg[4]_rep__0_n_0\, + S => ififo_rst + ); +\my_empty_reg[4]_rep__1\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[4]_i_1_n_0\, + Q => \^my_empty_reg[4]_rep__1_0\, + S => ififo_rst + ); +\my_empty_reg[4]_rep__2\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_empty[4]_i_1_n_0\, + Q => \my_empty_reg[4]_rep__2_n_0\, + S => ififo_rst + ); +\my_full[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BAAAAAAB8AAAAAA8" + ) + port map ( + I0 => my_full(0), + I1 => my_empty(1), + I2 => my_full(1), + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => \wr_ptr[1]_i_2_n_0\, + I5 => \my_full[0]_i_2__0_n_0\, + O => \my_full[0]_i_1_n_0\ + ); +\my_full[0]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000960" + ) + port map ( + I0 => rd_ptr(1), + I1 => \^wr_ptr_reg[1]_0\, + I2 => \^wr_ptr_reg[0]_0\, + I3 => rd_ptr(0), + I4 => my_full(1), + O => \my_full[0]_i_2__0_n_0\ + ); +\my_full[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAFFFF" + ) + port map ( + I0 => my_full(1), + I1 => if_empty_r_0(0), + I2 => \my_empty_reg[4]_rep__2_1\(1), + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => my_empty(1), + O => \my_full[1]_i_1_n_0\ + ); +\my_full[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA00411400" + ) + port map ( + I0 => \my_full[1]_i_3_n_0\, + I1 => rd_ptr(1), + I2 => \^wr_ptr_reg[1]_0\, + I3 => \^wr_ptr_reg[0]_0\, + I4 => rd_ptr(0), + I5 => my_full(1), + O => \my_full[1]_i_2_n_0\ + ); +\my_full[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFFFFFEBFBFBF" + ) + port map ( + I0 => my_empty(1), + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => if_empty_r_0(0), + I4 => \my_empty_reg[4]_rep__2_1\(1), + I5 => \^my_empty_reg[3]_0\, + O => \my_full[1]_i_3_n_0\ + ); +\my_full_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_full[0]_i_1_n_0\, + Q => my_full(0), + R => ififo_rst + ); +\my_full_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \my_full[1]_i_2_n_0\, + Q => my_full(1), + R => ififo_rst + ); +\not_strict_mode.app_rd_data[104]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(6), + I1 => \not_strict_mode.app_rd_data_reg[127]\(6), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[105]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(48) + ); +\not_strict_mode.app_rd_data[105]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(46), + I1 => \not_strict_mode.app_rd_data_reg[127]\(46), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[105]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(49) + ); +\not_strict_mode.app_rd_data[106]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(14), + I1 => \not_strict_mode.app_rd_data_reg[127]\(14), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[107]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(50) + ); +\not_strict_mode.app_rd_data[107]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(22), + I1 => \not_strict_mode.app_rd_data_reg[127]\(22), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[107]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(51) + ); +\not_strict_mode.app_rd_data[108]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(38), + I1 => \not_strict_mode.app_rd_data_reg[127]\(38), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[109]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(52) + ); +\not_strict_mode.app_rd_data[109]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(54), + I1 => \not_strict_mode.app_rd_data_reg[127]\(54), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[109]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(53) + ); +\not_strict_mode.app_rd_data[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(8), + I1 => \not_strict_mode.app_rd_data_reg[127]\(8), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[11]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(2) + ); +\not_strict_mode.app_rd_data[110]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(30), + I1 => \not_strict_mode.app_rd_data_reg[127]\(30), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[111]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(54) + ); +\not_strict_mode.app_rd_data[111]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(62), + I1 => \not_strict_mode.app_rd_data_reg[127]\(62), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[111]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(55) + ); +\not_strict_mode.app_rd_data[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(16), + I1 => \not_strict_mode.app_rd_data_reg[127]\(16), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[11]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(3) + ); +\not_strict_mode.app_rd_data[120]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(7), + I1 => \not_strict_mode.app_rd_data_reg[127]\(7), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[121]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(56) + ); +\not_strict_mode.app_rd_data[121]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(47), + I1 => \not_strict_mode.app_rd_data_reg[127]\(47), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[121]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(57) + ); +\not_strict_mode.app_rd_data[122]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(15), + I1 => \not_strict_mode.app_rd_data_reg[127]\(15), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[123]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(58) + ); +\not_strict_mode.app_rd_data[123]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(23), + I1 => \not_strict_mode.app_rd_data_reg[127]\(23), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[123]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(59) + ); +\not_strict_mode.app_rd_data[124]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(39), + I1 => \not_strict_mode.app_rd_data_reg[127]\(39), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[125]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(60) + ); +\not_strict_mode.app_rd_data[125]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(55), + I1 => \not_strict_mode.app_rd_data_reg[127]\(55), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[125]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(61) + ); +\not_strict_mode.app_rd_data[126]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(31), + I1 => \not_strict_mode.app_rd_data_reg[127]\(31), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[127]_0\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(62) + ); +\not_strict_mode.app_rd_data[127]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(63), + I1 => \not_strict_mode.app_rd_data_reg[127]\(63), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[127]_0\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(63) + ); +\not_strict_mode.app_rd_data[127]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000007770000" + ) + port map ( + I0 => \^my_empty_reg[0]_0\, + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => \my_empty_reg[4]_rep__2_1\(0), + I3 => if_empty_r_0(0), + I4 => \read_fifo.tail_r_reg_0_sn_1\, + I5 => \not_strict_mode.app_rd_data[127]_i_2\(0), + O => rd_data_en + ); +\not_strict_mode.app_rd_data[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(32), + I1 => \not_strict_mode.app_rd_data_reg[127]\(32), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[13]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(4) + ); +\not_strict_mode.app_rd_data[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(48), + I1 => \not_strict_mode.app_rd_data_reg[127]\(48), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[13]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(5) + ); +\not_strict_mode.app_rd_data[14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(24), + I1 => \not_strict_mode.app_rd_data_reg[127]\(24), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[15]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(6) + ); +\not_strict_mode.app_rd_data[15]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(56), + I1 => \not_strict_mode.app_rd_data_reg[127]\(56), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[15]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(7) + ); +\not_strict_mode.app_rd_data[24]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(1), + I1 => \not_strict_mode.app_rd_data_reg[127]\(1), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[25]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(8) + ); +\not_strict_mode.app_rd_data[25]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(41), + I1 => \not_strict_mode.app_rd_data_reg[127]\(41), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[25]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(9) + ); +\not_strict_mode.app_rd_data[26]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(9), + I1 => \not_strict_mode.app_rd_data_reg[127]\(9), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[27]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(10) + ); +\not_strict_mode.app_rd_data[27]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(17), + I1 => \not_strict_mode.app_rd_data_reg[127]\(17), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[27]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(11) + ); +\not_strict_mode.app_rd_data[28]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(33), + I1 => \not_strict_mode.app_rd_data_reg[127]\(33), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[29]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(12) + ); +\not_strict_mode.app_rd_data[29]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(49), + I1 => \not_strict_mode.app_rd_data_reg[127]\(49), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[29]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(13) + ); +\not_strict_mode.app_rd_data[30]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(25), + I1 => \not_strict_mode.app_rd_data_reg[127]\(25), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[31]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(14) + ); +\not_strict_mode.app_rd_data[31]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(57), + I1 => \not_strict_mode.app_rd_data_reg[127]\(57), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[31]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(15) + ); +\not_strict_mode.app_rd_data[40]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(2), + I1 => \not_strict_mode.app_rd_data_reg[127]\(2), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[41]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(16) + ); +\not_strict_mode.app_rd_data[41]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(42), + I1 => \not_strict_mode.app_rd_data_reg[127]\(42), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[41]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(17) + ); +\not_strict_mode.app_rd_data[42]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(10), + I1 => \not_strict_mode.app_rd_data_reg[127]\(10), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[43]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(18) + ); +\not_strict_mode.app_rd_data[43]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(18), + I1 => \not_strict_mode.app_rd_data_reg[127]\(18), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[43]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(19) + ); +\not_strict_mode.app_rd_data[44]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(34), + I1 => \not_strict_mode.app_rd_data_reg[127]\(34), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[45]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(20) + ); +\not_strict_mode.app_rd_data[45]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(50), + I1 => \not_strict_mode.app_rd_data_reg[127]\(50), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[45]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(21) + ); +\not_strict_mode.app_rd_data[46]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(26), + I1 => \not_strict_mode.app_rd_data_reg[127]\(26), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[47]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(22) + ); +\not_strict_mode.app_rd_data[47]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(58), + I1 => \not_strict_mode.app_rd_data_reg[127]\(58), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[47]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(23) + ); +\not_strict_mode.app_rd_data[56]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(3), + I1 => \not_strict_mode.app_rd_data_reg[127]\(3), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[57]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(24) + ); +\not_strict_mode.app_rd_data[57]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(43), + I1 => \not_strict_mode.app_rd_data_reg[127]\(43), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[57]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(25) + ); +\not_strict_mode.app_rd_data[58]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(11), + I1 => \not_strict_mode.app_rd_data_reg[127]\(11), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[59]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(26) + ); +\not_strict_mode.app_rd_data[59]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(19), + I1 => \not_strict_mode.app_rd_data_reg[127]\(19), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[59]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(27) + ); +\not_strict_mode.app_rd_data[60]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(35), + I1 => \not_strict_mode.app_rd_data_reg[127]\(35), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[61]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(28) + ); +\not_strict_mode.app_rd_data[61]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(51), + I1 => \not_strict_mode.app_rd_data_reg[127]\(51), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[61]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(29) + ); +\not_strict_mode.app_rd_data[62]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(27), + I1 => \not_strict_mode.app_rd_data_reg[127]\(27), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[63]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(30) + ); +\not_strict_mode.app_rd_data[63]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(59), + I1 => \not_strict_mode.app_rd_data_reg[127]\(59), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[63]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(31) + ); +\not_strict_mode.app_rd_data[72]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(4), + I1 => \not_strict_mode.app_rd_data_reg[127]\(4), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[73]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(32) + ); +\not_strict_mode.app_rd_data[73]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(44), + I1 => \not_strict_mode.app_rd_data_reg[127]\(44), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[73]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(33) + ); +\not_strict_mode.app_rd_data[74]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(12), + I1 => \not_strict_mode.app_rd_data_reg[127]\(12), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[75]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(34) + ); +\not_strict_mode.app_rd_data[75]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(20), + I1 => \not_strict_mode.app_rd_data_reg[127]\(20), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[75]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(35) + ); +\not_strict_mode.app_rd_data[76]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(36), + I1 => \not_strict_mode.app_rd_data_reg[127]\(36), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[77]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(36) + ); +\not_strict_mode.app_rd_data[77]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(52), + I1 => \not_strict_mode.app_rd_data_reg[127]\(52), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[77]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(37) + ); +\not_strict_mode.app_rd_data[78]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(28), + I1 => \not_strict_mode.app_rd_data_reg[127]\(28), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[79]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(38) + ); +\not_strict_mode.app_rd_data[79]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(60), + I1 => \not_strict_mode.app_rd_data_reg[127]\(60), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[79]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(39) + ); +\not_strict_mode.app_rd_data[88]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(5), + I1 => \not_strict_mode.app_rd_data_reg[127]\(5), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[89]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(40) + ); +\not_strict_mode.app_rd_data[89]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(45), + I1 => \not_strict_mode.app_rd_data_reg[127]\(45), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[89]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(41) + ); +\not_strict_mode.app_rd_data[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(0), + I1 => \not_strict_mode.app_rd_data_reg[127]\(0), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[9]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(0) + ); +\not_strict_mode.app_rd_data[90]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(13), + I1 => \not_strict_mode.app_rd_data_reg[127]\(13), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[91]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(42) + ); +\not_strict_mode.app_rd_data[91]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(21), + I1 => \not_strict_mode.app_rd_data_reg[127]\(21), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[91]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(43) + ); +\not_strict_mode.app_rd_data[92]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(37), + I1 => \not_strict_mode.app_rd_data_reg[127]\(37), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[93]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(44) + ); +\not_strict_mode.app_rd_data[93]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(53), + I1 => \not_strict_mode.app_rd_data_reg[127]\(53), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[93]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(45) + ); +\not_strict_mode.app_rd_data[94]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(29), + I1 => \not_strict_mode.app_rd_data_reg[127]\(29), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[95]\(0), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(46) + ); +\not_strict_mode.app_rd_data[95]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(61), + I1 => \not_strict_mode.app_rd_data_reg[127]\(61), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[95]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(47) + ); +\not_strict_mode.app_rd_data[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(40), + I1 => \not_strict_mode.app_rd_data_reg[127]\(40), + I2 => my_empty(4), + I3 => \not_strict_mode.app_rd_data_reg[9]\(1), + I4 => \not_strict_mode.app_rd_data_reg[8]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(59), + I1 => \not_strict_mode.app_rd_data_reg[127]\(59), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(27), + I1 => \not_strict_mode.app_rd_data_reg[127]\(27), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(51), + I1 => \not_strict_mode.app_rd_data_reg[127]\(51), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(35), + I1 => \not_strict_mode.app_rd_data_reg[127]\(35), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(52), + I1 => \not_strict_mode.app_rd_data_reg[127]\(52), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(36), + I1 => \not_strict_mode.app_rd_data_reg[127]\(36), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(20), + I1 => \not_strict_mode.app_rd_data_reg[127]\(20), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(12), + I1 => \not_strict_mode.app_rd_data_reg[127]\(12), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(44), + I1 => \not_strict_mode.app_rd_data_reg[127]\(44), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(4), + I1 => \not_strict_mode.app_rd_data_reg[127]\(4), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(60), + I1 => \not_strict_mode.app_rd_data_reg[127]\(60), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(28), + I1 => \not_strict_mode.app_rd_data_reg[127]\(28), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(45), + I1 => \not_strict_mode.app_rd_data_reg[127]\(45), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(5), + I1 => \not_strict_mode.app_rd_data_reg[127]\(5), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(61), + I1 => \not_strict_mode.app_rd_data_reg[127]\(61), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(29), + I1 => \not_strict_mode.app_rd_data_reg[127]\(29), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(53), + I1 => \not_strict_mode.app_rd_data_reg[127]\(53), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(37), + I1 => \not_strict_mode.app_rd_data_reg[127]\(37), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(21), + I1 => \not_strict_mode.app_rd_data_reg[127]\(21), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(13), + I1 => \not_strict_mode.app_rd_data_reg[127]\(13), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(22), + I1 => \not_strict_mode.app_rd_data_reg[127]\(22), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(14), + I1 => \not_strict_mode.app_rd_data_reg[127]\(14), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(46), + I1 => \not_strict_mode.app_rd_data_reg[127]\(46), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(6), + I1 => \not_strict_mode.app_rd_data_reg[127]\(6), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(62), + I1 => \not_strict_mode.app_rd_data_reg[127]\(62), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(30), + I1 => \not_strict_mode.app_rd_data_reg[127]\(30), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(54), + I1 => \not_strict_mode.app_rd_data_reg[127]\(54), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(38), + I1 => \not_strict_mode.app_rd_data_reg[127]\(38), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(16), + I1 => \not_strict_mode.app_rd_data_reg[127]\(16), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(8), + I1 => \not_strict_mode.app_rd_data_reg[127]\(8), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(40), + I1 => \not_strict_mode.app_rd_data_reg[127]\(40), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(0), + I1 => \not_strict_mode.app_rd_data_reg[127]\(0), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(55), + I1 => \not_strict_mode.app_rd_data_reg[127]\(55), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(39), + I1 => \not_strict_mode.app_rd_data_reg[127]\(39), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(23), + I1 => \not_strict_mode.app_rd_data_reg[127]\(23), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(15), + I1 => \not_strict_mode.app_rd_data_reg[127]\(15), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(47), + I1 => \not_strict_mode.app_rd_data_reg[127]\(47), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(7), + I1 => \not_strict_mode.app_rd_data_reg[127]\(7), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(63), + I1 => \not_strict_mode.app_rd_data_reg[127]\(63), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(31), + I1 => \not_strict_mode.app_rd_data_reg[127]\(31), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(56), + I1 => \not_strict_mode.app_rd_data_reg[127]\(56), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(24), + I1 => \not_strict_mode.app_rd_data_reg[127]\(24), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(48), + I1 => \not_strict_mode.app_rd_data_reg[127]\(48), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(32), + I1 => \not_strict_mode.app_rd_data_reg[127]\(32), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(49), + I1 => \not_strict_mode.app_rd_data_reg[127]\(49), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(33), + I1 => \not_strict_mode.app_rd_data_reg[127]\(33), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(17), + I1 => \not_strict_mode.app_rd_data_reg[127]\(17), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(9), + I1 => \not_strict_mode.app_rd_data_reg[127]\(9), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(41), + I1 => \not_strict_mode.app_rd_data_reg[127]\(41), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(1), + I1 => \not_strict_mode.app_rd_data_reg[127]\(1), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(57), + I1 => \not_strict_mode.app_rd_data_reg[127]\(57), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(25), + I1 => \not_strict_mode.app_rd_data_reg[127]\(25), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(42), + I1 => \not_strict_mode.app_rd_data_reg[127]\(42), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(2), + I1 => \not_strict_mode.app_rd_data_reg[127]\(2), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(58), + I1 => \not_strict_mode.app_rd_data_reg[127]\(58), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(26), + I1 => \not_strict_mode.app_rd_data_reg[127]\(26), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(50), + I1 => \not_strict_mode.app_rd_data_reg[127]\(50), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(34), + I1 => \not_strict_mode.app_rd_data_reg[127]\(34), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(18), + I1 => \not_strict_mode.app_rd_data_reg[127]\(18), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(10), + I1 => \not_strict_mode.app_rd_data_reg[127]\(10), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(19), + I1 => \not_strict_mode.app_rd_data_reg[127]\(19), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(11), + I1 => \not_strict_mode.app_rd_data_reg[127]\(11), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(43), + I1 => \not_strict_mode.app_rd_data_reg[127]\(43), + I2 => \my_empty_reg[4]_rep__2_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(3), + I1 => \not_strict_mode.app_rd_data_reg[127]\(3), + I2 => \^my_empty_reg[4]_rep__1_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(0) + ); +\rd_ptr[0]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => my_empty(1), + I1 => \wr_ptr[1]_i_2_n_0\, + I2 => rd_ptr(0), + O => \rd_ptr[0]_i_1__0_n_0\ + ); +\rd_ptr[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F708" + ) + port map ( + I0 => rd_ptr(0), + I1 => \wr_ptr[1]_i_2_n_0\, + I2 => my_empty(1), + I3 => rd_ptr(1), + O => \rd_ptr[1]_i_1__0_n_0\ + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_ptr[0]_i_1__0_n_0\, + Q => rd_ptr(0), + R => ififo_rst + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_ptr[1]_i_1__0_n_0\, + Q => rd_ptr(1), + R => ififo_rst + ); +\rd_ptr_timing[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EF0F0000FFFF10F0" + ) + port map ( + I0 => \my_empty_reg[4]_rep__2_0\, + I1 => my_full(1), + I2 => \wr_ptr[1]_i_2_n_0\, + I3 => my_empty(1), + I4 => rd_ptr_timing(0), + I5 => rd_ptr(0), + O => \rd_ptr_timing[0]_i_1__1_n_0\ + ); +\rd_ptr_timing[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF10F0EF0F0000" + ) + port map ( + I0 => \my_empty_reg[4]_rep__2_0\, + I1 => my_full(1), + I2 => \wr_ptr[1]_i_2_n_0\, + I3 => my_empty(1), + I4 => rd_ptr_timing(1), + I5 => my_empty1(1), + O => \rd_ptr_timing[1]_i_1__1_n_0\ + ); +\rd_ptr_timing[1]_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + O => my_empty1(1) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \rd_ptr_timing[0]_i_1__1_n_0\, + Q => rd_ptr_timing(0), + R => ififo_rst + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1_n_0\, + D => \rd_ptr_timing[1]_i_1__1_n_0\, + Q => rd_ptr_timing(1), + R => ififo_rst + ); +\read_fifo.fifo_ram[0].RAM32M0_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0777000000000000" + ) + port map ( + I0 => \^my_empty_reg[0]_0\, + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => \my_empty_reg[4]_rep__2_1\(0), + I3 => if_empty_r_0(0), + I4 => \read_fifo.tail_r_reg_0_sn_1\, + I5 => \read_fifo.tail_r_reg\(0), + O => \my_empty_reg[0]_1\ + ); +\read_fifo.tail_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F888FFFF07770000" + ) + port map ( + I0 => \^my_empty_reg[0]_0\, + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => \my_empty_reg[4]_rep__2_1\(0), + I3 => if_empty_r_0(0), + I4 => \read_fifo.tail_r_reg_0_sn_1\, + I5 => \read_fifo.tail_r_reg\(0), + O => \my_empty_reg[0]_2\ + ); +\wr_ptr[0]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFEC1013" + ) + port map ( + I0 => my_empty(1), + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => \wr_ptr[1]_i_2_n_0\, + I3 => my_full(1), + I4 => \^wr_ptr_reg[0]_0\, + O => \wr_ptr[0]_i_1__1_n_0\ + ); +\wr_ptr[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFDFF5D000200A2" + ) + port map ( + I0 => \^wr_ptr_reg[0]_0\, + I1 => my_full(1), + I2 => \wr_ptr[1]_i_2_n_0\, + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => my_empty(1), + I5 => \^wr_ptr_reg[1]_0\, + O => \wr_ptr[1]_i_1__1_n_0\ + ); +\wr_ptr[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0777" + ) + port map ( + I0 => \^my_empty_reg[3]_0\, + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => \my_empty_reg[4]_rep__2_1\(1), + I3 => if_empty_r_0(0), + O => \wr_ptr[1]_i_2_n_0\ + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_ptr[0]_i_1__1_n_0\, + Q => \^wr_ptr_reg[0]_0\, + R => ififo_rst + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_ptr[1]_i_1__1_n_0\, + Q => \^wr_ptr_reg[1]_0\, + R => ififo_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_if_post_fifo_7 is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + init_complete_r1_timing_reg : out STD_LOGIC; + \my_empty_reg[0]_0\ : out STD_LOGIC; + phy_rddata_en : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \my_empty_reg[3]_0\ : out STD_LOGIC; + DIC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[4]_rep__0_0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \read_fifo.tail_r_reg[1]\ : in STD_LOGIC; + \my_empty_reg[4]_rep__2_0\ : in STD_LOGIC; + if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + my_empty : in STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DOC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[0]\ : in STD_LOGIC; + DOB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[81]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[87]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[97]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[99]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[103]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[115]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + ififo_rst : in STD_LOGIC; + CLK : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_if_post_fifo_7 : entity is "mig_7series_v4_2_ddr_if_post_fifo"; +end ddr3_mig_7series_v4_2_ddr_if_post_fifo_7; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_if_post_fifo_7 is + signal my_empty1 : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \my_empty[0]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[1]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[1]_i_2__0_n_0\ : STD_LOGIC; + signal \my_empty[2]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[3]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[4]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[4]_i_2_n_0\ : STD_LOGIC; + signal my_empty_0 : STD_LOGIC_VECTOR ( 4 downto 1 ); + signal \^my_empty_reg[0]_0\ : STD_LOGIC; + signal \^my_empty_reg[3]_0\ : STD_LOGIC; + signal \^my_empty_reg[4]_rep__0_0\ : STD_LOGIC; + signal \my_empty_reg[4]_rep__1_n_0\ : STD_LOGIC; + signal \my_empty_reg[4]_rep__2_n_0\ : STD_LOGIC; + signal \my_empty_reg[4]_rep_n_0\ : STD_LOGIC; + signal my_full : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \my_full[0]_i_1__0_n_0\ : STD_LOGIC; + signal \my_full[0]_i_2_n_0\ : STD_LOGIC; + signal \my_full[1]_i_1__0_n_0\ : STD_LOGIC; + signal \my_full[1]_i_2__0_n_0\ : STD_LOGIC; + signal \my_full[1]_i_3__0_n_0\ : STD_LOGIC; + signal rd_ptr : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \rd_ptr[0]_i_1_n_0\ : STD_LOGIC; + signal \rd_ptr[1]_i_1_n_0\ : STD_LOGIC; + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of rd_ptr_timing : signal is "true"; + attribute syn_maxfan : string; + attribute syn_maxfan of rd_ptr_timing : signal is "10"; + signal \rd_ptr_timing[0]_i_1__2_n_0\ : STD_LOGIC; + signal \rd_ptr_timing[1]_i_1__2_n_0\ : STD_LOGIC; + signal \wr_ptr[0]_i_1__0_n_0\ : STD_LOGIC; + signal \wr_ptr[1]_i_1__0_n_0\ : STD_LOGIC; + signal \wr_ptr[1]_i_2__0_n_0\ : STD_LOGIC; + signal \^wr_ptr_reg[0]_0\ : STD_LOGIC; + signal \^wr_ptr_reg[1]_0\ : STD_LOGIC; + attribute ORIG_CELL_NAME : string; + attribute ORIG_CELL_NAME of \my_empty_reg[4]\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED : integer; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__0\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__0\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__1\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__1\ : label is "my_empty_reg[4]"; + attribute IS_FANOUT_CONSTRAINED of \my_empty_reg[4]_rep__2\ : label is 1; + attribute ORIG_CELL_NAME of \my_empty_reg[4]_rep__2\ : label is "my_empty_reg[4]"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \my_full[0]_i_2\ : label is "soft_lutpair472"; + attribute SOFT_HLUTNM of rd_active_r_i_1 : label is "soft_lutpair471"; + attribute SOFT_HLUTNM of \rd_ptr[0]_i_1\ : label is "soft_lutpair473"; + attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair473"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_2\ : label is "soft_lutpair472"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10"; + attribute SOFT_HLUTNM of \read_fifo.fifo_ram[0].RAM32M0_i_15\ : label is "soft_lutpair471"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; +begin + \my_empty_reg[0]_0\ <= \^my_empty_reg[0]_0\; + \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\; + \my_empty_reg[4]_rep__0_0\ <= \^my_empty_reg[4]_rep__0_0\; + \out\(1 downto 0) <= rd_ptr_timing(1 downto 0); + \wr_ptr_reg[0]_0\ <= \^wr_ptr_reg[0]_0\; + \wr_ptr_reg[1]_0\ <= \^wr_ptr_reg[1]_0\; +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(9), + I4 => Q(9), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(11), + I4 => Q(11), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(13), + I4 => Q(13), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(15), + I4 => Q(15), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(8), + I4 => Q(8), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(10), + I4 => Q(10), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(14), + I4 => Q(14), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(1), + I4 => Q(1), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(3), + I4 => Q(3), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(5), + I4 => Q(5), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(7), + I4 => Q(7), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(0), + I4 => Q(0), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(2), + I4 => Q(2), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(4), + I4 => Q(4), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(6), + I4 => Q(6), + O => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(33), + I4 => Q(33), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(35), + I4 => Q(35), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(37), + I4 => Q(37), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(39), + I4 => Q(39), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(32), + I4 => Q(32), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(34), + I4 => Q(34), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(36), + I4 => Q(36), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(38), + I4 => Q(38), + O => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(49), + I4 => Q(49), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(51), + I4 => Q(51), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(53), + I4 => Q(53), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(55), + I4 => Q(55), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(48), + I4 => Q(48), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(50), + I4 => Q(50), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(52), + I4 => Q(52), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(17), + I4 => Q(17), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(19), + I4 => Q(19), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(21), + I4 => Q(21), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(23), + I4 => Q(23), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(16), + I4 => Q(16), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(18), + I4 => Q(18), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(22), + I4 => Q(22), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(57), + I4 => Q(57), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(59), + I4 => Q(59), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(61), + I4 => Q(61), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(63), + I4 => Q(63), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(56), + I4 => Q(56), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(58), + I4 => Q(58), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(60), + I4 => Q(60), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(62), + I4 => Q(62), + O => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(41), + I4 => Q(41), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(43), + I4 => Q(43), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(45), + I4 => Q(45), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(47), + I4 => Q(47), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(40), + I4 => Q(40), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(42), + I4 => Q(42), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(44), + I4 => Q(44), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(46), + I4 => Q(46), + O => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(25), + I4 => Q(25), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(27), + I4 => Q(27), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(29), + I4 => Q(29), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(31), + I4 => Q(31), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(24), + I4 => Q(24), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(26), + I4 => Q(26), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(28), + I4 => Q(28), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ + ); +\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__1_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(12), + I4 => Q(12), + O => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ + ); +\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(54), + I4 => Q(54), + O => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ + ); +\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(0), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(20), + I4 => Q(20), + O => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ + ); +\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBB88B88" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\(1), + I1 => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + I2 => \my_empty_reg[4]_rep__2_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]\(30), + I4 => Q(30), + O => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ + ); +mem_reg_0_3_6_11_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000078F" + ) + port map ( + I0 => if_empty_r_0(0), + I1 => my_empty(1), + I2 => my_empty_0(2), + I3 => my_full(0), + I4 => \my_empty_reg[4]_rep__2_0\, + O => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ + ); +\my_empty[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => \^my_empty_reg[0]_0\, + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2__0_n_0\, + I4 => my_empty_0(1), + I5 => \my_empty[4]_i_2_n_0\, + O => \my_empty[0]_i_1__0_n_0\ + ); +\my_empty[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA00411400" + ) + port map ( + I0 => \my_empty[1]_i_2__0_n_0\, + I1 => \^wr_ptr_reg[1]_0\, + I2 => rd_ptr(1), + I3 => rd_ptr(0), + I4 => \^wr_ptr_reg[0]_0\, + I5 => my_empty_0(1), + O => \my_empty[1]_i_1__0_n_0\ + ); +\my_empty[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFBFFFBFFFFFEAFF" + ) + port map ( + I0 => my_full(1), + I1 => if_empty_r_0(0), + I2 => my_empty(1), + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => \^my_empty_reg[3]_0\, + I5 => my_empty_0(1), + O => \my_empty[1]_i_2__0_n_0\ + ); +\my_empty[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => my_empty_0(2), + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2__0_n_0\, + I4 => my_empty_0(1), + I5 => \my_empty[4]_i_2_n_0\, + O => \my_empty[2]_i_1__0_n_0\ + ); +\my_empty[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => \^my_empty_reg[3]_0\, + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2__0_n_0\, + I4 => my_empty_0(1), + I5 => \my_empty[4]_i_2_n_0\, + O => \my_empty[3]_i_1__0_n_0\ + ); +\my_empty[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABBAAAAAA88AAA" + ) + port map ( + I0 => \my_empty_reg[4]_rep_n_0\, + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => \wr_ptr[1]_i_2__0_n_0\, + I4 => my_empty_0(1), + I5 => \my_empty[4]_i_2_n_0\, + O => \my_empty[4]_i_1__0_n_0\ + ); +\my_empty[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000960" + ) + port map ( + I0 => \^wr_ptr_reg[1]_0\, + I1 => rd_ptr(1), + I2 => rd_ptr(0), + I3 => \^wr_ptr_reg[0]_0\, + I4 => my_empty_0(1), + O => \my_empty[4]_i_2_n_0\ + ); +\my_empty_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[0]_i_1__0_n_0\, + Q => \^my_empty_reg[0]_0\, + S => ififo_rst + ); +\my_empty_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[1]_i_1__0_n_0\, + Q => my_empty_0(1), + S => ififo_rst + ); +\my_empty_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[2]_i_1__0_n_0\, + Q => my_empty_0(2), + S => ififo_rst + ); +\my_empty_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[3]_i_1__0_n_0\, + Q => \^my_empty_reg[3]_0\, + S => ififo_rst + ); +\my_empty_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[4]_i_1__0_n_0\, + Q => my_empty_0(4), + S => ififo_rst + ); +\my_empty_reg[4]_rep\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[4]_i_1__0_n_0\, + Q => \my_empty_reg[4]_rep_n_0\, + S => ififo_rst + ); +\my_empty_reg[4]_rep__0\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[4]_i_1__0_n_0\, + Q => \^my_empty_reg[4]_rep__0_0\, + S => ififo_rst + ); +\my_empty_reg[4]_rep__1\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[4]_i_1__0_n_0\, + Q => \my_empty_reg[4]_rep__1_n_0\, + S => ififo_rst + ); +\my_empty_reg[4]_rep__2\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_empty[4]_i_1__0_n_0\, + Q => \my_empty_reg[4]_rep__2_n_0\, + S => ififo_rst + ); +\my_full[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BAAAAAAB8AAAAAA8" + ) + port map ( + I0 => my_full(0), + I1 => my_empty_0(1), + I2 => my_full(1), + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => \wr_ptr[1]_i_2__0_n_0\, + I5 => \my_full[0]_i_2_n_0\, + O => \my_full[0]_i_1__0_n_0\ + ); +\my_full[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000960" + ) + port map ( + I0 => rd_ptr(1), + I1 => \^wr_ptr_reg[1]_0\, + I2 => \^wr_ptr_reg[0]_0\, + I3 => rd_ptr(0), + I4 => my_full(1), + O => \my_full[0]_i_2_n_0\ + ); +\my_full[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAFFFF" + ) + port map ( + I0 => my_full(1), + I1 => if_empty_r_0(0), + I2 => my_empty(1), + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => my_empty_0(1), + O => \my_full[1]_i_1__0_n_0\ + ); +\my_full[1]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA00411400" + ) + port map ( + I0 => \my_full[1]_i_3__0_n_0\, + I1 => rd_ptr(1), + I2 => \^wr_ptr_reg[1]_0\, + I3 => \^wr_ptr_reg[0]_0\, + I4 => rd_ptr(0), + I5 => my_full(1), + O => \my_full[1]_i_2__0_n_0\ + ); +\my_full[1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFFFFFEBFBFBF" + ) + port map ( + I0 => my_empty_0(1), + I1 => my_full(1), + I2 => \my_empty_reg[4]_rep__2_0\, + I3 => if_empty_r_0(0), + I4 => my_empty(1), + I5 => \^my_empty_reg[3]_0\, + O => \my_full[1]_i_3__0_n_0\ + ); +\my_full_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_full[0]_i_1__0_n_0\, + Q => my_full(0), + R => ififo_rst + ); +\my_full_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \my_full[1]_i_2__0_n_0\, + Q => my_full(1), + R => ififo_rst + ); +\not_strict_mode.app_rd_data[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(8), + I1 => \not_strict_mode.app_rd_data_reg[117]\(8), + I2 => my_empty_0(4), + I3 => DOC(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(0) + ); +\not_strict_mode.app_rd_data[100]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(22), + I1 => \not_strict_mode.app_rd_data_reg[117]\(22), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[101]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(52) + ); +\not_strict_mode.app_rd_data[101]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(62), + I1 => \not_strict_mode.app_rd_data_reg[117]\(62), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[101]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(53) + ); +\not_strict_mode.app_rd_data[102]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(46), + I1 => \not_strict_mode.app_rd_data_reg[117]\(46), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[103]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(54) + ); +\not_strict_mode.app_rd_data[103]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(30), + I1 => \not_strict_mode.app_rd_data_reg[117]\(30), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[103]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(55) + ); +\not_strict_mode.app_rd_data[112]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(15), + I1 => \not_strict_mode.app_rd_data_reg[117]\(15), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[113]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(56) + ); +\not_strict_mode.app_rd_data[113]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(7), + I1 => \not_strict_mode.app_rd_data_reg[117]\(7), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[113]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(57) + ); +\not_strict_mode.app_rd_data[114]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(39), + I1 => \not_strict_mode.app_rd_data_reg[117]\(39), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[115]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(58) + ); +\not_strict_mode.app_rd_data[115]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(55), + I1 => \not_strict_mode.app_rd_data_reg[117]\(55), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[115]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(59) + ); +\not_strict_mode.app_rd_data[116]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(23), + I1 => \not_strict_mode.app_rd_data_reg[117]\(23), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]_0\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(60) + ); +\not_strict_mode.app_rd_data[117]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(63), + I1 => \not_strict_mode.app_rd_data_reg[117]\(63), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[117]_0\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(61) + ); +\not_strict_mode.app_rd_data[118]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(47), + I1 => \not_strict_mode.app_rd_data_reg[117]\(47), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[119]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(62) + ); +\not_strict_mode.app_rd_data[119]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(31), + I1 => \not_strict_mode.app_rd_data_reg[117]\(31), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[119]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(63) + ); +\not_strict_mode.app_rd_data[16]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(9), + I1 => \not_strict_mode.app_rd_data_reg[117]\(9), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[17]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(8) + ); +\not_strict_mode.app_rd_data[17]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(1), + I1 => \not_strict_mode.app_rd_data_reg[117]\(1), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[17]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(9) + ); +\not_strict_mode.app_rd_data[18]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(33), + I1 => \not_strict_mode.app_rd_data_reg[117]\(33), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[19]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(10) + ); +\not_strict_mode.app_rd_data[19]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(49), + I1 => \not_strict_mode.app_rd_data_reg[117]\(49), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[19]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(11) + ); +\not_strict_mode.app_rd_data[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(0), + I1 => \not_strict_mode.app_rd_data_reg[117]\(0), + I2 => my_empty_0(4), + I3 => DOC(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1) + ); +\not_strict_mode.app_rd_data[20]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(17), + I1 => \not_strict_mode.app_rd_data_reg[117]\(17), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[21]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(12) + ); +\not_strict_mode.app_rd_data[21]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(57), + I1 => \not_strict_mode.app_rd_data_reg[117]\(57), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[21]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(13) + ); +\not_strict_mode.app_rd_data[22]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(41), + I1 => \not_strict_mode.app_rd_data_reg[117]\(41), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[23]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(14) + ); +\not_strict_mode.app_rd_data[23]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(25), + I1 => \not_strict_mode.app_rd_data_reg[117]\(25), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[23]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(15) + ); +\not_strict_mode.app_rd_data[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(32), + I1 => \not_strict_mode.app_rd_data_reg[117]\(32), + I2 => my_empty_0(4), + I3 => DOB(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(2) + ); +\not_strict_mode.app_rd_data[32]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(10), + I1 => \not_strict_mode.app_rd_data_reg[117]\(10), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[33]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(16) + ); +\not_strict_mode.app_rd_data[33]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(2), + I1 => \not_strict_mode.app_rd_data_reg[117]\(2), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[33]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(17) + ); +\not_strict_mode.app_rd_data[34]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(34), + I1 => \not_strict_mode.app_rd_data_reg[117]\(34), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[35]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(18) + ); +\not_strict_mode.app_rd_data[35]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(50), + I1 => \not_strict_mode.app_rd_data_reg[117]\(50), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[35]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(19) + ); +\not_strict_mode.app_rd_data[36]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(18), + I1 => \not_strict_mode.app_rd_data_reg[117]\(18), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[37]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(20) + ); +\not_strict_mode.app_rd_data[37]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(58), + I1 => \not_strict_mode.app_rd_data_reg[117]\(58), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[37]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(21) + ); +\not_strict_mode.app_rd_data[38]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(42), + I1 => \not_strict_mode.app_rd_data_reg[117]\(42), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[39]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(22) + ); +\not_strict_mode.app_rd_data[39]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(26), + I1 => \not_strict_mode.app_rd_data_reg[117]\(26), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[39]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(23) + ); +\not_strict_mode.app_rd_data[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(48), + I1 => \not_strict_mode.app_rd_data_reg[117]\(48), + I2 => my_empty_0(4), + I3 => DOB(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(3) + ); +\not_strict_mode.app_rd_data[48]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(11), + I1 => \not_strict_mode.app_rd_data_reg[117]\(11), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[49]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(24) + ); +\not_strict_mode.app_rd_data[49]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(3), + I1 => \not_strict_mode.app_rd_data_reg[117]\(3), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[49]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(25) + ); +\not_strict_mode.app_rd_data[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(16), + I1 => \not_strict_mode.app_rd_data_reg[117]\(16), + I2 => my_empty_0(4), + I3 => DOA(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(4) + ); +\not_strict_mode.app_rd_data[50]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(35), + I1 => \not_strict_mode.app_rd_data_reg[117]\(35), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[51]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(26) + ); +\not_strict_mode.app_rd_data[51]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(51), + I1 => \not_strict_mode.app_rd_data_reg[117]\(51), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[51]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(27) + ); +\not_strict_mode.app_rd_data[52]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(19), + I1 => \not_strict_mode.app_rd_data_reg[117]\(19), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[53]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(28) + ); +\not_strict_mode.app_rd_data[53]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(59), + I1 => \not_strict_mode.app_rd_data_reg[117]\(59), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[53]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(29) + ); +\not_strict_mode.app_rd_data[54]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(43), + I1 => \not_strict_mode.app_rd_data_reg[117]\(43), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[55]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(30) + ); +\not_strict_mode.app_rd_data[55]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(27), + I1 => \not_strict_mode.app_rd_data_reg[117]\(27), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[55]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(31) + ); +\not_strict_mode.app_rd_data[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(56), + I1 => \not_strict_mode.app_rd_data_reg[117]\(56), + I2 => my_empty_0(4), + I3 => DOA(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(5) + ); +\not_strict_mode.app_rd_data[64]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(12), + I1 => \not_strict_mode.app_rd_data_reg[117]\(12), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[65]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(32) + ); +\not_strict_mode.app_rd_data[65]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(4), + I1 => \not_strict_mode.app_rd_data_reg[117]\(4), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[65]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(33) + ); +\not_strict_mode.app_rd_data[66]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(36), + I1 => \not_strict_mode.app_rd_data_reg[117]\(36), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[67]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(34) + ); +\not_strict_mode.app_rd_data[67]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(52), + I1 => \not_strict_mode.app_rd_data_reg[117]\(52), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[67]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(35) + ); +\not_strict_mode.app_rd_data[68]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(20), + I1 => \not_strict_mode.app_rd_data_reg[117]\(20), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[69]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(36) + ); +\not_strict_mode.app_rd_data[69]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(60), + I1 => \not_strict_mode.app_rd_data_reg[117]\(60), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[69]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(37) + ); +\not_strict_mode.app_rd_data[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(40), + I1 => \not_strict_mode.app_rd_data_reg[117]\(40), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[7]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(6) + ); +\not_strict_mode.app_rd_data[70]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(44), + I1 => \not_strict_mode.app_rd_data_reg[117]\(44), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[71]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(38) + ); +\not_strict_mode.app_rd_data[71]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(28), + I1 => \not_strict_mode.app_rd_data_reg[117]\(28), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[71]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(39) + ); +\not_strict_mode.app_rd_data[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(24), + I1 => \not_strict_mode.app_rd_data_reg[117]\(24), + I2 => my_empty_0(4), + I3 => \not_strict_mode.app_rd_data_reg[7]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(7) + ); +\not_strict_mode.app_rd_data[80]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(13), + I1 => \not_strict_mode.app_rd_data_reg[117]\(13), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[81]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(40) + ); +\not_strict_mode.app_rd_data[81]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(5), + I1 => \not_strict_mode.app_rd_data_reg[117]\(5), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[81]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(41) + ); +\not_strict_mode.app_rd_data[82]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(37), + I1 => \not_strict_mode.app_rd_data_reg[117]\(37), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[83]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(42) + ); +\not_strict_mode.app_rd_data[83]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(53), + I1 => \not_strict_mode.app_rd_data_reg[117]\(53), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[83]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(43) + ); +\not_strict_mode.app_rd_data[84]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(21), + I1 => \not_strict_mode.app_rd_data_reg[117]\(21), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[85]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(44) + ); +\not_strict_mode.app_rd_data[85]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(61), + I1 => \not_strict_mode.app_rd_data_reg[117]\(61), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[85]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(45) + ); +\not_strict_mode.app_rd_data[86]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(45), + I1 => \not_strict_mode.app_rd_data_reg[117]\(45), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[87]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(46) + ); +\not_strict_mode.app_rd_data[87]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(29), + I1 => \not_strict_mode.app_rd_data_reg[117]\(29), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[87]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(47) + ); +\not_strict_mode.app_rd_data[96]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(14), + I1 => \not_strict_mode.app_rd_data_reg[117]\(14), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[97]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(48) + ); +\not_strict_mode.app_rd_data[97]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(6), + I1 => \not_strict_mode.app_rd_data_reg[117]\(6), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[97]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(49) + ); +\not_strict_mode.app_rd_data[98]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(38), + I1 => \not_strict_mode.app_rd_data_reg[117]\(38), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[99]\(0), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(50) + ); +\not_strict_mode.app_rd_data[99]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => Q(54), + I1 => \not_strict_mode.app_rd_data_reg[117]\(54), + I2 => \my_empty_reg[4]_rep_n_0\, + I3 => \not_strict_mode.app_rd_data_reg[99]\(1), + I4 => \not_strict_mode.app_rd_data_reg[0]\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(51) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(56), + I1 => \not_strict_mode.app_rd_data_reg[117]\(56), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(16), + I1 => \not_strict_mode.app_rd_data_reg[117]\(16), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(48), + I1 => \not_strict_mode.app_rd_data_reg[117]\(48), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(32), + I1 => \not_strict_mode.app_rd_data_reg[117]\(32), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(0), + I1 => \not_strict_mode.app_rd_data_reg[117]\(0), + I2 => \my_empty_reg[4]_rep_n_0\, + O => DIC(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(8), + I1 => \not_strict_mode.app_rd_data_reg[117]\(8), + I2 => \my_empty_reg[4]_rep_n_0\, + O => DIC(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(4), + I1 => \not_strict_mode.app_rd_data_reg[117]\(4), + I2 => \my_empty_reg[4]_rep_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(12), + I1 => \not_strict_mode.app_rd_data_reg[117]\(12), + I2 => \my_empty_reg[4]_rep_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(28), + I1 => \not_strict_mode.app_rd_data_reg[117]\(28), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(44), + I1 => \not_strict_mode.app_rd_data_reg[117]\(44), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(60), + I1 => \not_strict_mode.app_rd_data_reg[117]\(60), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(20), + I1 => \not_strict_mode.app_rd_data_reg[117]\(20), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(52), + I1 => \not_strict_mode.app_rd_data_reg[117]\(52), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(36), + I1 => \not_strict_mode.app_rd_data_reg[117]\(36), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(53), + I1 => \not_strict_mode.app_rd_data_reg[117]\(53), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(37), + I1 => \not_strict_mode.app_rd_data_reg[117]\(37), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(5), + I1 => \not_strict_mode.app_rd_data_reg[117]\(5), + I2 => \my_empty_reg[4]_rep_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(13), + I1 => \not_strict_mode.app_rd_data_reg[117]\(13), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(29), + I1 => \not_strict_mode.app_rd_data_reg[117]\(29), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(45), + I1 => \not_strict_mode.app_rd_data_reg[117]\(45), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(61), + I1 => \not_strict_mode.app_rd_data_reg[117]\(61), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(21), + I1 => \not_strict_mode.app_rd_data_reg[117]\(21), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(62), + I1 => \not_strict_mode.app_rd_data_reg[117]\(62), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(22), + I1 => \not_strict_mode.app_rd_data_reg[117]\(22), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(54), + I1 => \not_strict_mode.app_rd_data_reg[117]\(54), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(38), + I1 => \not_strict_mode.app_rd_data_reg[117]\(38), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(6), + I1 => \not_strict_mode.app_rd_data_reg[117]\(6), + I2 => \my_empty_reg[4]_rep_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(14), + I1 => \not_strict_mode.app_rd_data_reg[117]\(14), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(30), + I1 => \not_strict_mode.app_rd_data_reg[117]\(30), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(46), + I1 => \not_strict_mode.app_rd_data_reg[117]\(46), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(7), + I1 => \not_strict_mode.app_rd_data_reg[117]\(7), + I2 => \my_empty_reg[4]_rep_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(15), + I1 => \not_strict_mode.app_rd_data_reg[117]\(15), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(31), + I1 => \not_strict_mode.app_rd_data_reg[117]\(31), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(47), + I1 => \not_strict_mode.app_rd_data_reg[117]\(47), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(63), + I1 => \not_strict_mode.app_rd_data_reg[117]\(63), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(23), + I1 => \not_strict_mode.app_rd_data_reg[117]\(23), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(55), + I1 => \not_strict_mode.app_rd_data_reg[117]\(55), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(39), + I1 => \not_strict_mode.app_rd_data_reg[117]\(39), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(24), + I1 => \not_strict_mode.app_rd_data_reg[117]\(24), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(40), + I1 => \not_strict_mode.app_rd_data_reg[117]\(40), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(1), + I1 => \not_strict_mode.app_rd_data_reg[117]\(1), + I2 => \my_empty_reg[4]_rep_n_0\, + O => DIA(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(9), + I1 => \not_strict_mode.app_rd_data_reg[117]\(9), + I2 => \my_empty_reg[4]_rep_n_0\, + O => DIA(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(25), + I1 => \not_strict_mode.app_rd_data_reg[117]\(25), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(41), + I1 => \not_strict_mode.app_rd_data_reg[117]\(41), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(57), + I1 => \not_strict_mode.app_rd_data_reg[117]\(57), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(17), + I1 => \not_strict_mode.app_rd_data_reg[117]\(17), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(49), + I1 => \not_strict_mode.app_rd_data_reg[117]\(49), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(33), + I1 => \not_strict_mode.app_rd_data_reg[117]\(33), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(50), + I1 => \not_strict_mode.app_rd_data_reg[117]\(50), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(34), + I1 => \not_strict_mode.app_rd_data_reg[117]\(34), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(2), + I1 => \not_strict_mode.app_rd_data_reg[117]\(2), + I2 => \my_empty_reg[4]_rep_n_0\, + O => DIB(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(10), + I1 => \not_strict_mode.app_rd_data_reg[117]\(10), + I2 => \my_empty_reg[4]_rep_n_0\, + O => DIB(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(26), + I1 => \not_strict_mode.app_rd_data_reg[117]\(26), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(42), + I1 => \not_strict_mode.app_rd_data_reg[117]\(42), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(58), + I1 => \not_strict_mode.app_rd_data_reg[117]\(58), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(18), + I1 => \not_strict_mode.app_rd_data_reg[117]\(18), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(59), + I1 => \not_strict_mode.app_rd_data_reg[117]\(59), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(19), + I1 => \not_strict_mode.app_rd_data_reg[117]\(19), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(51), + I1 => \not_strict_mode.app_rd_data_reg[117]\(51), + I2 => \my_empty_reg[4]_rep__1_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(35), + I1 => \not_strict_mode.app_rd_data_reg[117]\(35), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(3), + I1 => \not_strict_mode.app_rd_data_reg[117]\(3), + I2 => \my_empty_reg[4]_rep_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(11), + I1 => \not_strict_mode.app_rd_data_reg[117]\(11), + I2 => \my_empty_reg[4]_rep_n_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(0) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(27), + I1 => \not_strict_mode.app_rd_data_reg[117]\(27), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1) + ); +\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => Q(43), + I1 => \not_strict_mode.app_rd_data_reg[117]\(43), + I2 => \^my_empty_reg[4]_rep__0_0\, + O => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(0) + ); +rd_active_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0777" + ) + port map ( + I0 => \my_empty_reg[4]_rep__2_0\, + I1 => \^my_empty_reg[0]_0\, + I2 => if_empty_r_0(0), + I3 => my_empty(0), + O => phy_rddata_en + ); +\rd_ptr[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => my_empty_0(1), + I1 => \wr_ptr[1]_i_2__0_n_0\, + I2 => rd_ptr(0), + O => \rd_ptr[0]_i_1_n_0\ + ); +\rd_ptr[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F708" + ) + port map ( + I0 => rd_ptr(0), + I1 => \wr_ptr[1]_i_2__0_n_0\, + I2 => my_empty_0(1), + I3 => rd_ptr(1), + O => \rd_ptr[1]_i_1_n_0\ + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_ptr[0]_i_1_n_0\, + Q => rd_ptr(0), + R => ififo_rst + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_ptr[1]_i_1_n_0\, + Q => rd_ptr(1), + R => ififo_rst + ); +\rd_ptr_timing[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EF0F0000FFFF10F0" + ) + port map ( + I0 => \my_empty_reg[4]_rep__2_0\, + I1 => my_full(1), + I2 => \wr_ptr[1]_i_2__0_n_0\, + I3 => my_empty_0(1), + I4 => rd_ptr_timing(0), + I5 => rd_ptr(0), + O => \rd_ptr_timing[0]_i_1__2_n_0\ + ); +\rd_ptr_timing[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF10F0EF0F0000" + ) + port map ( + I0 => \my_empty_reg[4]_rep__2_0\, + I1 => my_full(1), + I2 => \wr_ptr[1]_i_2__0_n_0\, + I3 => my_empty_0(1), + I4 => rd_ptr_timing(1), + I5 => my_empty1(1), + O => \rd_ptr_timing[1]_i_1__2_n_0\ + ); +\rd_ptr_timing[1]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + O => my_empty1(1) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \rd_ptr_timing[0]_i_1__2_n_0\, + Q => rd_ptr_timing(0), + R => ififo_rst + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_full[1]_i_1__0_n_0\, + D => \rd_ptr_timing[1]_i_1__2_n_0\, + Q => rd_ptr_timing(1), + R => ififo_rst + ); +\read_fifo.fifo_ram[0].RAM32M0_i_15\: unisim.vcomponents.LUT5 + generic map( + INIT => X"002A2A2A" + ) + port map ( + I0 => \read_fifo.tail_r_reg[1]\, + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => \^my_empty_reg[0]_0\, + I3 => if_empty_r_0(0), + I4 => my_empty(0), + O => init_complete_r1_timing_reg + ); +\wr_ptr[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFEC1013" + ) + port map ( + I0 => my_empty_0(1), + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => \wr_ptr[1]_i_2__0_n_0\, + I3 => my_full(1), + I4 => \^wr_ptr_reg[0]_0\, + O => \wr_ptr[0]_i_1__0_n_0\ + ); +\wr_ptr[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFDFF5D000200A2" + ) + port map ( + I0 => \^wr_ptr_reg[0]_0\, + I1 => my_full(1), + I2 => \wr_ptr[1]_i_2__0_n_0\, + I3 => \my_empty_reg[4]_rep__2_0\, + I4 => my_empty_0(1), + I5 => \^wr_ptr_reg[1]_0\, + O => \wr_ptr[1]_i_1__0_n_0\ + ); +\wr_ptr[1]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0777" + ) + port map ( + I0 => \^my_empty_reg[3]_0\, + I1 => \my_empty_reg[4]_rep__2_0\, + I2 => my_empty(1), + I3 => if_empty_r_0(0), + O => \wr_ptr[1]_i_2__0_n_0\ + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_ptr[0]_i_1__0_n_0\, + Q => \^wr_ptr_reg[0]_0\, + R => ififo_rst + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_ptr[1]_i_1__0_n_0\, + Q => \^wr_ptr_reg[1]_0\, + R => ififo_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_of_pre_fifo is + port ( + \my_empty_reg[5]_0\ : out STD_LOGIC; + \my_empty_reg[3]_0\ : out STD_LOGIC; + UNCONN_IN : in STD_LOGIC; + mux_cmd_wren : in STD_LOGIC; + \my_full_reg[0]_0\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[8]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[4]_inv_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_of_pre_fifo : entity is "mig_7series_v4_2_ddr_of_pre_fifo"; +end ddr3_mig_7series_v4_2_ddr_of_pre_fifo; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_of_pre_fifo is + signal \my_empty0__0_n_0\ : STD_LOGIC; + signal \my_empty0__1_n_0\ : STD_LOGIC; + signal \my_empty0__2_n_0\ : STD_LOGIC; + signal \my_empty0__3_n_0\ : STD_LOGIC; + signal \my_empty0__4_n_0\ : STD_LOGIC; + signal my_empty0_n_0 : STD_LOGIC; + signal \my_empty[2]_i_1__1_n_0\ : STD_LOGIC; + signal \my_empty[3]_i_1__1_n_0\ : STD_LOGIC; + signal \my_empty[4]_inv_i_1_n_0\ : STD_LOGIC; + signal \my_empty[5]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[6]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[8]_i_1_n_0\ : STD_LOGIC; + signal \^my_empty_reg[3]_0\ : STD_LOGIC; + signal \my_empty_reg[4]_inv_n_0\ : STD_LOGIC; + signal \^my_empty_reg[5]_0\ : STD_LOGIC; + signal \my_empty_reg_n_0_[6]\ : STD_LOGIC; + signal \my_full[0]_i_1__1_n_0\ : STD_LOGIC; + signal \my_full[3]_i_1__0_n_0\ : STD_LOGIC; + signal \my_full[5]_i_1_n_0\ : STD_LOGIC; + signal \my_full_reg_n_0_[0]\ : STD_LOGIC; + signal \my_full_reg_n_0_[3]\ : STD_LOGIC; + signal \my_full_reg_n_0_[5]\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_3_in : STD_LOGIC; + signal rd_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of rd_ptr_timing : signal is "50"; + attribute RTL_KEEP : string; + attribute RTL_KEEP of rd_ptr_timing : signal is "true"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of rd_ptr_timing : signal is "10"; + signal wr_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal wr_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute syn_maxfan of \my_empty_reg[2]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[3]\ : label is "3"; + attribute inverted : string; + attribute inverted of \my_empty_reg[4]_inv\ : label is "yes"; + attribute syn_maxfan of \my_empty_reg[4]_inv\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[5]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[6]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[8]\ : label is "3"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \my_full[0]_i_1__1\ : label is "soft_lutpair444"; + attribute SOFT_HLUTNM of \my_full[3]_i_1__0\ : label is "soft_lutpair444"; + attribute syn_maxfan of \my_full_reg[0]\ : label is "3"; + attribute syn_maxfan of \my_full_reg[3]\ : label is "3"; + attribute syn_maxfan of \my_full_reg[5]\ : label is "3"; + attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair445"; + attribute SOFT_HLUTNM of \rd_ptr[2]_i_1\ : label is "soft_lutpair445"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10"; + attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair446"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_2\ : label is "soft_lutpair446"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10"; + attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes"; +begin + \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\; + \my_empty_reg[5]_0\ <= \^my_empty_reg[5]_0\; +my_empty0: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => my_empty0_n_0 + ); +\my_empty0__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__0_n_0\ + ); +\my_empty0__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__1_n_0\ + ); +\my_empty0__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__2_n_0\ + ); +\my_empty0__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__3_n_0\ + ); +\my_empty0__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__4_n_0\ + ); +\my_empty[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F1F0" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => p_1_in, + I3 => \my_empty0__0_n_0\, + O => \my_empty[2]_i_1__1_n_0\ + ); +\my_empty[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => p_1_in, + I3 => \my_empty0__1_n_0\, + I4 => \^my_empty_reg[3]_0\, + O => \my_empty[3]_i_1__1_n_0\ + ); +\my_empty[4]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFF0001" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__2_n_0\, + I4 => \my_empty_reg[4]_inv_n_0\, + O => \my_empty[4]_inv_i_1_n_0\ + ); +\my_empty[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__3_n_0\, + I4 => \^my_empty_reg[5]_0\, + O => \my_empty[5]_i_1_n_0\ + ); +\my_empty[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__4_n_0\, + I4 => \my_empty_reg_n_0_[6]\, + O => \my_empty[6]_i_1_n_0\ + ); +\my_empty[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDCC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => my_empty0_n_0, + O => \my_empty[8]_i_1_n_0\ + ); +\my_empty_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[2]_i_1__1_n_0\, + Q => p_1_in, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[3]_i_1__1_n_0\, + Q => \^my_empty_reg[3]_0\, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[4]_inv\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[4]_inv_i_1_n_0\, + Q => \my_empty_reg[4]_inv_n_0\, + R => \my_empty_reg[4]_inv_0\(0) + ); +\my_empty_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[5]_i_1_n_0\, + Q => \^my_empty_reg[5]_0\, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[6]_i_1_n_0\, + Q => \my_empty_reg_n_0_[6]\, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[8]_i_1_n_0\, + Q => p_3_in, + S => \my_empty_reg[8]_0\(0) + ); +\my_full[0]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00C8" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[0]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg[0]_0\, + O => \my_full[0]_i_1__1_n_0\ + ); +\my_full[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000C8CC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg_n_0_[0]\, + I4 => \my_full_reg[0]_0\, + O => \my_full[3]_i_1__0_n_0\ + ); +\my_full[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000C8CC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[5]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg_n_0_[0]\, + I4 => \my_full_reg[0]_0\, + O => \my_full[5]_i_1_n_0\ + ); +\my_full_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[0]_i_1__1_n_0\, + Q => \my_full_reg_n_0_[0]\, + R => '0' + ); +\my_full_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[3]_i_1__0_n_0\, + Q => \my_full_reg_n_0_[3]\, + R => '0' + ); +\my_full_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[5]_i_1_n_0\, + Q => \my_full_reg_n_0_[5]\, + R => '0' + ); +\rd_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rd_ptr(0), + O => rd_ptr0(0) + ); +\rd_ptr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + O => rd_ptr0(1) + ); +\rd_ptr[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + I2 => rd_ptr(2), + O => rd_ptr0(2) + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(0), + Q => rd_ptr(0), + R => SR(0) + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(1), + Q => rd_ptr(1), + R => SR(0) + ); +\rd_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(2), + Q => rd_ptr(2), + R => SR(0) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(0), + Q => rd_ptr_timing(0), + R => SR(0) + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(1), + Q => rd_ptr_timing(1), + R => SR(0) + ); +\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(2), + Q => rd_ptr_timing(2), + R => SR(0) + ); +\wr_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => wr_ptr(0), + O => wr_ptr0(0) + ); +\wr_ptr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => wr_ptr(0), + I1 => wr_ptr(1), + O => wr_ptr0(1) + ); +\wr_ptr[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => wr_ptr(0), + I1 => wr_ptr(1), + I2 => wr_ptr(2), + O => wr_ptr0(2) + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => wr_ptr0(0), + Q => wr_ptr(0), + R => SR(0) + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => wr_ptr0(1), + Q => wr_ptr(1), + R => SR(0) + ); +\wr_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => wr_ptr0(2), + Q => wr_ptr(2), + R => SR(0) + ); +\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => wr_ptr0(0), + Q => wr_ptr_timing(0), + R => \my_empty_reg[8]_0\(0) + ); +\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => wr_ptr0(1), + Q => wr_ptr_timing(1), + R => \my_empty_reg[8]_0\(0) + ); +\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => wr_ptr0(2), + Q => wr_ptr_timing(2), + R => \my_empty_reg[8]_0\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ is + port ( + \my_empty_reg[5]_0\ : out STD_LOGIC; + \my_empty_reg[3]_0\ : out STD_LOGIC; + UNCONN_IN : in STD_LOGIC; + mux_cmd_wren : in STD_LOGIC; + \my_full_reg[0]_0\ : in STD_LOGIC; + \rd_ptr_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[4]_inv_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo"; +end \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ is + signal \my_empty0__0_n_0\ : STD_LOGIC; + signal \my_empty0__1_n_0\ : STD_LOGIC; + signal \my_empty0__2_n_0\ : STD_LOGIC; + signal \my_empty0__3_n_0\ : STD_LOGIC; + signal \my_empty0__4_n_0\ : STD_LOGIC; + signal my_empty0_n_0 : STD_LOGIC; + signal \my_empty[2]_i_1__2_n_0\ : STD_LOGIC; + signal \my_empty[3]_i_1__2_n_0\ : STD_LOGIC; + signal \my_empty[4]_inv_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[5]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[6]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[8]_i_1__0_n_0\ : STD_LOGIC; + signal \^my_empty_reg[3]_0\ : STD_LOGIC; + signal \my_empty_reg[4]_inv_n_0\ : STD_LOGIC; + signal \^my_empty_reg[5]_0\ : STD_LOGIC; + signal \my_empty_reg_n_0_[6]\ : STD_LOGIC; + signal \my_full[0]_i_1__2_n_0\ : STD_LOGIC; + signal \my_full[3]_i_1__1_n_0\ : STD_LOGIC; + signal \my_full[5]_i_1__0_n_0\ : STD_LOGIC; + signal \my_full_reg_n_0_[0]\ : STD_LOGIC; + signal \my_full_reg_n_0_[3]\ : STD_LOGIC; + signal \my_full_reg_n_0_[5]\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_3_in : STD_LOGIC; + signal rd_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of rd_ptr_timing : signal is "50"; + attribute RTL_KEEP : string; + attribute RTL_KEEP of rd_ptr_timing : signal is "true"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of rd_ptr_timing : signal is "10"; + signal wr_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal wr_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute syn_maxfan of \my_empty_reg[2]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[3]\ : label is "3"; + attribute inverted : string; + attribute inverted of \my_empty_reg[4]_inv\ : label is "yes"; + attribute syn_maxfan of \my_empty_reg[4]_inv\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[5]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[6]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[8]\ : label is "3"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \my_full[0]_i_1__2\ : label is "soft_lutpair447"; + attribute SOFT_HLUTNM of \my_full[3]_i_1__1\ : label is "soft_lutpair447"; + attribute syn_maxfan of \my_full_reg[0]\ : label is "3"; + attribute syn_maxfan of \my_full_reg[3]\ : label is "3"; + attribute syn_maxfan of \my_full_reg[5]\ : label is "3"; + attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair448"; + attribute SOFT_HLUTNM of \rd_ptr[2]_i_1\ : label is "soft_lutpair448"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10"; + attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair449"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_2\ : label is "soft_lutpair449"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10"; + attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes"; +begin + \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\; + \my_empty_reg[5]_0\ <= \^my_empty_reg[5]_0\; +my_empty0: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => my_empty0_n_0 + ); +\my_empty0__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__0_n_0\ + ); +\my_empty0__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__1_n_0\ + ); +\my_empty0__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__2_n_0\ + ); +\my_empty0__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__3_n_0\ + ); +\my_empty0__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__4_n_0\ + ); +\my_empty[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F1F0" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => p_1_in, + I3 => \my_empty0__0_n_0\, + O => \my_empty[2]_i_1__2_n_0\ + ); +\my_empty[3]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => p_1_in, + I3 => \my_empty0__1_n_0\, + I4 => \^my_empty_reg[3]_0\, + O => \my_empty[3]_i_1__2_n_0\ + ); +\my_empty[4]_inv_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFF0001" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__2_n_0\, + I4 => \my_empty_reg[4]_inv_n_0\, + O => \my_empty[4]_inv_i_1__0_n_0\ + ); +\my_empty[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__3_n_0\, + I4 => \^my_empty_reg[5]_0\, + O => \my_empty[5]_i_1__0_n_0\ + ); +\my_empty[6]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__4_n_0\, + I4 => \my_empty_reg_n_0_[6]\, + O => \my_empty[6]_i_1__0_n_0\ + ); +\my_empty[8]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDCC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => my_empty0_n_0, + O => \my_empty[8]_i_1__0_n_0\ + ); +\my_empty_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[2]_i_1__2_n_0\, + Q => p_1_in, + S => SR(0) + ); +\my_empty_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[3]_i_1__2_n_0\, + Q => \^my_empty_reg[3]_0\, + S => SR(0) + ); +\my_empty_reg[4]_inv\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[4]_inv_i_1__0_n_0\, + Q => \my_empty_reg[4]_inv_n_0\, + R => \my_empty_reg[4]_inv_0\(0) + ); +\my_empty_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[5]_i_1__0_n_0\, + Q => \^my_empty_reg[5]_0\, + S => SR(0) + ); +\my_empty_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[6]_i_1__0_n_0\, + Q => \my_empty_reg_n_0_[6]\, + S => SR(0) + ); +\my_empty_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[8]_i_1__0_n_0\, + Q => p_3_in, + S => SR(0) + ); +\my_full[0]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00C8" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[0]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg[0]_0\, + O => \my_full[0]_i_1__2_n_0\ + ); +\my_full[3]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000C8CC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg_n_0_[0]\, + I4 => \my_full_reg[0]_0\, + O => \my_full[3]_i_1__1_n_0\ + ); +\my_full[5]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000C8CC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[5]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg_n_0_[0]\, + I4 => \my_full_reg[0]_0\, + O => \my_full[5]_i_1__0_n_0\ + ); +\my_full_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[0]_i_1__2_n_0\, + Q => \my_full_reg_n_0_[0]\, + R => '0' + ); +\my_full_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[3]_i_1__1_n_0\, + Q => \my_full_reg_n_0_[3]\, + R => '0' + ); +\my_full_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[5]_i_1__0_n_0\, + Q => \my_full_reg_n_0_[5]\, + R => '0' + ); +\rd_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rd_ptr(0), + O => rd_ptr0(0) + ); +\rd_ptr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + O => rd_ptr0(1) + ); +\rd_ptr[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + I2 => rd_ptr(2), + O => rd_ptr0(2) + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(0), + Q => rd_ptr(0), + R => \rd_ptr_reg[2]_0\(0) + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(1), + Q => rd_ptr(1), + R => \rd_ptr_reg[2]_0\(0) + ); +\rd_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(2), + Q => rd_ptr(2), + R => \rd_ptr_reg[2]_0\(0) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(0), + Q => rd_ptr_timing(0), + R => \rd_ptr_reg[2]_0\(0) + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(1), + Q => rd_ptr_timing(1), + R => \rd_ptr_reg[2]_0\(0) + ); +\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(2), + Q => rd_ptr_timing(2), + R => \rd_ptr_reg[2]_0\(0) + ); +\wr_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => wr_ptr(0), + O => wr_ptr0(0) + ); +\wr_ptr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => wr_ptr(0), + I1 => wr_ptr(1), + O => wr_ptr0(1) + ); +\wr_ptr[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => wr_ptr(0), + I1 => wr_ptr(1), + I2 => wr_ptr(2), + O => wr_ptr0(2) + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(0), + Q => wr_ptr(0), + R => SR(0) + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(1), + Q => wr_ptr(1), + R => SR(0) + ); +\wr_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(2), + Q => wr_ptr(2), + R => SR(0) + ); +\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(0), + Q => wr_ptr_timing(0), + R => SR(0) + ); +\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(1), + Q => wr_ptr_timing(1), + R => SR(0) + ); +\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(2), + Q => wr_ptr_timing(2), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\ is + port ( + \my_empty_reg[5]_0\ : out STD_LOGIC; + \my_empty_reg[3]_0\ : out STD_LOGIC; + UNCONN_IN : in STD_LOGIC; + mux_cmd_wren : in STD_LOGIC; + \my_full_reg[0]_0\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[8]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[4]_inv_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo"; +end \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\ is + signal \my_empty0__0_n_0\ : STD_LOGIC; + signal \my_empty0__1_n_0\ : STD_LOGIC; + signal \my_empty0__2_n_0\ : STD_LOGIC; + signal \my_empty0__3_n_0\ : STD_LOGIC; + signal \my_empty0__4_n_0\ : STD_LOGIC; + signal my_empty0_n_0 : STD_LOGIC; + signal \my_empty[2]_i_1__3_n_0\ : STD_LOGIC; + signal \my_empty[3]_i_1__3_n_0\ : STD_LOGIC; + signal \my_empty[4]_inv_i_1__1_n_0\ : STD_LOGIC; + signal \my_empty[5]_i_1__1_n_0\ : STD_LOGIC; + signal \my_empty[6]_i_1__1_n_0\ : STD_LOGIC; + signal \my_empty[8]_i_1__1_n_0\ : STD_LOGIC; + signal \^my_empty_reg[3]_0\ : STD_LOGIC; + signal \my_empty_reg[4]_inv_n_0\ : STD_LOGIC; + signal \^my_empty_reg[5]_0\ : STD_LOGIC; + signal \my_empty_reg_n_0_[6]\ : STD_LOGIC; + signal \my_full[0]_i_1__3_n_0\ : STD_LOGIC; + signal \my_full[3]_i_1__2_n_0\ : STD_LOGIC; + signal \my_full[5]_i_1__1_n_0\ : STD_LOGIC; + signal \my_full_reg_n_0_[0]\ : STD_LOGIC; + signal \my_full_reg_n_0_[3]\ : STD_LOGIC; + signal \my_full_reg_n_0_[5]\ : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal p_3_in : STD_LOGIC; + signal rd_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of rd_ptr_timing : signal is "50"; + attribute RTL_KEEP : string; + attribute RTL_KEEP of rd_ptr_timing : signal is "true"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of rd_ptr_timing : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of rd_ptr_timing : signal is "10"; + signal wr_ptr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal wr_ptr0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal wr_ptr_timing : STD_LOGIC_VECTOR ( 2 downto 0 ); + attribute syn_maxfan of \my_empty_reg[2]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[3]\ : label is "3"; + attribute inverted : string; + attribute inverted of \my_empty_reg[4]_inv\ : label is "yes"; + attribute syn_maxfan of \my_empty_reg[4]_inv\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[5]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[6]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[8]\ : label is "3"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \my_full[0]_i_1__3\ : label is "soft_lutpair450"; + attribute SOFT_HLUTNM of \my_full[3]_i_1__2\ : label is "soft_lutpair450"; + attribute syn_maxfan of \my_full_reg[0]\ : label is "3"; + attribute syn_maxfan of \my_full_reg[3]\ : label is "3"; + attribute syn_maxfan of \my_full_reg[5]\ : label is "3"; + attribute SOFT_HLUTNM of \rd_ptr[1]_i_1\ : label is "soft_lutpair451"; + attribute SOFT_HLUTNM of \rd_ptr[2]_i_1\ : label is "soft_lutpair451"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[0]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[0]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[1]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[1]\ : label is "10"; + attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes"; + attribute RTL_MAX_FANOUT of \rd_ptr_timing_reg[2]\ : label is "found"; + attribute syn_maxfan of \rd_ptr_timing_reg[2]\ : label is "10"; + attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair452"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_2\ : label is "soft_lutpair452"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10"; + attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes"; +begin + \my_empty_reg[3]_0\ <= \^my_empty_reg[3]_0\; + \my_empty_reg[5]_0\ <= \^my_empty_reg[5]_0\; +my_empty0: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => my_empty0_n_0 + ); +\my_empty0__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__0_n_0\ + ); +\my_empty0__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__1_n_0\ + ); +\my_empty0__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__2_n_0\ + ); +\my_empty0__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__3_n_0\ + ); +\my_empty0__4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0041820014000082" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(2), + I2 => rd_ptr(2), + I3 => rd_ptr(1), + I4 => rd_ptr(0), + I5 => wr_ptr_timing(1), + O => \my_empty0__4_n_0\ + ); +\my_empty[2]_i_1__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F1F0" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => p_1_in, + I3 => \my_empty0__0_n_0\, + O => \my_empty[2]_i_1__3_n_0\ + ); +\my_empty[3]_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => p_1_in, + I3 => \my_empty0__1_n_0\, + I4 => \^my_empty_reg[3]_0\, + O => \my_empty[3]_i_1__3_n_0\ + ); +\my_empty[4]_inv_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFF0001" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__2_n_0\, + I4 => \my_empty_reg[4]_inv_n_0\, + O => \my_empty[4]_inv_i_1__1_n_0\ + ); +\my_empty[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__3_n_0\, + I4 => \^my_empty_reg[5]_0\, + O => \my_empty[5]_i_1__1_n_0\ + ); +\my_empty[6]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0100" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => \my_empty0__4_n_0\, + I4 => \my_empty_reg_n_0_[6]\, + O => \my_empty[6]_i_1__1_n_0\ + ); +\my_empty[8]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDCC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => p_3_in, + I2 => \my_full_reg_n_0_[5]\, + I3 => my_empty0_n_0, + O => \my_empty[8]_i_1__1_n_0\ + ); +\my_empty_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[2]_i_1__3_n_0\, + Q => p_1_in, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[3]_i_1__3_n_0\, + Q => \^my_empty_reg[3]_0\, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[4]_inv\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[4]_inv_i_1__1_n_0\, + Q => \my_empty_reg[4]_inv_n_0\, + R => \my_empty_reg[4]_inv_0\(0) + ); +\my_empty_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[5]_i_1__1_n_0\, + Q => \^my_empty_reg[5]_0\, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[6]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[6]_i_1__1_n_0\, + Q => \my_empty_reg_n_0_[6]\, + S => \my_empty_reg[8]_0\(0) + ); +\my_empty_reg[8]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => \my_empty[8]_i_1__1_n_0\, + Q => p_3_in, + S => \my_empty_reg[8]_0\(0) + ); +\my_full[0]_i_1__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00C8" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[0]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg[0]_0\, + O => \my_full[0]_i_1__3_n_0\ + ); +\my_full[3]_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000C8CC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[3]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg_n_0_[0]\, + I4 => \my_full_reg[0]_0\, + O => \my_full[3]_i_1__2_n_0\ + ); +\my_full[5]_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000C8CC" + ) + port map ( + I0 => mux_cmd_wren, + I1 => \my_full_reg_n_0_[5]\, + I2 => \my_empty_reg_n_0_[6]\, + I3 => \my_full_reg_n_0_[0]\, + I4 => \my_full_reg[0]_0\, + O => \my_full[5]_i_1__1_n_0\ + ); +\my_full_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[0]_i_1__3_n_0\, + Q => \my_full_reg_n_0_[0]\, + R => '0' + ); +\my_full_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[3]_i_1__2_n_0\, + Q => \my_full_reg_n_0_[3]\, + R => '0' + ); +\my_full_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[5]_i_1__1_n_0\, + Q => \my_full_reg_n_0_[5]\, + R => '0' + ); +\rd_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rd_ptr(0), + O => rd_ptr0(0) + ); +\rd_ptr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + O => rd_ptr0(1) + ); +\rd_ptr[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => rd_ptr(0), + I1 => rd_ptr(1), + I2 => rd_ptr(2), + O => rd_ptr0(2) + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(0), + Q => rd_ptr(0), + R => SR(0) + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(1), + Q => rd_ptr(1), + R => SR(0) + ); +\rd_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(2), + Q => rd_ptr(2), + R => SR(0) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(0), + Q => rd_ptr_timing(0), + R => SR(0) + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(1), + Q => rd_ptr_timing(1), + R => SR(0) + ); +\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \my_empty_reg[4]_inv_n_0\, + D => rd_ptr0(2), + Q => rd_ptr_timing(2), + R => SR(0) + ); +\wr_ptr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => wr_ptr(0), + O => wr_ptr0(0) + ); +\wr_ptr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => wr_ptr(0), + I1 => wr_ptr(1), + O => wr_ptr0(1) + ); +\wr_ptr[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => wr_ptr(0), + I1 => wr_ptr(1), + I2 => wr_ptr(2), + O => wr_ptr0(2) + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(0), + Q => wr_ptr(0), + R => SR(0) + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(1), + Q => wr_ptr(1), + R => SR(0) + ); +\wr_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(2), + Q => wr_ptr(2), + R => SR(0) + ); +\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(0), + Q => wr_ptr_timing(0), + R => \my_empty_reg[8]_0\(0) + ); +\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(1), + Q => wr_ptr_timing(1), + R => \my_empty_reg[8]_0\(0) + ); +\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr_timing_reg[0]_0\(0), + D => wr_ptr0(2), + Q => wr_ptr_timing(2), + R => \my_empty_reg[8]_0\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ is + port ( + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \my_empty_reg[1]_0\ : out STD_LOGIC; + \my_empty_reg[1]_1\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 2 downto 0 ); + wr_en : out STD_LOGIC; + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + ofifo_rst : in STD_LOGIC; + CLK : in STD_LOGIC; + D_of_full : in STD_LOGIC; + mux_wrdata_en : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + out_fifo : in STD_LOGIC; + calib_wrdata_en : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo"; +end \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ is + signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \entry_cnt10_out__0\ : STD_LOGIC; + signal \entry_cnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal \entry_cnt[1]_i_1__0_n_0\ : STD_LOGIC; + signal \entry_cnt[2]_i_1__0_n_0\ : STD_LOGIC; + signal \entry_cnt[3]_i_1__0_n_0\ : STD_LOGIC; + signal \entry_cnt[4]_i_1__0_n_0\ : STD_LOGIC; + signal \entry_cnt[4]_i_2__0_n_0\ : STD_LOGIC; + signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal my_empty0 : STD_LOGIC; + signal \my_empty[1]_i_1__2_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_1__1_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_3__1_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_4__1_n_0\ : STD_LOGIC; + signal \^my_empty_reg[1]_1\ : STD_LOGIC; + signal \my_empty_reg_n_0_[7]\ : STD_LOGIC; + signal my_full0 : STD_LOGIC; + signal \my_full[4]_i_1__1_n_0\ : STD_LOGIC; + signal \my_full[4]_i_3__1_n_0\ : STD_LOGIC; + signal \my_full[4]_i_4__1_n_0\ : STD_LOGIC; + signal \my_full_reg_n_0_[4]\ : STD_LOGIC; + signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^rd_ptr_reg[0]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[1]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[2]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[3]_0\ : STD_LOGIC; + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rd_ptr_timing[3]_i_1__2_n_0\ : STD_LOGIC; + signal wr_ptr0 : STD_LOGIC; + signal \^wr_ptr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \entry_cnt[0]_i_1__0\ : label is "soft_lutpair483"; + attribute SOFT_HLUTNM of \entry_cnt[1]_i_1__0\ : label is "soft_lutpair483"; + attribute SOFT_HLUTNM of \my_empty[7]_i_3__1\ : label is "soft_lutpair484"; + attribute SOFT_HLUTNM of \my_empty[7]_i_4__1\ : label is "soft_lutpair484"; + attribute syn_maxfan : string; + attribute syn_maxfan of \my_empty_reg[1]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[7]\ : label is "3"; + attribute SOFT_HLUTNM of \my_full[4]_i_3__1\ : label is "soft_lutpair485"; + attribute SOFT_HLUTNM of \my_full[4]_i_4__1\ : label is "soft_lutpair485"; + attribute syn_maxfan of \my_full_reg[4]\ : label is "3"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10"; + attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__4\ : label is "soft_lutpair488"; + attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__4\ : label is "soft_lutpair488"; + attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__2\ : label is "soft_lutpair486"; + attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__2\ : label is "soft_lutpair486"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes"; + attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__4\ : label is "soft_lutpair489"; + attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__4\ : label is "soft_lutpair489"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__2\ : label is "soft_lutpair487"; + attribute SOFT_HLUTNM of \wr_ptr[3]_i_2__0\ : label is "soft_lutpair487"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10"; + attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes"; +begin + Q(2 downto 0) <= \^q\(2 downto 0); + \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\; + \rd_ptr_reg[0]_0\ <= \^rd_ptr_reg[0]_0\; + \rd_ptr_reg[1]_0\ <= \^rd_ptr_reg[1]_0\; + \rd_ptr_reg[2]_0\ <= \^rd_ptr_reg[2]_0\; + \rd_ptr_reg[3]_0\ <= \^rd_ptr_reg[3]_0\; + \wr_ptr_reg[3]_0\(3 downto 0) <= \^wr_ptr_reg[3]_0\(3 downto 0); +\entry_cnt[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[0]\, + O => \entry_cnt[0]_i_1__0_n_0\ + ); +\entry_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AA6A5595" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[0]\, + I1 => D_of_full, + I2 => mux_wrdata_en, + I3 => \my_full_reg_n_0_[4]\, + I4 => \entry_cnt_reg_n_0_[1]\, + O => \entry_cnt[1]_i_1__0_n_0\ + ); +\entry_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF7F0080AAEA5515" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[0]\, + I1 => D_of_full, + I2 => mux_wrdata_en, + I3 => \my_full_reg_n_0_[4]\, + I4 => \^q\(0), + I5 => \entry_cnt_reg_n_0_[1]\, + O => \entry_cnt[2]_i_1__0_n_0\ + ); +\entry_cnt[3]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F80FE01" + ) + port map ( + I0 => \entry_cnt10_out__0\, + I1 => \entry_cnt_reg_n_0_[0]\, + I2 => \entry_cnt_reg_n_0_[1]\, + I3 => \^q\(1), + I4 => \^q\(0), + O => \entry_cnt[3]_i_1__0_n_0\ + ); +\entry_cnt[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050500303035003" + ) + port map ( + I0 => \my_full_reg_n_0_[4]\, + I1 => \my_empty_reg_n_0_[7]\, + I2 => D_of_full, + I3 => calib_wrdata_en, + I4 => \wr_ptr_timing_reg[0]_0\, + I5 => mc_wrdata_en, + O => \entry_cnt[4]_i_1__0_n_0\ + ); +\entry_cnt[4]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF8000FFFE0001" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[1]\, + I1 => \entry_cnt_reg_n_0_[0]\, + I2 => \entry_cnt10_out__0\, + I3 => \^q\(0), + I4 => \^q\(2), + I5 => \^q\(1), + O => \entry_cnt[4]_i_2__0_n_0\ + ); +\entry_cnt[4]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008A80" + ) + port map ( + I0 => D_of_full, + I1 => mc_wrdata_en, + I2 => \wr_ptr_timing_reg[0]_0\, + I3 => calib_wrdata_en, + I4 => \my_full_reg_n_0_[4]\, + O => \entry_cnt10_out__0\ + ); +\entry_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1__0_n_0\, + D => \entry_cnt[0]_i_1__0_n_0\, + Q => \entry_cnt_reg_n_0_[0]\, + R => ofifo_rst + ); +\entry_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1__0_n_0\, + D => \entry_cnt[1]_i_1__0_n_0\, + Q => \entry_cnt_reg_n_0_[1]\, + R => ofifo_rst + ); +\entry_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1__0_n_0\, + D => \entry_cnt[2]_i_1__0_n_0\, + Q => \^q\(0), + R => ofifo_rst + ); +\entry_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1__0_n_0\, + D => \entry_cnt[3]_i_1__0_n_0\, + Q => \^q\(1), + R => ofifo_rst + ); +\entry_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1__0_n_0\, + D => \entry_cnt[4]_i_2__0_n_0\, + Q => \^q\(2), + R => ofifo_rst + ); +mem_reg_0_15_0_5_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"2727270000002700" + ) + port map ( + I0 => D_of_full, + I1 => \my_full_reg_n_0_[4]\, + I2 => \^my_empty_reg[1]_1\, + I3 => calib_wrdata_en, + I4 => \wr_ptr_timing_reg[0]_0\, + I5 => mc_wrdata_en, + O => wr_en + ); +\my_empty[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => D_of_full, + I1 => mux_wrdata_en, + I2 => \my_full_reg_n_0_[4]\, + I3 => \^my_empty_reg[1]_1\, + I4 => my_empty0, + I5 => ofifo_rst, + O => \my_empty[1]_i_1__2_n_0\ + ); +\my_empty[7]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => D_of_full, + I1 => mux_wrdata_en, + I2 => \my_full_reg_n_0_[4]\, + I3 => \my_empty_reg_n_0_[7]\, + I4 => my_empty0, + I5 => ofifo_rst, + O => \my_empty[7]_i_1__1_n_0\ + ); +\my_empty[7]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => wr_ptr_timing(2), + I1 => \my_empty[7]_i_3__1_n_0\, + I2 => wr_ptr_timing(3), + I3 => \my_empty[7]_i_4__1_n_0\, + I4 => \^rd_ptr_reg[2]_0\, + O => my_empty0 + ); +\my_empty[7]_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => wr_ptr_timing(1), + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + I3 => \^rd_ptr_reg[3]_0\, + I4 => wr_ptr_timing(0), + O => \my_empty[7]_i_3__1_n_0\ + ); +\my_empty[7]_i_4__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(1), + I2 => \^rd_ptr_reg[0]_0\, + I3 => \^rd_ptr_reg[1]_0\, + I4 => \^rd_ptr_reg[3]_0\, + O => \my_empty[7]_i_4__1_n_0\ + ); +\my_empty_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[1]_i_1__2_n_0\, + Q => \^my_empty_reg[1]_1\, + R => '0' + ); +\my_empty_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[7]_i_1__1_n_0\, + Q => \my_empty_reg_n_0_[7]\, + R => '0' + ); +\my_full[4]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFC0080" + ) + port map ( + I0 => my_full0, + I1 => mux_wrdata_en, + I2 => D_of_full, + I3 => \my_empty_reg_n_0_[7]\, + I4 => \my_full_reg_n_0_[4]\, + I5 => ofifo_rst, + O => \my_full[4]_i_1__1_n_0\ + ); +\my_full[4]_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => rd_ptr_timing(2), + I1 => \my_full[4]_i_3__1_n_0\, + I2 => rd_ptr_timing(3), + I3 => \my_full[4]_i_4__1_n_0\, + I4 => \^wr_ptr_reg[3]_0\(2), + O => my_full0 + ); +\my_full[4]_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => rd_ptr_timing(1), + I1 => \^wr_ptr_reg[3]_0\(0), + I2 => \^wr_ptr_reg[3]_0\(1), + I3 => \^wr_ptr_reg[3]_0\(3), + I4 => rd_ptr_timing(0), + O => \my_full[4]_i_3__1_n_0\ + ); +\my_full[4]_i_4__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => rd_ptr_timing(0), + I1 => rd_ptr_timing(1), + I2 => \^wr_ptr_reg[3]_0\(0), + I3 => \^wr_ptr_reg[3]_0\(1), + I4 => \^wr_ptr_reg[3]_0\(3), + O => \my_full[4]_i_4__1_n_0\ + ); +\my_full_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[4]_i_1__1_n_0\, + Q => \my_full_reg_n_0_[4]\, + R => '0' + ); +\out_fifo_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000DFD5" + ) + port map ( + I0 => \^my_empty_reg[1]_1\, + I1 => mc_wrdata_en, + I2 => out_fifo, + I3 => calib_wrdata_en, + I4 => D_of_full, + O => \my_empty_reg[1]_0\ + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(0), + Q => \^rd_ptr_reg[0]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(1), + Q => \^rd_ptr_reg[1]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(2), + Q => \^rd_ptr_reg[2]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(3), + Q => \^rd_ptr_reg[3]_0\, + R => ofifo_rst + ); +\rd_ptr_timing[0]_i_1__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[0]_0\, + O => nxt_rd_ptr(0) + ); +\rd_ptr_timing[1]_i_1__4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + O => nxt_rd_ptr(1) + ); +\rd_ptr_timing[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => \^rd_ptr_reg[2]_0\, + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + I3 => \^rd_ptr_reg[3]_0\, + O => nxt_rd_ptr(2) + ); +\rd_ptr_timing[3]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => D_of_full, + I1 => \my_empty_reg_n_0_[7]\, + O => \rd_ptr_timing[3]_i_1__2_n_0\ + ); +\rd_ptr_timing[3]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[1]_0\, + I2 => \^rd_ptr_reg[0]_0\, + I3 => \^rd_ptr_reg[2]_0\, + O => nxt_rd_ptr(3) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(0), + Q => rd_ptr_timing(0), + R => ofifo_rst + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(1), + Q => rd_ptr_timing(1), + R => ofifo_rst + ); +\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(2), + Q => rd_ptr_timing(2), + R => ofifo_rst + ); +\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__2_n_0\, + D => nxt_rd_ptr(3), + Q => rd_ptr_timing(3), + R => ofifo_rst + ); +\wr_ptr[0]_i_1__4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^wr_ptr_reg[3]_0\(3), + I1 => \^wr_ptr_reg[3]_0\(0), + O => nxt_wr_ptr(0) + ); +\wr_ptr[1]_i_1__4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => \^wr_ptr_reg[3]_0\(3), + I1 => \^wr_ptr_reg[3]_0\(0), + I2 => \^wr_ptr_reg[3]_0\(1), + O => nxt_wr_ptr(1) + ); +\wr_ptr[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => \^wr_ptr_reg[3]_0\(2), + I1 => \^wr_ptr_reg[3]_0\(0), + I2 => \^wr_ptr_reg[3]_0\(1), + I3 => \^wr_ptr_reg[3]_0\(3), + O => nxt_wr_ptr(2) + ); +\wr_ptr[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000E20000E2E2E2" + ) + port map ( + I0 => calib_wrdata_en, + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => mc_wrdata_en, + I3 => D_of_full, + I4 => \my_full_reg_n_0_[4]\, + I5 => \my_empty_reg_n_0_[7]\, + O => wr_ptr0 + ); +\wr_ptr[3]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^wr_ptr_reg[3]_0\(3), + I1 => \^wr_ptr_reg[3]_0\(1), + I2 => \^wr_ptr_reg[3]_0\(0), + I3 => \^wr_ptr_reg[3]_0\(2), + O => nxt_wr_ptr(3) + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(0), + Q => \^wr_ptr_reg[3]_0\(0), + R => ofifo_rst + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(1), + Q => \^wr_ptr_reg[3]_0\(1), + R => ofifo_rst + ); +\wr_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(2), + Q => \^wr_ptr_reg[3]_0\(2), + R => ofifo_rst + ); +\wr_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(3), + Q => \^wr_ptr_reg[3]_0\(3), + R => ofifo_rst + ); +\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(0), + Q => wr_ptr_timing(0), + R => ofifo_rst + ); +\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(1), + Q => wr_ptr_timing(1), + R => ofifo_rst + ); +\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(2), + Q => wr_ptr_timing(2), + R => ofifo_rst + ); +\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(3), + Q => wr_ptr_timing(3), + R => ofifo_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\ is + port ( + \my_empty_reg[1]_0\ : out STD_LOGIC; + D0 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D9 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D6 : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[1]_1\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + calib_cmd_wren : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + A_of_full : in STD_LOGIC; + mc_address : in STD_LOGIC_VECTOR ( 5 downto 0 ); + mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + out_fifo : in STD_LOGIC; + mux_cmd_wren : in STD_LOGIC; + phy_dout : in STD_LOGIC_VECTOR ( 39 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo"; +end \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\ is + signal mem_out : STD_LOGIC_VECTOR ( 75 downto 0 ); + signal my_empty0 : STD_LOGIC; + signal \my_empty[1]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_4_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_5_n_0\ : STD_LOGIC; + signal \^my_empty_reg[1]_0\ : STD_LOGIC; + signal \my_empty_reg_n_0_[7]\ : STD_LOGIC; + signal my_full0 : STD_LOGIC; + signal \my_full[4]_i_1_n_0\ : STD_LOGIC; + signal \my_full[4]_i_3_n_0\ : STD_LOGIC; + signal \my_full[4]_i_4_n_0\ : STD_LOGIC; + signal \my_full_reg_n_0_[4]\ : STD_LOGIC; + signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rd_ptr_timing[3]_i_1_n_0\ : STD_LOGIC; + signal wr_en : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of wr_en : signal is "50"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of wr_en : signal is "found"; + signal wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wr_ptr0__0\ : STD_LOGIC; + signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_mem_reg_0_15_0_5_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_12_17_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_12_17_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_18_23_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_18_23_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_24_29_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_30_35_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_36_41_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_36_41_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_42_47_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_42_47_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_60_65_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_60_65_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_66_71_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_66_71_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_6_11_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_72_77_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_0_5 : label is ""; + attribute RTL_RAM_BITS : integer; + attribute RTL_RAM_BITS of mem_reg_0_15_0_5 : label is 720; + attribute RTL_RAM_NAME : string; + attribute RTL_RAM_NAME of mem_reg_0_15_0_5 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE : string; + attribute RTL_RAM_TYPE of mem_reg_0_15_0_5 : label is "RAM_SDP"; + attribute ram_addr_begin : integer; + attribute ram_addr_begin of mem_reg_0_15_0_5 : label is 0; + attribute ram_addr_end : integer; + attribute ram_addr_end of mem_reg_0_15_0_5 : label is 8; + attribute ram_offset : integer; + attribute ram_offset of mem_reg_0_15_0_5 : label is 0; + attribute ram_slice_begin : integer; + attribute ram_slice_begin of mem_reg_0_15_0_5 : label is 0; + attribute ram_slice_end : integer; + attribute ram_slice_end of mem_reg_0_15_0_5 : label is 5; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_12_17 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_12_17 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_12_17 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_12_17 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_12_17 : label is 0; + attribute ram_addr_end of mem_reg_0_15_12_17 : label is 8; + attribute ram_offset of mem_reg_0_15_12_17 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_12_17 : label is 12; + attribute ram_slice_end of mem_reg_0_15_12_17 : label is 17; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_18_23 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_18_23 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_18_23 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_18_23 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_18_23 : label is 0; + attribute ram_addr_end of mem_reg_0_15_18_23 : label is 8; + attribute ram_offset of mem_reg_0_15_18_23 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_18_23 : label is 18; + attribute ram_slice_end of mem_reg_0_15_18_23 : label is 23; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_24_29 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_24_29 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_24_29 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_24_29 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_24_29 : label is 0; + attribute ram_addr_end of mem_reg_0_15_24_29 : label is 8; + attribute ram_offset of mem_reg_0_15_24_29 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_24_29 : label is 24; + attribute ram_slice_end of mem_reg_0_15_24_29 : label is 29; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_30_35 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_30_35 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_30_35 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_30_35 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_30_35 : label is 0; + attribute ram_addr_end of mem_reg_0_15_30_35 : label is 8; + attribute ram_offset of mem_reg_0_15_30_35 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_30_35 : label is 30; + attribute ram_slice_end of mem_reg_0_15_30_35 : label is 35; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_36_41 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_36_41 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_36_41 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_36_41 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_36_41 : label is 0; + attribute ram_addr_end of mem_reg_0_15_36_41 : label is 8; + attribute ram_offset of mem_reg_0_15_36_41 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_36_41 : label is 36; + attribute ram_slice_end of mem_reg_0_15_36_41 : label is 41; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_42_47 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_42_47 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_42_47 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_42_47 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_42_47 : label is 0; + attribute ram_addr_end of mem_reg_0_15_42_47 : label is 8; + attribute ram_offset of mem_reg_0_15_42_47 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_42_47 : label is 42; + attribute ram_slice_end of mem_reg_0_15_42_47 : label is 47; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_48_53 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_48_53 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_48_53 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_48_53 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_48_53 : label is 0; + attribute ram_addr_end of mem_reg_0_15_48_53 : label is 8; + attribute ram_offset of mem_reg_0_15_48_53 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_48_53 : label is 48; + attribute ram_slice_end of mem_reg_0_15_48_53 : label is 53; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_54_59 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_54_59 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_54_59 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_54_59 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_54_59 : label is 0; + attribute ram_addr_end of mem_reg_0_15_54_59 : label is 8; + attribute ram_offset of mem_reg_0_15_54_59 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_54_59 : label is 54; + attribute ram_slice_end of mem_reg_0_15_54_59 : label is 59; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_60_65 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_60_65 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_60_65 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_60_65 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_60_65 : label is 0; + attribute ram_addr_end of mem_reg_0_15_60_65 : label is 8; + attribute ram_offset of mem_reg_0_15_60_65 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_60_65 : label is 60; + attribute ram_slice_end of mem_reg_0_15_60_65 : label is 65; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_66_71 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_66_71 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_66_71 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_66_71 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_66_71 : label is 0; + attribute ram_addr_end of mem_reg_0_15_66_71 : label is 8; + attribute ram_offset of mem_reg_0_15_66_71 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_66_71 : label is 66; + attribute ram_slice_end of mem_reg_0_15_66_71 : label is 71; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_6_11 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_6_11 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_6_11 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_6_11 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_6_11 : label is 0; + attribute ram_addr_end of mem_reg_0_15_6_11 : label is 8; + attribute ram_offset of mem_reg_0_15_6_11 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_6_11 : label is 6; + attribute ram_slice_end of mem_reg_0_15_6_11 : label is 11; + attribute METHODOLOGY_DRC_VIOS of mem_reg_0_15_72_77 : label is ""; + attribute RTL_RAM_BITS of mem_reg_0_15_72_77 : label is 720; + attribute RTL_RAM_NAME of mem_reg_0_15_72_77 : label is "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of mem_reg_0_15_72_77 : label is "RAM_SDP"; + attribute ram_addr_begin of mem_reg_0_15_72_77 : label is 0; + attribute ram_addr_end of mem_reg_0_15_72_77 : label is 8; + attribute ram_offset of mem_reg_0_15_72_77 : label is 0; + attribute ram_slice_begin of mem_reg_0_15_72_77 : label is 72; + attribute ram_slice_end of mem_reg_0_15_72_77 : label is 77; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \my_empty[7]_i_4\ : label is "soft_lutpair453"; + attribute SOFT_HLUTNM of \my_empty[7]_i_5\ : label is "soft_lutpair453"; + attribute syn_maxfan : string; + attribute syn_maxfan of \my_empty_reg[1]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[7]\ : label is "3"; + attribute SOFT_HLUTNM of \my_full[4]_i_3\ : label is "soft_lutpair454"; + attribute SOFT_HLUTNM of \my_full[4]_i_4\ : label is "soft_lutpair454"; + attribute syn_maxfan of \my_full_reg[4]\ : label is "3"; + attribute SOFT_HLUTNM of out_fifo_i_2 : label is "soft_lutpair455"; + attribute SOFT_HLUTNM of out_fifo_i_26 : label is "soft_lutpair457"; + attribute SOFT_HLUTNM of out_fifo_i_28 : label is "soft_lutpair458"; + attribute SOFT_HLUTNM of out_fifo_i_3 : label is "soft_lutpair455"; + attribute SOFT_HLUTNM of out_fifo_i_4 : label is "soft_lutpair457"; + attribute SOFT_HLUTNM of out_fifo_i_42 : label is "soft_lutpair456"; + attribute SOFT_HLUTNM of out_fifo_i_44 : label is "soft_lutpair458"; + attribute SOFT_HLUTNM of out_fifo_i_5 : label is "soft_lutpair456"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10"; + attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1\ : label is "soft_lutpair461"; + attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1\ : label is "soft_lutpair461"; + attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1\ : label is "soft_lutpair459"; + attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2\ : label is "soft_lutpair459"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes"; + attribute SOFT_HLUTNM of \wr_ptr[0]_i_1\ : label is "soft_lutpair462"; + attribute SOFT_HLUTNM of \wr_ptr[1]_i_1\ : label is "soft_lutpair462"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_1\ : label is "soft_lutpair460"; + attribute SOFT_HLUTNM of \wr_ptr[3]_i_1\ : label is "soft_lutpair460"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10"; + attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes"; +begin + \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\; +mem_reg_0_15_0_5: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1) => phy_dout(37), + DIA(0) => phy_dout(0), + DIB(1) => phy_dout(39), + DIB(0) => phy_dout(1), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => mem_out(1 downto 0), + DOB(1 downto 0) => mem_out(3 downto 2), + DOC(1 downto 0) => NLW_mem_reg_0_15_0_5_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_12_17: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => phy_dout(7 downto 6), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => NLW_mem_reg_0_15_12_17_DOA_UNCONNECTED(1 downto 0), + DOB(1 downto 0) => NLW_mem_reg_0_15_12_17_DOB_UNCONNECTED(1 downto 0), + DOC(1 downto 0) => \rd_ptr_reg[3]_0\(5 downto 4), + DOD(1 downto 0) => NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_18_23: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => phy_dout(9 downto 8), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \rd_ptr_reg[3]_0\(7 downto 6), + DOB(1 downto 0) => NLW_mem_reg_0_15_18_23_DOB_UNCONNECTED(1 downto 0), + DOC(1 downto 0) => NLW_mem_reg_0_15_18_23_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_24_29: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => phy_dout(11 downto 10), + DIB(1 downto 0) => phy_dout(13 downto 12), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \rd_ptr_reg[3]_0\(9 downto 8), + DOB(1 downto 0) => \rd_ptr_reg[3]_0\(11 downto 10), + DOC(1 downto 0) => NLW_mem_reg_0_15_24_29_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_30_35: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => phy_dout(15 downto 14), + DIC(1 downto 0) => phy_dout(17 downto 16), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => NLW_mem_reg_0_15_30_35_DOA_UNCONNECTED(1 downto 0), + DOB(1 downto 0) => \rd_ptr_reg[3]_0\(13 downto 12), + DOC(1 downto 0) => \rd_ptr_reg[3]_0\(15 downto 14), + DOD(1 downto 0) => NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_36_41: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => phy_dout(19 downto 18), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => NLW_mem_reg_0_15_36_41_DOA_UNCONNECTED(1 downto 0), + DOB(1 downto 0) => NLW_mem_reg_0_15_36_41_DOB_UNCONNECTED(1 downto 0), + DOC(1 downto 0) => \rd_ptr_reg[3]_0\(17 downto 16), + DOD(1 downto 0) => NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_42_47: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => phy_dout(21 downto 20), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \rd_ptr_reg[3]_0\(19 downto 18), + DOB(1 downto 0) => NLW_mem_reg_0_15_42_47_DOB_UNCONNECTED(1 downto 0), + DOC(1 downto 0) => NLW_mem_reg_0_15_42_47_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_48_53: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => phy_dout(23 downto 22), + DIB(1 downto 0) => phy_dout(25 downto 24), + DIC(1) => phy_dout(37), + DIC(0) => phy_dout(26), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \rd_ptr_reg[3]_0\(21 downto 20), + DOB(1 downto 0) => \rd_ptr_reg[3]_0\(23 downto 22), + DOC(1 downto 0) => mem_out(53 downto 52), + DOD(1 downto 0) => NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_54_59: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1) => phy_dout(39), + DIA(0) => phy_dout(27), + DIB(1 downto 0) => phy_dout(29 downto 28), + DIC(1 downto 0) => phy_dout(31 downto 30), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => mem_out(55 downto 54), + DOB(1 downto 0) => \rd_ptr_reg[3]_0\(25 downto 24), + DOC(1 downto 0) => \rd_ptr_reg[3]_0\(27 downto 26), + DOD(1 downto 0) => NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_60_65: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => phy_dout(33 downto 32), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => NLW_mem_reg_0_15_60_65_DOA_UNCONNECTED(1 downto 0), + DOB(1 downto 0) => NLW_mem_reg_0_15_60_65_DOB_UNCONNECTED(1 downto 0), + DOC(1 downto 0) => \rd_ptr_reg[3]_0\(29 downto 28), + DOD(1 downto 0) => NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_66_71: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => phy_dout(35 downto 34), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \rd_ptr_reg[3]_0\(31 downto 30), + DOB(1 downto 0) => NLW_mem_reg_0_15_66_71_DOB_UNCONNECTED(1 downto 0), + DOC(1 downto 0) => NLW_mem_reg_0_15_66_71_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_6_11: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => phy_dout(3 downto 2), + DIC(1 downto 0) => phy_dout(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => NLW_mem_reg_0_15_6_11_DOA_UNCONNECTED(1 downto 0), + DOB(1 downto 0) => \rd_ptr_reg[3]_0\(1 downto 0), + DOC(1 downto 0) => \rd_ptr_reg[3]_0\(3 downto 2), + DOD(1 downto 0) => NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +mem_reg_0_15_72_77: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => rd_ptr(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => rd_ptr(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => rd_ptr(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => wr_ptr(3 downto 0), + DIA(1 downto 0) => phy_dout(37 downto 36), + DIB(1 downto 0) => phy_dout(39 downto 38), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => mem_out(73 downto 72), + DOB(1 downto 0) => mem_out(75 downto 74), + DOC(1 downto 0) => NLW_mem_reg_0_15_72_77_DOC_UNCONNECTED(1 downto 0), + DOD(1 downto 0) => NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0), + WCLK => CLK, + WE => wr_en + ); +\my_empty[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => A_of_full, + I1 => mux_cmd_wren, + I2 => \my_full_reg_n_0_[4]\, + I3 => \^my_empty_reg[1]_0\, + I4 => my_empty0, + I5 => SR(0), + O => \my_empty[1]_i_1_n_0\ + ); +\my_empty[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => A_of_full, + I1 => mux_cmd_wren, + I2 => \my_full_reg_n_0_[4]\, + I3 => \my_empty_reg_n_0_[7]\, + I4 => my_empty0, + I5 => SR(0), + O => \my_empty[7]_i_1_n_0\ + ); +\my_empty[7]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => wr_ptr_timing(2), + I1 => \my_empty[7]_i_4_n_0\, + I2 => wr_ptr_timing(3), + I3 => \my_empty[7]_i_5_n_0\, + I4 => rd_ptr(2), + O => my_empty0 + ); +\my_empty[7]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => wr_ptr_timing(1), + I1 => rd_ptr(0), + I2 => rd_ptr(1), + I3 => rd_ptr(3), + I4 => wr_ptr_timing(0), + O => \my_empty[7]_i_4_n_0\ + ); +\my_empty[7]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(1), + I2 => rd_ptr(0), + I3 => rd_ptr(1), + I4 => rd_ptr(3), + O => \my_empty[7]_i_5_n_0\ + ); +\my_empty_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[1]_i_1_n_0\, + Q => \^my_empty_reg[1]_0\, + R => '0' + ); +\my_empty_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[7]_i_1_n_0\, + Q => \my_empty_reg_n_0_[7]\, + R => '0' + ); +\my_full[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFC0080" + ) + port map ( + I0 => my_full0, + I1 => mux_cmd_wren, + I2 => A_of_full, + I3 => \my_empty_reg_n_0_[7]\, + I4 => \my_full_reg_n_0_[4]\, + I5 => SR(0), + O => \my_full[4]_i_1_n_0\ + ); +\my_full[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => rd_ptr_timing(2), + I1 => \my_full[4]_i_3_n_0\, + I2 => rd_ptr_timing(3), + I3 => \my_full[4]_i_4_n_0\, + I4 => wr_ptr(2), + O => my_full0 + ); +\my_full[4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => rd_ptr_timing(1), + I1 => wr_ptr(0), + I2 => wr_ptr(1), + I3 => wr_ptr(3), + I4 => rd_ptr_timing(0), + O => \my_full[4]_i_3_n_0\ + ); +\my_full[4]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => rd_ptr_timing(0), + I1 => rd_ptr_timing(1), + I2 => wr_ptr(0), + I3 => wr_ptr(1), + I4 => wr_ptr(3), + O => \my_full[4]_i_4_n_0\ + ); +\my_full_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[4]_i_1_n_0\, + Q => \my_full_reg_n_0_[4]\, + R => '0' + ); +out_fifo_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00FD" + ) + port map ( + I0 => \^my_empty_reg[1]_0\, + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => calib_cmd_wren, + I3 => A_of_full, + O => \my_empty_reg[1]_1\ + ); +out_fifo_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \wr_ptr_timing_reg[0]_0\, + I1 => mem_out(3), + I2 => \^my_empty_reg[1]_0\, + O => D0(3) + ); +out_fifo_i_26: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \wr_ptr_timing_reg[0]_0\, + I1 => mem_out(55), + I2 => \^my_empty_reg[1]_0\, + O => D6(3) + ); +out_fifo_i_27: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_address(5), + I1 => out_fifo, + I2 => mem_out(54), + I3 => \^my_empty_reg[1]_0\, + O => D6(2) + ); +out_fifo_i_28: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_cas_n(0), + I1 => out_fifo, + I2 => mem_out(53), + I3 => \^my_empty_reg[1]_0\, + O => D6(1) + ); +out_fifo_i_29: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_address(2), + I1 => out_fifo, + I2 => mem_out(52), + I3 => \^my_empty_reg[1]_0\, + O => D6(0) + ); +out_fifo_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_address(3), + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => mem_out(2), + I3 => \^my_empty_reg[1]_0\, + O => D0(2) + ); +out_fifo_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_cas_n(0), + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => mem_out(1), + I3 => \^my_empty_reg[1]_0\, + O => D0(1) + ); +out_fifo_i_42: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \wr_ptr_timing_reg[0]_0\, + I1 => mem_out(75), + I2 => \^my_empty_reg[1]_0\, + O => D9(3) + ); +out_fifo_i_43: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_address(4), + I1 => out_fifo, + I2 => mem_out(74), + I3 => \^my_empty_reg[1]_0\, + O => D9(2) + ); +out_fifo_i_44: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_cas_n(0), + I1 => out_fifo, + I2 => mem_out(73), + I3 => \^my_empty_reg[1]_0\, + O => D9(1) + ); +out_fifo_i_45: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_address(1), + I1 => out_fifo, + I2 => mem_out(72), + I3 => \^my_empty_reg[1]_0\, + O => D9(0) + ); +out_fifo_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => mc_address(0), + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => mem_out(0), + I3 => \^my_empty_reg[1]_0\, + O => D0(0) + ); +p_17_out: unisim.vcomponents.LUT5 + generic map( + INIT => X"27272700" + ) + port map ( + I0 => A_of_full, + I1 => \my_full_reg_n_0_[4]\, + I2 => \^my_empty_reg[1]_0\, + I3 => calib_cmd_wren, + I4 => \wr_ptr_timing_reg[0]_0\, + O => wr_en + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(0), + Q => rd_ptr(0), + R => SR(0) + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(1), + Q => rd_ptr(1), + R => SR(0) + ); +\rd_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(2), + Q => rd_ptr(2), + R => SR(0) + ); +\rd_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(3), + Q => rd_ptr(3), + R => SR(0) + ); +\rd_ptr_timing[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => rd_ptr(3), + I1 => rd_ptr(0), + O => nxt_rd_ptr(0) + ); +\rd_ptr_timing[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => rd_ptr(3), + I1 => rd_ptr(0), + I2 => rd_ptr(1), + O => nxt_rd_ptr(1) + ); +\rd_ptr_timing[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => rd_ptr(2), + I1 => rd_ptr(0), + I2 => rd_ptr(1), + I3 => rd_ptr(3), + O => nxt_rd_ptr(2) + ); +\rd_ptr_timing[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => A_of_full, + I1 => \my_empty_reg_n_0_[7]\, + O => \rd_ptr_timing[3]_i_1_n_0\ + ); +\rd_ptr_timing[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => rd_ptr(3), + I1 => rd_ptr(1), + I2 => rd_ptr(0), + I3 => rd_ptr(2), + O => nxt_rd_ptr(3) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(0), + Q => rd_ptr_timing(0), + R => SR(0) + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(1), + Q => rd_ptr_timing(1), + R => SR(0) + ); +\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(2), + Q => rd_ptr_timing(2), + R => SR(0) + ); +\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1_n_0\, + D => nxt_rd_ptr(3), + Q => rd_ptr_timing(3), + R => SR(0) + ); +wr_ptr0: unisim.vcomponents.LUT5 + generic map( + INIT => X"00E00EEE" + ) + port map ( + I0 => calib_cmd_wren, + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => A_of_full, + I3 => \my_full_reg_n_0_[4]\, + I4 => \my_empty_reg_n_0_[7]\, + O => \wr_ptr0__0\ + ); +\wr_ptr[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => wr_ptr(3), + I1 => wr_ptr(0), + O => nxt_wr_ptr(0) + ); +\wr_ptr[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => wr_ptr(3), + I1 => wr_ptr(0), + I2 => wr_ptr(1), + O => nxt_wr_ptr(1) + ); +\wr_ptr[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => wr_ptr(2), + I1 => wr_ptr(0), + I2 => wr_ptr(1), + I3 => wr_ptr(3), + O => nxt_wr_ptr(2) + ); +\wr_ptr[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => wr_ptr(3), + I1 => wr_ptr(1), + I2 => wr_ptr(0), + I3 => wr_ptr(2), + O => nxt_wr_ptr(3) + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(0), + Q => wr_ptr(0), + R => SR(0) + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(1), + Q => wr_ptr(1), + R => SR(0) + ); +\wr_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(2), + Q => wr_ptr(2), + R => SR(0) + ); +\wr_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(3), + Q => wr_ptr(3), + R => SR(0) + ); +\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(0), + Q => wr_ptr_timing(0), + R => SR(0) + ); +\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(1), + Q => wr_ptr_timing(1), + R => SR(0) + ); +\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(2), + Q => wr_ptr_timing(2), + R => SR(0) + ); +\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(3), + Q => wr_ptr_timing(3), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\ is + port ( + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \my_empty_reg[1]_0\ : out STD_LOGIC; + \my_empty_reg[1]_1\ : out STD_LOGIC; + phy_mc_data_full : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + ofifo_rst : in STD_LOGIC; + CLK : in STD_LOGIC; + C_of_full : in STD_LOGIC; + mux_wrdata_en : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + calib_wrdata_en : in STD_LOGIC; + ofs_rdy_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo"; +end \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\ is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \entry_cnt10_out__0\ : STD_LOGIC; + signal \entry_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \entry_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \entry_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \entry_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \entry_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \entry_cnt[4]_i_2_n_0\ : STD_LOGIC; + signal entry_cnt_reg : STD_LOGIC_VECTOR ( 4 downto 2 ); + signal \entry_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \entry_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal my_empty0 : STD_LOGIC; + signal \my_empty[1]_i_1__1_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_4__0_n_0\ : STD_LOGIC; + signal \my_empty[7]_i_5__0_n_0\ : STD_LOGIC; + signal \^my_empty_reg[1]_1\ : STD_LOGIC; + signal \my_empty_reg_n_0_[7]\ : STD_LOGIC; + signal my_full0 : STD_LOGIC; + signal \my_full[4]_i_1__0_n_0\ : STD_LOGIC; + signal \my_full[4]_i_3__0_n_0\ : STD_LOGIC; + signal \my_full[4]_i_4__0_n_0\ : STD_LOGIC; + signal \my_full_reg_n_0_[4]\ : STD_LOGIC; + signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^rd_ptr_reg[0]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[1]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[2]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[3]_0\ : STD_LOGIC; + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rd_ptr_timing[3]_i_1__1_n_0\ : STD_LOGIC; + signal wr_ptr0 : STD_LOGIC; + signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \entry_cnt[0]_i_1\ : label is "soft_lutpair474"; + attribute SOFT_HLUTNM of \entry_cnt[1]_i_1\ : label is "soft_lutpair474"; + attribute SOFT_HLUTNM of \my_empty[7]_i_4__0\ : label is "soft_lutpair475"; + attribute SOFT_HLUTNM of \my_empty[7]_i_5__0\ : label is "soft_lutpair475"; + attribute syn_maxfan : string; + attribute syn_maxfan of \my_empty_reg[1]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[7]\ : label is "3"; + attribute SOFT_HLUTNM of \my_full[4]_i_3__0\ : label is "soft_lutpair476"; + attribute SOFT_HLUTNM of \my_full[4]_i_4__0\ : label is "soft_lutpair476"; + attribute syn_maxfan of \my_full_reg[4]\ : label is "3"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10"; + attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__3\ : label is "soft_lutpair479"; + attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__3\ : label is "soft_lutpair479"; + attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__1\ : label is "soft_lutpair477"; + attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__1\ : label is "soft_lutpair477"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes"; + attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__3\ : label is "soft_lutpair480"; + attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__3\ : label is "soft_lutpair480"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__1\ : label is "soft_lutpair478"; + attribute SOFT_HLUTNM of \wr_ptr[3]_i_2\ : label is "soft_lutpair478"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10"; + attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); + \my_empty_reg[1]_1\ <= \^my_empty_reg[1]_1\; + \rd_ptr_reg[0]_0\ <= \^rd_ptr_reg[0]_0\; + \rd_ptr_reg[1]_0\ <= \^rd_ptr_reg[1]_0\; + \rd_ptr_reg[2]_0\ <= \^rd_ptr_reg[2]_0\; + \rd_ptr_reg[3]_0\ <= \^rd_ptr_reg[3]_0\; +\entry_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[0]\, + O => \entry_cnt[0]_i_1_n_0\ + ); +\entry_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AA6A5595" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[0]\, + I1 => C_of_full, + I2 => mux_wrdata_en, + I3 => \my_full_reg_n_0_[4]\, + I4 => \entry_cnt_reg_n_0_[1]\, + O => \entry_cnt[1]_i_1_n_0\ + ); +\entry_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF7F0080AAEA5515" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[0]\, + I1 => C_of_full, + I2 => mux_wrdata_en, + I3 => \my_full_reg_n_0_[4]\, + I4 => entry_cnt_reg(2), + I5 => \entry_cnt_reg_n_0_[1]\, + O => \entry_cnt[2]_i_1_n_0\ + ); +\entry_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7F80FE01" + ) + port map ( + I0 => \entry_cnt10_out__0\, + I1 => \entry_cnt_reg_n_0_[0]\, + I2 => \entry_cnt_reg_n_0_[1]\, + I3 => entry_cnt_reg(3), + I4 => entry_cnt_reg(2), + O => \entry_cnt[3]_i_1_n_0\ + ); +\entry_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050500303035003" + ) + port map ( + I0 => \my_full_reg_n_0_[4]\, + I1 => \my_empty_reg_n_0_[7]\, + I2 => C_of_full, + I3 => calib_wrdata_en, + I4 => \wr_ptr_timing_reg[0]_0\, + I5 => mc_wrdata_en, + O => \entry_cnt[4]_i_1_n_0\ + ); +\entry_cnt[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF8000FFFE0001" + ) + port map ( + I0 => \entry_cnt_reg_n_0_[1]\, + I1 => \entry_cnt_reg_n_0_[0]\, + I2 => \entry_cnt10_out__0\, + I3 => entry_cnt_reg(2), + I4 => entry_cnt_reg(4), + I5 => entry_cnt_reg(3), + O => \entry_cnt[4]_i_2_n_0\ + ); +\entry_cnt[4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008A80" + ) + port map ( + I0 => C_of_full, + I1 => mc_wrdata_en, + I2 => \wr_ptr_timing_reg[0]_0\, + I3 => calib_wrdata_en, + I4 => \my_full_reg_n_0_[4]\, + O => \entry_cnt10_out__0\ + ); +\entry_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1_n_0\, + D => \entry_cnt[0]_i_1_n_0\, + Q => \entry_cnt_reg_n_0_[0]\, + R => ofifo_rst + ); +\entry_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1_n_0\, + D => \entry_cnt[1]_i_1_n_0\, + Q => \entry_cnt_reg_n_0_[1]\, + R => ofifo_rst + ); +\entry_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1_n_0\, + D => \entry_cnt[2]_i_1_n_0\, + Q => entry_cnt_reg(2), + R => ofifo_rst + ); +\entry_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1_n_0\, + D => \entry_cnt[3]_i_1_n_0\, + Q => entry_cnt_reg(3), + R => ofifo_rst + ); +\entry_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \entry_cnt[4]_i_1_n_0\, + D => \entry_cnt[4]_i_2_n_0\, + Q => entry_cnt_reg(4), + R => ofifo_rst + ); +mem_reg_0_15_6_11_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"2727270000002700" + ) + port map ( + I0 => C_of_full, + I1 => \my_full_reg_n_0_[4]\, + I2 => \^my_empty_reg[1]_1\, + I3 => calib_wrdata_en, + I4 => \wr_ptr_timing_reg[0]_0\, + I5 => mc_wrdata_en, + O => wr_en_2 + ); +\my_empty[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => C_of_full, + I1 => mux_wrdata_en, + I2 => \my_full_reg_n_0_[4]\, + I3 => \^my_empty_reg[1]_1\, + I4 => my_empty0, + I5 => ofifo_rst, + O => \my_empty[1]_i_1__1_n_0\ + ); +\my_empty[7]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => C_of_full, + I1 => mux_wrdata_en, + I2 => \my_full_reg_n_0_[4]\, + I3 => \my_empty_reg_n_0_[7]\, + I4 => my_empty0, + I5 => ofifo_rst, + O => \my_empty[7]_i_1__0_n_0\ + ); +\my_empty[7]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => wr_ptr_timing(2), + I1 => \my_empty[7]_i_4__0_n_0\, + I2 => wr_ptr_timing(3), + I3 => \my_empty[7]_i_5__0_n_0\, + I4 => \^rd_ptr_reg[2]_0\, + O => my_empty0 + ); +\my_empty[7]_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => wr_ptr_timing(1), + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + I3 => \^rd_ptr_reg[3]_0\, + I4 => wr_ptr_timing(0), + O => \my_empty[7]_i_4__0_n_0\ + ); +\my_empty[7]_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(1), + I2 => \^rd_ptr_reg[0]_0\, + I3 => \^rd_ptr_reg[1]_0\, + I4 => \^rd_ptr_reg[3]_0\, + O => \my_empty[7]_i_5__0_n_0\ + ); +\my_empty_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[1]_i_1__1_n_0\, + Q => \^my_empty_reg[1]_1\, + R => '0' + ); +\my_empty_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[7]_i_1__0_n_0\, + Q => \my_empty_reg_n_0_[7]\, + R => '0' + ); +\my_full[4]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFC0080" + ) + port map ( + I0 => my_full0, + I1 => mux_wrdata_en, + I2 => C_of_full, + I3 => \my_empty_reg_n_0_[7]\, + I4 => \my_full_reg_n_0_[4]\, + I5 => ofifo_rst, + O => \my_full[4]_i_1__0_n_0\ + ); +\my_full[4]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => rd_ptr_timing(2), + I1 => \my_full[4]_i_3__0_n_0\, + I2 => rd_ptr_timing(3), + I3 => \my_full[4]_i_4__0_n_0\, + I4 => \^q\(2), + O => my_full0 + ); +\my_full[4]_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => rd_ptr_timing(1), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + I4 => rd_ptr_timing(0), + O => \my_full[4]_i_3__0_n_0\ + ); +\my_full[4]_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => rd_ptr_timing(0), + I1 => rd_ptr_timing(1), + I2 => \^q\(0), + I3 => \^q\(1), + I4 => \^q\(3), + O => \my_full[4]_i_4__0_n_0\ + ); +\my_full_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[4]_i_1__0_n_0\, + Q => \my_full_reg_n_0_[4]\, + R => '0' + ); +ofs_rdy_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => entry_cnt_reg(4), + I1 => entry_cnt_reg(2), + I2 => entry_cnt_reg(3), + I3 => ofs_rdy_r_reg(2), + I4 => ofs_rdy_r_reg(0), + I5 => ofs_rdy_r_reg(1), + O => phy_mc_data_full + ); +\out_fifo_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000DFD5" + ) + port map ( + I0 => \^my_empty_reg[1]_1\, + I1 => mc_wrdata_en, + I2 => \wr_ptr_timing_reg[0]_0\, + I3 => calib_wrdata_en, + I4 => C_of_full, + O => \my_empty_reg[1]_0\ + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(0), + Q => \^rd_ptr_reg[0]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(1), + Q => \^rd_ptr_reg[1]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(2), + Q => \^rd_ptr_reg[2]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(3), + Q => \^rd_ptr_reg[3]_0\, + R => ofifo_rst + ); +\rd_ptr_timing[0]_i_1__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[0]_0\, + O => nxt_rd_ptr(0) + ); +\rd_ptr_timing[1]_i_1__3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + O => nxt_rd_ptr(1) + ); +\rd_ptr_timing[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => \^rd_ptr_reg[2]_0\, + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + I3 => \^rd_ptr_reg[3]_0\, + O => nxt_rd_ptr(2) + ); +\rd_ptr_timing[3]_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => C_of_full, + I1 => \my_empty_reg_n_0_[7]\, + O => \rd_ptr_timing[3]_i_1__1_n_0\ + ); +\rd_ptr_timing[3]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[1]_0\, + I2 => \^rd_ptr_reg[0]_0\, + I3 => \^rd_ptr_reg[2]_0\, + O => nxt_rd_ptr(3) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(0), + Q => rd_ptr_timing(0), + R => ofifo_rst + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(1), + Q => rd_ptr_timing(1), + R => ofifo_rst + ); +\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(2), + Q => rd_ptr_timing(2), + R => ofifo_rst + ); +\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__1_n_0\, + D => nxt_rd_ptr(3), + Q => rd_ptr_timing(3), + R => ofifo_rst + ); +\wr_ptr[0]_i_1__3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(0), + O => nxt_wr_ptr(0) + ); +\wr_ptr[1]_i_1__3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(0), + I2 => \^q\(1), + O => nxt_wr_ptr(1) + ); +\wr_ptr[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + O => nxt_wr_ptr(2) + ); +\wr_ptr[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000E20000E2E2E2" + ) + port map ( + I0 => calib_wrdata_en, + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => mc_wrdata_en, + I3 => C_of_full, + I4 => \my_full_reg_n_0_[4]\, + I5 => \my_empty_reg_n_0_[7]\, + O => wr_ptr0 + ); +\wr_ptr[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(2), + O => nxt_wr_ptr(3) + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(0), + Q => \^q\(0), + R => ofifo_rst + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(1), + Q => \^q\(1), + R => ofifo_rst + ); +\wr_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(2), + Q => \^q\(2), + R => ofifo_rst + ); +\wr_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(3), + Q => \^q\(3), + R => ofifo_rst + ); +\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(0), + Q => wr_ptr_timing(0), + R => ofifo_rst + ); +\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(1), + Q => wr_ptr_timing(1), + R => ofifo_rst + ); +\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(2), + Q => wr_ptr_timing(2), + R => ofifo_rst + ); +\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_ptr0, + D => nxt_wr_ptr(3), + Q => wr_ptr_timing(3), + R => ofifo_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_9\ is + port ( + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + \my_empty_reg[1]_0\ : out STD_LOGIC; + \my_empty_reg[1]_1\ : out STD_LOGIC; + D2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + D6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + D9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + ofifo_rst : in STD_LOGIC; + CLK : in STD_LOGIC; + calib_cmd_wren : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + \rd_ptr_reg[3]_1\ : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mux_cmd_wren : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_9\ : entity is "mig_7series_v4_2_ddr_of_pre_fifo"; +end \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_9\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_9\ is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal my_empty0 : STD_LOGIC; + signal \my_empty[1]_i_1__0_n_0\ : STD_LOGIC; + signal \my_empty[6]_i_1_n_0\ : STD_LOGIC; + signal \my_empty[6]_i_3_n_0\ : STD_LOGIC; + signal \my_empty[6]_i_4_n_0\ : STD_LOGIC; + signal \^my_empty_reg[1]_0\ : STD_LOGIC; + signal \my_empty_reg_n_0_[6]\ : STD_LOGIC; + signal my_full0 : STD_LOGIC; + signal \my_full[3]_i_1_n_0\ : STD_LOGIC; + signal \my_full[3]_i_3_n_0\ : STD_LOGIC; + signal \my_full[3]_i_4_n_0\ : STD_LOGIC; + signal \my_full_reg_n_0_[3]\ : STD_LOGIC; + signal nxt_rd_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal nxt_wr_ptr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^rd_ptr_reg[0]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[1]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[2]_0\ : STD_LOGIC; + signal \^rd_ptr_reg[3]_0\ : STD_LOGIC; + signal rd_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \rd_ptr_timing[3]_i_1__0_n_0\ : STD_LOGIC; + signal \wr_ptr0__0\ : STD_LOGIC; + signal wr_ptr_timing : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \my_empty[6]_i_3\ : label is "soft_lutpair463"; + attribute SOFT_HLUTNM of \my_empty[6]_i_4\ : label is "soft_lutpair463"; + attribute syn_maxfan : string; + attribute syn_maxfan of \my_empty_reg[1]\ : label is "3"; + attribute syn_maxfan of \my_empty_reg[6]\ : label is "3"; + attribute SOFT_HLUTNM of \my_full[3]_i_3\ : label is "soft_lutpair464"; + attribute SOFT_HLUTNM of \my_full[3]_i_4\ : label is "soft_lutpair464"; + attribute syn_maxfan of \my_full_reg[3]\ : label is "3"; + attribute SOFT_HLUTNM of \out_fifo_i_10__1\ : label is "soft_lutpair465"; + attribute SOFT_HLUTNM of \out_fifo_i_1__0\ : label is "soft_lutpair465"; + attribute SOFT_HLUTNM of \out_fifo_i_34__1\ : label is "soft_lutpair470"; + attribute SOFT_HLUTNM of \out_fifo_i_46__1\ : label is "soft_lutpair470"; + attribute syn_maxfan of \rd_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \rd_ptr_reg[3]\ : label is "10"; + attribute SOFT_HLUTNM of \rd_ptr_timing[0]_i_1__0\ : label is "soft_lutpair468"; + attribute SOFT_HLUTNM of \rd_ptr_timing[1]_i_1__0\ : label is "soft_lutpair468"; + attribute SOFT_HLUTNM of \rd_ptr_timing[2]_i_1__0\ : label is "soft_lutpair466"; + attribute SOFT_HLUTNM of \rd_ptr_timing[3]_i_2__0\ : label is "soft_lutpair466"; + attribute KEEP : string; + attribute KEEP of \rd_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \rd_ptr_timing_reg[3]\ : label is "yes"; + attribute SOFT_HLUTNM of \wr_ptr[0]_i_1__2\ : label is "soft_lutpair469"; + attribute SOFT_HLUTNM of \wr_ptr[1]_i_1__2\ : label is "soft_lutpair469"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__0\ : label is "soft_lutpair467"; + attribute SOFT_HLUTNM of \wr_ptr[3]_i_1__0\ : label is "soft_lutpair467"; + attribute syn_maxfan of \wr_ptr_reg[0]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[1]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[2]\ : label is "10"; + attribute syn_maxfan of \wr_ptr_reg[3]\ : label is "10"; + attribute KEEP of \wr_ptr_timing_reg[0]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[1]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[2]\ : label is "yes"; + attribute KEEP of \wr_ptr_timing_reg[3]\ : label is "yes"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); + \my_empty_reg[1]_0\ <= \^my_empty_reg[1]_0\; + \rd_ptr_reg[0]_0\ <= \^rd_ptr_reg[0]_0\; + \rd_ptr_reg[1]_0\ <= \^rd_ptr_reg[1]_0\; + \rd_ptr_reg[2]_0\ <= \^rd_ptr_reg[2]_0\; + \rd_ptr_reg[3]_0\ <= \^rd_ptr_reg[3]_0\; +\my_empty[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => \rd_ptr_reg[3]_1\, + I1 => mux_cmd_wren, + I2 => \my_full_reg_n_0_[3]\, + I3 => \^my_empty_reg[1]_0\, + I4 => my_empty0, + I5 => ofifo_rst, + O => \my_empty[1]_i_1__0_n_0\ + ); +\my_empty[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF701F700" + ) + port map ( + I0 => \rd_ptr_reg[3]_1\, + I1 => mux_cmd_wren, + I2 => \my_full_reg_n_0_[3]\, + I3 => \my_empty_reg_n_0_[6]\, + I4 => my_empty0, + I5 => ofifo_rst, + O => \my_empty[6]_i_1_n_0\ + ); +\my_empty[6]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => wr_ptr_timing(2), + I1 => \my_empty[6]_i_3_n_0\, + I2 => wr_ptr_timing(3), + I3 => \my_empty[6]_i_4_n_0\, + I4 => \^rd_ptr_reg[2]_0\, + O => my_empty0 + ); +\my_empty[6]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => wr_ptr_timing(1), + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + I3 => \^rd_ptr_reg[3]_0\, + I4 => wr_ptr_timing(0), + O => \my_empty[6]_i_3_n_0\ + ); +\my_empty[6]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => wr_ptr_timing(0), + I1 => wr_ptr_timing(1), + I2 => \^rd_ptr_reg[0]_0\, + I3 => \^rd_ptr_reg[1]_0\, + I4 => \^rd_ptr_reg[3]_0\, + O => \my_empty[6]_i_4_n_0\ + ); +\my_empty_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[1]_i_1__0_n_0\, + Q => \^my_empty_reg[1]_0\, + R => '0' + ); +\my_empty_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_empty[6]_i_1_n_0\, + Q => \my_empty_reg_n_0_[6]\, + R => '0' + ); +\my_full[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFC0080" + ) + port map ( + I0 => my_full0, + I1 => mux_cmd_wren, + I2 => \rd_ptr_reg[3]_1\, + I3 => \my_empty_reg_n_0_[6]\, + I4 => \my_full_reg_n_0_[3]\, + I5 => ofifo_rst, + O => \my_full[3]_i_1_n_0\ + ); +\my_full[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"4A400D08" + ) + port map ( + I0 => rd_ptr_timing(2), + I1 => \my_full[3]_i_3_n_0\, + I2 => rd_ptr_timing(3), + I3 => \my_full[3]_i_4_n_0\, + I4 => \^q\(2), + O => my_full0 + ); +\my_full[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => rd_ptr_timing(1), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + I4 => rd_ptr_timing(0), + O => \my_full[3]_i_3_n_0\ + ); +\my_full[3]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"84210842" + ) + port map ( + I0 => rd_ptr_timing(0), + I1 => rd_ptr_timing(1), + I2 => \^q\(0), + I3 => \^q\(1), + I4 => \^q\(3), + O => \my_full[3]_i_4_n_0\ + ); +\my_full_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \my_full[3]_i_1_n_0\, + Q => \my_full_reg_n_0_[3]\, + R => '0' + ); +\out_fifo_i_10__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => mem_out(0), + I1 => \^my_empty_reg[1]_0\, + O => D2(0) + ); +\out_fifo_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00FD" + ) + port map ( + I0 => \^my_empty_reg[1]_0\, + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => calib_cmd_wren, + I3 => \rd_ptr_reg[3]_1\, + O => \my_empty_reg[1]_1\ + ); +\out_fifo_i_34__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => mem_out(1), + I1 => \^my_empty_reg[1]_0\, + O => D6(0) + ); +\out_fifo_i_46__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => mem_out(2), + I1 => \^my_empty_reg[1]_0\, + O => D9(0) + ); +p_17_out: unisim.vcomponents.LUT5 + generic map( + INIT => X"27272700" + ) + port map ( + I0 => \rd_ptr_reg[3]_1\, + I1 => \my_full_reg_n_0_[3]\, + I2 => \^my_empty_reg[1]_0\, + I3 => calib_cmd_wren, + I4 => \wr_ptr_timing_reg[0]_0\, + O => wr_en_3 + ); +\rd_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(0), + Q => \^rd_ptr_reg[0]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(1), + Q => \^rd_ptr_reg[1]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(2), + Q => \^rd_ptr_reg[2]_0\, + R => ofifo_rst + ); +\rd_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(3), + Q => \^rd_ptr_reg[3]_0\, + R => ofifo_rst + ); +\rd_ptr_timing[0]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[0]_0\, + O => nxt_rd_ptr(0) + ); +\rd_ptr_timing[1]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + O => nxt_rd_ptr(1) + ); +\rd_ptr_timing[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => \^rd_ptr_reg[2]_0\, + I1 => \^rd_ptr_reg[0]_0\, + I2 => \^rd_ptr_reg[1]_0\, + I3 => \^rd_ptr_reg[3]_0\, + O => nxt_rd_ptr(2) + ); +\rd_ptr_timing[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \rd_ptr_reg[3]_1\, + I1 => \my_empty_reg_n_0_[6]\, + O => \rd_ptr_timing[3]_i_1__0_n_0\ + ); +\rd_ptr_timing[3]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^rd_ptr_reg[3]_0\, + I1 => \^rd_ptr_reg[1]_0\, + I2 => \^rd_ptr_reg[0]_0\, + I3 => \^rd_ptr_reg[2]_0\, + O => nxt_rd_ptr(3) + ); +\rd_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(0), + Q => rd_ptr_timing(0), + R => ofifo_rst + ); +\rd_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(1), + Q => rd_ptr_timing(1), + R => ofifo_rst + ); +\rd_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(2), + Q => rd_ptr_timing(2), + R => ofifo_rst + ); +\rd_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rd_ptr_timing[3]_i_1__0_n_0\, + D => nxt_rd_ptr(3), + Q => rd_ptr_timing(3), + R => ofifo_rst + ); +wr_ptr0: unisim.vcomponents.LUT5 + generic map( + INIT => X"00E00EEE" + ) + port map ( + I0 => calib_cmd_wren, + I1 => \wr_ptr_timing_reg[0]_0\, + I2 => \rd_ptr_reg[3]_1\, + I3 => \my_full_reg_n_0_[3]\, + I4 => \my_empty_reg_n_0_[6]\, + O => \wr_ptr0__0\ + ); +\wr_ptr[0]_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(0), + O => nxt_wr_ptr(0) + ); +\wr_ptr[1]_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(0), + I2 => \^q\(1), + O => nxt_wr_ptr(1) + ); +\wr_ptr[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA6A" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + O => nxt_wr_ptr(2) + ); +\wr_ptr[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(2), + O => nxt_wr_ptr(3) + ); +\wr_ptr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(0), + Q => \^q\(0), + R => ofifo_rst + ); +\wr_ptr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(1), + Q => \^q\(1), + R => ofifo_rst + ); +\wr_ptr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(2), + Q => \^q\(2), + R => ofifo_rst + ); +\wr_ptr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(3), + Q => \^q\(3), + R => ofifo_rst + ); +\wr_ptr_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(0), + Q => wr_ptr_timing(0), + R => ofifo_rst + ); +\wr_ptr_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(1), + Q => wr_ptr_timing(1), + R => ofifo_rst + ); +\wr_ptr_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(2), + Q => wr_ptr_timing(2), + R => ofifo_rst + ); +\wr_ptr_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wr_ptr0__0\, + D => nxt_wr_ptr(3), + Q => wr_ptr_timing(3), + R => ofifo_rst + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay is + port ( + ck_addr_cmd_delay_done : out STD_LOGIC; + cmd_po_en_stg2_f : out STD_LOGIC; + po_cnt_dec_0 : out STD_LOGIC; + \ctl_lane_cnt_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + delay_done_r4_reg_0 : out STD_LOGIC; + \ctl_lane_cnt_reg[1]_0\ : out STD_LOGIC; + CLK : in STD_LOGIC; + po_en_stg2_f_reg_0 : in STD_LOGIC; + p_1_in : in STD_LOGIC; + \wait_cnt_r_reg[0]_0\ : in STD_LOGIC; + \wait_cnt_r_reg[0]_1\ : in STD_LOGIC; + delay_dec_done_reg_0 : in STD_LOGIC; + cnt_pwron_cke_done_r : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + cmd_delay_start0 : in STD_LOGIC; + rd_data_offset_cal_done : in STD_LOGIC; + \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ : in STD_LOGIC; + \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0\ : in STD_LOGIC; + \wait_cnt_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay : entity is "mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay"; +end ddr3_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay is + signal \^ck_addr_cmd_delay_done\ : STD_LOGIC; + signal ctl_lane_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \ctl_lane_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \ctl_lane_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \ctl_lane_cnt[1]_i_3_n_0\ : STD_LOGIC; + signal \^ctl_lane_cnt_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal delay_dec_done : STD_LOGIC; + signal delay_dec_done_i_1_n_0 : STD_LOGIC; + signal delay_dec_done_i_2_n_0 : STD_LOGIC; + signal delay_done_r3_reg_srl3_n_0 : STD_LOGIC; + signal delaydec_cnt_r0 : STD_LOGIC; + signal \delaydec_cnt_r0__0\ : STD_LOGIC_VECTOR ( 5 downto 1 ); + signal \delaydec_cnt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \delaydec_cnt_r[5]_i_1_n_0\ : STD_LOGIC; + signal delaydec_cnt_r_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \^po_cnt_dec_0\ : STD_LOGIC; + signal \po_cnt_dec_i_1__0_n_0\ : STD_LOGIC; + signal wait_cnt_r0 : STD_LOGIC; + signal \wait_cnt_r0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wait_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \ctl_lane_cnt[0]_i_1\ : label is "soft_lutpair217"; + attribute SOFT_HLUTNM of \ctl_lane_cnt[1]_i_1\ : label is "soft_lutpair217"; + attribute srl_name : string; + attribute srl_name of delay_done_r3_reg_srl3 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 "; + attribute syn_maxfan : string; + attribute syn_maxfan of delay_done_r4_reg : label is "10"; + attribute SOFT_HLUTNM of \delaydec_cnt_r[0]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \delaydec_cnt_r[2]_i_1\ : label is "soft_lutpair219"; + attribute SOFT_HLUTNM of \delaydec_cnt_r[3]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \delaydec_cnt_r[4]_i_1\ : label is "soft_lutpair218"; + attribute SOFT_HLUTNM of \wait_cnt_r[1]_i_1\ : label is "soft_lutpair220"; + attribute SOFT_HLUTNM of \wait_cnt_r[2]_i_1\ : label is "soft_lutpair220"; +begin + ck_addr_cmd_delay_done <= \^ck_addr_cmd_delay_done\; + \ctl_lane_cnt_reg[0]_0\(0) <= \^ctl_lane_cnt_reg[0]_0\(0); + po_cnt_dec_0 <= \^po_cnt_dec_0\; +\ctl_lane_cnt[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CCC7" + ) + port map ( + I0 => ctl_lane_cnt(1), + I1 => \^ctl_lane_cnt_reg[0]_0\(0), + I2 => delaydec_cnt_r_reg(0), + I3 => \ctl_lane_cnt[1]_i_3_n_0\, + I4 => p_1_in, + O => \ctl_lane_cnt[0]_i_1_n_0\ + ); +\ctl_lane_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"54550000" + ) + port map ( + I0 => p_1_in, + I1 => \ctl_lane_cnt[1]_i_3_n_0\, + I2 => delaydec_cnt_r_reg(0), + I3 => \^ctl_lane_cnt_reg[0]_0\(0), + I4 => ctl_lane_cnt(1), + O => \ctl_lane_cnt[1]_i_1_n_0\ + ); +\ctl_lane_cnt[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => delaydec_cnt_r_reg(4), + I1 => delaydec_cnt_r_reg(2), + I2 => delaydec_cnt_r_reg(1), + I3 => delaydec_cnt_r_reg(3), + I4 => delaydec_cnt_r_reg(5), + O => \ctl_lane_cnt[1]_i_3_n_0\ + ); +\ctl_lane_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ctl_lane_cnt[0]_i_1_n_0\, + Q => \^ctl_lane_cnt_reg[0]_0\(0), + R => '0' + ); +\ctl_lane_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ctl_lane_cnt[1]_i_1_n_0\, + Q => ctl_lane_cnt(1), + R => '0' + ); +delay_dec_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAE0000" + ) + port map ( + I0 => delay_dec_done, + I1 => \^ctl_lane_cnt_reg[0]_0\(0), + I2 => ctl_lane_cnt(1), + I3 => delay_dec_done_i_2_n_0, + I4 => cmd_delay_start0, + I5 => delay_dec_done_reg_0, + O => delay_dec_done_i_1_n_0 + ); +delay_dec_done_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => delaydec_cnt_r_reg(5), + I1 => delaydec_cnt_r_reg(3), + I2 => delaydec_cnt_r_reg(1), + I3 => delaydec_cnt_r_reg(2), + I4 => delaydec_cnt_r_reg(4), + I5 => delaydec_cnt_r_reg(0), + O => delay_dec_done_i_2_n_0 + ); +delay_dec_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => delay_dec_done_i_1_n_0, + Q => delay_dec_done, + R => '0' + ); +delay_done_r3_reg_srl3: unisim.vcomponents.SRL16E + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => delay_dec_done, + Q => delay_done_r3_reg_srl3_n_0 + ); +delay_done_r4_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => delay_done_r3_reg_srl3_n_0, + Q => \^ck_addr_cmd_delay_done\, + R => '0' + ); +\delaydec_cnt_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => delaydec_cnt_r_reg(0), + O => \delaydec_cnt_r[0]_i_1_n_0\ + ); +\delaydec_cnt_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => delaydec_cnt_r_reg(1), + I1 => delaydec_cnt_r_reg(0), + O => \delaydec_cnt_r0__0\(1) + ); +\delaydec_cnt_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => delaydec_cnt_r_reg(0), + I1 => delaydec_cnt_r_reg(1), + I2 => delaydec_cnt_r_reg(2), + O => \delaydec_cnt_r0__0\(2) + ); +\delaydec_cnt_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => delaydec_cnt_r_reg(0), + I1 => delaydec_cnt_r_reg(2), + I2 => delaydec_cnt_r_reg(1), + I3 => delaydec_cnt_r_reg(3), + O => \delaydec_cnt_r0__0\(3) + ); +\delaydec_cnt_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0001" + ) + port map ( + I0 => delaydec_cnt_r_reg(0), + I1 => delaydec_cnt_r_reg(3), + I2 => delaydec_cnt_r_reg(1), + I3 => delaydec_cnt_r_reg(2), + I4 => delaydec_cnt_r_reg(4), + O => \delaydec_cnt_r0__0\(4) + ); +\delaydec_cnt_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF45FFFFFF" + ) + port map ( + I0 => delay_dec_done_i_2_n_0, + I1 => ctl_lane_cnt(1), + I2 => \^ctl_lane_cnt_reg[0]_0\(0), + I3 => \wait_cnt_r_reg[0]_0\, + I4 => \wait_cnt_r_reg[0]_1\, + I5 => delay_dec_done_reg_0, + O => \delaydec_cnt_r[5]_i_1_n_0\ + ); +\delaydec_cnt_r[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => delay_dec_done_i_2_n_0, + I1 => \^po_cnt_dec_0\, + O => delaydec_cnt_r0 + ); +\delaydec_cnt_r[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000001" + ) + port map ( + I0 => delaydec_cnt_r_reg(0), + I1 => delaydec_cnt_r_reg(4), + I2 => delaydec_cnt_r_reg(2), + I3 => delaydec_cnt_r_reg(1), + I4 => delaydec_cnt_r_reg(3), + I5 => delaydec_cnt_r_reg(5), + O => \delaydec_cnt_r0__0\(5) + ); +\delaydec_cnt_r_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => delaydec_cnt_r0, + D => \delaydec_cnt_r[0]_i_1_n_0\, + Q => delaydec_cnt_r_reg(0), + S => \delaydec_cnt_r[5]_i_1_n_0\ + ); +\delaydec_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => delaydec_cnt_r0, + D => \delaydec_cnt_r0__0\(1), + Q => delaydec_cnt_r_reg(1), + R => \delaydec_cnt_r[5]_i_1_n_0\ + ); +\delaydec_cnt_r_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => delaydec_cnt_r0, + D => \delaydec_cnt_r0__0\(2), + Q => delaydec_cnt_r_reg(2), + S => \delaydec_cnt_r[5]_i_1_n_0\ + ); +\delaydec_cnt_r_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => delaydec_cnt_r0, + D => \delaydec_cnt_r0__0\(3), + Q => delaydec_cnt_r_reg(3), + S => \delaydec_cnt_r[5]_i_1_n_0\ + ); +\delaydec_cnt_r_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => delaydec_cnt_r0, + D => \delaydec_cnt_r0__0\(4), + Q => delaydec_cnt_r_reg(4), + S => \delaydec_cnt_r[5]_i_1_n_0\ + ); +\delaydec_cnt_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => delaydec_cnt_r0, + D => \delaydec_cnt_r0__0\(5), + Q => delaydec_cnt_r_reg(5), + R => \delaydec_cnt_r[5]_i_1_n_0\ + ); +\gen_byte_sel_div2.ctl_lane_sel[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFB3BFB08080808" + ) + port map ( + I0 => ctl_lane_cnt(1), + I1 => cmd_delay_start0, + I2 => \^ck_addr_cmd_delay_done\, + I3 => rd_data_offset_cal_done, + I4 => \gen_byte_sel_div2.ctl_lane_sel_reg[1]\, + I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0\, + O => \ctl_lane_cnt_reg[1]_0\ + ); +\init_state_r[0]_i_24\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \^ck_addr_cmd_delay_done\, + I1 => cnt_pwron_cke_done_r, + I2 => Q(0), + O => delay_done_r4_reg_0 + ); +\po_cnt_dec_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001000000000" + ) + port map ( + I0 => p_1_in, + I1 => wait_cnt_r_reg(1), + I2 => wait_cnt_r_reg(0), + I3 => wait_cnt_r_reg(3), + I4 => wait_cnt_r_reg(2), + I5 => delay_dec_done_i_2_n_0, + O => \po_cnt_dec_i_1__0_n_0\ + ); +po_cnt_dec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \po_cnt_dec_i_1__0_n_0\, + Q => \^po_cnt_dec_0\, + R => '0' + ); +po_en_stg2_f_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^po_cnt_dec_0\, + Q => cmd_po_en_stg2_f, + R => po_en_stg2_f_reg_0 + ); +\wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => wait_cnt_r_reg(0), + O => \wait_cnt_r0__0\(0) + ); +\wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => wait_cnt_r_reg(1), + I1 => wait_cnt_r_reg(0), + O => \wait_cnt_r0__0\(1) + ); +\wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => wait_cnt_r_reg(2), + I1 => wait_cnt_r_reg(0), + I2 => wait_cnt_r_reg(1), + O => \wait_cnt_r0__0\(2) + ); +\wait_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFE000000000000" + ) + port map ( + I0 => wait_cnt_r_reg(3), + I1 => wait_cnt_r_reg(1), + I2 => wait_cnt_r_reg(0), + I3 => wait_cnt_r_reg(2), + I4 => \wait_cnt_r_reg[0]_1\, + I5 => \wait_cnt_r_reg[0]_0\, + O => wait_cnt_r0 + ); +\wait_cnt_r[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => wait_cnt_r_reg(3), + I1 => wait_cnt_r_reg(1), + I2 => wait_cnt_r_reg(0), + I3 => wait_cnt_r_reg(2), + O => \wait_cnt_r0__0\(3) + ); +\wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r0__0\(0), + Q => wait_cnt_r_reg(0), + R => \wait_cnt_r_reg[0]_2\(0) + ); +\wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r0__0\(1), + Q => wait_cnt_r_reg(1), + R => \wait_cnt_r_reg[0]_2\(0) + ); +\wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r0__0\(2), + Q => wait_cnt_r_reg(2), + R => \wait_cnt_r_reg[0]_2\(0) + ); +\wait_cnt_r_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r0__0\(3), + Q => wait_cnt_r_reg(3), + S => \wait_cnt_r_reg[0]_2\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr is + port ( + rd_data_offset_cal_done : out STD_LOGIC; + pi_dqs_found_rank_done : out STD_LOGIC; + pi_dqs_found_done : out STD_LOGIC; + fine_adjust_done_r_reg_0 : out STD_LOGIC; + dqs_found_prech_req : out STD_LOGIC; + ck_po_stg2_f_indec : out STD_LOGIC; + ck_po_stg2_f_en : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg\ : out STD_LOGIC; + \calib_sel_reg[1]\ : out STD_LOGIC; + \calib_sel_reg[1]_0\ : out STD_LOGIC; + ck_po_stg2_f_indec_reg_0 : out STD_LOGIC; + \pi_rst_stg1_cal_reg[0]_0\ : out STD_LOGIC; + calib_sel15_out : out STD_LOGIC; + pi_dqs_found_done_r1_reg : out STD_LOGIC; + pi_dqs_found_done_r1_reg_0 : out STD_LOGIC; + pi_calib_done_r1_reg : out STD_LOGIC; + pi_dqs_found_done_r1_reg_1 : out STD_LOGIC; + pi_dqs_found_done_r1_reg_2 : out STD_LOGIC; + pi_dqs_found_done_r1_reg_3 : out STD_LOGIC; + dqs_found_done_r_reg_0 : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\ : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + ififo_rst_reg0 : out STD_LOGIC; + ofifo_rst_reg0 : out STD_LOGIC; + ififo_rst_reg0_1 : out STD_LOGIC; + ofifo_rst_reg0_2 : out STD_LOGIC; + \ctl_lane_cnt_reg[0]_0\ : out STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : out STD_LOGIC; + RSTB : out STD_LOGIC; + calib_in_common4_out : out STD_LOGIC; + dqs_found_done_r_reg_1 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + pi_dqs_found_lanes : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dqs_found_start_r_reg_0 : in STD_LOGIC; + ck_po_stg2_f_en_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + first_fail_detect_reg_0 : in STD_LOGIC; + rst_dqs_find_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + ofifo_rst_reg : in STD_LOGIC; + dqs_po_stg2_f_incdec : in STD_LOGIC; + ofifo_rst_reg_0 : in STD_LOGIC; + ofifo_rst_reg_1 : in STD_LOGIC; + calib_zero_inputs : in STD_LOGIC; + ck_addr_cmd_delay_done : in STD_LOGIC; + pi_dqs_found_done_r1 : in STD_LOGIC; + pi_calib_done : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_if_reset : in STD_LOGIC; + A_rst_primitives : in STD_LOGIC; + ctl_lane_cnt : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ : in STD_LOGIC; + \calib_sel_reg[1]_1\ : in STD_LOGIC; + cmd_delay_start0 : in STD_LOGIC; + calib_sel0 : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ : in STD_LOGIC; + \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0\ : in STD_LOGIC; + \gen_byte_sel_div2.ctl_lane_sel_reg[0]_1\ : in STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_0\ : in STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_1\ : in STD_LOGIC; + init_dqsfound_done_r_reg_0 : in STD_LOGIC; + \pi_rst_stg1_cal_r_reg[0]_0\ : in STD_LOGIC; + detect_pi_found_dqs : in STD_LOGIC; + prech_done : in STD_LOGIC; + rst_dqs_find_i_4_0 : in STD_LOGIC; + \stable_pass_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr : entity is "mig_7series_v4_2_ddr_phy_dqs_found_cal_hr"; +end ddr3_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr is + signal \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_8_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\ : STD_LOGIC; + signal \FSM_sequential_fine_adj_state_r[3]_i_8_n_0\ : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal byte_sel_cnt1 : STD_LOGIC; + signal \^ck_po_stg2_f_en\ : STD_LOGIC; + signal ck_po_stg2_f_en_i_1_n_0 : STD_LOGIC; + signal \^ck_po_stg2_f_indec\ : STD_LOGIC; + signal ck_po_stg2_f_indec_i_1_n_0 : STD_LOGIC; + signal \ctl_lane_cnt[0]_i_1__0_n_0\ : STD_LOGIC; + signal ctl_lane_sel : STD_LOGIC; + signal dec_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \dec_cnt[0]_i_2_n_0\ : STD_LOGIC; + signal \dec_cnt[0]_i_3_n_0\ : STD_LOGIC; + signal \dec_cnt[0]_i_4_n_0\ : STD_LOGIC; + signal \dec_cnt[0]_i_5_n_0\ : STD_LOGIC; + signal \dec_cnt[1]_i_2_n_0\ : STD_LOGIC; + signal \dec_cnt[1]_i_3_n_0\ : STD_LOGIC; + signal \dec_cnt[2]_i_2_n_0\ : STD_LOGIC; + signal \dec_cnt[2]_i_3_n_0\ : STD_LOGIC; + signal \dec_cnt[2]_i_5_n_0\ : STD_LOGIC; + signal \dec_cnt[2]_i_6_n_0\ : STD_LOGIC; + signal \dec_cnt[2]_i_7_n_0\ : STD_LOGIC; + signal \dec_cnt[2]_i_8_n_0\ : STD_LOGIC; + signal \dec_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \dec_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_10_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_11_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_12_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_13_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_2_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_3_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_4_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_6_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_7_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_8_n_0\ : STD_LOGIC; + signal \dec_cnt[4]_i_9_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_10_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_11_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_12_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_13_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_14_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_3_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_4_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_5_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_6_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_7_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_8_n_0\ : STD_LOGIC; + signal \dec_cnt[5]_i_9_n_0\ : STD_LOGIC; + signal \dec_cnt_reg[2]_i_4_n_0\ : STD_LOGIC; + signal \dec_cnt_reg[2]_i_4_n_1\ : STD_LOGIC; + signal \dec_cnt_reg[2]_i_4_n_2\ : STD_LOGIC; + signal \dec_cnt_reg[2]_i_4_n_3\ : STD_LOGIC; + signal \dec_cnt_reg[2]_i_4_n_4\ : STD_LOGIC; + signal \dec_cnt_reg[2]_i_4_n_5\ : STD_LOGIC; + signal \dec_cnt_reg[2]_i_4_n_6\ : STD_LOGIC; + signal \dec_cnt_reg[4]_i_5_n_3\ : STD_LOGIC; + signal \dec_cnt_reg[4]_i_5_n_6\ : STD_LOGIC; + signal \dec_cnt_reg[4]_i_5_n_7\ : STD_LOGIC; + signal \dec_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \dec_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \dec_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \dec_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \dec_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \dec_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal detect_rd_cnt0 : STD_LOGIC; + signal \detect_rd_cnt0__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \detect_rd_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \detect_rd_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \detect_rd_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \detect_rd_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal detect_rd_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal dqs_found_done_r0 : STD_LOGIC; + signal dqs_found_done_r_i_2_n_0 : STD_LOGIC; + signal \^dqs_found_prech_req\ : STD_LOGIC; + signal dqs_found_prech_req_i_1_n_0 : STD_LOGIC; + signal dqs_found_prech_req_i_2_n_0 : STD_LOGIC; + signal dqs_found_prech_req_i_3_n_0 : STD_LOGIC; + signal dqs_found_prech_req_i_4_n_0 : STD_LOGIC; + signal dqs_found_prech_req_i_5_n_0 : STD_LOGIC; + signal dqs_found_prech_req_i_6_n_0 : STD_LOGIC; + signal dqs_found_prech_req_i_7_n_0 : STD_LOGIC; + signal dqs_found_start_r : STD_LOGIC; + signal final_data_offset_mc : STD_LOGIC; + signal final_dec_done_i_1_n_0 : STD_LOGIC; + signal final_dec_done_reg_n_0 : STD_LOGIC; + signal fine_adj_state_r : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal fine_adjust : STD_LOGIC; + signal fine_adjust_done_r : STD_LOGIC; + signal fine_adjust_done_r_i_1_n_0 : STD_LOGIC; + signal \^fine_adjust_done_r_reg_0\ : STD_LOGIC; + signal fine_adjust_i_1_n_0 : STD_LOGIC; + signal fine_adjust_lane_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal fine_adjust_reg_n_0 : STD_LOGIC; + signal first_fail_detect : STD_LOGIC; + signal first_fail_detect_i_1_n_0 : STD_LOGIC; + signal first_fail_detect_reg_n_0 : STD_LOGIC; + signal \first_fail_taps[5]_i_2_n_0\ : STD_LOGIC; + signal \first_fail_taps_reg_n_0_[0]\ : STD_LOGIC; + signal \first_fail_taps_reg_n_0_[1]\ : STD_LOGIC; + signal \first_fail_taps_reg_n_0_[2]\ : STD_LOGIC; + signal \first_fail_taps_reg_n_0_[3]\ : STD_LOGIC; + signal \first_fail_taps_reg_n_0_[4]\ : STD_LOGIC; + signal \first_fail_taps_reg_n_0_[5]\ : STD_LOGIC; + signal inc_cnt : STD_LOGIC; + signal \inc_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal \inc_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \inc_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \inc_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \inc_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \inc_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \inc_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal init_dec_cnt : STD_LOGIC; + signal init_dec_cnt0 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \init_dec_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \init_dec_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \init_dec_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \init_dec_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \init_dec_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal init_dec_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal init_dec_done_i_1_n_0 : STD_LOGIC; + signal init_dec_done_i_2_n_0 : STD_LOGIC; + signal init_dec_done_reg_n_0 : STD_LOGIC; + signal init_dqsfound_done_r1_reg_n_0 : STD_LOGIC; + signal init_dqsfound_done_r2 : STD_LOGIC; + signal init_dqsfound_done_r4_reg_srl2_n_0 : STD_LOGIC; + signal init_dqsfound_done_r5 : STD_LOGIC; + signal init_dqsfound_done_r_i_1_n_0 : STD_LOGIC; + signal n_0_0 : STD_LOGIC; + signal n_0_1 : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 2 ); + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal p_44_out : STD_LOGIC; + signal pi_dqs_found_all_bank : STD_LOGIC; + signal \pi_dqs_found_all_bank[0]_i_1_n_0\ : STD_LOGIC; + signal pi_dqs_found_all_bank_r : STD_LOGIC; + signal pi_dqs_found_any_bank : STD_LOGIC; + signal \pi_dqs_found_any_bank[0]_i_1_n_0\ : STD_LOGIC; + signal pi_dqs_found_any_bank_r : STD_LOGIC; + signal \^pi_dqs_found_done\ : STD_LOGIC; + signal pi_dqs_found_lanes_r1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute async_reg : string; + attribute async_reg of pi_dqs_found_lanes_r1 : signal is "true"; + signal pi_dqs_found_lanes_r2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute async_reg of pi_dqs_found_lanes_r2 : signal is "true"; + signal pi_dqs_found_lanes_r3 : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute async_reg of pi_dqs_found_lanes_r3 : signal is "true"; + signal \^pi_dqs_found_rank_done\ : STD_LOGIC; + signal \pi_rst_stg1_cal[0]_i_1_n_0\ : STD_LOGIC; + signal pi_rst_stg1_cal_r : STD_LOGIC; + signal \pi_rst_stg1_cal_r1[0]_i_1_n_0\ : STD_LOGIC; + signal \pi_rst_stg1_cal_r1_reg_n_0_[0]\ : STD_LOGIC; + signal \pi_rst_stg1_cal_r[0]_i_1_n_0\ : STD_LOGIC; + signal \pi_rst_stg1_cal_r[0]_i_2_n_0\ : STD_LOGIC; + signal rank_done_r1 : STD_LOGIC; + signal rank_done_r_i_1_n_0 : STD_LOGIC; + signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\ : STD_LOGIC; + signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\ : STD_LOGIC; + signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\ : STD_LOGIC; + signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\ : STD_LOGIC; + signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\ : STD_LOGIC; + signal \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\ : STD_LOGIC; + signal \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal rd_byte_data_offset : STD_LOGIC; + signal \rd_byte_data_offset[0][1]_i_1_n_0\ : STD_LOGIC; + signal \rd_byte_data_offset[0][5]_i_1_n_0\ : STD_LOGIC; + signal \rd_byte_data_offset[0][5]_i_4_n_0\ : STD_LOGIC; + signal \rd_byte_data_offset[0][5]_i_5_n_0\ : STD_LOGIC; + signal \rd_byte_data_offset[0][5]_i_6_n_0\ : STD_LOGIC; + signal \rd_byte_data_offset_reg[0]_10\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \^rd_data_offset_cal_done\ : STD_LOGIC; + signal rd_data_offset_ranks_0 : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \rnk_cnt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \rnk_cnt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC; + signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC; + signal rst_dqs_find : STD_LOGIC; + signal \rst_dqs_find__0\ : STD_LOGIC; + signal rst_dqs_find_i_10_n_0 : STD_LOGIC; + signal rst_dqs_find_i_11_n_0 : STD_LOGIC; + signal rst_dqs_find_i_12_n_0 : STD_LOGIC; + signal rst_dqs_find_i_14_n_0 : STD_LOGIC; + signal rst_dqs_find_i_16_n_0 : STD_LOGIC; + signal rst_dqs_find_i_18_n_0 : STD_LOGIC; + signal rst_dqs_find_i_19_n_0 : STD_LOGIC; + signal rst_dqs_find_i_1_n_0 : STD_LOGIC; + signal rst_dqs_find_i_3_n_0 : STD_LOGIC; + signal rst_dqs_find_i_4_n_0 : STD_LOGIC; + signal rst_dqs_find_i_5_n_0 : STD_LOGIC; + signal rst_dqs_find_i_6_n_0 : STD_LOGIC; + signal rst_dqs_find_i_7_n_0 : STD_LOGIC; + signal rst_dqs_find_i_8_n_0 : STD_LOGIC; + signal rst_dqs_find_i_9_n_0 : STD_LOGIC; + signal rst_dqs_find_r1 : STD_LOGIC; + signal rst_dqs_find_r2 : STD_LOGIC; + signal rst_stg1_cal : STD_LOGIC; + signal stable_pass_cnt : STD_LOGIC; + signal \stable_pass_cnt[5]_i_3_n_0\ : STD_LOGIC; + signal stable_pass_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 1 ); + signal \stable_pass_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \NLW_dec_cnt_reg[2]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_dec_cnt_reg[4]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_dec_cnt_reg[4]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_1\ : label is "soft_lutpair185"; + attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_3\ : label is "soft_lutpair191"; + attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_4\ : label is "soft_lutpair181"; + attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[0]_i_5\ : label is "soft_lutpair194"; + attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_3\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of \FSM_sequential_fine_adj_state_r[1]_i_4\ : label is "soft_lutpair204"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[0]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[1]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[2]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110"; + attribute FSM_ENCODED_STATES of \FSM_sequential_fine_adj_state_r_reg[3]\ : label is "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110"; + attribute SOFT_HLUTNM of \calib_data_offset_0[0]_i_1\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \calib_data_offset_0[1]_i_1\ : label is "soft_lutpair207"; + attribute SOFT_HLUTNM of \calib_sel[0]_i_3\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of ck_po_stg2_f_en_i_1 : label is "soft_lutpair204"; + attribute SOFT_HLUTNM of ck_po_stg2_f_indec_i_1 : label is "soft_lutpair203"; + attribute SOFT_HLUTNM of \ctl_lane_cnt[0]_i_1__0\ : label is "soft_lutpair194"; + attribute SOFT_HLUTNM of \dec_cnt[0]_i_4\ : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of \dec_cnt[1]_i_3\ : label is "soft_lutpair210"; + attribute SOFT_HLUTNM of \dec_cnt[2]_i_2\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \dec_cnt[2]_i_3\ : label is "soft_lutpair184"; + attribute SOFT_HLUTNM of \dec_cnt[3]_i_2\ : label is "soft_lutpair198"; + attribute SOFT_HLUTNM of \dec_cnt[3]_i_3\ : label is "soft_lutpair184"; + attribute SOFT_HLUTNM of \dec_cnt[4]_i_10\ : label is "soft_lutpair196"; + attribute SOFT_HLUTNM of \dec_cnt[4]_i_12\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \dec_cnt[4]_i_13\ : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of \dec_cnt[4]_i_4\ : label is "soft_lutpair186"; + attribute SOFT_HLUTNM of \dec_cnt[5]_i_11\ : label is "soft_lutpair186"; + attribute SOFT_HLUTNM of \dec_cnt[5]_i_12\ : label is "soft_lutpair182"; + attribute SOFT_HLUTNM of \dec_cnt[5]_i_4\ : label is "soft_lutpair181"; + attribute SOFT_HLUTNM of \dec_cnt[5]_i_5\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \dec_cnt[5]_i_6\ : label is "soft_lutpair190"; + attribute SOFT_HLUTNM of \dec_cnt[5]_i_8\ : label is "soft_lutpair211"; + attribute SOFT_HLUTNM of \dec_cnt[5]_i_9\ : label is "soft_lutpair196"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \dec_cnt_reg[2]_i_4\ : label is 35; + attribute ADDER_THRESHOLD of \dec_cnt_reg[4]_i_5\ : label is 35; + attribute SOFT_HLUTNM of \detect_rd_cnt[1]_i_1\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \detect_rd_cnt[2]_i_1\ : label is "soft_lutpair213"; + attribute SOFT_HLUTNM of \detect_rd_cnt[3]_i_3\ : label is "soft_lutpair192"; + attribute SOFT_HLUTNM of dqs_found_done_r_i_2 : label is "soft_lutpair195"; + attribute SOFT_HLUTNM of dqs_found_prech_req_i_3 : label is "soft_lutpair203"; + attribute SOFT_HLUTNM of dqs_found_prech_req_i_4 : label is "soft_lutpair191"; + attribute SOFT_HLUTNM of dqs_found_prech_req_i_7 : label is "soft_lutpair215"; + attribute SOFT_HLUTNM of \first_fail_taps[5]_i_2\ : label is "soft_lutpair183"; + attribute SOFT_HLUTNM of \gen_byte_sel_div2.ctl_lane_sel[0]_i_2\ : label is "soft_lutpair197"; + attribute SOFT_HLUTNM of \inc_cnt[0]_i_1\ : label is "soft_lutpair216"; + attribute SOFT_HLUTNM of \inc_cnt[1]_i_1\ : label is "soft_lutpair216"; + attribute SOFT_HLUTNM of \inc_cnt[2]_i_1\ : label is "soft_lutpair210"; + attribute SOFT_HLUTNM of \inc_cnt[3]_i_1\ : label is "soft_lutpair205"; + attribute SOFT_HLUTNM of \inc_cnt[4]_i_1\ : label is "soft_lutpair189"; + attribute SOFT_HLUTNM of \init_dec_cnt[1]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \init_dec_cnt[2]_i_1\ : label is "soft_lutpair212"; + attribute SOFT_HLUTNM of \init_dec_cnt[3]_i_1\ : label is "soft_lutpair200"; + attribute SOFT_HLUTNM of \init_dec_cnt[4]_i_1\ : label is "soft_lutpair200"; + attribute SOFT_HLUTNM of init_dec_done_i_2 : label is "soft_lutpair185"; + attribute srl_name : string; + attribute srl_name of init_dqsfound_done_r4_reg_srl2 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r4_reg_srl2 "; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5\ : label is "soft_lutpair187"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_5__0\ : label is "soft_lutpair187"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \pi_dqs_found_lanes_r1_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[1]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r1_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[2]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r1_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r1_reg[3]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r1_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[0]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r2_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[1]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r2_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[2]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r2_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r2_reg[3]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r2_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[0]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r3_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[1]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r3_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[2]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r3_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \pi_dqs_found_lanes_r3_reg[3]\ : label is std.standard.true; + attribute KEEP of \pi_dqs_found_lanes_r3_reg[3]\ : label is "yes"; + attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1\ : label is "soft_lutpair207"; + attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1\ : label is "soft_lutpair214"; + attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1\ : label is "soft_lutpair199"; + attribute SOFT_HLUTNM of \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1\ : label is "soft_lutpair199"; + attribute SOFT_HLUTNM of \rd_byte_data_offset[0][1]_i_1\ : label is "soft_lutpair208"; + attribute SOFT_HLUTNM of \rd_byte_data_offset[0][3]_i_1\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \rd_byte_data_offset[0][4]_i_1\ : label is "soft_lutpair201"; + attribute SOFT_HLUTNM of \rnk_cnt_r[0]_i_1\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of \rnk_cnt_r[1]_i_1\ : label is "soft_lutpair209"; + attribute SOFT_HLUTNM of rst_dqs_find_i_11 : label is "soft_lutpair195"; + attribute SOFT_HLUTNM of rst_dqs_find_i_13 : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of rst_dqs_find_i_15 : label is "soft_lutpair190"; + attribute SOFT_HLUTNM of rst_dqs_find_i_16 : label is "soft_lutpair183"; + attribute SOFT_HLUTNM of rst_dqs_find_i_18 : label is "soft_lutpair188"; + attribute SOFT_HLUTNM of rst_dqs_find_i_19 : label is "soft_lutpair205"; + attribute SOFT_HLUTNM of rst_dqs_find_i_9 : label is "soft_lutpair193"; + attribute SOFT_HLUTNM of \stable_pass_cnt[1]_i_1\ : label is "soft_lutpair206"; + attribute SOFT_HLUTNM of \stable_pass_cnt[2]_i_1\ : label is "soft_lutpair202"; + attribute SOFT_HLUTNM of \stable_pass_cnt[3]_i_1\ : label is "soft_lutpair202"; + attribute SOFT_HLUTNM of \stable_pass_cnt[5]_i_2\ : label is "soft_lutpair206"; + attribute SOFT_HLUTNM of \stable_pass_cnt[5]_i_3\ : label is "soft_lutpair182"; +begin + Q(0) <= \^q\(0); + ck_po_stg2_f_en <= \^ck_po_stg2_f_en\; + ck_po_stg2_f_indec <= \^ck_po_stg2_f_indec\; + dqs_found_prech_req <= \^dqs_found_prech_req\; + fine_adjust_done_r_reg_0 <= \^fine_adjust_done_r_reg_0\; + pi_dqs_found_done <= \^pi_dqs_found_done\; + pi_dqs_found_rank_done <= \^pi_dqs_found_rank_done\; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5 downto 0) <= \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5 downto 0); + rd_data_offset_cal_done <= \^rd_data_offset_cal_done\; +\FSM_sequential_fine_adj_state_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEFEEEEE" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\, + I1 => \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\, + I2 => fine_adj_state_r(2), + I3 => \^q\(0), + I4 => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\, + O => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\ + ); +\FSM_sequential_fine_adj_state_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAEF" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\, + I1 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + I2 => final_dec_done_reg_n_0, + I3 => fine_adj_state_r(3), + I4 => fine_adj_state_r(1), + I5 => fine_adj_state_r(2), + O => \FSM_sequential_fine_adj_state_r[0]_i_2_n_0\ + ); +\FSM_sequential_fine_adj_state_r[0]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"CFE00000" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\, + I1 => fine_adj_state_r(2), + I2 => \^q\(0), + I3 => fine_adj_state_r(1), + I4 => fine_adj_state_r(3), + O => \FSM_sequential_fine_adj_state_r[0]_i_3_n_0\ + ); +\FSM_sequential_fine_adj_state_r[0]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => fine_adjust_lane_cnt(0), + I1 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + I2 => \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\, + O => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\ + ); +\FSM_sequential_fine_adj_state_r[0]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F0110011" + ) + port map ( + I0 => \^q\(0), + I1 => fine_adj_state_r(3), + I2 => fine_adj_state_r(2), + I3 => fine_adj_state_r(1), + I4 => fine_adjust_lane_cnt(0), + O => \FSM_sequential_fine_adj_state_r[0]_i_5_n_0\ + ); +\FSM_sequential_fine_adj_state_r[0]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \dec_cnt_reg_n_0_[4]\, + I1 => \dec_cnt_reg_n_0_[2]\, + I2 => \dec_cnt_reg_n_0_[0]\, + I3 => \dec_cnt_reg_n_0_[1]\, + I4 => \dec_cnt_reg_n_0_[3]\, + I5 => \dec_cnt_reg_n_0_[5]\, + O => \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFAABA" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\, + I1 => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\, + I2 => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\, + I3 => fine_adj_state_r(2), + I4 => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\, + I5 => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\, + O => \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF19090808" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => \^q\(0), + I2 => fine_adj_state_r(1), + I3 => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\, + I4 => fine_adj_state_r(3), + I5 => \FSM_sequential_fine_adj_state_r[1]_i_8_n_0\, + O => \FSM_sequential_fine_adj_state_r[1]_i_2_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFF7" + ) + port map ( + I0 => detect_pi_found_dqs, + I1 => detect_rd_cnt_reg(0), + I2 => detect_rd_cnt_reg(3), + I3 => detect_rd_cnt_reg(1), + I4 => detect_rd_cnt_reg(2), + O => \FSM_sequential_fine_adj_state_r[1]_i_3_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => fine_adj_state_r(3), + I1 => fine_adj_state_r(1), + O => \FSM_sequential_fine_adj_state_r[1]_i_4_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800080008000000" + ) + port map ( + I0 => \dec_cnt[5]_i_5_n_0\, + I1 => fine_adj_state_r(3), + I2 => fine_adj_state_r(2), + I3 => \dec_cnt[5]_i_12_n_0\, + I4 => first_fail_detect_reg_n_0, + I5 => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\, + O => \FSM_sequential_fine_adj_state_r[1]_i_5_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000005500D000" + ) + port map ( + I0 => fine_adj_state_r(3), + I1 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\, + I2 => pi_dqs_found_all_bank, + I3 => fine_adj_state_r(1), + I4 => fine_adj_state_r(2), + I5 => \^q\(0), + O => \FSM_sequential_fine_adj_state_r[1]_i_6_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF8AFF" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => detect_pi_found_dqs, + I3 => \dec_cnt[5]_i_3_n_0\, + I4 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\, + O => \FSM_sequential_fine_adj_state_r[1]_i_7_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000F004400000044" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + I1 => \^q\(0), + I2 => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\, + I3 => fine_adj_state_r(1), + I4 => fine_adj_state_r(3), + I5 => fine_adj_state_r(2), + O => \FSM_sequential_fine_adj_state_r[1]_i_8_n_0\ + ); +\FSM_sequential_fine_adj_state_r[1]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAAAAAAAAAAAAA" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[5]\, + I1 => \inc_cnt_reg_n_0_[1]\, + I2 => \inc_cnt_reg_n_0_[0]\, + I3 => \inc_cnt_reg_n_0_[2]\, + I4 => \inc_cnt_reg_n_0_[4]\, + I5 => \inc_cnt_reg_n_0_[3]\, + O => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\ + ); +\FSM_sequential_fine_adj_state_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABBEEFEBBFFBBAA" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\, + I1 => fine_adj_state_r(1), + I2 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + I3 => fine_adj_state_r(3), + I4 => fine_adj_state_r(2), + I5 => \^q\(0), + O => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\ + ); +\FSM_sequential_fine_adj_state_r[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF3FAA0800000000" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => \dec_cnt[5]_i_12_n_0\, + I3 => \first_fail_taps[5]_i_2_n_0\, + I4 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\, + I5 => \dec_cnt[5]_i_6_n_0\, + O => \FSM_sequential_fine_adj_state_r[2]_i_2_n_0\ + ); +\FSM_sequential_fine_adj_state_r[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0200000000020200" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[5]\, + I1 => \inc_cnt_reg_n_0_[0]\, + I2 => \inc_cnt_reg_n_0_[1]\, + I3 => \inc_cnt_reg_n_0_[4]\, + I4 => \inc_cnt_reg_n_0_[2]\, + I5 => \inc_cnt_reg_n_0_[3]\, + O => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFFEBFEEAFFEAFEE" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\, + I1 => fine_adj_state_r(2), + I2 => fine_adj_state_r(1), + I3 => fine_adj_state_r(3), + I4 => pi_dqs_found_all_bank, + I5 => detect_pi_found_dqs, + O => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BEFBBEFABAAABAAA" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\, + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + I3 => fine_adj_state_r(2), + I4 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + I5 => \^q\(0), + O => \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFAFF4450FAFF44" + ) + port map ( + I0 => fine_adj_state_r(1), + I1 => init_dqsfound_done_r5, + I2 => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\, + I3 => fine_adj_state_r(2), + I4 => \^q\(0), + I5 => prech_done, + O => \FSM_sequential_fine_adj_state_r[3]_i_3_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF40004040" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + I3 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\, + I4 => \dec_cnt[5]_i_3_n_0\, + I5 => \FSM_sequential_fine_adj_state_r[3]_i_8_n_0\, + O => \FSM_sequential_fine_adj_state_r[3]_i_4_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => init_dec_cnt_reg(4), + I1 => init_dec_cnt_reg(2), + I2 => init_dec_cnt_reg(0), + I3 => init_dec_cnt_reg(1), + I4 => init_dec_cnt_reg(3), + I5 => init_dec_cnt_reg(5), + O => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => rst_dqs_find_r2, + I1 => pi_dqs_found_any_bank, + O => \FSM_sequential_fine_adj_state_r[3]_i_6_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001000100000" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + I1 => \inc_cnt_reg_n_0_[1]\, + I2 => \inc_cnt_reg_n_0_[3]\, + I3 => \inc_cnt_reg_n_0_[5]\, + I4 => \inc_cnt_reg_n_0_[4]\, + I5 => \inc_cnt_reg_n_0_[2]\, + O => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\ + ); +\FSM_sequential_fine_adj_state_r[3]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCCFAC000000000" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\, + I1 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\, + I2 => first_fail_detect_reg_n_0, + I3 => \dec_cnt[5]_i_12_n_0\, + I4 => \first_fail_taps[5]_i_2_n_0\, + I5 => \dec_cnt[5]_i_6_n_0\, + O => \FSM_sequential_fine_adj_state_r[3]_i_8_n_0\ + ); +\FSM_sequential_fine_adj_state_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\, + D => \FSM_sequential_fine_adj_state_r[0]_i_1_n_0\, + Q => \^q\(0), + R => rst_dqs_find_reg_0(0) + ); +\FSM_sequential_fine_adj_state_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\, + D => \FSM_sequential_fine_adj_state_r[1]_i_1_n_0\, + Q => fine_adj_state_r(1), + R => rst_dqs_find_reg_0(0) + ); +\FSM_sequential_fine_adj_state_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\, + D => \FSM_sequential_fine_adj_state_r[2]_i_1_n_0\, + Q => fine_adj_state_r(2), + R => rst_dqs_find_reg_0(0) + ); +\FSM_sequential_fine_adj_state_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \FSM_sequential_fine_adj_state_r[3]_i_1_n_0\, + D => \FSM_sequential_fine_adj_state_r[3]_i_2_n_0\, + Q => fine_adj_state_r(3), + R => rst_dqs_find_reg_0(0) + ); +\calib_data_offset_0[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDC8" + ) + port map ( + I0 => pi_dqs_found_done_r1, + I1 => rd_data_offset_ranks_0(0), + I2 => init_dqsfound_done_r2, + I3 => \rd_byte_data_offset_reg[0]_10\(0), + O => pi_dqs_found_done_r1_reg_3 + ); +\calib_data_offset_0[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDC8" + ) + port map ( + I0 => pi_dqs_found_done_r1, + I1 => rd_data_offset_ranks_0(1), + I2 => init_dqsfound_done_r2, + I3 => \rd_byte_data_offset_reg[0]_10\(1), + O => pi_dqs_found_done_r1_reg_2 + ); +\calib_data_offset_0[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDC8" + ) + port map ( + I0 => pi_dqs_found_done_r1, + I1 => rd_data_offset_ranks_0(2), + I2 => init_dqsfound_done_r2, + I3 => \rd_byte_data_offset_reg[0]_10\(2), + O => pi_dqs_found_done_r1_reg_1 + ); +\calib_data_offset_0[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55FF57F7" + ) + port map ( + I0 => pi_calib_done, + I1 => \rd_byte_data_offset_reg[0]_10\(3), + I2 => init_dqsfound_done_r2, + I3 => rd_data_offset_ranks_0(3), + I4 => pi_dqs_found_done_r1, + O => pi_calib_done_r1_reg + ); +\calib_data_offset_0[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDC8" + ) + port map ( + I0 => pi_dqs_found_done_r1, + I1 => rd_data_offset_ranks_0(4), + I2 => init_dqsfound_done_r2, + I3 => \rd_byte_data_offset_reg[0]_10\(4), + O => pi_dqs_found_done_r1_reg_0 + ); +\calib_data_offset_0[5]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CDC8" + ) + port map ( + I0 => pi_dqs_found_done_r1, + I1 => rd_data_offset_ranks_0(5), + I2 => init_dqsfound_done_r2, + I3 => \rd_byte_data_offset_reg[0]_10\(5), + O => pi_dqs_found_done_r1_reg + ); +\calib_sel[0]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \^fine_adjust_done_r_reg_0\, + I1 => \^rd_data_offset_cal_done\, + I2 => ck_addr_cmd_delay_done, + O => calib_sel15_out + ); +\calib_sel[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000051551111" + ) + port map ( + I0 => \calib_sel_reg[1]_1\, + I1 => cmd_delay_start0, + I2 => \^fine_adjust_done_r_reg_0\, + I3 => \^rd_data_offset_cal_done\, + I4 => ck_addr_cmd_delay_done, + I5 => calib_sel0, + O => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ + ); +ck_po_stg2_f_en_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FB7F2040" + ) + port map ( + I0 => \^q\(0), + I1 => fine_adj_state_r(2), + I2 => fine_adj_state_r(1), + I3 => fine_adj_state_r(3), + I4 => \^ck_po_stg2_f_en\, + O => ck_po_stg2_f_en_i_1_n_0 + ); +ck_po_stg2_f_en_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ck_po_stg2_f_en_i_1_n_0, + Q => \^ck_po_stg2_f_en\, + R => ck_po_stg2_f_en_reg_0(0) + ); +ck_po_stg2_f_indec_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"DB7F0040" + ) + port map ( + I0 => \^q\(0), + I1 => fine_adj_state_r(2), + I2 => fine_adj_state_r(1), + I3 => fine_adj_state_r(3), + I4 => \^ck_po_stg2_f_indec\, + O => ck_po_stg2_f_indec_i_1_n_0 + ); +ck_po_stg2_f_indec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ck_po_stg2_f_indec_i_1_n_0, + Q => \^ck_po_stg2_f_indec\, + R => rst_dqs_find_reg_0(0) + ); +\cmd_pipe_plus.mc_data_offset[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(0), + O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\ + ); +\ctl_lane_cnt[0]_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DBFF2400" + ) + port map ( + I0 => fine_adj_state_r(1), + I1 => fine_adj_state_r(3), + I2 => \^q\(0), + I3 => fine_adj_state_r(2), + I4 => fine_adjust_lane_cnt(0), + O => \ctl_lane_cnt[0]_i_1__0_n_0\ + ); +\ctl_lane_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ctl_lane_cnt[0]_i_1__0_n_0\, + Q => fine_adjust_lane_cnt(0), + R => ck_po_stg2_f_en_reg_0(0) + ); +\dec_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF44F4" + ) + port map ( + I0 => \dec_cnt_reg_n_0_[0]\, + I1 => \^q\(0), + I2 => \dec_cnt[4]_i_4_n_0\, + I3 => \first_fail_taps_reg_n_0_[1]\, + I4 => \dec_cnt[0]_i_2_n_0\, + I5 => \dec_cnt[0]_i_3_n_0\, + O => dec_cnt(0) + ); +\dec_cnt[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000080800080" + ) + port map ( + I0 => \dec_cnt_reg[2]_i_4_n_6\, + I1 => \dec_cnt[5]_i_9_n_0\, + I2 => first_fail_detect_reg_n_0, + I3 => detect_pi_found_dqs, + I4 => pi_dqs_found_all_bank, + I5 => \^q\(0), + O => \dec_cnt[0]_i_2_n_0\ + ); +\dec_cnt[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000C080C0F0C0C0" + ) + port map ( + I0 => \dec_cnt[0]_i_4_n_0\, + I1 => \dec_cnt_reg[2]_i_4_n_6\, + I2 => \dec_cnt[5]_i_5_n_0\, + I3 => \dec_cnt[0]_i_5_n_0\, + I4 => \inc_cnt_reg_n_0_[5]\, + I5 => \inc_cnt_reg_n_0_[1]\, + O => \dec_cnt[0]_i_3_n_0\ + ); +\dec_cnt[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + I1 => \inc_cnt_reg_n_0_[2]\, + I2 => \inc_cnt_reg_n_0_[4]\, + I3 => \inc_cnt_reg_n_0_[3]\, + O => \dec_cnt[0]_i_4_n_0\ + ); +\dec_cnt[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAABFFFFFFF" + ) + port map ( + I0 => first_fail_detect_reg_n_0, + I1 => stable_pass_cnt_reg(3), + I2 => stable_pass_cnt_reg(1), + I3 => stable_pass_cnt_reg(2), + I4 => stable_pass_cnt_reg(4), + I5 => stable_pass_cnt_reg(5), + O => \dec_cnt[0]_i_5_n_0\ + ); +\dec_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFEFEEEFEEEFEE" + ) + port map ( + I0 => \dec_cnt[1]_i_2_n_0\, + I1 => \dec_cnt[1]_i_3_n_0\, + I2 => \first_fail_taps_reg_n_0_[2]\, + I3 => \dec_cnt[4]_i_4_n_0\, + I4 => \dec_cnt_reg[2]_i_4_n_5\, + I5 => \dec_cnt[4]_i_6_n_0\, + O => dec_cnt(1) + ); +\dec_cnt[1]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"82" + ) + port map ( + I0 => \^q\(0), + I1 => \dec_cnt_reg_n_0_[1]\, + I2 => \dec_cnt_reg_n_0_[0]\, + O => \dec_cnt[1]_i_2_n_0\ + ); +\dec_cnt[1]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => \dec_cnt[4]_i_7_n_0\, + I1 => \inc_cnt_reg_n_0_[2]\, + I2 => \inc_cnt_reg_n_0_[1]\, + O => \dec_cnt[1]_i_3_n_0\ + ); +\dec_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFEFEEEFEEEFEE" + ) + port map ( + I0 => \dec_cnt[2]_i_2_n_0\, + I1 => \dec_cnt[2]_i_3_n_0\, + I2 => \first_fail_taps_reg_n_0_[3]\, + I3 => \dec_cnt[4]_i_4_n_0\, + I4 => \dec_cnt_reg[2]_i_4_n_4\, + I5 => \dec_cnt[4]_i_6_n_0\, + O => dec_cnt(2) + ); +\dec_cnt[2]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8882" + ) + port map ( + I0 => \^q\(0), + I1 => \dec_cnt_reg_n_0_[2]\, + I2 => \dec_cnt_reg_n_0_[0]\, + I3 => \dec_cnt_reg_n_0_[1]\, + O => \dec_cnt[2]_i_2_n_0\ + ); +\dec_cnt[2]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2888" + ) + port map ( + I0 => \dec_cnt[4]_i_7_n_0\, + I1 => \inc_cnt_reg_n_0_[3]\, + I2 => \inc_cnt_reg_n_0_[1]\, + I3 => \inc_cnt_reg_n_0_[2]\, + O => \dec_cnt[2]_i_3_n_0\ + ); +\dec_cnt[2]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[3]\, + I1 => \first_fail_taps_reg_n_0_[3]\, + O => \dec_cnt[2]_i_5_n_0\ + ); +\dec_cnt[2]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[2]\, + I1 => \first_fail_taps_reg_n_0_[2]\, + O => \dec_cnt[2]_i_6_n_0\ + ); +\dec_cnt[2]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[1]\, + I1 => \first_fail_taps_reg_n_0_[1]\, + O => \dec_cnt[2]_i_7_n_0\ + ); +\dec_cnt[2]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + I1 => \first_fail_taps_reg_n_0_[0]\, + O => \dec_cnt[2]_i_8_n_0\ + ); +\dec_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFEFEEEFEEEFEE" + ) + port map ( + I0 => \dec_cnt[3]_i_2_n_0\, + I1 => \dec_cnt[3]_i_3_n_0\, + I2 => \first_fail_taps_reg_n_0_[4]\, + I3 => \dec_cnt[4]_i_4_n_0\, + I4 => \dec_cnt_reg[4]_i_5_n_7\, + I5 => \dec_cnt[4]_i_6_n_0\, + O => dec_cnt(3) + ); +\dec_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88888882" + ) + port map ( + I0 => \^q\(0), + I1 => \dec_cnt_reg_n_0_[3]\, + I2 => \dec_cnt_reg_n_0_[1]\, + I3 => \dec_cnt_reg_n_0_[0]\, + I4 => \dec_cnt_reg_n_0_[2]\, + O => \dec_cnt[3]_i_2_n_0\ + ); +\dec_cnt[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"28888888" + ) + port map ( + I0 => \dec_cnt[4]_i_7_n_0\, + I1 => \inc_cnt_reg_n_0_[4]\, + I2 => \inc_cnt_reg_n_0_[2]\, + I3 => \inc_cnt_reg_n_0_[1]\, + I4 => \inc_cnt_reg_n_0_[3]\, + O => \dec_cnt[3]_i_3_n_0\ + ); +\dec_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFEFEEEFEEEFEE" + ) + port map ( + I0 => \dec_cnt[4]_i_2_n_0\, + I1 => \dec_cnt[4]_i_3_n_0\, + I2 => \first_fail_taps_reg_n_0_[5]\, + I3 => \dec_cnt[4]_i_4_n_0\, + I4 => \dec_cnt_reg[4]_i_5_n_6\, + I5 => \dec_cnt[4]_i_6_n_0\, + O => dec_cnt(4) + ); +\dec_cnt[4]_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \first_fail_taps_reg_n_0_[2]\, + I1 => \first_fail_taps_reg_n_0_[1]\, + I2 => \first_fail_taps_reg_n_0_[4]\, + I3 => \first_fail_taps_reg_n_0_[3]\, + O => \dec_cnt[4]_i_10_n_0\ + ); +\dec_cnt[4]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A2AAAAAAFBFFFFFF" + ) + port map ( + I0 => \dec_cnt[0]_i_5_n_0\, + I1 => \inc_cnt_reg_n_0_[3]\, + I2 => \dec_cnt[4]_i_13_n_0\, + I3 => \inc_cnt_reg_n_0_[0]\, + I4 => \inc_cnt_reg_n_0_[1]\, + I5 => \inc_cnt_reg_n_0_[5]\, + O => \dec_cnt[4]_i_11_n_0\ + ); +\dec_cnt[4]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[3]\, + I1 => \inc_cnt_reg_n_0_[4]\, + I2 => \inc_cnt_reg_n_0_[2]\, + I3 => \inc_cnt_reg_n_0_[0]\, + I4 => \inc_cnt_reg_n_0_[1]\, + O => \dec_cnt[4]_i_12_n_0\ + ); +\dec_cnt[4]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[2]\, + I1 => \inc_cnt_reg_n_0_[4]\, + O => \dec_cnt[4]_i_13_n_0\ + ); +\dec_cnt[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888888888882" + ) + port map ( + I0 => \^q\(0), + I1 => \dec_cnt_reg_n_0_[4]\, + I2 => \dec_cnt_reg_n_0_[2]\, + I3 => \dec_cnt_reg_n_0_[0]\, + I4 => \dec_cnt_reg_n_0_[1]\, + I5 => \dec_cnt_reg_n_0_[3]\, + O => \dec_cnt[4]_i_2_n_0\ + ); +\dec_cnt[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2888888888888888" + ) + port map ( + I0 => \dec_cnt[4]_i_7_n_0\, + I1 => \inc_cnt_reg_n_0_[5]\, + I2 => \inc_cnt_reg_n_0_[3]\, + I3 => \inc_cnt_reg_n_0_[1]\, + I4 => \inc_cnt_reg_n_0_[4]\, + I5 => \inc_cnt_reg_n_0_[2]\, + O => \dec_cnt[4]_i_3_n_0\ + ); +\dec_cnt[4]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => \dec_cnt[5]_i_3_n_0\, + I1 => detect_pi_found_dqs, + I2 => pi_dqs_found_all_bank, + I3 => \^q\(0), + I4 => first_fail_detect_i_1_n_0, + O => \dec_cnt[4]_i_4_n_0\ + ); +\dec_cnt[4]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"004F00CF004000C0" + ) + port map ( + I0 => \dec_cnt[4]_i_10_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => \first_fail_taps[5]_i_2_n_0\, + I3 => \^q\(0), + I4 => \first_fail_taps_reg_n_0_[5]\, + I5 => \dec_cnt[4]_i_11_n_0\, + O => \dec_cnt[4]_i_6_n_0\ + ); +\dec_cnt[4]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0004000000000004" + ) + port map ( + I0 => first_fail_detect_reg_n_0, + I1 => \dec_cnt[5]_i_12_n_0\, + I2 => \first_fail_taps[5]_i_2_n_0\, + I3 => \^q\(0), + I4 => \inc_cnt_reg_n_0_[5]\, + I5 => \dec_cnt[4]_i_12_n_0\, + O => \dec_cnt[4]_i_7_n_0\ + ); +\dec_cnt[4]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[5]\, + I1 => \first_fail_taps_reg_n_0_[5]\, + O => \dec_cnt[4]_i_8_n_0\ + ); +\dec_cnt[4]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[4]\, + I1 => \first_fail_taps_reg_n_0_[4]\, + O => \dec_cnt[4]_i_9_n_0\ + ); +\dec_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF4F4F4F4F4F4F4" + ) + port map ( + I0 => \dec_cnt[5]_i_3_n_0\, + I1 => stable_pass_cnt, + I2 => \dec_cnt[5]_i_4_n_0\, + I3 => \dec_cnt[5]_i_5_n_0\, + I4 => \dec_cnt[5]_i_6_n_0\, + I5 => \dec_cnt[5]_i_7_n_0\, + O => \dec_cnt[5]_i_1_n_0\ + ); +\dec_cnt[5]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"90FF909090909090" + ) + port map ( + I0 => \dec_cnt[5]_i_13_n_0\, + I1 => \dec_cnt_reg_n_0_[5]\, + I2 => \^q\(0), + I3 => first_fail_detect_reg_n_0, + I4 => \dec_cnt[5]_i_12_n_0\, + I5 => \dec_cnt[5]_i_14_n_0\, + O => \dec_cnt[5]_i_10_n_0\ + ); +\dec_cnt[5]_i_11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \^q\(0), + I1 => pi_dqs_found_all_bank, + I2 => detect_pi_found_dqs, + I3 => \dec_cnt[5]_i_3_n_0\, + O => \dec_cnt[5]_i_11_n_0\ + ); +\dec_cnt[5]_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAAAAAAA" + ) + port map ( + I0 => stable_pass_cnt_reg(5), + I1 => stable_pass_cnt_reg(4), + I2 => stable_pass_cnt_reg(2), + I3 => stable_pass_cnt_reg(1), + I4 => stable_pass_cnt_reg(3), + O => \dec_cnt[5]_i_12_n_0\ + ); +\dec_cnt[5]_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \dec_cnt_reg_n_0_[3]\, + I1 => \dec_cnt_reg_n_0_[1]\, + I2 => \dec_cnt_reg_n_0_[0]\, + I3 => \dec_cnt_reg_n_0_[2]\, + I4 => \dec_cnt_reg_n_0_[4]\, + O => \dec_cnt[5]_i_13_n_0\ + ); +\dec_cnt[5]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0080000000000000" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[2]\, + I1 => \inc_cnt_reg_n_0_[4]\, + I2 => \inc_cnt_reg_n_0_[1]\, + I3 => \^q\(0), + I4 => \inc_cnt_reg_n_0_[5]\, + I5 => \inc_cnt_reg_n_0_[3]\, + O => \dec_cnt[5]_i_14_n_0\ + ); +\dec_cnt[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF2AFF2AFFFFFF2A" + ) + port map ( + I0 => \dec_cnt[5]_i_8_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => \dec_cnt[5]_i_9_n_0\, + I3 => \dec_cnt[5]_i_10_n_0\, + I4 => \dec_cnt[5]_i_11_n_0\, + I5 => \dec_cnt[5]_i_12_n_0\, + O => dec_cnt(5) + ); +\dec_cnt[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFFFFFFFFFF" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[1]\, + I1 => \inc_cnt_reg_n_0_[0]\, + I2 => \inc_cnt_reg_n_0_[2]\, + I3 => \inc_cnt_reg_n_0_[4]\, + I4 => \inc_cnt_reg_n_0_[3]\, + I5 => \inc_cnt_reg_n_0_[5]\, + O => \dec_cnt[5]_i_3_n_0\ + ); +\dec_cnt[5]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[0]_i_6_n_0\, + I1 => \dec_cnt[5]_i_6_n_0\, + I2 => \^q\(0), + I3 => fine_adjust_lane_cnt(0), + I4 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + O => \dec_cnt[5]_i_4_n_0\ + ); +\dec_cnt[5]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => detect_pi_found_dqs, + I1 => pi_dqs_found_all_bank, + I2 => \^q\(0), + O => \dec_cnt[5]_i_5_n_0\ + ); +\dec_cnt[5]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + O => \dec_cnt[5]_i_6_n_0\ + ); +\dec_cnt[5]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E0" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[1]_i_9_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => \dec_cnt[5]_i_12_n_0\, + O => \dec_cnt[5]_i_7_n_0\ + ); +\dec_cnt[5]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => detect_pi_found_dqs, + I1 => pi_dqs_found_all_bank, + I2 => \^q\(0), + O => \dec_cnt[5]_i_8_n_0\ + ); +\dec_cnt[5]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0001FFFF" + ) + port map ( + I0 => \first_fail_taps_reg_n_0_[3]\, + I1 => \first_fail_taps_reg_n_0_[4]\, + I2 => \first_fail_taps_reg_n_0_[1]\, + I3 => \first_fail_taps_reg_n_0_[2]\, + I4 => \first_fail_taps_reg_n_0_[5]\, + O => \dec_cnt[5]_i_9_n_0\ + ); +\dec_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \dec_cnt[5]_i_1_n_0\, + D => dec_cnt(0), + Q => \dec_cnt_reg_n_0_[0]\, + R => rst_dqs_find_reg_0(0) + ); +\dec_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \dec_cnt[5]_i_1_n_0\, + D => dec_cnt(1), + Q => \dec_cnt_reg_n_0_[1]\, + R => rst_dqs_find_reg_0(0) + ); +\dec_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \dec_cnt[5]_i_1_n_0\, + D => dec_cnt(2), + Q => \dec_cnt_reg_n_0_[2]\, + R => rst_dqs_find_reg_0(0) + ); +\dec_cnt_reg[2]_i_4\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \dec_cnt_reg[2]_i_4_n_0\, + CO(2) => \dec_cnt_reg[2]_i_4_n_1\, + CO(1) => \dec_cnt_reg[2]_i_4_n_2\, + CO(0) => \dec_cnt_reg[2]_i_4_n_3\, + CYINIT => '1', + DI(3) => \inc_cnt_reg_n_0_[3]\, + DI(2) => \inc_cnt_reg_n_0_[2]\, + DI(1) => \inc_cnt_reg_n_0_[1]\, + DI(0) => \inc_cnt_reg_n_0_[0]\, + O(3) => \dec_cnt_reg[2]_i_4_n_4\, + O(2) => \dec_cnt_reg[2]_i_4_n_5\, + O(1) => \dec_cnt_reg[2]_i_4_n_6\, + O(0) => \NLW_dec_cnt_reg[2]_i_4_O_UNCONNECTED\(0), + S(3) => \dec_cnt[2]_i_5_n_0\, + S(2) => \dec_cnt[2]_i_6_n_0\, + S(1) => \dec_cnt[2]_i_7_n_0\, + S(0) => \dec_cnt[2]_i_8_n_0\ + ); +\dec_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \dec_cnt[5]_i_1_n_0\, + D => dec_cnt(3), + Q => \dec_cnt_reg_n_0_[3]\, + R => rst_dqs_find_reg_0(0) + ); +\dec_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \dec_cnt[5]_i_1_n_0\, + D => dec_cnt(4), + Q => \dec_cnt_reg_n_0_[4]\, + R => rst_dqs_find_reg_0(0) + ); +\dec_cnt_reg[4]_i_5\: unisim.vcomponents.CARRY4 + port map ( + CI => \dec_cnt_reg[2]_i_4_n_0\, + CO(3 downto 1) => \NLW_dec_cnt_reg[4]_i_5_CO_UNCONNECTED\(3 downto 1), + CO(0) => \dec_cnt_reg[4]_i_5_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \inc_cnt_reg_n_0_[4]\, + O(3 downto 2) => \NLW_dec_cnt_reg[4]_i_5_O_UNCONNECTED\(3 downto 2), + O(1) => \dec_cnt_reg[4]_i_5_n_6\, + O(0) => \dec_cnt_reg[4]_i_5_n_7\, + S(3 downto 2) => B"00", + S(1) => \dec_cnt[4]_i_8_n_0\, + S(0) => \dec_cnt[4]_i_9_n_0\ + ); +\dec_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \dec_cnt[5]_i_1_n_0\, + D => dec_cnt(5), + Q => \dec_cnt_reg_n_0_[5]\, + R => rst_dqs_find_reg_0(0) + ); +\detect_rd_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => detect_rd_cnt_reg(0), + O => \detect_rd_cnt0__0\(0) + ); +\detect_rd_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => detect_rd_cnt_reg(0), + I1 => detect_rd_cnt_reg(1), + O => \detect_rd_cnt[1]_i_1_n_0\ + ); +\detect_rd_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => detect_rd_cnt_reg(0), + I1 => detect_rd_cnt_reg(1), + I2 => detect_rd_cnt_reg(2), + O => \detect_rd_cnt[2]_i_1_n_0\ + ); +\detect_rd_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0001" + ) + port map ( + I0 => detect_rd_cnt_reg(0), + I1 => detect_rd_cnt_reg(2), + I2 => detect_rd_cnt_reg(1), + I3 => detect_rd_cnt_reg(3), + I4 => \pi_rst_stg1_cal_r_reg[0]_0\, + O => \detect_rd_cnt[3]_i_1_n_0\ + ); +\detect_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF00FE00" + ) + port map ( + I0 => detect_rd_cnt_reg(2), + I1 => detect_rd_cnt_reg(1), + I2 => detect_rd_cnt_reg(3), + I3 => detect_pi_found_dqs, + I4 => detect_rd_cnt_reg(0), + O => detect_rd_cnt0 + ); +\detect_rd_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => detect_rd_cnt_reg(0), + I1 => detect_rd_cnt_reg(1), + I2 => detect_rd_cnt_reg(2), + I3 => detect_rd_cnt_reg(3), + O => \detect_rd_cnt[3]_i_3_n_0\ + ); +\detect_rd_cnt_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => detect_rd_cnt0, + D => \detect_rd_cnt0__0\(0), + Q => detect_rd_cnt_reg(0), + S => \detect_rd_cnt[3]_i_1_n_0\ + ); +\detect_rd_cnt_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => detect_rd_cnt0, + D => \detect_rd_cnt[1]_i_1_n_0\, + Q => detect_rd_cnt_reg(1), + S => \detect_rd_cnt[3]_i_1_n_0\ + ); +\detect_rd_cnt_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => detect_rd_cnt0, + D => \detect_rd_cnt[2]_i_1_n_0\, + Q => detect_rd_cnt_reg(2), + S => \detect_rd_cnt[3]_i_1_n_0\ + ); +\detect_rd_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => detect_rd_cnt0, + D => \detect_rd_cnt[3]_i_3_n_0\, + Q => detect_rd_cnt_reg(3), + R => \detect_rd_cnt[3]_i_1_n_0\ + ); +dqs_found_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001000000000" + ) + port map ( + I0 => \^q\(0), + I1 => fine_adj_state_r(3), + I2 => init_dqsfound_done_r1_reg_n_0, + I3 => \rnk_cnt_r_reg_n_0_[1]\, + I4 => \rnk_cnt_r_reg_n_0_[0]\, + I5 => dqs_found_done_r_i_2_n_0, + O => dqs_found_done_r0 + ); +dqs_found_done_r_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => fine_adj_state_r(1), + I2 => pi_dqs_found_all_bank, + O => dqs_found_done_r_i_2_n_0 + ); +dqs_found_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_found_done_r0, + Q => \^pi_dqs_found_done\, + R => ck_po_stg2_f_en_reg_0(0) + ); +dqs_found_prech_req_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAABFFFAAAA8000" + ) + port map ( + I0 => dqs_found_prech_req_i_2_n_0, + I1 => dqs_found_prech_req_i_3_n_0, + I2 => dqs_found_prech_req_i_4_n_0, + I3 => prech_done, + I4 => dqs_found_prech_req_i_5_n_0, + I5 => \^dqs_found_prech_req\, + O => dqs_found_prech_req_i_1_n_0 + ); +dqs_found_prech_req_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFF080A0A0808" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => fine_adj_state_r(2), + I3 => first_fail_detect_i_1_n_0, + I4 => \first_fail_taps[5]_i_2_n_0\, + I5 => dqs_found_prech_req_i_6_n_0, + O => dqs_found_prech_req_i_2_n_0 + ); +dqs_found_prech_req_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => fine_adj_state_r(1), + I1 => fine_adj_state_r(3), + O => dqs_found_prech_req_i_3_n_0 + ); +dqs_found_prech_req_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^q\(0), + I1 => fine_adj_state_r(2), + O => dqs_found_prech_req_i_4_n_0 + ); +dqs_found_prech_req_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF3FAA0800000000" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[2]_i_3_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => \dec_cnt[5]_i_12_n_0\, + I3 => pi_dqs_found_all_bank, + I4 => \FSM_sequential_fine_adj_state_r[3]_i_7_n_0\, + I5 => stable_pass_cnt, + O => dqs_found_prech_req_i_5_n_0 + ); +dqs_found_prech_req_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000040000" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => dqs_found_prech_req_i_7_n_0, + I2 => \inc_cnt_reg_n_0_[0]\, + I3 => \inc_cnt_reg_n_0_[1]\, + I4 => \inc_cnt_reg_n_0_[3]\, + I5 => \inc_cnt_reg_n_0_[5]\, + O => dqs_found_prech_req_i_6_n_0 + ); +dqs_found_prech_req_i_7: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[2]\, + I1 => \inc_cnt_reg_n_0_[4]\, + O => dqs_found_prech_req_i_7_n_0 + ); +dqs_found_prech_req_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_found_prech_req_i_1_n_0, + Q => \^dqs_found_prech_req\, + R => ck_po_stg2_f_en_reg_0(0) + ); +dqs_found_start_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_found_start_r_reg_0, + Q => dqs_found_start_r, + R => '0' + ); +final_dec_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00400000" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\, + I1 => init_dec_done_i_2_n_0, + I2 => fine_adj_state_r(3), + I3 => fine_adj_state_r(1), + I4 => init_dec_done_reg_n_0, + I5 => final_dec_done_reg_n_0, + O => final_dec_done_i_1_n_0 + ); +final_dec_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => final_dec_done_i_1_n_0, + Q => final_dec_done_reg_n_0, + R => rst_dqs_find_reg_0(0) + ); +fine_adjust_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00001000" + ) + port map ( + I0 => fine_adj_state_r(3), + I1 => \^q\(0), + I2 => pi_dqs_found_all_bank, + I3 => fine_adj_state_r(1), + I4 => fine_adj_state_r(2), + I5 => \^fine_adjust_done_r_reg_0\, + O => fine_adjust_done_r_i_1_n_0 + ); +fine_adjust_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => fine_adjust_done_r_i_1_n_0, + Q => \^fine_adjust_done_r_reg_0\, + R => rst_dqs_find_reg_0(0) + ); +fine_adjust_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00000002" + ) + port map ( + I0 => init_dqsfound_done_r5, + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + I3 => fine_adj_state_r(2), + I4 => \^q\(0), + I5 => fine_adjust_reg_n_0, + O => fine_adjust_i_1_n_0 + ); +fine_adjust_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => fine_adjust_i_1_n_0, + Q => fine_adjust_reg_n_0, + R => rst_dqs_find_reg_0(0) + ); +first_fail_detect_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00007FFFFFFFFFFF" + ) + port map ( + I0 => stable_pass_cnt_reg(3), + I1 => stable_pass_cnt_reg(1), + I2 => stable_pass_cnt_reg(2), + I3 => stable_pass_cnt_reg(4), + I4 => stable_pass_cnt_reg(5), + I5 => first_fail_detect_reg_n_0, + O => first_fail_detect_i_1_n_0 + ); +first_fail_detect_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => first_fail_detect, + D => first_fail_detect_i_1_n_0, + Q => first_fail_detect_reg_n_0, + R => first_fail_detect_reg_0 + ); +\first_fail_taps[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000004000000000" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + I3 => \first_fail_taps[5]_i_2_n_0\, + I4 => \^q\(0), + I5 => first_fail_detect_i_1_n_0, + O => first_fail_detect + ); +\first_fail_taps[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => pi_dqs_found_all_bank, + I1 => detect_pi_found_dqs, + O => \first_fail_taps[5]_i_2_n_0\ + ); +\first_fail_taps_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => first_fail_detect, + D => \inc_cnt_reg_n_0_[0]\, + Q => \first_fail_taps_reg_n_0_[0]\, + R => ck_po_stg2_f_en_reg_0(0) + ); +\first_fail_taps_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => first_fail_detect, + D => \inc_cnt_reg_n_0_[1]\, + Q => \first_fail_taps_reg_n_0_[1]\, + R => ck_po_stg2_f_en_reg_0(0) + ); +\first_fail_taps_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => first_fail_detect, + D => \inc_cnt_reg_n_0_[2]\, + Q => \first_fail_taps_reg_n_0_[2]\, + R => ck_po_stg2_f_en_reg_0(0) + ); +\first_fail_taps_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => first_fail_detect, + D => \inc_cnt_reg_n_0_[3]\, + Q => \first_fail_taps_reg_n_0_[3]\, + R => ck_po_stg2_f_en_reg_0(0) + ); +\first_fail_taps_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => first_fail_detect, + D => \inc_cnt_reg_n_0_[4]\, + Q => \first_fail_taps_reg_n_0_[4]\, + R => ck_po_stg2_f_en_reg_0(0) + ); +\first_fail_taps_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => first_fail_detect, + D => \inc_cnt_reg_n_0_[5]\, + Q => \first_fail_taps_reg_n_0_[5]\, + R => ck_po_stg2_f_en_reg_0(0) + ); +\gen_byte_sel_div2.byte_sel_cnt[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFBFBFBBBFBFBFB" + ) + port map ( + I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\, + I1 => cmd_delay_start0, + I2 => ck_addr_cmd_delay_done, + I3 => pi_calib_done, + I4 => \^pi_dqs_found_done\, + I5 => byte_sel_cnt1, + O => RSTB + ); +\gen_byte_sel_div2.byte_sel_cnt[1]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^rd_data_offset_cal_done\, + I1 => \^fine_adjust_done_r_reg_0\, + O => byte_sel_cnt1 + ); +\gen_byte_sel_div2.calib_in_common_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A2AAA2A2A200A2A2" + ) + port map ( + I0 => ck_addr_cmd_delay_done, + I1 => pi_calib_done, + I2 => \gen_byte_sel_div2.calib_in_common_reg_0\, + I3 => \^fine_adjust_done_r_reg_0\, + I4 => \^rd_data_offset_cal_done\, + I5 => rst_stg1_cal, + O => calib_in_common4_out + ); +\gen_byte_sel_div2.calib_in_common_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DFDFFFDFFFFFFFFF" + ) + port map ( + I0 => \^pi_dqs_found_done\, + I1 => \gen_byte_sel_div2.calib_in_common_reg_1\, + I2 => pi_calib_done, + I3 => \^rd_data_offset_cal_done\, + I4 => \^fine_adjust_done_r_reg_0\, + I5 => ck_addr_cmd_delay_done, + O => dqs_found_done_r_reg_1 + ); +\gen_byte_sel_div2.ctl_lane_sel[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2F20FFFF2F200000" + ) + port map ( + I0 => fine_adjust_lane_cnt(0), + I1 => rst_stg1_cal, + I2 => ck_addr_cmd_delay_done, + I3 => ctl_lane_cnt(0), + I4 => ctl_lane_sel, + I5 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]\, + O => \ctl_lane_cnt_reg[0]_0\ + ); +\gen_byte_sel_div2.ctl_lane_sel[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08088808" + ) + port map ( + I0 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0\, + I1 => \gen_byte_sel_div2.ctl_lane_sel_reg[0]_1\, + I2 => ck_addr_cmd_delay_done, + I3 => \^rd_data_offset_cal_done\, + I4 => \^fine_adjust_done_r_reg_0\, + O => ctl_lane_sel + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \^pi_dqs_found_done\, + I1 => D(0), + O => dqs_found_done_r_reg_0 + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '1', + O => n_0_0 + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '1', + O => n_0_1 + ); +ififo_rst_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF45004400" + ) + port map ( + I0 => calib_zero_inputs, + I1 => ofifo_rst_reg, + I2 => ofifo_rst_reg_0, + I3 => rst_stg1_cal, + I4 => ofifo_rst_reg_1, + I5 => phy_if_reset, + O => ififo_rst_reg0 + ); +\ififo_rst_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF54440000" + ) + port map ( + I0 => calib_zero_inputs, + I1 => ofifo_rst_reg, + I2 => ofifo_rst_reg_1, + I3 => ofifo_rst_reg_0, + I4 => rst_stg1_cal, + I5 => phy_if_reset, + O => ififo_rst_reg0_1 + ); +\inc_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + O => \p_0_in__0\(0) + ); +\inc_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + I1 => \inc_cnt_reg_n_0_[1]\, + O => \p_0_in__0\(1) + ); +\inc_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + I1 => \inc_cnt_reg_n_0_[1]\, + I2 => \inc_cnt_reg_n_0_[2]\, + O => \p_0_in__0\(2) + ); +\inc_cnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + I1 => \inc_cnt_reg_n_0_[1]\, + I2 => \inc_cnt_reg_n_0_[2]\, + I3 => \inc_cnt_reg_n_0_[3]\, + O => \p_0_in__0\(3) + ); +\inc_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[1]\, + I1 => \inc_cnt_reg_n_0_[2]\, + I2 => \inc_cnt_reg_n_0_[0]\, + I3 => \inc_cnt_reg_n_0_[3]\, + I4 => \inc_cnt_reg_n_0_[4]\, + O => \p_0_in__0\(4) + ); +\inc_cnt[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => fine_adjust_lane_cnt(0), + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + I3 => \^q\(0), + I4 => fine_adj_state_r(2), + O => inc_cnt + ); +\inc_cnt[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[1]\, + I1 => \inc_cnt_reg_n_0_[0]\, + I2 => \inc_cnt_reg_n_0_[2]\, + I3 => \inc_cnt_reg_n_0_[4]\, + I4 => \inc_cnt_reg_n_0_[3]\, + I5 => \inc_cnt_reg_n_0_[5]\, + O => \inc_cnt[5]_i_2_n_0\ + ); +\inc_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => inc_cnt, + D => \p_0_in__0\(0), + Q => \inc_cnt_reg_n_0_[0]\, + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\inc_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => inc_cnt, + D => \p_0_in__0\(1), + Q => \inc_cnt_reg_n_0_[1]\, + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\inc_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => inc_cnt, + D => \p_0_in__0\(2), + Q => \inc_cnt_reg_n_0_[2]\, + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\inc_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => inc_cnt, + D => \p_0_in__0\(3), + Q => \inc_cnt_reg_n_0_[3]\, + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\inc_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => inc_cnt, + D => \p_0_in__0\(4), + Q => \inc_cnt_reg_n_0_[4]\, + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\inc_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => inc_cnt, + D => \inc_cnt[5]_i_2_n_0\, + Q => \inc_cnt_reg_n_0_[5]\, + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\init_dec_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => init_dec_cnt_reg(0), + O => init_dec_cnt0(0) + ); +\init_dec_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => init_dec_cnt_reg(0), + I1 => init_dec_cnt_reg(1), + O => \init_dec_cnt[1]_i_1_n_0\ + ); +\init_dec_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => init_dec_cnt_reg(1), + I1 => init_dec_cnt_reg(0), + I2 => init_dec_cnt_reg(2), + O => \init_dec_cnt[2]_i_1_n_0\ + ); +\init_dec_cnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => init_dec_cnt_reg(2), + I1 => init_dec_cnt_reg(0), + I2 => init_dec_cnt_reg(1), + I3 => init_dec_cnt_reg(3), + O => \init_dec_cnt[3]_i_1_n_0\ + ); +\init_dec_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0001" + ) + port map ( + I0 => init_dec_cnt_reg(3), + I1 => init_dec_cnt_reg(1), + I2 => init_dec_cnt_reg(0), + I3 => init_dec_cnt_reg(2), + I4 => init_dec_cnt_reg(4), + O => \init_dec_cnt[4]_i_1_n_0\ + ); +\init_dec_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4000000000000000" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + I3 => \^q\(0), + I4 => fine_adjust_lane_cnt(0), + I5 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + O => init_dec_cnt + ); +\init_dec_cnt[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000001" + ) + port map ( + I0 => init_dec_cnt_reg(4), + I1 => init_dec_cnt_reg(2), + I2 => init_dec_cnt_reg(0), + I3 => init_dec_cnt_reg(1), + I4 => init_dec_cnt_reg(3), + I5 => init_dec_cnt_reg(5), + O => \init_dec_cnt[5]_i_2_n_0\ + ); +\init_dec_cnt_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => init_dec_cnt, + D => init_dec_cnt0(0), + Q => init_dec_cnt_reg(0), + S => \stable_pass_cnt_reg[0]_0\(0) + ); +\init_dec_cnt_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => init_dec_cnt, + D => \init_dec_cnt[1]_i_1_n_0\, + Q => init_dec_cnt_reg(1), + S => \stable_pass_cnt_reg[0]_0\(0) + ); +\init_dec_cnt_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => init_dec_cnt, + D => \init_dec_cnt[2]_i_1_n_0\, + Q => init_dec_cnt_reg(2), + S => \stable_pass_cnt_reg[0]_0\(0) + ); +\init_dec_cnt_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => init_dec_cnt, + D => \init_dec_cnt[3]_i_1_n_0\, + Q => init_dec_cnt_reg(3), + S => \stable_pass_cnt_reg[0]_0\(0) + ); +\init_dec_cnt_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => init_dec_cnt, + D => \init_dec_cnt[4]_i_1_n_0\, + Q => init_dec_cnt_reg(4), + S => \stable_pass_cnt_reg[0]_0\(0) + ); +\init_dec_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => init_dec_cnt, + D => \init_dec_cnt[5]_i_2_n_0\, + Q => init_dec_cnt_reg(5), + R => \stable_pass_cnt_reg[0]_0\(0) + ); +init_dec_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCCCCCCCDCCCCCC" + ) + port map ( + I0 => \FSM_sequential_fine_adj_state_r[3]_i_5_n_0\, + I1 => init_dec_done_reg_n_0, + I2 => fine_adj_state_r(1), + I3 => fine_adj_state_r(3), + I4 => init_dec_done_i_2_n_0, + I5 => \FSM_sequential_fine_adj_state_r[0]_i_4_n_0\, + O => init_dec_done_i_1_n_0 + ); +init_dec_done_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => fine_adj_state_r(2), + I1 => \^q\(0), + O => init_dec_done_i_2_n_0 + ); +init_dec_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_dec_done_i_1_n_0, + Q => init_dec_done_reg_n_0, + R => ck_po_stg2_f_en_reg_0(0) + ); +init_dqsfound_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^rd_data_offset_cal_done\, + Q => init_dqsfound_done_r1_reg_n_0, + R => '0' + ); +init_dqsfound_done_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_dqsfound_done_r1_reg_n_0, + Q => init_dqsfound_done_r2, + R => '0' + ); +init_dqsfound_done_r4_reg_srl2: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => init_dqsfound_done_r2, + Q => init_dqsfound_done_r4_reg_srl2_n_0 + ); +init_dqsfound_done_r5_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_dqsfound_done_r4_reg_srl2_n_0, + Q => init_dqsfound_done_r5, + R => '0' + ); +init_dqsfound_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0010001000101110" + ) + port map ( + I0 => init_dqsfound_done_r_reg_0, + I1 => pi_rst_stg1_cal_r, + I2 => \^rd_data_offset_cal_done\, + I3 => pi_dqs_found_all_bank, + I4 => \rnk_cnt_r_reg_n_0_[0]\, + I5 => \rnk_cnt_r_reg_n_0_[1]\, + O => init_dqsfound_done_r_i_1_n_0 + ); +init_dqsfound_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_dqsfound_done_r_i_1_n_0, + Q => \^rd_data_offset_cal_done\, + R => '0' + ); +ofifo_rst_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF45004400" + ) + port map ( + I0 => calib_zero_inputs, + I1 => ofifo_rst_reg, + I2 => ofifo_rst_reg_0, + I3 => rst_stg1_cal, + I4 => ofifo_rst_reg_1, + I5 => A_rst_primitives, + O => ofifo_rst_reg0 + ); +\ofifo_rst_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF54440000" + ) + port map ( + I0 => calib_zero_inputs, + I1 => ofifo_rst_reg, + I2 => ofifo_rst_reg_1, + I3 => ofifo_rst_reg_0, + I4 => rst_stg1_cal, + I5 => A_rst_primitives, + O => ofifo_rst_reg0_2 + ); +\phaser_in_gen.phaser_in_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => ofifo_rst_reg_1, + I1 => rst_stg1_cal, + I2 => ofifo_rst_reg_0, + I3 => ofifo_rst_reg, + I4 => calib_zero_inputs, + O => \calib_sel_reg[1]_0\ + ); +\phaser_in_gen.phaser_in_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => rst_stg1_cal, + I1 => ofifo_rst_reg_0, + I2 => ofifo_rst_reg_1, + I3 => ofifo_rst_reg, + I4 => calib_zero_inputs, + O => \pi_rst_stg1_cal_reg[0]_0\ + ); +\phaser_out_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FCFC00A8" + ) + port map ( + I0 => ofifo_rst_reg_1, + I1 => \^ck_po_stg2_f_indec\, + I2 => dqs_po_stg2_f_incdec, + I3 => ofifo_rst_reg_0, + I4 => ofifo_rst_reg, + I5 => calib_zero_inputs, + O => \calib_sel_reg[1]\ + ); +\phaser_out_i_3__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEEEE000" + ) + port map ( + I0 => \^ck_po_stg2_f_indec\, + I1 => dqs_po_stg2_f_incdec, + I2 => ofifo_rst_reg_0, + I3 => ofifo_rst_reg_1, + I4 => ofifo_rst_reg, + I5 => calib_zero_inputs, + O => ck_po_stg2_f_indec_reg_0 + ); +phaser_out_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000054" + ) + port map ( + I0 => ofifo_rst_reg, + I1 => \^ck_po_stg2_f_indec\, + I2 => dqs_po_stg2_f_incdec, + I3 => ofifo_rst_reg_0, + I4 => ofifo_rst_reg_1, + I5 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg\ + ); +\pi_dqs_found_all_bank[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8F80" + ) + port map ( + I0 => pi_dqs_found_lanes_r3(3), + I1 => pi_dqs_found_lanes_r3(2), + I2 => dqs_found_start_r_reg_0, + I3 => pi_dqs_found_all_bank, + O => \pi_dqs_found_all_bank[0]_i_1_n_0\ + ); +\pi_dqs_found_all_bank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_all_bank, + Q => pi_dqs_found_all_bank_r, + R => '0' + ); +\pi_dqs_found_all_bank_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_dqs_found_all_bank[0]_i_1_n_0\, + Q => pi_dqs_found_all_bank, + R => rst_dqs_find_reg_0(0) + ); +\pi_dqs_found_any_bank[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFE0" + ) + port map ( + I0 => pi_dqs_found_lanes_r3(3), + I1 => pi_dqs_found_lanes_r3(2), + I2 => dqs_found_start_r_reg_0, + I3 => pi_dqs_found_any_bank, + O => \pi_dqs_found_any_bank[0]_i_1_n_0\ + ); +\pi_dqs_found_any_bank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_any_bank, + Q => pi_dqs_found_any_bank_r, + R => '0' + ); +\pi_dqs_found_any_bank_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_dqs_found_any_bank[0]_i_1_n_0\, + Q => pi_dqs_found_any_bank, + R => rst_dqs_find_reg_0(0) + ); +\pi_dqs_found_lanes_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => n_0_1, + Q => pi_dqs_found_lanes_r1(0), + R => '0' + ); +\pi_dqs_found_lanes_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => n_0_0, + Q => pi_dqs_found_lanes_r1(1), + R => '0' + ); +\pi_dqs_found_lanes_r1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes(0), + Q => pi_dqs_found_lanes_r1(2), + R => '0' + ); +\pi_dqs_found_lanes_r1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes(1), + Q => pi_dqs_found_lanes_r1(3), + R => '0' + ); +\pi_dqs_found_lanes_r2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r1(0), + Q => pi_dqs_found_lanes_r2(0), + R => '0' + ); +\pi_dqs_found_lanes_r2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r1(1), + Q => pi_dqs_found_lanes_r2(1), + R => '0' + ); +\pi_dqs_found_lanes_r2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r1(2), + Q => pi_dqs_found_lanes_r2(2), + R => '0' + ); +\pi_dqs_found_lanes_r2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r1(3), + Q => pi_dqs_found_lanes_r2(3), + R => '0' + ); +\pi_dqs_found_lanes_r3_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r2(0), + Q => pi_dqs_found_lanes_r3(0), + R => '0' + ); +\pi_dqs_found_lanes_r3_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r2(1), + Q => pi_dqs_found_lanes_r3(1), + R => '0' + ); +\pi_dqs_found_lanes_r3_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r2(2), + Q => pi_dqs_found_lanes_r3(2), + R => '0' + ); +\pi_dqs_found_lanes_r3_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_lanes_r2(3), + Q => pi_dqs_found_lanes_r3(3), + R => '0' + ); +\pi_rst_stg1_cal[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pi_rst_stg1_cal_r, + I1 => \rst_dqs_find__0\, + O => \pi_rst_stg1_cal[0]_i_1_n_0\ + ); +\pi_rst_stg1_cal_r1[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1110111011101100" + ) + port map ( + I0 => init_dqsfound_done_r_reg_0, + I1 => fine_adjust_reg_n_0, + I2 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\, + I3 => pi_rst_stg1_cal_r, + I4 => pi_dqs_found_any_bank_r, + I5 => pi_dqs_found_all_bank, + O => \pi_rst_stg1_cal_r1[0]_i_1_n_0\ + ); +\pi_rst_stg1_cal_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_rst_stg1_cal_r1[0]_i_1_n_0\, + Q => \pi_rst_stg1_cal_r1_reg_n_0_[0]\, + R => '0' + ); +\pi_rst_stg1_cal_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => \pi_rst_stg1_cal_r1_reg_n_0_[0]\, + I1 => \pi_rst_stg1_cal_r[0]_i_2_n_0\, + I2 => \pi_rst_stg1_cal_r_reg[0]_0\, + I3 => fine_adjust_reg_n_0, + O => \pi_rst_stg1_cal_r[0]_i_1_n_0\ + ); +\pi_rst_stg1_cal_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF2F22" + ) + port map ( + I0 => dqs_found_start_r_reg_0, + I1 => dqs_found_start_r, + I2 => pi_dqs_found_all_bank, + I3 => pi_dqs_found_any_bank_r, + I4 => \rd_byte_data_offset[0][5]_i_4_n_0\, + I5 => pi_rst_stg1_cal_r, + O => \pi_rst_stg1_cal_r[0]_i_2_n_0\ + ); +\pi_rst_stg1_cal_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_rst_stg1_cal_r[0]_i_1_n_0\, + Q => pi_rst_stg1_cal_r, + R => '0' + ); +\pi_rst_stg1_cal_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_rst_stg1_cal[0]_i_1_n_0\, + Q => rst_stg1_cal, + R => ck_po_stg2_f_en_reg_0(0) + ); +rank_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^pi_dqs_found_rank_done\, + Q => rank_done_r1, + R => '0' + ); +rank_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0404040404040004" + ) + port map ( + I0 => init_dqsfound_done_r_reg_0, + I1 => pi_dqs_found_all_bank, + I2 => pi_dqs_found_all_bank_r, + I3 => \^rd_data_offset_cal_done\, + I4 => \rnk_cnt_r_reg_n_0_[0]\, + I5 => \rnk_cnt_r_reg_n_0_[1]\, + O => rank_done_r_i_1_n_0 + ); +rank_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rank_done_r_i_1_n_0, + Q => \^pi_dqs_found_rank_done\, + R => '0' + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^rd_data_offset_cal_done\, + I1 => init_dqsfound_done_r1_reg_n_0, + O => p_44_out + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(0), + O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\ + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(1), + I1 => \rd_byte_data_offset_reg[0]_10\(0), + O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\ + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(1), + I1 => \rd_byte_data_offset_reg[0]_10\(0), + I2 => \rd_byte_data_offset_reg[0]_10\(2), + O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\ + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FE01" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(0), + I1 => \rd_byte_data_offset_reg[0]_10\(1), + I2 => \rd_byte_data_offset_reg[0]_10\(2), + I3 => \rd_byte_data_offset_reg[0]_10\(3), + O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\ + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFE0001" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(0), + I1 => \rd_byte_data_offset_reg[0]_10\(2), + I2 => \rd_byte_data_offset_reg[0]_10\(1), + I3 => \rd_byte_data_offset_reg[0]_10\(3), + I4 => \rd_byte_data_offset_reg[0]_10\(4), + O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\ + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"10" + ) + port map ( + I0 => \pi_rst_stg1_cal_r_reg[0]_0\, + I1 => init_dqsfound_done_r1_reg_n_0, + I2 => \^rd_data_offset_cal_done\, + O => final_data_offset_mc + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000001" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(2), + I1 => \rd_byte_data_offset_reg[0]_10\(1), + I2 => \rd_byte_data_offset_reg[0]_10\(3), + I3 => \rd_byte_data_offset_reg[0]_10\(0), + I4 => \rd_byte_data_offset_reg[0]_10\(4), + I5 => \rd_byte_data_offset_reg[0]_10\(5), + O => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\ + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => final_data_offset_mc, + D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\, + Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(0), + R => '0' + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => final_data_offset_mc, + D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0\, + Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(1), + R => '0' + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => final_data_offset_mc, + D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0\, + Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(2), + R => '0' + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => final_data_offset_mc, + D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0\, + Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(3), + R => '0' + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => final_data_offset_mc, + D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0\, + Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(4), + R => '0' + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => final_data_offset_mc, + D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0\, + Q => \^rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5), + R => '0' + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_44_out, + D => \rd_byte_data_offset_reg[0]_10\(0), + Q => rd_data_offset_ranks_0(0), + R => rst_dqs_find_reg_0(0) + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_44_out, + D => \rd_byte_data_offset_reg[0]_10\(1), + Q => rd_data_offset_ranks_0(1), + R => rst_dqs_find_reg_0(0) + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_44_out, + D => \rd_byte_data_offset_reg[0]_10\(2), + Q => rd_data_offset_ranks_0(2), + R => rst_dqs_find_reg_0(0) + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_44_out, + D => \rd_byte_data_offset_reg[0]_10\(3), + Q => rd_data_offset_ranks_0(3), + R => rst_dqs_find_reg_0(0) + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_44_out, + D => \rd_byte_data_offset_reg[0]_10\(4), + Q => rd_data_offset_ranks_0(4), + R => rst_dqs_find_reg_0(0) + ); +\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_44_out, + D => \rd_byte_data_offset_reg[0]_10\(5), + Q => rd_data_offset_ranks_0(5), + R => rst_dqs_find_reg_0(0) + ); +\rd_byte_data_offset[0][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(0), + I1 => \rd_byte_data_offset_reg[0]_10\(1), + O => \rd_byte_data_offset[0][1]_i_1_n_0\ + ); +\rd_byte_data_offset[0][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(1), + I1 => \rd_byte_data_offset_reg[0]_10\(0), + I2 => \rd_byte_data_offset_reg[0]_10\(2), + O => p_0_in(2) + ); +\rd_byte_data_offset[0][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(2), + I1 => \rd_byte_data_offset_reg[0]_10\(0), + I2 => \rd_byte_data_offset_reg[0]_10\(1), + I3 => \rd_byte_data_offset_reg[0]_10\(3), + O => p_0_in(3) + ); +\rd_byte_data_offset[0][4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(0), + I1 => \rd_byte_data_offset_reg[0]_10\(1), + I2 => \rd_byte_data_offset_reg[0]_10\(2), + I3 => \rd_byte_data_offset_reg[0]_10\(3), + I4 => \rd_byte_data_offset_reg[0]_10\(4), + O => p_0_in(4) + ); +\rd_byte_data_offset[0][5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAFFAAAAAABA" + ) + port map ( + I0 => init_dqsfound_done_r_reg_0, + I1 => \^rd_data_offset_cal_done\, + I2 => rank_done_r1, + I3 => \rnk_cnt_r_reg_n_0_[0]\, + I4 => \rnk_cnt_r_reg_n_0_[1]\, + I5 => \rd_byte_data_offset[0][5]_i_4_n_0\, + O => \rd_byte_data_offset[0][5]_i_1_n_0\ + ); +\rd_byte_data_offset[0][5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"01FF000000000000" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(1), + I1 => \rd_byte_data_offset_reg[0]_10\(2), + I2 => \rd_byte_data_offset_reg[0]_10\(3), + I3 => \rd_byte_data_offset_reg[0]_10\(4), + I4 => \rd_byte_data_offset[0][5]_i_5_n_0\, + I5 => \rd_byte_data_offset[0][5]_i_6_n_0\, + O => rd_byte_data_offset + ); +\rd_byte_data_offset[0][5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFF80000000" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(0), + I1 => \rd_byte_data_offset_reg[0]_10\(1), + I2 => \rd_byte_data_offset_reg[0]_10\(4), + I3 => \rd_byte_data_offset_reg[0]_10\(3), + I4 => \rd_byte_data_offset_reg[0]_10\(2), + I5 => \rd_byte_data_offset_reg[0]_10\(5), + O => p_0_in(5) + ); +\rd_byte_data_offset[0][5]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFAAA8" + ) + port map ( + I0 => \rd_byte_data_offset_reg[0]_10\(4), + I1 => \rd_byte_data_offset_reg[0]_10\(2), + I2 => \rd_byte_data_offset_reg[0]_10\(1), + I3 => \rd_byte_data_offset_reg[0]_10\(3), + I4 => \rd_byte_data_offset_reg[0]_10\(5), + O => \rd_byte_data_offset[0][5]_i_4_n_0\ + ); +\rd_byte_data_offset[0][5]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \rnk_cnt_r_reg_n_0_[0]\, + I1 => \rnk_cnt_r_reg_n_0_[1]\, + I2 => \first_fail_taps[5]_i_2_n_0\, + I3 => detect_rd_cnt_reg(3), + I4 => detect_rd_cnt_reg(1), + I5 => detect_rd_cnt_reg(2), + O => \rd_byte_data_offset[0][5]_i_5_n_0\ + ); +\rd_byte_data_offset[0][5]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000020" + ) + port map ( + I0 => detect_rd_cnt_reg(0), + I1 => \rd_byte_data_offset_reg[0]_10\(5), + I2 => dqs_found_start_r, + I3 => rank_done_r1, + I4 => fine_adjust_reg_n_0, + I5 => \^rd_data_offset_cal_done\, + O => \rd_byte_data_offset[0][5]_i_6_n_0\ + ); +\rd_byte_data_offset_reg[0][0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => rd_byte_data_offset, + D => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0\, + Q => \rd_byte_data_offset_reg[0]_10\(0), + S => \rd_byte_data_offset[0][5]_i_1_n_0\ + ); +\rd_byte_data_offset_reg[0][1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => rd_byte_data_offset, + D => \rd_byte_data_offset[0][1]_i_1_n_0\, + Q => \rd_byte_data_offset_reg[0]_10\(1), + S => \rd_byte_data_offset[0][5]_i_1_n_0\ + ); +\rd_byte_data_offset_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_byte_data_offset, + D => p_0_in(2), + Q => \rd_byte_data_offset_reg[0]_10\(2), + R => \rd_byte_data_offset[0][5]_i_1_n_0\ + ); +\rd_byte_data_offset_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_byte_data_offset, + D => p_0_in(3), + Q => \rd_byte_data_offset_reg[0]_10\(3), + R => \rd_byte_data_offset[0][5]_i_1_n_0\ + ); +\rd_byte_data_offset_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_byte_data_offset, + D => p_0_in(4), + Q => \rd_byte_data_offset_reg[0]_10\(4), + R => \rd_byte_data_offset[0][5]_i_1_n_0\ + ); +\rd_byte_data_offset_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_byte_data_offset, + D => p_0_in(5), + Q => \rd_byte_data_offset_reg[0]_10\(5), + R => \rd_byte_data_offset[0][5]_i_1_n_0\ + ); +\rnk_cnt_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B4" + ) + port map ( + I0 => \^rd_data_offset_cal_done\, + I1 => \^pi_dqs_found_rank_done\, + I2 => \rnk_cnt_r_reg_n_0_[0]\, + O => \rnk_cnt_r[0]_i_1_n_0\ + ); +\rnk_cnt_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F708" + ) + port map ( + I0 => \rnk_cnt_r_reg_n_0_[0]\, + I1 => \^pi_dqs_found_rank_done\, + I2 => \^rd_data_offset_cal_done\, + I3 => \rnk_cnt_r_reg_n_0_[1]\, + O => \rnk_cnt_r[1]_i_1_n_0\ + ); +\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rnk_cnt_r[0]_i_1_n_0\, + Q => \rnk_cnt_r_reg_n_0_[0]\, + R => rst_dqs_find_reg_0(0) + ); +\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rnk_cnt_r[1]_i_1_n_0\, + Q => \rnk_cnt_r_reg_n_0_[1]\, + R => rst_dqs_find_reg_0(0) + ); +rst_dqs_find_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAABAAAAAAA8" + ) + port map ( + I0 => rst_dqs_find, + I1 => rst_dqs_find_i_3_n_0, + I2 => rst_dqs_find_i_4_n_0, + I3 => rst_dqs_find_i_5_n_0, + I4 => rst_dqs_find_i_6_n_0, + I5 => \rst_dqs_find__0\, + O => rst_dqs_find_i_1_n_0 + ); +rst_dqs_find_i_10: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000020" + ) + port map ( + I0 => rst_dqs_find_r2, + I1 => pi_dqs_found_any_bank, + I2 => \^q\(0), + I3 => fine_adj_state_r(2), + I4 => fine_adj_state_r(3), + I5 => fine_adj_state_r(1), + O => rst_dqs_find_i_10_n_0 + ); +rst_dqs_find_i_11: unisim.vcomponents.LUT5 + generic map( + INIT => X"00080000" + ) + port map ( + I0 => pi_dqs_found_all_bank, + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(2), + I3 => \^q\(0), + I4 => detect_pi_found_dqs, + O => rst_dqs_find_i_11_n_0 + ); +rst_dqs_find_i_12: unisim.vcomponents.LUT6 + generic map( + INIT => X"3000202000002020" + ) + port map ( + I0 => \dec_cnt[5]_i_5_n_0\, + I1 => \dec_cnt[5]_i_12_n_0\, + I2 => dqs_found_prech_req_i_3_n_0, + I3 => rst_dqs_find_i_4_0, + I4 => \inc_cnt_reg_n_0_[1]\, + I5 => rst_dqs_find_i_18_n_0, + O => rst_dqs_find_i_12_n_0 + ); +rst_dqs_find_i_13: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000002" + ) + port map ( + I0 => init_dqsfound_done_r5, + I1 => fine_adj_state_r(1), + I2 => fine_adj_state_r(3), + I3 => fine_adj_state_r(2), + I4 => \^q\(0), + O => fine_adjust + ); +rst_dqs_find_i_14: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BB00BF00" + ) + port map ( + I0 => rst_dqs_find_i_19_n_0, + I1 => \inc_cnt_reg_n_0_[3]\, + I2 => \inc_cnt_reg_n_0_[1]\, + I3 => detect_pi_found_dqs, + I4 => pi_dqs_found_all_bank, + I5 => \^q\(0), + O => rst_dqs_find_i_14_n_0 + ); +rst_dqs_find_i_15: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001000" + ) + port map ( + I0 => fine_adj_state_r(3), + I1 => \^q\(0), + I2 => pi_dqs_found_all_bank, + I3 => fine_adj_state_r(1), + I4 => fine_adj_state_r(2), + O => fine_adjust_done_r + ); +rst_dqs_find_i_16: unisim.vcomponents.LUT5 + generic map( + INIT => X"AA2FAAAA" + ) + port map ( + I0 => \dec_cnt[5]_i_3_n_0\, + I1 => \dec_cnt[5]_i_12_n_0\, + I2 => first_fail_detect_reg_n_0, + I3 => pi_dqs_found_all_bank, + I4 => detect_pi_found_dqs, + O => rst_dqs_find_i_16_n_0 + ); +rst_dqs_find_i_18: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFFFFFF" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[3]\, + I1 => \inc_cnt_reg_n_0_[4]\, + I2 => \inc_cnt_reg_n_0_[2]\, + I3 => \inc_cnt_reg_n_0_[0]\, + I4 => \inc_cnt_reg_n_0_[5]\, + O => rst_dqs_find_i_18_n_0 + ); +rst_dqs_find_i_19: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F00" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[0]\, + I1 => \inc_cnt_reg_n_0_[2]\, + I2 => \inc_cnt_reg_n_0_[4]\, + I3 => \inc_cnt_reg_n_0_[1]\, + O => rst_dqs_find_i_19_n_0 + ); +rst_dqs_find_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEAAA" + ) + port map ( + I0 => rst_dqs_find_i_7_n_0, + I1 => prech_done, + I2 => fine_adj_state_r(1), + I3 => fine_adj_state_r(2), + I4 => rst_dqs_find_i_8_n_0, + I5 => rst_dqs_find_i_9_n_0, + O => rst_dqs_find + ); +rst_dqs_find_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFEAEAFFAAAAAAAA" + ) + port map ( + I0 => rst_dqs_find_i_10_n_0, + I1 => \inc_cnt_reg_n_0_[3]\, + I2 => \inc_cnt_reg_n_0_[5]\, + I3 => \inc_cnt_reg_n_0_[2]\, + I4 => \inc_cnt_reg_n_0_[4]\, + I5 => rst_dqs_find_i_11_n_0, + O => rst_dqs_find_i_3_n_0 + ); +rst_dqs_find_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEEEFEFEEEEEEEEE" + ) + port map ( + I0 => rst_dqs_find_i_12_n_0, + I1 => fine_adjust, + I2 => dqs_found_prech_req_i_3_n_0, + I3 => prech_done, + I4 => \^q\(0), + I5 => fine_adj_state_r(2), + O => rst_dqs_find_i_4_n_0 + ); +rst_dqs_find_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"000022F200002222" + ) + port map ( + I0 => rst_dqs_find_i_11_n_0, + I1 => \inc_cnt_reg_n_0_[3]\, + I2 => rst_dqs_find_i_14_n_0, + I3 => first_fail_detect_reg_n_0, + I4 => \inc_cnt_reg_n_0_[5]\, + I5 => dqs_found_prech_req_i_3_n_0, + O => rst_dqs_find_i_5_n_0 + ); +rst_dqs_find_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF60E0E0E0" + ) + port map ( + I0 => \inc_cnt_reg_n_0_[1]\, + I1 => \inc_cnt_reg_n_0_[0]\, + I2 => rst_dqs_find_i_11_n_0, + I3 => \inc_cnt_reg_n_0_[4]\, + I4 => \inc_cnt_reg_n_0_[2]\, + I5 => fine_adjust_done_r, + O => rst_dqs_find_i_6_n_0 + ); +rst_dqs_find_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"F200220022002200" + ) + port map ( + I0 => \dec_cnt[5]_i_5_n_0\, + I1 => first_fail_detect_reg_n_0, + I2 => rst_dqs_find_i_16_n_0, + I3 => fine_adj_state_r(3), + I4 => fine_adj_state_r(1), + I5 => prech_done, + O => rst_dqs_find_i_7_n_0 + ); +rst_dqs_find_i_8: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000880800008888" + ) + port map ( + I0 => fine_adj_state_r(3), + I1 => \dec_cnt[5]_i_3_n_0\, + I2 => detect_pi_found_dqs, + I3 => pi_dqs_found_all_bank, + I4 => \^q\(0), + I5 => \dec_cnt[5]_i_12_n_0\, + O => rst_dqs_find_i_8_n_0 + ); +rst_dqs_find_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"0F02" + ) + port map ( + I0 => init_dqsfound_done_r5, + I1 => fine_adj_state_r(1), + I2 => \^q\(0), + I3 => fine_adj_state_r(2), + O => rst_dqs_find_i_9_n_0 + ); +rst_dqs_find_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rst_dqs_find__0\, + Q => rst_dqs_find_r1, + R => '0' + ); +rst_dqs_find_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rst_dqs_find_r1, + Q => rst_dqs_find_r2, + R => '0' + ); +rst_dqs_find_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rst_dqs_find_i_1_n_0, + Q => \rst_dqs_find__0\, + R => rst_dqs_find_reg_0(0) + ); +\stable_pass_cnt[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pi_dqs_found_all_bank, + I1 => \stable_pass_cnt_reg_n_0_[0]\, + O => \p_0_in__1\(0) + ); +\stable_pass_cnt[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => pi_dqs_found_all_bank, + I1 => stable_pass_cnt_reg(1), + I2 => \stable_pass_cnt_reg_n_0_[0]\, + O => \p_0_in__1\(1) + ); +\stable_pass_cnt[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2888" + ) + port map ( + I0 => pi_dqs_found_all_bank, + I1 => stable_pass_cnt_reg(2), + I2 => stable_pass_cnt_reg(1), + I3 => \stable_pass_cnt_reg_n_0_[0]\, + O => \p_0_in__1\(2) + ); +\stable_pass_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"28888888" + ) + port map ( + I0 => pi_dqs_found_all_bank, + I1 => stable_pass_cnt_reg(3), + I2 => \stable_pass_cnt_reg_n_0_[0]\, + I3 => stable_pass_cnt_reg(2), + I4 => stable_pass_cnt_reg(1), + O => \p_0_in__1\(3) + ); +\stable_pass_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2888888888888888" + ) + port map ( + I0 => \first_fail_taps[5]_i_2_n_0\, + I1 => stable_pass_cnt_reg(4), + I2 => \stable_pass_cnt_reg_n_0_[0]\, + I3 => stable_pass_cnt_reg(3), + I4 => stable_pass_cnt_reg(1), + I5 => stable_pass_cnt_reg(2), + O => \p_0_in__1\(4) + ); +\stable_pass_cnt[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00004000" + ) + port map ( + I0 => \^q\(0), + I1 => detect_pi_found_dqs, + I2 => fine_adj_state_r(3), + I3 => fine_adj_state_r(1), + I4 => fine_adj_state_r(2), + O => stable_pass_cnt + ); +\stable_pass_cnt[5]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8828" + ) + port map ( + I0 => pi_dqs_found_all_bank, + I1 => stable_pass_cnt_reg(5), + I2 => \stable_pass_cnt_reg_n_0_[0]\, + I3 => \stable_pass_cnt[5]_i_3_n_0\, + O => \p_0_in__1\(5) + ); +\stable_pass_cnt[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => stable_pass_cnt_reg(3), + I1 => stable_pass_cnt_reg(1), + I2 => stable_pass_cnt_reg(2), + I3 => stable_pass_cnt_reg(4), + O => \stable_pass_cnt[5]_i_3_n_0\ + ); +\stable_pass_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_pass_cnt, + D => \p_0_in__1\(0), + Q => \stable_pass_cnt_reg_n_0_[0]\, + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\stable_pass_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_pass_cnt, + D => \p_0_in__1\(1), + Q => stable_pass_cnt_reg(1), + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\stable_pass_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_pass_cnt, + D => \p_0_in__1\(2), + Q => stable_pass_cnt_reg(2), + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\stable_pass_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_pass_cnt, + D => \p_0_in__1\(3), + Q => stable_pass_cnt_reg(3), + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\stable_pass_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_pass_cnt, + D => \p_0_in__1\(4), + Q => stable_pass_cnt_reg(4), + R => \stable_pass_cnt_reg[0]_0\(0) + ); +\stable_pass_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_pass_cnt, + D => \p_0_in__1\(5), + Q => stable_pass_cnt_reg(5), + R => \stable_pass_cnt_reg[0]_0\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_init is + port ( + prech_done : out STD_LOGIC; + \out\ : out STD_LOGIC; + prech_req_posedge_r_reg_0 : out STD_LOGIC; + wrlvl_done_r1 : out STD_LOGIC; + prbs_rdlvl_done_pulse_reg_0 : out STD_LOGIC; + pi_calib_done : out STD_LOGIC; + wl_sm_start : out STD_LOGIC; + wrcal_rd_wait : out STD_LOGIC; + wrcal_sanity_chk : out STD_LOGIC; + detect_pi_found_dqs : out STD_LOGIC; + calib_complete : out STD_LOGIC; + calib_ctl_wren_reg_0 : out STD_LOGIC; + cnt_pwron_cke_done_r : out STD_LOGIC; + pi_dqs_found_done_r1 : out STD_LOGIC; + calib_wrdata_en : out STD_LOGIC; + \one_rank.stg1_wr_done_reg_0\ : out STD_LOGIC; + wrlvl_final_if_rst : out STD_LOGIC; + wr_lvl_start_reg_0 : out STD_LOGIC; + rdlvl_stg1_start_reg_0 : out STD_LOGIC; + phy_write_calib : out STD_LOGIC; + phy_read_calib : out STD_LOGIC; + first_rdlvl_pat_r : out STD_LOGIC; + first_wrcal_pat_r : out STD_LOGIC; + rdlvl_stg1_done_r1_reg_0 : out STD_LOGIC; + calib_ctl_wren_reg_1 : out STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC_VECTOR ( 32 downto 0 ); + phy_dout : out STD_LOGIC_VECTOR ( 31 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[3]\ : out STD_LOGIC; + \my_empty_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[3]_0\ : out STD_LOGIC; + \my_empty_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[3]_1\ : out STD_LOGIC; + mem_init_done_r : out STD_LOGIC; + \init_state_r_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_lm_done_r : out STD_LOGIC; + \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 43 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 43 downto 0 ); + mux_wrdata_en : out STD_LOGIC; + mux_cmd_wren : out STD_LOGIC; + mux_reset_n : out STD_LOGIC; + D1 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + D2 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + D3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + D5 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + D6 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + D7 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + D8 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + D9 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + D0 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \write_buffer.wr_buf_out_data_reg[122]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \write_buffer.wr_buf_out_data_reg[123]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \write_buffer.wr_buf_out_data_reg[126]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \write_buffer.wr_buf_out_data_reg[108]\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \write_buffer.wr_buf_out_data_reg[121]\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \write_buffer.wr_buf_out_data_reg[125]\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + detect_pi_found_dqs_reg_0 : out STD_LOGIC; + \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_ras_n_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_cke_reg[3]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_we_n_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + wrcal_start_reg_0 : out STD_LOGIC; + pi_dqs_found_start_reg_0 : out STD_LOGIC; + mpr_rdlvl_start_reg_0 : out STD_LOGIC; + \calib_seq_reg[1]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); + CLK : in STD_LOGIC; + in0 : in STD_LOGIC; + pi_dqs_found_done_r1_reg_0 : in STD_LOGIC; + wrlvl_done_r_reg_0 : in STD_LOGIC; + wrlvl_rank_done : in STD_LOGIC; + prbs_rdlvl_done_pulse0 : in STD_LOGIC; + wrcal_resume_w : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rdlvl_last_byte_done : in STD_LOGIC; + pi_dqs_found_done : in STD_LOGIC; + \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_ctl_wr_i1_reg : in STD_LOGIC; + \init_state_r[1]_i_3_0\ : in STD_LOGIC; + \init_state_r_reg[4]_0\ : in STD_LOGIC; + \back_to_back_reads_4_1.num_reads_reg[1]_0\ : in STD_LOGIC; + \init_state_r[2]_i_5_0\ : in STD_LOGIC; + complex_row0_rd_done_reg_0 : in STD_LOGIC; + \complex_wait_cnt_reg[3]_0\ : in STD_LOGIC; + burst_addr_r_reg_0 : in STD_LOGIC; + wrlvl_byte_redo : in STD_LOGIC; + \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : in STD_LOGIC; + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + \wr_en_inferred__0_i_1_0\ : in STD_LOGIC; + \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC; + \wr_en_inferred__0_i_1__0_0\ : in STD_LOGIC; + \wr_ptr_timing_reg[0]_2\ : in STD_LOGIC; + \wr_en_inferred__0_i_1__1_0\ : in STD_LOGIC; + \init_state_r[2]_i_7_0\ : in STD_LOGIC; + \init_state_r[2]_i_7_1\ : in STD_LOGIC; + \init_state_r[0]_i_15_0\ : in STD_LOGIC; + \calib_data_offset_0_reg[3]_0\ : in STD_LOGIC; + \init_state_r[0]_i_3_0\ : in STD_LOGIC; + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_1\ : in STD_LOGIC; + ck_addr_cmd_delay_done : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + dqs_found_prech_req : in STD_LOGIC; + \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_1\ : in STD_LOGIC; + rdlvl_stg1_rank_done : in STD_LOGIC; + rdlvl_prech_req : in STD_LOGIC; + wrcal_prech_req : in STD_LOGIC; + rdlvl_pi_incdec : in STD_LOGIC; + done_dqs_tap_inc : in STD_LOGIC; + \init_state_r[0]_i_5_0\ : in STD_LOGIC; + \init_state_r[4]_i_7_0\ : in STD_LOGIC; + \init_state_r[4]_i_4_0\ : in STD_LOGIC; + \init_state_r[1]_i_4_0\ : in STD_LOGIC; + \init_state_r[1]_i_3_1\ : in STD_LOGIC; + pi_dqs_found_rank_done : in STD_LOGIC; + out_fifo : in STD_LOGIC_VECTOR ( 87 downto 0 ); + \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : in STD_LOGIC; + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_ras_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_we_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + out_fifo_0 : in STD_LOGIC; + out_fifo_1 : in STD_LOGIC_VECTOR ( 43 downto 0 ); + out_fifo_2 : in STD_LOGIC; + out_fifo_3 : in STD_LOGIC; + out_fifo_4 : in STD_LOGIC; + out_fifo_5 : in STD_LOGIC_VECTOR ( 43 downto 0 ); + out_fifo_6 : in STD_LOGIC; + mc_address : in STD_LOGIC_VECTOR ( 34 downto 0 ); + \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC; + rst_dqs_find_i_12 : in STD_LOGIC_VECTOR ( 0 to 0 ); + out_fifo_7 : in STD_LOGIC; + out_fifo_8 : in STD_LOGIC_VECTOR ( 38 downto 0 ); + out_fifo_9 : in STD_LOGIC; + mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 ); + out_fifo_10 : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 31 downto 0 ); + out_fifo_11 : in STD_LOGIC; + \calib_data_offset_0_reg[5]_0\ : in STD_LOGIC; + \calib_data_offset_0_reg[4]_0\ : in STD_LOGIC; + \calib_data_offset_0_reg[2]_0\ : in STD_LOGIC; + \calib_data_offset_0_reg[1]_0\ : in STD_LOGIC; + \calib_data_offset_0_reg[0]_0\ : in STD_LOGIC; + \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cnt_pwron_ce_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[18]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC; + mc_data_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); + \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[22]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_init : entity is "mig_7series_v4_2_ddr_phy_init"; +end ddr3_mig_7series_v4_2_ddr_phy_init; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_init is + signal address_w : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal address_w173_out : STD_LOGIC; + signal \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\ : STD_LOGIC; + signal \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\ : STD_LOGIC; + signal \back_to_back_reads_4_1.num_reads[2]_i_1_n_0\ : STD_LOGIC; + signal \back_to_back_reads_4_1.num_reads[2]_i_2_n_0\ : STD_LOGIC; + signal bank_w : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal burst_addr_r_i_1_n_0 : STD_LOGIC; + signal burst_addr_r_i_2_n_0 : STD_LOGIC; + signal calib_cke : STD_LOGIC_VECTOR ( 3 to 3 ); + signal calib_cmd : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \calib_cmd[0]_i_1_n_0\ : STD_LOGIC; + signal \calib_cmd[1]_i_1_n_0\ : STD_LOGIC; + signal \calib_cmd[2]_i_1_n_0\ : STD_LOGIC; + signal \calib_cmd[2]_i_2_n_0\ : STD_LOGIC; + signal \calib_cmd[2]_i_3_n_0\ : STD_LOGIC; + signal \calib_cmd[2]_i_4_n_0\ : STD_LOGIC; + signal \^calib_ctl_wren_reg_0\ : STD_LOGIC; + signal calib_data_offset_0 : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \calib_data_offset_0[3]_i_1_n_0\ : STD_LOGIC; + signal \calib_data_offset_0[5]_i_1_n_0\ : STD_LOGIC; + signal calib_odt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \calib_odt[0]_i_1_n_0\ : STD_LOGIC; + signal \calib_odt[0]_i_2_n_0\ : STD_LOGIC; + signal \calib_odt[0]_i_3_n_0\ : STD_LOGIC; + signal \calib_odt[0]_i_4_n_0\ : STD_LOGIC; + signal \calib_seq[0]_i_1_n_0\ : STD_LOGIC; + signal \calib_seq[1]_i_1_n_0\ : STD_LOGIC; + signal \^calib_seq_reg[1]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \^calib_wrdata_en\ : STD_LOGIC; + signal calib_wrdata_en_i_2_n_0 : STD_LOGIC; + signal clear : STD_LOGIC; + signal cnt_cmd_done_m7_r : STD_LOGIC; + signal cnt_cmd_done_m7_r_i_1_n_0 : STD_LOGIC; + signal cnt_cmd_done_m7_r_i_2_n_0 : STD_LOGIC; + signal cnt_cmd_done_r : STD_LOGIC; + signal cnt_cmd_done_r_i_1_n_0 : STD_LOGIC; + signal \cnt_cmd_r[0]_i_1_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[1]_i_1_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[2]_i_1_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[3]_i_1_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[4]_i_1_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[5]_i_1_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[6]_i_1_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[6]_i_2_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[6]_i_3_n_0\ : STD_LOGIC; + signal \cnt_cmd_r[6]_i_4_n_0\ : STD_LOGIC; + signal \cnt_cmd_r_reg_n_0_[0]\ : STD_LOGIC; + signal \cnt_cmd_r_reg_n_0_[1]\ : STD_LOGIC; + signal \cnt_cmd_r_reg_n_0_[2]\ : STD_LOGIC; + signal \cnt_cmd_r_reg_n_0_[3]\ : STD_LOGIC; + signal \cnt_cmd_r_reg_n_0_[4]\ : STD_LOGIC; + signal \cnt_cmd_r_reg_n_0_[5]\ : STD_LOGIC; + signal \cnt_cmd_r_reg_n_0_[6]\ : STD_LOGIC; + signal cnt_dllk_zqinit_done_r : STD_LOGIC; + signal cnt_dllk_zqinit_done_r_i_1_n_0 : STD_LOGIC; + signal \cnt_dllk_zqinit_r[7]_i_1_n_0\ : STD_LOGIC; + signal cnt_dllk_zqinit_r_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal cnt_init_af_done_r : STD_LOGIC; + signal cnt_init_af_done_r_i_1_n_0 : STD_LOGIC; + signal cnt_init_af_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \cnt_init_af_r[0]_i_1_n_0\ : STD_LOGIC; + signal \cnt_init_af_r[1]_i_1_n_0\ : STD_LOGIC; + signal cnt_init_mr_done_r : STD_LOGIC; + signal cnt_init_mr_done_r_i_1_n_0 : STD_LOGIC; + signal cnt_init_mr_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal cnt_init_mr_r1 : STD_LOGIC; + signal \cnt_init_mr_r[0]_i_1_n_0\ : STD_LOGIC; + signal \cnt_init_mr_r[0]_i_2_n_0\ : STD_LOGIC; + signal \cnt_init_mr_r[1]_i_1_n_0\ : STD_LOGIC; + signal cnt_pwron_ce_r_reg : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \^cnt_pwron_cke_done_r\ : STD_LOGIC; + signal cnt_pwron_cke_done_r_i_1_n_0 : STD_LOGIC; + signal cnt_pwron_cke_done_r_i_2_n_0 : STD_LOGIC; + signal cnt_pwron_cke_done_r_i_3_n_0 : STD_LOGIC; + signal \cnt_pwron_r[6]_i_2_n_0\ : STD_LOGIC; + signal \cnt_pwron_r[8]_i_2_n_0\ : STD_LOGIC; + signal cnt_pwron_r_reg : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal cnt_pwron_reset_done_r : STD_LOGIC; + signal cnt_pwron_reset_done_r_i_1_n_0 : STD_LOGIC; + signal cnt_pwron_reset_done_r_i_2_n_0 : STD_LOGIC; + signal cnt_txpr_done_r : STD_LOGIC; + signal cnt_txpr_done_r_i_1_n_0 : STD_LOGIC; + signal cnt_txpr_done_r_i_2_n_0 : STD_LOGIC; + signal \cnt_txpr_r[7]_i_3_n_0\ : STD_LOGIC; + signal cnt_txpr_r_reg : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal complex_address0 : STD_LOGIC; + signal \complex_address[9]_i_2_n_0\ : STD_LOGIC; + signal \complex_address[9]_i_3_n_0\ : STD_LOGIC; + signal \complex_address[9]_i_4_n_0\ : STD_LOGIC; + signal \complex_address_reg_n_0_[0]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[1]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[2]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[3]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[4]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[5]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[6]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[7]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[8]\ : STD_LOGIC; + signal \complex_address_reg_n_0_[9]\ : STD_LOGIC; + signal complex_byte_rd_done : STD_LOGIC; + signal complex_byte_rd_done_i_1_n_0 : STD_LOGIC; + signal complex_byte_rd_done_i_2_n_0 : STD_LOGIC; + signal \complex_num_reads[0]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads[1]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads[1]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_reads[1]_i_3_n_0\ : STD_LOGIC; + signal \complex_num_reads[1]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_reads[1]_i_5_n_0\ : STD_LOGIC; + signal \complex_num_reads[2]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads[2]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_reads[2]_i_3_n_0\ : STD_LOGIC; + signal \complex_num_reads[2]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_reads[2]_i_5_n_0\ : STD_LOGIC; + signal \complex_num_reads[2]_i_6_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_3_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_5_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_6_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_7_n_0\ : STD_LOGIC; + signal \complex_num_reads[3]_i_8_n_0\ : STD_LOGIC; + signal complex_num_reads_dec : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \complex_num_reads_dec[0]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads_dec[1]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads_dec[2]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads_dec[3]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_reads_dec[3]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_reads_dec[3]_i_3_n_0\ : STD_LOGIC; + signal \complex_num_reads_dec[3]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_reads_reg_n_0_[0]\ : STD_LOGIC; + signal \complex_num_reads_reg_n_0_[1]\ : STD_LOGIC; + signal \complex_num_reads_reg_n_0_[2]\ : STD_LOGIC; + signal \complex_num_reads_reg_n_0_[3]\ : STD_LOGIC; + signal \complex_num_writes[0]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_writes[1]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_writes[1]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_3_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_5_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_6_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_7_n_0\ : STD_LOGIC; + signal \complex_num_writes[2]_i_8_n_0\ : STD_LOGIC; + signal \complex_num_writes[3]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_writes[3]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_writes[3]_i_3_n_0\ : STD_LOGIC; + signal \complex_num_writes[3]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_10_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_11_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_12_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_13_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_14_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_15_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_16_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_17_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_18_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_1_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_3_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_5_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_6_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_7_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_8_n_0\ : STD_LOGIC; + signal \complex_num_writes[4]_i_9_n_0\ : STD_LOGIC; + signal \complex_num_writes_dec[4]_i_2_n_0\ : STD_LOGIC; + signal \complex_num_writes_dec[4]_i_4_n_0\ : STD_LOGIC; + signal \complex_num_writes_dec[4]_i_5_n_0\ : STD_LOGIC; + signal complex_num_writes_dec_reg : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \complex_num_writes_reg_n_0_[0]\ : STD_LOGIC; + signal \complex_num_writes_reg_n_0_[1]\ : STD_LOGIC; + signal \complex_num_writes_reg_n_0_[2]\ : STD_LOGIC; + signal \complex_num_writes_reg_n_0_[3]\ : STD_LOGIC; + signal \complex_num_writes_reg_n_0_[4]\ : STD_LOGIC; + signal complex_ocal_odt_ext : STD_LOGIC; + signal complex_ocal_odt_ext_i_1_n_0 : STD_LOGIC; + signal complex_ocal_odt_ext_i_2_n_0 : STD_LOGIC; + signal complex_ocal_odt_ext_i_3_n_0 : STD_LOGIC; + signal complex_ocal_reset_rd_addr : STD_LOGIC; + signal complex_ocal_reset_rd_addr0 : STD_LOGIC; + signal complex_ocal_reset_rd_addr_i_2_n_0 : STD_LOGIC; + signal complex_oclkdelay_calib_done_r1 : STD_LOGIC; + signal complex_oclkdelay_calib_start_int : STD_LOGIC; + signal complex_oclkdelay_calib_start_int_i_1_n_0 : STD_LOGIC; + signal complex_oclkdelay_calib_start_int_i_2_n_0 : STD_LOGIC; + signal complex_oclkdelay_calib_start_r1 : STD_LOGIC; + signal complex_odt_ext : STD_LOGIC; + signal complex_odt_ext_i_1_n_0 : STD_LOGIC; + signal complex_row0_rd_done : STD_LOGIC; + signal complex_row0_rd_done1 : STD_LOGIC; + signal complex_row0_rd_done_i_1_n_0 : STD_LOGIC; + signal complex_row0_wr_done : STD_LOGIC; + signal complex_row0_wr_done0 : STD_LOGIC; + signal complex_row1_rd_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \complex_row1_rd_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \complex_row1_rd_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \complex_row1_rd_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal complex_row1_rd_done : STD_LOGIC; + signal complex_row1_rd_done_i_1_n_0 : STD_LOGIC; + signal complex_row1_rd_done_i_2_n_0 : STD_LOGIC; + signal complex_row1_rd_done_r1 : STD_LOGIC; + signal complex_row1_wr_done : STD_LOGIC; + signal complex_row1_wr_done0 : STD_LOGIC; + signal complex_row_cnt : STD_LOGIC; + signal complex_row_cnt_ocal : STD_LOGIC; + signal complex_row_cnt_ocal0 : STD_LOGIC; + signal \complex_row_cnt_ocal[3]_i_4_n_0\ : STD_LOGIC; + signal \complex_row_cnt_ocal[3]_i_5_n_0\ : STD_LOGIC; + signal \complex_row_cnt_ocal[3]_i_6_n_0\ : STD_LOGIC; + signal \complex_row_cnt_ocal[3]_i_7_n_0\ : STD_LOGIC; + signal complex_row_cnt_ocal_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal complex_sample_cnt_inc0 : STD_LOGIC; + signal complex_sample_cnt_inc_i_2_n_0 : STD_LOGIC; + signal complex_sample_cnt_inc_r1 : STD_LOGIC; + signal complex_sample_cnt_inc_r2 : STD_LOGIC; + signal complex_sample_cnt_inc_reg_n_0 : STD_LOGIC; + signal \complex_wait_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \complex_wait_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal complex_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ddr2_pre_flag_r : STD_LOGIC; + signal ddr2_pre_flag_r_i_1_n_0 : STD_LOGIC; + signal ddr2_pre_flag_r_i_2_n_0 : STD_LOGIC; + signal ddr2_pre_flag_r_reg_n_0 : STD_LOGIC; + signal ddr2_refresh_flag_r : STD_LOGIC; + signal ddr2_refresh_flag_r_i_1_n_0 : STD_LOGIC; + signal ddr2_refresh_flag_r_i_2_n_0 : STD_LOGIC; + signal \^ddr3_lm_done_r\ : STD_LOGIC; + signal ddr3_lm_done_r_i_1_n_0 : STD_LOGIC; + signal ddr3_lm_done_r_i_2_n_0 : STD_LOGIC; + signal \^detect_pi_found_dqs\ : STD_LOGIC; + signal detect_pi_found_dqs0 : STD_LOGIC; + signal detect_pi_found_dqs_i_2_n_0 : STD_LOGIC; + signal detect_pi_found_dqs_i_3_n_0 : STD_LOGIC; + signal dqs_asrt_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \dqs_asrt_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \dqs_asrt_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal \en_cnt_div4.wrlvl_odt_i_1_n_0\ : STD_LOGIC; + signal \en_cnt_div4.wrlvl_odt_i_2_n_0\ : STD_LOGIC; + signal enable_wrlvl_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^first_rdlvl_pat_r\ : STD_LOGIC; + signal first_rdlvl_pat_r_i_1_n_0 : STD_LOGIC; + signal \^first_wrcal_pat_r\ : STD_LOGIC; + signal first_wrcal_pat_r_i_1_n_0 : STD_LOGIC; + signal first_wrcal_pat_r_i_2_n_0 : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_22_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\ : STD_LOGIC; + signal \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\ : STD_LOGIC; + signal \gen_rnk[0].mr1_r_reg_n_0_[0][0]\ : STD_LOGIC; + signal init_complete_r1 : STD_LOGIC; + signal init_complete_r1_timing : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of init_complete_r1_timing : signal is "true"; + signal init_complete_r2 : STD_LOGIC; + signal init_complete_r_i_1_n_0 : STD_LOGIC; + signal init_complete_r_reg_n_0 : STD_LOGIC; + signal init_complete_r_timing : STD_LOGIC; + attribute RTL_KEEP of init_complete_r_timing : signal is "true"; + signal init_complete_r_timing_i_1_n_0 : STD_LOGIC; + signal init_next_state199_out : STD_LOGIC; + signal init_state_r : STD_LOGIC_VECTOR ( 6 to 6 ); + signal init_state_r1 : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal \init_state_r[0]_i_10_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_11_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_12_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_13_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_14_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_15_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_16_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_17_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_18_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_19_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_1_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_20_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_21_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_22_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_23_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_25_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_27_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_28_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_29_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_2_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_30_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_31_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_32_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_33_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_34_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_35_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_36_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_3_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_4_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_5_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_6_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_7_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_8_n_0\ : STD_LOGIC; + signal \init_state_r[0]_i_9_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_10_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_11_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_12_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_13_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_14_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_15_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_16_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_17_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_18_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_19_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_1_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_20_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_21_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_22_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_23_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_24_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_25_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_28_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_29_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_2_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_30_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_32_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_33_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_34_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_35_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_3_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_4_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_5_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_6_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_7_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_8_n_0\ : STD_LOGIC; + signal \init_state_r[1]_i_9_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_10_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_11_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_12_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_13_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_14_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_15_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_16_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_17_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_18_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_19_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_1_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_20_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_21_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_22_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_23_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_24_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_25_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_26_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_27_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_28_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_29_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_2_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_30_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_31_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_34_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_35_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_36_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_37_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_38_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_3_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_4_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_5_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_6_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_7_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_8_n_0\ : STD_LOGIC; + signal \init_state_r[2]_i_9_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_10_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_11_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_12_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_13_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_14_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_15_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_16_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_17_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_18_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_19_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_1_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_20_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_21_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_22_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_2_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_3_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_4_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_5_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_6_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_7_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_8_n_0\ : STD_LOGIC; + signal \init_state_r[3]_i_9_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_10_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_11_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_12_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_13_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_14_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_15_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_16_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_17_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_18_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_19_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_1_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_20_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_21_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_22_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_23_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_24_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_25_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_26_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_27_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_28_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_29_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_2_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_30_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_32_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_33_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_34_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_35_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_37_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_38_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_39_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_3_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_40_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_41_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_43_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_44_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_4_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_5_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_6_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_7_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_8_n_0\ : STD_LOGIC; + signal \init_state_r[4]_i_9_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_10_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_11_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_12_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_13_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_14_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_15_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_16_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_17_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_18_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_19_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_1_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_20_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_21_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_22_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_23_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_24_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_25_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_26_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_27_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_28_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_29_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_2_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_30_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_31_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_32_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_33_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_3_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_4_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_5_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_6_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_7_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_8_n_0\ : STD_LOGIC; + signal \init_state_r[5]_i_9_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_10_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_1_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_2_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_3_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_4_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_5_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_6_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_7_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_8_n_0\ : STD_LOGIC; + signal \init_state_r[6]_i_9_n_0\ : STD_LOGIC; + signal \^init_state_r_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \init_state_r_reg_n_0_[0]\ : STD_LOGIC; + signal \init_state_r_reg_n_0_[1]\ : STD_LOGIC; + signal \init_state_r_reg_n_0_[2]\ : STD_LOGIC; + signal \init_state_r_reg_n_0_[3]\ : STD_LOGIC; + signal \init_state_r_reg_n_0_[4]\ : STD_LOGIC; + signal \init_state_r_reg_n_0_[5]\ : STD_LOGIC; + signal \^mem_init_done_r\ : STD_LOGIC; + signal mem_init_done_r_i_1_n_0 : STD_LOGIC; + signal mem_init_done_r_i_2_n_0 : STD_LOGIC; + signal mpr_rdlvl_start_i_1_n_0 : STD_LOGIC; + signal mpr_rdlvl_start_i_2_n_0 : STD_LOGIC; + signal \^mpr_rdlvl_start_reg_0\ : STD_LOGIC; + signal num_reads : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal num_reads0 : STD_LOGIC; + signal num_refresh0 : STD_LOGIC; + signal \num_refresh[3]_i_1_n_0\ : STD_LOGIC; + signal \num_refresh[3]_i_4_n_0\ : STD_LOGIC; + signal \num_refresh[3]_i_5_n_0\ : STD_LOGIC; + signal \num_refresh[3]_i_6_n_0\ : STD_LOGIC; + signal num_refresh_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \ocal_act_wait_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \ocal_act_wait_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal \ocal_act_wait_cnt[3]_i_4_n_0\ : STD_LOGIC; + signal ocal_act_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal oclk_wr_cnt0 : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \oclk_wr_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \oclk_wr_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \oclk_wr_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \oclk_wr_cnt[3]_i_4_n_0\ : STD_LOGIC; + signal oclk_wr_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \odd_cwl.phy_cas_n[1]_i_1_n_0\ : STD_LOGIC; + signal \odd_cwl.phy_ras_n[1]_i_1_n_0\ : STD_LOGIC; + signal \odd_cwl.phy_ras_n[1]_i_2_n_0\ : STD_LOGIC; + signal \odd_cwl.phy_ras_n[1]_i_3_n_0\ : STD_LOGIC; + signal \odd_cwl.phy_ras_n[1]_i_4_n_0\ : STD_LOGIC; + signal \odd_cwl.phy_ras_n[1]_i_5_n_0\ : STD_LOGIC; + signal \odd_cwl.phy_ras_n[1]_i_6_n_0\ : STD_LOGIC; + signal \odd_cwl.phy_we_n[1]_i_1_n_0\ : STD_LOGIC; + signal \one_rank.stg1_wr_done_i_1_n_0\ : STD_LOGIC; + signal \^one_rank.stg1_wr_done_reg_0\ : STD_LOGIC; + signal p_0_in0_in : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal p_116_in : STD_LOGIC; + signal p_15_in : STD_LOGIC_VECTOR ( 3 to 3 ); + signal phy_bank : STD_LOGIC_VECTOR ( 11 downto 9 ); + signal phy_cas_n : STD_LOGIC_VECTOR ( 1 to 1 ); + signal phy_ras_n : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^phy_read_calib\ : STD_LOGIC; + signal phy_reset_n : STD_LOGIC; + signal phy_we_n : STD_LOGIC_VECTOR ( 1 to 1 ); + signal phy_wrdata : STD_LOGIC_VECTOR ( 126 downto 13 ); + signal phy_wrdata_en : STD_LOGIC; + signal \^phy_write_calib\ : STD_LOGIC; + signal \^pi_calib_done\ : STD_LOGIC; + signal pi_calib_done_r : STD_LOGIC; + signal pi_calib_done_r_i_1_n_0 : STD_LOGIC; + signal pi_calib_rank_done_r : STD_LOGIC; + signal pi_dqs_found_start_i_1_n_0 : STD_LOGIC; + signal pi_dqs_found_start_i_2_n_0 : STD_LOGIC; + signal \^pi_dqs_found_start_reg_0\ : STD_LOGIC; + signal pi_phase_locked_all_r1 : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of pi_phase_locked_all_r1 : signal is "true"; + signal pi_phase_locked_all_r2 : STD_LOGIC; + attribute async_reg of pi_phase_locked_all_r2 : signal is "true"; + signal pi_phase_locked_all_r3 : STD_LOGIC; + attribute async_reg of pi_phase_locked_all_r3 : signal is "true"; + signal pi_phase_locked_all_r4 : STD_LOGIC; + attribute async_reg of pi_phase_locked_all_r4 : signal is "true"; + signal \^prbs_rdlvl_done_pulse_reg_0\ : STD_LOGIC; + signal \prech_done_dly_r_reg[15]_srl16_n_0\ : STD_LOGIC; + signal prech_done_pre : STD_LOGIC; + signal prech_pending_r : STD_LOGIC; + signal prech_pending_r_i_1_n_0 : STD_LOGIC; + signal prech_pending_r_i_2_n_0 : STD_LOGIC; + signal prech_pending_r_i_3_n_0 : STD_LOGIC; + signal prech_pending_r_i_4_n_0 : STD_LOGIC; + signal prech_pending_r_i_5_n_0 : STD_LOGIC; + signal prech_pending_r_i_6_n_0 : STD_LOGIC; + signal prech_pending_r_i_7_n_0 : STD_LOGIC; + signal prech_req : STD_LOGIC; + signal prech_req_posedge_r0 : STD_LOGIC; + signal prech_req_posedge_r_i_2_n_0 : STD_LOGIC; + signal prech_req_posedge_r_i_3_n_0 : STD_LOGIC; + signal \^prech_req_posedge_r_reg_0\ : STD_LOGIC; + signal prech_req_r : STD_LOGIC; + signal pwron_ce_r : STD_LOGIC; + signal pwron_ce_r_i_1_n_0 : STD_LOGIC; + signal pwron_ce_r_i_2_n_0 : STD_LOGIC; + signal rdlvl_last_byte_done_r : STD_LOGIC; + signal rdlvl_start_dly0_r : STD_LOGIC_VECTOR ( 14 to 14 ); + signal \rdlvl_start_dly0_r_reg[13]_srl14_n_0\ : STD_LOGIC; + signal rdlvl_start_pre : STD_LOGIC; + signal rdlvl_start_pre_i_1_n_0 : STD_LOGIC; + signal \^rdlvl_stg1_done_r1_reg_0\ : STD_LOGIC; + signal rdlvl_stg1_start_i_1_n_0 : STD_LOGIC; + signal \^rdlvl_stg1_start_reg_0\ : STD_LOGIC; + signal read_calib_i_1_n_0 : STD_LOGIC; + signal read_calib_i_2_n_0 : STD_LOGIC; + signal reg_ctrl_cnt_r : STD_LOGIC; + signal reg_ctrl_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal reset_rd_addr_r1 : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\ : STD_LOGIC; + signal \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\ : STD_LOGIC; + signal stg1_wr_done : STD_LOGIC; + signal \stg1_wr_rd_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[4]_i_2_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[4]_i_3_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[4]_i_4_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[6]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[6]_i_2_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[7]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[8]_i_1_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[8]_i_2_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[8]_i_3_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[8]_i_4_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[8]_i_5_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt[8]_i_6_n_0\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[6]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[7]\ : STD_LOGIC; + signal \stg1_wr_rd_cnt_reg_n_0_[8]\ : STD_LOGIC; + signal temp_lmr_done : STD_LOGIC; + signal \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\ : STD_LOGIC; + signal \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\ : STD_LOGIC; + signal \wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0\ : STD_LOGIC; + signal \wr_done_victim_rotate.complex_row0_wr_done_i_5_n_0\ : STD_LOGIC; + signal \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\ : STD_LOGIC; + signal wr_level_dqs_asrt : STD_LOGIC; + signal wr_level_dqs_asrt_i_1_n_0 : STD_LOGIC; + signal wr_level_dqs_asrt_r1 : STD_LOGIC; + signal wr_lvl_start_i_1_n_0 : STD_LOGIC; + signal \^wr_lvl_start_reg_0\ : STD_LOGIC; + signal wr_victim_inc : STD_LOGIC; + signal wr_victim_inc0 : STD_LOGIC; + signal wr_victim_inc_i_2_n_0 : STD_LOGIC; + signal wrcal_final_chk : STD_LOGIC; + signal wrcal_final_chk_i_1_n_0 : STD_LOGIC; + signal wrcal_final_chk_i_2_n_0 : STD_LOGIC; + signal wrcal_rd_wait_i_1_n_0 : STD_LOGIC; + signal wrcal_reads : STD_LOGIC; + signal wrcal_reads05_out : STD_LOGIC; + signal \wrcal_reads[0]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_reads[1]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_reads[2]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_reads[3]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_reads[4]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_reads[5]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_reads[6]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_reads[7]_i_2_n_0\ : STD_LOGIC; + signal \wrcal_reads[7]_i_3_n_0\ : STD_LOGIC; + signal \wrcal_reads[7]_i_4_n_0\ : STD_LOGIC; + signal \wrcal_reads[7]_i_5_n_0\ : STD_LOGIC; + signal \wrcal_reads[7]_i_6_n_0\ : STD_LOGIC; + signal \wrcal_reads[7]_i_8_n_0\ : STD_LOGIC; + signal \wrcal_reads[7]_i_9_n_0\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[0]\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[1]\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[2]\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[3]\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[4]\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[5]\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[6]\ : STD_LOGIC; + signal \wrcal_reads_reg_n_0_[7]\ : STD_LOGIC; + signal wrcal_resume_r : STD_LOGIC; + signal wrcal_start_dly_r : STD_LOGIC_VECTOR ( 5 to 5 ); + signal \wrcal_start_dly_r_reg[4]_srl5_n_0\ : STD_LOGIC; + signal wrcal_start_i_1_n_0 : STD_LOGIC; + signal wrcal_start_pre : STD_LOGIC; + signal \^wrcal_start_reg_0\ : STD_LOGIC; + signal wrcal_wr_cnt0 : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \wrcal_wr_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_wr_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_wr_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_wr_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \wrcal_wr_cnt[3]_i_4_n_0\ : STD_LOGIC; + signal wrcal_wr_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1_n_0\ : STD_LOGIC; + signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2_n_0\ : STD_LOGIC; + signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1_n_0\ : STD_LOGIC; + signal write_calib_i_1_n_0 : STD_LOGIC; + signal write_calib_i_2_n_0 : STD_LOGIC; + signal wrlvl_active : STD_LOGIC; + signal wrlvl_active_i_1_n_0 : STD_LOGIC; + signal wrlvl_active_r1 : STD_LOGIC; + signal wrlvl_done_r : STD_LOGIC; + signal \^wrlvl_done_r1\ : STD_LOGIC; + signal \^wrlvl_final_if_rst\ : STD_LOGIC; + signal wrlvl_final_if_rst_i_1_n_0 : STD_LOGIC; + signal wrlvl_final_if_rst_i_2_n_0 : STD_LOGIC; + signal wrlvl_odt : STD_LOGIC; + signal wrlvl_odt_ctl : STD_LOGIC; + signal wrlvl_odt_ctl_i_1_n_0 : STD_LOGIC; + signal wrlvl_odt_ctl_i_2_n_0 : STD_LOGIC; + signal wrlvl_rank_done_r1 : STD_LOGIC; + signal wrlvl_rank_done_r6_reg_srl5_n_0 : STD_LOGIC; + signal wrlvl_rank_done_r7 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \back_to_back_reads_4_1.num_reads[0]_i_2\ : label is "soft_lutpair332"; + attribute SOFT_HLUTNM of \back_to_back_reads_4_1.num_reads[2]_i_1\ : label is "soft_lutpair332"; + attribute SOFT_HLUTNM of \calib_cmd[0]_i_1\ : label is "soft_lutpair350"; + attribute SOFT_HLUTNM of \calib_cmd[1]_i_1\ : label is "soft_lutpair351"; + attribute SOFT_HLUTNM of \calib_cmd[2]_i_1\ : label is "soft_lutpair382"; + attribute SOFT_HLUTNM of calib_ctl_wren_i_1 : label is "soft_lutpair309"; + attribute SOFT_HLUTNM of \calib_data_offset_0[3]_i_1\ : label is "soft_lutpair351"; + attribute SOFT_HLUTNM of \calib_odt[0]_i_4\ : label is "soft_lutpair301"; + attribute SOFT_HLUTNM of \calib_seq[0]_i_1\ : label is "soft_lutpair379"; + attribute SOFT_HLUTNM of \calib_seq[1]_i_1\ : label is "soft_lutpair379"; + attribute SOFT_HLUTNM of cnt_cmd_done_m7_r_i_2 : label is "soft_lutpair396"; + attribute SOFT_HLUTNM of \cnt_cmd_r[0]_i_1\ : label is "soft_lutpair415"; + attribute SOFT_HLUTNM of \cnt_cmd_r[1]_i_1\ : label is "soft_lutpair415"; + attribute SOFT_HLUTNM of \cnt_cmd_r[2]_i_1\ : label is "soft_lutpair396"; + attribute SOFT_HLUTNM of \cnt_cmd_r[3]_i_1\ : label is "soft_lutpair341"; + attribute SOFT_HLUTNM of \cnt_cmd_r[4]_i_1\ : label is "soft_lutpair341"; + attribute SOFT_HLUTNM of cnt_dllk_zqinit_done_r_i_1 : label is "soft_lutpair374"; + attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[1]_i_1\ : label is "soft_lutpair397"; + attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[2]_i_1\ : label is "soft_lutpair397"; + attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[3]_i_1\ : label is "soft_lutpair340"; + attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[4]_i_1\ : label is "soft_lutpair340"; + attribute SOFT_HLUTNM of \cnt_dllk_zqinit_r[7]_i_2\ : label is "soft_lutpair374"; + attribute SOFT_HLUTNM of cnt_init_af_done_r_i_1 : label is "soft_lutpair303"; + attribute SOFT_HLUTNM of \cnt_init_af_r[1]_i_1\ : label is "soft_lutpair303"; + attribute SOFT_HLUTNM of \cnt_init_mr_r[0]_i_2\ : label is "soft_lutpair370"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[1]_i_1\ : label is "soft_lutpair399"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[2]_i_1\ : label is "soft_lutpair399"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[3]_i_1\ : label is "soft_lutpair342"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[4]_i_1\ : label is "soft_lutpair342"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[6]_i_1\ : label is "soft_lutpair394"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[7]_i_1\ : label is "soft_lutpair394"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[8]_i_1\ : label is "soft_lutpair339"; + attribute SOFT_HLUTNM of \cnt_pwron_ce_r[9]_i_1\ : label is "soft_lutpair339"; + attribute SOFT_HLUTNM of \cnt_pwron_r[0]_i_1\ : label is "soft_lutpair418"; + attribute SOFT_HLUTNM of \cnt_pwron_r[1]_i_1\ : label is "soft_lutpair418"; + attribute SOFT_HLUTNM of \cnt_pwron_r[2]_i_1\ : label is "soft_lutpair400"; + attribute SOFT_HLUTNM of \cnt_pwron_r[3]_i_1\ : label is "soft_lutpair343"; + attribute SOFT_HLUTNM of \cnt_pwron_r[4]_i_1\ : label is "soft_lutpair343"; + attribute SOFT_HLUTNM of \cnt_pwron_r[6]_i_2\ : label is "soft_lutpair400"; + attribute SOFT_HLUTNM of \cnt_pwron_r[7]_i_1\ : label is "soft_lutpair372"; + attribute SOFT_HLUTNM of \cnt_pwron_r[8]_i_1\ : label is "soft_lutpair372"; + attribute SOFT_HLUTNM of cnt_txpr_done_r_i_2 : label is "soft_lutpair373"; + attribute SOFT_HLUTNM of \cnt_txpr_r[0]_i_1\ : label is "soft_lutpair419"; + attribute SOFT_HLUTNM of \cnt_txpr_r[1]_i_1\ : label is "soft_lutpair419"; + attribute SOFT_HLUTNM of \cnt_txpr_r[2]_i_1\ : label is "soft_lutpair373"; + attribute SOFT_HLUTNM of \cnt_txpr_r[3]_i_1\ : label is "soft_lutpair344"; + attribute SOFT_HLUTNM of \cnt_txpr_r[4]_i_1\ : label is "soft_lutpair344"; + attribute SOFT_HLUTNM of \cnt_txpr_r[6]_i_1\ : label is "soft_lutpair395"; + attribute SOFT_HLUTNM of \cnt_txpr_r[7]_i_2\ : label is "soft_lutpair395"; + attribute SOFT_HLUTNM of \complex_address[9]_i_3\ : label is "soft_lutpair324"; + attribute SOFT_HLUTNM of \complex_num_reads[1]_i_3\ : label is "soft_lutpair361"; + attribute SOFT_HLUTNM of \complex_num_reads[2]_i_2\ : label is "soft_lutpair380"; + attribute SOFT_HLUTNM of \complex_num_reads[2]_i_3\ : label is "soft_lutpair361"; + attribute SOFT_HLUTNM of \complex_num_reads[2]_i_4\ : label is "soft_lutpair360"; + attribute SOFT_HLUTNM of \complex_num_reads[2]_i_6\ : label is "soft_lutpair349"; + attribute SOFT_HLUTNM of \complex_num_reads[3]_i_4\ : label is "soft_lutpair349"; + attribute SOFT_HLUTNM of \complex_num_reads[3]_i_8\ : label is "soft_lutpair353"; + attribute SOFT_HLUTNM of \complex_num_reads_dec[1]_i_1\ : label is "soft_lutpair360"; + attribute SOFT_HLUTNM of \complex_num_writes[2]_i_4\ : label is "soft_lutpair381"; + attribute SOFT_HLUTNM of \complex_num_writes[2]_i_7\ : label is "soft_lutpair412"; + attribute SOFT_HLUTNM of \complex_num_writes[2]_i_8\ : label is "soft_lutpair353"; + attribute SOFT_HLUTNM of \complex_num_writes[3]_i_2\ : label is "soft_lutpair381"; + attribute SOFT_HLUTNM of \complex_num_writes[3]_i_3\ : label is "soft_lutpair322"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_13\ : label is "soft_lutpair298"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_15\ : label is "soft_lutpair311"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_16\ : label is "soft_lutpair298"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_17\ : label is "soft_lutpair412"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_18\ : label is "soft_lutpair312"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_6\ : label is "soft_lutpair297"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_7\ : label is "soft_lutpair380"; + attribute SOFT_HLUTNM of \complex_num_writes[4]_i_9\ : label is "soft_lutpair322"; + attribute SOFT_HLUTNM of \complex_num_writes_dec[2]_i_1\ : label is "soft_lutpair320"; + attribute SOFT_HLUTNM of \complex_num_writes_dec[4]_i_5\ : label is "soft_lutpair320"; + attribute SOFT_HLUTNM of complex_ocal_odt_ext_i_3 : label is "soft_lutpair301"; + attribute SOFT_HLUTNM of complex_oclkdelay_calib_start_int_i_1 : label is "soft_lutpair375"; + attribute SOFT_HLUTNM of complex_row0_rd_done_i_3 : label is "soft_lutpair330"; + attribute SOFT_HLUTNM of \complex_row_cnt_ocal[1]_i_1\ : label is "soft_lutpair398"; + attribute SOFT_HLUTNM of \complex_row_cnt_ocal[2]_i_1\ : label is "soft_lutpair398"; + attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_3\ : label is "soft_lutpair363"; + attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_4\ : label is "soft_lutpair363"; + attribute SOFT_HLUTNM of \complex_row_cnt_ocal[3]_i_7\ : label is "soft_lutpair312"; + attribute SOFT_HLUTNM of complex_sample_cnt_inc_i_2 : label is "soft_lutpair291"; + attribute SOFT_HLUTNM of \complex_wait_cnt[0]_i_1\ : label is "soft_lutpair421"; + attribute SOFT_HLUTNM of \complex_wait_cnt[1]_i_1\ : label is "soft_lutpair421"; + attribute SOFT_HLUTNM of \complex_wait_cnt[2]_i_1\ : label is "soft_lutpair377"; + attribute SOFT_HLUTNM of \complex_wait_cnt[3]_i_2\ : label is "soft_lutpair377"; + attribute SOFT_HLUTNM of ddr3_lm_done_r_i_2 : label is "soft_lutpair293"; + attribute SOFT_HLUTNM of detect_pi_found_dqs_i_2 : label is "soft_lutpair407"; + attribute SOFT_HLUTNM of detect_pi_found_dqs_i_3 : label is "soft_lutpair408"; + attribute SOFT_HLUTNM of \en_cnt_div4.enable_wrlvl_cnt[2]_i_1\ : label is "soft_lutpair327"; + attribute SOFT_HLUTNM of \en_cnt_div4.enable_wrlvl_cnt[3]_i_1\ : label is "soft_lutpair327"; + attribute SOFT_HLUTNM of first_wrcal_pat_r_i_2 : label is "soft_lutpair336"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2\ : label is "soft_lutpair347"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3\ : label is "soft_lutpair346"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2\ : label is "soft_lutpair407"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5\ : label is "soft_lutpair321"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6\ : label is "soft_lutpair364"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3\ : label is "soft_lutpair346"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4\ : label is "soft_lutpair348"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3\ : label is "soft_lutpair393"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11\ : label is "soft_lutpair371"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12\ : label is "soft_lutpair413"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13\ : label is "soft_lutpair311"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14\ : label is "soft_lutpair291"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3\ : label is "soft_lutpair290"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5\ : label is "soft_lutpair393"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4\ : label is "soft_lutpair371"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5\ : label is "soft_lutpair338"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6\ : label is "soft_lutpair368"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\ : label is "soft_lutpair352"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3\ : label is "soft_lutpair338"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5\ : label is "soft_lutpair337"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7\ : label is "soft_lutpair369"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2\ : label is "soft_lutpair337"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4\ : label is "soft_lutpair321"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13\ : label is "soft_lutpair290"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16\ : label is "soft_lutpair297"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19\ : label is "soft_lutpair324"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20\ : label is "soft_lutpair302"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3\ : label is "soft_lutpair369"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4\ : label is "soft_lutpair408"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5\ : label is "soft_lutpair413"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6\ : label is "soft_lutpair388"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1\ : label is "soft_lutpair368"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1\ : label is "soft_lutpair364"; + attribute SOFT_HLUTNM of \gen_reset_obuf.u_reset_obuf_i_1\ : label is "soft_lutpair414"; + attribute KEEP : string; + attribute KEEP of init_complete_r1_timing_reg : label is "yes"; + attribute KEEP of init_complete_r_timing_reg : label is "yes"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_15\ : label is "soft_lutpair308"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_17\ : label is "soft_lutpair388"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_19\ : label is "soft_lutpair307"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_2\ : label is "soft_lutpair366"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_30\ : label is "soft_lutpair314"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_33\ : label is "soft_lutpair319"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_34\ : label is "soft_lutpair317"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_35\ : label is "soft_lutpair299"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_36\ : label is "soft_lutpair306"; + attribute SOFT_HLUTNM of \init_state_r[0]_i_8\ : label is "soft_lutpair313"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_19\ : label is "soft_lutpair299"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_20\ : label is "soft_lutpair411"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_21\ : label is "soft_lutpair314"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_22\ : label is "soft_lutpair328"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_25\ : label is "soft_lutpair310"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_33\ : label is "soft_lutpair313"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_34\ : label is "soft_lutpair318"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_35\ : label is "soft_lutpair305"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_9\ : label is "soft_lutpair308"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_1\ : label is "soft_lutpair366"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_10\ : label is "soft_lutpair295"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_13\ : label is "soft_lutpair410"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_14\ : label is "soft_lutpair387"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_17\ : label is "soft_lutpair292"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_18\ : label is "soft_lutpair387"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_25\ : label is "soft_lutpair334"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_27\ : label is "soft_lutpair410"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_28\ : label is "soft_lutpair316"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_30\ : label is "soft_lutpair305"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_31\ : label is "soft_lutpair385"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_34\ : label is "soft_lutpair310"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_35\ : label is "soft_lutpair316"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_36\ : label is "soft_lutpair385"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_37\ : label is "soft_lutpair315"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_38\ : label is "soft_lutpair304"; + attribute SOFT_HLUTNM of \init_state_r[3]_i_13\ : label is "soft_lutpair367"; + attribute SOFT_HLUTNM of \init_state_r[3]_i_17\ : label is "soft_lutpair335"; + attribute SOFT_HLUTNM of \init_state_r[3]_i_21\ : label is "soft_lutpair304"; + attribute SOFT_HLUTNM of \init_state_r[3]_i_22\ : label is "soft_lutpair409"; + attribute SOFT_HLUTNM of \init_state_r[3]_i_7\ : label is "soft_lutpair356"; + attribute SOFT_HLUTNM of \init_state_r[3]_i_8\ : label is "soft_lutpair334"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_16\ : label is "soft_lutpair367"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_17\ : label is "soft_lutpair318"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_19\ : label is "soft_lutpair336"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_22\ : label is "soft_lutpair354"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_23\ : label is "soft_lutpair315"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_29\ : label is "soft_lutpair296"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_30\ : label is "soft_lutpair335"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_33\ : label is "soft_lutpair357"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_34\ : label is "soft_lutpair358"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_35\ : label is "soft_lutpair357"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_38\ : label is "soft_lutpair319"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_39\ : label is "soft_lutpair306"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_41\ : label is "soft_lutpair317"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_43\ : label is "soft_lutpair384"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_8\ : label is "soft_lutpair362"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_12\ : label is "soft_lutpair409"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_17\ : label is "soft_lutpair329"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_25\ : label is "soft_lutpair296"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_26\ : label is "soft_lutpair307"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_27\ : label is "soft_lutpair347"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_29\ : label is "soft_lutpair328"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_31\ : label is "soft_lutpair411"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_33\ : label is "soft_lutpair355"; + attribute SOFT_HLUTNM of \init_state_r[5]_i_5\ : label is "soft_lutpair391"; + attribute SOFT_HLUTNM of \init_state_r[6]_i_10\ : label is "soft_lutpair309"; + attribute SOFT_HLUTNM of \init_state_r[6]_i_3\ : label is "soft_lutpair370"; + attribute SOFT_HLUTNM of \init_state_r[6]_i_4\ : label is "soft_lutpair375"; + attribute SOFT_HLUTNM of \init_state_r[6]_i_7\ : label is "soft_lutpair354"; + attribute SOFT_HLUTNM of mpr_rdlvl_start_i_1 : label is "soft_lutpair376"; + attribute SOFT_HLUTNM of \my_empty[7]_i_2__0\ : label is "soft_lutpair392"; + attribute SOFT_HLUTNM of \my_empty[7]_i_2__1\ : label is "soft_lutpair392"; + attribute SOFT_HLUTNM of \num_refresh[1]_i_1\ : label is "soft_lutpair401"; + attribute SOFT_HLUTNM of \num_refresh[2]_i_1\ : label is "soft_lutpair401"; + attribute SOFT_HLUTNM of \num_refresh[3]_i_3\ : label is "soft_lutpair358"; + attribute SOFT_HLUTNM of \ocal_act_wait_cnt[0]_i_1\ : label is "soft_lutpair422"; + attribute SOFT_HLUTNM of \ocal_act_wait_cnt[1]_i_1\ : label is "soft_lutpair422"; + attribute SOFT_HLUTNM of \ocal_act_wait_cnt[2]_i_1\ : label is "soft_lutpair333"; + attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_2\ : label is "soft_lutpair329"; + attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_3\ : label is "soft_lutpair333"; + attribute SOFT_HLUTNM of \ocal_act_wait_cnt[3]_i_4\ : label is "soft_lutpair391"; + attribute SOFT_HLUTNM of \oclk_wr_cnt[0]_i_1\ : label is "soft_lutpair416"; + attribute SOFT_HLUTNM of \oclk_wr_cnt[1]_i_1\ : label is "soft_lutpair416"; + attribute SOFT_HLUTNM of \oclk_wr_cnt[3]_i_3\ : label is "soft_lutpair356"; + attribute SOFT_HLUTNM of \odd_cwl.phy_cas_n[1]_i_1\ : label is "soft_lutpair350"; + attribute SOFT_HLUTNM of \odd_cwl.phy_ras_n[1]_i_6\ : label is "soft_lutpair362"; + attribute SOFT_HLUTNM of \odd_cwl.phy_we_n[1]_i_1\ : label is "soft_lutpair382"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[0]_i_1\ : label is "soft_lutpair402"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[17]_i_1\ : label is "soft_lutpair403"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[18]_i_1\ : label is "soft_lutpair404"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[19]_i_1\ : label is "soft_lutpair404"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[1]_i_1\ : label is "soft_lutpair402"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[20]_i_1\ : label is "soft_lutpair405"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[21]_i_1\ : label is "soft_lutpair405"; + attribute SOFT_HLUTNM of \phy_ctl_wd_i1[2]_i_1\ : label is "soft_lutpair403"; + attribute SOFT_HLUTNM of phy_ctl_wr_i1_i_1 : label is "soft_lutpair414"; + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of pi_phase_locked_all_r1_reg : label is std.standard.true; + attribute KEEP of pi_phase_locked_all_r1_reg : label is "yes"; + attribute ASYNC_REG_boolean of pi_phase_locked_all_r2_reg : label is std.standard.true; + attribute KEEP of pi_phase_locked_all_r2_reg : label is "yes"; + attribute ASYNC_REG_boolean of pi_phase_locked_all_r3_reg : label is std.standard.true; + attribute KEEP of pi_phase_locked_all_r3_reg : label is "yes"; + attribute ASYNC_REG_boolean of pi_phase_locked_all_r4_reg : label is std.standard.true; + attribute KEEP of pi_phase_locked_all_r4_reg : label is "yes"; + attribute srl_bus_name : string; + attribute srl_bus_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg "; + attribute srl_name : string; + attribute srl_name of \prech_done_dly_r_reg[15]_srl16\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 "; + attribute SOFT_HLUTNM of \prech_done_dly_r_reg[15]_srl16_i_1\ : label is "soft_lutpair383"; + attribute SOFT_HLUTNM of prech_pending_r_i_1 : label is "soft_lutpair383"; + attribute SOFT_HLUTNM of prech_req_posedge_r_i_2 : label is "soft_lutpair288"; + attribute SOFT_HLUTNM of prech_req_posedge_r_i_3 : label is "soft_lutpair300"; + attribute srl_bus_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg "; + attribute srl_name of \rdlvl_start_dly0_r_reg[13]_srl14\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 "; + attribute SOFT_HLUTNM of read_calib_i_2 : label is "soft_lutpair300"; + attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[0]_i_1\ : label is "soft_lutpair420"; + attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[1]_i_1\ : label is "soft_lutpair420"; + attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[2]_i_1\ : label is "soft_lutpair378"; + attribute SOFT_HLUTNM of \reg_ctrl_cnt_r[3]_i_3\ : label is "soft_lutpair378"; + attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[0]_i_1\ : label is "soft_lutpair331"; + attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[1]_i_1\ : label is "soft_lutpair331"; + attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[3]_i_1\ : label is "soft_lutpair323"; + attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[4]_i_4\ : label is "soft_lutpair359"; + attribute SOFT_HLUTNM of \row_cnt_victim_rotate.complex_row_cnt[5]_i_2\ : label is "soft_lutpair323"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[0]_i_1\ : label is "soft_lutpair345"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[2]_i_1\ : label is "soft_lutpair345"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[4]_i_3\ : label is "soft_lutpair288"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[4]_i_4\ : label is "soft_lutpair292"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[5]_i_2\ : label is "soft_lutpair330"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[6]_i_2\ : label is "soft_lutpair294"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[7]_i_1\ : label is "soft_lutpair289"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_2\ : label is "soft_lutpair289"; + attribute SOFT_HLUTNM of \stg1_wr_rd_cnt[8]_i_3\ : label is "soft_lutpair294"; + attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_1\ : label is "soft_lutpair365"; + attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row0_wr_done_i_2\ : label is "soft_lutpair295"; + attribute SOFT_HLUTNM of \wr_done_victim_rotate.complex_row1_wr_done_i_1\ : label is "soft_lutpair365"; + attribute SOFT_HLUTNM of \wr_en_inferred__0_i_1\ : label is "soft_lutpair390"; + attribute SOFT_HLUTNM of \wr_en_inferred__0_i_1__0\ : label is "soft_lutpair406"; + attribute SOFT_HLUTNM of \wr_en_inferred__0_i_1__1\ : label is "soft_lutpair406"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__3\ : label is "soft_lutpair389"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__4\ : label is "soft_lutpair389"; + attribute SOFT_HLUTNM of \wr_ptr[2]_i_1__5\ : label is "soft_lutpair390"; + attribute SOFT_HLUTNM of \wrcal_reads[0]_i_1\ : label is "soft_lutpair386"; + attribute SOFT_HLUTNM of \wrcal_reads[2]_i_1\ : label is "soft_lutpair326"; + attribute SOFT_HLUTNM of \wrcal_reads[3]_i_1\ : label is "soft_lutpair326"; + attribute SOFT_HLUTNM of \wrcal_reads[5]_i_1\ : label is "soft_lutpair386"; + attribute SOFT_HLUTNM of \wrcal_reads[6]_i_1\ : label is "soft_lutpair325"; + attribute SOFT_HLUTNM of \wrcal_reads[7]_i_3\ : label is "soft_lutpair325"; + attribute SOFT_HLUTNM of \wrcal_reads[7]_i_4\ : label is "soft_lutpair352"; + attribute SOFT_HLUTNM of \wrcal_reads[7]_i_5\ : label is "soft_lutpair376"; + attribute SOFT_HLUTNM of \wrcal_reads[7]_i_7\ : label is "soft_lutpair293"; + attribute SOFT_HLUTNM of \wrcal_reads[7]_i_9\ : label is "soft_lutpair355"; + attribute srl_bus_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg "; + attribute srl_name of \wrcal_start_dly_r_reg[4]_srl5\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 "; + attribute SOFT_HLUTNM of \wrcal_wr_cnt[0]_i_1\ : label is "soft_lutpair417"; + attribute SOFT_HLUTNM of \wrcal_wr_cnt[1]_i_1\ : label is "soft_lutpair417"; + attribute SOFT_HLUTNM of \wrcal_wr_cnt[3]_i_3\ : label is "soft_lutpair302"; + attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1\ : label is "soft_lutpair359"; + attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2\ : label is "soft_lutpair384"; + attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1\ : label is "soft_lutpair348"; + attribute srl_name of wrlvl_rank_done_r6_reg_srl5 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 "; +begin + calib_ctl_wren_reg_0 <= \^calib_ctl_wren_reg_0\; + \calib_seq_reg[1]_0\(10 downto 0) <= \^calib_seq_reg[1]_0\(10 downto 0); + calib_wrdata_en <= \^calib_wrdata_en\; + cnt_pwron_cke_done_r <= \^cnt_pwron_cke_done_r\; + ddr3_lm_done_r <= \^ddr3_lm_done_r\; + detect_pi_found_dqs <= \^detect_pi_found_dqs\; + first_rdlvl_pat_r <= \^first_rdlvl_pat_r\; + first_wrcal_pat_r <= \^first_wrcal_pat_r\; + \init_state_r_reg[2]_0\(0) <= \^init_state_r_reg[2]_0\(0); + mem_init_done_r <= \^mem_init_done_r\; + mpr_rdlvl_start_reg_0 <= \^mpr_rdlvl_start_reg_0\; + \one_rank.stg1_wr_done_reg_0\ <= \^one_rank.stg1_wr_done_reg_0\; + \out\ <= init_complete_r1_timing; + phy_read_calib <= \^phy_read_calib\; + phy_write_calib <= \^phy_write_calib\; + pi_calib_done <= \^pi_calib_done\; + pi_dqs_found_start_reg_0 <= \^pi_dqs_found_start_reg_0\; + prbs_rdlvl_done_pulse_reg_0 <= \^prbs_rdlvl_done_pulse_reg_0\; + prech_req_posedge_r_reg_0 <= \^prech_req_posedge_r_reg_0\; + rdlvl_stg1_done_r1_reg_0 <= \^rdlvl_stg1_done_r1_reg_0\; + rdlvl_stg1_start_reg_0 <= \^rdlvl_stg1_start_reg_0\; + wr_lvl_start_reg_0 <= \^wr_lvl_start_reg_0\; + wrcal_start_reg_0 <= \^wrcal_start_reg_0\; + wrlvl_done_r1 <= \^wrlvl_done_r1\; + wrlvl_final_if_rst <= \^wrlvl_final_if_rst\; +\back_to_back_reads_4_1.num_reads[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000066606766" + ) + port map ( + I0 => num_reads(0), + I1 => num_reads0, + I2 => prech_req_posedge_r_i_3_n_0, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\ + ); +\back_to_back_reads_4_1.num_reads[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => num_reads(0), + I1 => num_reads(2), + I2 => num_reads(1), + O => num_reads0 + ); +\back_to_back_reads_4_1.num_reads[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000CC320000" + ) + port map ( + I0 => pi_dqs_found_start_i_2_n_0, + I1 => num_reads(1), + I2 => num_reads(2), + I3 => num_reads(0), + I4 => \back_to_back_reads_4_1.num_reads[2]_i_2_n_0\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\ + ); +\back_to_back_reads_4_1.num_reads[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44004000" + ) + port map ( + I0 => \complex_wait_cnt_reg[3]_0\, + I1 => \back_to_back_reads_4_1.num_reads[2]_i_2_n_0\, + I2 => num_reads(0), + I3 => num_reads(2), + I4 => num_reads(1), + O => \back_to_back_reads_4_1.num_reads[2]_i_1_n_0\ + ); +\back_to_back_reads_4_1.num_reads[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFDFFFFFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[5]\, + I5 => prech_req_posedge_r_i_2_n_0, + O => \back_to_back_reads_4_1.num_reads[2]_i_2_n_0\ + ); +\back_to_back_reads_4_1.num_reads_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \back_to_back_reads_4_1.num_reads[0]_i_1_n_0\, + Q => num_reads(0), + R => '0' + ); +\back_to_back_reads_4_1.num_reads_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \back_to_back_reads_4_1.num_reads[1]_i_1_n_0\, + Q => num_reads(1), + R => '0' + ); +\back_to_back_reads_4_1.num_reads_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \back_to_back_reads_4_1.num_reads[2]_i_1_n_0\, + Q => num_reads(2), + R => '0' + ); +burst_addr_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000F0FE" + ) + port map ( + I0 => phy_wrdata_en, + I1 => \calib_cmd[2]_i_2_n_0\, + I2 => burst_addr_r_i_2_n_0, + I3 => p_15_in(3), + I4 => burst_addr_r_reg_0, + I5 => \complex_wait_cnt_reg[3]_0\, + O => burst_addr_r_i_1_n_0 + ); +burst_addr_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000020000C03F" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \wrcal_reads[7]_i_4_n_0\, + I5 => \init_state_r_reg_n_0_[4]\, + O => burst_addr_r_i_2_n_0 + ); +burst_addr_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => burst_addr_r_i_1_n_0, + Q => p_15_in(3), + R => '0' + ); +\calib_cke_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^cnt_pwron_cke_done_r\, + Q => calib_cke(3), + R => pi_dqs_found_done_r1_reg_0 + ); +\calib_cmd[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \calib_cmd[2]_i_2_n_0\, + I1 => phy_wrdata_en, + I2 => wr_level_dqs_asrt, + O => \calib_cmd[0]_i_1_n_0\ + ); +\calib_cmd[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \calib_cmd[2]_i_2_n_0\, + I1 => phy_wrdata_en, + I2 => wr_level_dqs_asrt, + O => \calib_cmd[1]_i_1_n_0\ + ); +\calib_cmd[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \calib_cmd[2]_i_2_n_0\, + I1 => phy_wrdata_en, + I2 => wr_level_dqs_asrt, + O => \calib_cmd[2]_i_1_n_0\ + ); +\calib_cmd[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF4445" + ) + port map ( + I0 => rdlvl_pi_incdec, + I1 => \calib_cmd[2]_i_3_n_0\, + I2 => mpr_rdlvl_start_i_2_n_0, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \calib_cmd[2]_i_4_n_0\, + I5 => wrcal_start_pre, + O => \calib_cmd[2]_i_2_n_0\ + ); +\calib_cmd[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000001000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => detect_pi_found_dqs_i_2_n_0, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[5]\, + O => \calib_cmd[2]_i_3_n_0\ + ); +\calib_cmd[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CDCCCDFCCDFCCDFC" + ) + port map ( + I0 => read_calib_i_2_n_0, + I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => complex_ocal_odt_ext_i_3_n_0, + I5 => prech_req_posedge_r_i_3_n_0, + O => \calib_cmd[2]_i_4_n_0\ + ); +\calib_cmd_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_cmd[0]_i_1_n_0\, + Q => calib_cmd(0), + R => '0' + ); +\calib_cmd_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_cmd[1]_i_1_n_0\, + Q => calib_cmd(1), + R => '0' + ); +\calib_cmd_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_cmd[2]_i_1_n_0\, + Q => calib_cmd(2), + R => '0' + ); +calib_ctl_wren_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^cnt_pwron_cke_done_r\, + I1 => Q(0), + O => p_116_in + ); +calib_ctl_wren_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_116_in, + Q => \^calib_ctl_wren_reg_0\, + R => pi_dqs_found_done_r1_reg_0 + ); +\calib_data_offset_0[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFEE" + ) + port map ( + I0 => phy_wrdata_en, + I1 => wr_level_dqs_asrt, + I2 => \calib_data_offset_0_reg[3]_0\, + I3 => \calib_cmd[2]_i_2_n_0\, + O => \calib_data_offset_0[3]_i_1_n_0\ + ); +\calib_data_offset_0[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FDFF" + ) + port map ( + I0 => \calib_cmd[2]_i_2_n_0\, + I1 => phy_wrdata_en, + I2 => wr_level_dqs_asrt, + I3 => \^pi_calib_done\, + O => \calib_data_offset_0[5]_i_1_n_0\ + ); +\calib_data_offset_0_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_data_offset_0_reg[0]_0\, + Q => calib_data_offset_0(0), + R => \calib_data_offset_0[5]_i_1_n_0\ + ); +\calib_data_offset_0_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_data_offset_0_reg[1]_0\, + Q => calib_data_offset_0(1), + R => \calib_data_offset_0[5]_i_1_n_0\ + ); +\calib_data_offset_0_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_data_offset_0_reg[2]_0\, + Q => calib_data_offset_0(2), + R => \calib_data_offset_0[5]_i_1_n_0\ + ); +\calib_data_offset_0_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_data_offset_0[3]_i_1_n_0\, + Q => calib_data_offset_0(3), + R => '0' + ); +\calib_data_offset_0_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_data_offset_0_reg[4]_0\, + Q => calib_data_offset_0(4), + R => \calib_data_offset_0[5]_i_1_n_0\ + ); +\calib_data_offset_0_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_data_offset_0_reg[5]_0\, + Q => calib_data_offset_0(5), + R => \calib_data_offset_0[5]_i_1_n_0\ + ); +\calib_odt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFE0000" + ) + port map ( + I0 => \calib_odt[0]_i_2_n_0\, + I1 => \calib_odt[0]_i_3_n_0\, + I2 => \complex_address[9]_i_2_n_0\, + I3 => phy_wrdata_en, + I4 => \gen_rnk[0].mr1_r_reg_n_0_[0][0]\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \calib_odt[0]_i_1_n_0\ + ); +\calib_odt[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000800F80F080FF" + ) + port map ( + I0 => wrlvl_odt, + I1 => \calib_odt[0]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => complex_ocal_odt_ext_i_3_n_0, + I5 => first_wrcal_pat_r_i_2_n_0, + O => \calib_odt[0]_i_2_n_0\ + ); +\calib_odt[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF8000" + ) + port map ( + I0 => ddr3_lm_done_r_i_2_n_0, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r[6]_i_3_n_0\, + I4 => complex_odt_ext, + I5 => complex_ocal_odt_ext, + O => \calib_odt[0]_i_3_n_0\ + ); +\calib_odt[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010000" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[2]\, + O => \calib_odt[0]_i_4_n_0\ + ); +\calib_odt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_odt[0]_i_1_n_0\, + Q => calib_odt(0), + R => '0' + ); +\calib_seq[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => Q(0), + I1 => \^cnt_pwron_cke_done_r\, + I2 => \^calib_seq_reg[1]_0\(9), + O => \calib_seq[0]_i_1_n_0\ + ); +\calib_seq[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^calib_seq_reg[1]_0\(9), + I1 => \^cnt_pwron_cke_done_r\, + I2 => Q(0), + I3 => \^calib_seq_reg[1]_0\(10), + O => \calib_seq[1]_i_1_n_0\ + ); +\calib_seq_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_seq[0]_i_1_n_0\, + Q => \^calib_seq_reg[1]_0\(9), + R => pi_dqs_found_done_r1_reg_0 + ); +\calib_seq_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \calib_seq[1]_i_1_n_0\, + Q => \^calib_seq_reg[1]_0\(10), + R => pi_dqs_found_done_r1_reg_0 + ); +calib_wrdata_en_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"EFEFEFFF" + ) + port map ( + I0 => p_0_in0_in, + I1 => \wrcal_wr_cnt[3]_i_2_n_0\, + I2 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => calib_wrdata_en_i_2_n_0, + O => phy_wrdata_en + ); +calib_wrdata_en_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFD" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \init_state_r_reg_n_0_[3]\, + O => calib_wrdata_en_i_2_n_0 + ); +calib_wrdata_en_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_wrdata_en, + Q => \^calib_wrdata_en\, + R => '0' + ); +cnt_cmd_done_m7_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0040000000000000" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[2]\, + I1 => \cnt_cmd_r_reg_n_0_[6]\, + I2 => \cnt_cmd_r_reg_n_0_[3]\, + I3 => cnt_cmd_done_m7_r_i_2_n_0, + I4 => \cnt_cmd_r_reg_n_0_[5]\, + I5 => \cnt_cmd_r_reg_n_0_[4]\, + O => cnt_cmd_done_m7_r_i_1_n_0 + ); +cnt_cmd_done_m7_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[1]\, + I1 => \cnt_cmd_r_reg_n_0_[0]\, + O => cnt_cmd_done_m7_r_i_2_n_0 + ); +cnt_cmd_done_m7_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_cmd_done_m7_r_i_1_n_0, + Q => cnt_cmd_done_m7_r, + R => '0' + ); +cnt_cmd_done_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[6]\, + I1 => \cnt_cmd_r[6]_i_4_n_0\, + O => cnt_cmd_done_r_i_1_n_0 + ); +cnt_cmd_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_cmd_done_r_i_1_n_0, + Q => cnt_cmd_done_r, + R => '0' + ); +\cnt_cmd_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[0]\, + O => \cnt_cmd_r[0]_i_1_n_0\ + ); +\cnt_cmd_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[0]\, + I1 => \cnt_cmd_r_reg_n_0_[1]\, + O => \cnt_cmd_r[1]_i_1_n_0\ + ); +\cnt_cmd_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[2]\, + I1 => \cnt_cmd_r_reg_n_0_[0]\, + I2 => \cnt_cmd_r_reg_n_0_[1]\, + O => \cnt_cmd_r[2]_i_1_n_0\ + ); +\cnt_cmd_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[3]\, + I1 => \cnt_cmd_r_reg_n_0_[2]\, + I2 => \cnt_cmd_r_reg_n_0_[1]\, + I3 => \cnt_cmd_r_reg_n_0_[0]\, + O => \cnt_cmd_r[3]_i_1_n_0\ + ); +\cnt_cmd_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[4]\, + I1 => \cnt_cmd_r_reg_n_0_[3]\, + I2 => \cnt_cmd_r_reg_n_0_[0]\, + I3 => \cnt_cmd_r_reg_n_0_[1]\, + I4 => \cnt_cmd_r_reg_n_0_[2]\, + O => \cnt_cmd_r[4]_i_1_n_0\ + ); +\cnt_cmd_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[5]\, + I1 => \cnt_cmd_r_reg_n_0_[2]\, + I2 => \cnt_cmd_r_reg_n_0_[1]\, + I3 => \cnt_cmd_r_reg_n_0_[0]\, + I4 => \cnt_cmd_r_reg_n_0_[3]\, + I5 => \cnt_cmd_r_reg_n_0_[4]\, + O => \cnt_cmd_r[5]_i_1_n_0\ + ); +\cnt_cmd_r[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => init_state_r(6), + I1 => \cnt_cmd_r[6]_i_3_n_0\, + O => \cnt_cmd_r[6]_i_1_n_0\ + ); +\cnt_cmd_r[6]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[6]\, + I1 => \cnt_cmd_r[6]_i_4_n_0\, + O => \cnt_cmd_r[6]_i_2_n_0\ + ); +\cnt_cmd_r[6]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEEE6EADF97919F" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[5]\, + O => \cnt_cmd_r[6]_i_3_n_0\ + ); +\cnt_cmd_r[6]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFFFFFFFFFF" + ) + port map ( + I0 => \cnt_cmd_r_reg_n_0_[4]\, + I1 => \cnt_cmd_r_reg_n_0_[5]\, + I2 => \cnt_cmd_r_reg_n_0_[3]\, + I3 => \cnt_cmd_r_reg_n_0_[0]\, + I4 => \cnt_cmd_r_reg_n_0_[1]\, + I5 => \cnt_cmd_r_reg_n_0_[2]\, + O => \cnt_cmd_r[6]_i_4_n_0\ + ); +\cnt_cmd_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_cmd_r[0]_i_1_n_0\, + Q => \cnt_cmd_r_reg_n_0_[0]\, + R => \cnt_cmd_r[6]_i_1_n_0\ + ); +\cnt_cmd_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_cmd_r[1]_i_1_n_0\, + Q => \cnt_cmd_r_reg_n_0_[1]\, + R => \cnt_cmd_r[6]_i_1_n_0\ + ); +\cnt_cmd_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_cmd_r[2]_i_1_n_0\, + Q => \cnt_cmd_r_reg_n_0_[2]\, + R => \cnt_cmd_r[6]_i_1_n_0\ + ); +\cnt_cmd_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_cmd_r[3]_i_1_n_0\, + Q => \cnt_cmd_r_reg_n_0_[3]\, + R => \cnt_cmd_r[6]_i_1_n_0\ + ); +\cnt_cmd_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_cmd_r[4]_i_1_n_0\, + Q => \cnt_cmd_r_reg_n_0_[4]\, + R => \cnt_cmd_r[6]_i_1_n_0\ + ); +\cnt_cmd_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_cmd_r[5]_i_1_n_0\, + Q => \cnt_cmd_r_reg_n_0_[5]\, + R => \cnt_cmd_r[6]_i_1_n_0\ + ); +\cnt_cmd_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_cmd_r[6]_i_2_n_0\, + Q => \cnt_cmd_r_reg_n_0_[6]\, + R => \cnt_cmd_r[6]_i_1_n_0\ + ); +cnt_dllk_zqinit_done_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"EAAA" + ) + port map ( + I0 => cnt_dllk_zqinit_done_r, + I1 => cnt_dllk_zqinit_r_reg(6), + I2 => mem_init_done_r_i_2_n_0, + I3 => cnt_dllk_zqinit_r_reg(7), + O => cnt_dllk_zqinit_done_r_i_1_n_0 + ); +cnt_dllk_zqinit_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_dllk_zqinit_done_r_i_1_n_0, + Q => cnt_dllk_zqinit_done_r, + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(0), + O => \p_0_in__3\(0) + ); +\cnt_dllk_zqinit_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(1), + I1 => cnt_dllk_zqinit_r_reg(0), + O => \p_0_in__3\(1) + ); +\cnt_dllk_zqinit_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(2), + I1 => cnt_dllk_zqinit_r_reg(0), + I2 => cnt_dllk_zqinit_r_reg(1), + O => \p_0_in__3\(2) + ); +\cnt_dllk_zqinit_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(3), + I1 => cnt_dllk_zqinit_r_reg(1), + I2 => cnt_dllk_zqinit_r_reg(0), + I3 => cnt_dllk_zqinit_r_reg(2), + O => \p_0_in__3\(3) + ); +\cnt_dllk_zqinit_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(4), + I1 => cnt_dllk_zqinit_r_reg(2), + I2 => cnt_dllk_zqinit_r_reg(0), + I3 => cnt_dllk_zqinit_r_reg(1), + I4 => cnt_dllk_zqinit_r_reg(3), + O => \p_0_in__3\(4) + ); +\cnt_dllk_zqinit_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(5), + I1 => cnt_dllk_zqinit_r_reg(3), + I2 => cnt_dllk_zqinit_r_reg(1), + I3 => cnt_dllk_zqinit_r_reg(0), + I4 => cnt_dllk_zqinit_r_reg(2), + I5 => cnt_dllk_zqinit_r_reg(4), + O => \p_0_in__3\(5) + ); +\cnt_dllk_zqinit_r[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(6), + I1 => mem_init_done_r_i_2_n_0, + O => \p_0_in__3\(6) + ); +\cnt_dllk_zqinit_r[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(7), + I1 => mem_init_done_r_i_2_n_0, + I2 => cnt_dllk_zqinit_r_reg(6), + O => \p_0_in__3\(7) + ); +\cnt_dllk_zqinit_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(0), + Q => cnt_dllk_zqinit_r_reg(0), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(1), + Q => cnt_dllk_zqinit_r_reg(1), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(2), + Q => cnt_dllk_zqinit_r_reg(2), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(3), + Q => cnt_dllk_zqinit_r_reg(3), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(4), + Q => cnt_dllk_zqinit_r_reg(4), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(5), + Q => cnt_dllk_zqinit_r_reg(5), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(6), + Q => cnt_dllk_zqinit_r_reg(6), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +\cnt_dllk_zqinit_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__3\(7), + Q => cnt_dllk_zqinit_r_reg(7), + R => \cnt_dllk_zqinit_r[7]_i_1_n_0\ + ); +cnt_init_af_done_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E222" + ) + port map ( + I0 => cnt_init_af_done_r, + I1 => cnt_init_mr_r1, + I2 => cnt_init_af_r(1), + I3 => cnt_init_af_r(0), + I4 => ddr2_pre_flag_r, + O => cnt_init_af_done_r_i_1_n_0 + ); +cnt_init_af_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_init_af_done_r_i_1_n_0, + Q => cnt_init_af_done_r, + R => '0' + ); +\cnt_init_af_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => cnt_init_af_r(0), + I1 => cnt_init_mr_r1, + I2 => ddr2_pre_flag_r, + O => \cnt_init_af_r[0]_i_1_n_0\ + ); +\cnt_init_af_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"006A" + ) + port map ( + I0 => cnt_init_af_r(1), + I1 => cnt_init_mr_r1, + I2 => cnt_init_af_r(0), + I3 => ddr2_pre_flag_r, + O => \cnt_init_af_r[1]_i_1_n_0\ + ); +\cnt_init_af_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_init_af_r[0]_i_1_n_0\, + Q => cnt_init_af_r(0), + R => '0' + ); +\cnt_init_af_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_init_af_r[1]_i_1_n_0\, + Q => cnt_init_af_r(1), + R => '0' + ); +cnt_init_mr_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000E222" + ) + port map ( + I0 => cnt_init_mr_done_r, + I1 => temp_lmr_done, + I2 => cnt_init_mr_r(0), + I3 => cnt_init_mr_r(1), + I4 => ddr2_pre_flag_r, + I5 => cnt_init_mr_r1, + O => cnt_init_mr_done_r_i_1_n_0 + ); +cnt_init_mr_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_init_mr_done_r_i_1_n_0, + Q => cnt_init_mr_done_r, + R => '0' + ); +\cnt_init_mr_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAAA6A2" + ) + port map ( + I0 => cnt_init_mr_r(0), + I1 => \cnt_init_mr_r[0]_i_2_n_0\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => cnt_init_mr_r1, + O => \cnt_init_mr_r[0]_i_1_n_0\ + ); +\cnt_init_mr_r[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => init_state_r(6), + I3 => \init_state_r_reg_n_0_[4]\, + O => \cnt_init_mr_r[0]_i_2_n_0\ + ); +\cnt_init_mr_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000006A" + ) + port map ( + I0 => cnt_init_mr_r(1), + I1 => temp_lmr_done, + I2 => cnt_init_mr_r(0), + I3 => ddr2_pre_flag_r, + I4 => cnt_init_mr_r1, + O => \cnt_init_mr_r[1]_i_1_n_0\ + ); +\cnt_init_mr_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => detect_pi_found_dqs_i_2_n_0, + O => temp_lmr_done + ); +\cnt_init_mr_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000800" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => detect_pi_found_dqs_i_3_n_0, + I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \^mem_init_done_r\, + O => cnt_init_mr_r1 + ); +\cnt_init_mr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_init_mr_r[0]_i_1_n_0\, + Q => cnt_init_mr_r(0), + R => '0' + ); +\cnt_init_mr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cnt_init_mr_r[1]_i_1_n_0\, + Q => cnt_init_mr_r(1), + R => '0' + ); +\cnt_pwron_ce_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(0), + O => \p_0_in__0\(0) + ); +\cnt_pwron_ce_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(1), + I1 => cnt_pwron_ce_r_reg(0), + O => \p_0_in__0\(1) + ); +\cnt_pwron_ce_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(2), + I1 => cnt_pwron_ce_r_reg(0), + I2 => cnt_pwron_ce_r_reg(1), + O => \p_0_in__0\(2) + ); +\cnt_pwron_ce_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(3), + I1 => cnt_pwron_ce_r_reg(1), + I2 => cnt_pwron_ce_r_reg(0), + I3 => cnt_pwron_ce_r_reg(2), + O => \p_0_in__0\(3) + ); +\cnt_pwron_ce_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(4), + I1 => cnt_pwron_ce_r_reg(2), + I2 => cnt_pwron_ce_r_reg(0), + I3 => cnt_pwron_ce_r_reg(1), + I4 => cnt_pwron_ce_r_reg(3), + O => \p_0_in__0\(4) + ); +\cnt_pwron_ce_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(5), + I1 => cnt_pwron_ce_r_reg(3), + I2 => cnt_pwron_ce_r_reg(1), + I3 => cnt_pwron_ce_r_reg(0), + I4 => cnt_pwron_ce_r_reg(2), + I5 => cnt_pwron_ce_r_reg(4), + O => \p_0_in__0\(5) + ); +\cnt_pwron_ce_r[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(6), + I1 => pwron_ce_r_i_2_n_0, + O => \p_0_in__0\(6) + ); +\cnt_pwron_ce_r[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(7), + I1 => pwron_ce_r_i_2_n_0, + I2 => cnt_pwron_ce_r_reg(6), + O => \p_0_in__0\(7) + ); +\cnt_pwron_ce_r[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(8), + I1 => cnt_pwron_ce_r_reg(6), + I2 => pwron_ce_r_i_2_n_0, + I3 => cnt_pwron_ce_r_reg(7), + O => \p_0_in__0\(8) + ); +\cnt_pwron_ce_r[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(9), + I1 => cnt_pwron_ce_r_reg(7), + I2 => pwron_ce_r_i_2_n_0, + I3 => cnt_pwron_ce_r_reg(6), + I4 => cnt_pwron_ce_r_reg(8), + O => \p_0_in__0\(9) + ); +\cnt_pwron_ce_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(0), + Q => cnt_pwron_ce_r_reg(0), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(1), + Q => cnt_pwron_ce_r_reg(1), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(2), + Q => cnt_pwron_ce_r_reg(2), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(3), + Q => cnt_pwron_ce_r_reg(3), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(4), + Q => cnt_pwron_ce_r_reg(4), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(5), + Q => cnt_pwron_ce_r_reg(5), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(6), + Q => cnt_pwron_ce_r_reg(6), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(7), + Q => cnt_pwron_ce_r_reg(7), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_ce_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(8), + Q => cnt_pwron_ce_r_reg(8), + R => \cnt_pwron_ce_r_reg[9]_0\(1) + ); +\cnt_pwron_ce_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(9), + Q => cnt_pwron_ce_r_reg(9), + R => \cnt_pwron_ce_r_reg[9]_0\(1) + ); +cnt_pwron_cke_done_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000F200" + ) + port map ( + I0 => cnt_pwron_cke_done_r_i_2_n_0, + I1 => cnt_pwron_cke_done_r_i_3_n_0, + I2 => \^cnt_pwron_cke_done_r\, + I3 => Q(0), + I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => cnt_pwron_cke_done_r_i_1_n_0 + ); +cnt_pwron_cke_done_r_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => cnt_pwron_r_reg(6), + I1 => cnt_pwron_r_reg(7), + I2 => cnt_pwron_r_reg(8), + O => cnt_pwron_cke_done_r_i_2_n_0 + ); +cnt_pwron_cke_done_r_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"DFFFFFFFFFFFFFFF" + ) + port map ( + I0 => cnt_pwron_r_reg(4), + I1 => cnt_pwron_r_reg(2), + I2 => cnt_pwron_r_reg(3), + I3 => cnt_pwron_r_reg(5), + I4 => cnt_pwron_r_reg(1), + I5 => cnt_pwron_r_reg(0), + O => cnt_pwron_cke_done_r_i_3_n_0 + ); +cnt_pwron_cke_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_pwron_cke_done_r_i_1_n_0, + Q => \^cnt_pwron_cke_done_r\, + R => '0' + ); +\cnt_pwron_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cnt_pwron_r_reg(0), + O => \p_0_in__0__0\(0) + ); +\cnt_pwron_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_pwron_r_reg(1), + I1 => cnt_pwron_r_reg(0), + O => \p_0_in__0__0\(1) + ); +\cnt_pwron_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_pwron_r_reg(2), + I1 => cnt_pwron_r_reg(0), + I2 => cnt_pwron_r_reg(1), + O => \p_0_in__0__0\(2) + ); +\cnt_pwron_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cnt_pwron_r_reg(3), + I1 => cnt_pwron_r_reg(1), + I2 => cnt_pwron_r_reg(0), + I3 => cnt_pwron_r_reg(2), + O => \p_0_in__0__0\(3) + ); +\cnt_pwron_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => cnt_pwron_r_reg(4), + I1 => cnt_pwron_r_reg(2), + I2 => cnt_pwron_r_reg(0), + I3 => cnt_pwron_r_reg(1), + I4 => cnt_pwron_r_reg(3), + O => \p_0_in__0__0\(4) + ); +\cnt_pwron_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => cnt_pwron_r_reg(5), + I1 => cnt_pwron_r_reg(3), + I2 => cnt_pwron_r_reg(1), + I3 => cnt_pwron_r_reg(0), + I4 => cnt_pwron_r_reg(2), + I5 => cnt_pwron_r_reg(4), + O => \p_0_in__0__0\(5) + ); +\cnt_pwron_r[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => cnt_pwron_r_reg(6), + I1 => cnt_pwron_r_reg(4), + I2 => cnt_pwron_r_reg(2), + I3 => \cnt_pwron_r[6]_i_2_n_0\, + I4 => cnt_pwron_r_reg(3), + I5 => cnt_pwron_r_reg(5), + O => \p_0_in__0__0\(6) + ); +\cnt_pwron_r[6]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => cnt_pwron_r_reg(1), + I1 => cnt_pwron_r_reg(0), + O => \cnt_pwron_r[6]_i_2_n_0\ + ); +\cnt_pwron_r[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_pwron_r_reg(7), + I1 => \cnt_pwron_r[8]_i_2_n_0\, + I2 => cnt_pwron_r_reg(6), + O => \p_0_in__0__0\(7) + ); +\cnt_pwron_r[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cnt_pwron_r_reg(8), + I1 => cnt_pwron_r_reg(6), + I2 => \cnt_pwron_r[8]_i_2_n_0\, + I3 => cnt_pwron_r_reg(7), + O => \p_0_in__0__0\(8) + ); +\cnt_pwron_r[8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => cnt_pwron_r_reg(5), + I1 => cnt_pwron_r_reg(3), + I2 => cnt_pwron_r_reg(1), + I3 => cnt_pwron_r_reg(0), + I4 => cnt_pwron_r_reg(2), + I5 => cnt_pwron_r_reg(4), + O => \cnt_pwron_r[8]_i_2_n_0\ + ); +\cnt_pwron_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(0), + Q => cnt_pwron_r_reg(0), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(1), + Q => cnt_pwron_r_reg(1), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(2), + Q => cnt_pwron_r_reg(2), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(3), + Q => cnt_pwron_r_reg(3), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(4), + Q => cnt_pwron_r_reg(4), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(5), + Q => cnt_pwron_r_reg(5), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(6), + Q => cnt_pwron_r_reg(6), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(7), + Q => cnt_pwron_r_reg(7), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +\cnt_pwron_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pwron_ce_r, + D => \p_0_in__0__0\(8), + Q => cnt_pwron_r_reg(8), + R => \cnt_pwron_ce_r_reg[9]_0\(0) + ); +cnt_pwron_reset_done_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000F200" + ) + port map ( + I0 => cnt_pwron_cke_done_r_i_2_n_0, + I1 => cnt_pwron_reset_done_r_i_2_n_0, + I2 => cnt_pwron_reset_done_r, + I3 => Q(0), + I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => cnt_pwron_reset_done_r_i_1_n_0 + ); +cnt_pwron_reset_done_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFDFFFFFFFF" + ) + port map ( + I0 => cnt_pwron_r_reg(0), + I1 => cnt_pwron_r_reg(1), + I2 => cnt_pwron_r_reg(3), + I3 => cnt_pwron_r_reg(5), + I4 => cnt_pwron_r_reg(2), + I5 => cnt_pwron_r_reg(4), + O => cnt_pwron_reset_done_r_i_2_n_0 + ); +cnt_pwron_reset_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_pwron_reset_done_r_i_1_n_0, + Q => cnt_pwron_reset_done_r, + R => '0' + ); +cnt_txpr_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAAB" + ) + port map ( + I0 => cnt_txpr_done_r, + I1 => cnt_txpr_done_r_i_2_n_0, + I2 => cnt_txpr_r_reg(7), + I3 => cnt_txpr_r_reg(2), + I4 => cnt_txpr_r_reg(6), + I5 => cnt_txpr_r_reg(3), + O => cnt_txpr_done_r_i_1_n_0 + ); +cnt_txpr_done_r_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => cnt_txpr_r_reg(0), + I1 => cnt_txpr_r_reg(1), + I2 => cnt_txpr_r_reg(5), + I3 => cnt_txpr_r_reg(4), + O => cnt_txpr_done_r_i_2_n_0 + ); +cnt_txpr_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cnt_txpr_done_r_i_1_n_0, + Q => cnt_txpr_done_r, + R => clear + ); +\cnt_txpr_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cnt_txpr_r_reg(0), + O => \p_0_in__1\(0) + ); +\cnt_txpr_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_txpr_r_reg(1), + I1 => cnt_txpr_r_reg(0), + O => \p_0_in__1\(1) + ); +\cnt_txpr_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_txpr_r_reg(2), + I1 => cnt_txpr_r_reg(0), + I2 => cnt_txpr_r_reg(1), + O => \p_0_in__1\(2) + ); +\cnt_txpr_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cnt_txpr_r_reg(3), + I1 => cnt_txpr_r_reg(1), + I2 => cnt_txpr_r_reg(0), + I3 => cnt_txpr_r_reg(2), + O => \p_0_in__1\(3) + ); +\cnt_txpr_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => cnt_txpr_r_reg(4), + I1 => cnt_txpr_r_reg(2), + I2 => cnt_txpr_r_reg(0), + I3 => cnt_txpr_r_reg(1), + I4 => cnt_txpr_r_reg(3), + O => \p_0_in__1\(4) + ); +\cnt_txpr_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => cnt_txpr_r_reg(5), + I1 => cnt_txpr_r_reg(3), + I2 => cnt_txpr_r_reg(1), + I3 => cnt_txpr_r_reg(0), + I4 => cnt_txpr_r_reg(2), + I5 => cnt_txpr_r_reg(4), + O => \p_0_in__1\(5) + ); +\cnt_txpr_r[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_txpr_r_reg(6), + I1 => \cnt_txpr_r[7]_i_3_n_0\, + O => \p_0_in__1\(6) + ); +\cnt_txpr_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^cnt_pwron_cke_done_r\, + O => clear + ); +\cnt_txpr_r[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_txpr_r_reg(7), + I1 => \cnt_txpr_r[7]_i_3_n_0\, + I2 => cnt_txpr_r_reg(6), + O => \p_0_in__1\(7) + ); +\cnt_txpr_r[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => cnt_txpr_r_reg(5), + I1 => cnt_txpr_r_reg(3), + I2 => cnt_txpr_r_reg(1), + I3 => cnt_txpr_r_reg(0), + I4 => cnt_txpr_r_reg(2), + I5 => cnt_txpr_r_reg(4), + O => \cnt_txpr_r[7]_i_3_n_0\ + ); +\cnt_txpr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(0), + Q => cnt_txpr_r_reg(0), + R => clear + ); +\cnt_txpr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(1), + Q => cnt_txpr_r_reg(1), + R => clear + ); +\cnt_txpr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(2), + Q => cnt_txpr_r_reg(2), + R => clear + ); +\cnt_txpr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(3), + Q => cnt_txpr_r_reg(3), + R => clear + ); +\cnt_txpr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(4), + Q => cnt_txpr_r_reg(4), + R => clear + ); +\cnt_txpr_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(5), + Q => cnt_txpr_r_reg(5), + R => clear + ); +\cnt_txpr_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(6), + Q => cnt_txpr_r_reg(6), + R => clear + ); +\cnt_txpr_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__1\(7), + Q => cnt_txpr_r_reg(7), + R => clear + ); +\complex_address[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFFFF8AAAAAAA" + ) + port map ( + I0 => \complex_address[9]_i_2_n_0\, + I1 => \complex_address[9]_i_3_n_0\, + I2 => init_state_r1(2), + I3 => init_state_r1(0), + I4 => init_state_r1(5), + I5 => \complex_address[9]_i_4_n_0\, + O => complex_address0 + ); +\complex_address[9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000020000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r[6]_i_4_n_0\, + O => \complex_address[9]_i_2_n_0\ + ); +\complex_address[9]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFBF" + ) + port map ( + I0 => init_state_r1(1), + I1 => init_state_r1(4), + I2 => init_state_r1(3), + I3 => init_state_r1(6), + O => \complex_address[9]_i_3_n_0\ + ); +\complex_address[9]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000002000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r[6]_i_4_n_0\, + O => \complex_address[9]_i_4_n_0\ + ); +\complex_address_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + Q => \complex_address_reg_n_0_[0]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + Q => \complex_address_reg_n_0_[1]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + Q => \complex_address_reg_n_0_[2]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + Q => \complex_address_reg_n_0_[3]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + Q => \complex_address_reg_n_0_[4]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + Q => \complex_address_reg_n_0_[5]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + Q => \complex_address_reg_n_0_[6]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + Q => \complex_address_reg_n_0_[7]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + Q => \complex_address_reg_n_0_[8]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\complex_address_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_address0, + D => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + Q => \complex_address_reg_n_0_[9]\, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +complex_byte_rd_done_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"02020200" + ) + port map ( + I0 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + I1 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I2 => \^prbs_rdlvl_done_pulse_reg_0\, + I3 => complex_byte_rd_done_i_2_n_0, + I4 => complex_byte_rd_done, + O => complex_byte_rd_done_i_1_n_0 + ); +complex_byte_rd_done_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000800000000000" + ) + port map ( + I0 => complex_row1_rd_cnt(1), + I1 => complex_row1_rd_cnt(0), + I2 => complex_row1_rd_cnt(2), + I3 => complex_row1_rd_done, + I4 => complex_row1_rd_done_r1, + I5 => D(3), + O => complex_byte_rd_done_i_2_n_0 + ); +complex_byte_rd_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_byte_rd_done_i_1_n_0, + Q => complex_byte_rd_done, + R => '0' + ); +\complex_num_reads[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF26EE" + ) + port map ( + I0 => \complex_num_reads_reg_n_0_[0]\, + I1 => \complex_num_reads[3]_i_2_n_0\, + I2 => \complex_num_writes[4]_i_6_n_0\, + I3 => \complex_num_reads[2]_i_5_n_0\, + I4 => \complex_num_reads[3]_i_4_n_0\, + O => \complex_num_reads[0]_i_1_n_0\ + ); +\complex_num_reads[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000222FE22" + ) + port map ( + I0 => \complex_num_reads_reg_n_0_[1]\, + I1 => \complex_num_reads[2]_i_2_n_0\, + I2 => \complex_num_reads[1]_i_2_n_0\, + I3 => \complex_num_reads[2]_i_5_n_0\, + I4 => \complex_num_reads[1]_i_3_n_0\, + I5 => \complex_num_reads[1]_i_4_n_0\, + O => \complex_num_reads[1]_i_1_n_0\ + ); +\complex_num_reads[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0800000000000000" + ) + port map ( + I0 => \complex_num_reads[1]_i_5_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + O => \complex_num_reads[1]_i_2_n_0\ + ); +\complex_num_reads[1]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A88A" + ) + port map ( + I0 => \complex_num_writes[4]_i_7_n_0\, + I1 => \complex_num_writes[4]_i_6_n_0\, + I2 => \complex_num_reads_reg_n_0_[1]\, + I3 => \complex_num_reads_reg_n_0_[0]\, + O => \complex_num_reads[1]_i_3_n_0\ + ); +\complex_num_reads[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEAAAAAAAAAAA" + ) + port map ( + I0 => \complex_wait_cnt_reg[3]_0\, + I1 => \complex_num_writes[4]_i_12_n_0\, + I2 => \complex_num_reads_reg_n_0_[2]\, + I3 => \complex_num_reads_reg_n_0_[1]\, + I4 => \complex_num_reads_reg_n_0_[3]\, + I5 => \complex_num_reads[2]_i_5_n_0\, + O => \complex_num_reads[1]_i_4_n_0\ + ); +\complex_num_reads[1]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + O => \complex_num_reads[1]_i_5_n_0\ + ); +\complex_num_reads[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000006EAE2222" + ) + port map ( + I0 => \complex_num_reads_reg_n_0_[2]\, + I1 => \complex_num_reads[2]_i_2_n_0\, + I2 => \complex_num_reads[2]_i_3_n_0\, + I3 => \complex_num_reads[2]_i_4_n_0\, + I4 => \complex_num_reads[2]_i_5_n_0\, + I5 => \complex_num_reads[2]_i_6_n_0\, + O => \complex_num_reads[2]_i_1_n_0\ + ); +\complex_num_reads[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => \complex_num_reads[2]_i_5_n_0\, + I1 => \complex_num_reads[3]_i_7_n_0\, + I2 => \complex_num_reads[3]_i_2_n_0\, + O => \complex_num_reads[2]_i_2_n_0\ + ); +\complex_num_reads[2]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \complex_num_reads[3]_i_7_n_0\, + I1 => \complex_num_writes[4]_i_6_n_0\, + O => \complex_num_reads[2]_i_3_n_0\ + ); +\complex_num_reads[2]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \complex_num_reads_reg_n_0_[1]\, + I1 => \complex_num_reads_reg_n_0_[0]\, + O => \complex_num_reads[2]_i_4_n_0\ + ); +\complex_num_reads[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000008000" + ) + port map ( + I0 => \complex_address[9]_i_4_n_0\, + I1 => complex_wait_cnt_reg(2), + I2 => complex_wait_cnt_reg(3), + I3 => complex_wait_cnt_reg(1), + I4 => complex_wait_cnt_reg(0), + I5 => complex_row0_rd_done, + O => \complex_num_reads[2]_i_5_n_0\ + ); +\complex_num_reads[2]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \complex_num_reads[1]_i_4_n_0\, + I1 => \complex_num_reads[2]_i_5_n_0\, + I2 => \complex_num_reads[1]_i_2_n_0\, + O => \complex_num_reads[2]_i_6_n_0\ + ); +\complex_num_reads[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => \complex_num_reads_reg_n_0_[3]\, + I1 => \complex_num_reads[3]_i_2_n_0\, + I2 => \complex_num_reads[3]_i_3_n_0\, + I3 => \complex_num_reads[3]_i_4_n_0\, + O => \complex_num_reads[3]_i_1_n_0\ + ); +\complex_num_reads[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F70" + ) + port map ( + I0 => \complex_num_reads[3]_i_5_n_0\, + I1 => \complex_num_reads[3]_i_6_n_0\, + I2 => \complex_num_reads[2]_i_5_n_0\, + I3 => \complex_num_reads_dec[3]_i_4_n_0\, + O => \complex_num_reads[3]_i_2_n_0\ + ); +\complex_num_reads[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8AA8A8A8A8A8A8A8" + ) + port map ( + I0 => \complex_num_reads[2]_i_5_n_0\, + I1 => \complex_num_writes[4]_i_6_n_0\, + I2 => \complex_num_reads_reg_n_0_[3]\, + I3 => \complex_num_reads_reg_n_0_[1]\, + I4 => \complex_num_reads_reg_n_0_[0]\, + I5 => \complex_num_reads_reg_n_0_[2]\, + O => \complex_num_reads[3]_i_3_n_0\ + ); +\complex_num_reads[3]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FCEC" + ) + port map ( + I0 => \complex_num_reads[1]_i_2_n_0\, + I1 => \complex_num_reads[1]_i_4_n_0\, + I2 => \complex_num_reads[2]_i_5_n_0\, + I3 => \complex_num_reads[3]_i_7_n_0\, + O => \complex_num_reads[3]_i_4_n_0\ + ); +\complex_num_reads[3]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBBABAAA" + ) + port map ( + I0 => \complex_num_writes[4]_i_15_n_0\, + I1 => \complex_num_writes[4]_i_6_n_0\, + I2 => \complex_num_reads_reg_n_0_[1]\, + I3 => \complex_num_reads_reg_n_0_[2]\, + I4 => \complex_num_writes[4]_i_14_n_0\, + O => \complex_num_reads[3]_i_5_n_0\ + ); +\complex_num_reads[3]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5554444444444444" + ) + port map ( + I0 => \complex_num_writes[4]_i_12_n_0\, + I1 => \complex_num_reads_reg_n_0_[3]\, + I2 => \complex_num_reads_reg_n_0_[1]\, + I3 => \complex_num_reads_reg_n_0_[0]\, + I4 => \complex_num_reads_reg_n_0_[2]\, + I5 => \complex_num_writes[4]_i_15_n_0\, + O => \complex_num_reads[3]_i_6_n_0\ + ); +\complex_num_reads[3]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000800000" + ) + port map ( + I0 => \complex_num_reads[3]_i_8_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + O => \complex_num_reads[3]_i_7_n_0\ + ); +\complex_num_reads[3]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + O => \complex_num_reads[3]_i_8_n_0\ + ); +\complex_num_reads_dec[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"74" + ) + port map ( + I0 => complex_num_reads_dec(0), + I1 => \complex_num_reads_dec[3]_i_3_n_0\, + I2 => \complex_num_reads_reg_n_0_[0]\, + O => \complex_num_reads_dec[0]_i_1_n_0\ + ); +\complex_num_reads_dec[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9F90" + ) + port map ( + I0 => complex_num_reads_dec(1), + I1 => complex_num_reads_dec(0), + I2 => \complex_num_reads_dec[3]_i_3_n_0\, + I3 => \complex_num_reads_reg_n_0_[1]\, + O => \complex_num_reads_dec[1]_i_1_n_0\ + ); +\complex_num_reads_dec[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A9FFA900" + ) + port map ( + I0 => complex_num_reads_dec(2), + I1 => complex_num_reads_dec(0), + I2 => complex_num_reads_dec(1), + I3 => \complex_num_reads_dec[3]_i_3_n_0\, + I4 => \complex_num_reads_reg_n_0_[2]\, + O => \complex_num_reads_dec[2]_i_1_n_0\ + ); +\complex_num_reads_dec[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDDDDDDDDDD5" + ) + port map ( + I0 => \complex_num_reads_dec[3]_i_3_n_0\, + I1 => \stg1_wr_rd_cnt[8]_i_4_n_0\, + I2 => complex_num_reads_dec(0), + I3 => complex_num_reads_dec(1), + I4 => complex_num_reads_dec(3), + I5 => complex_num_reads_dec(2), + O => \complex_num_reads_dec[3]_i_1_n_0\ + ); +\complex_num_reads_dec[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAA9FFFFAAA90000" + ) + port map ( + I0 => complex_num_reads_dec(3), + I1 => complex_num_reads_dec(2), + I2 => complex_num_reads_dec(1), + I3 => complex_num_reads_dec(0), + I4 => \complex_num_reads_dec[3]_i_3_n_0\, + I5 => \complex_num_reads_reg_n_0_[3]\, + O => \complex_num_reads_dec[3]_i_2_n_0\ + ); +\complex_num_reads_dec[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5455" + ) + port map ( + I0 => \complex_num_reads_dec[3]_i_4_n_0\, + I1 => complex_row0_rd_done, + I2 => \init_state_r[1]_i_22_n_0\, + I3 => \complex_address[9]_i_4_n_0\, + O => \complex_num_reads_dec[3]_i_3_n_0\ + ); +\complex_num_reads_dec[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000020000080" + ) + port map ( + I0 => ddr3_lm_done_r_i_2_n_0, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => init_state_r(6), + O => \complex_num_reads_dec[3]_i_4_n_0\ + ); +\complex_num_reads_dec_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \complex_num_reads_dec[3]_i_1_n_0\, + D => \complex_num_reads_dec[0]_i_1_n_0\, + Q => complex_num_reads_dec(0), + S => pi_dqs_found_done_r1_reg_0 + ); +\complex_num_reads_dec_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \complex_num_reads_dec[3]_i_1_n_0\, + D => \complex_num_reads_dec[1]_i_1_n_0\, + Q => complex_num_reads_dec(1), + R => pi_dqs_found_done_r1_reg_0 + ); +\complex_num_reads_dec_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \complex_num_reads_dec[3]_i_1_n_0\, + D => \complex_num_reads_dec[2]_i_1_n_0\, + Q => complex_num_reads_dec(2), + R => pi_dqs_found_done_r1_reg_0 + ); +\complex_num_reads_dec_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \complex_num_reads_dec[3]_i_1_n_0\, + D => \complex_num_reads_dec[3]_i_2_n_0\, + Q => complex_num_reads_dec(3), + R => pi_dqs_found_done_r1_reg_0 + ); +\complex_num_reads_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_reads[0]_i_1_n_0\, + Q => \complex_num_reads_reg_n_0_[0]\, + R => '0' + ); +\complex_num_reads_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_reads[1]_i_1_n_0\, + Q => \complex_num_reads_reg_n_0_[1]\, + R => '0' + ); +\complex_num_reads_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_reads[2]_i_1_n_0\, + Q => \complex_num_reads_reg_n_0_[2]\, + R => '0' + ); +\complex_num_reads_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_reads[3]_i_1_n_0\, + Q => \complex_num_reads_reg_n_0_[3]\, + R => '0' + ); +\complex_num_writes[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"222E662EFFFFFFFF" + ) + port map ( + I0 => \complex_num_writes_reg_n_0_[0]\, + I1 => \complex_num_writes[3]_i_2_n_0\, + I2 => \complex_num_writes[3]_i_4_n_0\, + I3 => \complex_num_writes[4]_i_5_n_0\, + I4 => \complex_num_writes[4]_i_6_n_0\, + I5 => \complex_num_writes[4]_i_2_n_0\, + O => \complex_num_writes[0]_i_1_n_0\ + ); +\complex_num_writes[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FE020000" + ) + port map ( + I0 => \complex_num_writes_reg_n_0_[1]\, + I1 => \complex_num_writes[2]_i_4_n_0\, + I2 => \complex_num_writes[2]_i_5_n_0\, + I3 => \complex_num_writes[1]_i_2_n_0\, + I4 => \complex_num_writes[2]_i_2_n_0\, + O => \complex_num_writes[1]_i_1_n_0\ + ); +\complex_num_writes[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF22222AA2" + ) + port map ( + I0 => \complex_num_writes[4]_i_5_n_0\, + I1 => \complex_num_writes[4]_i_7_n_0\, + I2 => \complex_num_writes_reg_n_0_[1]\, + I3 => \complex_num_writes_reg_n_0_[0]\, + I4 => \complex_num_writes[4]_i_6_n_0\, + I5 => \complex_num_writes[3]_i_4_n_0\, + O => \complex_num_writes[1]_i_2_n_0\ + ); +\complex_num_writes[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008A80" + ) + port map ( + I0 => \complex_num_writes[2]_i_2_n_0\, + I1 => \complex_num_writes[2]_i_3_n_0\, + I2 => \complex_num_writes[2]_i_4_n_0\, + I3 => \complex_num_writes_reg_n_0_[2]\, + I4 => \complex_num_writes[2]_i_5_n_0\, + O => \complex_num_writes[2]_i_1_n_0\ + ); +\complex_num_writes[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"222A2A2AAAAAAAAA" + ) + port map ( + I0 => complex_row0_rd_done_reg_0, + I1 => \complex_num_writes[4]_i_12_n_0\, + I2 => \complex_num_writes[2]_i_6_n_0\, + I3 => \complex_num_writes_reg_n_0_[2]\, + I4 => \complex_num_writes_reg_n_0_[1]\, + I5 => \complex_num_writes[4]_i_5_n_0\, + O => \complex_num_writes[2]_i_2_n_0\ + ); +\complex_num_writes[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CEEEECCCEEEEEEEE" + ) + port map ( + I0 => \complex_num_writes[4]_i_5_n_0\, + I1 => \complex_num_writes[3]_i_4_n_0\, + I2 => \complex_num_writes_reg_n_0_[1]\, + I3 => \complex_num_writes_reg_n_0_[0]\, + I4 => \complex_num_writes_reg_n_0_[2]\, + I5 => \complex_num_reads[2]_i_3_n_0\, + O => \complex_num_writes[2]_i_3_n_0\ + ); +\complex_num_writes[2]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => \complex_num_reads[2]_i_3_n_0\, + I1 => \complex_num_writes[4]_i_5_n_0\, + I2 => \complex_num_writes[4]_i_4_n_0\, + O => \complex_num_writes[2]_i_4_n_0\ + ); +\complex_num_writes[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000002000000000" + ) + port map ( + I0 => \complex_num_writes[4]_i_5_n_0\, + I1 => \complex_num_writes[2]_i_7_n_0\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I5 => \complex_num_writes[2]_i_8_n_0\, + O => \complex_num_writes[2]_i_5_n_0\ + ); +\complex_num_writes[2]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \complex_num_writes_reg_n_0_[4]\, + I1 => \complex_num_writes_reg_n_0_[3]\, + O => \complex_num_writes[2]_i_6_n_0\ + ); +\complex_num_writes[2]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + O => \complex_num_writes[2]_i_7_n_0\ + ); +\complex_num_writes[2]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + O => \complex_num_writes[2]_i_8_n_0\ + ); +\complex_num_writes[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EE2EEE2200000000" + ) + port map ( + I0 => \complex_num_writes_reg_n_0_[3]\, + I1 => \complex_num_writes[3]_i_2_n_0\, + I2 => \complex_num_writes[3]_i_3_n_0\, + I3 => \complex_num_writes[3]_i_4_n_0\, + I4 => \complex_num_writes[4]_i_5_n_0\, + I5 => \complex_num_writes[4]_i_2_n_0\, + O => \complex_num_writes[3]_i_1_n_0\ + ); +\complex_num_writes[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F8" + ) + port map ( + I0 => \complex_num_writes[4]_i_6_n_0\, + I1 => \complex_num_writes[4]_i_5_n_0\, + I2 => \complex_num_writes[4]_i_4_n_0\, + O => \complex_num_writes[3]_i_2_n_0\ + ); +\complex_num_writes[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40001555" + ) + port map ( + I0 => \complex_num_writes[4]_i_6_n_0\, + I1 => \complex_num_writes_reg_n_0_[2]\, + I2 => \complex_num_writes_reg_n_0_[0]\, + I3 => \complex_num_writes_reg_n_0_[1]\, + I4 => \complex_num_writes_reg_n_0_[3]\, + O => \complex_num_writes[3]_i_3_n_0\ + ); +\complex_num_writes[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000800000000000" + ) + port map ( + I0 => complex_row0_wr_done, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => ddr3_lm_done_r_i_2_n_0, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[5]\, + O => \complex_num_writes[3]_i_4_n_0\ + ); +\complex_num_writes[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00008A808A808A80" + ) + port map ( + I0 => \complex_num_writes[4]_i_2_n_0\, + I1 => \complex_num_writes[4]_i_3_n_0\, + I2 => \complex_num_writes[4]_i_4_n_0\, + I3 => \complex_num_writes_reg_n_0_[4]\, + I4 => \complex_num_writes[4]_i_5_n_0\, + I5 => \complex_num_writes[4]_i_6_n_0\, + O => \complex_num_writes[4]_i_1_n_0\ + ); +\complex_num_writes[4]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFE080" + ) + port map ( + I0 => \complex_num_writes_reg_n_0_[1]\, + I1 => \complex_num_writes_reg_n_0_[2]\, + I2 => \complex_num_writes_reg_n_0_[3]\, + I3 => \complex_num_writes[4]_i_14_n_0\, + I4 => \complex_num_writes[4]_i_15_n_0\, + I5 => \complex_num_writes_reg_n_0_[4]\, + O => \complex_num_writes[4]_i_10_n_0\ + ); +\complex_num_writes[4]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000222A" + ) + port map ( + I0 => \complex_num_writes[4]_i_15_n_0\, + I1 => \complex_num_writes_reg_n_0_[2]\, + I2 => \complex_num_writes_reg_n_0_[0]\, + I3 => \complex_num_writes_reg_n_0_[1]\, + I4 => \complex_num_writes_reg_n_0_[4]\, + I5 => \complex_num_writes_reg_n_0_[3]\, + O => \complex_num_writes[4]_i_11_n_0\ + ); +\complex_num_writes[4]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FCF8FCF0FCF8FCF8" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I2 => \complex_num_writes[4]_i_16_n_0\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I5 => \complex_num_writes[4]_i_17_n_0\, + O => \complex_num_writes[4]_i_12_n_0\ + ); +\complex_num_writes[4]_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + O => \complex_num_writes[4]_i_13_n_0\ + ); +\complex_num_writes[4]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEF0" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + O => \complex_num_writes[4]_i_14_n_0\ + ); +\complex_num_writes[4]_i_15\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAEAEAAA" + ) + port map ( + I0 => \complex_num_writes[4]_i_18_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + O => \complex_num_writes[4]_i_15_n_0\ + ); +\complex_num_writes[4]_i_16\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + O => \complex_num_writes[4]_i_16_n_0\ + ); +\complex_num_writes[4]_i_17\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + O => \complex_num_writes[4]_i_17_n_0\ + ); +\complex_num_writes[4]_i_18\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FEFEFEFC" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + O => \complex_num_writes[4]_i_18_n_0\ + ); +\complex_num_writes[4]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => \complex_num_writes[2]_i_2_n_0\, + I1 => \complex_num_writes[4]_i_7_n_0\, + I2 => \complex_num_writes[4]_i_5_n_0\, + O => \complex_num_writes[4]_i_2_n_0\ + ); +\complex_num_writes[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C0EAEAC0EAC0EAC0" + ) + port map ( + I0 => \complex_num_writes[4]_i_5_n_0\, + I1 => complex_row0_wr_done, + I2 => \complex_num_writes[4]_i_8_n_0\, + I3 => \complex_num_writes_reg_n_0_[4]\, + I4 => \complex_num_writes[4]_i_9_n_0\, + I5 => \complex_num_writes_reg_n_0_[3]\, + O => \complex_num_writes[4]_i_3_n_0\ + ); +\complex_num_writes[4]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFBAAAA" + ) + port map ( + I0 => \complex_num_writes[4]_i_8_n_0\, + I1 => \complex_num_writes[4]_i_10_n_0\, + I2 => \complex_num_writes[4]_i_11_n_0\, + I3 => \complex_num_writes[4]_i_12_n_0\, + I4 => \complex_num_writes[4]_i_5_n_0\, + O => \complex_num_writes[4]_i_4_n_0\ + ); +\complex_num_writes[4]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000800000" + ) + port map ( + I0 => complex_wait_cnt_reg(2), + I1 => complex_wait_cnt_reg(3), + I2 => complex_wait_cnt_reg(1), + I3 => complex_wait_cnt_reg(0), + I4 => \complex_address[9]_i_2_n_0\, + I5 => complex_row0_wr_done, + O => \complex_num_writes[4]_i_5_n_0\ + ); +\complex_num_writes[4]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \complex_num_writes[4]_i_13_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + O => \complex_num_writes[4]_i_6_n_0\ + ); +\complex_num_writes[4]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \complex_num_reads[3]_i_7_n_0\, + I1 => \complex_num_reads[1]_i_2_n_0\, + O => \complex_num_writes[4]_i_7_n_0\ + ); +\complex_num_writes[4]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000200000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => ddr3_lm_done_r_i_2_n_0, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r_reg_n_0_[2]\, + O => \complex_num_writes[4]_i_8_n_0\ + ); +\complex_num_writes[4]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \complex_num_writes_reg_n_0_[2]\, + I1 => \complex_num_writes_reg_n_0_[0]\, + I2 => \complex_num_writes_reg_n_0_[1]\, + O => \complex_num_writes[4]_i_9_n_0\ + ); +\complex_num_writes_dec[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"74" + ) + port map ( + I0 => complex_num_writes_dec_reg(0), + I1 => \complex_num_writes_dec[4]_i_4_n_0\, + I2 => \complex_num_writes_reg_n_0_[0]\, + O => \p_0_in__7\(0) + ); +\complex_num_writes_dec[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9F90" + ) + port map ( + I0 => complex_num_writes_dec_reg(1), + I1 => complex_num_writes_dec_reg(0), + I2 => \complex_num_writes_dec[4]_i_4_n_0\, + I3 => \complex_num_writes_reg_n_0_[1]\, + O => \p_0_in__7\(1) + ); +\complex_num_writes_dec[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A9FFA900" + ) + port map ( + I0 => complex_num_writes_dec_reg(2), + I1 => complex_num_writes_dec_reg(0), + I2 => complex_num_writes_dec_reg(1), + I3 => \complex_num_writes_dec[4]_i_4_n_0\, + I4 => \complex_num_writes_reg_n_0_[2]\, + O => \p_0_in__7\(2) + ); +\complex_num_writes_dec[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAA9FFFFAAA90000" + ) + port map ( + I0 => complex_num_writes_dec_reg(3), + I1 => complex_num_writes_dec_reg(2), + I2 => complex_num_writes_dec_reg(1), + I3 => complex_num_writes_dec_reg(0), + I4 => \complex_num_writes_dec[4]_i_4_n_0\, + I5 => \complex_num_writes_reg_n_0_[3]\, + O => \p_0_in__7\(3) + ); +\complex_num_writes_dec[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^prbs_rdlvl_done_pulse_reg_0\, + I1 => \complex_wait_cnt_reg[3]_0\, + O => complex_row0_rd_done1 + ); +\complex_num_writes_dec[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"5555FDFF" + ) + port map ( + I0 => \complex_num_writes_dec[4]_i_4_n_0\, + I1 => complex_num_writes_dec_reg(4), + I2 => complex_num_writes_dec_reg(3), + I3 => \complex_num_writes_dec[4]_i_5_n_0\, + I4 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + O => \complex_num_writes_dec[4]_i_2_n_0\ + ); +\complex_num_writes_dec[4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"9AFF9A00" + ) + port map ( + I0 => complex_num_writes_dec_reg(4), + I1 => complex_num_writes_dec_reg(3), + I2 => \complex_num_writes_dec[4]_i_5_n_0\, + I3 => \complex_num_writes_dec[4]_i_4_n_0\, + I4 => \complex_num_writes_reg_n_0_[4]\, + O => \p_0_in__7\(4) + ); +\complex_num_writes_dec[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555554555555" + ) + port map ( + I0 => \complex_num_reads_dec[3]_i_4_n_0\, + I1 => complex_row0_rd_done, + I2 => \init_state_r[1]_i_22_n_0\, + I3 => \stg1_wr_rd_cnt[4]_i_4_n_0\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => \complex_num_writes_dec[4]_i_4_n_0\ + ); +\complex_num_writes_dec[4]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => complex_num_writes_dec_reg(0), + I1 => complex_num_writes_dec_reg(1), + I2 => complex_num_writes_dec_reg(2), + O => \complex_num_writes_dec[4]_i_5_n_0\ + ); +\complex_num_writes_dec_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \complex_num_writes_dec[4]_i_2_n_0\, + D => \p_0_in__7\(0), + Q => complex_num_writes_dec_reg(0), + S => complex_row0_rd_done1 + ); +\complex_num_writes_dec_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \complex_num_writes_dec[4]_i_2_n_0\, + D => \p_0_in__7\(1), + Q => complex_num_writes_dec_reg(1), + R => complex_row0_rd_done1 + ); +\complex_num_writes_dec_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \complex_num_writes_dec[4]_i_2_n_0\, + D => \p_0_in__7\(2), + Q => complex_num_writes_dec_reg(2), + R => complex_row0_rd_done1 + ); +\complex_num_writes_dec_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \complex_num_writes_dec[4]_i_2_n_0\, + D => \p_0_in__7\(3), + Q => complex_num_writes_dec_reg(3), + R => complex_row0_rd_done1 + ); +\complex_num_writes_dec_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \complex_num_writes_dec[4]_i_2_n_0\, + D => \p_0_in__7\(4), + Q => complex_num_writes_dec_reg(4), + R => complex_row0_rd_done1 + ); +\complex_num_writes_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_writes[0]_i_1_n_0\, + Q => \complex_num_writes_reg_n_0_[0]\, + R => '0' + ); +\complex_num_writes_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_writes[1]_i_1_n_0\, + Q => \complex_num_writes_reg_n_0_[1]\, + R => '0' + ); +\complex_num_writes_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_writes[2]_i_1_n_0\, + Q => \complex_num_writes_reg_n_0_[2]\, + R => '0' + ); +\complex_num_writes_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_writes[3]_i_1_n_0\, + Q => \complex_num_writes_reg_n_0_[3]\, + R => '0' + ); +\complex_num_writes_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_num_writes[4]_i_1_n_0\, + Q => \complex_num_writes_reg_n_0_[4]\, + R => '0' + ); +complex_ocal_odt_ext_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"2202220200002202" + ) + port map ( + I0 => complex_ocal_odt_ext_i_2_n_0, + I1 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I2 => calib_wrdata_en_i_2_n_0, + I3 => complex_ocal_odt_ext, + I4 => prech_req_posedge_r_i_2_n_0, + I5 => complex_ocal_odt_ext_i_3_n_0, + O => complex_ocal_odt_ext_i_1_n_0 + ); +complex_ocal_odt_ext_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF7FFFFFFFFFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => detect_pi_found_dqs_i_2_n_0, + I2 => init_state_r(6), + I3 => \init_state_r_reg_n_0_[5]\, + I4 => ddr3_lm_done_r_i_2_n_0, + I5 => cnt_cmd_done_m7_r, + O => complex_ocal_odt_ext_i_2_n_0 + ); +complex_ocal_odt_ext_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFDFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[4]\, + O => complex_ocal_odt_ext_i_3_n_0 + ); +complex_ocal_odt_ext_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_ocal_odt_ext_i_1_n_0, + Q => complex_ocal_odt_ext, + R => '0' + ); +complex_ocal_reset_rd_addr_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAEAAAAAAAAAA" + ) + port map ( + I0 => prbs_rdlvl_done_pulse0, + I1 => complex_wait_cnt_reg(0), + I2 => complex_wait_cnt_reg(1), + I3 => complex_wait_cnt_reg(3), + I4 => complex_wait_cnt_reg(2), + I5 => complex_ocal_reset_rd_addr_i_2_n_0, + O => complex_ocal_reset_rd_addr0 + ); +complex_ocal_reset_rd_addr_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \wrcal_reads[7]_i_5_n_0\, + O => complex_ocal_reset_rd_addr_i_2_n_0 + ); +complex_ocal_reset_rd_addr_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_ocal_reset_rd_addr0, + Q => complex_ocal_reset_rd_addr, + R => '0' + ); +complex_oclkdelay_calib_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(3), + Q => complex_oclkdelay_calib_done_r1, + R => pi_dqs_found_done_r1_reg_0 + ); +complex_oclkdelay_calib_start_int_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF08" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => complex_oclkdelay_calib_start_int_i_2_n_0, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => complex_oclkdelay_calib_start_int, + O => complex_oclkdelay_calib_start_int_i_1_n_0 + ); +complex_oclkdelay_calib_start_int_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0020000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => complex_oclkdelay_calib_start_int_i_2_n_0 + ); +complex_oclkdelay_calib_start_int_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_oclkdelay_calib_start_int_i_1_n_0, + Q => complex_oclkdelay_calib_start_int, + R => pi_dqs_found_done_r1_reg_0 + ); +complex_oclkdelay_calib_start_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_oclkdelay_calib_start_int, + Q => complex_oclkdelay_calib_start_r1, + R => '0' + ); +complex_odt_ext_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAA0020" + ) + port map ( + I0 => complex_row1_rd_done_i_2_n_0, + I1 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => complex_sample_cnt_inc_i_2_n_0, + I4 => complex_odt_ext, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => complex_odt_ext_i_1_n_0 + ); +complex_odt_ext_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_odt_ext_i_1_n_0, + Q => complex_odt_ext, + R => '0' + ); +complex_row0_rd_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAA8000" + ) + port map ( + I0 => complex_row0_rd_done_reg_0, + I1 => complex_row1_wr_done, + I2 => complex_oclkdelay_calib_start_int, + I3 => complex_row1_wr_done0, + I4 => complex_row0_rd_done, + I5 => complex_sample_cnt_inc_reg_n_0, + O => complex_row0_rd_done_i_1_n_0 + ); +complex_row0_rd_done_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000020" + ) + port map ( + I0 => complex_row0_wr_done, + I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I4 => wr_victim_inc_i_2_n_0, + O => complex_row1_wr_done0 + ); +complex_row0_rd_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_row0_rd_done_i_1_n_0, + Q => complex_row0_rd_done, + R => '0' + ); +\complex_row1_rd_cnt[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000A6" + ) + port map ( + I0 => complex_row1_rd_cnt(0), + I1 => complex_row1_rd_done, + I2 => complex_row1_rd_done_r1, + I3 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I4 => \^prbs_rdlvl_done_pulse_reg_0\, + O => \complex_row1_rd_cnt[0]_i_1_n_0\ + ); +\complex_row1_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000009AAA" + ) + port map ( + I0 => complex_row1_rd_cnt(1), + I1 => complex_row1_rd_done_r1, + I2 => complex_row1_rd_done, + I3 => complex_row1_rd_cnt(0), + I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I5 => \^prbs_rdlvl_done_pulse_reg_0\, + O => \complex_row1_rd_cnt[1]_i_1_n_0\ + ); +\complex_row1_rd_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000009AAAAAAA" + ) + port map ( + I0 => complex_row1_rd_cnt(2), + I1 => complex_row1_rd_done_r1, + I2 => complex_row1_rd_done, + I3 => complex_row1_rd_cnt(1), + I4 => complex_row1_rd_cnt(0), + I5 => complex_row0_rd_done1, + O => \complex_row1_rd_cnt[2]_i_1_n_0\ + ); +\complex_row1_rd_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_row1_rd_cnt[0]_i_1_n_0\, + Q => complex_row1_rd_cnt(0), + R => '0' + ); +\complex_row1_rd_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_row1_rd_cnt[1]_i_1_n_0\, + Q => complex_row1_rd_cnt(1), + R => '0' + ); +\complex_row1_rd_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \complex_row1_rd_cnt[2]_i_1_n_0\, + Q => complex_row1_rd_cnt(2), + R => '0' + ); +complex_row1_rd_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0202020200020000" + ) + port map ( + I0 => complex_row1_rd_done_i_2_n_0, + I1 => \complex_wait_cnt_reg[3]_0\, + I2 => \^prbs_rdlvl_done_pulse_reg_0\, + I3 => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\, + I4 => complex_row0_rd_done, + I5 => complex_row1_rd_done, + O => complex_row1_rd_done_i_1_n_0 + ); +complex_row1_rd_done_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFDF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => init_state_r(6), + O => complex_row1_rd_done_i_2_n_0 + ); +complex_row1_rd_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_row1_rd_done, + Q => complex_row1_rd_done_r1, + R => '0' + ); +complex_row1_rd_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_row1_rd_done_i_1_n_0, + Q => complex_row1_rd_done, + R => '0' + ); +\complex_row_cnt_ocal[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => complex_row_cnt_ocal_reg(0), + O => \p_0_in__4\(0) + ); +\complex_row_cnt_ocal[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => complex_row_cnt_ocal_reg(1), + I1 => complex_row_cnt_ocal_reg(0), + O => \p_0_in__4\(1) + ); +\complex_row_cnt_ocal[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => complex_row_cnt_ocal_reg(2), + I1 => complex_row_cnt_ocal_reg(0), + I2 => complex_row_cnt_ocal_reg(1), + O => \p_0_in__4\(2) + ); +\complex_row_cnt_ocal[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFF8F" + ) + port map ( + I0 => wr_victim_inc, + I1 => \complex_row_cnt_ocal[3]_i_4_n_0\, + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => complex_byte_rd_done, + I4 => \^prbs_rdlvl_done_pulse_reg_0\, + I5 => \complex_wait_cnt_reg[3]_0\, + O => complex_row_cnt_ocal0 + ); +\complex_row_cnt_ocal[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFF20000" + ) + port map ( + I0 => \complex_row_cnt_ocal[3]_i_5_n_0\, + I1 => \complex_row_cnt_ocal[3]_i_6_n_0\, + I2 => wr_victim_inc, + I3 => complex_sample_cnt_inc_r2, + I4 => D(3), + I5 => \complex_row_cnt_ocal[3]_i_4_n_0\, + O => complex_row_cnt_ocal + ); +\complex_row_cnt_ocal[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => complex_row_cnt_ocal_reg(3), + I1 => complex_row_cnt_ocal_reg(1), + I2 => complex_row_cnt_ocal_reg(0), + I3 => complex_row_cnt_ocal_reg(2), + O => \p_0_in__4\(3) + ); +\complex_row_cnt_ocal[3]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => complex_row_cnt_ocal_reg(3), + I1 => complex_row_cnt_ocal_reg(1), + I2 => complex_row_cnt_ocal_reg(0), + I3 => complex_row_cnt_ocal_reg(2), + O => \complex_row_cnt_ocal[3]_i_4_n_0\ + ); +\complex_row_cnt_ocal[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0002000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + O => \complex_row_cnt_ocal[3]_i_5_n_0\ + ); +\complex_row_cnt_ocal[3]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFDFFFFFFFFFFF" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I4 => \complex_row_cnt_ocal[3]_i_7_n_0\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + O => \complex_row_cnt_ocal[3]_i_6_n_0\ + ); +\complex_row_cnt_ocal[3]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + O => \complex_row_cnt_ocal[3]_i_7_n_0\ + ); +\complex_row_cnt_ocal_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt_ocal, + D => \p_0_in__4\(0), + Q => complex_row_cnt_ocal_reg(0), + R => complex_row_cnt_ocal0 + ); +\complex_row_cnt_ocal_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt_ocal, + D => \p_0_in__4\(1), + Q => complex_row_cnt_ocal_reg(1), + R => complex_row_cnt_ocal0 + ); +\complex_row_cnt_ocal_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt_ocal, + D => \p_0_in__4\(2), + Q => complex_row_cnt_ocal_reg(2), + R => complex_row_cnt_ocal0 + ); +\complex_row_cnt_ocal_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt_ocal, + D => \p_0_in__4\(3), + Q => complex_row_cnt_ocal_reg(3), + R => complex_row_cnt_ocal0 + ); +complex_sample_cnt_inc_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => complex_row1_rd_done, + I1 => complex_sample_cnt_inc_i_2_n_0, + O => complex_sample_cnt_inc0 + ); +complex_sample_cnt_inc_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => wr_victim_inc_i_2_n_0, + I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + O => complex_sample_cnt_inc_i_2_n_0 + ); +complex_sample_cnt_inc_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_sample_cnt_inc_reg_n_0, + Q => complex_sample_cnt_inc_r1, + R => '0' + ); +complex_sample_cnt_inc_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_sample_cnt_inc_r1, + Q => complex_sample_cnt_inc_r2, + R => '0' + ); +complex_sample_cnt_inc_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_sample_cnt_inc0, + Q => complex_sample_cnt_inc_reg_n_0, + R => pi_dqs_found_done_r1_reg_0 + ); +\complex_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => complex_wait_cnt_reg(0), + O => \p_0_in__6\(0) + ); +\complex_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => complex_wait_cnt_reg(1), + I1 => complex_wait_cnt_reg(0), + O => \p_0_in__6\(1) + ); +\complex_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => complex_wait_cnt_reg(1), + I1 => complex_wait_cnt_reg(0), + I2 => complex_wait_cnt_reg(2), + O => \p_0_in__6\(2) + ); +\complex_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFEAAAAAAA" + ) + port map ( + I0 => \complex_wait_cnt[3]_i_3_n_0\, + I1 => complex_wait_cnt_reg(2), + I2 => complex_wait_cnt_reg(3), + I3 => complex_wait_cnt_reg(0), + I4 => complex_wait_cnt_reg(1), + I5 => \complex_wait_cnt_reg[3]_0\, + O => \complex_wait_cnt[3]_i_1_n_0\ + ); +\complex_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => complex_wait_cnt_reg(3), + I1 => complex_wait_cnt_reg(1), + I2 => complex_wait_cnt_reg(0), + I3 => complex_wait_cnt_reg(2), + O => \p_0_in__6\(3) + ); +\complex_wait_cnt[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFC5FF9FFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \wrcal_reads[7]_i_4_n_0\, + O => \complex_wait_cnt[3]_i_3_n_0\ + ); +\complex_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__6\(0), + Q => complex_wait_cnt_reg(0), + R => \complex_wait_cnt[3]_i_1_n_0\ + ); +\complex_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__6\(1), + Q => complex_wait_cnt_reg(1), + R => \complex_wait_cnt[3]_i_1_n_0\ + ); +\complex_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__6\(2), + Q => complex_wait_cnt_reg(2), + R => \complex_wait_cnt[3]_i_1_n_0\ + ); +\complex_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__6\(3), + Q => complex_wait_cnt_reg(3), + R => \complex_wait_cnt[3]_i_1_n_0\ + ); +ddr2_pre_flag_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"22222F2022222222" + ) + port map ( + I0 => ddr2_pre_flag_r_reg_n_0, + I1 => ddr2_pre_flag_r_i_2_n_0, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \cnt_init_mr_r[0]_i_2_n_0\, + O => ddr2_pre_flag_r_i_1_n_0 + ); +ddr2_pre_flag_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \init_state_r[6]_i_3_n_0\, + I1 => detect_pi_found_dqs_i_2_n_0, + I2 => ddr3_lm_done_r_i_2_n_0, + I3 => cnt_cmd_done_r, + I4 => ddr2_refresh_flag_r, + I5 => cnt_init_mr_done_r, + O => ddr2_pre_flag_r_i_2_n_0 + ); +ddr2_pre_flag_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ddr2_pre_flag_r_i_1_n_0, + Q => ddr2_pre_flag_r_reg_n_0, + R => '0' + ); +ddr2_refresh_flag_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFF70F0" + ) + port map ( + I0 => ddr2_refresh_flag_r_i_2_n_0, + I1 => cnt_cmd_done_r, + I2 => ddr2_refresh_flag_r, + I3 => cnt_init_mr_done_r, + I4 => cnt_init_mr_r1, + I5 => ddr2_pre_flag_r, + O => ddr2_refresh_flag_r_i_1_n_0 + ); +ddr2_refresh_flag_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => ddr3_lm_done_r_i_2_n_0, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => ddr2_refresh_flag_r_i_2_n_0 + ); +ddr2_refresh_flag_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ddr2_refresh_flag_r_i_1_n_0, + Q => ddr2_refresh_flag_r, + R => '0' + ); +ddr3_lm_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF02000000" + ) + port map ( + I0 => ddr3_lm_done_r_i_2_n_0, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r[6]_i_3_n_0\, + I4 => burst_addr_r_reg_0, + I5 => \^ddr3_lm_done_r\, + O => ddr3_lm_done_r_i_1_n_0 + ); +ddr3_lm_done_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[1]\, + O => ddr3_lm_done_r_i_2_n_0 + ); +ddr3_lm_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => ddr3_lm_done_r_i_1_n_0, + Q => \^ddr3_lm_done_r\, + R => pi_dqs_found_done_r1_reg_0 + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_ras_n(0), + I1 => out_fifo_7, + I2 => phy_ras_n(1), + I3 => out_fifo_8(8), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_ras_n_reg[1]\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_14\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => phy_bank(11), + I1 => out_fifo_7, + I2 => out_fifo_8(12), + I3 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_15\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(8), + I1 => phy_bank(11), + I2 => out_fifo_7, + I3 => out_fifo_8(11), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_16\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(5), + I1 => phy_bank(11), + I2 => out_fifo_7, + I3 => out_fifo_8(10), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_17\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(2), + I1 => phy_bank(11), + I2 => out_fifo_7, + I3 => out_fifo_8(9), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_18\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I1 => out_fifo_7, + I2 => out_fifo_8(16), + I3 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_19\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(28), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I2 => out_fifo_7, + I3 => out_fifo_8(15), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I1 => out_fifo_7, + I2 => out_fifo_8(3), + I3 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_20\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(17), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I2 => out_fifo_7, + I3 => out_fifo_8(14), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_21\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(5), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I2 => out_fifo_7, + I3 => out_fifo_8(13), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_22\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_cke(0), + I1 => out_fifo_0, + I2 => calib_cke(3), + I3 => out_fifo_8(24), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(7) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_23\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_cke(0), + I1 => out_fifo_0, + I2 => calib_cke(3), + I3 => out_fifo_8(23), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(6) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_24\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_cke(0), + I1 => out_fifo_0, + I2 => calib_cke(3), + I3 => out_fifo_8(22), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(5) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_25\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_cke(0), + I1 => out_fifo_0, + I2 => calib_cke(3), + I3 => out_fifo_8(21), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(4) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_26\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I1 => out_fifo_0, + I2 => out_fifo_8(20), + I3 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_27\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(23), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I2 => out_fifo_0, + I3 => out_fifo_8(19), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_28\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(12), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I2 => out_fifo_0, + I3 => out_fifo_8(18), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_29\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(0), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I2 => out_fifo_7, + I3 => out_fifo_8(17), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_cke_reg[3]\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(26), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => out_fifo_7, + I3 => out_fifo_8(2), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_30\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => phy_bank(10), + I1 => out_fifo_0, + I2 => out_fifo_8(29), + I3 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(4) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_31\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(7), + I1 => phy_bank(10), + I2 => out_fifo_0, + I3 => out_fifo_8(28), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_32\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(4), + I1 => phy_bank(10), + I2 => out_fifo_0, + I3 => out_fifo_8(27), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_33\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(1), + I1 => phy_bank(10), + I2 => out_fifo_0, + I3 => out_fifo_8(26), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_36\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_cas_n(0), + I1 => out_fifo_0, + I2 => phy_cas_n(1), + I3 => out_fifo_8(25), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_38\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => phy_bank(9), + I1 => out_fifo_0, + I2 => out_fifo_8(33), + I3 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_39\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(6), + I1 => phy_bank(9), + I2 => out_fifo_0, + I3 => out_fifo_8(32), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(15), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => out_fifo_7, + I3 => out_fifo_8(1), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_40\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(3), + I1 => phy_bank(9), + I2 => out_fifo_0, + I3 => out_fifo_8(31), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_41\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_bank(0), + I1 => phy_bank(9), + I2 => out_fifo_0, + I3 => out_fifo_8(30), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_42\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_odt(0), + I1 => out_fifo_0, + I2 => calib_odt(0), + I3 => out_fifo_8(37), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_odt_reg[0]\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_43\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_odt(0), + I1 => out_fifo_0, + I2 => calib_odt(0), + I3 => out_fifo_8(36), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_odt_reg[0]\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_44\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_odt(0), + I1 => out_fifo_0, + I2 => calib_odt(0), + I3 => out_fifo_8(35), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_odt_reg[0]\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_45\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_odt(0), + I1 => out_fifo_0, + I2 => calib_odt(0), + I3 => out_fifo_8(34), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_odt_reg[0]\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_48\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8B8FF00" + ) + port map ( + I0 => mc_we_n(0), + I1 => out_fifo_0, + I2 => phy_we_n(1), + I3 => out_fifo_8(38), + I4 => out_fifo_9, + O => \cmd_pipe_plus.mc_we_n_reg[1]_0\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(3), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => out_fifo_7, + I3 => out_fifo_8(0), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I1 => out_fifo_7, + I2 => out_fifo_8(7), + I3 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(3) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(33), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I2 => out_fifo_7, + I3 => out_fifo_8(6), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(22), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I2 => out_fifo_7, + I3 => out_fifo_8(5), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(10), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I2 => out_fifo_7, + I3 => out_fifo_8(4), + I4 => out_fifo_9, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(0) + ); +detect_pi_found_dqs_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000400000" + ) + port map ( + I0 => \cnt_cmd_r[6]_i_4_n_0\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => detect_pi_found_dqs_i_2_n_0, + I3 => detect_pi_found_dqs_i_3_n_0, + I4 => prech_req_posedge_r_i_2_n_0, + I5 => \cnt_cmd_r_reg_n_0_[6]\, + O => detect_pi_found_dqs0 + ); +detect_pi_found_dqs_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[3]\, + O => detect_pi_found_dqs_i_2_n_0 + ); +detect_pi_found_dqs_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[5]\, + O => detect_pi_found_dqs_i_3_n_0 + ); +detect_pi_found_dqs_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => detect_pi_found_dqs0, + Q => \^detect_pi_found_dqs\, + R => pi_dqs_found_done_r1_reg_0 + ); +\dqs_asrt_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000E6E600E6" + ) + port map ( + I0 => dqs_asrt_cnt(0), + I1 => wr_level_dqs_asrt, + I2 => dqs_asrt_cnt(1), + I3 => wrlvl_done_r, + I4 => \^wrlvl_done_r1\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \dqs_asrt_cnt[0]_i_1_n_0\ + ); +\dqs_asrt_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000ECEC00EC" + ) + port map ( + I0 => dqs_asrt_cnt(0), + I1 => dqs_asrt_cnt(1), + I2 => wr_level_dqs_asrt, + I3 => wrlvl_done_r, + I4 => \^wrlvl_done_r1\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \dqs_asrt_cnt[1]_i_1_n_0\ + ); +\dqs_asrt_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \dqs_asrt_cnt[0]_i_1_n_0\, + Q => dqs_asrt_cnt(0), + R => '0' + ); +\dqs_asrt_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \dqs_asrt_cnt[1]_i_1_n_0\, + Q => dqs_asrt_cnt(1), + R => '0' + ); +\en_cnt_div4.enable_wrlvl_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000005554" + ) + port map ( + I0 => enable_wrlvl_cnt(0), + I1 => enable_wrlvl_cnt(2), + I2 => enable_wrlvl_cnt(3), + I3 => enable_wrlvl_cnt(1), + I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\ + ); +\en_cnt_div4.enable_wrlvl_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000009998" + ) + port map ( + I0 => enable_wrlvl_cnt(1), + I1 => enable_wrlvl_cnt(0), + I2 => enable_wrlvl_cnt(3), + I3 => enable_wrlvl_cnt(2), + I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\ + ); +\en_cnt_div4.enable_wrlvl_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFEE10" + ) + port map ( + I0 => enable_wrlvl_cnt(1), + I1 => enable_wrlvl_cnt(0), + I2 => enable_wrlvl_cnt(3), + I3 => enable_wrlvl_cnt(2), + I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\, + O => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\ + ); +\en_cnt_div4.enable_wrlvl_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF0E0" + ) + port map ( + I0 => enable_wrlvl_cnt(1), + I1 => enable_wrlvl_cnt(0), + I2 => enable_wrlvl_cnt(3), + I3 => enable_wrlvl_cnt(2), + I4 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\, + O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\ + ); +\en_cnt_div4.enable_wrlvl_cnt[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00010000" + ) + port map ( + I0 => enable_wrlvl_cnt(2), + I1 => enable_wrlvl_cnt(3), + I2 => enable_wrlvl_cnt(0), + I3 => enable_wrlvl_cnt(1), + I4 => wrlvl_odt, + I5 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0\, + O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_2_n_0\ + ); +\en_cnt_div4.enable_wrlvl_cnt[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000200000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => init_state_r(6), + I5 => prech_req_posedge_r_i_2_n_0, + O => \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0\ + ); +\en_cnt_div4.enable_wrlvl_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0\, + Q => enable_wrlvl_cnt(0), + R => '0' + ); +\en_cnt_div4.enable_wrlvl_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0\, + Q => enable_wrlvl_cnt(1), + R => '0' + ); +\en_cnt_div4.enable_wrlvl_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0\, + Q => enable_wrlvl_cnt(2), + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\en_cnt_div4.enable_wrlvl_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0\, + Q => enable_wrlvl_cnt(3), + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +\en_cnt_div4.wrlvl_odt_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0054" + ) + port map ( + I0 => \complex_wait_cnt_reg[3]_0\, + I1 => \en_cnt_div4.wrlvl_odt_i_2_n_0\, + I2 => wrlvl_odt, + I3 => wrlvl_odt_ctl, + O => \en_cnt_div4.wrlvl_odt_i_1_n_0\ + ); +\en_cnt_div4.wrlvl_odt_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => enable_wrlvl_cnt(2), + I1 => enable_wrlvl_cnt(3), + I2 => enable_wrlvl_cnt(0), + I3 => enable_wrlvl_cnt(1), + O => \en_cnt_div4.wrlvl_odt_i_2_n_0\ + ); +\en_cnt_div4.wrlvl_odt_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \en_cnt_div4.wrlvl_odt_i_1_n_0\, + Q => wrlvl_odt, + R => '0' + ); +first_rdlvl_pat_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF8" + ) + port map ( + I0 => \^first_rdlvl_pat_r\, + I1 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + I2 => rdlvl_stg1_rank_done, + I3 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => first_rdlvl_pat_r_i_1_n_0 + ); +first_rdlvl_pat_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => first_rdlvl_pat_r_i_1_n_0, + Q => \^first_rdlvl_pat_r\, + R => '0' + ); +first_wrcal_pat_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFBAAAB" + ) + port map ( + I0 => \complex_wait_cnt_reg[3]_0\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => first_wrcal_pat_r_i_2_n_0, + I4 => \^first_wrcal_pat_r\, + I5 => wrcal_resume_w, + O => first_wrcal_pat_r_i_1_n_0 + ); +first_wrcal_pat_r_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFB" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[2]\, + O => first_wrcal_pat_r_i_2_n_0 + ); +first_wrcal_pat_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => first_wrcal_pat_r_i_1_n_0, + Q => \^first_wrcal_pat_r\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFF20000" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\, + O => address_w(0) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I1 => D(3), + I2 => complex_row_cnt_ocal_reg(0), + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA20" + ) + port map ( + I0 => \complex_address_reg_n_0_[0]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\, + I2 => init_state_r(6), + I3 => reg_ctrl_cnt_r_reg(0), + I4 => reg_ctrl_cnt_r_reg(3), + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0109000100000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => init_state_r(6), + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + O => address_w173_out + ); +\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000010020" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \init_state_r[6]_i_4_n_0\, + O => \^init_state_r_reg[2]_0\(0) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFF4F4F4" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\, + I3 => \complex_address_reg_n_0_[1]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\, + O => address_w(1) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"454045404540FFFF" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\, + I1 => complex_row_cnt_ocal_reg(1), + I2 => D(3), + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\, + I5 => init_state_r(6), + O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FBAA" + ) + port map ( + I0 => address_w173_out, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000FFFFA0C" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\, + I5 => init_state_r(6), + O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FDDD" + ) + port map ( + I0 => cnt_init_mr_r(1), + I1 => cnt_init_mr_r(0), + I2 => D(3), + I3 => pi_dqs_found_done, + O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => reg_ctrl_cnt_r_reg(3), + I1 => reg_ctrl_cnt_r_reg(1), + O => \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFBBFBAAAAAAAA" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\, + O => address_w(2) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4501010101014501" + ) + port map ( + I0 => init_state_r(6), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\, + I3 => \gen_rnk[0].mr1_r_reg_n_0_[0][0]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"55DF" + ) + port map ( + I0 => \complex_address_reg_n_0_[2]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\, + I1 => D(3), + I2 => complex_row_cnt_ocal_reg(2), + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FF00FFFFFBFB" + ) + port map ( + I0 => reg_ctrl_cnt_r_reg(3), + I1 => reg_ctrl_cnt_r_reg(2), + I2 => reg_ctrl_cnt_r_reg(1), + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000040070000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => \^init_state_r_reg[2]_0\(0), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8FFFFFF" + ) + port map ( + I0 => pi_dqs_found_done, + I1 => D(3), + I2 => cnt_init_mr_r(0), + I3 => cnt_init_mr_r(1), + I4 => \gen_rnk[0].mr1_r_reg_n_0_[0][0]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8A888A888A88AAAA" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\, + I2 => \complex_address_reg_n_0_[3]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + O => address_w(3) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFE200E2" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\, + I1 => D(3), + I2 => complex_row_cnt_ocal_reg(3), + I3 => \^init_state_r_reg[2]_0\(0), + I4 => p_15_in(3), + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFEFEFEFFFEFFFEF" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\, + I3 => D(3), + I4 => \stg1_wr_rd_cnt[8]_i_4_n_0\, + I5 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFAABEAAAAAAAA" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\, + O => address_w(4) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F444F444F4F4F44" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \complex_address_reg_n_0_[4]\, + I1 => \complex_address_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AEEEEAAA" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\, + O => address_w(5) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF111111F1" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\, + I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\, + I2 => \complex_num_writes[2]_i_8_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[5]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_13_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => D(3), + I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I4 => wr_victim_inc_i_2_n_0, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_14_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF44444F44" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_1\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF5510" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\, + I2 => init_state_r1(3), + I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDD5D5D5DDD5" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_11_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"95" + ) + port map ( + I0 => \complex_address_reg_n_0_[5]\, + I1 => \complex_address_reg_n_0_[3]\, + I2 => \complex_address_reg_n_0_[4]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBBBBBBBBBBBFB" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\, + I2 => detect_pi_found_dqs_i_2_n_0, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_12_n_0\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => init_state_r(6), + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555545445555" + ) + port map ( + I0 => D(3), + I1 => \calib_cmd[2]_i_3_n_0\, + I2 => read_calib_i_2_n_0, + I3 => prech_req_posedge_r_i_2_n_0, + I4 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + I5 => \stg1_wr_rd_cnt[8]_i_4_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFF7" + ) + port map ( + I0 => init_state_r1(2), + I1 => init_state_r1(1), + I2 => init_state_r1(5), + I3 => init_state_r1(0), + I4 => init_state_r1(4), + I5 => init_state_r1(6), + O => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8A88AAAA8A888A88" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\, + O => address_w(6) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA22AA2AAA2" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9555" + ) + port map ( + I0 => \complex_address_reg_n_0_[6]\, + I1 => \complex_address_reg_n_0_[5]\, + I2 => \complex_address_reg_n_0_[4]\, + I3 => \complex_address_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[4]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA20AA20AA20AAAA" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\, + O => address_w(7) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5540" + ) + port map ( + I0 => address_w173_out, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\, + I3 => init_state_r(6), + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"95555555" + ) + port map ( + I0 => \complex_address_reg_n_0_[7]\, + I1 => \complex_address_reg_n_0_[6]\, + I2 => \complex_address_reg_n_0_[3]\, + I3 => \complex_address_reg_n_0_[4]\, + I4 => \complex_address_reg_n_0_[5]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0200FFFF02000200" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\, + I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"95555555" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF9DDFFFFFFFFFEF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0191" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFB" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\, + I4 => \^init_state_r_reg[2]_0\(0), + I5 => D(3), + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000001000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => init_state_r(6), + O => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFF141414" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\, + O => address_w(8) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => \complex_address_reg_n_0_[8]\, + I1 => \complex_address_reg_n_0_[7]\, + I2 => \complex_address_reg_n_0_[5]\, + I3 => \complex_address_reg_n_0_[4]\, + I4 => \complex_address_reg_n_0_[3]\, + I5 => \complex_address_reg_n_0_[6]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00808080" + ) + port map ( + I0 => temp_lmr_done, + I1 => cnt_init_mr_r(1), + I2 => cnt_init_mr_r(0), + I3 => pi_dqs_found_done, + I4 => D(3), + O => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF90FF90FFFFFF90" + ) + port map ( + I0 => \complex_address_reg_n_0_[9]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\, + O => address_w(9) + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00020000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \wrcal_reads[7]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => ddr3_lm_done_r_i_2_n_0, + I5 => temp_lmr_done, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFFEFFFEFFFEFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBBBBBBBBBBBBB8B" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\, + I2 => oclk_wr_cnt_reg(2), + I3 => oclk_wr_cnt_reg(3), + I4 => oclk_wr_cnt_reg(1), + I5 => oclk_wr_cnt_reg(0), + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F4" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\, + I1 => init_state_r1(3), + I2 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14\: unisim.vcomponents.LUT5 + generic map( + INIT => X"1F1F1FFF" + ) + port map ( + I0 => \complex_row_cnt_ocal[3]_i_6_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFFFFFFFFFFFFFFF" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17\: unisim.vcomponents.LUT6 + generic map( + INIT => X"20000000AAAAAAAA" + ) + port map ( + I0 => D(3), + I1 => \wrcal_reads[7]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I4 => \wrcal_reads[7]_i_5_n_0\, + I5 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00F2" + ) + port map ( + I0 => init_state_r1(3), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\, + I2 => \^one_rank.stg1_wr_done_reg_0\, + I3 => complex_row0_rd_done, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00001000" + ) + port map ( + I0 => init_state_r1(2), + I1 => init_state_r1(6), + I2 => init_state_r1(3), + I3 => init_state_r1(4), + I4 => init_state_r1(1), + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFFFFFFFFFFFFFF" + ) + port map ( + I0 => \complex_address_reg_n_0_[8]\, + I1 => \complex_address_reg_n_0_[7]\, + I2 => \complex_address_reg_n_0_[5]\, + I3 => \complex_address_reg_n_0_[4]\, + I4 => \complex_address_reg_n_0_[3]\, + I5 => \complex_address_reg_n_0_[6]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAA8AAAA" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0\, + I1 => wrcal_wr_cnt_reg(3), + I2 => wrcal_wr_cnt_reg(1), + I3 => wrcal_wr_cnt_reg(0), + I4 => wrcal_wr_cnt_reg(2), + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055554555" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_22_n_0\, + I1 => \init_state_r[6]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => detect_pi_found_dqs_i_2_n_0, + I4 => \wrcal_reads[7]_i_4_n_0\, + I5 => p_0_in0_in, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_22\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r[2]_i_13_n_0\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => init_state_r(6), + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_22_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AE" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2222200020002000" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0\, + I2 => D(3), + I3 => pi_dqs_found_done, + I4 => cnt_init_mr_r(0), + I5 => cnt_init_mr_r(1), + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"07070007" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5400540054000000" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0\, + I5 => \complex_row_cnt_ocal[3]_i_6_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_10_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"40FF" + ) + port map ( + I0 => init_state_r1(0), + I1 => init_state_r1(5), + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0\, + I3 => \stg1_wr_rd_cnt[8]_i_4_n_0\, + O => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(0), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w173_out, + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^init_state_r_reg[2]_0\(0), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(1), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(2), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(3), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(4), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(5), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(6), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(7), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(8), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => address_w(9), + Q => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00BB003000B00030" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + O => bank_w(0) + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555DFFD5555DDDD" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => cnt_init_mr_r(1), + I3 => cnt_init_mr_r(0), + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_1\, + O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F77F" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => init_state_r(6), + O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[5]\, + O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r_reg_n_0_[2]\, + O => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\, + O => bank_w(1) + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BE7FBE7EBE7FBE7F" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => cnt_init_mr_r(1), + I5 => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_1\, + O => \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0\ + ); +\gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => reg_ctrl_cnt_r, + I1 => reg_ctrl_cnt_r_reg(2), + I2 => reg_ctrl_cnt_r_reg(3), + I3 => reg_ctrl_cnt_r_reg(1), + O => bank_w(2) + ); +\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bank_w(0), + Q => phy_bank(9), + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bank_w(1), + Q => phy_bank(10), + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bank_w(2), + Q => phy_bank(11), + R => '0' + ); +\gen_reset_obuf.u_reset_obuf_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => phy_ctl_wr_i1_reg, + I1 => phy_reset_n, + O => mux_reset_n + ); +\gen_rnk[0].mr1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => '1', + Q => \gen_rnk[0].mr1_r_reg_n_0_[0][0]\, + R => pi_dqs_found_done_r1_reg_0 + ); +init_calib_complete_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_complete_r2, + Q => calib_complete, + R => pi_dqs_found_done_r1_reg_0 + ); +init_complete_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_complete_r_reg_n_0, + Q => init_complete_r1, + R => pi_dqs_found_done_r1_reg_0 + ); +init_complete_r1_timing_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_complete_r_timing, + Q => init_complete_r1_timing, + R => \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) + ); +init_complete_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_complete_r1, + Q => init_complete_r2, + R => pi_dqs_found_done_r1_reg_0 + ); +init_complete_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00004000" + ) + port map ( + I0 => detect_pi_found_dqs_i_3_n_0, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => init_complete_r_reg_n_0, + O => init_complete_r_i_1_n_0 + ); +init_complete_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_complete_r_i_1_n_0, + Q => init_complete_r_reg_n_0, + R => pi_dqs_found_done_r1_reg_0 + ); +init_complete_r_timing_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00004000" + ) + port map ( + I0 => detect_pi_found_dqs_i_3_n_0, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => init_complete_r_timing, + O => init_complete_r_timing_i_1_n_0 + ); +init_complete_r_timing_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_complete_r_timing_i_1_n_0, + Q => init_complete_r_timing, + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r_reg_n_0_[0]\, + Q => init_state_r1(0), + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r_reg_n_0_[1]\, + Q => init_state_r1(1), + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r_reg_n_0_[2]\, + Q => init_state_r1(2), + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r_reg_n_0_[3]\, + Q => init_state_r1(3), + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r_reg_n_0_[4]\, + Q => init_state_r1(4), + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r_reg_n_0_[5]\, + Q => init_state_r1(5), + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_state_r(6), + Q => init_state_r1(6), + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAFEAAFEFFFFAAFE" + ) + port map ( + I0 => \init_state_r[0]_i_2_n_0\, + I1 => \init_state_r[0]_i_3_n_0\, + I2 => \init_state_r[0]_i_4_n_0\, + I3 => \init_state_r[0]_i_5_n_0\, + I4 => \init_state_r[0]_i_6_n_0\, + I5 => \init_state_r[0]_i_7_n_0\, + O => \init_state_r[0]_i_1_n_0\ + ); +\init_state_r[0]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFFFAAAAAFFFAAAA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => cnt_cmd_done_r, + I4 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I5 => \^wrlvl_done_r1\, + O => \init_state_r[0]_i_10_n_0\ + ); +\init_state_r[0]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"223300000FFFFFFF" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => reset_rd_addr_r1, + I2 => \init_state_r[1]_i_4_0\, + I3 => cnt_cmd_done_r, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[0]_i_11_n_0\ + ); +\init_state_r[0]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFFFFFFFFFFFF" + ) + port map ( + I0 => \init_state_r[4]_i_40_n_0\, + I1 => complex_num_writes_dec_reg(1), + I2 => complex_row0_wr_done, + I3 => \^rdlvl_stg1_done_r1_reg_0\, + I4 => D(3), + I5 => complex_num_writes_dec_reg(0), + O => \init_state_r[0]_i_12_n_0\ + ); +\init_state_r[0]_i_13\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFF0008" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => num_reads(0), + I2 => num_reads(1), + I3 => num_reads(2), + I4 => \init_state_r[1]_i_29_n_0\, + I5 => \init_state_r[0]_i_25_n_0\, + O => \init_state_r[0]_i_13_n_0\ + ); +\init_state_r[0]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF10001010" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r[0]_i_5_0\, + I4 => \init_state_r[1]_i_34_n_0\, + I5 => \init_state_r[0]_i_27_n_0\, + O => \init_state_r[0]_i_14_n_0\ + ); +\init_state_r[0]_i_15\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFAAFF3F" + ) + port map ( + I0 => \init_state_r[4]_i_20_n_0\, + I1 => cnt_cmd_done_r, + I2 => ddr2_pre_flag_r_reg_n_0, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[0]_i_15_n_0\ + ); +\init_state_r[0]_i_16\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF0000F800" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r[0]_i_28_n_0\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r[0]_i_29_n_0\, + O => \init_state_r[0]_i_16_n_0\ + ); +\init_state_r[0]_i_17\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[0]_i_17_n_0\ + ); +\init_state_r[0]_i_18\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFB000000000000" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I3 => wr_victim_inc_i_2_n_0, + I4 => \init_state_r[1]_i_22_n_0\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[0]_i_18_n_0\ + ); +\init_state_r[0]_i_19\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0DFF" + ) + port map ( + I0 => D(3), + I1 => complex_oclkdelay_calib_done_r1, + I2 => \^prech_req_posedge_r_reg_0\, + I3 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[0]_i_19_n_0\ + ); +\init_state_r[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8C88" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \ocal_act_wait_cnt[3]_i_3_n_0\, + O => \init_state_r[0]_i_2_n_0\ + ); +\init_state_r[0]_i_20\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF07000FFF07FF0F" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => complex_sample_cnt_inc_i_2_n_0, + I2 => \init_state_r[0]_i_30_n_0\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => prbs_rdlvl_done_pulse0, + O => \init_state_r[0]_i_20_n_0\ + ); +\init_state_r[0]_i_21\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00F202F200000200" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => p_15_in(3), + I5 => cnt_cmd_done_r, + O => \init_state_r[0]_i_21_n_0\ + ); +\init_state_r[0]_i_22\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7500FFFF75007500" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r[3]_i_7_n_0\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r[5]_i_12_n_0\, + I4 => \init_state_r[5]_i_20_n_0\, + I5 => \init_state_r[0]_i_31_n_0\, + O => \init_state_r[0]_i_22_n_0\ + ); +\init_state_r[0]_i_23\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F020F0F00020F" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[0]\, + I1 => \wrcal_reads[7]_i_6_n_0\, + I2 => \init_state_r[0]_i_32_n_0\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r[5]_i_24_n_0\, + O => \init_state_r[0]_i_23_n_0\ + ); +\init_state_r[0]_i_25\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000AAAAAAAAAAA8" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => pi_dqs_found_rank_done, + I2 => \^prech_req_posedge_r_reg_0\, + I3 => pi_dqs_found_done, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => cnt_cmd_done_r, + O => \init_state_r[0]_i_25_n_0\ + ); +\init_state_r[0]_i_27\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0FFF0F0F0F8F0F" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \init_state_r[0]_i_33_n_0\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r[5]_i_12_n_0\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[0]_i_27_n_0\ + ); +\init_state_r[0]_i_28\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000D0CCDDCCDD" + ) + port map ( + I0 => \init_state_r[0]_i_34_n_0\, + I1 => \init_state_r[0]_i_35_n_0\, + I2 => complex_row1_wr_done, + I3 => \init_state_r[1]_i_22_n_0\, + I4 => \^one_rank.stg1_wr_done_reg_0\, + I5 => \init_state_r[4]_i_30_n_0\, + O => \init_state_r[0]_i_28_n_0\ + ); +\init_state_r[0]_i_29\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF40E0FFFF" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => detect_pi_found_dqs_i_2_n_0, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \init_state_r[0]_i_36_n_0\, + O => \init_state_r[0]_i_29_n_0\ + ); +\init_state_r[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF15550000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r[0]_i_8_n_0\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r[0]_i_9_n_0\, + I5 => \init_state_r[0]_i_10_n_0\, + O => \init_state_r[0]_i_3_n_0\ + ); +\init_state_r[0]_i_30\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF44F4" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r[4]_i_28_n_0\, + I2 => D(3), + I3 => \^rdlvl_stg1_done_r1_reg_0\, + I4 => \^prech_req_posedge_r_reg_0\, + O => \init_state_r[0]_i_30_n_0\ + ); +\init_state_r[0]_i_31\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAA8A88" + ) + port map ( + I0 => detect_pi_found_dqs_i_2_n_0, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => wrcal_prech_req, + I3 => cnt_cmd_done_r, + I4 => burst_addr_r_reg_0, + I5 => \^prech_req_posedge_r_reg_0\, + O => \init_state_r[0]_i_31_n_0\ + ); +\init_state_r[0]_i_32\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1111111111111110" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => wrlvl_byte_redo, + I3 => \^prech_req_posedge_r_reg_0\, + I4 => burst_addr_r_reg_0, + I5 => wrcal_resume_r, + O => \init_state_r[0]_i_32_n_0\ + ); +\init_state_r[0]_i_33\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => reg_ctrl_cnt_r_reg(0), + I1 => reg_ctrl_cnt_r_reg(1), + I2 => reg_ctrl_cnt_r_reg(3), + I3 => reg_ctrl_cnt_r_reg(2), + O => \init_state_r[0]_i_33_n_0\ + ); +\init_state_r[0]_i_34\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => D(3), + O => \init_state_r[0]_i_34_n_0\ + ); +\init_state_r[0]_i_35\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF4F" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => D(3), + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[0]_i_35_n_0\ + ); +\init_state_r[0]_i_36\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => D(3), + O => \init_state_r[0]_i_36_n_0\ + ); +\init_state_r[0]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"888AAAAA88888888" + ) + port map ( + I0 => \init_state_r[5]_i_12_n_0\, + I1 => \init_state_r[0]_i_11_n_0\, + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => complex_sample_cnt_inc_i_2_n_0, + I4 => \init_state_r[0]_i_12_n_0\, + I5 => prech_req_posedge_r_i_2_n_0, + O => \init_state_r[0]_i_4_n_0\ + ); +\init_state_r[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF33303322" + ) + port map ( + I0 => \init_state_r[0]_i_13_n_0\, + I1 => \init_state_r[0]_i_14_n_0\, + I2 => \init_state_r[0]_i_15_n_0\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => detect_pi_found_dqs_i_3_n_0, + O => \init_state_r[0]_i_5_n_0\ + ); +\init_state_r[0]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAEEEAEEFFFFEAEE" + ) + port map ( + I0 => \init_state_r[0]_i_16_n_0\, + I1 => \init_state_r[0]_i_17_n_0\, + I2 => \init_state_r[0]_i_18_n_0\, + I3 => \init_state_r[0]_i_19_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I5 => \init_state_r[0]_i_20_n_0\, + O => \init_state_r[0]_i_6_n_0\ + ); +\init_state_r[0]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABAAAAAAABAAAB" + ) + port map ( + I0 => \wrcal_reads[7]_i_4_n_0\, + I1 => \init_state_r[0]_i_21_n_0\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r[0]_i_22_n_0\, + I4 => \init_state_r[0]_i_23_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + O => \init_state_r[0]_i_7_n_0\ + ); +\init_state_r[0]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => wrlvl_rank_done_r7, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => cnt_dllk_zqinit_done_r, + O => \init_state_r[0]_i_8_n_0\ + ); +\init_state_r[0]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF05F5FCFC" + ) + port map ( + I0 => cnt_txpr_done_r, + I1 => \init_state_r[0]_i_3_0\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => cnt_cmd_done_r, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[0]_i_9_n_0\ + ); +\init_state_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEFFAEFFAEAEAEFF" + ) + port map ( + I0 => \init_state_r[1]_i_2_n_0\, + I1 => \init_state_r[1]_i_3_n_0\, + I2 => \init_state_r[1]_i_4_n_0\, + I3 => \init_state_r[1]_i_5_n_0\, + I4 => \init_state_r[1]_i_6_n_0\, + I5 => \init_state_r[1]_i_7_n_0\, + O => \init_state_r[1]_i_1_n_0\ + ); +\init_state_r[1]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFBAA0000" + ) + port map ( + I0 => prech_req_posedge_r_i_2_n_0, + I1 => \init_state_r[1]_i_3_1\, + I2 => \init_state_r_reg[4]_0\, + I3 => \init_state_r[4]_i_22_n_0\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I5 => \init_state_r[1]_i_28_n_0\, + O => \init_state_r[1]_i_10_n_0\ + ); +\init_state_r[1]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFBAAAA" + ) + port map ( + I0 => \init_state_r[1]_i_29_n_0\, + I1 => num_reads(0), + I2 => num_reads(1), + I3 => num_reads(2), + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r[1]_i_30_n_0\, + O => \init_state_r[1]_i_11_n_0\ + ); +\init_state_r[1]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA08AA08AA080808" + ) + port map ( + I0 => \init_state_r[5]_i_12_n_0\, + I1 => \init_state_r[1]_i_4_0\, + I2 => \init_state_r[1]_i_32_n_0\, + I3 => prech_req_posedge_r_i_2_n_0, + I4 => \init_state_r[4]_i_41_n_0\, + I5 => \init_state_r[4]_i_40_n_0\, + O => \init_state_r[1]_i_12_n_0\ + ); +\init_state_r[1]_i_13\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF34343404" + ) + port map ( + I0 => \init_state_r[1]_i_33_n_0\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r[1]_i_34_n_0\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \init_state_r[1]_i_13_n_0\ + ); +\init_state_r[1]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7777FFFF7F77FFFF" + ) + port map ( + I0 => \init_state_r[5]_i_12_n_0\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => cnt_cmd_done_r, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => reset_rd_addr_r1, + O => \init_state_r[1]_i_14_n_0\ + ); +\init_state_r[1]_i_15\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB000FFF00000FFF" + ) + port map ( + I0 => cnt_init_mr_done_r, + I1 => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_1\, + I2 => cnt_txpr_done_r, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => cnt_cmd_done_r, + O => \init_state_r[1]_i_15_n_0\ + ); +\init_state_r[1]_i_16\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000155550001" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => burst_addr_r_reg_0, + I2 => \^prech_req_posedge_r_reg_0\, + I3 => wrlvl_byte_redo, + I4 => wrcal_resume_r, + I5 => wrcal_final_chk, + O => \init_state_r[1]_i_16_n_0\ + ); +\init_state_r[1]_i_17\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BFBEAAAAFFBEAAAA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r[3]_i_7_n_0\, + O => \init_state_r[1]_i_17_n_0\ + ); +\init_state_r[1]_i_18\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF4FFF4FFF4" + ) + port map ( + I0 => \init_state_r[5]_i_20_n_0\, + I1 => \init_state_r[4]_i_17_n_0\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => p_15_in(3), + I5 => ddr3_lm_done_r_i_2_n_0, + O => \init_state_r[1]_i_18_n_0\ + ); +\init_state_r[1]_i_19\: unisim.vcomponents.LUT5 + generic map( + INIT => X"08080C08" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => D(3), + I4 => \^rdlvl_stg1_done_r1_reg_0\, + O => \init_state_r[1]_i_19_n_0\ + ); +\init_state_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C5C4C4C400000000" + ) + port map ( + I0 => \init_state_r[5]_i_17_n_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \^prech_req_posedge_r_reg_0\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => init_state_r(6), + O => \init_state_r[1]_i_2_n_0\ + ); +\init_state_r[1]_i_20\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \init_state_r[4]_i_28_n_0\, + I1 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[1]_i_20_n_0\ + ); +\init_state_r[1]_i_21\: unisim.vcomponents.LUT3 + generic map( + INIT => X"45" + ) + port map ( + I0 => \^prech_req_posedge_r_reg_0\, + I1 => \^rdlvl_stg1_done_r1_reg_0\, + I2 => D(3), + O => \init_state_r[1]_i_21_n_0\ + ); +\init_state_r[1]_i_22\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => complex_wait_cnt_reg(2), + I1 => complex_wait_cnt_reg(3), + I2 => complex_wait_cnt_reg(0), + I3 => complex_wait_cnt_reg(1), + O => \init_state_r[1]_i_22_n_0\ + ); +\init_state_r[1]_i_23\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAABAAAAAAAAAA" + ) + port map ( + I0 => \init_state_r[5]_i_26_n_0\, + I1 => wr_victim_inc_i_2_n_0, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[1]_i_23_n_0\ + ); +\init_state_r[1]_i_24\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFAAFFAAEFFAFFFA" + ) + port map ( + I0 => \init_state_r[1]_i_35_n_0\, + I1 => \^prech_req_posedge_r_reg_0\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \^one_rank.stg1_wr_done_reg_0\, + I5 => \init_state_r[1]_i_22_n_0\, + O => \init_state_r[1]_i_24_n_0\ + ); +\init_state_r[1]_i_25\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BAABAAAB" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => cnt_cmd_done_r, + O => \init_state_r[1]_i_25_n_0\ + ); +\init_state_r[1]_i_28\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3E000000FFFFFFFF" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \init_state_r[1]_i_28_n_0\ + ); +\init_state_r[1]_i_29\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABAAAAAAABAAAB" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => rdlvl_stg1_rank_done, + I3 => \^prech_req_posedge_r_reg_0\, + I4 => \^rdlvl_stg1_done_r1_reg_0\, + I5 => D(3), + O => \init_state_r[1]_i_29_n_0\ + ); +\init_state_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0F0FDF0F0F0FDFF" + ) + port map ( + I0 => \init_state_r[1]_i_8_n_0\, + I1 => \init_state_r[1]_i_9_n_0\, + I2 => \init_state_r[1]_i_10_n_0\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r[1]_i_11_n_0\, + O => \init_state_r[1]_i_3_n_0\ + ); +\init_state_r[1]_i_30\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44444440CCCCCCCC" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => pi_dqs_found_rank_done, + I3 => \^prech_req_posedge_r_reg_0\, + I4 => pi_dqs_found_done, + I5 => cnt_cmd_done_r, + O => \init_state_r[1]_i_30_n_0\ + ); +\init_state_r[1]_i_32\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFBFFFBFFFBFBFBF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => cnt_cmd_done_r, + I3 => \^pi_calib_done\, + I4 => D(3), + I5 => \^one_rank.stg1_wr_done_reg_0\, + O => \init_state_r[1]_i_32_n_0\ + ); +\init_state_r[1]_i_33\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FB0B0F0F" + ) + port map ( + I0 => \^mem_init_done_r\, + I1 => cnt_dllk_zqinit_done_r, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => wrlvl_rank_done_r7, + I4 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[1]_i_33_n_0\ + ); +\init_state_r[1]_i_34\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => cnt_cmd_done_r, + O => \init_state_r[1]_i_34_n_0\ + ); +\init_state_r[1]_i_35\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0040FFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => D(3), + I3 => \^rdlvl_stg1_done_r1_reg_0\, + I4 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[1]_i_35_n_0\ + ); +\init_state_r[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABAAAAAAABAAABAA" + ) + port map ( + I0 => detect_pi_found_dqs_i_3_n_0, + I1 => \init_state_r[1]_i_12_n_0\, + I2 => \init_state_r[1]_i_13_n_0\, + I3 => \init_state_r[1]_i_14_n_0\, + I4 => \init_state_r[1]_i_15_n_0\, + I5 => detect_pi_found_dqs_i_2_n_0, + O => \init_state_r[1]_i_4_n_0\ + ); +\init_state_r[1]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFEFAAAAAAAA" + ) + port map ( + I0 => \wrcal_reads[7]_i_4_n_0\, + I1 => \init_state_r[1]_i_16_n_0\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r[1]_i_17_n_0\, + I5 => \init_state_r[1]_i_18_n_0\, + O => \init_state_r[1]_i_5_n_0\ + ); +\init_state_r[1]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55544444FFFFFFFF" + ) + port map ( + I0 => \init_state_r[1]_i_19_n_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => complex_sample_cnt_inc_i_2_n_0, + I3 => \init_state_r[1]_i_20_n_0\, + I4 => \init_state_r[1]_i_21_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + O => \init_state_r[1]_i_6_n_0\ + ); +\init_state_r[1]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D0FFD0FFFFFFD0FF" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => \init_state_r[1]_i_23_n_0\, + I2 => \init_state_r[5]_i_12_n_0\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r[1]_i_24_n_0\, + I5 => \init_state_r[1]_i_25_n_0\, + O => \init_state_r[1]_i_7_n_0\ + ); +\init_state_r[1]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"15151500FFFFFFFF" + ) + port map ( + I0 => \init_state_r[4]_i_32_n_0\, + I1 => \init_state_r[4]_i_34_n_0\, + I2 => \init_state_r[4]_i_35_n_0\, + I3 => \init_state_r[4]_i_37_n_0\, + I4 => \init_state_r[1]_i_3_0\, + I5 => prech_req_posedge_r_i_2_n_0, + O => \init_state_r[1]_i_8_n_0\ + ); +\init_state_r[1]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00F2" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => ddr2_pre_flag_r_reg_n_0, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[1]_i_9_n_0\ + ); +\init_state_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8F" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => init_state_r(6), + I2 => \init_state_r[2]_i_2_n_0\, + O => \init_state_r[2]_i_1_n_0\ + ); +\init_state_r[2]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55555575" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I4 => wr_victim_inc_i_2_n_0, + O => \init_state_r[2]_i_10_n_0\ + ); +\init_state_r[2]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFFFBFBF3F3F3F3" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \^rdlvl_stg1_done_r1_reg_0\, + I4 => D(3), + I5 => prech_req_posedge_r_i_2_n_0, + O => \init_state_r[2]_i_11_n_0\ + ); +\init_state_r[2]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44454444FFFFFFFF" + ) + port map ( + I0 => \init_state_r[2]_i_30_n_0\, + I1 => \init_state_r[5]_i_26_n_0\, + I2 => wr_victim_inc_i_2_n_0, + I3 => \init_state_r[4]_i_29_n_0\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r[5]_i_12_n_0\, + O => \init_state_r[2]_i_12_n_0\ + ); +\init_state_r[2]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[2]_i_13_n_0\ + ); +\init_state_r[2]_i_14\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => p_15_in(3), + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[2]_i_14_n_0\ + ); +\init_state_r[2]_i_15\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00FFFF0FEEFFFF" + ) + port map ( + I0 => wrcal_resume_r, + I1 => \init_state_r[4]_i_4_0\, + I2 => \init_state_r[5]_i_24_n_0\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[2]_i_15_n_0\ + ); +\init_state_r[2]_i_16\: unisim.vcomponents.LUT6 + generic map( + INIT => X"080C000C0800000C" + ) + port map ( + I0 => \init_state_r[3]_i_7_n_0\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => ddr3_lm_done_r_i_2_n_0, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r[2]_i_31_n_0\, + O => \init_state_r[2]_i_16_n_0\ + ); +\init_state_r[2]_i_17\: unisim.vcomponents.LUT5 + generic map( + INIT => X"01000000" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[2]_i_17_n_0\ + ); +\init_state_r[2]_i_18\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => reset_rd_addr_r1, + O => \init_state_r[2]_i_18_n_0\ + ); +\init_state_r[2]_i_19\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000DDFFF0FF" + ) + port map ( + I0 => \^pi_calib_done\, + I1 => \init_state_r[2]_i_5_0\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => cnt_cmd_done_r, + I5 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[2]_i_19_n_0\ + ); +\init_state_r[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000D000D000D0000" + ) + port map ( + I0 => \init_state_r[2]_i_3_n_0\, + I1 => \init_state_r[2]_i_4_n_0\, + I2 => \init_state_r[2]_i_5_n_0\, + I3 => \init_state_r[2]_i_6_n_0\, + I4 => detect_pi_found_dqs_i_3_n_0, + I5 => \init_state_r[2]_i_7_n_0\, + O => \init_state_r[2]_i_2_n_0\ + ); +\init_state_r[2]_i_20\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFEFE00FFFFFFFF" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => \init_state_r[4]_i_29_n_0\, + I2 => wr_victim_inc_i_2_n_0, + I3 => \init_state_r[4]_i_40_n_0\, + I4 => \init_state_r[4]_i_41_n_0\, + I5 => prech_req_posedge_r_i_2_n_0, + O => \init_state_r[2]_i_20_n_0\ + ); +\init_state_r[2]_i_21\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEEEEEEEEEEEEEEE" + ) + port map ( + I0 => detect_pi_found_dqs_i_3_n_0, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => wrlvl_rank_done_r7, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[2]_i_21_n_0\ + ); +\init_state_r[2]_i_22\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E0E0E0E0E0FFE0E0" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \^wrlvl_done_r1\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \^mem_init_done_r\, + I4 => cnt_dllk_zqinit_done_r, + I5 => \init_state_r[6]_i_4_n_0\, + O => \init_state_r[2]_i_22_n_0\ + ); +\init_state_r[2]_i_23\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888888808080" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => ddr3_lm_done_r_i_2_n_0, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => D(3), + I4 => pi_dqs_found_done, + I5 => cnt_init_mr_done_r, + O => \init_state_r[2]_i_23_n_0\ + ); +\init_state_r[2]_i_24\: unisim.vcomponents.LUT6 + generic map( + INIT => X"30FF3000BAFFBAFF" + ) + port map ( + I0 => cnt_init_af_done_r, + I1 => \init_state_r[4]_i_34_n_0\, + I2 => \init_state_r[2]_i_7_0\, + I3 => \init_state_r[4]_i_37_n_0\, + I4 => \init_state_r[2]_i_7_1\, + I5 => \^mem_init_done_r\, + O => \init_state_r[2]_i_24_n_0\ + ); +\init_state_r[2]_i_25\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7FF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[2]_i_25_n_0\ + ); +\init_state_r[2]_i_26\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA00808888" + ) + port map ( + I0 => \init_state_r[2]_i_34_n_0\, + I1 => \init_state_r[2]_i_35_n_0\, + I2 => \init_state_r[2]_i_36_n_0\, + I3 => \init_state_r[2]_i_37_n_0\, + I4 => \init_state_r[2]_i_38_n_0\, + I5 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[2]_i_26_n_0\ + ); +\init_state_r[2]_i_27\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[2]_i_27_n_0\ + ); +\init_state_r[2]_i_28\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55D55555" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => cnt_cmd_done_r, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[2]_i_28_n_0\ + ); +\init_state_r[2]_i_29\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D555555515555555" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => complex_wait_cnt_reg(2), + I2 => complex_wait_cnt_reg(3), + I3 => complex_wait_cnt_reg(0), + I4 => complex_wait_cnt_reg(1), + I5 => \^one_rank.stg1_wr_done_reg_0\, + O => \init_state_r[2]_i_29_n_0\ + ); +\init_state_r[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFFAEFFFFFFFF" + ) + port map ( + I0 => \init_state_r[2]_i_8_n_0\, + I1 => \init_state_r[2]_i_9_n_0\, + I2 => \init_state_r[2]_i_10_n_0\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r[2]_i_11_n_0\, + I5 => \init_state_r[2]_i_12_n_0\, + O => \init_state_r[2]_i_3_n_0\ + ); +\init_state_r[2]_i_30\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => D(3), + I2 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[2]_i_30_n_0\ + ); +\init_state_r[2]_i_31\: unisim.vcomponents.LUT3 + generic map( + INIT => X"07" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[2]_i_31_n_0\ + ); +\init_state_r[2]_i_34\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF5F5FDF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[2]_i_34_n_0\ + ); +\init_state_r[2]_i_35\: unisim.vcomponents.LUT4 + generic map( + INIT => X"DFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => cnt_cmd_done_r, + I3 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[2]_i_35_n_0\ + ); +\init_state_r[2]_i_36\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg[4]_0\, + O => \init_state_r[2]_i_36_n_0\ + ); +\init_state_r[2]_i_37\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \^ddr3_lm_done_r\, + I1 => pi_dqs_found_done, + I2 => D(3), + I3 => \^wrlvl_done_r1\, + I4 => burst_addr_r_reg_0, + O => \init_state_r[2]_i_37_n_0\ + ); +\init_state_r[2]_i_38\: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[2]_i_38_n_0\ + ); +\init_state_r[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF4500" + ) + port map ( + I0 => \init_state_r[2]_i_13_n_0\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r[2]_i_14_n_0\, + I3 => \init_state_r[2]_i_15_n_0\, + I4 => \init_state_r[2]_i_16_n_0\, + I5 => \wrcal_reads[7]_i_4_n_0\, + O => \init_state_r[2]_i_4_n_0\ + ); +\init_state_r[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA2000AAAAAAAA" + ) + port map ( + I0 => \init_state_r[2]_i_17_n_0\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r[2]_i_18_n_0\, + I4 => \init_state_r[2]_i_19_n_0\, + I5 => \init_state_r[2]_i_20_n_0\, + O => \init_state_r[2]_i_5_n_0\ + ); +\init_state_r[2]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"11101110FF101110" + ) + port map ( + I0 => \init_state_r[2]_i_21_n_0\, + I1 => \init_state_r[2]_i_22_n_0\, + I2 => \init_state_r[2]_i_23_n_0\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => complex_sample_cnt_inc_i_2_n_0, + I5 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + O => \init_state_r[2]_i_6_n_0\ + ); +\init_state_r[2]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF450000FF45FF45" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r[2]_i_24_n_0\, + I2 => cnt_cmd_done_r, + I3 => \init_state_r[2]_i_25_n_0\, + I4 => \init_state_r[2]_i_26_n_0\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \init_state_r[2]_i_7_n_0\ + ); +\init_state_r[2]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8888888A8A8A8A8A" + ) + port map ( + I0 => \init_state_r[2]_i_27_n_0\, + I1 => \init_state_r[2]_i_28_n_0\, + I2 => \init_state_r[1]_i_35_n_0\, + I3 => \^prech_req_posedge_r_reg_0\, + I4 => \init_state_r[2]_i_29_n_0\, + I5 => ddr3_lm_done_r_i_2_n_0, + O => \init_state_r[2]_i_8_n_0\ + ); +\init_state_r[2]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2022202200003033" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => \^prech_req_posedge_r_reg_0\, + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => D(3), + I4 => \init_state_r[4]_i_28_n_0\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[2]_i_9_n_0\ + ); +\init_state_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF1110" + ) + port map ( + I0 => \wrcal_reads[7]_i_4_n_0\, + I1 => \init_state_r[3]_i_2_n_0\, + I2 => \init_state_r[3]_i_3_n_0\, + I3 => \init_state_r[3]_i_4_n_0\, + I4 => \init_state_r[3]_i_5_n_0\, + I5 => \init_state_r[3]_i_6_n_0\, + O => \init_state_r[3]_i_1_n_0\ + ); +\init_state_r[3]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BAFFFFFFAAAAFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \^rdlvl_stg1_done_r1_reg_0\, + I2 => D(3), + I3 => \init_state_r[1]_i_22_n_0\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => prech_req_posedge_r_i_2_n_0, + O => \init_state_r[3]_i_10_n_0\ + ); +\init_state_r[3]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1111111111101111" + ) + port map ( + I0 => prbs_rdlvl_done_pulse0, + I1 => \^prech_req_posedge_r_reg_0\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => complex_sample_cnt_inc_i_2_n_0, + I5 => \init_state_r[4]_i_28_n_0\, + O => \init_state_r[3]_i_11_n_0\ + ); +\init_state_r[3]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5510FFFF55115511" + ) + port map ( + I0 => \init_state_r[4]_i_30_n_0\, + I1 => \^rdlvl_stg1_done_r1_reg_0\, + I2 => D(3), + I3 => \init_state_r[6]_i_4_n_0\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r[1]_i_22_n_0\, + O => \init_state_r[3]_i_12_n_0\ + ); +\init_state_r[3]_i_13\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0444" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[3]_i_13_n_0\ + ); +\init_state_r[3]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FFFF8DDD0000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r[4]_i_32_n_0\, + I2 => cnt_cmd_done_r, + I3 => ddr2_pre_flag_r_reg_n_0, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[3]_i_14_n_0\ + ); +\init_state_r[3]_i_15\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00BF0000FFFFFFFF" + ) + port map ( + I0 => \init_state_r[3]_i_18_n_0\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r[4]_i_38_n_0\, + I3 => \init_state_r[3]_i_19_n_0\, + I4 => \init_state_r[3]_i_20_n_0\, + I5 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[3]_i_15_n_0\ + ); +\init_state_r[3]_i_16\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5400540044005400" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r[3]_i_21_n_0\, + I2 => \init_state_r[3]_i_22_n_0\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => cnt_cmd_done_r, + I5 => reset_rd_addr_r1, + O => \init_state_r[3]_i_16_n_0\ + ); +\init_state_r[3]_i_17\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ABAAAAAA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \^prech_req_posedge_r_reg_0\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[3]_i_17_n_0\ + ); +\init_state_r[3]_i_18\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[4]\, + O => \init_state_r[3]_i_18_n_0\ + ); +\init_state_r[3]_i_19\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000F08800000000" + ) + port map ( + I0 => cnt_dllk_zqinit_done_r, + I1 => \^mem_init_done_r\, + I2 => wrlvl_rank_done_r7, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r[2]_i_13_n_0\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[3]_i_19_n_0\ + ); +\init_state_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BB3FFFFF" + ) + port map ( + I0 => \init_state_r[3]_i_7_n_0\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => cnt_cmd_done_r, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r[3]_i_8_n_0\, + O => \init_state_r[3]_i_2_n_0\ + ); +\init_state_r[3]_i_20\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF13FFFFFFFFFFFF" + ) + port map ( + I0 => \init_state_r[0]_i_5_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => cnt_cmd_done_r, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[3]_i_20_n_0\ + ); +\init_state_r[3]_i_21\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40FF55FF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r[2]_i_5_0\, + I2 => \^pi_calib_done\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[3]_i_21_n_0\ + ); +\init_state_r[3]_i_22\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[3]_i_22_n_0\ + ); +\init_state_r[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000080A0A0A0A0" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => D(3), + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r[3]_i_9_n_0\, + O => \init_state_r[3]_i_3_n_0\ + ); +\init_state_r[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"54FF54FFFFFF54FF" + ) + port map ( + I0 => \init_state_r[3]_i_10_n_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r[3]_i_11_n_0\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I5 => \init_state_r[3]_i_12_n_0\, + O => \init_state_r[3]_i_4_n_0\ + ); +\init_state_r[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555545445555" + ) + port map ( + I0 => detect_pi_found_dqs_i_3_n_0, + I1 => \init_state_r[3]_i_13_n_0\, + I2 => \init_state_r[3]_i_14_n_0\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I4 => \init_state_r[3]_i_15_n_0\, + I5 => \init_state_r[3]_i_16_n_0\, + O => \init_state_r[3]_i_5_n_0\ + ); +\init_state_r[3]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AE00AE000000AA00" + ) + port map ( + I0 => \init_state_r[3]_i_17_n_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r[5]_i_17_n_0\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[3]_i_6_n_0\ + ); +\init_state_r[3]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => oclk_wr_cnt_reg(3), + I1 => oclk_wr_cnt_reg(2), + I2 => oclk_wr_cnt_reg(0), + I3 => oclk_wr_cnt_reg(1), + O => \init_state_r[3]_i_7_n_0\ + ); +\init_state_r[3]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BEBAFABA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[3]_i_8_n_0\ + ); +\init_state_r[3]_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAFBAA" + ) + port map ( + I0 => \init_state_r[5]_i_26_n_0\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => complex_sample_cnt_inc_i_2_n_0, + I3 => \init_state_r[1]_i_22_n_0\, + I4 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[3]_i_9_n_0\ + ); +\init_state_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAEAEAEFFFFAEFF" + ) + port map ( + I0 => \init_state_r[4]_i_2_n_0\, + I1 => \init_state_r[4]_i_3_n_0\, + I2 => \init_state_r[4]_i_4_n_0\, + I3 => \init_state_r[4]_i_5_n_0\, + I4 => \init_state_r[4]_i_6_n_0\, + I5 => \init_state_r[4]_i_7_n_0\, + O => \init_state_r[4]_i_1_n_0\ + ); +\init_state_r[4]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0EFE0EFE0EFEFFFF" + ) + port map ( + I0 => \init_state_r[4]_i_28_n_0\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r[1]_i_22_n_0\, + I4 => wr_victim_inc_i_2_n_0, + I5 => \init_state_r[4]_i_29_n_0\, + O => \init_state_r[4]_i_10_n_0\ + ); +\init_state_r[4]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEEEFEEEFFFFFEEE" + ) + port map ( + I0 => \^prech_req_posedge_r_reg_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => D(3), + I5 => \^rdlvl_stg1_done_r1_reg_0\, + O => \init_state_r[4]_i_11_n_0\ + ); +\init_state_r[4]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A0A0000FACA0000" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => D(3), + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r[5]_i_12_n_0\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[4]_i_12_n_0\ + ); +\init_state_r[4]_i_13\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55555555FDFFFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r[1]_i_22_n_0\, + I2 => \^one_rank.stg1_wr_done_reg_0\, + I3 => \init_state_r[4]_i_30_n_0\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[4]_i_13_n_0\ + ); +\init_state_r[4]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000004044444444" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r[5]_i_12_n_0\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r[4]_i_29_n_0\, + I4 => wr_victim_inc_i_2_n_0, + I5 => \init_state_r[0]_i_19_n_0\, + O => \init_state_r[4]_i_14_n_0\ + ); +\init_state_r[4]_i_15\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0020022200200020" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r[5]_i_24_n_0\, + I4 => wrcal_resume_r, + I5 => \init_state_r[4]_i_4_0\, + O => \init_state_r[4]_i_15_n_0\ + ); +\init_state_r[4]_i_16\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[4]_i_16_n_0\ + ); +\init_state_r[4]_i_17\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF11F1" + ) + port map ( + I0 => \^prech_req_posedge_r_reg_0\, + I1 => burst_addr_r_reg_0, + I2 => cnt_cmd_done_r, + I3 => wrcal_prech_req, + I4 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[4]_i_17_n_0\ + ); +\init_state_r[4]_i_18\: unisim.vcomponents.LUT6 + generic map( + INIT => X"58F8FFFFFFFFFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r[3]_i_7_n_0\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[4]_i_18_n_0\ + ); +\init_state_r[4]_i_19\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => init_state_r(6), + O => \init_state_r[4]_i_19_n_0\ + ); +\init_state_r[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF000000F4F00000" + ) + port map ( + I0 => \init_state_r[5]_i_17_n_0\, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r[4]_i_8_n_0\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[4]_i_2_n_0\ + ); +\init_state_r[4]_i_20\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AABAAABAFFFFAABA" + ) + port map ( + I0 => \init_state_r[4]_i_32_n_0\, + I1 => \init_state_r[4]_i_33_n_0\, + I2 => \init_state_r[4]_i_34_n_0\, + I3 => \init_state_r[4]_i_35_n_0\, + I4 => \init_state_r[0]_i_15_0\, + I5 => \init_state_r[4]_i_37_n_0\, + O => \init_state_r[4]_i_20_n_0\ + ); +\init_state_r[4]_i_21\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFDFDDDDDDDD" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => detect_pi_found_dqs_i_2_n_0, + I2 => cnt_cmd_done_r, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r[4]_i_38_n_0\, + I5 => \init_state_r[4]_i_39_n_0\, + O => \init_state_r[4]_i_21_n_0\ + ); +\init_state_r[4]_i_22\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[4]_i_22_n_0\ + ); +\init_state_r[4]_i_23\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \^ddr3_lm_done_r\, + I1 => pi_dqs_found_done, + I2 => D(3), + I3 => \^wrlvl_done_r1\, + I4 => burst_addr_r_reg_0, + O => \init_state_r[4]_i_23_n_0\ + ); +\init_state_r[4]_i_24\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FDFDFD00FFFFFFFF" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => \init_state_r[4]_i_29_n_0\, + I2 => wr_victim_inc_i_2_n_0, + I3 => \init_state_r[4]_i_40_n_0\, + I4 => \init_state_r[4]_i_41_n_0\, + I5 => prech_req_posedge_r_i_2_n_0, + O => \init_state_r[4]_i_24_n_0\ + ); +\init_state_r[4]_i_25\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF54101010" + ) + port map ( + I0 => \init_state_r[6]_i_4_n_0\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r[4]_i_7_0\, + I4 => \init_state_r[4]_i_43_n_0\, + I5 => \init_state_r[4]_i_44_n_0\, + O => \init_state_r[4]_i_25_n_0\ + ); +\init_state_r[4]_i_26\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF8000FFFF0000" + ) + port map ( + I0 => \^wrlvl_done_r1\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + O => \init_state_r[4]_i_26_n_0\ + ); +\init_state_r[4]_i_27\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8F8FFF00DFDFFFFF" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_1\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r[6]_i_10_n_0\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \init_state_r[4]_i_27_n_0\ + ); +\init_state_r[4]_i_28\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000004" + ) + port map ( + I0 => complex_num_reads_dec(1), + I1 => complex_num_reads_dec(0), + I2 => D(3), + I3 => complex_row0_rd_done, + I4 => complex_num_reads_dec(2), + I5 => complex_num_reads_dec(3), + O => \init_state_r[4]_i_28_n_0\ + ); +\init_state_r[4]_i_29\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FB" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + O => \init_state_r[4]_i_29_n_0\ + ); +\init_state_r[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFF54" + ) + port map ( + I0 => \init_state_r[4]_i_9_n_0\, + I1 => \init_state_r[4]_i_10_n_0\, + I2 => \init_state_r[4]_i_11_n_0\, + I3 => \init_state_r[4]_i_12_n_0\, + I4 => \init_state_r[4]_i_13_n_0\, + I5 => \init_state_r[4]_i_14_n_0\, + O => \init_state_r[4]_i_3_n_0\ + ); +\init_state_r[4]_i_30\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \^prech_req_posedge_r_reg_0\, + O => \init_state_r[4]_i_30_n_0\ + ); +\init_state_r[4]_i_32\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5D5D5D5D5D5DFF5D" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => cnt_init_af_done_r, + I2 => \^mem_init_done_r\, + I3 => pi_dqs_found_done, + I4 => \^wrlvl_done_r1\, + I5 => wrlvl_byte_redo, + O => \init_state_r[4]_i_32_n_0\ + ); +\init_state_r[4]_i_33\: unisim.vcomponents.LUT3 + generic map( + INIT => X"D0" + ) + port map ( + I0 => \^wrlvl_done_r1\, + I1 => D(3), + I2 => pi_dqs_found_done, + O => \init_state_r[4]_i_33_n_0\ + ); +\init_state_r[4]_i_34\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => num_refresh_reg(0), + I1 => num_refresh_reg(1), + I2 => num_refresh_reg(3), + I3 => num_refresh_reg(2), + O => \init_state_r[4]_i_34_n_0\ + ); +\init_state_r[4]_i_35\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => D(3), + I1 => \^mem_init_done_r\, + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => pi_dqs_found_done, + O => \init_state_r[4]_i_35_n_0\ + ); +\init_state_r[4]_i_37\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F08FFFF0FFFFFFF" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => \^mem_init_done_r\, + I2 => D(3), + I3 => \^wrlvl_done_r1\, + I4 => pi_dqs_found_done, + I5 => wrlvl_byte_redo, + O => \init_state_r[4]_i_37_n_0\ + ); +\init_state_r[4]_i_38\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFEF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => reg_ctrl_cnt_r_reg(2), + I2 => reg_ctrl_cnt_r_reg(3), + I3 => reg_ctrl_cnt_r_reg(1), + I4 => reg_ctrl_cnt_r_reg(0), + O => \init_state_r[4]_i_38_n_0\ + ); +\init_state_r[4]_i_39\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0888" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[4]_i_39_n_0\ + ); +\init_state_r[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAABBABAAAAAAAA" + ) + port map ( + I0 => \wrcal_reads[7]_i_4_n_0\, + I1 => \init_state_r[4]_i_15_n_0\, + I2 => \init_state_r[4]_i_16_n_0\, + I3 => \init_state_r[4]_i_17_n_0\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \init_state_r[4]_i_18_n_0\, + O => \init_state_r[4]_i_4_n_0\ + ); +\init_state_r[4]_i_40\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => complex_num_writes_dec_reg(2), + I1 => complex_num_writes_dec_reg(4), + I2 => complex_num_writes_dec_reg(3), + O => \init_state_r[4]_i_40_n_0\ + ); +\init_state_r[4]_i_41\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFF7F" + ) + port map ( + I0 => complex_num_writes_dec_reg(0), + I1 => D(3), + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => complex_row0_wr_done, + I4 => complex_num_writes_dec_reg(1), + O => \init_state_r[4]_i_41_n_0\ + ); +\init_state_r[4]_i_43\: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => \^pi_calib_done\, + I1 => D(3), + I2 => pi_dqs_found_done, + O => \init_state_r[4]_i_43_n_0\ + ); +\init_state_r[4]_i_44\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BA000000FE000000" + ) + port map ( + I0 => reset_rd_addr_r1, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \^rdlvl_stg1_done_r1_reg_0\, + O => \init_state_r[4]_i_44_n_0\ + ); +\init_state_r[4]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555D5D5555555DD" + ) + port map ( + I0 => \init_state_r[4]_i_19_n_0\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r[4]_i_20_n_0\, + I3 => ddr2_pre_flag_r_reg_n_0, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[4]_i_5_n_0\ + ); +\init_state_r[4]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5455555544444444" + ) + port map ( + I0 => detect_pi_found_dqs_i_3_n_0, + I1 => \init_state_r[4]_i_21_n_0\, + I2 => \init_state_r_reg[4]_0\, + I3 => \init_state_r[4]_i_22_n_0\, + I4 => \init_state_r[4]_i_23_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + O => \init_state_r[4]_i_6_n_0\ + ); +\init_state_r[4]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"020F0F0F020F0F00" + ) + port map ( + I0 => \init_state_r[4]_i_24_n_0\, + I1 => \init_state_r[4]_i_25_n_0\, + I2 => \init_state_r[4]_i_26_n_0\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r[4]_i_27_n_0\, + O => \init_state_r[4]_i_7_n_0\ + ); +\init_state_r[4]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E0" + ) + port map ( + I0 => \^prech_req_posedge_r_reg_0\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[4]_i_8_n_0\ + ); +\init_state_r[4]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45000000FFFFFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \^rdlvl_stg1_done_r1_reg_0\, + I2 => D(3), + I3 => \init_state_r[1]_i_22_n_0\, + I4 => prech_req_posedge_r_i_2_n_0, + I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + O => \init_state_r[4]_i_9_n_0\ + ); +\init_state_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF4444F444" + ) + port map ( + I0 => \init_state_r[5]_i_2_n_0\, + I1 => \init_state_r[5]_i_3_n_0\, + I2 => \init_state_r[5]_i_4_n_0\, + I3 => init_state_r(6), + I4 => \init_state_r[5]_i_5_n_0\, + I5 => \init_state_r[5]_i_6_n_0\, + O => \init_state_r[5]_i_1_n_0\ + ); +\init_state_r[5]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"005500770F55FF55" + ) + port map ( + I0 => \init_state_r[5]_i_22_n_0\, + I1 => \init_state_r[5]_i_23_n_0\, + I2 => \init_state_r[5]_i_24_n_0\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[5]_i_10_n_0\ + ); +\init_state_r[5]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F100F3F3F1F1F3F3" + ) + port map ( + I0 => \init_state_r[1]_i_22_n_0\, + I1 => \init_state_r[5]_i_25_n_0\, + I2 => \init_state_r[5]_i_26_n_0\, + I3 => \init_state_r[5]_i_27_n_0\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[5]_i_11_n_0\ + ); +\init_state_r[5]_i_12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[3]\, + O => \init_state_r[5]_i_12_n_0\ + ); +\init_state_r[5]_i_13\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF555D55555" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => detect_pi_found_dqs_i_2_n_0, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => cnt_cmd_done_r, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r[4]_i_16_n_0\, + O => \init_state_r[5]_i_13_n_0\ + ); +\init_state_r[5]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000077755575" + ) + port map ( + I0 => ddr3_lm_done_r_i_2_n_0, + I1 => \^prech_req_posedge_r_reg_0\, + I2 => \^one_rank.stg1_wr_done_reg_0\, + I3 => \init_state_r[1]_i_22_n_0\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r[5]_i_28_n_0\, + O => \init_state_r[5]_i_14_n_0\ + ); +\init_state_r[5]_i_15\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFBAAAAAAAA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => complex_sample_cnt_inc_i_2_n_0, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r[5]_i_29_n_0\, + I4 => \init_state_r[1]_i_20_n_0\, + I5 => \init_state_r[1]_i_21_n_0\, + O => \init_state_r[5]_i_15_n_0\ + ); +\init_state_r[5]_i_16\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F440000FFFFFFFF" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => D(3), + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r[1]_i_22_n_0\, + I4 => prech_req_posedge_r_i_2_n_0, + I5 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + O => \init_state_r[5]_i_16_n_0\ + ); +\init_state_r[5]_i_17\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => ocal_act_wait_cnt_reg(2), + I1 => ocal_act_wait_cnt_reg(0), + I2 => ocal_act_wait_cnt_reg(1), + I3 => ocal_act_wait_cnt_reg(3), + I4 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[5]_i_17_n_0\ + ); +\init_state_r[5]_i_18\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCECCCCCFCECCCC" + ) + port map ( + I0 => \init_state_r[6]_i_7_n_0\, + I1 => \init_state_r[5]_i_30_n_0\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r[5]_i_31_n_0\, + O => \init_state_r[5]_i_18_n_0\ + ); +\init_state_r[5]_i_19\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00020F0F0A020F0F" + ) + port map ( + I0 => \init_state_r[0]_i_12_n_0\, + I1 => \^rdlvl_stg1_done_r1_reg_0\, + I2 => \init_state_r[5]_i_32_n_0\, + I3 => complex_sample_cnt_inc_i_2_n_0, + I4 => prech_req_posedge_r_i_2_n_0, + I5 => \init_state_r_reg_n_0_[5]\, + O => \init_state_r[5]_i_19_n_0\ + ); +\init_state_r[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAEFAAAAAAEFAAEF" + ) + port map ( + I0 => \wrcal_reads[7]_i_4_n_0\, + I1 => \init_state_r[5]_i_7_n_0\, + I2 => \init_state_r[5]_i_8_n_0\, + I3 => \init_state_r[5]_i_9_n_0\, + I4 => \init_state_r[5]_i_10_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + O => \init_state_r[5]_i_2_n_0\ + ); +\init_state_r[5]_i_20\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAABAAAAAAAAAA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => wrcal_wr_cnt_reg(3), + I2 => wrcal_wr_cnt_reg(2), + I3 => wrcal_wr_cnt_reg(0), + I4 => wrcal_wr_cnt_reg(1), + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[5]_i_20_n_0\ + ); +\init_state_r[5]_i_21\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E0F0E0F0F0000000" + ) + port map ( + I0 => \init_state_r[3]_i_7_n_0\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r[5]_i_12_n_0\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => cnt_cmd_done_r, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[5]_i_21_n_0\ + ); +\init_state_r[5]_i_22\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEFEEEEEEEE" + ) + port map ( + I0 => wrcal_resume_r, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => wrlvl_byte_redo, + I3 => \^prech_req_posedge_r_reg_0\, + I4 => burst_addr_r_reg_0, + I5 => \init_state_r_reg_n_0_[5]\, + O => \init_state_r[5]_i_22_n_0\ + ); +\init_state_r[5]_i_23\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000002" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[0]\, + I1 => \init_state_r[5]_i_33_n_0\, + I2 => \wrcal_reads_reg_n_0_[4]\, + I3 => \wrcal_reads_reg_n_0_[2]\, + I4 => \wrcal_reads_reg_n_0_[7]\, + O => \init_state_r[5]_i_23_n_0\ + ); +\init_state_r[5]_i_24\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => pi_phase_locked_all_r4, + I1 => pi_phase_locked_all_r3, + O => \init_state_r[5]_i_24_n_0\ + ); +\init_state_r[5]_i_25\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000020" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I4 => wr_victim_inc_i_2_n_0, + O => \init_state_r[5]_i_25_n_0\ + ); +\init_state_r[5]_i_26\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAEEEAEA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \^prech_req_posedge_r_reg_0\, + I3 => complex_oclkdelay_calib_done_r1, + I4 => D(3), + O => \init_state_r[5]_i_26_n_0\ + ); +\init_state_r[5]_i_27\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => D(3), + O => \init_state_r[5]_i_27_n_0\ + ); +\init_state_r[5]_i_28\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00004F44FFFFFFFF" + ) + port map ( + I0 => \^rdlvl_stg1_done_r1_reg_0\, + I1 => D(3), + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r[1]_i_22_n_0\, + I4 => \init_state_r[6]_i_4_n_0\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + O => \init_state_r[5]_i_28_n_0\ + ); +\init_state_r[5]_i_29\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => complex_wait_cnt_reg(1), + I2 => complex_wait_cnt_reg(0), + I3 => complex_wait_cnt_reg(3), + I4 => complex_wait_cnt_reg(2), + O => \init_state_r[5]_i_29_n_0\ + ); +\init_state_r[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF4FFF4FFFFFFF4" + ) + port map ( + I0 => \init_state_r[5]_i_11_n_0\, + I1 => \init_state_r[5]_i_12_n_0\, + I2 => \init_state_r[5]_i_13_n_0\, + I3 => \init_state_r[5]_i_14_n_0\, + I4 => \init_state_r[5]_i_15_n_0\, + I5 => \init_state_r[5]_i_16_n_0\, + O => \init_state_r[5]_i_3_n_0\ + ); +\init_state_r[5]_i_30\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ABAAAAAAAAAAAAAA" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r[0]_i_8_n_0\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[5]_i_30_n_0\ + ); +\init_state_r[5]_i_31\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => cnt_cmd_done_r, + I1 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[5]_i_31_n_0\ + ); +\init_state_r[5]_i_32\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCCC4C400C004C40" + ) + port map ( + I0 => \init_state_r[4]_i_43_n_0\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => cnt_cmd_done_r, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => reset_rd_addr_r1, + O => \init_state_r[5]_i_32_n_0\ + ); +\init_state_r[5]_i_33\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[5]\, + I1 => \wrcal_reads_reg_n_0_[6]\, + I2 => \wrcal_reads_reg_n_0_[3]\, + I3 => \wrcal_reads_reg_n_0_[1]\, + O => \init_state_r[5]_i_33_n_0\ + ); +\init_state_r[5]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF444400C0" + ) + port map ( + I0 => \init_state_r[5]_i_17_n_0\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \^prech_req_posedge_r_reg_0\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[5]_i_4_n_0\ + ); +\init_state_r[5]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[5]\, + O => \init_state_r[5]_i_5_n_0\ + ); +\init_state_r[5]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BB0A0B0A" + ) + port map ( + I0 => \init_state_r[5]_i_18_n_0\, + I1 => \init_state_r[5]_i_19_n_0\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r[5]_i_12_n_0\, + I4 => ddr3_lm_done_r_i_2_n_0, + I5 => detect_pi_found_dqs_i_3_n_0, + O => \init_state_r[5]_i_6_n_0\ + ); +\init_state_r[5]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00005300FFFFFFFF" + ) + port map ( + I0 => p_15_in(3), + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => detect_pi_found_dqs_i_2_n_0, + O => \init_state_r[5]_i_7_n_0\ + ); +\init_state_r[5]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF88888F88" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => \init_state_r[4]_i_17_n_0\, + I2 => wrcal_prech_req, + I3 => cnt_cmd_done_r, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r[5]_i_20_n_0\, + O => \init_state_r[5]_i_8_n_0\ + ); +\init_state_r[5]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFEEEEEEEA" + ) + port map ( + I0 => \init_state_r[5]_i_21_n_0\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I2 => cnt_cmd_done_r, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \init_state_r[5]_i_9_n_0\ + ); +\init_state_r[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF444F4F4" + ) + port map ( + I0 => \init_state_r[6]_i_2_n_0\, + I1 => \init_state_r[6]_i_3_n_0\, + I2 => init_state_r(6), + I3 => \init_state_r[6]_i_4_n_0\, + I4 => \init_state_r[6]_i_5_n_0\, + I5 => \init_state_r[6]_i_6_n_0\, + O => \init_state_r[6]_i_1_n_0\ + ); +\init_state_r[6]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8888888" + ) + port map ( + I0 => cnt_txpr_done_r, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => ck_addr_cmd_delay_done, + I3 => \^cnt_pwron_cke_done_r\, + I4 => Q(0), + O => \init_state_r[6]_i_10_n_0\ + ); +\init_state_r[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"070F070F000F070F" + ) + port map ( + I0 => detect_pi_found_dqs_i_2_n_0, + I1 => \init_state_r[6]_i_7_n_0\, + I2 => \init_state_r[6]_i_8_n_0\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r[6]_i_9_n_0\, + O => \init_state_r[6]_i_2_n_0\ + ); +\init_state_r[6]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => init_state_r(6), + O => \init_state_r[6]_i_3_n_0\ + ); +\init_state_r[6]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + O => \init_state_r[6]_i_4_n_0\ + ); +\init_state_r[6]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^prech_req_posedge_r_reg_0\, + I1 => \init_state_r_reg_n_0_[2]\, + O => \init_state_r[6]_i_5_n_0\ + ); +\init_state_r[6]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \wrcal_reads[7]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \init_state_r[6]_i_6_n_0\ + ); +\init_state_r[6]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"3055" + ) + port map ( + I0 => \init_state_r[6]_i_10_n_0\, + I1 => cnt_cmd_done_r, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + O => \init_state_r[6]_i_7_n_0\ + ); +\init_state_r[6]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000080888000" + ) + port map ( + I0 => \init_state_r[5]_i_12_n_0\, + I1 => ddr3_lm_done_r_i_2_n_0, + I2 => \^rdlvl_stg1_done_r1_reg_0\, + I3 => cnt_cmd_done_r, + I4 => init_state_r(6), + I5 => reset_rd_addr_r1, + O => \init_state_r[6]_i_8_n_0\ + ); +\init_state_r[6]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFAFCFF000AFCF" + ) + port map ( + I0 => wrlvl_rank_done_r7, + I1 => cnt_dllk_zqinit_done_r, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => cnt_cmd_done_r, + O => \init_state_r[6]_i_9_n_0\ + ); +\init_state_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r[0]_i_1_n_0\, + Q => \init_state_r_reg_n_0_[0]\, + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r[1]_i_1_n_0\, + Q => \init_state_r_reg_n_0_[1]\, + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r[2]_i_1_n_0\, + Q => \init_state_r_reg_n_0_[2]\, + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r[3]_i_1_n_0\, + Q => \init_state_r_reg_n_0_[3]\, + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r[4]_i_1_n_0\, + Q => \init_state_r_reg_n_0_[4]\, + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r[5]_i_1_n_0\, + Q => \init_state_r_reg_n_0_[5]\, + R => pi_dqs_found_done_r1_reg_0 + ); +\init_state_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \init_state_r[6]_i_1_n_0\, + Q => init_state_r(6), + R => pi_dqs_found_done_r1_reg_0 + ); +mem_init_done_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF4000" + ) + port map ( + I0 => cnt_dllk_zqinit_done_r, + I1 => cnt_dllk_zqinit_r_reg(7), + I2 => mem_init_done_r_i_2_n_0, + I3 => cnt_dllk_zqinit_r_reg(6), + I4 => \^mem_init_done_r\, + O => mem_init_done_r_i_1_n_0 + ); +mem_init_done_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => cnt_dllk_zqinit_r_reg(5), + I1 => cnt_dllk_zqinit_r_reg(3), + I2 => cnt_dllk_zqinit_r_reg(1), + I3 => cnt_dllk_zqinit_r_reg(0), + I4 => cnt_dllk_zqinit_r_reg(2), + I5 => cnt_dllk_zqinit_r_reg(4), + O => mem_init_done_r_i_2_n_0 + ); +mem_init_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mem_init_done_r_i_1_n_0, + Q => \^mem_init_done_r\, + R => pi_dqs_found_done_r1_reg_0 + ); +\mem_reg_0_15_0_5_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(15), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(1) + ); +mem_reg_0_15_0_5_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(3), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(0) + ); +\mem_reg_0_15_0_5_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(12), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(0) + ); +\mem_reg_0_15_0_5_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(3) + ); +mem_reg_0_15_0_5_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(26), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(2) + ); +\mem_reg_0_15_0_5_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(34), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(2) + ); +mem_reg_0_15_0_5_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(22), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(1) + ); +mem_reg_0_15_0_5_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(54), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(4) + ); +mem_reg_0_15_0_5_i_7: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(44), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(3) + ); +mem_reg_0_15_12_17_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_ras_n(0), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(5) + ); +\mem_reg_0_15_12_17_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(49), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(3) + ); +\mem_reg_0_15_12_17_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => mc_ras_n(0), + I1 => phy_ctl_wr_i1_reg, + I2 => phy_ras_n(1), + O => \cmd_pipe_plus.mc_we_n_reg[1]\(8) + ); +mem_reg_0_15_12_17_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(11), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(4) + ); +mem_reg_0_15_12_17_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(76), + I1 => phy_wrdata(121), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[117]\(5) + ); +mem_reg_0_15_12_17_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(61), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(4) + ); +mem_reg_0_15_12_17_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(8), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[117]\(6) + ); +\mem_reg_0_15_12_17_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(5), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[127]\(6) + ); +mem_reg_0_15_18_23_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(28), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(8) + ); +\mem_reg_0_15_18_23_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(7) + ); +mem_reg_0_15_18_23_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(34), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(6) + ); +\mem_reg_0_15_18_23_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(16), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(7) + ); +\mem_reg_0_15_18_23_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(23), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(7) + ); +mem_reg_0_15_18_23_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(48), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(10) + ); +\mem_reg_0_15_18_23_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(56), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(8) + ); +mem_reg_0_15_18_23_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(40), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(9) + ); +\mem_reg_0_15_18_23_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(83), + I1 => phy_wrdata(126), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[127]\(10) + ); +mem_reg_0_15_18_23_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(60), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(11) + ); +\mem_reg_0_15_18_23_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(70), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(9) + ); +mem_reg_0_15_24_29_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(18), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(9) + ); +\mem_reg_0_15_24_29_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(5), + I1 => phy_bank(11), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(10) + ); +\mem_reg_0_15_24_29_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(10), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(12) + ); +mem_reg_0_15_24_29_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(6), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(8) + ); +\mem_reg_0_15_24_29_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(2), + I1 => phy_bank(11), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(9) + ); +mem_reg_0_15_24_29_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(31), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(14) + ); +\mem_reg_0_15_24_29_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(11) + ); +\mem_reg_0_15_24_29_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => phy_bank(11), + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(12) + ); +mem_reg_0_15_24_29_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(29), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(10) + ); +\mem_reg_0_15_24_29_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(8), + I1 => phy_bank(11), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(11) + ); +\mem_reg_0_15_24_29_i_4__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(19), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(13) + ); +mem_reg_0_15_24_29_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(51), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(16) + ); +mem_reg_0_15_24_29_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(42), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(15) + ); +mem_reg_0_15_30_35_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(17), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(14) + ); +\mem_reg_0_15_30_35_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(19), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(13) + ); +mem_reg_0_15_30_35_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(5), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(13) + ); +\mem_reg_0_15_30_35_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(7), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(12) + ); +\mem_reg_0_15_30_35_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(64), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(17) + ); +mem_reg_0_15_30_35_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(36), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(12) + ); +\mem_reg_0_15_30_35_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(16) + ); +\mem_reg_0_15_30_35_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(15) + ); +mem_reg_0_15_30_35_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(28), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(15) + ); +\mem_reg_0_15_30_35_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(30), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(14) + ); +\mem_reg_0_15_30_35_i_4__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(24), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(11) + ); +mem_reg_0_15_36_41_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(12), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(18) + ); +\mem_reg_0_15_36_41_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(21), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(17) + ); +mem_reg_0_15_36_41_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(0), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(17) + ); +\mem_reg_0_15_36_41_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(9), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(16) + ); +\mem_reg_0_15_36_41_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(45), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(13) + ); +mem_reg_0_15_36_41_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(84), + I1 => phy_wrdata(123), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[127]\(15) + ); +mem_reg_0_15_36_41_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(71), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(14) + ); +\mem_reg_0_15_36_41_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(7), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[127]\(16) + ); +mem_reg_0_15_42_47_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(33), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(19) + ); +\mem_reg_0_15_42_47_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(20) + ); +\mem_reg_0_15_42_47_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(19) + ); +mem_reg_0_15_42_47_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(23), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(19) + ); +\mem_reg_0_15_42_47_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(32), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(18) + ); +\mem_reg_0_15_42_47_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(21), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(18) + ); +\mem_reg_0_15_42_47_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(26), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(17) + ); +\mem_reg_0_15_42_47_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(59), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(18) + ); +\mem_reg_0_15_42_47_i_3__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => mc_cke(0), + I1 => phy_ctl_wr_i1_reg, + I2 => calib_cke(3), + O => \cmd_pipe_plus.mc_we_n_reg[1]\(21) + ); +mem_reg_0_15_42_47_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(43), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(20) + ); +mem_reg_0_15_42_47_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(81), + I1 => phy_wrdata(123), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[117]\(22) + ); +\mem_reg_0_15_42_47_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(86), + I1 => phy_wrdata(126), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[127]\(20) + ); +mem_reg_0_15_42_47_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(67), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(21) + ); +\mem_reg_0_15_42_47_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(74), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(19) + ); +mem_reg_0_15_48_53_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(16), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(21) + ); +\mem_reg_0_15_48_53_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(14), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(21) + ); +\mem_reg_0_15_48_53_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => mc_cas_n(0), + I1 => phy_ctl_wr_i1_reg, + I2 => phy_cas_n(1), + O => \cmd_pipe_plus.mc_we_n_reg[1]\(22) + ); +mem_reg_0_15_48_53_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(4), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(20) + ); +\mem_reg_0_15_48_53_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(1), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[117]\(23) + ); +\mem_reg_0_15_48_53_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(37), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(23) + ); +\mem_reg_0_15_48_53_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(23) + ); +mem_reg_0_15_48_53_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(27), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(22) + ); +\mem_reg_0_15_48_53_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(4), + I1 => phy_bank(10), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(24) + ); +\mem_reg_0_15_48_53_i_4__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(17), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(24) + ); +\mem_reg_0_15_48_53_i_4__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(25), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(22) + ); +\mem_reg_0_15_48_53_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(1), + I1 => phy_bank(10), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(23) + ); +\mem_reg_0_15_48_53_i_5__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(50), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(25) + ); +\mem_reg_0_15_48_53_i_5__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(57), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(25) + ); +\mem_reg_0_15_48_53_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(46), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(24) + ); +\mem_reg_0_15_54_59_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(77), + I1 => phy_wrdata(126), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[117]\(27) + ); +\mem_reg_0_15_54_59_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => phy_bank(10), + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(26) + ); +mem_reg_0_15_54_59_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(20), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(25) + ); +\mem_reg_0_15_54_59_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(7), + I1 => phy_bank(10), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(25) + ); +\mem_reg_0_15_54_59_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(62), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(26) + ); +\mem_reg_0_15_54_59_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(72), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(26) + ); +mem_reg_0_15_54_59_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(8), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(24) + ); +\mem_reg_0_15_54_59_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(3), + I1 => phy_bank(9), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(28) + ); +\mem_reg_0_15_54_59_i_3__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(13), + I1 => phy_wrdata(25), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(28) + ); +mem_reg_0_15_54_59_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(0), + I1 => phy_bank(9), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(27) + ); +\mem_reg_0_15_54_59_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(3), + I1 => phy_wrdata(121), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[117]\(28) + ); +\mem_reg_0_15_54_59_i_4__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(4), + I1 => phy_wrdata(13), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[127]\(27) + ); +\mem_reg_0_15_54_59_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(27) + ); +mem_reg_0_15_54_59_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(31), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(26) + ); +\mem_reg_0_15_54_59_i_5__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(35), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(29) + ); +\mem_reg_0_15_54_59_i_5__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => phy_bank(9), + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(30) + ); +mem_reg_0_15_54_59_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_bank(6), + I1 => phy_bank(9), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(29) + ); +\mem_reg_0_15_54_59_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(20), + I1 => phy_wrdata(46), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(29) + ); +mem_reg_0_15_60_65_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(14), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(29) + ); +\mem_reg_0_15_60_65_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(53), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(30) + ); +\mem_reg_0_15_60_65_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(55), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(30) + ); +\mem_reg_0_15_60_65_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => mc_odt(0), + I1 => phy_ctl_wr_i1_reg, + I2 => calib_odt(0), + O => \cmd_pipe_plus.mc_we_n_reg[1]\(31) + ); +mem_reg_0_15_60_65_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(2), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(28) + ); +mem_reg_0_15_60_65_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(80), + I1 => phy_wrdata(126), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[117]\(32) + ); +\mem_reg_0_15_60_65_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(82), + I1 => phy_wrdata(121), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[127]\(32) + ); +mem_reg_0_15_60_65_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(66), + I1 => phy_wrdata(123), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(31) + ); +\mem_reg_0_15_60_65_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(69), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(31) + ); +\mem_reg_0_15_60_65_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(15), + I1 => phy_wrdata(25), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(34) + ); +\mem_reg_0_15_60_65_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(6), + I1 => phy_wrdata(13), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[127]\(33) + ); +mem_reg_0_15_66_71_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(30), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(34) + ); +\mem_reg_0_15_66_71_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(38), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(35) + ); +\mem_reg_0_15_66_71_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(31) + ); +mem_reg_0_15_66_71_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(25), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(30) + ); +\mem_reg_0_15_66_71_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(18), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(33) + ); +\mem_reg_0_15_66_71_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(58), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(36) + ); +mem_reg_0_15_66_71_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(41), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(35) + ); +mem_reg_0_15_66_71_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(78), + I1 => phy_wrdata(123), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[117]\(37) + ); +\mem_reg_0_15_66_71_i_5__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(85), + I1 => phy_wrdata(121), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[127]\(38) + ); +mem_reg_0_15_66_71_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(63), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(36) + ); +\mem_reg_0_15_66_71_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(73), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(37) + ); +\mem_reg_0_15_6_11_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(13), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(1) + ); +\mem_reg_0_15_6_11_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(22), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(5) + ); +mem_reg_0_15_6_11_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(1), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(0) + ); +\mem_reg_0_15_6_11_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(10), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(4) + ); +\mem_reg_0_15_6_11_i_2__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(9), + I1 => phy_wrdata(25), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[117]\(1) + ); +\mem_reg_0_15_6_11_i_2__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(68), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(5) + ); +mem_reg_0_15_6_11_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(0), + I1 => phy_wrdata(13), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[117]\(0) + ); +\mem_reg_0_15_6_11_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => phy_dout(3) + ); +\mem_reg_0_15_6_11_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I1 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(7) + ); +mem_reg_0_15_6_11_i_4: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(24), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => phy_dout(2) + ); +\mem_reg_0_15_6_11_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_address(33), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10]\, + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \cmd_pipe_plus.mc_we_n_reg[1]\(6) + ); +\mem_reg_0_15_6_11_i_4__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(29), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(2) + ); +\mem_reg_0_15_72_77_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(11), + I1 => phy_wrdata(25), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(39) + ); +\mem_reg_0_15_72_77_i_1__2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => mc_we_n(0), + I1 => phy_ctl_wr_i1_reg, + I2 => phy_we_n(1), + O => \cmd_pipe_plus.mc_we_n_reg[1]\(32) + ); +\mem_reg_0_15_72_77_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(2), + I1 => phy_wrdata(13), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\, + O => \write_buffer.wr_buf_out_data_reg[117]\(38) + ); +mem_reg_0_15_72_77_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(32), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[117]\(40) + ); +\mem_reg_0_15_72_77_i_3__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(39), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(40) + ); +\mem_reg_0_15_72_77_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(27), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\, + O => \write_buffer.wr_buf_out_data_reg[127]\(39) + ); +mem_reg_0_15_72_77_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(52), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(41) + ); +\mem_reg_0_15_72_77_i_6__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(47), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(41) + ); +mem_reg_0_15_78_79_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(79), + I1 => phy_wrdata(121), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[117]\(43) + ); +\mem_reg_0_15_78_79_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(87), + I1 => phy_wrdata(123), + I2 => \wr_ptr_timing_reg[0]_0\, + O => \write_buffer.wr_buf_out_data_reg[127]\(43) + ); +mem_reg_0_15_78_79_i_2: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(65), + I1 => phy_wrdata(109), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[117]\(42) + ); +\mem_reg_0_15_78_79_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => out_fifo(75), + I1 => phy_wrdata(111), + I2 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\, + O => \write_buffer.wr_buf_out_data_reg[127]\(42) + ); +mpr_rdlvl_start_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF02" + ) + port map ( + I0 => pi_dqs_found_done, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => mpr_rdlvl_start_i_2_n_0, + I3 => \^mpr_rdlvl_start_reg_0\, + O => mpr_rdlvl_start_i_1_n_0 + ); +mpr_rdlvl_start_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFEFFFFFFF" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => \init_state_r_reg_n_0_[2]\, + O => mpr_rdlvl_start_i_2_n_0 + ); +mpr_rdlvl_start_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mpr_rdlvl_start_i_1_n_0, + Q => \^mpr_rdlvl_start_reg_0\, + R => pi_dqs_found_done_r1_reg_0 + ); +\my_empty[7]_i_2__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => mc_wrdata_en, + I1 => phy_ctl_wr_i1_reg, + I2 => \^calib_wrdata_en\, + O => mux_wrdata_en + ); +\my_empty[7]_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => phy_ctl_wr_i1_reg, + I1 => \^calib_ctl_wren_reg_0\, + O => mux_cmd_wren + ); +\num_refresh[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => num_refresh_reg(0), + O => \p_0_in__5\(0) + ); +\num_refresh[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => num_refresh_reg(1), + I1 => num_refresh_reg(0), + O => \p_0_in__5\(1) + ); +\num_refresh[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => num_refresh_reg(2), + I1 => num_refresh_reg(0), + I2 => num_refresh_reg(1), + O => \p_0_in__5\(2) + ); +\num_refresh[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \num_refresh[3]_i_4_n_0\, + I1 => \complex_wait_cnt_reg[3]_0\, + I2 => complex_oclkdelay_calib_start_int_i_2_n_0, + I3 => \num_refresh[3]_i_5_n_0\, + O => \num_refresh[3]_i_1_n_0\ + ); +\num_refresh[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"2A22" + ) + port map ( + I0 => \num_refresh[3]_i_6_n_0\, + I1 => pi_dqs_found_done, + I2 => D(3), + I3 => \^wrlvl_done_r1\, + O => num_refresh0 + ); +\num_refresh[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => num_refresh_reg(3), + I1 => num_refresh_reg(1), + I2 => num_refresh_reg(0), + I3 => num_refresh_reg(2), + O => \p_0_in__5\(3) + ); +\num_refresh[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2002000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \wrcal_reads[7]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => \num_refresh[3]_i_4_n_0\ + ); +\num_refresh[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000004004" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r[5]_i_12_n_0\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[4]\, + O => \num_refresh[3]_i_5_n_0\ + ); +\num_refresh[3]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0004000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => \num_refresh[3]_i_6_n_0\ + ); +\num_refresh_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => num_refresh0, + D => \p_0_in__5\(0), + Q => num_refresh_reg(0), + R => \num_refresh[3]_i_1_n_0\ + ); +\num_refresh_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => num_refresh0, + D => \p_0_in__5\(1), + Q => num_refresh_reg(1), + R => \num_refresh[3]_i_1_n_0\ + ); +\num_refresh_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => num_refresh0, + D => \p_0_in__5\(2), + Q => num_refresh_reg(2), + R => \num_refresh[3]_i_1_n_0\ + ); +\num_refresh_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => num_refresh0, + D => \p_0_in__5\(3), + Q => num_refresh_reg(3), + R => \num_refresh[3]_i_1_n_0\ + ); +\ocal_act_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => ocal_act_wait_cnt_reg(0), + O => \p_0_in__8\(0) + ); +\ocal_act_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => ocal_act_wait_cnt_reg(1), + I1 => ocal_act_wait_cnt_reg(0), + O => \p_0_in__8\(1) + ); +\ocal_act_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => ocal_act_wait_cnt_reg(2), + I1 => ocal_act_wait_cnt_reg(0), + I2 => ocal_act_wait_cnt_reg(1), + O => \p_0_in__8\(2) + ); +\ocal_act_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFFFFFF" + ) + port map ( + I0 => \ocal_act_wait_cnt[3]_i_3_n_0\, + I1 => \complex_wait_cnt_reg[3]_0\, + I2 => \ocal_act_wait_cnt[3]_i_4_n_0\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => init_state_r(6), + O => \ocal_act_wait_cnt[3]_i_1_n_0\ + ); +\ocal_act_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => ocal_act_wait_cnt_reg(3), + I1 => ocal_act_wait_cnt_reg(1), + I2 => ocal_act_wait_cnt_reg(0), + I3 => ocal_act_wait_cnt_reg(2), + O => \p_0_in__8\(3) + ); +\ocal_act_wait_cnt[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8000FFFF" + ) + port map ( + I0 => ocal_act_wait_cnt_reg(2), + I1 => ocal_act_wait_cnt_reg(0), + I2 => ocal_act_wait_cnt_reg(1), + I3 => ocal_act_wait_cnt_reg(3), + I4 => \init_state_r_reg_n_0_[1]\, + O => \ocal_act_wait_cnt[3]_i_3_n_0\ + ); +\ocal_act_wait_cnt[3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[0]\, + O => \ocal_act_wait_cnt[3]_i_4_n_0\ + ); +\ocal_act_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__8\(0), + Q => ocal_act_wait_cnt_reg(0), + R => \ocal_act_wait_cnt[3]_i_1_n_0\ + ); +\ocal_act_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__8\(1), + Q => ocal_act_wait_cnt_reg(1), + R => \ocal_act_wait_cnt[3]_i_1_n_0\ + ); +\ocal_act_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__8\(2), + Q => ocal_act_wait_cnt_reg(2), + R => \ocal_act_wait_cnt[3]_i_1_n_0\ + ); +\ocal_act_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__8\(3), + Q => ocal_act_wait_cnt_reg(3), + R => \ocal_act_wait_cnt[3]_i_1_n_0\ + ); +\oclk_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => oclk_wr_cnt_reg(0), + O => \oclk_wr_cnt[0]_i_1_n_0\ + ); +\oclk_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => oclk_wr_cnt_reg(0), + I1 => oclk_wr_cnt_reg(1), + O => \oclk_wr_cnt[1]_i_1_n_0\ + ); +\oclk_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => oclk_wr_cnt_reg(2), + I1 => oclk_wr_cnt_reg(1), + I2 => oclk_wr_cnt_reg(0), + O => oclk_wr_cnt0(2) + ); +\oclk_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFAAAAAAAB" + ) + port map ( + I0 => \oclk_wr_cnt[3]_i_4_n_0\, + I1 => oclk_wr_cnt_reg(1), + I2 => oclk_wr_cnt_reg(0), + I3 => oclk_wr_cnt_reg(3), + I4 => oclk_wr_cnt_reg(2), + I5 => \complex_wait_cnt_reg[3]_0\, + O => \oclk_wr_cnt[3]_i_1_n_0\ + ); +\oclk_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000800000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => ddr3_lm_done_r_i_2_n_0, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => p_0_in0_in + ); +\oclk_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => oclk_wr_cnt_reg(3), + I1 => oclk_wr_cnt_reg(2), + I2 => oclk_wr_cnt_reg(0), + I3 => oclk_wr_cnt_reg(1), + O => oclk_wr_cnt0(3) + ); +\oclk_wr_cnt[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000100000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => detect_pi_found_dqs_i_2_n_0, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[5]\, + O => \oclk_wr_cnt[3]_i_4_n_0\ + ); +\oclk_wr_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_0_in0_in, + D => \oclk_wr_cnt[0]_i_1_n_0\, + Q => oclk_wr_cnt_reg(0), + R => \oclk_wr_cnt[3]_i_1_n_0\ + ); +\oclk_wr_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_0_in0_in, + D => \oclk_wr_cnt[1]_i_1_n_0\, + Q => oclk_wr_cnt_reg(1), + R => \oclk_wr_cnt[3]_i_1_n_0\ + ); +\oclk_wr_cnt_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => p_0_in0_in, + D => oclk_wr_cnt0(2), + Q => oclk_wr_cnt_reg(2), + S => \oclk_wr_cnt[3]_i_1_n_0\ + ); +\oclk_wr_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_0_in0_in, + D => oclk_wr_cnt0(3), + Q => oclk_wr_cnt_reg(3), + R => \oclk_wr_cnt[3]_i_1_n_0\ + ); +\odd_cwl.phy_cas_n[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => phy_wrdata_en, + I1 => \calib_cmd[2]_i_2_n_0\, + I2 => \odd_cwl.phy_ras_n[1]_i_2_n_0\, + I3 => \num_refresh[3]_i_6_n_0\, + O => \odd_cwl.phy_cas_n[1]_i_1_n_0\ + ); +\odd_cwl.phy_cas_n_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \odd_cwl.phy_cas_n[1]_i_1_n_0\, + Q => phy_cas_n(1), + R => '0' + ); +\odd_cwl.phy_ras_n[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000020202" + ) + port map ( + I0 => \odd_cwl.phy_ras_n[1]_i_2_n_0\, + I1 => \odd_cwl.phy_ras_n[1]_i_3_n_0\, + I2 => \num_refresh[3]_i_5_n_0\, + I3 => complex_oclkdelay_calib_start_int_i_2_n_0, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \odd_cwl.phy_ras_n[1]_i_4_n_0\, + O => \odd_cwl.phy_ras_n[1]_i_1_n_0\ + ); +\odd_cwl.phy_ras_n[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001000000010001" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0\, + I1 => \en_cnt_div4.enable_wrlvl_cnt[3]_i_3_n_0\, + I2 => reg_ctrl_cnt_r, + I3 => write_calib_i_2_n_0, + I4 => mpr_rdlvl_start_i_2_n_0, + I5 => \init_state_r_reg_n_0_[1]\, + O => \odd_cwl.phy_ras_n[1]_i_2_n_0\ + ); +\odd_cwl.phy_ras_n[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEFE" + ) + port map ( + I0 => \num_refresh[3]_i_6_n_0\, + I1 => \odd_cwl.phy_ras_n[1]_i_5_n_0\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => init_state_r(6), + I4 => \odd_cwl.phy_ras_n[1]_i_6_n_0\, + O => \odd_cwl.phy_ras_n[1]_i_3_n_0\ + ); +\odd_cwl.phy_ras_n[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1003000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0\, + O => \odd_cwl.phy_ras_n[1]_i_4_n_0\ + ); +\odd_cwl.phy_ras_n[1]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0020000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[3]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[5]\, + I5 => prech_req_posedge_r_i_2_n_0, + O => \odd_cwl.phy_ras_n[1]_i_5_n_0\ + ); +\odd_cwl.phy_ras_n[1]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \init_state_r_reg_n_0_[0]\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[3]\, + O => \odd_cwl.phy_ras_n[1]_i_6_n_0\ + ); +\odd_cwl.phy_ras_n_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \odd_cwl.phy_ras_n[1]_i_1_n_0\, + Q => phy_ras_n(1), + R => '0' + ); +\odd_cwl.phy_we_n[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \odd_cwl.phy_ras_n[1]_i_2_n_0\, + I1 => phy_wrdata_en, + I2 => address_w173_out, + O => \odd_cwl.phy_we_n[1]_i_1_n_0\ + ); +\odd_cwl.phy_we_n_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \odd_cwl.phy_we_n[1]_i_1_n_0\, + Q => phy_we_n(1), + R => '0' + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I1 => out_fifo_10, + I2 => mem_out(7), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(34), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I2 => out_fifo_10, + I3 => mem_out(6), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_ras_n(0), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I2 => out_fifo_10, + I3 => mem_out(5), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(11), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12]\, + I2 => out_fifo_10, + I3 => mem_out(4), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(0) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_14\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I1 => out_fifo_10, + I2 => mem_out(11), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_15\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(29), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I2 => out_fifo_10, + I3 => mem_out(10), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_16\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(18), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I2 => out_fifo_10, + I3 => mem_out(9), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_17\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(6), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6]\, + I2 => out_fifo_10, + I3 => mem_out(8), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(0) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_18\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I1 => out_fifo_7, + I2 => mem_out(15), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_19\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(30), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I2 => out_fifo_7, + I3 => mem_out(14), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_20\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(19), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I2 => out_fifo_10, + I3 => mem_out(13), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_21\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(7), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7]\, + I2 => out_fifo_10, + I3 => mem_out(12), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(0) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_22\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I1 => out_fifo_7, + I2 => mem_out(19), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_23\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(32), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I2 => out_fifo_7, + I3 => mem_out(18), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_24\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(21), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I2 => out_fifo_7, + I3 => mem_out(17), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_25\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(9), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9]\, + I2 => out_fifo_7, + I3 => mem_out(16), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(0) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_30\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I1 => out_fifo_7, + I2 => mem_out(23), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_31\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(27), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I2 => out_fifo_7, + I3 => mem_out(22), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_32\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(16), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I2 => out_fifo_7, + I3 => mem_out(21), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_33\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(4), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4]\, + I2 => out_fifo_7, + I3 => mem_out(20), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0\(0) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_34\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I1 => out_fifo_7, + I2 => mem_out(27), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_35\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(31), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I2 => out_fifo_7, + I3 => mem_out(26), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_36\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(20), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I2 => out_fifo_7, + I3 => mem_out(25), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_37\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(8), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8]\, + I2 => out_fifo_7, + I3 => mem_out(24), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(0) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_38\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I1 => out_fifo_7, + I2 => mem_out(31), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_39\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(25), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I2 => out_fifo_7, + I3 => mem_out(30), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_40\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(14), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I2 => out_fifo_7, + I3 => mem_out(29), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_41\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(2), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2]\, + I2 => out_fifo_7, + I3 => mem_out(28), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(0) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EEF0" + ) + port map ( + I0 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I1 => out_fifo_10, + I2 => mem_out(3), + I3 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(3) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(24), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I2 => out_fifo_10, + I3 => mem_out(2), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(2) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(13), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I2 => out_fifo_10, + I3 => mem_out(1), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => mc_address(1), + I1 => \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1]\, + I2 => out_fifo_10, + I3 => mem_out(0), + I4 => out_fifo_11, + O => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(0) + ); +\one_rank.stg1_wr_done_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000001010100" + ) + port map ( + I0 => \^prbs_rdlvl_done_pulse_reg_0\, + I1 => rdlvl_last_byte_done, + I2 => ddr2_pre_flag_r, + I3 => stg1_wr_done, + I4 => \^one_rank.stg1_wr_done_reg_0\, + I5 => complex_byte_rd_done, + O => \one_rank.stg1_wr_done_i_1_n_0\ + ); +\one_rank.stg1_wr_done_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \one_rank.stg1_wr_done_i_1_n_0\, + Q => \^one_rank.stg1_wr_done_reg_0\, + R => '0' + ); +out_fifo_i_11: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(60), + I1 => phy_wrdata(111), + I2 => out_fifo_3, + I3 => out_fifo_1(11), + I4 => out_fifo_2, + O => D2(5) + ); +out_fifo_i_12: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(48), + I1 => phy_wrdata(109), + I2 => out_fifo_3, + I3 => out_fifo_1(10), + I4 => out_fifo_2, + O => D2(4) + ); +out_fifo_i_13: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(40), + I1 => phy_wrdata(121), + I2 => out_fifo_0, + I3 => out_fifo_1(9), + I4 => out_fifo_2, + O => D2(3) + ); +out_fifo_i_14: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(28), + I1 => phy_wrdata(121), + I2 => out_fifo_0, + I3 => out_fifo_1(8), + I4 => out_fifo_2, + O => D2(2) + ); +out_fifo_i_15: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(16), + I1 => phy_wrdata(109), + I2 => out_fifo_0, + I3 => out_fifo_1(7), + I4 => out_fifo_2, + O => D2(1) + ); +out_fifo_i_16: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(8), + I1 => phy_wrdata(46), + I2 => out_fifo_0, + I3 => out_fifo_1(6), + I4 => out_fifo_2, + O => D2(0) + ); +\out_fifo_i_18__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(83), + I1 => phy_wrdata(126), + I2 => out_fifo_4, + I3 => out_fifo_5(10), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[122]\(4) + ); +out_fifo_i_19: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(64), + I1 => phy_wrdata(111), + I2 => out_fifo_3, + I3 => out_fifo_1(17), + I4 => out_fifo_2, + O => D3(5) + ); +\out_fifo_i_19__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(70), + I1 => phy_wrdata(123), + I2 => out_fifo_4, + I3 => out_fifo_5(9), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[122]\(3) + ); +out_fifo_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(76), + I1 => phy_wrdata(121), + I2 => out_fifo_0, + I3 => out_fifo_1(5), + I4 => out_fifo_2, + O => D1(5) + ); +out_fifo_i_20: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(51), + I1 => phy_wrdata(109), + I2 => out_fifo_3, + I3 => out_fifo_1(16), + I4 => out_fifo_2, + O => D3(4) + ); +\out_fifo_i_20__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(56), + I1 => phy_wrdata(123), + I2 => out_fifo_4, + I3 => out_fifo_5(8), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[122]\(2) + ); +out_fifo_i_21: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(42), + I1 => phy_wrdata(121), + I2 => out_fifo_3, + I3 => out_fifo_1(15), + I4 => out_fifo_2, + O => D3(3) + ); +out_fifo_i_22: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(31), + I1 => phy_wrdata(121), + I2 => out_fifo_3, + I3 => out_fifo_1(14), + I4 => out_fifo_2, + O => D3(2) + ); +out_fifo_i_23: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(19), + I1 => phy_wrdata(109), + I2 => out_fifo_3, + I3 => out_fifo_1(13), + I4 => out_fifo_2, + O => D3(1) + ); +\out_fifo_i_23__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(23), + I1 => phy_wrdata(46), + I2 => out_fifo_4, + I3 => out_fifo_5(7), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[122]\(1) + ); +out_fifo_i_24: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(10), + I1 => phy_wrdata(46), + I2 => out_fifo_3, + I3 => out_fifo_1(12), + I4 => out_fifo_2, + O => D3(0) + ); +\out_fifo_i_25__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(5), + I1 => phy_wrdata(121), + I2 => out_fifo_4, + I3 => out_fifo_5(6), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[122]\(0) + ); +\out_fifo_i_26__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(84), + I1 => phy_wrdata(123), + I2 => out_fifo_4, + I3 => out_fifo_5(15), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[123]\(4) + ); +\out_fifo_i_27__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(71), + I1 => phy_wrdata(111), + I2 => out_fifo_4, + I3 => out_fifo_5(14), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[123]\(3) + ); +\out_fifo_i_29__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(45), + I1 => phy_wrdata(109), + I2 => out_fifo_4, + I3 => out_fifo_5(13), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[123]\(2) + ); +out_fifo_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(61), + I1 => phy_wrdata(109), + I2 => out_fifo_0, + I3 => out_fifo_1(4), + I4 => out_fifo_2, + O => D1(4) + ); +\out_fifo_i_30__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(36), + I1 => phy_wrdata(109), + I2 => out_fifo_4, + I3 => out_fifo_5(12), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[123]\(1) + ); +\out_fifo_i_31__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(24), + I1 => phy_wrdata(111), + I2 => out_fifo_4, + I3 => out_fifo_5(11), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[123]\(0) + ); +out_fifo_i_34: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(81), + I1 => phy_wrdata(123), + I2 => out_fifo_3, + I3 => out_fifo_1(22), + I4 => out_fifo_2, + O => D5(4) + ); +\out_fifo_i_34__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(86), + I1 => phy_wrdata(126), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(20), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[126]\(4) + ); +out_fifo_i_35: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(67), + I1 => phy_wrdata(111), + I2 => out_fifo_3, + I3 => out_fifo_1(21), + I4 => out_fifo_2, + O => D5(3) + ); +\out_fifo_i_35__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(74), + I1 => phy_wrdata(123), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(19), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[126]\(3) + ); +\out_fifo_i_36__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(59), + I1 => phy_wrdata(123), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(18), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[126]\(2) + ); +out_fifo_i_37: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(43), + I1 => phy_wrdata(109), + I2 => out_fifo_3, + I3 => out_fifo_1(20), + I4 => out_fifo_2, + O => D5(2) + ); +out_fifo_i_38: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(33), + I1 => phy_wrdata(109), + I2 => out_fifo_3, + I3 => out_fifo_1(19), + I4 => out_fifo_2, + O => D5(1) + ); +out_fifo_i_39: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(21), + I1 => phy_wrdata(111), + I2 => out_fifo_3, + I3 => out_fifo_1(18), + I4 => out_fifo_2, + O => D5(0) + ); +\out_fifo_i_39__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(26), + I1 => phy_wrdata(46), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(17), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[126]\(1) + ); +\out_fifo_i_3__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(68), + I1 => phy_wrdata(111), + I2 => out_fifo_4, + I3 => out_fifo_5(5), + I4 => out_fifo_6, + O => D0(5) + ); +out_fifo_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(49), + I1 => phy_wrdata(111), + I2 => out_fifo_0, + I3 => out_fifo_1(3), + I4 => out_fifo_2, + O => D1(3) + ); +\out_fifo_i_41__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(7), + I1 => phy_wrdata(121), + I2 => out_fifo_4, + I3 => out_fifo_5(16), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[126]\(0) + ); +out_fifo_i_42: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(77), + I1 => phy_wrdata(126), + I2 => out_fifo_3, + I3 => out_fifo_1(27), + I4 => out_fifo_2, + O => D6(4) + ); +out_fifo_i_43: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(62), + I1 => phy_wrdata(123), + I2 => out_fifo_3, + I3 => out_fifo_1(26), + I4 => out_fifo_2, + O => D6(3) + ); +\out_fifo_i_43__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(72), + I1 => phy_wrdata(111), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(26), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[108]\(5) + ); +out_fifo_i_44: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(50), + I1 => phy_wrdata(123), + I2 => out_fifo_3, + I3 => out_fifo_1(25), + I4 => out_fifo_2, + O => D6(2) + ); +\out_fifo_i_44__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(57), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(25), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[108]\(4) + ); +\out_fifo_i_45__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(46), + I1 => phy_wrdata(121), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(24), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[108]\(3) + ); +\out_fifo_i_46__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(37), + I1 => phy_wrdata(121), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(23), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[108]\(2) + ); +out_fifo_i_47: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(17), + I1 => phy_wrdata(46), + I2 => out_fifo_3, + I3 => out_fifo_1(24), + I4 => out_fifo_2, + O => D6(1) + ); +\out_fifo_i_47__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(25), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(22), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[108]\(1) + ); +\out_fifo_i_48__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(14), + I1 => phy_wrdata(46), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(21), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[108]\(0) + ); +out_fifo_i_49: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(1), + I1 => phy_wrdata(121), + I2 => out_fifo_3, + I3 => out_fifo_1(23), + I4 => out_fifo_2, + O => D6(0) + ); +\out_fifo_i_4__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(54), + I1 => phy_wrdata(109), + I2 => out_fifo_4, + I3 => out_fifo_5(4), + I4 => out_fifo_6, + O => D0(4) + ); +out_fifo_i_50: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(80), + I1 => phy_wrdata(126), + I2 => out_fifo_3, + I3 => out_fifo_1(32), + I4 => out_fifo_2, + O => D7(4) + ); +\out_fifo_i_50__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(82), + I1 => phy_wrdata(121), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(32), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[121]\(5) + ); +out_fifo_i_51: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(66), + I1 => phy_wrdata(123), + I2 => out_fifo_3, + I3 => out_fifo_1(31), + I4 => out_fifo_2, + O => D7(3) + ); +\out_fifo_i_51__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(69), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(31), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[121]\(4) + ); +out_fifo_i_52: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(53), + I1 => phy_wrdata(123), + I2 => out_fifo_3, + I3 => out_fifo_1(30), + I4 => out_fifo_2, + O => D7(2) + ); +\out_fifo_i_52__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(55), + I1 => phy_wrdata(111), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(30), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[121]\(3) + ); +\out_fifo_i_54__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(35), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(29), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[121]\(2) + ); +out_fifo_i_55: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(20), + I1 => phy_wrdata(46), + I2 => out_fifo_3, + I3 => out_fifo_1(29), + I4 => out_fifo_2, + O => D7(1) + ); +\out_fifo_i_56__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(13), + I1 => phy_wrdata(25), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(28), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[121]\(1) + ); +out_fifo_i_57: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(3), + I1 => phy_wrdata(121), + I2 => out_fifo_3, + I3 => out_fifo_1(28), + I4 => out_fifo_2, + O => D7(0) + ); +\out_fifo_i_57__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(4), + I1 => phy_wrdata(13), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(27), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[121]\(0) + ); +out_fifo_i_58: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(78), + I1 => phy_wrdata(123), + I2 => out_fifo_4, + I3 => out_fifo_1(37), + I4 => out_fifo_2, + O => D8(4) + ); +\out_fifo_i_58__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(85), + I1 => phy_wrdata(121), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(38), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[125]\(5) + ); +out_fifo_i_59: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(63), + I1 => phy_wrdata(111), + I2 => out_fifo_4, + I3 => out_fifo_1(36), + I4 => out_fifo_2, + O => D8(3) + ); +\out_fifo_i_59__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(73), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(37), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[125]\(4) + ); +\out_fifo_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(44), + I1 => phy_wrdata(121), + I2 => out_fifo_4, + I3 => out_fifo_5(3), + I4 => out_fifo_6, + O => D0(3) + ); +out_fifo_i_6: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(29), + I1 => phy_wrdata(109), + I2 => out_fifo_0, + I3 => out_fifo_1(2), + I4 => out_fifo_2, + O => D1(2) + ); +\out_fifo_i_60__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(58), + I1 => phy_wrdata(111), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(36), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[125]\(3) + ); +out_fifo_i_61: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(41), + I1 => phy_wrdata(109), + I2 => out_fifo_4, + I3 => out_fifo_1(35), + I4 => out_fifo_2, + O => D8(2) + ); +out_fifo_i_62: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(30), + I1 => phy_wrdata(109), + I2 => out_fifo_3, + I3 => out_fifo_1(34), + I4 => out_fifo_2, + O => D8(1) + ); +\out_fifo_i_62__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(38), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(35), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[125]\(2) + ); +out_fifo_i_63: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(18), + I1 => phy_wrdata(111), + I2 => out_fifo_3, + I3 => out_fifo_1(33), + I4 => out_fifo_2, + O => D8(0) + ); +\out_fifo_i_64__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(15), + I1 => phy_wrdata(25), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(34), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[125]\(1) + ); +\out_fifo_i_65__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(6), + I1 => phy_wrdata(13), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(33), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[125]\(0) + ); +out_fifo_i_66: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(79), + I1 => phy_wrdata(121), + I2 => out_fifo_4, + I3 => out_fifo_1(43), + I4 => out_fifo_2, + O => D9(5) + ); +\out_fifo_i_66__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(87), + I1 => phy_wrdata(123), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(43), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(4) + ); +out_fifo_i_67: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(65), + I1 => phy_wrdata(109), + I2 => out_fifo_4, + I3 => out_fifo_1(42), + I4 => out_fifo_2, + O => D9(4) + ); +\out_fifo_i_67__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(75), + I1 => phy_wrdata(111), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(42), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(3) + ); +out_fifo_i_68: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(52), + I1 => phy_wrdata(111), + I2 => out_fifo_4, + I3 => out_fifo_1(41), + I4 => out_fifo_2, + O => D9(3) + ); +\out_fifo_i_69__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(47), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(41), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(2) + ); +\out_fifo_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(34), + I1 => phy_wrdata(121), + I2 => out_fifo_4, + I3 => out_fifo_5(2), + I4 => out_fifo_6, + O => D0(2) + ); +out_fifo_i_70: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(32), + I1 => phy_wrdata(109), + I2 => out_fifo_4, + I3 => out_fifo_1(40), + I4 => out_fifo_2, + O => D9(2) + ); +\out_fifo_i_70__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(39), + I1 => phy_wrdata(109), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(40), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(1) + ); +\out_fifo_i_71__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(27), + I1 => phy_wrdata(111), + I2 => phy_ctl_wr_i1_reg, + I3 => out_fifo_5(39), + I4 => out_fifo_6, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(0) + ); +out_fifo_i_72: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(11), + I1 => phy_wrdata(25), + I2 => out_fifo_4, + I3 => out_fifo_1(39), + I4 => out_fifo_2, + O => D9(1) + ); +out_fifo_i_73: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(2), + I1 => phy_wrdata(13), + I2 => out_fifo_4, + I3 => out_fifo_1(38), + I4 => out_fifo_2, + O => D9(0) + ); +\out_fifo_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(22), + I1 => phy_wrdata(109), + I2 => out_fifo_4, + I3 => out_fifo_5(1), + I4 => out_fifo_6, + O => D0(1) + ); +out_fifo_i_8: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(9), + I1 => phy_wrdata(25), + I2 => out_fifo_0, + I3 => out_fifo_1(1), + I4 => out_fifo_2, + O => D1(1) + ); +\out_fifo_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(12), + I1 => phy_wrdata(46), + I2 => out_fifo_4, + I3 => out_fifo_5(0), + I4 => out_fifo_6, + O => D0(0) + ); +out_fifo_i_9: unisim.vcomponents.LUT5 + generic map( + INIT => X"ACACFF00" + ) + port map ( + I0 => out_fifo(0), + I1 => phy_wrdata(13), + I2 => out_fifo_0, + I3 => out_fifo_1(0), + I4 => out_fifo_2, + O => D1(0) + ); +\phy_ctl_wd_i1[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_cmd(0), + I1 => calib_cmd(0), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(0) + ); +\phy_ctl_wd_i1[17]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \phy_ctl_wd_i1_reg[17]\, + I1 => calib_data_offset_0(0), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(3) + ); +\phy_ctl_wd_i1[18]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \phy_ctl_wd_i1_reg[18]\, + I1 => calib_data_offset_0(1), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(4) + ); +\phy_ctl_wd_i1[19]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \phy_ctl_wd_i1_reg[19]\, + I1 => calib_data_offset_0(2), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(5) + ); +\phy_ctl_wd_i1[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_cmd(1), + I1 => calib_cmd(1), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(1) + ); +\phy_ctl_wd_i1[20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_data_offset(0), + I1 => calib_data_offset_0(3), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(6) + ); +\phy_ctl_wd_i1[21]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \phy_ctl_wd_i1_reg[21]\, + I1 => calib_data_offset_0(4), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(7) + ); +\phy_ctl_wd_i1[22]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \phy_ctl_wd_i1_reg[22]_0\, + I1 => calib_data_offset_0(5), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(8) + ); +\phy_ctl_wd_i1[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => mc_cas_n(0), + I1 => calib_cmd(2), + I2 => \phy_ctl_wd_i1_reg[22]\, + O => \^calib_seq_reg[1]_0\(2) + ); +phy_ctl_wr_i1_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^calib_ctl_wren_reg_0\, + I1 => phy_ctl_wr_i1_reg, + O => calib_ctl_wren_reg_1 + ); +phy_reset_n_reg: unisim.vcomponents.FDCE + port map ( + C => CLK, + CE => '1', + CLR => pi_dqs_found_done_r1_reg_0, + D => cnt_pwron_reset_done_r, + Q => phy_reset_n + ); +pi_calib_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_calib_done_r, + Q => \^pi_calib_done\, + R => '0' + ); +pi_calib_done_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => pi_calib_rank_done_r, + I1 => pi_calib_done_r, + O => pi_calib_done_r_i_1_n_0 + ); +pi_calib_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_calib_done_r_i_1_n_0, + Q => pi_calib_done_r, + R => pi_dqs_found_done_r1_reg_0 + ); +pi_calib_rank_done_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => pi_phase_locked_all_r3, + I1 => pi_phase_locked_all_r4, + O => init_next_state199_out + ); +pi_calib_rank_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => init_next_state199_out, + Q => pi_calib_rank_done_r, + R => pi_dqs_found_done_r1_reg_0 + ); +pi_dqs_found_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_done, + Q => pi_dqs_found_done_r1, + R => pi_dqs_found_done_r1_reg_0 + ); +pi_dqs_found_start_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000AE" + ) + port map ( + I0 => \^pi_dqs_found_start_reg_0\, + I1 => pi_dqs_found_start_i_2_n_0, + I2 => pi_dqs_found_done, + I3 => wrlvl_byte_redo, + I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => pi_dqs_found_start_i_1_n_0 + ); +pi_dqs_found_start_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000004" + ) + port map ( + I0 => \init_state_r[6]_i_4_n_0\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[5]\, + O => pi_dqs_found_start_i_2_n_0 + ); +pi_dqs_found_start_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_dqs_found_start_i_1_n_0, + Q => \^pi_dqs_found_start_reg_0\, + R => '0' + ); +pi_phase_locked_all_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => in0, + Q => pi_phase_locked_all_r1, + R => '0' + ); +pi_phase_locked_all_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_phase_locked_all_r1, + Q => pi_phase_locked_all_r2, + R => '0' + ); +pi_phase_locked_all_r3_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_phase_locked_all_r2, + Q => pi_phase_locked_all_r3, + R => '0' + ); +pi_phase_locked_all_r4_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_phase_locked_all_r3, + Q => pi_phase_locked_all_r4, + R => '0' + ); +prbs_rdlvl_done_pulse_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => prbs_rdlvl_done_pulse0, + Q => \^prbs_rdlvl_done_pulse_reg_0\, + R => '0' + ); +\prech_done_dly_r_reg[15]_srl16\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '1', + A2 => '1', + A3 => '1', + CE => '1', + CLK => CLK, + D => prech_done_pre, + Q => \prech_done_dly_r_reg[15]_srl16_n_0\ + ); +\prech_done_dly_r_reg[15]_srl16_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => prech_pending_r_i_2_n_0, + I1 => \^prech_req_posedge_r_reg_0\, + O => prech_done_pre + ); +prech_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \prech_done_dly_r_reg[15]_srl16_n_0\, + Q => prech_done, + R => '0' + ); +prech_pending_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \^prech_req_posedge_r_reg_0\, + I1 => prech_pending_r_i_2_n_0, + I2 => prech_pending_r, + O => prech_pending_r_i_1_n_0 + ); +prech_pending_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"A8AAA8A888888888" + ) + port map ( + I0 => prech_pending_r, + I1 => prech_pending_r_i_3_n_0, + I2 => prech_pending_r_i_4_n_0, + I3 => prech_pending_r_i_5_n_0, + I4 => rdlvl_last_byte_done_r, + I5 => cnt_cmd_done_r, + O => prech_pending_r_i_2_n_0 + ); +prech_pending_r_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFF4" + ) + port map ( + I0 => prech_pending_r_i_5_n_0, + I1 => dqs_found_prech_req, + I2 => \calib_cmd[2]_i_3_n_0\, + I3 => stg1_wr_done, + I4 => \num_refresh[3]_i_4_n_0\, + I5 => prech_pending_r_i_6_n_0, + O => prech_pending_r_i_3_n_0 + ); +prech_pending_r_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000100000000001" + ) + port map ( + I0 => \wrcal_reads[7]_i_4_n_0\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[1]\, + O => prech_pending_r_i_4_n_0 + ); +prech_pending_r_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFBF" + ) + port map ( + I0 => \init_state_r[6]_i_4_n_0\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => init_state_r(6), + O => prech_pending_r_i_5_n_0 + ); +prech_pending_r_i_6: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF800F800F800" + ) + port map ( + I0 => \init_state_r[4]_i_22_n_0\, + I1 => \init_state_r[2]_i_17_n_0\, + I2 => \complex_row_cnt_ocal[3]_i_5_n_0\, + I3 => \^rdlvl_stg1_done_r1_reg_0\, + I4 => prech_pending_r_i_7_n_0, + I5 => complex_oclkdelay_calib_start_r1, + O => prech_pending_r_i_6_n_0 + ); +prech_pending_r_i_7: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000800000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[5]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => prech_pending_r_i_7_n_0 + ); +prech_pending_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => prech_pending_r_i_1_n_0, + Q => prech_pending_r, + R => pi_dqs_found_done_r1_reg_0 + ); +prech_req_posedge_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"5454545455545454" + ) + port map ( + I0 => prech_req_r, + I1 => rdlvl_prech_req, + I2 => wrcal_prech_req, + I3 => dqs_found_prech_req, + I4 => prech_req_posedge_r_i_2_n_0, + I5 => prech_req_posedge_r_i_3_n_0, + O => prech_req_posedge_r0 + ); +prech_req_posedge_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \init_state_r_reg_n_0_[0]\, + O => prech_req_posedge_r_i_2_n_0 + ); +prech_req_posedge_r_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEFFFF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[2]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[4]\, + O => prech_req_posedge_r_i_3_n_0 + ); +prech_req_posedge_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => prech_req_posedge_r0, + Q => \^prech_req_posedge_r_reg_0\, + R => pi_dqs_found_done_r1_reg_0 + ); +prech_req_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEEEEEEEEFEEE" + ) + port map ( + I0 => rdlvl_prech_req, + I1 => wrcal_prech_req, + I2 => dqs_found_prech_req, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => \init_state_r_reg_n_0_[0]\, + I5 => prech_req_posedge_r_i_3_n_0, + O => prech_req + ); +prech_req_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => prech_req, + Q => prech_req_r, + R => pi_dqs_found_done_r1_reg_0 + ); +pwron_ce_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(9), + I1 => cnt_pwron_ce_r_reg(7), + I2 => pwron_ce_r_i_2_n_0, + I3 => cnt_pwron_ce_r_reg(6), + I4 => cnt_pwron_ce_r_reg(8), + O => pwron_ce_r_i_1_n_0 + ); +pwron_ce_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => cnt_pwron_ce_r_reg(5), + I1 => cnt_pwron_ce_r_reg(3), + I2 => cnt_pwron_ce_r_reg(1), + I3 => cnt_pwron_ce_r_reg(0), + I4 => cnt_pwron_ce_r_reg(2), + I5 => cnt_pwron_ce_r_reg(4), + O => pwron_ce_r_i_2_n_0 + ); +pwron_ce_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pwron_ce_r_i_1_n_0, + Q => pwron_ce_r, + R => pi_dqs_found_done_r1_reg_0 + ); +rdlvl_last_byte_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_last_byte_done, + Q => rdlvl_last_byte_done_r, + R => '0' + ); +\rdlvl_start_dly0_r_reg[13]_srl14\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '1', + A3 => '1', + CE => '1', + CLK => CLK, + D => rdlvl_start_pre, + Q => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\ + ); +\rdlvl_start_dly0_r_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rdlvl_start_dly0_r_reg[13]_srl14_n_0\, + Q => rdlvl_start_dly0_r(14), + R => '0' + ); +rdlvl_start_pre_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00008000" + ) + port map ( + I0 => pi_dqs_found_done, + I1 => \wrcal_reads[7]_i_5_n_0\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => detect_pi_found_dqs_i_2_n_0, + I4 => detect_pi_found_dqs_i_3_n_0, + I5 => rdlvl_start_pre, + O => rdlvl_start_pre_i_1_n_0 + ); +rdlvl_start_pre_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_start_pre_i_1_n_0, + Q => rdlvl_start_pre, + R => pi_dqs_found_done_r1_reg_0 + ); +rdlvl_stg1_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(3), + Q => \^rdlvl_stg1_done_r1_reg_0\, + R => '0' + ); +rdlvl_stg1_start_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFEFFFF00020000" + ) + port map ( + I0 => rdlvl_start_dly0_r(14), + I1 => prech_req_posedge_r_i_3_n_0, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[1]\, + I4 => pi_dqs_found_done, + I5 => \^rdlvl_stg1_start_reg_0\, + O => rdlvl_stg1_start_i_1_n_0 + ); +rdlvl_stg1_start_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_stg1_start_i_1_n_0, + Q => \^rdlvl_stg1_start_reg_0\, + R => pi_dqs_found_done_r1_reg_0 + ); +read_calib_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055550010" + ) + port map ( + I0 => \complex_wait_cnt_reg[3]_0\, + I1 => read_calib_i_2_n_0, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => \^phy_read_calib\, + I5 => \^pi_calib_done\, + O => read_calib_i_1_n_0 + ); +read_calib_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFDF" + ) + port map ( + I0 => \init_state_r_reg_n_0_[2]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[4]\, + O => read_calib_i_2_n_0 + ); +read_calib_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => read_calib_i_1_n_0, + Q => \^phy_read_calib\, + R => '0' + ); +\reg_ctrl_cnt_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => reg_ctrl_cnt_r_reg(0), + O => \p_0_in__2\(0) + ); +\reg_ctrl_cnt_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => reg_ctrl_cnt_r_reg(1), + I1 => reg_ctrl_cnt_r_reg(0), + O => \p_0_in__2\(1) + ); +\reg_ctrl_cnt_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => reg_ctrl_cnt_r_reg(2), + I1 => reg_ctrl_cnt_r_reg(0), + I2 => reg_ctrl_cnt_r_reg(1), + O => \p_0_in__2\(2) + ); +\reg_ctrl_cnt_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => init_state_r(6), + I2 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_5_n_0\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[2]\, + O => ddr2_pre_flag_r + ); +\reg_ctrl_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0008000000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[0]\, + I5 => \init_state_r_reg_n_0_[4]\, + O => reg_ctrl_cnt_r + ); +\reg_ctrl_cnt_r[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => reg_ctrl_cnt_r_reg(3), + I1 => reg_ctrl_cnt_r_reg(1), + I2 => reg_ctrl_cnt_r_reg(0), + I3 => reg_ctrl_cnt_r_reg(2), + O => \p_0_in__2\(3) + ); +\reg_ctrl_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => reg_ctrl_cnt_r, + D => \p_0_in__2\(0), + Q => reg_ctrl_cnt_r_reg(0), + R => ddr2_pre_flag_r + ); +\reg_ctrl_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => reg_ctrl_cnt_r, + D => \p_0_in__2\(1), + Q => reg_ctrl_cnt_r_reg(1), + R => ddr2_pre_flag_r + ); +\reg_ctrl_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => reg_ctrl_cnt_r, + D => \p_0_in__2\(2), + Q => reg_ctrl_cnt_r_reg(2), + R => ddr2_pre_flag_r + ); +\reg_ctrl_cnt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => reg_ctrl_cnt_r, + D => \p_0_in__2\(3), + Q => reg_ctrl_cnt_r_reg(3), + R => ddr2_pre_flag_r + ); +reset_rd_addr_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => complex_ocal_reset_rd_addr, + Q => reset_rd_addr_r1, + R => '0' + ); +\row_cnt_victim_rotate.complex_row_cnt[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0455" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I1 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\, + I2 => \^one_rank.stg1_wr_done_reg_0\, + I3 => complex_sample_cnt_inc_r2, + O => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00606666" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\, + I3 => \^one_rank.stg1_wr_done_reg_0\, + I4 => complex_sample_cnt_inc_r2, + O => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000780078787878" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\, + I4 => \^one_rank.stg1_wr_done_reg_0\, + I5 => complex_sample_cnt_inc_r2, + O => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00007F80" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\, + I4 => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => complex_sample_cnt_inc_r2, + I1 => \^one_rank.stg1_wr_done_reg_0\, + I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAEEEFAAAA" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\, + I1 => reset_rd_addr_r1, + I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\, + I3 => complex_sample_cnt_inc_r2, + I4 => \^one_rank.stg1_wr_done_reg_0\, + I5 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\, + I1 => \^one_rank.stg1_wr_done_reg_0\, + I2 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\, + O => complex_row_cnt + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1555555540000000" + ) + port map ( + I0 => complex_sample_cnt_inc_r2, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\, + I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\, + I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFB" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\, + I1 => \^rdlvl_stg1_done_r1_reg_0\, + I2 => \complex_wait_cnt_reg[3]_0\, + I3 => D(3), + O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\, + O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0101010101000101" + ) + port map ( + I0 => wr_victim_inc, + I1 => complex_sample_cnt_inc_r2, + I2 => reset_rd_addr_r1, + I3 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => complex_row1_rd_done_i_2_n_0, + O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000008" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\, + I1 => wr_victim_inc, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\, + I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\, + O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[4]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFBFFFFFF" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I5 => \complex_row_cnt_ocal[3]_i_7_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022226AAA" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\, + I1 => complex_row_cnt, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\, + I4 => complex_sample_cnt_inc_r2, + I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[5]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\, + O => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000262A" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\, + I1 => complex_row_cnt, + I2 => complex_sample_cnt_inc_r2, + I3 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\, + I4 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022226AAA" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\, + I1 => complex_row_cnt, + I2 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\, + I4 => complex_sample_cnt_inc_r2, + I5 => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\, + I4 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\, + I5 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\, + O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt[7]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF0000FD00" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0\, + I1 => reset_rd_addr_r1, + I2 => complex_sample_cnt_inc_r2, + I3 => \^one_rank.stg1_wr_done_reg_0\, + I4 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0\, + I5 => \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0\, + O => \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt, + D => \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0]\, + R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt, + D => \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1]\, + R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt, + D => \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2]\, + R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt, + D => \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3]\, + R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => complex_row_cnt, + D => \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + R => \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0\ + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\, + R => '0' + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\, + R => '0' + ); +\row_cnt_victim_rotate.complex_row_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0\, + Q => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\, + R => '0' + ); +rst_dqs_find_i_17: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^detect_pi_found_dqs\, + I1 => rst_dqs_find_i_12(0), + O => detect_pi_found_dqs_reg_0 + ); +\stg1_wr_rd_cnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt[8]_i_3_n_0\, + O => \stg1_wr_rd_cnt[0]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0D00000D0D0D0D0D" + ) + port map ( + I0 => stg1_wr_done, + I1 => D(3), + I2 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I5 => \stg1_wr_rd_cnt[4]_i_3_n_0\, + O => \stg1_wr_rd_cnt[1]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100000000000000" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => ddr3_lm_done_r_i_2_n_0, + O => stg1_wr_done + ); +\stg1_wr_rd_cnt[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FD57" + ) + port map ( + I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + O => \stg1_wr_rd_cnt[2]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00A8AAA8AAA800A8" + ) + port map ( + I0 => \stg1_wr_rd_cnt[4]_i_2_n_0\, + I1 => \stg1_wr_rd_cnt[3]_i_2_n_0\, + I2 => D(3), + I3 => \stg1_wr_rd_cnt[4]_i_3_n_0\, + I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + O => \stg1_wr_rd_cnt[3]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFD0FF" + ) + port map ( + I0 => complex_row0_rd_done, + I1 => complex_row1_rd_done, + I2 => complex_row1_wr_done, + I3 => complex_row0_wr_done, + I4 => wr_victim_inc, + O => \stg1_wr_rd_cnt[3]_i_2_n_0\ + ); +\stg1_wr_rd_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8288AAAA" + ) + port map ( + I0 => \stg1_wr_rd_cnt[4]_i_2_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I3 => \stg1_wr_rd_cnt[5]_i_2_n_0\, + I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\, + O => \stg1_wr_rd_cnt[4]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4555555555555555" + ) + port map ( + I0 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I1 => D(3), + I2 => \init_state_r[6]_i_3_n_0\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[3]\, + I5 => ddr3_lm_done_r_i_2_n_0, + O => \stg1_wr_rd_cnt[4]_i_2_n_0\ + ); +\stg1_wr_rd_cnt[4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AAA2" + ) + port map ( + I0 => complex_sample_cnt_inc_i_2_n_0, + I1 => \stg1_wr_rd_cnt[4]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[1]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => rdlvl_last_byte_done, + O => \stg1_wr_rd_cnt[4]_i_3_n_0\ + ); +\stg1_wr_rd_cnt[4]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00800000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[3]\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[2]\, + I3 => init_state_r(6), + I4 => \init_state_r_reg_n_0_[5]\, + O => \stg1_wr_rd_cnt[4]_i_4_n_0\ + ); +\stg1_wr_rd_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEBEEEEAAAAAAAA" + ) + port map ( + I0 => \stg1_wr_rd_cnt[6]_i_2_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I4 => \stg1_wr_rd_cnt[5]_i_2_n_0\, + I5 => \stg1_wr_rd_cnt[8]_i_3_n_0\, + O => \stg1_wr_rd_cnt[5]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[5]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + O => \stg1_wr_rd_cnt[5]_i_2_n_0\ + ); +\stg1_wr_rd_cnt[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF60" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I1 => \stg1_wr_rd_cnt[8]_i_6_n_0\, + I2 => \stg1_wr_rd_cnt[8]_i_3_n_0\, + I3 => \stg1_wr_rd_cnt[6]_i_2_n_0\, + O => \stg1_wr_rd_cnt[6]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[6]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002022" + ) + port map ( + I0 => \stg1_wr_rd_cnt[3]_i_2_n_0\, + I1 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I2 => D(3), + I3 => stg1_wr_done, + I4 => \stg1_wr_rd_cnt[4]_i_3_n_0\, + O => \stg1_wr_rd_cnt[6]_i_2_n_0\ + ); +\stg1_wr_rd_cnt[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A208" + ) + port map ( + I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\, + I1 => \stg1_wr_rd_cnt[8]_i_6_n_0\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + O => \stg1_wr_rd_cnt[7]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D5FF" + ) + port map ( + I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\, + I1 => D(3), + I2 => \stg1_wr_rd_cnt[8]_i_4_n_0\, + I3 => \stg1_wr_rd_cnt[8]_i_5_n_0\, + O => \stg1_wr_rd_cnt[8]_i_1_n_0\ + ); +\stg1_wr_rd_cnt[8]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A8AA0200" + ) + port map ( + I0 => \stg1_wr_rd_cnt[8]_i_3_n_0\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I3 => \stg1_wr_rd_cnt[8]_i_6_n_0\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + O => \stg1_wr_rd_cnt[8]_i_2_n_0\ + ); +\stg1_wr_rd_cnt[8]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00A2" + ) + port map ( + I0 => \stg1_wr_rd_cnt[4]_i_3_n_0\, + I1 => stg1_wr_done, + I2 => D(3), + I3 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => \stg1_wr_rd_cnt[8]_i_3_n_0\ + ); +\stg1_wr_rd_cnt[8]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000002000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[5]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[4]\, + I3 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => \stg1_wr_rd_cnt[8]_i_4_n_0\ + ); +\stg1_wr_rd_cnt[8]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFFFFFFFFFFFFFF" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[5]\, + I2 => \init_state_r_reg_n_0_[4]\, + I3 => prech_req_posedge_r_i_2_n_0, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[3]\, + O => \stg1_wr_rd_cnt[8]_i_5_n_0\ + ); +\stg1_wr_rd_cnt[8]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + O => \stg1_wr_rd_cnt[8]_i_6_n_0\ + ); +\stg1_wr_rd_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[0]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[0]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[1]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[1]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[2]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[2]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[3]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[3]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[4]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[4]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[5]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[5]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[6]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[6]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[7]_i_1_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[7]\, + R => '0' + ); +\stg1_wr_rd_cnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \stg1_wr_rd_cnt[8]_i_1_n_0\, + D => \stg1_wr_rd_cnt[8]_i_2_n_0\, + Q => \stg1_wr_rd_cnt_reg_n_0_[8]\, + R => '0' + ); +wl_sm_start_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_dqs_asrt_r1, + Q => wl_sm_start, + R => pi_dqs_found_done_r1_reg_0 + ); +\wr_done_victim_rotate.complex_row0_wr_done_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AE" + ) + port map ( + I0 => complex_row0_wr_done, + I1 => \^rdlvl_stg1_done_r1_reg_0\, + I2 => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\, + I3 => complex_row0_wr_done0, + O => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\ + ); +\wr_done_victim_rotate.complex_row0_wr_done_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => wr_victim_inc_i_2_n_0, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + O => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\ + ); +\wr_done_victim_rotate.complex_row0_wr_done_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF0011F011" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0\, + I1 => \wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0\, + I2 => wr_victim_inc, + I3 => D(3), + I4 => \complex_row_cnt_ocal[3]_i_4_n_0\, + I5 => \wr_done_victim_rotate.complex_row0_wr_done_i_5_n_0\, + O => complex_row0_wr_done0 + ); +\wr_done_victim_rotate.complex_row0_wr_done_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEFFFF" + ) + port map ( + I0 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6]\, + I1 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5]\, + I2 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4]\, + I3 => \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7]\, + I4 => wr_victim_inc, + O => \wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0\ + ); +\wr_done_victim_rotate.complex_row0_wr_done_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => complex_byte_rd_done, + I1 => \^prbs_rdlvl_done_pulse_reg_0\, + I2 => \complex_wait_cnt_reg[3]_0\, + O => \wr_done_victim_rotate.complex_row0_wr_done_i_5_n_0\ + ); +\wr_done_victim_rotate.complex_row0_wr_done_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0\, + Q => complex_row0_wr_done, + R => '0' + ); +\wr_done_victim_rotate.complex_row1_wr_done_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00AE" + ) + port map ( + I0 => complex_row1_wr_done, + I1 => complex_row0_wr_done, + I2 => \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0\, + I3 => complex_row0_wr_done0, + O => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\ + ); +\wr_done_victim_rotate.complex_row1_wr_done_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0\, + Q => complex_row1_wr_done, + R => '0' + ); +\wr_en_inferred__0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"54" + ) + port map ( + I0 => \wr_en_inferred__0_i_1_0\, + I1 => \^calib_ctl_wren_reg_0\, + I2 => \wr_ptr_timing_reg[0]_0\, + O => \my_empty_reg[3]\ + ); +\wr_en_inferred__0_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"54" + ) + port map ( + I0 => \wr_en_inferred__0_i_1__0_0\, + I1 => \^calib_ctl_wren_reg_0\, + I2 => \wr_ptr_timing_reg[0]_0\, + O => \my_empty_reg[3]_0\ + ); +\wr_en_inferred__0_i_1__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"54" + ) + port map ( + I0 => \wr_en_inferred__0_i_1__1_0\, + I1 => \^calib_ctl_wren_reg_0\, + I2 => \wr_ptr_timing_reg[0]_0\, + O => \my_empty_reg[3]_1\ + ); +wr_level_dqs_asrt_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"00A8" + ) + port map ( + I0 => \en_cnt_div4.wrlvl_odt_i_2_n_0\, + I1 => wrlvl_active_r1, + I2 => wr_level_dqs_asrt, + I3 => \complex_wait_cnt_reg[3]_0\, + O => wr_level_dqs_asrt_i_1_n_0 + ); +wr_level_dqs_asrt_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_dqs_asrt, + Q => wr_level_dqs_asrt_r1, + R => '0' + ); +wr_level_dqs_asrt_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_dqs_asrt_i_1_n_0, + Q => wr_level_dqs_asrt, + R => '0' + ); +wr_lvl_start_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000EA00" + ) + port map ( + I0 => \^wr_lvl_start_reg_0\, + I1 => dqs_asrt_cnt(0), + I2 => dqs_asrt_cnt(1), + I3 => wrlvl_active, + I4 => \complex_wait_cnt_reg[3]_0\, + O => wr_lvl_start_i_1_n_0 + ); +wr_lvl_start_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_lvl_start_i_1_n_0, + Q => \^wr_lvl_start_reg_0\, + R => '0' + ); +\wr_ptr[2]_i_1__3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"54" + ) + port map ( + I0 => \wr_ptr_timing_reg[0]\, + I1 => \^calib_ctl_wren_reg_0\, + I2 => \wr_ptr_timing_reg[0]_0\, + O => E(0) + ); +\wr_ptr[2]_i_1__4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"54" + ) + port map ( + I0 => \wr_ptr_timing_reg[0]_1\, + I1 => \^calib_ctl_wren_reg_0\, + I2 => \wr_ptr_timing_reg[0]_0\, + O => \my_empty_reg[5]\(0) + ); +\wr_ptr[2]_i_1__5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"54" + ) + port map ( + I0 => \wr_ptr_timing_reg[0]_2\, + I1 => \^calib_ctl_wren_reg_0\, + I2 => \wr_ptr_timing_reg[0]_0\, + O => \my_empty_reg[5]_0\(0) + ); +wr_victim_inc_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000100000" + ) + port map ( + I0 => wr_victim_inc_i_2_n_0, + I1 => \stg1_wr_rd_cnt_reg_n_0_[0]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[1]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[2]\, + I4 => complex_row0_wr_done, + I5 => \^one_rank.stg1_wr_done_reg_0\, + O => wr_victim_inc0 + ); +wr_victim_inc_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \stg1_wr_rd_cnt_reg_n_0_[4]\, + I1 => \stg1_wr_rd_cnt_reg_n_0_[3]\, + I2 => \stg1_wr_rd_cnt_reg_n_0_[6]\, + I3 => \stg1_wr_rd_cnt_reg_n_0_[5]\, + I4 => \stg1_wr_rd_cnt_reg_n_0_[7]\, + I5 => \stg1_wr_rd_cnt_reg_n_0_[8]\, + O => wr_victim_inc_i_2_n_0 + ); +wr_victim_inc_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_victim_inc0, + Q => wr_victim_inc, + R => pi_dqs_found_done_r1_reg_0 + ); +wrcal_final_chk_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0040" + ) + port map ( + I0 => wrcal_final_chk_i_2_n_0, + I1 => \init_state_r[3]_i_1_n_0\, + I2 => \init_state_r[0]_i_1_n_0\, + I3 => \init_state_r[5]_i_1_n_0\, + I4 => wrcal_final_chk, + O => wrcal_final_chk_i_1_n_0 + ); +wrcal_final_chk_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF7F" + ) + port map ( + I0 => \init_state_r[4]_i_1_n_0\, + I1 => burst_addr_r_reg_0, + I2 => \init_state_r[1]_i_1_n_0\, + I3 => \init_state_r[2]_i_2_n_0\, + O => wrcal_final_chk_i_2_n_0 + ); +wrcal_final_chk_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_final_chk_i_1_n_0, + Q => wrcal_final_chk, + R => pi_dqs_found_done_r1_reg_0 + ); +wrcal_rd_wait_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000020000000000" + ) + port map ( + I0 => \wrcal_reads[7]_i_5_n_0\, + I1 => \init_state_r_reg_n_0_[4]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[2]\, + O => wrcal_rd_wait_i_1_n_0 + ); +wrcal_rd_wait_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_rd_wait_i_1_n_0, + Q => wrcal_rd_wait, + R => pi_dqs_found_done_r1_reg_0 + ); +\wrcal_reads[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => wrcal_reads, + I1 => \wrcal_reads_reg_n_0_[0]\, + O => \wrcal_reads[0]_i_1_n_0\ + ); +\wrcal_reads[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F9" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[0]\, + I1 => \wrcal_reads_reg_n_0_[1]\, + I2 => wrcal_reads, + O => \wrcal_reads[1]_i_1_n_0\ + ); +\wrcal_reads[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFE1" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[1]\, + I1 => \wrcal_reads_reg_n_0_[0]\, + I2 => \wrcal_reads_reg_n_0_[2]\, + I3 => wrcal_reads, + O => \wrcal_reads[2]_i_1_n_0\ + ); +\wrcal_reads[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFE01" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[0]\, + I1 => \wrcal_reads_reg_n_0_[1]\, + I2 => \wrcal_reads_reg_n_0_[2]\, + I3 => \wrcal_reads_reg_n_0_[3]\, + I4 => wrcal_reads, + O => \wrcal_reads[3]_i_1_n_0\ + ); +\wrcal_reads[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFE0001" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[2]\, + I1 => \wrcal_reads_reg_n_0_[1]\, + I2 => \wrcal_reads_reg_n_0_[0]\, + I3 => \wrcal_reads_reg_n_0_[3]\, + I4 => \wrcal_reads_reg_n_0_[4]\, + I5 => wrcal_reads, + O => \wrcal_reads[4]_i_1_n_0\ + ); +\wrcal_reads[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"F6" + ) + port map ( + I0 => \wrcal_reads[7]_i_8_n_0\, + I1 => \wrcal_reads_reg_n_0_[5]\, + I2 => wrcal_reads, + O => \wrcal_reads[5]_i_1_n_0\ + ); +\wrcal_reads[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFD2" + ) + port map ( + I0 => \wrcal_reads[7]_i_8_n_0\, + I1 => \wrcal_reads_reg_n_0_[5]\, + I2 => \wrcal_reads_reg_n_0_[6]\, + I3 => wrcal_reads, + O => \wrcal_reads[6]_i_1_n_0\ + ); +\wrcal_reads[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAEAAAAAAAA" + ) + port map ( + I0 => \complex_wait_cnt_reg[3]_0\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \wrcal_reads[7]_i_4_n_0\, + I3 => \init_state_r_reg_n_0_[3]\, + I4 => \init_state_r_reg_n_0_[4]\, + I5 => \wrcal_reads[7]_i_5_n_0\, + O => wrcal_reads05_out + ); +\wrcal_reads[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \wrcal_reads[7]_i_6_n_0\, + I1 => \wrcal_reads_reg_n_0_[0]\, + I2 => wrcal_reads, + O => \wrcal_reads[7]_i_2_n_0\ + ); +\wrcal_reads[7]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFD02" + ) + port map ( + I0 => \wrcal_reads[7]_i_8_n_0\, + I1 => \wrcal_reads_reg_n_0_[5]\, + I2 => \wrcal_reads_reg_n_0_[6]\, + I3 => \wrcal_reads_reg_n_0_[7]\, + I4 => wrcal_reads, + O => \wrcal_reads[7]_i_3_n_0\ + ); +\wrcal_reads[7]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => init_state_r(6), + I1 => \init_state_r_reg_n_0_[5]\, + O => \wrcal_reads[7]_i_4_n_0\ + ); +\wrcal_reads[7]_i_5\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \init_state_r_reg_n_0_[0]\, + I1 => \init_state_r_reg_n_0_[1]\, + O => \wrcal_reads[7]_i_5_n_0\ + ); +\wrcal_reads[7]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[7]\, + I1 => \wrcal_reads_reg_n_0_[2]\, + I2 => \wrcal_reads_reg_n_0_[4]\, + I3 => \wrcal_reads_reg_n_0_[1]\, + I4 => \wrcal_reads_reg_n_0_[3]\, + I5 => \wrcal_reads[7]_i_9_n_0\, + O => \wrcal_reads[7]_i_6_n_0\ + ); +\wrcal_reads[7]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000010" + ) + port map ( + I0 => read_calib_i_2_n_0, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \wrcal_reads[7]_i_6_n_0\, + I4 => \wrcal_reads_reg_n_0_[0]\, + O => wrcal_reads + ); +\wrcal_reads[7]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[3]\, + I1 => \wrcal_reads_reg_n_0_[0]\, + I2 => \wrcal_reads_reg_n_0_[1]\, + I3 => \wrcal_reads_reg_n_0_[2]\, + I4 => \wrcal_reads_reg_n_0_[4]\, + O => \wrcal_reads[7]_i_8_n_0\ + ); +\wrcal_reads[7]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \wrcal_reads_reg_n_0_[6]\, + I1 => \wrcal_reads_reg_n_0_[5]\, + O => \wrcal_reads[7]_i_9_n_0\ + ); +\wrcal_reads_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[0]_i_1_n_0\, + Q => \wrcal_reads_reg_n_0_[0]\, + R => wrcal_reads05_out + ); +\wrcal_reads_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[1]_i_1_n_0\, + Q => \wrcal_reads_reg_n_0_[1]\, + R => wrcal_reads05_out + ); +\wrcal_reads_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[2]_i_1_n_0\, + Q => \wrcal_reads_reg_n_0_[2]\, + R => wrcal_reads05_out + ); +\wrcal_reads_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[3]_i_1_n_0\, + Q => \wrcal_reads_reg_n_0_[3]\, + R => wrcal_reads05_out + ); +\wrcal_reads_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[4]_i_1_n_0\, + Q => \wrcal_reads_reg_n_0_[4]\, + R => wrcal_reads05_out + ); +\wrcal_reads_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[5]_i_1_n_0\, + Q => \wrcal_reads_reg_n_0_[5]\, + R => wrcal_reads05_out + ); +\wrcal_reads_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[6]_i_1_n_0\, + Q => \wrcal_reads_reg_n_0_[6]\, + R => wrcal_reads05_out + ); +\wrcal_reads_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_reads[7]_i_2_n_0\, + D => \wrcal_reads[7]_i_3_n_0\, + Q => \wrcal_reads_reg_n_0_[7]\, + R => wrcal_reads05_out + ); +wrcal_resume_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_resume_w, + Q => wrcal_resume_r, + R => '0' + ); +wrcal_sanity_chk_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_final_chk, + Q => wrcal_sanity_chk, + R => '0' + ); +\wrcal_start_dly_r_reg[4]_srl5\: unisim.vcomponents.SRL16E + port map ( + A0 => '0', + A1 => '0', + A2 => '1', + A3 => '0', + CE => '1', + CLK => CLK, + D => wrcal_start_pre, + Q => \wrcal_start_dly_r_reg[4]_srl5_n_0\ + ); +\wrcal_start_dly_r_reg[4]_srl5_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0001010000000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => \wrcal_reads[7]_i_4_n_0\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \init_state_r_reg_n_0_[1]\, + I5 => \init_state_r_reg_n_0_[0]\, + O => wrcal_start_pre + ); +\wrcal_start_dly_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wrcal_start_dly_r_reg[4]_srl5_n_0\, + Q => wrcal_start_dly_r(5), + R => '0' + ); +wrcal_start_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"000E" + ) + port map ( + I0 => \^wrcal_start_reg_0\, + I1 => wrcal_start_dly_r(5), + I2 => wrlvl_byte_redo, + I3 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => wrcal_start_i_1_n_0 + ); +wrcal_start_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_start_i_1_n_0, + Q => \^wrcal_start_reg_0\, + R => '0' + ); +\wrcal_wr_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => wrcal_wr_cnt_reg(0), + O => \wrcal_wr_cnt[0]_i_1_n_0\ + ); +\wrcal_wr_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => wrcal_wr_cnt_reg(0), + I1 => wrcal_wr_cnt_reg(1), + O => \wrcal_wr_cnt[1]_i_1_n_0\ + ); +\wrcal_wr_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"E1" + ) + port map ( + I0 => wrcal_wr_cnt_reg(0), + I1 => wrcal_wr_cnt_reg(1), + I2 => wrcal_wr_cnt_reg(2), + O => wrcal_wr_cnt0(2) + ); +\wrcal_wr_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFAAAAAAAB" + ) + port map ( + I0 => \wrcal_wr_cnt[3]_i_4_n_0\, + I1 => wrcal_wr_cnt_reg(1), + I2 => wrcal_wr_cnt_reg(0), + I3 => wrcal_wr_cnt_reg(3), + I4 => wrcal_wr_cnt_reg(2), + I5 => \complex_wait_cnt_reg[3]_0\, + O => \wrcal_wr_cnt[3]_i_1_n_0\ + ); +\wrcal_wr_cnt[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000010000" + ) + port map ( + I0 => \init_state_r[6]_i_4_n_0\, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => init_state_r(6), + O => \wrcal_wr_cnt[3]_i_2_n_0\ + ); +\wrcal_wr_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCC9" + ) + port map ( + I0 => wrcal_wr_cnt_reg(2), + I1 => wrcal_wr_cnt_reg(3), + I2 => wrcal_wr_cnt_reg(0), + I3 => wrcal_wr_cnt_reg(1), + O => wrcal_wr_cnt0(3) + ); +\wrcal_wr_cnt[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000020000" + ) + port map ( + I0 => prech_req_posedge_r_i_2_n_0, + I1 => \init_state_r_reg_n_0_[2]\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[4]\, + I4 => \init_state_r_reg_n_0_[5]\, + I5 => init_state_r(6), + O => \wrcal_wr_cnt[3]_i_4_n_0\ + ); +\wrcal_wr_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_wr_cnt[3]_i_2_n_0\, + D => \wrcal_wr_cnt[0]_i_1_n_0\, + Q => wrcal_wr_cnt_reg(0), + R => \wrcal_wr_cnt[3]_i_1_n_0\ + ); +\wrcal_wr_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_wr_cnt[3]_i_2_n_0\, + D => \wrcal_wr_cnt[1]_i_1_n_0\, + Q => wrcal_wr_cnt_reg(1), + R => \wrcal_wr_cnt[3]_i_1_n_0\ + ); +\wrcal_wr_cnt_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \wrcal_wr_cnt[3]_i_2_n_0\, + D => wrcal_wr_cnt0(2), + Q => wrcal_wr_cnt_reg(2), + S => \wrcal_wr_cnt[3]_i_1_n_0\ + ); +\wrcal_wr_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrcal_wr_cnt[3]_i_2_n_0\, + D => wrcal_wr_cnt0(3), + Q => wrcal_wr_cnt_reg(3), + R => \wrcal_wr_cnt[3]_i_1_n_0\ + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^first_wrcal_pat_r\, + I1 => D(3), + O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1_n_0\ + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^first_wrcal_pat_r\, + I1 => D(3), + O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2_n_0\ + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^first_rdlvl_pat_r\, + I1 => D(3), + O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1_n_0\ + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[109]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => D(2), + Q => phy_wrdata(109), + R => '0' + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[111]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => D(3), + Q => phy_wrdata(111), + R => '0' + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[121]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1_n_0\, + Q => phy_wrdata(121), + R => '0' + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[123]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => D(4), + Q => phy_wrdata(123), + R => '0' + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2_n_0\, + Q => phy_wrdata(126), + R => '0' + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => D(0), + Q => phy_wrdata(13), + R => '0' + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1_n_0\, + Q => phy_wrdata(25), + R => '0' + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0), + D => D(1), + Q => phy_wrdata(46), + R => '0' + ); +write_calib_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000007F7F7F00" + ) + port map ( + I0 => done_dqs_tap_inc, + I1 => \init_state_r_reg_n_0_[1]\, + I2 => write_calib_i_2_n_0, + I3 => wrlvl_active_r1, + I4 => \^phy_write_calib\, + I5 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => write_calib_i_1_n_0 + ); +write_calib_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100000000" + ) + port map ( + I0 => \init_state_r_reg_n_0_[4]\, + I1 => init_state_r(6), + I2 => \init_state_r_reg_n_0_[0]\, + I3 => \init_state_r_reg_n_0_[5]\, + I4 => \init_state_r_reg_n_0_[2]\, + I5 => \init_state_r_reg_n_0_[3]\, + O => write_calib_i_2_n_0 + ); +write_calib_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => write_calib_i_1_n_0, + Q => \^phy_write_calib\, + R => '0' + ); +wrlvl_active_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000005540" + ) + port map ( + I0 => done_dqs_tap_inc, + I1 => wrlvl_odt, + I2 => \en_cnt_div4.wrlvl_odt_i_2_n_0\, + I3 => wrlvl_active, + I4 => wrlvl_rank_done, + I5 => \complex_wait_cnt_reg[3]_0\, + O => wrlvl_active_i_1_n_0 + ); +wrlvl_active_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_active, + Q => wrlvl_active_r1, + R => '0' + ); +wrlvl_active_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_active_i_1_n_0, + Q => wrlvl_active, + R => '0' + ); +wrlvl_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_done_r, + Q => \^wrlvl_done_r1\, + R => '0' + ); +wrlvl_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_done_r_reg_0, + Q => wrlvl_done_r, + R => '0' + ); +wrlvl_final_if_rst_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000004454" + ) + port map ( + I0 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + I1 => \^wrlvl_final_if_rst\, + I2 => wrlvl_done_r, + I3 => wrlvl_final_if_rst_i_2_n_0, + I4 => \num_refresh[3]_i_6_n_0\, + I5 => \wrcal_wr_cnt[3]_i_2_n_0\, + O => wrlvl_final_if_rst_i_1_n_0 + ); +wrlvl_final_if_rst_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFF7" + ) + port map ( + I0 => \init_state_r_reg_n_0_[1]\, + I1 => \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_6_n_0\, + I2 => \init_state_r_reg_n_0_[5]\, + I3 => \init_state_r_reg_n_0_[0]\, + I4 => init_state_r(6), + I5 => \init_state_r_reg_n_0_[4]\, + O => wrlvl_final_if_rst_i_2_n_0 + ); +wrlvl_final_if_rst_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_final_if_rst_i_1_n_0, + Q => \^wrlvl_final_if_rst\, + R => '0' + ); +wrlvl_odt_ctl_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA20" + ) + port map ( + I0 => wrlvl_odt_ctl_i_2_n_0, + I1 => wrlvl_rank_done_r1, + I2 => wrlvl_rank_done, + I3 => wrlvl_odt_ctl, + I4 => \back_to_back_reads_4_1.num_reads_reg[1]_0\, + O => wrlvl_odt_ctl_i_1_n_0 + ); +wrlvl_odt_ctl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"F7FFF7FFF7FFFFFF" + ) + port map ( + I0 => prech_req_posedge_r_i_2_n_0, + I1 => \init_state_r[6]_i_3_n_0\, + I2 => \init_state_r_reg_n_0_[3]\, + I3 => \init_state_r_reg_n_0_[2]\, + I4 => \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_9_n_0\, + I5 => init_state_r1(3), + O => wrlvl_odt_ctl_i_2_n_0 + ); +wrlvl_odt_ctl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_odt_ctl_i_1_n_0, + Q => wrlvl_odt_ctl, + R => '0' + ); +wrlvl_rank_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_rank_done, + Q => wrlvl_rank_done_r1, + R => '0' + ); +wrlvl_rank_done_r6_reg_srl5: unisim.vcomponents.SRL16E + port map ( + A0 => '0', + A1 => '0', + A2 => '1', + A3 => '0', + CE => '1', + CLK => CLK, + D => wrlvl_rank_done_r1, + Q => wrlvl_rank_done_r6_reg_srl5_n_0 + ); +wrlvl_rank_done_r7_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_rank_done_r6_reg_srl5_n_0, + Q => wrlvl_rank_done_r7, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_rdlvl is + port ( + \rd_mux_sel_r_reg[0]_0\ : out STD_LOGIC; + new_cnt_cpt_r_reg_0 : out STD_LOGIC; + samp_edge_cnt0_en_r : out STD_LOGIC; + idelay_ce_int : out STD_LOGIC; + idelay_inc_int : out STD_LOGIC; + rdlvl_prech_req : out STD_LOGIC; + pi_fine_dly_dec_done_reg_0 : out STD_LOGIC; + pi_cnt_dec_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 4 downto 0 ); + rdlvl_stg1_rank_done : out STD_LOGIC; + rdlvl_last_byte_done : out STD_LOGIC; + rdlvl_pi_incdec : out STD_LOGIC; + \calib_sel_reg[1]\ : out STD_LOGIC; + \calib_sel_reg[1]_0\ : out STD_LOGIC; + \calib_sel_reg[1]_1\ : out STD_LOGIC; + pi_en_stg2_f_reg_0 : out STD_LOGIC; + pi_stg2_f_incdec_reg_0 : out STD_LOGIC; + pi_stg2_load_reg_0 : out STD_LOGIC; + rdlvl_stg1_done_int_reg_0 : out STD_LOGIC; + rdlvl_last_byte_done_int_reg_0 : out STD_LOGIC; + p_1_in : out STD_LOGIC; + \cal1_cnt_cpt_r_reg[0]_0\ : out STD_LOGIC; + rdlvl_stg1_done_int_reg_1 : out STD_LOGIC; + rdlvl_last_byte_done_int_reg_1 : out STD_LOGIC; + \po_stg2_wrcal_cnt_reg[1]\ : out STD_LOGIC; + \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC; + reset_if_reg : out STD_LOGIC; + COUNTERLOADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \pi_stg2_reg_l_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \done_cnt_reg[1]_0\ : in STD_LOGIC; + CLK : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + mpr_rdlvl_start_r_reg_0 : in STD_LOGIC; + rdlvl_stg1_start_r_reg_0 : in STD_LOGIC; + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + dqs_po_dec_done_r1_reg_0 : in STD_LOGIC; + \samp_edge_cnt1_r_reg[0]_0\ : in STD_LOGIC; + sr_valid_r_reg_0 : in STD_LOGIC; + \FSM_onehot_cal1_state_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + found_second_edge_r_reg_0 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC; + tempmon_pi_f_en_r : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC; + calib_zero_inputs : in STD_LOGIC; + tempmon_pi_f_inc_r : in STD_LOGIC; + \done_cnt_reg[2]_0\ : in STD_LOGIC; + pi_dqs_found_done : in STD_LOGIC; + \init_state_r[4]_i_25\ : in STD_LOGIC; + po_cnt_dec_reg : in STD_LOGIC; + \pi_rdval_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \idelay_tap_cnt_r_reg[0][0][0]_0\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + prech_done : in STD_LOGIC; + store_sr_req_r_reg_0 : in STD_LOGIC; + address_w : in STD_LOGIC_VECTOR ( 0 to 0 ); + pi_calib_done : in STD_LOGIC; + first_rdlvl_pat_r : in STD_LOGIC; + first_wrcal_pat_r : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : in STD_LOGIC; + reset_if : in STD_LOGIC; + reset_if_reg_0 : in STD_LOGIC; + reset_if_r9 : in STD_LOGIC; + reset_if_reg_1 : in STD_LOGIC; + \idelay_tap_cnt_r_reg[0][1][4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \tap_cnt_cpt_r_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cnt_shift_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_rdlvl : entity is "mig_7series_v4_2_ddr_phy_rdlvl"; +end ddr3_mig_7series_v4_2_ddr_phy_rdlvl; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_rdlvl is + signal \^d\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \FSM_onehot_cal1_state_r[10]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[11]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[13]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[14]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[14]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[15]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[15]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[15]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[16]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[16]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[16]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[20]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[21]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[21]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[21]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[22]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[22]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[29]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_10_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_11_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_12_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_13_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_3_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_4_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_5_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_6_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_7_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[34]_i_9_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[5]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[5]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[6]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[6]_i_2_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[7]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r[9]_i_1_n_0\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[12]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[15]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[16]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[1]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[22]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[29]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[31]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[34]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[3]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[7]\ : STD_LOGIC; + signal \FSM_onehot_cal1_state_r_reg_n_0_[8]\ : STD_LOGIC; + signal cal1_cnt_cpt_r : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \cal1_cnt_cpt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \^cal1_cnt_cpt_r_reg[0]_0\ : STD_LOGIC; + signal \cal1_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC; + signal cal1_dlyce_cpt_r : STD_LOGIC; + signal cal1_dlyce_cpt_r_reg_n_0 : STD_LOGIC; + signal cal1_dlyinc_cpt_r : STD_LOGIC; + signal cal1_dlyinc_cpt_r_reg_n_0 : STD_LOGIC; + signal cal1_dq_idel_ce : STD_LOGIC; + signal cal1_dq_idel_inc : STD_LOGIC; + signal cal1_prech_req_r : STD_LOGIC; + signal \cal1_prech_req_r__0\ : STD_LOGIC; + signal \cal1_state_r1[0]_i_1_n_0\ : STD_LOGIC; + signal \cal1_state_r1[0]_i_2_n_0\ : STD_LOGIC; + signal \cal1_state_r1[1]_i_1_n_0\ : STD_LOGIC; + signal \cal1_state_r1[1]_i_2_n_0\ : STD_LOGIC; + signal \cal1_state_r1[1]_i_3_n_0\ : STD_LOGIC; + signal \cal1_state_r1[2]_i_1_n_0\ : STD_LOGIC; + signal \cal1_state_r1[2]_i_2_n_0\ : STD_LOGIC; + signal \cal1_state_r1[3]_i_1_n_0\ : STD_LOGIC; + signal \cal1_state_r1[3]_i_2_n_0\ : STD_LOGIC; + signal \cal1_state_r1[3]_i_3_n_0\ : STD_LOGIC; + signal \cal1_state_r1[4]_i_1_n_0\ : STD_LOGIC; + signal \cal1_state_r1[5]_i_1_n_0\ : STD_LOGIC; + signal \cal1_state_r1_reg_n_0_[0]\ : STD_LOGIC; + signal \cal1_state_r1_reg_n_0_[1]\ : STD_LOGIC; + signal \cal1_state_r1_reg_n_0_[2]\ : STD_LOGIC; + signal \cal1_state_r1_reg_n_0_[3]\ : STD_LOGIC; + signal \cal1_state_r1_reg_n_0_[4]\ : STD_LOGIC; + signal \cal1_state_r1_reg_n_0_[5]\ : STD_LOGIC; + signal cal1_wait_cnt_en_r : STD_LOGIC; + signal cal1_wait_cnt_en_r0 : STD_LOGIC; + signal cal1_wait_cnt_en_r_i_2_n_0 : STD_LOGIC; + signal \cal1_wait_cnt_r[4]_i_1_n_0\ : STD_LOGIC; + signal cal1_wait_cnt_r_reg : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal cal1_wait_r : STD_LOGIC; + signal cal1_wait_r_i_1_n_0 : STD_LOGIC; + signal cnt_idel_dec_cpt_r : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal cnt_idel_dec_cpt_r1 : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \cnt_idel_dec_cpt_r[0]_i_2_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[0]_i_3_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[1]_i_2_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[1]_i_3_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[1]_i_4_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_11_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_12_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_13_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_14_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_15_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_3_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_4_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_5_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_6_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_7_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_8_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[2]_i_9_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[3]_i_2_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[3]_i_3_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[3]_i_4_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[3]_i_5_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[3]_i_6_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_10_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_11_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_12_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_13_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_14_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_3_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_4_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_5_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_6_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_7_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[4]_i_9_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[5]_i_1_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[5]_i_4_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[5]_i_5_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[5]_i_6_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r[5]_i_7_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg[5]_i_3_n_0\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg_n_0_[0]\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg_n_0_[1]\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg_n_0_[2]\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg_n_0_[3]\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg_n_0_[4]\ : STD_LOGIC; + signal \cnt_idel_dec_cpt_r_reg_n_0_[5]\ : STD_LOGIC; + signal cnt_shift_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal detect_edge_done_r : STD_LOGIC; + signal detect_edge_done_r_i_1_n_0 : STD_LOGIC; + signal detect_edge_done_r_i_2_n_0 : STD_LOGIC; + signal done_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal done_cnt1 : STD_LOGIC; + signal \done_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \done_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \done_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \done_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \done_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal dqs_po_dec_done_r1 : STD_LOGIC; + signal dqs_po_dec_done_r2 : STD_LOGIC; + signal fine_dly_dec_done_r1 : STD_LOGIC; + signal fine_dly_dec_done_r1_i_1_n_0 : STD_LOGIC; + signal fine_dly_dec_done_r1_i_2_n_0 : STD_LOGIC; + signal fine_dly_dec_done_r2 : STD_LOGIC; + signal \first_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC; + signal \first_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC; + signal \first_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC; + signal \first_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC; + signal \first_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC; + signal \first_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC; + signal \first_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC; + signal \first_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC; + signal \first_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC; + signal found_edge_r_i_1_n_0 : STD_LOGIC; + signal found_edge_r_i_2_n_0 : STD_LOGIC; + signal found_edge_r_reg_n_0 : STD_LOGIC; + signal found_first_edge_r_i_1_n_0 : STD_LOGIC; + signal found_first_edge_r_reg_n_0 : STD_LOGIC; + signal found_second_edge_r_i_1_n_0 : STD_LOGIC; + signal found_second_edge_r_reg_n_0 : STD_LOGIC; + signal found_stable_eye_last_r : STD_LOGIC; + signal found_stable_eye_last_r_i_1_n_0 : STD_LOGIC; + signal found_stable_eye_r_i_1_n_0 : STD_LOGIC; + signal found_stable_eye_r_i_2_n_0 : STD_LOGIC; + signal found_stable_eye_r_reg_n_0 : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_139\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_155\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_163\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_187\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_171\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_147\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_179\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_195\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_75\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_107\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_131\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_123\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_91\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_99\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_115\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_83\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_140\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_156\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_164\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_188\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_172\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_148\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_180\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_196\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_76\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_108\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_132\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_124\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_92\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_100\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_116\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_84\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_141\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_157\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_165\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_189\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_173\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_149\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_181\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_197\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_77\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_109\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_133\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_125\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_93\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_101\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_117\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_85\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_142\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_158\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_166\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_190\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_174\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_150\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_182\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_198\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_78\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_110\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_134\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_126\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_94\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_102\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_118\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_86\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_143\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_159\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_167\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_191\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_175\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_151\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_183\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_199\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_79\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_111\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_135\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_127\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_95\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_103\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_119\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_87\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_144\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_160\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_168\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_192\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_176\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_152\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_184\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_200\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_80\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_112\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_136\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_128\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_96\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_104\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_120\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_88\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_145\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_161\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_169\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_193\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_177\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_153\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_185\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_201\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_81\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_113\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_137\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_129\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_97\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_105\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_121\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_89\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_146\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_162\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_170\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_194\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_178\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_154\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_186\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_202\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_82\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_114\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_138\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_130\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_98\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_106\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_122\ : STD_LOGIC; + signal \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_90\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_data_match_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_data_match_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0\ : STD_LOGIC; + signal \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\ : STD_LOGIC; + signal idel_adj_inc_i_1_n_0 : STD_LOGIC; + signal idel_adj_inc_reg_n_0 : STD_LOGIC; + signal idel_dec_cnt : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \idel_dec_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \idel_dec_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \idel_dec_cnt[4]_i_3_n_0\ : STD_LOGIC; + signal \idel_dec_cnt[4]_i_4_n_0\ : STD_LOGIC; + signal \idel_dec_cnt[4]_i_5_n_0\ : STD_LOGIC; + signal \idel_dec_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \idel_dec_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \idel_dec_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \idel_dec_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \idel_dec_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal idel_mpr_pat_detect_r : STD_LOGIC; + signal idel_pat0_data_match_r0 : STD_LOGIC; + signal idel_pat0_match_fall0_and_r : STD_LOGIC; + signal idel_pat0_match_fall1_and_r : STD_LOGIC; + signal idel_pat0_match_fall2_and_r : STD_LOGIC; + signal idel_pat0_match_fall3_and_r : STD_LOGIC; + signal idel_pat0_match_rise0_and_r : STD_LOGIC; + signal idel_pat0_match_rise1_and_r : STD_LOGIC; + signal idel_pat0_match_rise2_and_r : STD_LOGIC; + signal idel_pat0_match_rise3_and_r : STD_LOGIC; + signal idel_pat0_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal idel_pat1_data_match_r0 : STD_LOGIC; + signal idel_pat1_match_fall0_and_r : STD_LOGIC; + signal idel_pat1_match_fall1_and_r : STD_LOGIC; + signal idel_pat1_match_fall2_and_r : STD_LOGIC; + signal idel_pat1_match_fall3_and_r : STD_LOGIC; + signal idel_pat1_match_rise0_and_r : STD_LOGIC; + signal idel_pat1_match_rise1_and_r : STD_LOGIC; + signal idel_pat1_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal idel_pat1_match_rise2_and_r : STD_LOGIC; + signal idel_pat1_match_rise3_and_r : STD_LOGIC; + signal idel_pat_detect_valid_r_i_1_n_0 : STD_LOGIC; + signal idel_pat_detect_valid_r_reg_n_0 : STD_LOGIC; + signal \^idelay_ce_int\ : STD_LOGIC; + signal \^idelay_inc_int\ : STD_LOGIC; + signal idelay_tap_cnt_r : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \idelay_tap_cnt_r[0][0][4]_i_1_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r[0][0][4]_i_3_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r[0][1][0]_i_1_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r[0][1][1]_i_1_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r[0][1][2]_i_1_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r[0][1][3]_i_1_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r[0][1][4]_i_2_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r[0][1][4]_i_3_n_0\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC; + signal \idelay_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC; + signal idelay_tap_cnt_slice_r : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal idelay_tap_limit_r_i_1_n_0 : STD_LOGIC; + signal idelay_tap_limit_r_i_2_n_0 : STD_LOGIC; + signal idelay_tap_limit_r_reg_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r : STD_LOGIC; + signal \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\ : STD_LOGIC; + signal \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\ : STD_LOGIC; + signal \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\ : STD_LOGIC; + signal \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\ : STD_LOGIC; + signal \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\ : STD_LOGIC; + signal \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\ : STD_LOGIC; + signal \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\ : STD_LOGIC; + signal \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\ : STD_LOGIC; + signal \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal mpr_dec_cpt_r : STD_LOGIC; + signal mpr_dec_cpt_r_i_1_n_0 : STD_LOGIC; + signal mpr_dec_cpt_r_reg_n_0 : STD_LOGIC; + signal mpr_rd_fall0_prev_r : STD_LOGIC; + signal mpr_rd_fall1_prev_r : STD_LOGIC; + signal mpr_rd_fall2_prev_r : STD_LOGIC; + signal mpr_rd_fall3_prev_r : STD_LOGIC; + signal mpr_rd_rise0_prev_r : STD_LOGIC; + signal mpr_rd_rise0_prev_r0 : STD_LOGIC; + signal mpr_rd_rise1_prev_r : STD_LOGIC; + signal mpr_rd_rise2_prev_r : STD_LOGIC; + signal mpr_rd_rise3_prev_r : STD_LOGIC; + signal mpr_rdlvl_start_r : STD_LOGIC; + signal new_cnt_cpt_r : STD_LOGIC; + signal new_cnt_cpt_r_i_2_n_0 : STD_LOGIC; + signal \^new_cnt_cpt_r_reg_0\ : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal p_0_in100_in : STD_LOGIC; + signal p_0_in103_in : STD_LOGIC; + signal p_0_in118_in : STD_LOGIC; + signal p_0_in11_in : STD_LOGIC; + signal p_0_in125_in : STD_LOGIC; + signal p_0_in128_in : STD_LOGIC; + signal p_0_in136_in : STD_LOGIC; + signal p_0_in13_in : STD_LOGIC; + signal p_0_in144_in : STD_LOGIC; + signal p_0_in152_in : STD_LOGIC; + signal p_0_in160_in : STD_LOGIC; + signal p_0_in168_in : STD_LOGIC; + signal p_0_in16_in : STD_LOGIC; + signal p_0_in176_in : STD_LOGIC; + signal p_0_in184_in : STD_LOGIC; + signal p_0_in192_in : STD_LOGIC; + signal p_0_in19_in : STD_LOGIC; + signal p_0_in200_in : STD_LOGIC; + signal p_0_in208_in : STD_LOGIC; + signal p_0_in216_in : STD_LOGIC; + signal p_0_in224_in : STD_LOGIC; + signal p_0_in22_in : STD_LOGIC; + signal p_0_in250_in : STD_LOGIC; + signal p_0_in25_in : STD_LOGIC; + signal p_0_in28_in : STD_LOGIC; + signal p_0_in88_in : STD_LOGIC; + signal p_0_in91_in : STD_LOGIC; + signal p_0_in94_in : STD_LOGIC; + signal p_0_in97_in : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 5 downto 2 ); + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__7\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__8\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__9\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal p_12_in : STD_LOGIC; + signal p_13_in : STD_LOGIC; + signal p_14_in : STD_LOGIC; + signal p_1_in127_in : STD_LOGIC; + signal p_1_in12_in : STD_LOGIC; + signal p_1_in135_in : STD_LOGIC; + signal p_1_in143_in : STD_LOGIC; + signal p_1_in14_in : STD_LOGIC; + signal p_1_in151_in : STD_LOGIC; + signal p_1_in159_in : STD_LOGIC; + signal p_1_in167_in : STD_LOGIC; + signal p_1_in175_in : STD_LOGIC; + signal p_1_in17_in : STD_LOGIC; + signal p_1_in183_in : STD_LOGIC; + signal p_1_in191_in : STD_LOGIC; + signal p_1_in199_in : STD_LOGIC; + signal p_1_in207_in : STD_LOGIC; + signal p_1_in20_in : STD_LOGIC; + signal p_1_in215_in : STD_LOGIC; + signal p_1_in223_in : STD_LOGIC; + signal p_1_in231_in : STD_LOGIC; + signal p_1_in23_in : STD_LOGIC; + signal p_1_in26_in : STD_LOGIC; + signal p_1_in29_in : STD_LOGIC; + signal p_1_in2_in : STD_LOGIC; + signal p_2_in : STD_LOGIC; + signal p_2_in129_in : STD_LOGIC; + signal p_2_in137_in : STD_LOGIC; + signal p_2_in145_in : STD_LOGIC; + signal p_2_in153_in : STD_LOGIC; + signal p_2_in161_in : STD_LOGIC; + signal p_2_in169_in : STD_LOGIC; + signal p_2_in177_in : STD_LOGIC; + signal p_2_in185_in : STD_LOGIC; + signal p_2_in193_in : STD_LOGIC; + signal p_2_in201_in : STD_LOGIC; + signal p_2_in209_in : STD_LOGIC; + signal p_2_in217_in : STD_LOGIC; + signal p_2_in225_in : STD_LOGIC; + signal p_37_in : STD_LOGIC; + signal p_3_in : STD_LOGIC; + signal p_3_in130_in : STD_LOGIC; + signal p_3_in138_in : STD_LOGIC; + signal p_3_in146_in : STD_LOGIC; + signal p_3_in154_in : STD_LOGIC; + signal p_3_in162_in : STD_LOGIC; + signal p_3_in170_in : STD_LOGIC; + signal p_3_in178_in : STD_LOGIC; + signal p_3_in186_in : STD_LOGIC; + signal p_3_in194_in : STD_LOGIC; + signal p_3_in202_in : STD_LOGIC; + signal p_3_in210_in : STD_LOGIC; + signal p_3_in218_in : STD_LOGIC; + signal p_3_in226_in : STD_LOGIC; + signal p_3_in4_in : STD_LOGIC; + signal p_4_in : STD_LOGIC; + signal p_4_in131_in : STD_LOGIC; + signal p_4_in139_in : STD_LOGIC; + signal p_4_in147_in : STD_LOGIC; + signal p_4_in155_in : STD_LOGIC; + signal p_4_in163_in : STD_LOGIC; + signal p_4_in171_in : STD_LOGIC; + signal p_4_in179_in : STD_LOGIC; + signal p_4_in187_in : STD_LOGIC; + signal p_4_in195_in : STD_LOGIC; + signal p_4_in203_in : STD_LOGIC; + signal p_4_in211_in : STD_LOGIC; + signal p_4_in219_in : STD_LOGIC; + signal p_4_in227_in : STD_LOGIC; + signal p_5_in : STD_LOGIC; + signal p_5_in132_in : STD_LOGIC; + signal p_5_in140_in : STD_LOGIC; + signal p_5_in148_in : STD_LOGIC; + signal p_5_in156_in : STD_LOGIC; + signal p_5_in164_in : STD_LOGIC; + signal p_5_in172_in : STD_LOGIC; + signal p_5_in180_in : STD_LOGIC; + signal p_5_in188_in : STD_LOGIC; + signal p_5_in196_in : STD_LOGIC; + signal p_5_in204_in : STD_LOGIC; + signal p_5_in212_in : STD_LOGIC; + signal p_5_in220_in : STD_LOGIC; + signal p_5_in228_in : STD_LOGIC; + signal p_6_in126_in : STD_LOGIC; + signal p_6_in133_in : STD_LOGIC; + signal p_6_in141_in : STD_LOGIC; + signal p_6_in149_in : STD_LOGIC; + signal p_6_in157_in : STD_LOGIC; + signal p_6_in165_in : STD_LOGIC; + signal p_6_in173_in : STD_LOGIC; + signal p_6_in181_in : STD_LOGIC; + signal p_6_in189_in : STD_LOGIC; + signal p_6_in197_in : STD_LOGIC; + signal p_6_in205_in : STD_LOGIC; + signal p_6_in213_in : STD_LOGIC; + signal p_6_in221_in : STD_LOGIC; + signal p_6_in229_in : STD_LOGIC; + signal p_7_in : STD_LOGIC; + signal p_7_in134_in : STD_LOGIC; + signal p_7_in142_in : STD_LOGIC; + signal p_7_in150_in : STD_LOGIC; + signal p_7_in158_in : STD_LOGIC; + signal p_7_in166_in : STD_LOGIC; + signal p_7_in174_in : STD_LOGIC; + signal p_7_in182_in : STD_LOGIC; + signal p_7_in190_in : STD_LOGIC; + signal p_7_in198_in : STD_LOGIC; + signal p_7_in206_in : STD_LOGIC; + signal p_7_in214_in : STD_LOGIC; + signal p_7_in222_in : STD_LOGIC; + signal p_7_in230_in : STD_LOGIC; + signal p_9_in : STD_LOGIC; + signal pat0_data_match_r0 : STD_LOGIC; + signal pat0_match_fall0_and_r : STD_LOGIC; + signal pat0_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat0_match_fall1_and_r : STD_LOGIC; + signal pat0_match_fall1_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat0_match_fall2_and_r : STD_LOGIC; + signal pat0_match_fall2_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat0_match_fall3_and_r : STD_LOGIC; + signal pat0_match_fall3_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat0_match_rise0_and_r : STD_LOGIC; + signal pat0_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat0_match_rise1_and_r : STD_LOGIC; + signal pat0_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat0_match_rise2_and_r : STD_LOGIC; + signal pat0_match_rise2_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat0_match_rise3_and_r : STD_LOGIC; + signal pat0_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pat1_data_match_r0 : STD_LOGIC; + signal pat1_match_fall0_and_r : STD_LOGIC; + signal pat1_match_fall1_and_r : STD_LOGIC; + signal pat1_match_fall2_and_r : STD_LOGIC; + signal pat1_match_fall3_and_r : STD_LOGIC; + signal pat1_match_rise0_and_r : STD_LOGIC; + signal pat1_match_rise1_and_r : STD_LOGIC; + signal pat1_match_rise2_and_r : STD_LOGIC; + signal pat1_match_rise3_and_r : STD_LOGIC; + signal pb_cnt_eye_size_r : STD_LOGIC; + signal pb_detect_edge : STD_LOGIC; + signal pb_detect_edge_done_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pb_found_stable_eye_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal pb_found_stable_eye_r53_out : STD_LOGIC; + signal pb_found_stable_eye_r57_out : STD_LOGIC; + signal pb_found_stable_eye_r61_out : STD_LOGIC; + signal pb_found_stable_eye_r65_out : STD_LOGIC; + signal pb_found_stable_eye_r69_out : STD_LOGIC; + signal pb_found_stable_eye_r73_out : STD_LOGIC; + signal pb_found_stable_eye_r77_out : STD_LOGIC; + signal pi_cnt_dec_i_1_n_0 : STD_LOGIC; + signal pi_cnt_dec_i_2_n_0 : STD_LOGIC; + signal \^pi_cnt_dec_reg_0\ : STD_LOGIC; + signal pi_counter_load_en : STD_LOGIC; + signal pi_counter_load_val : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal pi_en_stg2_f_timing : STD_LOGIC; + signal pi_en_stg2_f_timing_i_1_n_0 : STD_LOGIC; + signal \^pi_fine_dly_dec_done_reg_0\ : STD_LOGIC; + signal pi_rdval_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \pi_rdval_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[3]_i_3_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[5]_i_2_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[5]_i_3_n_0\ : STD_LOGIC; + signal \pi_rdval_cnt[5]_i_4_n_0\ : STD_LOGIC; + signal pi_stg2_f_incdec_timing : STD_LOGIC; + signal pi_stg2_f_incdec_timing_i_1_n_0 : STD_LOGIC; + signal pi_stg2_load_timing : STD_LOGIC; + signal pi_stg2_load_timing_i_1_n_0 : STD_LOGIC; + signal pi_stg2_reg_l_timing : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \pi_stg2_reg_l_timing[0]_i_1_n_0\ : STD_LOGIC; + signal \pi_stg2_reg_l_timing[1]_i_1_n_0\ : STD_LOGIC; + signal \pi_stg2_reg_l_timing[2]_i_1_n_0\ : STD_LOGIC; + signal \pi_stg2_reg_l_timing[3]_i_1_n_0\ : STD_LOGIC; + signal \pi_stg2_reg_l_timing[4]_i_1_n_0\ : STD_LOGIC; + signal \pi_stg2_reg_l_timing[5]_i_1_n_0\ : STD_LOGIC; + signal \pi_stg2_reg_l_timing[5]_i_2_n_0\ : STD_LOGIC; + signal \^rd_mux_sel_r_reg[0]_0\ : STD_LOGIC; + signal rdlvl_dqs_tap_cnt_r : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\ : STD_LOGIC; + signal \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\ : STD_LOGIC; + signal \^rdlvl_last_byte_done\ : STD_LOGIC; + signal rdlvl_last_byte_done_int_i_1_n_0 : STD_LOGIC; + signal \^rdlvl_pi_incdec\ : STD_LOGIC; + signal rdlvl_pi_incdec_i_1_n_0 : STD_LOGIC; + signal rdlvl_pi_incdec_i_2_n_0 : STD_LOGIC; + signal rdlvl_pi_incdec_i_3_n_0 : STD_LOGIC; + signal rdlvl_pi_incdec_i_4_n_0 : STD_LOGIC; + signal rdlvl_pi_incdec_i_5_n_0 : STD_LOGIC; + signal rdlvl_pi_stg2_f_en : STD_LOGIC; + signal rdlvl_pi_stg2_f_incdec : STD_LOGIC; + signal rdlvl_rank_done_r : STD_LOGIC; + signal rdlvl_rank_done_r_i_1_n_0 : STD_LOGIC; + signal rdlvl_stg1_done_int : STD_LOGIC; + signal rdlvl_stg1_done_int_i_1_n_0 : STD_LOGIC; + signal \^rdlvl_stg1_rank_done\ : STD_LOGIC; + signal rdlvl_stg1_start_r : STD_LOGIC; + signal \regl_dqs_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \regl_dqs_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal regl_dqs_cnt_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \regl_dqs_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \regl_dqs_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal regl_rank_cnt : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \regl_rank_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \regl_rank_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \regl_rank_cnt[1]_i_2_n_0\ : STD_LOGIC; + signal right_edge_taps_r : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \right_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC; + signal \right_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC; + signal \right_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC; + signal \right_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC; + signal \right_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC; + signal \right_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC; + signal \right_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC; + signal \right_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC; + signal \rnk_cnt_r[0]_i_1__0_n_0\ : STD_LOGIC; + signal \rnk_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; + signal \rnk_cnt_r_reg_n_0_[0]\ : STD_LOGIC; + signal \rnk_cnt_r_reg_n_0_[1]\ : STD_LOGIC; + signal samp_cnt_done_r_i_1_n_0 : STD_LOGIC; + signal samp_cnt_done_r_i_2_n_0 : STD_LOGIC; + signal samp_cnt_done_r_i_3_n_0 : STD_LOGIC; + signal samp_cnt_done_r_i_4_n_0 : STD_LOGIC; + signal samp_cnt_done_r_reg_n_0 : STD_LOGIC; + signal \^samp_edge_cnt0_en_r\ : STD_LOGIC; + signal \samp_edge_cnt0_r[0]_i_3_n_0\ : STD_LOGIC; + signal samp_edge_cnt0_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \samp_edge_cnt0_r_reg[0]_i_2_n_0\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[0]_i_2_n_1\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[0]_i_2_n_2\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[0]_i_2_n_3\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[0]_i_2_n_4\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[0]_i_2_n_5\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[0]_i_2_n_6\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[0]_i_2_n_7\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \samp_edge_cnt0_r_reg[8]_i_1_n_7\ : STD_LOGIC; + signal samp_edge_cnt1_en_r : STD_LOGIC; + signal samp_edge_cnt1_en_r0 : STD_LOGIC; + signal samp_edge_cnt1_en_r_i_2_n_0 : STD_LOGIC; + signal samp_edge_cnt1_en_r_i_3_n_0 : STD_LOGIC; + signal \samp_edge_cnt1_r[0]_i_2_n_0\ : STD_LOGIC; + signal samp_edge_cnt1_r_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \samp_edge_cnt1_r_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[0]_i_1_n_1\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[0]_i_1_n_2\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[0]_i_1_n_3\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[0]_i_1_n_4\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[0]_i_1_n_5\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[0]_i_1_n_6\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[0]_i_1_n_7\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \samp_edge_cnt1_r_reg[8]_i_1_n_7\ : STD_LOGIC; + signal \second_edge_taps_r[1]_i_1_n_0\ : STD_LOGIC; + signal \second_edge_taps_r[2]_i_1_n_0\ : STD_LOGIC; + signal \second_edge_taps_r[3]_i_1_n_0\ : STD_LOGIC; + signal \second_edge_taps_r[4]_i_1_n_0\ : STD_LOGIC; + signal \second_edge_taps_r[5]_i_1_n_0\ : STD_LOGIC; + signal \second_edge_taps_r[5]_i_2_n_0\ : STD_LOGIC; + signal \second_edge_taps_r[5]_i_3_n_0\ : STD_LOGIC; + signal \second_edge_taps_r_reg_n_0_[0]\ : STD_LOGIC; + signal \second_edge_taps_r_reg_n_0_[1]\ : STD_LOGIC; + signal \second_edge_taps_r_reg_n_0_[2]\ : STD_LOGIC; + signal \second_edge_taps_r_reg_n_0_[3]\ : STD_LOGIC; + signal \second_edge_taps_r_reg_n_0_[4]\ : STD_LOGIC; + signal \second_edge_taps_r_reg_n_0_[5]\ : STD_LOGIC; + signal sr_valid_r1 : STD_LOGIC; + signal sr_valid_r2 : STD_LOGIC; + signal sr_valid_r_i_1_n_0 : STD_LOGIC; + signal sr_valid_r_reg_n_0 : STD_LOGIC; + signal stable_idel_cnt : STD_LOGIC; + signal stable_idel_cnt0 : STD_LOGIC; + signal store_sr_r0 : STD_LOGIC; + signal store_sr_r_i_1_n_0 : STD_LOGIC; + signal store_sr_r_reg_n_0 : STD_LOGIC; + signal store_sr_req_pulsed_r : STD_LOGIC; + signal \store_sr_req_pulsed_r__0\ : STD_LOGIC; + signal store_sr_req_r : STD_LOGIC; + signal store_sr_req_r_reg_n_0 : STD_LOGIC; + signal tap_cnt_cpt_r : STD_LOGIC; + signal tap_cnt_cpt_r0 : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \tap_cnt_cpt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \tap_cnt_cpt_r[5]_i_4_n_0\ : STD_LOGIC; + signal \tap_cnt_cpt_r[5]_i_5_n_0\ : STD_LOGIC; + signal \tap_cnt_cpt_r[5]_i_6_n_0\ : STD_LOGIC; + signal \tap_cnt_cpt_r_reg_n_0_[0]\ : STD_LOGIC; + signal \tap_cnt_cpt_r_reg_n_0_[1]\ : STD_LOGIC; + signal \tap_cnt_cpt_r_reg_n_0_[2]\ : STD_LOGIC; + signal \tap_cnt_cpt_r_reg_n_0_[3]\ : STD_LOGIC; + signal \tap_cnt_cpt_r_reg_n_0_[4]\ : STD_LOGIC; + signal \tap_cnt_cpt_r_reg_n_0_[5]\ : STD_LOGIC; + signal tap_limit_cpt_r : STD_LOGIC; + signal tap_limit_cpt_r_i_1_n_0 : STD_LOGIC; + signal tap_limit_cpt_r_i_2_n_0 : STD_LOGIC; + signal wait_cnt_r0 : STD_LOGIC; + signal \wait_cnt_r0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wait_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; + signal wait_cnt_r_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[10]_i_1\ : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[11]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[14]_i_1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[15]_i_2\ : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[16]_i_3\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[16]_i_4\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[21]_i_2\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[22]_i_2\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[29]_i_1\ : label is "soft_lutpair39"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_12\ : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_13\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_2\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_3\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_6\ : label is "soft_lutpair48"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[34]_i_8\ : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[4]_i_1\ : label is "soft_lutpair146"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[5]_i_2\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[6]_i_3\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[7]_i_1\ : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \FSM_onehot_cal1_state_r[9]_i_1\ : label is "soft_lutpair29"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[0]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[10]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[11]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[12]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[13]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[14]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[15]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[16]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[1]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[20]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[21]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[22]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[29]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[2]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[31]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[32]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[34]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[3]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[4]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[5]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[6]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[7]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[8]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute FSM_ENCODED_STATES of \FSM_onehot_cal1_state_r_reg[9]\ : label is "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000"; + attribute SOFT_HLUTNM of cal1_dlyinc_cpt_r_i_1 : label is "soft_lutpair44"; + attribute SOFT_HLUTNM of cal1_dq_idel_ce_i_1 : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \cal1_state_r1[0]_i_2\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \cal1_state_r1[1]_i_2\ : label is "soft_lutpair43"; + attribute SOFT_HLUTNM of \cal1_state_r1[1]_i_3\ : label is "soft_lutpair64"; + attribute SOFT_HLUTNM of \cal1_state_r1[2]_i_2\ : label is "soft_lutpair63"; + attribute SOFT_HLUTNM of \cal1_state_r1[5]_i_1\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of cal1_wait_cnt_en_r_i_2 : label is "soft_lutpair62"; + attribute SOFT_HLUTNM of \cal1_wait_cnt_r[1]_i_1\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \cal1_wait_cnt_r[2]_i_1\ : label is "soft_lutpair152"; + attribute SOFT_HLUTNM of \cal1_wait_cnt_r[3]_i_1\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \cal1_wait_cnt_r[4]_i_2\ : label is "soft_lutpair40"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[0]_i_3\ : label is "soft_lutpair65"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[1]_i_3\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[1]_i_4\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_2\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_5\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[3]_i_6\ : label is "soft_lutpair34"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_10\ : label is "soft_lutpair20"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[4]_i_3\ : label is "soft_lutpair42"; + attribute SOFT_HLUTNM of \cnt_idel_dec_cpt_r[5]_i_7\ : label is "soft_lutpair20"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \cnt_idel_dec_cpt_r_reg[2]_i_10\ : label is 35; + attribute ADDER_THRESHOLD of \cnt_idel_dec_cpt_r_reg[4]_i_8\ : label is 35; + attribute SOFT_HLUTNM of \cnt_shift_r[2]_i_1\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \cnt_shift_r[3]_i_2\ : label is "soft_lutpair138"; + attribute SOFT_HLUTNM of \done_cnt[1]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \done_cnt[3]_i_1\ : label is "soft_lutpair31"; + attribute SOFT_HLUTNM of \done_cnt[3]_i_2\ : label is "soft_lutpair50"; + attribute SOFT_HLUTNM of \done_cnt[3]_i_3\ : label is "soft_lutpair8"; + attribute SOFT_HLUTNM of \first_edge_taps_r[5]_i_3\ : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of found_second_edge_r_i_1 : label is "soft_lutpair30"; + attribute SOFT_HLUTNM of \gen_byte_sel_div2.byte_sel_cnt[1]_i_3\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1\ : label is "soft_lutpair149"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_fall0_and_r_i_1\ : label is "soft_lutpair148"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.pat0_match_rise2_and_r_i_1\ : label is "soft_lutpair150"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.pat1_match_fall2_and_r_i_1\ : label is "soft_lutpair149"; + attribute inverted : string; + attribute inverted of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair102"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\ : label is "soft_lutpair98"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\ : label is "soft_lutpair114"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\ : label is "soft_lutpair126"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\ : label is "soft_lutpair122"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\ : label is "soft_lutpair106"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\ : label is "soft_lutpair110"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\ : label is "soft_lutpair118"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\ : label is "soft_lutpair102"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair69"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\ : label is "soft_lutpair97"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\ : label is "soft_lutpair89"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\ : label is "soft_lutpair85"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\ : label is "soft_lutpair73"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\ : label is "soft_lutpair81"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\ : label is "soft_lutpair93"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\ : label is "soft_lutpair77"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\ : label is "soft_lutpair69"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair103"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\ : label is "soft_lutpair99"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\ : label is "soft_lutpair115"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\ : label is "soft_lutpair127"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\ : label is "soft_lutpair123"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\ : label is "soft_lutpair107"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\ : label is "soft_lutpair111"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\ : label is "soft_lutpair119"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\ : label is "soft_lutpair103"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair68"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\ : label is "soft_lutpair96"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\ : label is "soft_lutpair88"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\ : label is "soft_lutpair84"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\ : label is "soft_lutpair72"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\ : label is "soft_lutpair80"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\ : label is "soft_lutpair92"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\ : label is "soft_lutpair76"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\ : label is "soft_lutpair68"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair104"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\ : label is "soft_lutpair100"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\ : label is "soft_lutpair116"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\ : label is "soft_lutpair128"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\ : label is "soft_lutpair124"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\ : label is "soft_lutpair108"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\ : label is "soft_lutpair112"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\ : label is "soft_lutpair120"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\ : label is "soft_lutpair104"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair67"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\ : label is "soft_lutpair95"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\ : label is "soft_lutpair87"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\ : label is "soft_lutpair83"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\ : label is "soft_lutpair71"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\ : label is "soft_lutpair79"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\ : label is "soft_lutpair91"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\ : label is "soft_lutpair75"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\ : label is "soft_lutpair67"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair105"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\ : label is "soft_lutpair101"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\ : label is "soft_lutpair117"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\ : label is "soft_lutpair129"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\ : label is "soft_lutpair125"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\ : label is "soft_lutpair109"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\ : label is "soft_lutpair113"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\ : label is "soft_lutpair121"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\ : label is "soft_lutpair105"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair66"; + attribute inverted of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv\ : label is "yes"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\ : label is "soft_lutpair94"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\ : label is "soft_lutpair86"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\ : label is "soft_lutpair82"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\ : label is "soft_lutpair70"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\ : label is "soft_lutpair78"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\ : label is "soft_lutpair90"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\ : label is "soft_lutpair74"; + attribute SOFT_HLUTNM of \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\ : label is "soft_lutpair66"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\ : label is "soft_lutpair157"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\ : label is "soft_lutpair130"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5\ : label is "soft_lutpair12"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3\ : label is "soft_lutpair7"; + attribute SOFT_HLUTNM of \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4\ : label is "soft_lutpair52"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\ : label is "soft_lutpair158"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\ : label is "soft_lutpair131"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5\ : label is "soft_lutpair13"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3\ : label is "soft_lutpair53"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\ : label is "soft_lutpair159"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\ : label is "soft_lutpair132"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5\ : label is "soft_lutpair14"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3\ : label is "soft_lutpair54"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\ : label is "soft_lutpair160"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\ : label is "soft_lutpair133"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5\ : label is "soft_lutpair15"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3\ : label is "soft_lutpair55"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\ : label is "soft_lutpair161"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\ : label is "soft_lutpair161"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\ : label is "soft_lutpair134"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5\ : label is "soft_lutpair16"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3\ : label is "soft_lutpair56"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\ : label is "soft_lutpair162"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\ : label is "soft_lutpair135"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5\ : label is "soft_lutpair17"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3\ : label is "soft_lutpair57"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\ : label is "soft_lutpair163"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\ : label is "soft_lutpair136"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5\ : label is "soft_lutpair18"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3\ : label is "soft_lutpair58"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\ : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\ : label is "soft_lutpair164"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\ : label is "soft_lutpair137"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5\ : label is "soft_lutpair19"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3\ : label is "soft_lutpair59"; + attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_4\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of \idel_dec_cnt[4]_i_5\ : label is "soft_lutpair10"; + attribute SOFT_HLUTNM of idel_pat_detect_valid_r_i_1 : label is "soft_lutpair140"; + attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][0]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \idelay_tap_cnt_r[0][1][1]_i_1\ : label is "soft_lutpair36"; + attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[0]_i_1\ : label is "soft_lutpair41"; + attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[1]_i_1\ : label is "soft_lutpair143"; + attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[2]_i_1\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[3]_i_1\ : label is "soft_lutpair142"; + attribute SOFT_HLUTNM of \idelay_tap_cnt_slice_r[4]_i_1\ : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_31\ : label is "soft_lutpair46"; + attribute SOFT_HLUTNM of \init_state_r[3]_i_23\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_42\ : label is "soft_lutpair45"; + attribute SOFT_HLUTNM of \mpr_4to1.idel_mpr_pat_detect_r_i_3\ : label is "soft_lutpair60"; + attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[1]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[2]_i_1\ : label is "soft_lutpair9"; + attribute SOFT_HLUTNM of \mpr_4to1.stable_idel_cnt[2]_i_3\ : label is "soft_lutpair144"; + attribute SOFT_HLUTNM of mpr_dec_cpt_r_i_1 : label is "soft_lutpair141"; + attribute SOFT_HLUTNM of new_cnt_cpt_r_i_2 : label is "soft_lutpair32"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_10__0\ : label is "soft_lutpair24"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_11__0\ : label is "soft_lutpair23"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_1__0\ : label is "soft_lutpair21"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_6__0\ : label is "soft_lutpair28"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_7__0\ : label is "soft_lutpair27"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_8__0\ : label is "soft_lutpair26"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_9__0\ : label is "soft_lutpair25"; + attribute SOFT_HLUTNM of pi_cnt_dec_i_2 : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \pi_rdval_cnt[0]_i_1\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \pi_rdval_cnt[3]_i_2\ : label is "soft_lutpair22"; + attribute SOFT_HLUTNM of \pi_rdval_cnt[3]_i_3\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of \pi_rdval_cnt[5]_i_4\ : label is "soft_lutpair61"; + attribute SOFT_HLUTNM of pi_stg2_load_timing_i_1 : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[0]_i_1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[1]_i_1\ : label is "soft_lutpair156"; + attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[2]_i_1\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[3]_i_1\ : label is "soft_lutpair155"; + attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[4]_i_1\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of \pi_stg2_reg_l_timing[5]_i_2\ : label is "soft_lutpair154"; + attribute SOFT_HLUTNM of rdlvl_pi_incdec_i_5 : label is "soft_lutpair29"; + attribute SOFT_HLUTNM of rdlvl_rank_done_r_i_2 : label is "soft_lutpair147"; + attribute SOFT_HLUTNM of rdlvl_stg1_done_int_i_1 : label is "soft_lutpair50"; + attribute syn_maxfan : string; + attribute syn_maxfan of rdlvl_stg1_done_int_reg : label is "30"; + attribute SOFT_HLUTNM of \regl_dqs_cnt[1]_i_1\ : label is "soft_lutpair49"; + attribute SOFT_HLUTNM of \right_edge_taps_r[1]_i_1\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \right_edge_taps_r[2]_i_1\ : label is "soft_lutpair166"; + attribute SOFT_HLUTNM of \right_edge_taps_r[3]_i_1\ : label is "soft_lutpair145"; + attribute SOFT_HLUTNM of \right_edge_taps_r[4]_i_1\ : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \right_edge_taps_r[5]_i_2\ : label is "soft_lutpair165"; + attribute SOFT_HLUTNM of \right_edge_taps_r[5]_i_3\ : label is "soft_lutpair47"; + attribute SOFT_HLUTNM of samp_edge_cnt0_en_r_i_1 : label is "soft_lutpair47"; + attribute ADDER_THRESHOLD of \samp_edge_cnt0_r_reg[0]_i_2\ : label is 11; + attribute ADDER_THRESHOLD of \samp_edge_cnt0_r_reg[4]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \samp_edge_cnt0_r_reg[8]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \samp_edge_cnt1_r_reg[0]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \samp_edge_cnt1_r_reg[4]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \samp_edge_cnt1_r_reg[8]_i_1\ : label is 11; + attribute SOFT_HLUTNM of \second_edge_taps_r[0]_i_1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \second_edge_taps_r[1]_i_1\ : label is "soft_lutpair151"; + attribute SOFT_HLUTNM of \second_edge_taps_r[2]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of \second_edge_taps_r[3]_i_1\ : label is "soft_lutpair37"; + attribute SOFT_HLUTNM of store_sr_req_r_i_1 : label is "soft_lutpair33"; + attribute SOFT_HLUTNM of \tap_cnt_cpt_r[1]_i_1\ : label is "soft_lutpair51"; + attribute SOFT_HLUTNM of \tap_cnt_cpt_r[2]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \tap_cnt_cpt_r[3]_i_1\ : label is "soft_lutpair38"; + attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_4\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_6\ : label is "soft_lutpair11"; + attribute SOFT_HLUTNM of \wait_cnt_r[1]_i_1__0\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \wait_cnt_r[2]_i_1__0\ : label is "soft_lutpair153"; + attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_3__0\ : label is "soft_lutpair139"; + attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[109]_i_1\ : label is "soft_lutpair35"; + attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[13]_i_1\ : label is "soft_lutpair167"; + attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1\ : label is "soft_lutpair167"; +begin + D(4 downto 0) <= \^d\(4 downto 0); + \cal1_cnt_cpt_r_reg[0]_0\ <= \^cal1_cnt_cpt_r_reg[0]_0\; + idelay_ce_int <= \^idelay_ce_int\; + idelay_inc_int <= \^idelay_inc_int\; + new_cnt_cpt_r_reg_0 <= \^new_cnt_cpt_r_reg_0\; + pi_cnt_dec_reg_0 <= \^pi_cnt_dec_reg_0\; + pi_fine_dly_dec_done_reg_0 <= \^pi_fine_dly_dec_done_reg_0\; + \rd_mux_sel_r_reg[0]_0\ <= \^rd_mux_sel_r_reg[0]_0\; + rdlvl_last_byte_done <= \^rdlvl_last_byte_done\; + rdlvl_pi_incdec <= \^rdlvl_pi_incdec\; + rdlvl_stg1_rank_done <= \^rdlvl_stg1_rank_done\; + samp_edge_cnt0_en_r <= \^samp_edge_cnt0_en_r\; +\FSM_onehot_cal1_state_r[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => p_1_in2_in, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[34]\, + O => \FSM_onehot_cal1_state_r[10]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002AAA" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => found_edge_r_reg_n_0, + I2 => found_stable_eye_last_r, + I3 => found_first_edge_r_reg_n_0, + I4 => tap_limit_cpt_r, + O => \FSM_onehot_cal1_state_r[11]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[13]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FBAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + I1 => mpr_rdlvl_start_r_reg_0, + I2 => mpr_rdlvl_start_r, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + O => \FSM_onehot_cal1_state_r[13]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[14]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I1 => \FSM_onehot_cal1_state_r[14]_i_2_n_0\, + O => \FSM_onehot_cal1_state_r[14]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100000000" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\, + I1 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\, + I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\, + I3 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\, + I4 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\, + I5 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + O => \FSM_onehot_cal1_state_r[14]_i_2_n_0\ + ); +\FSM_onehot_cal1_state_r[15]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[15]_i_2_n_0\, + I1 => \FSM_onehot_cal1_state_r[15]_i_3_n_0\, + I2 => p_12_in, + O => \FSM_onehot_cal1_state_r[15]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[15]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[16]_i_3_n_0\, + I1 => mpr_dec_cpt_r_reg_n_0, + I2 => \FSM_onehot_cal1_state_r[16]_i_4_n_0\, + O => \FSM_onehot_cal1_state_r[15]_i_2_n_0\ + ); +\FSM_onehot_cal1_state_r[15]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \pi_rdval_cnt[5]_i_3_n_0\, + I1 => \idel_dec_cnt_reg_n_0_[2]\, + I2 => \idel_dec_cnt_reg_n_0_[0]\, + I3 => \idel_dec_cnt_reg_n_0_[1]\, + I4 => \idel_dec_cnt_reg_n_0_[3]\, + I5 => \idel_dec_cnt_reg_n_0_[4]\, + O => \FSM_onehot_cal1_state_r[15]_i_3_n_0\ + ); +\FSM_onehot_cal1_state_r[16]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8FFF8F8F88888888" + ) + port map ( + I0 => p_3_in4_in, + I1 => store_sr_req_r_reg_0, + I2 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\, + I3 => \FSM_onehot_cal1_state_r[16]_i_3_n_0\, + I4 => \FSM_onehot_cal1_state_r[16]_i_4_n_0\, + I5 => mpr_dec_cpt_r_reg_n_0, + O => \FSM_onehot_cal1_state_r[16]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[16]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I1 => \FSM_onehot_cal1_state_r[14]_i_2_n_0\, + O => \FSM_onehot_cal1_state_r[16]_i_3_n_0\ + ); +\FSM_onehot_cal1_state_r[16]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0151" + ) + port map ( + I0 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\, + I1 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\, + I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\, + O => \FSM_onehot_cal1_state_r[16]_i_4_n_0\ + ); +\FSM_onehot_cal1_state_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => mpr_dec_cpt_r, + I1 => p_9_in, + I2 => p_13_in, + O => \FSM_onehot_cal1_state_r[1]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[20]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => idel_adj_inc_reg_n_0, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + O => \FSM_onehot_cal1_state_r[20]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[21]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF1FFF1FFF1F1F1" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[21]_i_2_n_0\, + I1 => mpr_dec_cpt_r_reg_n_0, + I2 => \FSM_onehot_cal1_state_r[21]_i_3_n_0\, + I3 => p_37_in, + I4 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\, + I5 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\, + O => \FSM_onehot_cal1_state_r[21]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[21]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => p_12_in, + I1 => \FSM_onehot_cal1_state_r[15]_i_3_n_0\, + O => \FSM_onehot_cal1_state_r[21]_i_2_n_0\ + ); +\FSM_onehot_cal1_state_r[21]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFF808080" + ) + port map ( + I0 => p_0_in250_in, + I1 => idel_pat_detect_valid_r_reg_n_0, + I2 => idel_mpr_pat_detect_r, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + I4 => idel_adj_inc_reg_n_0, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + O => \FSM_onehot_cal1_state_r[21]_i_3_n_0\ + ); +\FSM_onehot_cal1_state_r[22]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0008AAAA00080008" + ) + port map ( + I0 => idelay_tap_limit_r_reg_n_0, + I1 => p_37_in, + I2 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\, + I3 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\, + I4 => idel_mpr_pat_detect_r, + I5 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\, + O => \FSM_onehot_cal1_state_r[22]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[22]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => p_0_in250_in, + I1 => idel_pat_detect_valid_r_reg_n_0, + O => \FSM_onehot_cal1_state_r[22]_i_2_n_0\ + ); +\FSM_onehot_cal1_state_r[29]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAA8000" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => found_edge_r_reg_n_0, + I2 => found_stable_eye_last_r, + I3 => found_first_edge_r_reg_n_0, + I4 => tap_limit_cpt_r, + O => \FSM_onehot_cal1_state_r[29]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0004555500040004" + ) + port map ( + I0 => idelay_tap_limit_r_reg_n_0, + I1 => p_37_in, + I2 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\, + I3 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\, + I4 => idel_mpr_pat_detect_r, + I5 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\, + O => \FSM_onehot_cal1_state_r[2]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF5554" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[34]_i_3_n_0\, + I1 => \FSM_onehot_cal1_state_r[34]_i_4_n_0\, + I2 => \FSM_onehot_cal1_state_r[34]_i_5_n_0\, + I3 => \FSM_onehot_cal1_state_r[34]_i_6_n_0\, + I4 => \FSM_onehot_cal1_state_r[34]_i_7_n_0\, + I5 => mpr_dec_cpt_r, + O => \FSM_onehot_cal1_state_r[34]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF8F8FFF8" + ) + port map ( + I0 => prech_done, + I1 => cal1_prech_req_r, + I2 => p_0_in118_in, + I3 => p_3_in4_in, + I4 => cal1_wait_r, + I5 => \FSM_onehot_cal1_state_r[34]_i_13_n_0\, + O => \FSM_onehot_cal1_state_r[34]_i_10_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + I1 => p_14_in, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + I5 => p_13_in, + O => \FSM_onehot_cal1_state_r[34]_i_11_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_12\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I1 => cal1_wait_r, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + O => \FSM_onehot_cal1_state_r[34]_i_12_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => cal1_dq_idel_inc, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + O => \FSM_onehot_cal1_state_r[34]_i_13_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p_0_in250_in, + I1 => idel_pat_detect_valid_r_reg_n_0, + O => \FSM_onehot_cal1_state_r[34]_i_2_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000222A" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[34]_i_9_n_0\, + I1 => detect_edge_done_r, + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => p_0_in250_in, + O => \FSM_onehot_cal1_state_r[34]_i_3_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => p_13_in, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + I2 => p_14_in, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + I4 => store_sr_req_pulsed_r, + O => \FSM_onehot_cal1_state_r[34]_i_4_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[34]\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + O => \FSM_onehot_cal1_state_r[34]_i_5_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => p_0_in250_in, + I1 => p_37_in, + I2 => p_9_in, + I3 => p_12_in, + O => \FSM_onehot_cal1_state_r[34]_i_6_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF40F04040" + ) + port map ( + I0 => mpr_rdlvl_start_r, + I1 => mpr_rdlvl_start_r_reg_0, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + I3 => rdlvl_stg1_start_r, + I4 => rdlvl_stg1_start_r_reg_0, + I5 => \FSM_onehot_cal1_state_r[34]_i_10_n_0\, + O => \FSM_onehot_cal1_state_r[34]_i_7_n_0\ + ); +\FSM_onehot_cal1_state_r[34]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => p_3_in4_in, + I1 => store_sr_req_r_reg_0, + O => mpr_dec_cpt_r + ); +\FSM_onehot_cal1_state_r[34]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00010000" + ) + port map ( + I0 => detect_edge_done_r, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I2 => p_9_in, + I3 => \FSM_onehot_cal1_state_r[34]_i_11_n_0\, + I4 => \cal1_state_r1[1]_i_2_n_0\, + I5 => \FSM_onehot_cal1_state_r[34]_i_12_n_0\, + O => \FSM_onehot_cal1_state_r[34]_i_9_n_0\ + ); +\FSM_onehot_cal1_state_r[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => mpr_dec_cpt_r_reg_n_0, + I1 => \FSM_onehot_cal1_state_r[14]_i_2_n_0\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + O => \FSM_onehot_cal1_state_r[4]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000008" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \regl_dqs_cnt_reg_n_0_[1]\, + I3 => regl_rank_cnt(0), + I4 => regl_rank_cnt(1), + O => \FSM_onehot_cal1_state_r[5]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00020000" + ) + port map ( + I0 => p_0_in118_in, + I1 => done_cnt(3), + I2 => done_cnt(2), + I3 => done_cnt(1), + I4 => done_cnt(0), + O => \FSM_onehot_cal1_state_r[5]_i_2_n_0\ + ); +\FSM_onehot_cal1_state_r[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FB00FFFFFB00FB00" + ) + port map ( + I0 => \regl_dqs_cnt_reg_n_0_[1]\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \FSM_onehot_cal1_state_r[6]_i_2_n_0\, + I3 => p_0_in118_in, + I4 => \^cal1_cnt_cpt_r_reg[0]_0\, + I5 => cal1_prech_req_r, + O => \FSM_onehot_cal1_state_r[6]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEFF" + ) + port map ( + I0 => done_cnt(3), + I1 => done_cnt(2), + I2 => done_cnt(1), + I3 => done_cnt(0), + I4 => regl_rank_cnt(0), + I5 => regl_rank_cnt(1), + O => \FSM_onehot_cal1_state_r[6]_i_2_n_0\ + ); +\FSM_onehot_cal1_state_r[6]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FD" + ) + port map ( + I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I1 => \rnk_cnt_r_reg_n_0_[1]\, + I2 => \rnk_cnt_r_reg_n_0_[0]\, + O => \^cal1_cnt_cpt_r_reg[0]_0\ + ); +\FSM_onehot_cal1_state_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8880" + ) + port map ( + I0 => cal1_prech_req_r, + I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I2 => \rnk_cnt_r_reg_n_0_[1]\, + I3 => \rnk_cnt_r_reg_n_0_[0]\, + O => \FSM_onehot_cal1_state_r[7]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => cal1_prech_req_r, + I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + O => cal1_cnt_cpt_r(0) + ); +\FSM_onehot_cal1_state_r[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => mpr_rdlvl_start_r, + I1 => mpr_rdlvl_start_r_reg_0, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + O => \FSM_onehot_cal1_state_r[9]_i_1_n_0\ + ); +\FSM_onehot_cal1_state_r_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + Q => p_13_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[10]_i_1_n_0\, + Q => p_0_in250_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[11]_i_1_n_0\, + Q => p_14_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => p_14_in, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[13]_i_1_n_0\, + Q => p_3_in4_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[14]_i_1_n_0\, + Q => p_9_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[15]_i_1_n_0\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[16]_i_1_n_0\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[1]_i_1_n_0\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[20]_i_1_n_0\, + Q => p_37_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[21]_i_1_n_0\, + Q => store_sr_req_pulsed_r, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[22]_i_1_n_0\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[22]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[29]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[29]_i_1_n_0\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[2]_i_1_n_0\, + Q => cal1_dq_idel_inc, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[31]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[32]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + Q => p_12_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[34]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[34]_i_2_n_0\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[34]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => cal1_dq_idel_inc, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[4]_i_1_n_0\, + Q => cal1_prech_req_r, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[5]_i_1_n_0\, + Q => rdlvl_stg1_done_int, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[6]_i_1_n_0\, + Q => p_0_in118_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[7]\: unisim.vcomponents.FDSE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[7]_i_1_n_0\, + Q => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + S => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => cal1_cnt_cpt_r(0), + Q => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\FSM_onehot_cal1_state_r_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \FSM_onehot_cal1_state_r[34]_i_1_n_0\, + D => \FSM_onehot_cal1_state_r[9]_i_1_n_0\, + Q => p_1_in2_in, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\cal1_cnt_cpt_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"15E015E015E055E0" + ) + port map ( + I0 => p_0_in118_in, + I1 => prech_done, + I2 => cal1_prech_req_r, + I3 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I4 => \rnk_cnt_r_reg_n_0_[1]\, + I5 => \rnk_cnt_r_reg_n_0_[0]\, + O => \cal1_cnt_cpt_r[0]_i_1_n_0\ + ); +\cal1_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_cnt_cpt_r[0]_i_1_n_0\, + Q => \cal1_cnt_cpt_r_reg_n_0_[0]\, + R => \done_cnt_reg[1]_0\ + ); +cal1_dlyce_cpt_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I1 => tap_limit_cpt_r, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + O => cal1_dlyce_cpt_r + ); +cal1_dlyce_cpt_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal1_dlyce_cpt_r, + Q => cal1_dlyce_cpt_r_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +cal1_dlyinc_cpt_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + I1 => tap_limit_cpt_r, + O => cal1_dlyinc_cpt_r + ); +cal1_dlyinc_cpt_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal1_dlyinc_cpt_r, + Q => cal1_dlyinc_cpt_r_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +cal1_dq_idel_ce_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I1 => cal1_dq_idel_inc, + O => cal1_dq_idel_ce + ); +cal1_dq_idel_ce_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal1_dq_idel_ce, + Q => \^idelay_ce_int\, + R => \done_cnt_reg[1]_0\ + ); +cal1_dq_idel_inc_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal1_dq_idel_inc, + Q => \^idelay_inc_int\, + R => \done_cnt_reg[1]_0\ + ); +cal1_prech_req_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal1_prech_req_r, + Q => \cal1_prech_req_r__0\, + R => \done_cnt_reg[1]_0\ + ); +\cal1_state_r1[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[34]_i_6_n_0\, + I1 => \cal1_state_r1[0]_i_2_n_0\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + I3 => p_1_in2_in, + I4 => p_3_in4_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + O => \cal1_state_r1[0]_i_1_n_0\ + ); +\cal1_state_r1[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => rdlvl_stg1_done_int, + I1 => p_0_in118_in, + I2 => p_14_in, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + O => \cal1_state_r1[0]_i_2_n_0\ + ); +\cal1_state_r1[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFD" + ) + port map ( + I0 => \cal1_state_r1[1]_i_2_n_0\, + I1 => p_13_in, + I2 => cal1_prech_req_r, + I3 => p_0_in250_in, + I4 => p_37_in, + I5 => \cal1_state_r1[1]_i_3_n_0\, + O => \cal1_state_r1[1]_i_1_n_0\ + ); +\cal1_state_r1[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_12_in, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[34]\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \cal1_state_r1[1]_i_2_n_0\ + ); +\cal1_state_r1[1]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => rdlvl_stg1_done_int, + I1 => p_0_in118_in, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + O => \cal1_state_r1[1]_i_3_n_0\ + ); +\cal1_state_r1[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \cal1_state_r1[3]_i_3_n_0\, + I1 => \cal1_state_r1[2]_i_2_n_0\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I3 => cal1_prech_req_r, + I4 => p_12_in, + I5 => rdlvl_stg1_done_int, + O => \cal1_state_r1[2]_i_1_n_0\ + ); +\cal1_state_r1[2]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + I1 => p_1_in2_in, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I3 => cal1_dq_idel_inc, + O => \cal1_state_r1[2]_i_2_n_0\ + ); +\cal1_state_r1[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \cal1_state_r1[3]_i_2_n_0\, + I1 => \cal1_state_r1[3]_i_3_n_0\, + I2 => rdlvl_stg1_done_int, + I3 => p_0_in118_in, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + O => \cal1_state_r1[3]_i_1_n_0\ + ); +\cal1_state_r1[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => p_1_in2_in, + I1 => store_sr_req_pulsed_r, + I2 => cal1_prech_req_r, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[12]\, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + O => \cal1_state_r1[3]_i_2_n_0\ + ); +\cal1_state_r1[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[34]\, + I2 => p_9_in, + I3 => p_0_in250_in, + O => \cal1_state_r1[3]_i_3_n_0\ + ); +\cal1_state_r1[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[34]\, + I1 => p_1_in2_in, + I2 => p_0_in118_in, + I3 => p_0_in250_in, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[22]\, + O => \cal1_state_r1[4]_i_1_n_0\ + ); +\cal1_state_r1[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + I1 => p_13_in, + I2 => p_14_in, + O => \cal1_state_r1[5]_i_1_n_0\ + ); +\cal1_state_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_state_r1[0]_i_1_n_0\, + Q => \cal1_state_r1_reg_n_0_[0]\, + R => '0' + ); +\cal1_state_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_state_r1[1]_i_1_n_0\, + Q => \cal1_state_r1_reg_n_0_[1]\, + R => '0' + ); +\cal1_state_r1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_state_r1[2]_i_1_n_0\, + Q => \cal1_state_r1_reg_n_0_[2]\, + R => '0' + ); +\cal1_state_r1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_state_r1[3]_i_1_n_0\, + Q => \cal1_state_r1_reg_n_0_[3]\, + R => '0' + ); +\cal1_state_r1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_state_r1[4]_i_1_n_0\, + Q => \cal1_state_r1_reg_n_0_[4]\, + R => '0' + ); +\cal1_state_r1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_state_r1[5]_i_1_n_0\, + Q => \cal1_state_r1_reg_n_0_[5]\, + R => '0' + ); +cal1_wait_cnt_en_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => \cal1_state_r1[5]_i_1_n_0\, + I1 => cal1_wait_cnt_en_r_i_2_n_0, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I4 => p_9_in, + I5 => p_3_in4_in, + O => cal1_wait_cnt_en_r0 + ); +cal1_wait_cnt_en_r_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + I1 => p_1_in2_in, + I2 => p_12_in, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[34]\, + O => cal1_wait_cnt_en_r_i_2_n_0 + ); +cal1_wait_cnt_en_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal1_wait_cnt_en_r0, + Q => cal1_wait_cnt_en_r, + R => '0' + ); +\cal1_wait_cnt_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cal1_wait_cnt_r_reg(0), + O => \p_0_in__0__0\(0) + ); +\cal1_wait_cnt_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cal1_wait_cnt_r_reg(0), + I1 => cal1_wait_cnt_r_reg(1), + O => \p_0_in__0__0\(1) + ); +\cal1_wait_cnt_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cal1_wait_cnt_r_reg(2), + I1 => cal1_wait_cnt_r_reg(1), + I2 => cal1_wait_cnt_r_reg(0), + O => \p_0_in__0__0\(2) + ); +\cal1_wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cal1_wait_cnt_r_reg(3), + I1 => cal1_wait_cnt_r_reg(0), + I2 => cal1_wait_cnt_r_reg(1), + I3 => cal1_wait_cnt_r_reg(2), + O => \p_0_in__0__0\(3) + ); +\cal1_wait_cnt_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"40000000FFFFFFFF" + ) + port map ( + I0 => cal1_wait_cnt_r_reg(4), + I1 => cal1_wait_cnt_r_reg(3), + I2 => cal1_wait_cnt_r_reg(0), + I3 => cal1_wait_cnt_r_reg(1), + I4 => cal1_wait_cnt_r_reg(2), + I5 => cal1_wait_cnt_en_r, + O => \cal1_wait_cnt_r[4]_i_1_n_0\ + ); +\cal1_wait_cnt_r[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => cal1_wait_cnt_r_reg(4), + I1 => cal1_wait_cnt_r_reg(2), + I2 => cal1_wait_cnt_r_reg(1), + I3 => cal1_wait_cnt_r_reg(0), + I4 => cal1_wait_cnt_r_reg(3), + O => \p_0_in__0__0\(4) + ); +\cal1_wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(0), + Q => cal1_wait_cnt_r_reg(0), + R => \cal1_wait_cnt_r[4]_i_1_n_0\ + ); +\cal1_wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(1), + Q => cal1_wait_cnt_r_reg(1), + R => \cal1_wait_cnt_r[4]_i_1_n_0\ + ); +\cal1_wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(2), + Q => cal1_wait_cnt_r_reg(2), + R => \cal1_wait_cnt_r[4]_i_1_n_0\ + ); +\cal1_wait_cnt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(3), + Q => cal1_wait_cnt_r_reg(3), + R => \cal1_wait_cnt_r[4]_i_1_n_0\ + ); +\cal1_wait_cnt_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(4), + Q => cal1_wait_cnt_r_reg(4), + R => \cal1_wait_cnt_r[4]_i_1_n_0\ + ); +cal1_wait_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"DFFFFFFFFFFFFFFF" + ) + port map ( + I0 => cal1_wait_cnt_en_r, + I1 => cal1_wait_cnt_r_reg(4), + I2 => cal1_wait_cnt_r_reg(3), + I3 => cal1_wait_cnt_r_reg(0), + I4 => cal1_wait_cnt_r_reg(1), + I5 => cal1_wait_cnt_r_reg(2), + O => cal1_wait_r_i_1_n_0 + ); +cal1_wait_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal1_wait_r_i_1_n_0, + Q => cal1_wait_r, + R => '0' + ); +\cnt_idel_dec_cpt_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7020" + ) + port map ( + I0 => found_second_edge_r_reg_n_0, + I1 => cnt_idel_dec_cpt_r1(0), + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I3 => \cnt_idel_dec_cpt_r[0]_i_2_n_0\, + I4 => \cnt_idel_dec_cpt_r[0]_i_3_n_0\, + O => cnt_idel_dec_cpt_r(0) + ); +\cnt_idel_dec_cpt_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B800B8FFB8FFB800" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\, + I1 => found_first_edge_r_reg_n_0, + I2 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\, + I4 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I5 => \right_edge_taps_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[0]_i_2_n_0\ + ); +\cnt_idel_dec_cpt_r[0]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8F88" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(0), + I1 => p_3_in4_in, + I2 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[0]_i_3_n_0\ + ); +\cnt_idel_dec_cpt_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF28AA2800" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I1 => cnt_idel_dec_cpt_r1(0), + I2 => cnt_idel_dec_cpt_r1(1), + I3 => found_second_edge_r_reg_n_0, + I4 => \cnt_idel_dec_cpt_r[1]_i_2_n_0\, + I5 => \cnt_idel_dec_cpt_r[1]_i_3_n_0\, + O => cnt_idel_dec_cpt_r(1) + ); +\cnt_idel_dec_cpt_r[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8FFB800" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\, + I1 => found_first_edge_r_reg_n_0, + I2 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\, + I4 => \cnt_idel_dec_cpt_r[1]_i_4_n_0\, + O => \cnt_idel_dec_cpt_r[1]_i_2_n_0\ + ); +\cnt_idel_dec_cpt_r[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F88F8888" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(1), + I1 => p_3_in4_in, + I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\, + I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[1]_i_3_n_0\ + ); +\cnt_idel_dec_cpt_r[1]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4BB4" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I1 => \right_edge_taps_r_reg_n_0_[1]\, + I2 => \right_edge_taps_r_reg_n_0_[2]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[1]_i_4_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF28AA2800" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I1 => cnt_idel_dec_cpt_r1(2), + I2 => \cnt_idel_dec_cpt_r[2]_i_3_n_0\, + I3 => found_second_edge_r_reg_n_0, + I4 => \cnt_idel_dec_cpt_r[2]_i_4_n_0\, + I5 => \cnt_idel_dec_cpt_r[2]_i_5_n_0\, + O => cnt_idel_dec_cpt_r(2) + ); +\cnt_idel_dec_cpt_r[2]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"08AEF751F75108AE" + ) + port map ( + I0 => \right_edge_taps_r_reg_n_0_[2]\, + I1 => \right_edge_taps_r_reg_n_0_[1]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I4 => \right_edge_taps_r_reg_n_0_[3]\, + I5 => \tap_cnt_cpt_r_reg_n_0_[2]\, + O => \cnt_idel_dec_cpt_r[2]_i_11_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I1 => \first_edge_taps_r_reg_n_0_[3]\, + O => \cnt_idel_dec_cpt_r[2]_i_12_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I1 => \first_edge_taps_r_reg_n_0_[2]\, + O => \cnt_idel_dec_cpt_r[2]_i_13_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_14\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I1 => \first_edge_taps_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[2]_i_14_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_15\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I1 => \first_edge_taps_r_reg_n_0_[0]\, + O => \cnt_idel_dec_cpt_r[2]_i_15_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => cnt_idel_dec_cpt_r1(0), + I1 => cnt_idel_dec_cpt_r1(1), + O => \cnt_idel_dec_cpt_r[2]_i_3_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8FFB800" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\, + I1 => found_first_edge_r_reg_n_0, + I2 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\, + I4 => \cnt_idel_dec_cpt_r[2]_i_11_n_0\, + O => \cnt_idel_dec_cpt_r[2]_i_4_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F888F888F88888F8" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(2), + I1 => p_3_in4_in, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I3 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\, + I4 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + I5 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[2]_i_5_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \second_edge_taps_r_reg_n_0_[3]\, + I1 => \first_edge_taps_r_reg_n_0_[3]\, + O => \cnt_idel_dec_cpt_r[2]_i_6_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \second_edge_taps_r_reg_n_0_[2]\, + I1 => \first_edge_taps_r_reg_n_0_[2]\, + O => \cnt_idel_dec_cpt_r[2]_i_7_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_8\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \second_edge_taps_r_reg_n_0_[1]\, + I1 => \first_edge_taps_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[2]_i_8_n_0\ + ); +\cnt_idel_dec_cpt_r[2]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \second_edge_taps_r_reg_n_0_[0]\, + I1 => \first_edge_taps_r_reg_n_0_[0]\, + O => \cnt_idel_dec_cpt_r[2]_i_9_n_0\ + ); +\cnt_idel_dec_cpt_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF28AA2800" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I1 => cnt_idel_dec_cpt_r1(3), + I2 => \cnt_idel_dec_cpt_r[3]_i_2_n_0\, + I3 => found_second_edge_r_reg_n_0, + I4 => \cnt_idel_dec_cpt_r[3]_i_3_n_0\, + I5 => \cnt_idel_dec_cpt_r[3]_i_4_n_0\, + O => cnt_idel_dec_cpt_r(3) + ); +\cnt_idel_dec_cpt_r[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => cnt_idel_dec_cpt_r1(2), + I1 => cnt_idel_dec_cpt_r1(1), + I2 => cnt_idel_dec_cpt_r1(0), + O => \cnt_idel_dec_cpt_r[3]_i_2_n_0\ + ); +\cnt_idel_dec_cpt_r[3]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8FFB800" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\, + I1 => found_first_edge_r_reg_n_0, + I2 => \tap_cnt_cpt_r_reg_n_0_[4]\, + I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\, + I4 => \cnt_idel_dec_cpt_r[3]_i_5_n_0\, + O => \cnt_idel_dec_cpt_r[3]_i_3_n_0\ + ); +\cnt_idel_dec_cpt_r[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F88888F8F888F888" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(3), + I1 => p_3_in4_in, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I3 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\, + I4 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\, + I5 => \cnt_idel_dec_cpt_r[3]_i_6_n_0\, + O => \cnt_idel_dec_cpt_r[3]_i_4_n_0\ + ); +\cnt_idel_dec_cpt_r[3]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\, + I1 => \right_edge_taps_r_reg_n_0_[4]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[3]\, + O => \cnt_idel_dec_cpt_r[3]_i_5_n_0\ + ); +\cnt_idel_dec_cpt_r[3]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\, + I1 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + O => \cnt_idel_dec_cpt_r[3]_i_6_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF28AA2800" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I1 => cnt_idel_dec_cpt_r1(4), + I2 => \cnt_idel_dec_cpt_r[4]_i_3_n_0\, + I3 => found_second_edge_r_reg_n_0, + I4 => \cnt_idel_dec_cpt_r[4]_i_4_n_0\, + I5 => \cnt_idel_dec_cpt_r[4]_i_5_n_0\, + O => cnt_idel_dec_cpt_r(4) + ); +\cnt_idel_dec_cpt_r[4]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2BD4D42B" + ) + port map ( + I0 => \right_edge_taps_r_reg_n_0_[4]\, + I1 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I2 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\, + I3 => \right_edge_taps_r_reg_n_0_[5]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[4]\, + O => \cnt_idel_dec_cpt_r[4]_i_10_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\, + I1 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\, + I2 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\, + I3 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + O => \cnt_idel_dec_cpt_r[4]_i_11_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[5]\, + I1 => \first_edge_taps_r_reg_n_0_[5]\, + O => \cnt_idel_dec_cpt_r[4]_i_12_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_13\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[4]\, + I1 => \first_edge_taps_r_reg_n_0_[4]\, + O => \cnt_idel_dec_cpt_r[4]_i_13_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_14\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F7510000FFFFF751" + ) + port map ( + I0 => \right_edge_taps_r_reg_n_0_[2]\, + I1 => \right_edge_taps_r_reg_n_0_[1]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I5 => \right_edge_taps_r_reg_n_0_[3]\, + O => \cnt_idel_dec_cpt_r[4]_i_14_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => cnt_idel_dec_cpt_r1(3), + I1 => cnt_idel_dec_cpt_r1(0), + I2 => cnt_idel_dec_cpt_r1(1), + I3 => cnt_idel_dec_cpt_r1(2), + O => \cnt_idel_dec_cpt_r[4]_i_3_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8FFB800" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\, + I1 => found_first_edge_r_reg_n_0, + I2 => \tap_cnt_cpt_r_reg_n_0_[5]\, + I3 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\, + I4 => \cnt_idel_dec_cpt_r[4]_i_10_n_0\, + O => \cnt_idel_dec_cpt_r[4]_i_4_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8FF88888" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(4), + I1 => p_3_in4_in, + I2 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\, + I3 => \cnt_idel_dec_cpt_r[4]_i_11_n_0\, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[4]_i_5_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \second_edge_taps_r_reg_n_0_[5]\, + I1 => \first_edge_taps_r_reg_n_0_[5]\, + O => \cnt_idel_dec_cpt_r[4]_i_6_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_7\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \second_edge_taps_r_reg_n_0_[4]\, + I1 => \first_edge_taps_r_reg_n_0_[4]\, + O => \cnt_idel_dec_cpt_r[4]_i_7_n_0\ + ); +\cnt_idel_dec_cpt_r[4]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \right_edge_taps_r_reg_n_0_[2]\, + I1 => \right_edge_taps_r_reg_n_0_[3]\, + I2 => \right_edge_taps_r_reg_n_0_[0]\, + I3 => \right_edge_taps_r_reg_n_0_[1]\, + I4 => \right_edge_taps_r_reg_n_0_[5]\, + I5 => \right_edge_taps_r_reg_n_0_[4]\, + O => \cnt_idel_dec_cpt_r[4]_i_9_n_0\ + ); +\cnt_idel_dec_cpt_r[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => mpr_dec_cpt_r, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + O => \cnt_idel_dec_cpt_r[5]_i_1_n_0\ + ); +\cnt_idel_dec_cpt_r[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF44F444F444F4" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg[5]_i_3_n_0\, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I3 => \cnt_idel_dec_cpt_r[5]_i_4_n_0\, + I4 => p_3_in4_in, + I5 => \pi_rdval_cnt_reg[5]_0\(5), + O => cnt_idel_dec_cpt_r(5) + ); +\cnt_idel_dec_cpt_r[5]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555555555556" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg_n_0_[5]\, + I1 => \cnt_idel_dec_cpt_r_reg_n_0_[3]\, + I2 => \cnt_idel_dec_cpt_r_reg_n_0_[2]\, + I3 => \cnt_idel_dec_cpt_r_reg_n_0_[1]\, + I4 => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + I5 => \cnt_idel_dec_cpt_r_reg_n_0_[4]\, + O => \cnt_idel_dec_cpt_r[5]_i_4_n_0\ + ); +\cnt_idel_dec_cpt_r[5]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFABEAFE" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r[4]_i_9_n_0\, + I1 => \cnt_idel_dec_cpt_r[5]_i_7_n_0\, + I2 => \tap_cnt_cpt_r_reg_n_0_[4]\, + I3 => \right_edge_taps_r_reg_n_0_[5]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[5]\, + O => \cnt_idel_dec_cpt_r[5]_i_5_n_0\ + ); +\cnt_idel_dec_cpt_r[5]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6AAAAAAAAAAAAAAA" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\, + I1 => cnt_idel_dec_cpt_r1(3), + I2 => cnt_idel_dec_cpt_r1(0), + I3 => cnt_idel_dec_cpt_r1(1), + I4 => cnt_idel_dec_cpt_r1(2), + I5 => cnt_idel_dec_cpt_r1(4), + O => \cnt_idel_dec_cpt_r[5]_i_6_n_0\ + ); +\cnt_idel_dec_cpt_r[5]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8E" + ) + port map ( + I0 => \cnt_idel_dec_cpt_r[4]_i_14_n_0\, + I1 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I2 => \right_edge_taps_r_reg_n_0_[4]\, + O => \cnt_idel_dec_cpt_r[5]_i_7_n_0\ + ); +\cnt_idel_dec_cpt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\, + D => cnt_idel_dec_cpt_r(0), + Q => \cnt_idel_dec_cpt_r_reg_n_0_[0]\, + R => '0' + ); +\cnt_idel_dec_cpt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\, + D => cnt_idel_dec_cpt_r(1), + Q => \cnt_idel_dec_cpt_r_reg_n_0_[1]\, + R => '0' + ); +\cnt_idel_dec_cpt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\, + D => cnt_idel_dec_cpt_r(2), + Q => \cnt_idel_dec_cpt_r_reg_n_0_[2]\, + R => '0' + ); +\cnt_idel_dec_cpt_r_reg[2]_i_10\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\, + CO(2) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1\, + CO(1) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2\, + CO(0) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3\, + CYINIT => '1', + DI(3) => \tap_cnt_cpt_r_reg_n_0_[3]\, + DI(2) => \tap_cnt_cpt_r_reg_n_0_[2]\, + DI(1) => \tap_cnt_cpt_r_reg_n_0_[1]\, + DI(0) => \tap_cnt_cpt_r_reg_n_0_[0]\, + O(3) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4\, + O(2) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5\, + O(1) => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6\, + O(0) => \NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED\(0), + S(3) => \cnt_idel_dec_cpt_r[2]_i_12_n_0\, + S(2) => \cnt_idel_dec_cpt_r[2]_i_13_n_0\, + S(1) => \cnt_idel_dec_cpt_r[2]_i_14_n_0\, + S(0) => \cnt_idel_dec_cpt_r[2]_i_15_n_0\ + ); +\cnt_idel_dec_cpt_r_reg[2]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\, + CO(2) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1\, + CO(1) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2\, + CO(0) => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3\, + CYINIT => '1', + DI(3) => \second_edge_taps_r_reg_n_0_[3]\, + DI(2) => \second_edge_taps_r_reg_n_0_[2]\, + DI(1) => \second_edge_taps_r_reg_n_0_[1]\, + DI(0) => \second_edge_taps_r_reg_n_0_[0]\, + O(3 downto 1) => cnt_idel_dec_cpt_r1(2 downto 0), + O(0) => \NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED\(0), + S(3) => \cnt_idel_dec_cpt_r[2]_i_6_n_0\, + S(2) => \cnt_idel_dec_cpt_r[2]_i_7_n_0\, + S(1) => \cnt_idel_dec_cpt_r[2]_i_8_n_0\, + S(0) => \cnt_idel_dec_cpt_r[2]_i_9_n_0\ + ); +\cnt_idel_dec_cpt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\, + D => cnt_idel_dec_cpt_r(3), + Q => \cnt_idel_dec_cpt_r_reg_n_0_[3]\, + R => '0' + ); +\cnt_idel_dec_cpt_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\, + D => cnt_idel_dec_cpt_r(4), + Q => \cnt_idel_dec_cpt_r_reg_n_0_[4]\, + R => '0' + ); +\cnt_idel_dec_cpt_r_reg[4]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0\, + CO(3) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\(3), + CO(2) => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1\, + CO(1) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED\(1), + CO(0) => \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => \second_edge_taps_r_reg_n_0_[5]\, + DI(0) => \second_edge_taps_r_reg_n_0_[4]\, + O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => cnt_idel_dec_cpt_r1(4 downto 3), + S(3 downto 2) => B"01", + S(1) => \cnt_idel_dec_cpt_r[4]_i_6_n_0\, + S(0) => \cnt_idel_dec_cpt_r[4]_i_7_n_0\ + ); +\cnt_idel_dec_cpt_r_reg[4]_i_8\: unisim.vcomponents.CARRY4 + port map ( + CI => \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0\, + CO(3 downto 1) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED\(3 downto 1), + CO(0) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => \tap_cnt_cpt_r_reg_n_0_[4]\, + O(3 downto 2) => \NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED\(3 downto 2), + O(1) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6\, + O(0) => \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7\, + S(3 downto 2) => B"00", + S(1) => \cnt_idel_dec_cpt_r[4]_i_12_n_0\, + S(0) => \cnt_idel_dec_cpt_r[4]_i_13_n_0\ + ); +\cnt_idel_dec_cpt_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \cnt_idel_dec_cpt_r[5]_i_1_n_0\, + D => cnt_idel_dec_cpt_r(5), + Q => \cnt_idel_dec_cpt_r_reg_n_0_[5]\, + R => '0' + ); +\cnt_idel_dec_cpt_r_reg[5]_i_3\: unisim.vcomponents.MUXF7 + port map ( + I0 => \cnt_idel_dec_cpt_r[5]_i_5_n_0\, + I1 => \cnt_idel_dec_cpt_r[5]_i_6_n_0\, + O => \cnt_idel_dec_cpt_r_reg[5]_i_3_n_0\, + S => found_second_edge_r_reg_n_0 + ); +\cnt_shift_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"5554" + ) + port map ( + I0 => cnt_shift_r_reg(0), + I1 => cnt_shift_r_reg(1), + I2 => cnt_shift_r_reg(3), + I3 => cnt_shift_r_reg(2), + O => \p_0_in__1\(0) + ); +\cnt_shift_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cnt_shift_r_reg(1), + I1 => cnt_shift_r_reg(0), + O => \p_0_in__1\(1) + ); +\cnt_shift_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cnt_shift_r_reg(2), + I1 => cnt_shift_r_reg(0), + I2 => cnt_shift_r_reg(1), + O => \p_0_in__1\(2) + ); +\cnt_shift_r[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cnt_shift_r_reg(3), + I1 => cnt_shift_r_reg(1), + I2 => cnt_shift_r_reg(0), + I3 => cnt_shift_r_reg(2), + O => \p_0_in__1\(3) + ); +\cnt_shift_r_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(0), + Q => cnt_shift_r_reg(0), + S => \cnt_shift_r_reg[0]_0\(0) + ); +\cnt_shift_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(1), + Q => cnt_shift_r_reg(1), + R => \cnt_shift_r_reg[0]_0\(0) + ); +\cnt_shift_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(2), + Q => cnt_shift_r_reg(2), + R => \cnt_shift_r_reg[0]_0\(0) + ); +\cnt_shift_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(3), + Q => cnt_shift_r_reg(3), + R => \cnt_shift_r_reg[0]_0\(0) + ); +\ctl_lane_cnt[1]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BF" + ) + port map ( + I0 => po_cnt_dec_reg, + I1 => \^pi_fine_dly_dec_done_reg_0\, + I2 => dqs_po_dec_done_r1_reg_0, + O => p_1_in + ); +detect_edge_done_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => pb_detect_edge_done_r(6), + I1 => pb_detect_edge_done_r(7), + I2 => pb_detect_edge_done_r(4), + I3 => pb_detect_edge_done_r(5), + I4 => detect_edge_done_r_i_2_n_0, + O => detect_edge_done_r_i_1_n_0 + ); +detect_edge_done_r_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => pb_detect_edge_done_r(1), + I1 => pb_detect_edge_done_r(0), + I2 => pb_detect_edge_done_r(3), + I3 => pb_detect_edge_done_r(2), + O => detect_edge_done_r_i_2_n_0 + ); +detect_edge_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => detect_edge_done_r_i_1_n_0, + Q => detect_edge_done_r, + R => '0' + ); +\done_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000005554" + ) + port map ( + I0 => done_cnt(0), + I1 => done_cnt(3), + I2 => done_cnt(1), + I3 => done_cnt(2), + I4 => done_cnt1, + I5 => \done_cnt_reg[2]_0\, + O => \done_cnt[0]_i_1_n_0\ + ); +\done_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FAAFFAAE" + ) + port map ( + I0 => done_cnt1, + I1 => done_cnt(3), + I2 => done_cnt(1), + I3 => done_cnt(0), + I4 => done_cnt(2), + O => \done_cnt[1]_i_1_n_0\ + ); +\done_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000A9A8" + ) + port map ( + I0 => done_cnt(2), + I1 => done_cnt(0), + I2 => done_cnt(1), + I3 => done_cnt(3), + I4 => done_cnt1, + I5 => \done_cnt_reg[2]_0\, + O => \done_cnt[2]_i_1_n_0\ + ); +\done_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEEA" + ) + port map ( + I0 => done_cnt1, + I1 => done_cnt(3), + I2 => done_cnt(1), + I3 => done_cnt(0), + I4 => done_cnt(2), + O => \done_cnt[3]_i_1_n_0\ + ); +\done_cnt[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"888F" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\, + I1 => p_0_in118_in, + I2 => \done_cnt[3]_i_3_n_0\, + I3 => rdlvl_stg1_done_int, + O => done_cnt1 + ); +\done_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => done_cnt(0), + I1 => done_cnt(1), + I2 => done_cnt(2), + I3 => done_cnt(3), + O => \done_cnt[3]_i_3_n_0\ + ); +\done_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \done_cnt[0]_i_1_n_0\, + Q => done_cnt(0), + R => '0' + ); +\done_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \done_cnt[1]_i_1_n_0\, + Q => done_cnt(1), + R => \done_cnt_reg[1]_0\ + ); +\done_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \done_cnt[2]_i_1_n_0\, + Q => done_cnt(2), + R => '0' + ); +\done_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \done_cnt[3]_i_1_n_0\, + Q => done_cnt(3), + R => \done_cnt_reg[1]_0\ + ); +dqs_po_dec_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_po_dec_done_r1_reg_0, + Q => dqs_po_dec_done_r1, + R => '0' + ); +dqs_po_dec_done_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_po_dec_done_r1, + Q => dqs_po_dec_done_r2, + R => '0' + ); +fine_dly_dec_done_r1_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF22F2" + ) + port map ( + I0 => \^pi_cnt_dec_reg_0\, + I1 => fine_dly_dec_done_r1_i_2_n_0, + I2 => dqs_po_dec_done_r2, + I3 => \pi_rdval_cnt[5]_i_3_n_0\, + I4 => fine_dly_dec_done_r1, + O => fine_dly_dec_done_r1_i_1_n_0 + ); +fine_dly_dec_done_r1_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEFF" + ) + port map ( + I0 => pi_rdval_cnt(4), + I1 => pi_rdval_cnt(5), + I2 => pi_rdval_cnt(1), + I3 => pi_rdval_cnt(0), + I4 => pi_rdval_cnt(2), + I5 => pi_rdval_cnt(3), + O => fine_dly_dec_done_r1_i_2_n_0 + ); +fine_dly_dec_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => fine_dly_dec_done_r1_i_1_n_0, + Q => fine_dly_dec_done_r1, + R => \done_cnt_reg[1]_0\ + ); +fine_dly_dec_done_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => fine_dly_dec_done_r1, + Q => fine_dly_dec_done_r2, + R => '0' + ); +\first_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"4" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => cal1_prech_req_r, + O => \first_edge_taps_r[5]_i_1_n_0\ + ); +\first_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF0000FFFF0080" + ) + port map ( + I0 => found_edge_r_reg_n_0, + I1 => store_sr_req_pulsed_r, + I2 => detect_edge_done_r, + I3 => tap_limit_cpt_r, + I4 => cal1_prech_req_r, + I5 => \first_edge_taps_r[5]_i_3_n_0\, + O => \first_edge_taps_r[5]_i_2_n_0\ + ); +\first_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => found_first_edge_r_reg_n_0, + I1 => found_stable_eye_last_r, + O => \first_edge_taps_r[5]_i_3_n_0\ + ); +\first_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \first_edge_taps_r[5]_i_2_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[0]\, + Q => \first_edge_taps_r_reg_n_0_[0]\, + R => \first_edge_taps_r[5]_i_1_n_0\ + ); +\first_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \first_edge_taps_r[5]_i_2_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[1]\, + Q => \first_edge_taps_r_reg_n_0_[1]\, + R => \first_edge_taps_r[5]_i_1_n_0\ + ); +\first_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \first_edge_taps_r[5]_i_2_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[2]\, + Q => \first_edge_taps_r_reg_n_0_[2]\, + R => \first_edge_taps_r[5]_i_1_n_0\ + ); +\first_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \first_edge_taps_r[5]_i_2_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[3]\, + Q => \first_edge_taps_r_reg_n_0_[3]\, + R => \first_edge_taps_r[5]_i_1_n_0\ + ); +\first_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \first_edge_taps_r[5]_i_2_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[4]\, + Q => \first_edge_taps_r_reg_n_0_[4]\, + R => \first_edge_taps_r[5]_i_1_n_0\ + ); +\first_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \first_edge_taps_r[5]_i_2_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[5]\, + Q => \first_edge_taps_r_reg_n_0_[5]\, + R => \first_edge_taps_r[5]_i_1_n_0\ + ); +found_edge_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\, + I1 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\, + I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\, + I3 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\, + I4 => found_edge_r_i_2_n_0, + O => found_edge_r_i_1_n_0 + ); +found_edge_r_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\, + I1 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\, + I2 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\, + I3 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\, + O => found_edge_r_i_2_n_0 + ); +found_edge_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => found_edge_r_i_1_n_0, + Q => found_edge_r_reg_n_0, + R => '0' + ); +found_first_edge_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF555555BA000000" + ) + port map ( + I0 => cal1_prech_req_r, + I1 => tap_limit_cpt_r, + I2 => detect_edge_done_r, + I3 => store_sr_req_pulsed_r, + I4 => found_edge_r_reg_n_0, + I5 => found_first_edge_r_reg_n_0, + O => found_first_edge_r_i_1_n_0 + ); +found_first_edge_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => found_first_edge_r_i_1_n_0, + Q => found_first_edge_r_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +found_second_edge_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"80FF8000" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => found_stable_eye_last_r, + I2 => found_first_edge_r_reg_n_0, + I3 => \second_edge_taps_r[5]_i_2_n_0\, + I4 => found_second_edge_r_reg_n_0, + O => found_second_edge_r_i_1_n_0 + ); +found_second_edge_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => found_second_edge_r_i_1_n_0, + Q => found_second_edge_r_reg_n_0, + R => found_second_edge_r_reg_0 + ); +found_stable_eye_last_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => found_stable_eye_r_reg_n_0, + I1 => detect_edge_done_r, + I2 => found_stable_eye_last_r, + O => found_stable_eye_last_r_i_1_n_0 + ); +found_stable_eye_last_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => found_stable_eye_last_r_i_1_n_0, + Q => found_stable_eye_last_r, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +found_stable_eye_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => pb_found_stable_eye_r(2), + I1 => pb_found_stable_eye_r(3), + I2 => pb_found_stable_eye_r(0), + I3 => pb_found_stable_eye_r(1), + I4 => found_stable_eye_r_i_2_n_0, + O => found_stable_eye_r_i_1_n_0 + ); +found_stable_eye_r_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => pb_found_stable_eye_r(5), + I1 => pb_found_stable_eye_r(4), + I2 => pb_found_stable_eye_r(7), + I3 => pb_found_stable_eye_r(6), + O => found_stable_eye_r_i_2_n_0 + ); +found_stable_eye_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => found_stable_eye_r_i_1_n_0, + Q => found_stable_eye_r_reg_n_0, + R => '0' + ); +\gen_byte_sel_div2.byte_sel_cnt[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2F202F2F2F202020" + ) + port map ( + I0 => Q(0), + I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\, + I2 => \^d\(3), + I3 => regl_dqs_cnt_r(0), + I4 => p_0_in118_in, + I5 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + O => \po_stg2_wrcal_cnt_reg[0]\ + ); +\gen_byte_sel_div2.byte_sel_cnt[1]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2F202020" + ) + port map ( + I0 => Q(1), + I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\, + I2 => \^d\(3), + I3 => p_0_in118_in, + I4 => regl_dqs_cnt_r(1), + O => \po_stg2_wrcal_cnt_reg[1]\ + ); +\gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[0].mux_rd_rise2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[0].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[1].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[2].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[3].mux_rd_rise3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[3].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_rise2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[4].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[5].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[6].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd[7].mux_rd_rise3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd[7].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\, + R => '0' + ); +\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^d\(3), + I1 => address_w(0), + O => rdlvl_stg1_done_int_reg_1 + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r[0][0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => store_sr_r_reg_n_0, + I1 => sr_valid_r_reg_n_0, + O => store_sr_r0 + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_139\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_155\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_163\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_187\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_171\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_147\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_179\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\, + Q => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_195\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_75\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_107\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_131\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_123\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_91\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_99\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_115\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\, + Q => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_83\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_140\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_156\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_164\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_188\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_172\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_148\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_180\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\, + Q => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_196\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_76\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_108\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_132\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_124\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_92\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_100\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_116\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\, + Q => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_84\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_141\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_157\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_165\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_189\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_173\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_149\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_181\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\, + Q => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_197\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_77\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_109\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_133\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_125\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_93\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_101\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_117\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\, + Q => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_85\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_142\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_158\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_166\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_190\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_174\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_150\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_182\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\, + Q => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_198\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_78\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_110\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_134\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_126\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_94\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_102\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_118\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\, + Q => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_86\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_143\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_159\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_167\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_191\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_175\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_151\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_183\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\, + Q => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_199\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_79\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_111\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_135\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_127\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_95\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_103\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_119\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\, + Q => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_87\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_144\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_160\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_168\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_192\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_176\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_152\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_184\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\, + Q => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_200\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_80\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_112\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_136\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_128\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_96\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_104\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_120\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\, + Q => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_88\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_145\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_161\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_169\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_193\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_177\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_153\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_185\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\, + Q => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_201\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_81\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_113\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_137\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_129\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_97\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_105\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_121\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\, + Q => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_89\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_146\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_162\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_170\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_194\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_178\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_154\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_186\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => store_sr_r0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\, + Q => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_202\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_82\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_114\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_138\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_130\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_98\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_106\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_122\, + R => '0' + ); +\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r_reg_n_0, + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\, + Q => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_90\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\, + Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\, + O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\, + O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0\, + Q => pat0_match_fall2_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\, + Q => pat0_match_fall3_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\, + Q => pat0_match_rise0_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\, + O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0\, + Q => pat0_match_rise1_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\, + Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\, + O => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0\, + Q => idel_pat0_match_rise3_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\, + Q => pat0_match_fall1_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\, + O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\, + O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\, + Q => idel_pat1_match_rise1_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\, + O => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0\, + Q => pat0_match_rise2_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\, + Q => pat0_match_rise3_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\, + O => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0\, + Q => pat0_match_fall0_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\, + Q => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\, + Q => pat0_match_fall0_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\, + O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0\, + Q => pat0_match_fall1_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\, + Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\, + Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\, + O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\, + Q => idel_pat1_match_rise1_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\, + O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\, + O => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0\, + Q => idel_pat0_match_rise3_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\, + O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\, + Q => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\, + O => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0\, + Q => pat0_match_fall2_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\, + Q => pat0_match_rise2_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\, + O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0\, + Q => pat0_match_fall3_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\, + Q => pat0_match_rise0_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\, + O => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0\, + Q => pat0_match_rise1_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\, + Q => pat0_match_rise3_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\, + Q => pat0_match_fall0_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\, + Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\, + O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\, + O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0\, + Q => pat0_match_fall3_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\, + O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\, + Q => pat0_match_rise1_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\, + O => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0\, + Q => pat0_match_rise2_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\, + Q => idel_pat0_match_rise3_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\, + O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\, + Q => pat0_match_fall2_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\, + Q => pat0_match_rise0_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\, + O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0\, + Q => idel_pat1_match_rise1_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\, + Q => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\, + O => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0\, + Q => pat0_match_rise3_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\, + O => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0\, + Q => pat0_match_fall1_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\, + Q => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\, + O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\, + Q => pat0_match_fall1_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\, + O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0\, + Q => pat0_match_fall2_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\, + Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\, + O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0\, + Q => pat0_match_rise0_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\, + Q => pat0_match_rise1_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\, + Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\, + O => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0\, + Q => idel_pat0_match_rise3_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\, + Q => pat0_match_fall0_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\, + O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\, + Q => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\, + O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0\, + Q => pat0_match_fall3_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\, + O => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0\, + Q => idel_pat1_match_rise1_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\, + Q => pat0_match_rise3_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\, + O => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0\, + Q => pat0_match_rise2_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\, + Q => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\, + Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\, + O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\, + O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0\, + Q => pat0_match_fall2_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\, + Q => pat0_match_fall3_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\, + Q => pat0_match_rise0_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\, + O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0\, + Q => pat0_match_rise1_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\, + Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\, + O => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0\, + Q => idel_pat0_match_rise3_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\, + Q => pat0_match_fall1_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\, + O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\, + O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\, + Q => idel_pat1_match_rise1_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\, + O => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0\, + Q => pat0_match_rise2_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\, + Q => pat0_match_rise3_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\, + O => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0\, + Q => pat0_match_fall0_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\, + Q => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\, + Q => pat0_match_fall0_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\, + O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0\, + Q => pat0_match_fall1_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\, + Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\, + Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\, + O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\, + Q => idel_pat1_match_rise1_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\, + O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\, + O => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0\, + Q => idel_pat0_match_rise3_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\, + O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\, + Q => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\, + O => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0\, + Q => pat0_match_fall2_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\, + Q => pat0_match_rise2_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\, + O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0\, + Q => pat0_match_fall3_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\, + Q => pat0_match_rise0_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\, + O => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0\, + Q => pat0_match_rise1_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\, + Q => pat0_match_rise3_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\, + Q => pat0_match_fall0_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\, + Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\, + O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\, + O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0\, + Q => pat0_match_fall3_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\, + O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\, + Q => pat0_match_rise1_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\, + O => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0\, + Q => pat0_match_rise2_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\, + Q => idel_pat0_match_rise3_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\, + O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\, + Q => pat0_match_fall2_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\, + Q => pat0_match_rise0_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\, + O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0\, + Q => idel_pat1_match_rise1_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\, + Q => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\, + O => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0\, + Q => pat0_match_rise3_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\, + O => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0\, + Q => pat0_match_fall1_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\, + Q => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\, + O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\, + Q => pat0_match_fall1_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\, + O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0\, + Q => pat0_match_fall2_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\, + Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\, + O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0\, + Q => pat0_match_rise0_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\, + Q => pat0_match_rise1_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\, + Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\, + O => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0\, + Q => idel_pat0_match_rise3_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\, + Q => pat0_match_fall0_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\, + O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\, + Q => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\, + O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0\, + Q => pat0_match_fall3_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\, + O => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0\, + Q => idel_pat1_match_rise1_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\, + Q => pat0_match_rise3_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\, + O => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0\, + Q => pat0_match_rise2_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\, + Q => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_data_match_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => idel_pat0_match_rise1_and_r, + I1 => idel_pat0_match_rise0_and_r, + I2 => idel_pat0_match_fall3_and_r, + I3 => idel_pat0_match_fall0_and_r, + I4 => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\, + O => idel_pat0_data_match_r0 + ); +\gen_pat_match_div4.idel_pat0_data_match_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => idel_pat0_match_rise3_and_r, + I1 => idel_pat0_match_fall1_and_r, + I2 => idel_pat0_match_fall2_and_r, + I3 => idel_pat0_match_rise2_and_r, + O => \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0\ + ); +\gen_pat_match_div4.idel_pat0_data_match_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idel_pat0_data_match_r0, + Q => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\, + I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\, + I3 => pat0_match_fall0_r(2), + I4 => pat0_match_fall0_r(5), + I5 => pat0_match_fall0_r(6), + O => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0\, + Q => idel_pat0_match_fall0_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\, + I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\, + I3 => pat0_match_fall1_r(1), + I4 => pat0_match_fall1_r(5), + I5 => pat0_match_fall1_r(7), + O => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0\, + Q => idel_pat0_match_fall1_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\, + I1 => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\, + I2 => pat0_match_fall2_r(3), + O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\, + I2 => pat0_match_fall2_r(0), + I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg\, + I4 => pat0_match_fall2_r(4), + I5 => pat0_match_fall2_r(7), + O => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0\, + Q => idel_pat0_match_fall2_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\, + I2 => pat0_match_fall3_r(6), + I3 => pat0_match_fall3_r(4), + I4 => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\, + O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => pat0_match_fall3_r(0), + I1 => pat0_match_fall3_r(2), + I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg\, + O => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0\, + Q => idel_pat0_match_fall3_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\, + I3 => pat0_match_rise0_r(7), + I4 => pat0_match_rise0_r(3), + O => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0\, + Q => idel_pat0_match_rise0_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\, + I1 => idel_pat1_match_rise1_r(5), + I2 => idel_pat1_match_rise1_r(1), + I3 => pat0_match_rise1_r(4), + I4 => pat0_match_rise1_r(0), + O => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0\, + Q => idel_pat0_match_rise1_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pat0_match_rise2_r(6), + I1 => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\, + I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\, + O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\, + I3 => pat0_match_rise2_r(2), + I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\, + I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\, + O => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0\, + Q => idel_pat0_match_rise2_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\, + I1 => idel_pat0_match_rise3_r(6), + I2 => idel_pat0_match_rise3_r(2), + I3 => idel_pat0_match_rise3_r(5), + I4 => idel_pat0_match_rise3_r(1), + O => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0\, + Q => idel_pat0_match_rise3_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_data_match_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => idel_pat1_match_fall0_and_r, + I1 => idel_pat1_match_rise1_and_r, + I2 => idel_pat1_match_rise3_and_r, + I3 => idel_pat1_match_fall2_and_r, + I4 => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\, + O => idel_pat1_data_match_r0 + ); +\gen_pat_match_div4.idel_pat1_data_match_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => idel_pat1_match_rise2_and_r, + I1 => idel_pat1_match_fall1_and_r, + I2 => idel_pat1_match_rise0_and_r, + I3 => idel_pat1_match_fall3_and_r, + O => \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0\ + ); +\gen_pat_match_div4.idel_pat1_data_match_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idel_pat1_data_match_r0, + Q => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\, + I1 => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\, + I2 => pat0_match_fall0_r(7), + O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg\, + I1 => pat0_match_fall0_r(3), + I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\, + I5 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\, + O => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0\, + Q => idel_pat1_match_fall0_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\, + I1 => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\, + I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg\, + O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => pat0_match_fall1_r(4), + I1 => pat0_match_fall1_r(0), + I2 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\, + I5 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\, + O => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0\, + Q => idel_pat1_match_fall1_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => pat0_match_fall2_r(6), + I1 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\, + I2 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\, + I3 => pat0_match_fall2_r(5), + I4 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\, + O => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0\, + Q => idel_pat1_match_fall2_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\, + O => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0\, + Q => idel_pat1_match_fall3_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\, + O => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0\, + Q => idel_pat1_match_rise0_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\, + I1 => idel_pat1_match_rise1_r(6), + I2 => idel_pat1_match_rise1_r(2), + I3 => idel_pat1_match_rise1_r(7), + I4 => idel_pat1_match_rise1_r(3), + O => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0\, + Q => idel_pat1_match_rise1_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\, + I1 => pat0_match_rise2_r(4), + I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\, + I3 => pat0_match_rise2_r(1), + I4 => pat0_match_rise2_r(5), + I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\, + O => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0\, + Q => idel_pat1_match_rise2_and_r, + R => '0' + ); +\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\, + I1 => idel_pat0_match_rise3_r(5), + I2 => idel_pat0_match_rise3_r(1), + I3 => pat0_match_rise3_r(6), + I4 => pat0_match_rise3_r(2), + O => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0\, + Q => idel_pat1_match_rise3_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_data_match_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => pat0_match_rise2_and_r, + I1 => pat0_match_fall2_and_r, + I2 => pat0_match_fall3_and_r, + I3 => pat0_match_rise3_and_r, + I4 => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\, + O => pat0_data_match_r0 + ); +\gen_pat_match_div4.pat0_data_match_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => pat0_match_fall1_and_r, + I1 => pat0_match_rise0_and_r, + I2 => pat0_match_fall0_and_r, + I3 => pat0_match_rise1_and_r, + O => \gen_pat_match_div4.pat0_data_match_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_data_match_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pat0_data_match_r0, + Q => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.pat0_match_fall0_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pat0_match_fall0_r(6), + I1 => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\, + I2 => pat0_match_fall0_r(7), + O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall0_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => pat0_match_fall0_r(4), + I1 => pat0_match_fall0_r(2), + I2 => pat0_match_fall0_r(0), + I3 => pat0_match_fall0_r(1), + I4 => pat0_match_fall0_r(3), + I5 => pat0_match_fall0_r(5), + O => \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0\, + Q => pat0_match_fall0_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_match_fall1_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pat0_match_fall1_r(6), + I1 => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\, + I2 => pat0_match_fall1_r(7), + O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall1_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => pat0_match_fall1_r(4), + I1 => pat0_match_fall1_r(1), + I2 => pat0_match_fall1_r(3), + I3 => pat0_match_fall1_r(2), + I4 => pat0_match_fall1_r(0), + I5 => pat0_match_fall1_r(5), + O => \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0\, + Q => pat0_match_fall1_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => pat0_match_fall2_r(7), + I1 => pat0_match_fall2_r(5), + I2 => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\, + I3 => pat0_match_fall2_r(6), + I4 => pat0_match_fall2_r(3), + O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => pat0_match_fall2_r(2), + I1 => pat0_match_fall2_r(1), + I2 => pat0_match_fall2_r(0), + I3 => pat0_match_fall2_r(4), + O => \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0\, + Q => pat0_match_fall2_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\, + I1 => pat0_match_fall3_r(4), + I2 => pat0_match_fall3_r(1), + I3 => pat0_match_fall3_r(5), + I4 => pat0_match_fall3_r(0), + O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => pat0_match_fall3_r(2), + I1 => pat0_match_fall3_r(7), + I2 => pat0_match_fall3_r(3), + I3 => pat0_match_fall3_r(6), + O => \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_fall3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0\, + Q => pat0_match_fall3_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\, + I1 => pat0_match_rise0_r(5), + I2 => pat0_match_rise0_r(1), + I3 => pat0_match_rise0_r(4), + I4 => pat0_match_rise0_r(0), + O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => pat0_match_rise0_r(2), + I1 => pat0_match_rise0_r(6), + I2 => pat0_match_rise0_r(3), + I3 => pat0_match_rise0_r(7), + O => \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0\, + Q => pat0_match_rise0_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\, + I1 => pat0_match_rise1_r(5), + I2 => pat0_match_rise1_r(1), + I3 => pat0_match_rise1_r(4), + I4 => pat0_match_rise1_r(0), + O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => pat0_match_rise1_r(3), + I1 => pat0_match_rise1_r(7), + I2 => pat0_match_rise1_r(2), + I3 => pat0_match_rise1_r(6), + O => \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0\, + Q => pat0_match_rise1_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_match_rise2_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pat0_match_rise2_r(7), + I1 => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\, + I2 => pat0_match_rise2_r(6), + O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise2_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => pat0_match_rise2_r(4), + I1 => pat0_match_rise2_r(2), + I2 => pat0_match_rise2_r(0), + I3 => pat0_match_rise2_r(1), + I4 => pat0_match_rise2_r(3), + I5 => pat0_match_rise2_r(5), + O => \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0\, + Q => pat0_match_rise2_and_r, + R => '0' + ); +\gen_pat_match_div4.pat0_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => pat0_match_rise3_r(6), + I1 => pat0_match_rise3_r(2), + I2 => pat0_match_rise3_r(5), + I3 => pat0_match_rise3_r(1), + I4 => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\, + O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => pat0_match_rise3_r(3), + I1 => pat0_match_rise3_r(7), + I2 => pat0_match_rise3_r(0), + I3 => pat0_match_rise3_r(4), + O => \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat0_match_rise3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0\, + Q => pat0_match_rise3_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_data_match_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => pat1_match_rise0_and_r, + I1 => pat1_match_rise3_and_r, + I2 => pat1_match_fall3_and_r, + I3 => pat1_match_rise2_and_r, + I4 => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\, + O => pat1_data_match_r0 + ); +\gen_pat_match_div4.pat1_data_match_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => pat1_match_fall1_and_r, + I1 => pat1_match_fall2_and_r, + I2 => pat1_match_fall0_and_r, + I3 => pat1_match_rise1_and_r, + O => \gen_pat_match_div4.pat1_data_match_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_data_match_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pat1_data_match_r0, + Q => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.pat1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg\, + I2 => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\, + I3 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg\, + I4 => pat0_match_fall0_r(5), + I5 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg\, + O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg\, + I1 => pat0_match_fall0_r(1), + I2 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg\, + O => \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0\, + Q => pat1_match_fall0_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg\, + I2 => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\, + I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg\, + I5 => pat0_match_fall1_r(7), + O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => pat0_match_fall1_r(3), + I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg\, + O => \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0\, + Q => pat1_match_fall1_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg\, + I1 => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\, + I2 => \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg\, + O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg\, + I2 => pat0_match_fall2_r(1), + I3 => \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg\, + I5 => pat0_match_fall2_r(5), + O => \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0\, + Q => pat1_match_fall2_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg\, + I2 => pat0_match_fall3_r(7), + I3 => pat0_match_fall3_r(5), + I4 => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\, + O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => pat0_match_fall3_r(1), + I1 => pat0_match_fall3_r(3), + I2 => \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg\, + O => \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0\, + Q => pat1_match_fall3_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg\, + O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => pat0_match_rise0_r(0), + I1 => pat0_match_rise0_r(4), + I2 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg\, + O => \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0\, + Q => pat1_match_rise0_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\, + I1 => idel_pat1_match_rise1_r(7), + I2 => idel_pat1_match_rise1_r(3), + I3 => pat0_match_rise1_r(6), + I4 => pat0_match_rise1_r(2), + O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => idel_pat1_match_rise1_r(0), + I1 => idel_pat1_match_rise1_r(4), + I2 => idel_pat1_match_rise1_r(1), + I3 => idel_pat1_match_rise1_r(5), + O => \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0\, + Q => pat1_match_rise1_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000000000000000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg\, + I1 => pat0_match_rise2_r(4), + I2 => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\, + I3 => \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg\, + I5 => \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg\, + O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg\, + I2 => pat0_match_rise2_r(0), + O => \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0\, + Q => pat1_match_rise2_and_r, + R => '0' + ); +\gen_pat_match_div4.pat1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => pat0_match_rise3_r(6), + I1 => pat0_match_rise3_r(2), + I2 => pat0_match_rise3_r(5), + I3 => pat0_match_rise3_r(1), + I4 => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\, + O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => idel_pat0_match_rise3_r(4), + I1 => idel_pat0_match_rise3_r(7), + I2 => idel_pat0_match_rise3_r(0), + I3 => idel_pat0_match_rise3_r(3), + O => \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0\, + Q => pat1_match_rise3_and_r, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\, + R => '0' + ); +\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\, + I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\, + I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\, + I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\, + I4 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\, + I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\, + I2 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\, + I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_139\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_155\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_163\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_187\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_171\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_147\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_179\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\, + I3 => \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_195\, + O => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sr_valid_r2, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\, + I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\, + I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\, + I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\, + I4 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\, + I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\, + I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\, + I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_75\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_107\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_131\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_123\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_91\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_99\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_115\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59\, + I3 => \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_83\, + O => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0\, + Q => \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg\, + Q => p_1_in29_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in222_in, + I1 => p_5_in220_in, + I2 => p_6_in221_in, + I3 => p_1_in223_in, + I4 => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_3_in218_in, + I1 => p_4_in219_in, + I2 => p_0_in216_in, + I3 => p_2_in217_in, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_140\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0\, + Q => p_0_in216_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_156\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0\, + Q => p_3_in218_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_164\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0\, + Q => p_5_in220_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_188\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0\, + Q => p_7_in222_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_172\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0\, + Q => p_1_in223_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_148\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0\, + Q => p_2_in217_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_180\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0\, + Q => p_4_in219_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\, + I3 => \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_196\, + O => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0\, + Q => p_6_in221_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg\, + Q => p_0_in103_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_2_in225_in, + I1 => p_0_in224_in, + I2 => p_6_in229_in, + I3 => p_3_in226_in, + I4 => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_7_in230_in, + I1 => p_1_in231_in, + I2 => p_4_in227_in, + I3 => p_5_in228_in, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_76\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0\, + Q => p_0_in224_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_108\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0\, + Q => p_3_in226_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_132\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0\, + Q => p_5_in228_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_124\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0\, + Q => p_7_in230_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_92\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0\, + Q => p_1_in231_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_100\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0\, + Q => p_2_in225_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_116\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0\, + Q => p_4_in227_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60\, + I3 => \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_84\, + O => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0\, + Q => p_6_in229_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg\, + Q => p_1_in26_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in206_in, + I1 => p_5_in204_in, + I2 => p_6_in205_in, + I3 => p_1_in207_in, + I4 => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_3_in202_in, + I1 => p_4_in203_in, + I2 => p_0_in200_in, + I3 => p_2_in201_in, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_141\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0\, + Q => p_0_in200_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_157\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0\, + Q => p_3_in202_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_165\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0\, + Q => p_5_in204_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_189\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0\, + Q => p_7_in206_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_173\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0\, + Q => p_1_in207_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_149\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0\, + Q => p_2_in201_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_181\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0\, + Q => p_4_in203_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\, + I3 => \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_197\, + O => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0\, + Q => p_6_in205_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg\, + Q => p_0_in100_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in214_in, + I1 => p_5_in212_in, + I2 => p_6_in213_in, + I3 => p_1_in215_in, + I4 => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_3_in210_in, + I1 => p_4_in211_in, + I2 => p_0_in208_in, + I3 => p_2_in209_in, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_77\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0\, + Q => p_0_in208_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_109\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0\, + Q => p_3_in210_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_133\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0\, + Q => p_5_in212_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_125\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0\, + Q => p_7_in214_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_93\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0\, + Q => p_1_in215_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_101\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0\, + Q => p_2_in209_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_117\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0\, + Q => p_4_in211_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61\, + I3 => \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_85\, + O => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0\, + Q => p_6_in213_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg\, + Q => p_1_in23_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in190_in, + I1 => p_4_in187_in, + I2 => p_0_in184_in, + I3 => p_1_in191_in, + I4 => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_2_in185_in, + I1 => p_3_in186_in, + I2 => p_5_in188_in, + I3 => p_6_in189_in, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_142\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0\, + Q => p_0_in184_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_158\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0\, + Q => p_3_in186_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_166\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0\, + Q => p_5_in188_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_190\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0\, + Q => p_7_in190_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_174\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0\, + Q => p_1_in191_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_150\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0\, + Q => p_2_in185_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_182\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0\, + Q => p_4_in187_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\, + I3 => \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_198\, + O => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0\, + Q => p_6_in189_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg\, + Q => p_0_in97_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_4_in195_in, + I1 => p_7_in198_in, + I2 => p_6_in197_in, + I3 => p_1_in199_in, + I4 => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_3_in194_in, + I1 => p_5_in196_in, + I2 => p_0_in192_in, + I3 => p_2_in193_in, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_78\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0\, + Q => p_0_in192_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_110\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0\, + Q => p_3_in194_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_134\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0\, + Q => p_5_in196_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_126\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0\, + Q => p_7_in198_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_94\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0\, + Q => p_1_in199_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_102\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0\, + Q => p_2_in193_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_118\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0\, + Q => p_4_in195_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62\, + I3 => \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_86\, + O => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0\, + Q => p_6_in197_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg\, + Q => p_1_in20_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_6_in173_in, + I1 => p_5_in172_in, + I2 => p_7_in174_in, + I3 => p_1_in175_in, + I4 => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_3_in170_in, + I1 => p_4_in171_in, + I2 => p_0_in168_in, + I3 => p_2_in169_in, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_143\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0\, + Q => p_0_in168_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_159\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0\, + Q => p_3_in170_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_167\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0\, + Q => p_5_in172_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_191\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0\, + Q => p_7_in174_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_175\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0\, + Q => p_1_in175_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_151\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0\, + Q => p_2_in169_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_183\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0\, + Q => p_4_in171_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\, + I3 => \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_199\, + O => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0\, + Q => p_6_in173_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg\, + Q => p_0_in94_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_6_in181_in, + I1 => p_5_in180_in, + I2 => p_7_in182_in, + I3 => p_1_in183_in, + I4 => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_3_in178_in, + I1 => p_4_in179_in, + I2 => p_0_in176_in, + I3 => p_2_in177_in, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_79\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0\, + Q => p_0_in176_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_111\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0\, + Q => p_3_in178_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_135\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0\, + Q => p_5_in180_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_127\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0\, + Q => p_7_in182_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_95\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0\, + Q => p_1_in183_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_103\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0\, + Q => p_2_in177_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_119\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0\, + Q => p_4_in179_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63\, + I3 => \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_87\, + O => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0\, + Q => p_6_in181_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg\, + Q => p_1_in17_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in158_in, + I1 => p_6_in157_in, + I2 => p_0_in152_in, + I3 => p_1_in159_in, + I4 => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_4_in155_in, + I1 => p_5_in156_in, + I2 => p_2_in153_in, + I3 => p_3_in154_in, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_144\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0\, + Q => p_0_in152_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_160\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0\, + Q => p_3_in154_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_168\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0\, + Q => p_5_in156_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_192\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0\, + Q => p_7_in158_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_176\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0\, + Q => p_1_in159_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_152\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0\, + Q => p_2_in153_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_184\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0\, + Q => p_4_in155_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\, + I3 => \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_200\, + O => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0\, + Q => p_6_in157_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg\, + Q => p_0_in91_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in166_in, + I1 => p_6_in165_in, + I2 => p_0_in160_in, + I3 => p_1_in167_in, + I4 => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_4_in163_in, + I1 => p_5_in164_in, + I2 => p_2_in161_in, + I3 => p_3_in162_in, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_80\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0\, + Q => p_0_in160_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_112\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0\, + Q => p_3_in162_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_136\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0\, + Q => p_5_in164_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_128\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0\, + Q => p_7_in166_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_96\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0\, + Q => p_1_in167_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_104\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0\, + Q => p_2_in161_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_120\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0\, + Q => p_4_in163_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64\, + I3 => \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_88\, + O => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0\, + Q => p_6_in165_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg\, + Q => p_1_in14_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in142_in, + I1 => p_6_in141_in, + I2 => p_0_in136_in, + I3 => p_1_in143_in, + I4 => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_4_in139_in, + I1 => p_5_in140_in, + I2 => p_2_in137_in, + I3 => p_3_in138_in, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_145\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0\, + Q => p_0_in136_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_161\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0\, + Q => p_3_in138_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_169\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0\, + Q => p_5_in140_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_193\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0\, + Q => p_7_in142_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_177\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0\, + Q => p_1_in143_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_153\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0\, + Q => p_2_in137_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_185\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0\, + Q => p_4_in139_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\, + I3 => \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_201\, + O => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0\, + Q => p_6_in141_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg\, + Q => p_0_in88_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in150_in, + I1 => p_6_in149_in, + I2 => p_0_in144_in, + I3 => p_1_in151_in, + I4 => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_4_in147_in, + I1 => p_5_in148_in, + I2 => p_2_in145_in, + I3 => p_3_in146_in, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_81\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0\, + Q => p_0_in144_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_113\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0\, + Q => p_3_in146_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_137\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0\, + Q => p_5_in148_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_129\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0\, + Q => p_7_in150_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_97\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0\, + Q => p_1_in151_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_105\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0\, + Q => p_2_in145_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_121\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0\, + Q => p_4_in147_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65\, + I3 => \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_89\, + O => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0\, + Q => p_6_in149_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg\, + Q => p_1_in12_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in, + I1 => p_6_in126_in, + I2 => p_0_in125_in, + I3 => p_1_in127_in, + I4 => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_4_in, + I1 => p_5_in, + I2 => p_2_in, + I3 => p_3_in, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_146\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0\, + Q => p_0_in125_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_162\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0\, + Q => p_3_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_170\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0\, + Q => p_5_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_194\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0\, + Q => p_7_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_178\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0\, + Q => p_1_in127_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_154\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0\, + Q => p_2_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_186\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0\, + Q => p_4_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\, + I3 => \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_202\, + O => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0\, + Q => p_6_in126_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg\, + Q => p_0_in, + R => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF7FFF" + ) + port map ( + I0 => p_7_in134_in, + I1 => p_6_in133_in, + I2 => p_0_in128_in, + I3 => p_1_in135_in, + I4 => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => p_4_in131_in, + I1 => p_5_in132_in, + I2 => p_2_in129_in, + I3 => p_3_in130_in, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv\: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg0\, + Q => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg\, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_82\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0\, + Q => p_0_in128_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_114\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0\, + Q => p_3_in130_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_138\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0\, + Q => p_5_in132_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_130\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0\, + Q => p_7_in134_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_98\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0\, + Q => p_1_in135_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_106\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0\, + Q => p_2_in129_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_122\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0\, + Q => p_4_in131_in, + R => '0' + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E00E" + ) + port map ( + I0 => \gen_pat_match_div4.pat1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.pat0_data_match_r_reg_n_0\, + I2 => \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66\, + I3 => \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_90\, + O => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\ + ); +\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0\, + Q => p_6_in133_in, + R => '0' + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(0), + O => \p_0_in__2\(0) + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(0), + I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(1), + O => \p_0_in__2\(1) + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(2), + I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(1), + I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(0), + O => \p_0_in__2\(2) + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(3), + I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(0), + I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(1), + I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(2), + O => \p_0_in__2\(3) + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\, + O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(0), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => pb_cnt_eye_size_r + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(4), + I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(2), + I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(1), + I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(0), + I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(3), + O => \p_0_in__2\(4) + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\, + I1 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\, + I2 => pb_detect_edge_done_r(0), + I3 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\, + I4 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0\ + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(4), + I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(2), + I2 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(1), + I3 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(0), + I4 => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(3), + O => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\ + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pb_cnt_eye_size_r, + D => \p_0_in__2\(0), + Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(0), + R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pb_cnt_eye_size_r, + D => \p_0_in__2\(1), + Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(1), + R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pb_cnt_eye_size_r, + D => \p_0_in__2\(2), + Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(2), + R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pb_cnt_eye_size_r, + D => \p_0_in__2\(3), + Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(3), + R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => pb_cnt_eye_size_r, + D => \p_0_in__2\(4), + Q => \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203\(4), + R => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\, + I3 => samp_cnt_done_r_reg_n_0, + I4 => pb_detect_edge_done_r(0), + O => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_detect_edge_done_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0\, + Q => pb_detect_edge_done_r(0), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[0].pb_found_edge_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\, + I3 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\, + I4 => pb_detect_edge_done_r(0), + I5 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0\, + O => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_found_edge_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0\, + Q => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => pb_found_stable_eye_r77_out, + I1 => \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(0), + I4 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0\, + I5 => pb_found_stable_eye_r(0), + O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0]\, + I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\, + O => pb_found_stable_eye_r77_out + ); +\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => p_37_in, + O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\ + ); +\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\, + I2 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\, + I3 => \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0]\, + O => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0\ + ); +\gen_track_left_edge[0].pb_found_stable_eye_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0\, + Q => pb_found_stable_eye_r(0), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(0), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0]\, + I4 => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\ + ); +\gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0\, + Q => \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0]\, + R => '0' + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(0), + O => \p_0_in__3\(0) + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(0), + I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(1), + O => \p_0_in__3\(1) + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(2), + I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(1), + I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(0), + O => \p_0_in__3\(2) + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(3), + I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(0), + I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(1), + I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(2), + O => \p_0_in__3\(3) + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\, + O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(1), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(4), + I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(2), + I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(1), + I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(0), + I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(3), + O => \p_0_in__3\(4) + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => p_0_in103_in, + I1 => p_1_in29_in, + I2 => pb_detect_edge_done_r(1), + I3 => p_0_in28_in, + I4 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(4), + I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(2), + I2 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(1), + I3 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(0), + I4 => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(3), + O => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\, + D => \p_0_in__3\(0), + Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(0), + R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\, + D => \p_0_in__3\(1), + Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(1), + R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\, + D => \p_0_in__3\(2), + Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(2), + R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\, + D => \p_0_in__3\(3), + Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(3), + R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0\, + D => \p_0_in__3\(4), + Q => \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204\(4), + R => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => samp_cnt_done_r_reg_n_0, + I3 => p_0_in103_in, + I4 => pb_detect_edge_done_r(1), + O => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_detect_edge_done_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0\, + Q => pb_detect_edge_done_r(1), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[1].pb_found_edge_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\, + I3 => p_0_in28_in, + I4 => pb_detect_edge_done_r(1), + I5 => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0\, + O => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_found_edge_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0\, + Q => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => pb_found_stable_eye_r73_out, + I1 => \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(1), + I4 => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0\, + I5 => pb_found_stable_eye_r(1), + O => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1]\, + I2 => p_0_in28_in, + O => pb_found_stable_eye_r73_out + ); +\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_0_in103_in, + I1 => samp_cnt_done_r_reg_n_0, + I2 => p_0_in28_in, + I3 => p_1_in29_in, + O => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0\ + ); +\gen_track_left_edge[1].pb_found_stable_eye_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0\, + Q => pb_found_stable_eye_r(1), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(1), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => p_0_in103_in, + I4 => p_0_in28_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\ + ); +\gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0\, + Q => p_0_in28_in, + R => '0' + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(0), + O => \p_0_in__4\(0) + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(0), + I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(1), + O => \p_0_in__4\(1) + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(2), + I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(1), + I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(0), + O => \p_0_in__4\(2) + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(3), + I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(0), + I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(1), + I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(2), + O => \p_0_in__4\(3) + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\, + O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(2), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(4), + I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(2), + I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(1), + I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(0), + I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(3), + O => \p_0_in__4\(4) + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => p_0_in100_in, + I1 => p_1_in26_in, + I2 => pb_detect_edge_done_r(2), + I3 => p_0_in25_in, + I4 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(4), + I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(2), + I2 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(1), + I3 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(0), + I4 => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(3), + O => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\, + D => \p_0_in__4\(0), + Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(0), + R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\, + D => \p_0_in__4\(1), + Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(1), + R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\, + D => \p_0_in__4\(2), + Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(2), + R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\, + D => \p_0_in__4\(3), + Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(3), + R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0\, + D => \p_0_in__4\(4), + Q => \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205\(4), + R => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => samp_cnt_done_r_reg_n_0, + I3 => p_0_in100_in, + I4 => pb_detect_edge_done_r(2), + O => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_detect_edge_done_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0\, + Q => pb_detect_edge_done_r(2), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[2].pb_found_edge_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\, + I3 => p_0_in25_in, + I4 => pb_detect_edge_done_r(2), + I5 => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0\, + O => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_found_edge_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0\, + Q => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => pb_found_stable_eye_r69_out, + I1 => \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(2), + I4 => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0\, + I5 => pb_found_stable_eye_r(2), + O => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2]\, + I2 => p_0_in25_in, + O => pb_found_stable_eye_r69_out + ); +\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_0_in100_in, + I1 => samp_cnt_done_r_reg_n_0, + I2 => p_0_in25_in, + I3 => p_1_in26_in, + O => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0\ + ); +\gen_track_left_edge[2].pb_found_stable_eye_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0\, + Q => pb_found_stable_eye_r(2), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(2), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => p_0_in100_in, + I4 => p_0_in25_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\ + ); +\gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0\, + Q => p_0_in25_in, + R => '0' + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(0), + O => \p_0_in__5\(0) + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(0), + I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(1), + O => \p_0_in__5\(1) + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(2), + I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(1), + I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(0), + O => \p_0_in__5\(2) + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(3), + I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(0), + I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(1), + I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(2), + O => \p_0_in__5\(3) + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\, + O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(3), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(4), + I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(2), + I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(1), + I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(0), + I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(3), + O => \p_0_in__5\(4) + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => p_0_in97_in, + I1 => p_1_in23_in, + I2 => pb_detect_edge_done_r(3), + I3 => p_0_in22_in, + I4 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(4), + I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(2), + I2 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(1), + I3 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(0), + I4 => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(3), + O => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\, + D => \p_0_in__5\(0), + Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(0), + R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\, + D => \p_0_in__5\(1), + Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(1), + R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\, + D => \p_0_in__5\(2), + Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(2), + R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\, + D => \p_0_in__5\(3), + Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(3), + R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0\, + D => \p_0_in__5\(4), + Q => \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206\(4), + R => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => samp_cnt_done_r_reg_n_0, + I3 => p_0_in97_in, + I4 => pb_detect_edge_done_r(3), + O => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_detect_edge_done_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0\, + Q => pb_detect_edge_done_r(3), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[3].pb_found_edge_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\, + I3 => p_0_in22_in, + I4 => pb_detect_edge_done_r(3), + I5 => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0\, + O => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_found_edge_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0\, + Q => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => pb_found_stable_eye_r65_out, + I1 => \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(3), + I4 => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0\, + I5 => pb_found_stable_eye_r(3), + O => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3]\, + I2 => p_0_in22_in, + O => pb_found_stable_eye_r65_out + ); +\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_0_in97_in, + I1 => samp_cnt_done_r_reg_n_0, + I2 => p_0_in22_in, + I3 => p_1_in23_in, + O => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0\ + ); +\gen_track_left_edge[3].pb_found_stable_eye_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0\, + Q => pb_found_stable_eye_r(3), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(3), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => p_0_in97_in, + I4 => p_0_in22_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\ + ); +\gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0\, + Q => p_0_in22_in, + R => '0' + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(0), + O => \p_0_in__6\(0) + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(0), + I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(1), + O => \p_0_in__6\(1) + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(2), + I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(1), + I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(0), + O => \p_0_in__6\(2) + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(3), + I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(0), + I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(1), + I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(2), + O => \p_0_in__6\(3) + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\, + O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(4), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(4), + I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(2), + I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(1), + I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(0), + I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(3), + O => \p_0_in__6\(4) + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => p_0_in94_in, + I1 => p_1_in20_in, + I2 => pb_detect_edge_done_r(4), + I3 => p_0_in19_in, + I4 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(4), + I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(2), + I2 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(1), + I3 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(0), + I4 => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(3), + O => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\, + D => \p_0_in__6\(0), + Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(0), + R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\, + D => \p_0_in__6\(1), + Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(1), + R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\, + D => \p_0_in__6\(2), + Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(2), + R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\, + D => \p_0_in__6\(3), + Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(3), + R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0\, + D => \p_0_in__6\(4), + Q => \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207\(4), + R => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => samp_cnt_done_r_reg_n_0, + I3 => p_0_in94_in, + I4 => pb_detect_edge_done_r(4), + O => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_detect_edge_done_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0\, + Q => pb_detect_edge_done_r(4), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[4].pb_found_edge_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\, + I3 => p_0_in19_in, + I4 => pb_detect_edge_done_r(4), + I5 => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0\, + O => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_found_edge_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0\, + Q => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => pb_found_stable_eye_r61_out, + I1 => \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(4), + I4 => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0\, + I5 => pb_found_stable_eye_r(4), + O => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4]\, + I2 => p_0_in19_in, + O => pb_found_stable_eye_r61_out + ); +\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_0_in94_in, + I1 => samp_cnt_done_r_reg_n_0, + I2 => p_0_in19_in, + I3 => p_1_in20_in, + O => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0\ + ); +\gen_track_left_edge[4].pb_found_stable_eye_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0\, + Q => pb_found_stable_eye_r(4), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(4), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => p_0_in94_in, + I4 => p_0_in19_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\ + ); +\gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0\, + Q => p_0_in19_in, + R => '0' + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(0), + O => \p_0_in__7\(0) + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(0), + I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(1), + O => \p_0_in__7\(1) + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(2), + I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(1), + I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(0), + O => \p_0_in__7\(2) + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(3), + I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(0), + I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(1), + I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(2), + O => \p_0_in__7\(3) + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\, + O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(5), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(4), + I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(2), + I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(1), + I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(0), + I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(3), + O => \p_0_in__7\(4) + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => p_0_in91_in, + I1 => p_1_in17_in, + I2 => pb_detect_edge_done_r(5), + I3 => p_0_in16_in, + I4 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(4), + I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(2), + I2 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(1), + I3 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(0), + I4 => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(3), + O => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\, + D => \p_0_in__7\(0), + Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(0), + R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\, + D => \p_0_in__7\(1), + Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(1), + R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\, + D => \p_0_in__7\(2), + Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(2), + R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\, + D => \p_0_in__7\(3), + Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(3), + R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0\, + D => \p_0_in__7\(4), + Q => \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208\(4), + R => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => samp_cnt_done_r_reg_n_0, + I3 => p_0_in91_in, + I4 => pb_detect_edge_done_r(5), + O => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_detect_edge_done_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0\, + Q => pb_detect_edge_done_r(5), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[5].pb_found_edge_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\, + I3 => p_0_in16_in, + I4 => pb_detect_edge_done_r(5), + I5 => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0\, + O => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_found_edge_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0\, + Q => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => pb_found_stable_eye_r57_out, + I1 => \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(5), + I4 => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0\, + I5 => pb_found_stable_eye_r(5), + O => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5]\, + I2 => p_0_in16_in, + O => pb_found_stable_eye_r57_out + ); +\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_0_in91_in, + I1 => samp_cnt_done_r_reg_n_0, + I2 => p_0_in16_in, + I3 => p_1_in17_in, + O => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0\ + ); +\gen_track_left_edge[5].pb_found_stable_eye_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0\, + Q => pb_found_stable_eye_r(5), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(5), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => p_0_in91_in, + I4 => p_0_in16_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\ + ); +\gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0\, + Q => p_0_in16_in, + R => '0' + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(0), + O => \p_0_in__8\(0) + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(0), + I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(1), + O => \p_0_in__8\(1) + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(2), + I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(1), + I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(0), + O => \p_0_in__8\(2) + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(3), + I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(0), + I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(1), + I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(2), + O => \p_0_in__8\(3) + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\, + O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(6), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(4), + I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(2), + I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(1), + I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(0), + I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(3), + O => \p_0_in__8\(4) + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => p_0_in88_in, + I1 => p_1_in14_in, + I2 => pb_detect_edge_done_r(6), + I3 => p_0_in13_in, + I4 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(4), + I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(2), + I2 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(1), + I3 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(0), + I4 => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(3), + O => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\, + D => \p_0_in__8\(0), + Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(0), + R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\, + D => \p_0_in__8\(1), + Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(1), + R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\, + D => \p_0_in__8\(2), + Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(2), + R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\, + D => \p_0_in__8\(3), + Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(3), + R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0\, + D => \p_0_in__8\(4), + Q => \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209\(4), + R => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => samp_cnt_done_r_reg_n_0, + I3 => p_0_in88_in, + I4 => pb_detect_edge_done_r(6), + O => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_detect_edge_done_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0\, + Q => pb_detect_edge_done_r(6), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[6].pb_found_edge_r[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\, + I3 => p_0_in13_in, + I4 => pb_detect_edge_done_r(6), + I5 => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0\, + O => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_found_edge_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0\, + Q => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => pb_found_stable_eye_r53_out, + I1 => \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(6), + I4 => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0\, + I5 => pb_found_stable_eye_r(6), + O => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6]\, + I2 => p_0_in13_in, + O => pb_found_stable_eye_r53_out + ); +\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_0_in88_in, + I1 => samp_cnt_done_r_reg_n_0, + I2 => p_0_in13_in, + I3 => p_1_in14_in, + O => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0\ + ); +\gen_track_left_edge[6].pb_found_stable_eye_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0\, + Q => pb_found_stable_eye_r(6), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(6), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => p_0_in88_in, + I4 => p_0_in13_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\ + ); +\gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0\, + Q => p_0_in13_in, + R => '0' + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(0), + O => \p_0_in__9\(0) + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(0), + I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(1), + O => \p_0_in__9\(1) + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(2), + I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(1), + I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(0), + O => \p_0_in__9\(2) + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(3), + I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(0), + I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(1), + I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(2), + O => \p_0_in__9\(3) + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAA" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => store_sr_req_pulsed_r, + I2 => p_37_in, + I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\, + O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"22200000" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\, + I1 => pb_detect_edge_done_r(7), + I2 => p_37_in, + I3 => store_sr_req_pulsed_r, + I4 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(4), + I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(2), + I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(1), + I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(0), + I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(3), + O => \p_0_in__9\(4) + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0F0F0F000F0E0F0E" + ) + port map ( + I0 => p_0_in, + I1 => p_1_in12_in, + I2 => pb_detect_edge_done_r(7), + I3 => p_0_in11_in, + I4 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\, + I5 => samp_cnt_done_r_reg_n_0, + O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFFFFFF" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(4), + I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(2), + I2 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(1), + I3 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(0), + I4 => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(3), + O => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\, + D => \p_0_in__9\(0), + Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(0), + R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\, + D => \p_0_in__9\(1), + Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(1), + R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\, + D => \p_0_in__9\(2), + Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(2), + R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\, + D => \p_0_in__9\(3), + Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(3), + R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0\, + D => \p_0_in__9\(4), + Q => \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210\(4), + R => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EEEEEEE0" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + I2 => samp_cnt_done_r_reg_n_0, + I3 => p_0_in, + I4 => pb_detect_edge_done_r(7), + O => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_detect_edge_done_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0\, + Q => pb_detect_edge_done_r(7), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[7].pb_found_edge_r[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5050505050505551" + ) + port map ( + I0 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I1 => samp_cnt_done_r_reg_n_0, + I2 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\, + I3 => p_0_in11_in, + I4 => pb_detect_edge_done_r(7), + I5 => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0\, + O => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_found_edge_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0\, + Q => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\, + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFA00000002" + ) + port map ( + I0 => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0\, + I1 => \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0\, + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => pb_detect_edge_done_r(7), + I4 => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0\, + I5 => pb_found_stable_eye_r(7), + O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7]\, + I2 => p_0_in11_in, + O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0\ + ); +\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => p_0_in, + I1 => samp_cnt_done_r_reg_n_0, + I2 => p_0_in11_in, + I3 => p_1_in12_in, + O => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0\ + ); +\gen_track_left_edge[7].pb_found_stable_eye_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0\, + Q => pb_found_stable_eye_r(7), + R => \FSM_onehot_cal1_state_r_reg_n_0_[16]\ + ); +\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FDFD0100" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => pb_detect_edge_done_r(7), + I2 => \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0\, + I3 => p_0_in, + I4 => p_0_in11_in, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + O => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\ + ); +\gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0\, + Q => p_0_in11_in, + R => '0' + ); +idel_adj_inc_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"C580" + ) + port map ( + I0 => \idel_dec_cnt[4]_i_3_n_0\, + I1 => cal1_wait_r, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[3]\, + I3 => idel_adj_inc_reg_n_0, + O => idel_adj_inc_i_1_n_0 + ); +idel_adj_inc_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idel_adj_inc_i_1_n_0, + Q => idel_adj_inc_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +\idel_dec_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F444F4F4F4444444" + ) + port map ( + I0 => \idel_dec_cnt_reg_n_0_[0]\, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\, + I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\, + O => idel_dec_cnt(0) + ); +\idel_dec_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF909090" + ) + port map ( + I0 => \idel_dec_cnt_reg_n_0_[0]\, + I1 => \idel_dec_cnt_reg_n_0_[1]\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I4 => idelay_tap_cnt_r(1), + O => idel_dec_cnt(1) + ); +\idel_dec_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF888288828882" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I1 => \idel_dec_cnt_reg_n_0_[2]\, + I2 => \idel_dec_cnt_reg_n_0_[1]\, + I3 => \idel_dec_cnt_reg_n_0_[0]\, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I5 => idelay_tap_cnt_r(2), + O => idel_dec_cnt(2) + ); +\idel_dec_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF282828" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I1 => \idel_dec_cnt_reg_n_0_[3]\, + I2 => \idel_dec_cnt[3]_i_2_n_0\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I4 => idelay_tap_cnt_r(3), + O => idel_dec_cnt(3) + ); +\idel_dec_cnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \idel_dec_cnt_reg_n_0_[1]\, + I1 => \idel_dec_cnt_reg_n_0_[0]\, + I2 => \idel_dec_cnt_reg_n_0_[2]\, + O => \idel_dec_cnt[3]_i_2_n_0\ + ); +\idel_dec_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEEEFEEEFEEE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[15]_i_2_n_0\, + I1 => \idel_dec_cnt[4]_i_3_n_0\, + I2 => \FSM_onehot_cal1_state_r[22]_i_2_n_0\, + I3 => idel_mpr_pat_detect_r, + I4 => \idel_dec_cnt[4]_i_4_n_0\, + I5 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + O => \idel_dec_cnt[4]_i_1_n_0\ + ); +\idel_dec_cnt[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF606060" + ) + port map ( + I0 => \idel_dec_cnt_reg_n_0_[4]\, + I1 => \idel_dec_cnt[4]_i_5_n_0\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[15]\, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[1]\, + I4 => idelay_tap_cnt_r(4), + O => idel_dec_cnt(4) + ); +\idel_dec_cnt[4]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A800" + ) + port map ( + I0 => detect_edge_done_r, + I1 => \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0\, + I2 => \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0\, + I3 => p_37_in, + O => \idel_dec_cnt[4]_i_3_n_0\ + ); +\idel_dec_cnt[4]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \idel_dec_cnt_reg_n_0_[4]\, + I1 => \idel_dec_cnt_reg_n_0_[3]\, + I2 => \idel_dec_cnt_reg_n_0_[1]\, + I3 => \idel_dec_cnt_reg_n_0_[0]\, + I4 => \idel_dec_cnt_reg_n_0_[2]\, + O => \idel_dec_cnt[4]_i_4_n_0\ + ); +\idel_dec_cnt[4]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \idel_dec_cnt_reg_n_0_[2]\, + I1 => \idel_dec_cnt_reg_n_0_[0]\, + I2 => \idel_dec_cnt_reg_n_0_[1]\, + I3 => \idel_dec_cnt_reg_n_0_[3]\, + O => \idel_dec_cnt[4]_i_5_n_0\ + ); +\idel_dec_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idel_dec_cnt[4]_i_1_n_0\, + D => idel_dec_cnt(0), + Q => \idel_dec_cnt_reg_n_0_[0]\, + R => \done_cnt_reg[1]_0\ + ); +\idel_dec_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idel_dec_cnt[4]_i_1_n_0\, + D => idel_dec_cnt(1), + Q => \idel_dec_cnt_reg_n_0_[1]\, + R => \done_cnt_reg[1]_0\ + ); +\idel_dec_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idel_dec_cnt[4]_i_1_n_0\, + D => idel_dec_cnt(2), + Q => \idel_dec_cnt_reg_n_0_[2]\, + R => \done_cnt_reg[1]_0\ + ); +\idel_dec_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idel_dec_cnt[4]_i_1_n_0\, + D => idel_dec_cnt(3), + Q => \idel_dec_cnt_reg_n_0_[3]\, + R => \done_cnt_reg[1]_0\ + ); +\idel_dec_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idel_dec_cnt[4]_i_1_n_0\, + D => idel_dec_cnt(4), + Q => \idel_dec_cnt_reg_n_0_[4]\, + R => \done_cnt_reg[1]_0\ + ); +idel_pat_detect_valid_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"CCCE" + ) + port map ( + I0 => idel_pat_detect_valid_r_reg_n_0, + I1 => p_0_in250_in, + I2 => cal1_dq_idel_inc, + I3 => store_sr_req_pulsed_r, + O => idel_pat_detect_valid_r_i_1_n_0 + ); +idel_pat_detect_valid_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idel_pat_detect_valid_r_i_1_n_0, + Q => idel_pat_detect_valid_r_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +\idelay_tap_cnt_r[0][0][4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF1111F111" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg[0][0][0]_0\, + I1 => Q(0), + I2 => \idelay_tap_cnt_r[0][0][4]_i_3_n_0\, + I3 => \^idelay_ce_int\, + I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I5 => \done_cnt_reg[2]_0\, + O => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\ + ); +\idelay_tap_cnt_r[0][0][4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \rnk_cnt_r_reg_n_0_[0]\, + I1 => \rnk_cnt_r_reg_n_0_[1]\, + O => \idelay_tap_cnt_r[0][0][4]_i_3_n_0\ + ); +\idelay_tap_cnt_r[0][1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \done_cnt_reg[2]_0\, + I1 => \^idelay_ce_int\, + I2 => idelay_tap_cnt_slice_r(0), + O => \idelay_tap_cnt_r[0][1][0]_i_1_n_0\ + ); +\idelay_tap_cnt_r[0][1][1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"04404004" + ) + port map ( + I0 => \done_cnt_reg[2]_0\, + I1 => \^idelay_ce_int\, + I2 => idelay_tap_cnt_slice_r(0), + I3 => idelay_tap_cnt_slice_r(1), + I4 => \^idelay_inc_int\, + O => \idelay_tap_cnt_r[0][1][1]_i_1_n_0\ + ); +\idelay_tap_cnt_r[0][1][2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0444400044400004" + ) + port map ( + I0 => \done_cnt_reg[2]_0\, + I1 => \^idelay_ce_int\, + I2 => \^idelay_inc_int\, + I3 => idelay_tap_cnt_slice_r(0), + I4 => idelay_tap_cnt_slice_r(2), + I5 => idelay_tap_cnt_slice_r(1), + O => \idelay_tap_cnt_r[0][1][2]_i_1_n_0\ + ); +\idelay_tap_cnt_r[0][1][3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"04404004" + ) + port map ( + I0 => \done_cnt_reg[2]_0\, + I1 => \^idelay_ce_int\, + I2 => idelay_tap_cnt_slice_r(2), + I3 => idelay_tap_cnt_slice_r(3), + I4 => \idelay_tap_cnt_r[0][1][4]_i_3_n_0\, + O => \idelay_tap_cnt_r[0][1][3]_i_1_n_0\ + ); +\idelay_tap_cnt_r[0][1][4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1444444100000000" + ) + port map ( + I0 => \done_cnt_reg[2]_0\, + I1 => idelay_tap_cnt_slice_r(4), + I2 => idelay_tap_cnt_slice_r(3), + I3 => idelay_tap_cnt_slice_r(2), + I4 => \idelay_tap_cnt_r[0][1][4]_i_3_n_0\, + I5 => \^idelay_ce_int\, + O => \idelay_tap_cnt_r[0][1][4]_i_2_n_0\ + ); +\idelay_tap_cnt_r[0][1][4]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"80FE" + ) + port map ( + I0 => idelay_tap_cnt_slice_r(1), + I1 => \^idelay_inc_int\, + I2 => idelay_tap_cnt_slice_r(0), + I3 => idelay_tap_cnt_slice_r(2), + O => \idelay_tap_cnt_r[0][1][4]_i_3_n_0\ + ); +\idelay_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\, + D => \idelay_tap_cnt_r[0][1][0]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\, + D => \idelay_tap_cnt_r[0][1][1]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\, + D => \idelay_tap_cnt_r[0][1][2]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\, + D => \idelay_tap_cnt_r[0][1][3]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r[0][0][4]_i_1_n_0\, + D => \idelay_tap_cnt_r[0][1][4]_i_2_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0), + D => \idelay_tap_cnt_r[0][1][0]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0), + D => \idelay_tap_cnt_r[0][1][1]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0), + D => \idelay_tap_cnt_r[0][1][2]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0), + D => \idelay_tap_cnt_r[0][1][3]_i_1_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\, + R => '0' + ); +\idelay_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \idelay_tap_cnt_r_reg[0][1][4]_0\(0), + D => \idelay_tap_cnt_r[0][1][4]_i_2_n_0\, + Q => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\, + R => '0' + ); +\idelay_tap_cnt_slice_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][0]\, + I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][0]\, + O => idelay_tap_cnt_r(0) + ); +\idelay_tap_cnt_slice_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][1]\, + I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][1]\, + O => idelay_tap_cnt_r(1) + ); +\idelay_tap_cnt_slice_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\, + I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\, + O => idelay_tap_cnt_r(2) + ); +\idelay_tap_cnt_slice_r[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][3]\, + I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][3]\, + O => idelay_tap_cnt_r(3) + ); +\idelay_tap_cnt_slice_r[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\, + I1 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I2 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\, + O => idelay_tap_cnt_r(4) + ); +\idelay_tap_cnt_slice_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_tap_cnt_r(0), + Q => idelay_tap_cnt_slice_r(0), + R => \done_cnt_reg[1]_0\ + ); +\idelay_tap_cnt_slice_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_tap_cnt_r(1), + Q => idelay_tap_cnt_slice_r(1), + R => \done_cnt_reg[1]_0\ + ); +\idelay_tap_cnt_slice_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_tap_cnt_r(2), + Q => idelay_tap_cnt_slice_r(2), + R => \done_cnt_reg[1]_0\ + ); +\idelay_tap_cnt_slice_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_tap_cnt_r(3), + Q => idelay_tap_cnt_slice_r(3), + R => \done_cnt_reg[1]_0\ + ); +\idelay_tap_cnt_slice_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_tap_cnt_r(4), + Q => idelay_tap_cnt_slice_r(4), + R => \done_cnt_reg[1]_0\ + ); +idelay_tap_limit_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000AAEA" + ) + port map ( + I0 => idelay_tap_limit_r_reg_n_0, + I1 => idelay_tap_cnt_r(0), + I2 => idelay_tap_cnt_r(3), + I3 => idelay_tap_limit_r_i_2_n_0, + I4 => \^new_cnt_cpt_r_reg_0\, + I5 => \done_cnt_reg[2]_0\, + O => idelay_tap_limit_r_i_1_n_0 + ); +idelay_tap_limit_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"3FFF5F5F3FFFFFFF" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\, + I1 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\, + I2 => idelay_tap_cnt_r(1), + I3 => \idelay_tap_cnt_r_reg_n_0_[0][1][2]\, + I4 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I5 => \idelay_tap_cnt_r_reg_n_0_[0][0][2]\, + O => idelay_tap_limit_r_i_2_n_0 + ); +idelay_tap_limit_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_tap_limit_r_i_1_n_0, + Q => idelay_tap_limit_r_reg_n_0, + R => '0' + ); +\init_state_r[1]_i_31\: unisim.vcomponents.LUT4 + generic map( + INIT => X"C4FF" + ) + port map ( + I0 => \^rdlvl_last_byte_done\, + I1 => pi_dqs_found_done, + I2 => \^d\(3), + I3 => pi_calib_done, + O => rdlvl_last_byte_done_int_reg_1 + ); +\init_state_r[3]_i_23\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4404" + ) + port map ( + I0 => \^d\(3), + I1 => pi_dqs_found_done, + I2 => \init_state_r[4]_i_25\, + I3 => \^rdlvl_last_byte_done\, + O => rdlvl_stg1_done_int_reg_0 + ); +\init_state_r[4]_i_42\: unisim.vcomponents.LUT3 + generic map( + INIT => X"4F" + ) + port map ( + I0 => \^rdlvl_last_byte_done\, + I1 => \init_state_r[4]_i_25\, + I2 => pi_dqs_found_done, + O => rdlvl_last_byte_done_int_reg_0 + ); +\mpr_4to1.idel_mpr_pat_detect_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000020" + ) + port map ( + I0 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\, + I1 => p_1_in2_in, + I2 => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\, + I3 => inhibit_edge_detect_r, + I4 => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\, + O => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\ + ); +\mpr_4to1.idel_mpr_pat_detect_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00100000" + ) + port map ( + I0 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\, + I1 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\, + I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\, + I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\, + I4 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\, + I5 => idel_mpr_pat_detect_r, + O => \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0\ + ); +\mpr_4to1.idel_mpr_pat_detect_r_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0008" + ) + port map ( + I0 => idel_pat_detect_valid_r_reg_n_0, + I1 => p_0_in250_in, + I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\, + I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\, + O => \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0\ + ); +\mpr_4to1.idel_mpr_pat_detect_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0\, + Q => idel_mpr_pat_detect_r, + R => '0' + ); +\mpr_4to1.inhibit_edge_detect_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F700FFFF" + ) + port map ( + I0 => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\, + I1 => p_0_in250_in, + I2 => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\, + I3 => inhibit_edge_detect_r, + I4 => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\, + O => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\ + ); +\mpr_4to1.inhibit_edge_detect_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEFEA" + ) + port map ( + I0 => idelay_tap_cnt_r(1), + I1 => \idelay_tap_cnt_r_reg_n_0_[0][1][4]\, + I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I3 => \idelay_tap_cnt_r_reg_n_0_[0][0][4]\, + I4 => idelay_tap_cnt_r(2), + I5 => idelay_tap_cnt_r(3), + O => \mpr_4to1.inhibit_edge_detect_r_i_2_n_0\ + ); +\mpr_4to1.inhibit_edge_detect_r_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFBFF" + ) + port map ( + I0 => mpr_rd_rise0_prev_r, + I1 => mpr_rd_fall2_prev_r, + I2 => mpr_rd_rise3_prev_r, + I3 => mpr_rd_fall3_prev_r, + I4 => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\, + O => \mpr_4to1.inhibit_edge_detect_r_i_3_n_0\ + ); +\mpr_4to1.inhibit_edge_detect_r_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555555555554" + ) + port map ( + I0 => \done_cnt_reg[2]_0\, + I1 => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\, + I2 => mpr_rd_fall2_prev_r, + I3 => mpr_rd_fall1_prev_r, + I4 => mpr_rd_fall3_prev_r, + I5 => mpr_rd_fall0_prev_r, + O => \mpr_4to1.inhibit_edge_detect_r_i_4_n_0\ + ); +\mpr_4to1.inhibit_edge_detect_r_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => mpr_rd_fall1_prev_r, + I1 => mpr_rd_rise1_prev_r, + I2 => mpr_rd_fall0_prev_r, + I3 => mpr_rd_rise2_prev_r, + O => \mpr_4to1.inhibit_edge_detect_r_i_5_n_0\ + ); +\mpr_4to1.inhibit_edge_detect_r_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => mpr_rd_rise1_prev_r, + I1 => mpr_rd_rise0_prev_r, + I2 => mpr_rd_rise2_prev_r, + I3 => mpr_rd_rise3_prev_r, + O => \mpr_4to1.inhibit_edge_detect_r_i_6_n_0\ + ); +\mpr_4to1.inhibit_edge_detect_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mpr_4to1.inhibit_edge_detect_r_i_1_n_0\, + Q => inhibit_edge_detect_r, + R => '0' + ); +\mpr_4to1.stable_idel_cnt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"06" + ) + port map ( + I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\, + I1 => stable_idel_cnt, + I2 => stable_idel_cnt0, + O => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\ + ); +\mpr_4to1.stable_idel_cnt[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"006A" + ) + port map ( + I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\, + I1 => stable_idel_cnt, + I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\, + I3 => stable_idel_cnt0, + O => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\ + ); +\mpr_4to1.stable_idel_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00006AAA" + ) + port map ( + I0 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\, + I1 => stable_idel_cnt, + I2 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\, + I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\, + I4 => stable_idel_cnt0, + O => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\ + ); +\mpr_4to1.stable_idel_cnt[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000040" + ) + port map ( + I0 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\, + I1 => idel_pat_detect_valid_r_reg_n_0, + I2 => p_0_in250_in, + I3 => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\, + I4 => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\, + I5 => \FSM_onehot_cal1_state_r[16]_i_4_n_0\, + O => stable_idel_cnt + ); +\mpr_4to1.stable_idel_cnt[2]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + I2 => \done_cnt_reg[2]_0\, + O => stable_idel_cnt0 + ); +\mpr_4to1.stable_idel_cnt[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBEFFFFBE" + ) + port map ( + I0 => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\, + I1 => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\, + I2 => mpr_rd_fall1_prev_r, + I3 => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\, + I4 => mpr_rd_fall2_prev_r, + I5 => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\, + O => \mpr_4to1.stable_idel_cnt[2]_i_4_n_0\ + ); +\mpr_4to1.stable_idel_cnt[2]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\, + I1 => mpr_rd_rise0_prev_r, + I2 => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\, + I3 => mpr_rd_fall0_prev_r, + O => \mpr_4to1.stable_idel_cnt[2]_i_5_n_0\ + ); +\mpr_4to1.stable_idel_cnt[2]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF6FF6" + ) + port map ( + I0 => mpr_rd_rise3_prev_r, + I1 => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\, + I2 => mpr_rd_rise2_prev_r, + I3 => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\, + I4 => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\, + O => \mpr_4to1.stable_idel_cnt[2]_i_6_n_0\ + ); +\mpr_4to1.stable_idel_cnt[2]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\, + I1 => mpr_rd_fall3_prev_r, + I2 => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\, + I3 => mpr_rd_rise1_prev_r, + O => \mpr_4to1.stable_idel_cnt[2]_i_7_n_0\ + ); +\mpr_4to1.stable_idel_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mpr_4to1.stable_idel_cnt[0]_i_1_n_0\, + Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[0]\, + R => '0' + ); +\mpr_4to1.stable_idel_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mpr_4to1.stable_idel_cnt[1]_i_1_n_0\, + Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[1]\, + R => '0' + ); +\mpr_4to1.stable_idel_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mpr_4to1.stable_idel_cnt[2]_i_1_n_0\, + Q => \mpr_4to1.stable_idel_cnt_reg_n_0_[2]\, + R => '0' + ); +mpr_dec_cpt_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"DC" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[16]\, + I1 => mpr_dec_cpt_r, + I2 => mpr_dec_cpt_r_reg_n_0, + O => mpr_dec_cpt_r_i_1_n_0 + ); +mpr_dec_cpt_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mpr_dec_cpt_r_i_1_n_0, + Q => mpr_dec_cpt_r_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +mpr_rd_fall0_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\, + Q => mpr_rd_fall0_prev_r, + R => '0' + ); +mpr_rd_fall1_prev_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => p_1_in2_in, + I1 => idel_pat_detect_valid_r_reg_n_0, + I2 => p_0_in250_in, + O => mpr_rd_rise0_prev_r0 + ); +mpr_rd_fall1_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\, + Q => mpr_rd_fall1_prev_r, + R => '0' + ); +mpr_rd_fall2_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\, + Q => mpr_rd_fall2_prev_r, + R => '0' + ); +mpr_rd_fall3_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\, + Q => mpr_rd_fall3_prev_r, + R => '0' + ); +mpr_rd_rise0_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\, + Q => mpr_rd_rise0_prev_r, + R => '0' + ); +mpr_rd_rise1_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\, + Q => mpr_rd_rise1_prev_r, + R => '0' + ); +mpr_rd_rise2_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0]\, + Q => mpr_rd_rise2_prev_r, + R => '0' + ); +mpr_rd_rise3_prev_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => mpr_rd_rise0_prev_r0, + D => \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\, + Q => mpr_rd_rise3_prev_r, + R => '0' + ); +mpr_rdlvl_start_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mpr_rdlvl_start_r_reg_0, + Q => mpr_rdlvl_start_r, + R => '0' + ); +new_cnt_cpt_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAEAEEAAAA" + ) + port map ( + I0 => new_cnt_cpt_r_i_2_n_0, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + I2 => mpr_rdlvl_start_r, + I3 => mpr_rdlvl_start_r_reg_0, + I4 => rdlvl_stg1_start_r_reg_0, + I5 => rdlvl_stg1_start_r, + O => new_cnt_cpt_r + ); +new_cnt_cpt_r_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"EF000000" + ) + port map ( + I0 => \rnk_cnt_r_reg_n_0_[0]\, + I1 => \rnk_cnt_r_reg_n_0_[1]\, + I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I3 => cal1_prech_req_r, + I4 => prech_done, + O => new_cnt_cpt_r_i_2_n_0 + ); +new_cnt_cpt_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => new_cnt_cpt_r, + Q => \^new_cnt_cpt_r_reg_0\, + R => \done_cnt_reg[1]_0\ + ); +\phaser_in_gen.phaser_in_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => pi_counter_load_en, + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => \calib_sel_reg[1]_1\ + ); +\phaser_in_gen.phaser_in_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => pi_counter_load_val(1), + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => COUNTERLOADVAL(1) + ); +\phaser_in_gen.phaser_in_i_10__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => pi_counter_load_val(1), + I1 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I2 => \pi_dqs_found_lanes_r1_reg[3]\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => \pi_stg2_reg_l_reg[5]_0\(1) + ); +\phaser_in_gen.phaser_in_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => pi_counter_load_val(0), + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => COUNTERLOADVAL(0) + ); +\phaser_in_gen.phaser_in_i_11__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => pi_counter_load_val(0), + I1 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I2 => \pi_dqs_found_lanes_r1_reg[3]\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => \pi_stg2_reg_l_reg[5]_0\(0) + ); +\phaser_in_gen.phaser_in_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => pi_counter_load_en, + I1 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I2 => \pi_dqs_found_lanes_r1_reg[3]\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => pi_stg2_load_reg_0 + ); +\phaser_in_gen.phaser_in_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FCFC00A8" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => rdlvl_pi_stg2_f_en, + I2 => tempmon_pi_f_en_r, + I3 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I4 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I5 => calib_zero_inputs, + O => \calib_sel_reg[1]\ + ); +\phaser_in_gen.phaser_in_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEEEE000" + ) + port map ( + I0 => rdlvl_pi_stg2_f_en, + I1 => tempmon_pi_f_en_r, + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]\, + I4 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I5 => calib_zero_inputs, + O => pi_en_stg2_f_reg_0 + ); +\phaser_in_gen.phaser_in_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FCFC00A8" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => rdlvl_pi_stg2_f_incdec, + I2 => tempmon_pi_f_inc_r, + I3 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I4 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I5 => calib_zero_inputs, + O => \calib_sel_reg[1]_0\ + ); +\phaser_in_gen.phaser_in_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEEEE000" + ) + port map ( + I0 => rdlvl_pi_stg2_f_incdec, + I1 => tempmon_pi_f_inc_r, + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]\, + I4 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I5 => calib_zero_inputs, + O => pi_stg2_f_incdec_reg_0 + ); +\phaser_in_gen.phaser_in_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => pi_counter_load_val(5), + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => COUNTERLOADVAL(5) + ); +\phaser_in_gen.phaser_in_i_6__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => pi_counter_load_val(5), + I1 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I2 => \pi_dqs_found_lanes_r1_reg[3]\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => \pi_stg2_reg_l_reg[5]_0\(5) + ); +\phaser_in_gen.phaser_in_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => pi_counter_load_val(4), + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => COUNTERLOADVAL(4) + ); +\phaser_in_gen.phaser_in_i_7__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => pi_counter_load_val(4), + I1 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I2 => \pi_dqs_found_lanes_r1_reg[3]\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => \pi_stg2_reg_l_reg[5]_0\(4) + ); +\phaser_in_gen.phaser_in_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => pi_counter_load_val(3), + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => COUNTERLOADVAL(3) + ); +\phaser_in_gen.phaser_in_i_8__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => pi_counter_load_val(3), + I1 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I2 => \pi_dqs_found_lanes_r1_reg[3]\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => \pi_stg2_reg_l_reg[5]_0\(3) + ); +\phaser_in_gen.phaser_in_i_9\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \pi_dqs_found_lanes_r1_reg[3]\, + I1 => pi_counter_load_val(2), + I2 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => COUNTERLOADVAL(2) + ); +\phaser_in_gen.phaser_in_i_9__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => pi_counter_load_val(2), + I1 => \pi_dqs_found_lanes_r1_reg[3]_0\, + I2 => \pi_dqs_found_lanes_r1_reg[3]\, + I3 => \pi_dqs_found_lanes_r1_reg[3]_1\, + I4 => calib_zero_inputs, + O => \pi_stg2_reg_l_reg[5]_0\(2) + ); +pi_cnt_dec_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000800" + ) + port map ( + I0 => \pi_rdval_cnt[5]_i_3_n_0\, + I1 => wait_cnt_r_reg(0), + I2 => wait_cnt_r_reg(1), + I3 => dqs_po_dec_done_r2, + I4 => \done_cnt_reg[2]_0\, + I5 => pi_cnt_dec_i_2_n_0, + O => pi_cnt_dec_i_1_n_0 + ); +pi_cnt_dec_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => wait_cnt_r_reg(2), + I1 => wait_cnt_r_reg(3), + O => pi_cnt_dec_i_2_n_0 + ); +pi_cnt_dec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_cnt_dec_i_1_n_0, + Q => \^pi_cnt_dec_reg_0\, + R => '0' + ); +pi_en_stg2_f_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_en_stg2_f_timing, + Q => rdlvl_pi_stg2_f_en, + R => '0' + ); +pi_en_stg2_f_timing_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => cal1_dlyce_cpt_r_reg_n_0, + I1 => \^pi_cnt_dec_reg_0\, + O => pi_en_stg2_f_timing_i_1_n_0 + ); +pi_en_stg2_f_timing_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_en_stg2_f_timing_i_1_n_0, + Q => pi_en_stg2_f_timing, + R => \done_cnt_reg[1]_0\ + ); +pi_fine_dly_dec_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => fine_dly_dec_done_r2, + Q => \^pi_fine_dly_dec_done_reg_0\, + R => '0' + ); +\pi_rdval_cnt[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0808FB08" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(0), + I1 => dqs_po_dec_done_r1, + I2 => dqs_po_dec_done_r2, + I3 => \pi_rdval_cnt[5]_i_3_n_0\, + I4 => pi_rdval_cnt(0), + O => \pi_rdval_cnt[0]_i_1_n_0\ + ); +\pi_rdval_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FB0808080808FB08" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(1), + I1 => dqs_po_dec_done_r1, + I2 => dqs_po_dec_done_r2, + I3 => \pi_rdval_cnt[5]_i_3_n_0\, + I4 => pi_rdval_cnt(1), + I5 => pi_rdval_cnt(0), + O => \pi_rdval_cnt[1]_i_1_n_0\ + ); +\pi_rdval_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8B8B888888888B8" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(2), + I1 => \pi_rdval_cnt[3]_i_2_n_0\, + I2 => \pi_rdval_cnt[5]_i_3_n_0\, + I3 => pi_rdval_cnt(0), + I4 => pi_rdval_cnt(1), + I5 => pi_rdval_cnt(2), + O => \pi_rdval_cnt[2]_i_1_n_0\ + ); +\pi_rdval_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8B888B88888B888" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(3), + I1 => \pi_rdval_cnt[3]_i_2_n_0\, + I2 => \pi_rdval_cnt[5]_i_3_n_0\, + I3 => \pi_rdval_cnt[3]_i_3_n_0\, + I4 => pi_rdval_cnt(2), + I5 => pi_rdval_cnt(3), + O => \pi_rdval_cnt[3]_i_1_n_0\ + ); +\pi_rdval_cnt[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => dqs_po_dec_done_r1, + I1 => dqs_po_dec_done_r2, + O => \pi_rdval_cnt[3]_i_2_n_0\ + ); +\pi_rdval_cnt[3]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => pi_rdval_cnt(0), + I1 => pi_rdval_cnt(1), + O => \pi_rdval_cnt[3]_i_3_n_0\ + ); +\pi_rdval_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0808FBFBFB080808" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(4), + I1 => dqs_po_dec_done_r1, + I2 => dqs_po_dec_done_r2, + I3 => pi_rdval_cnt(5), + I4 => \pi_rdval_cnt[5]_i_4_n_0\, + I5 => pi_rdval_cnt(4), + O => \pi_rdval_cnt[4]_i_1_n_0\ + ); +\pi_rdval_cnt[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBFB" + ) + port map ( + I0 => \^pi_cnt_dec_reg_0\, + I1 => \pi_rdval_cnt[5]_i_3_n_0\, + I2 => dqs_po_dec_done_r1, + I3 => dqs_po_dec_done_r2, + O => \pi_rdval_cnt[5]_i_1_n_0\ + ); +\pi_rdval_cnt[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FB080808FB08FB08" + ) + port map ( + I0 => \pi_rdval_cnt_reg[5]_0\(5), + I1 => dqs_po_dec_done_r1, + I2 => dqs_po_dec_done_r2, + I3 => pi_rdval_cnt(5), + I4 => pi_rdval_cnt(4), + I5 => \pi_rdval_cnt[5]_i_4_n_0\, + O => \pi_rdval_cnt[5]_i_2_n_0\ + ); +\pi_rdval_cnt[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFFE" + ) + port map ( + I0 => pi_rdval_cnt(4), + I1 => pi_rdval_cnt(5), + I2 => pi_rdval_cnt(2), + I3 => pi_rdval_cnt(3), + I4 => pi_rdval_cnt(0), + I5 => pi_rdval_cnt(1), + O => \pi_rdval_cnt[5]_i_3_n_0\ + ); +\pi_rdval_cnt[5]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => pi_rdval_cnt(1), + I1 => pi_rdval_cnt(0), + I2 => pi_rdval_cnt(3), + I3 => pi_rdval_cnt(2), + O => \pi_rdval_cnt[5]_i_4_n_0\ + ); +\pi_rdval_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \pi_rdval_cnt[5]_i_1_n_0\, + D => \pi_rdval_cnt[0]_i_1_n_0\, + Q => pi_rdval_cnt(0), + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\pi_rdval_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \pi_rdval_cnt[5]_i_1_n_0\, + D => \pi_rdval_cnt[1]_i_1_n_0\, + Q => pi_rdval_cnt(1), + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\pi_rdval_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \pi_rdval_cnt[5]_i_1_n_0\, + D => \pi_rdval_cnt[2]_i_1_n_0\, + Q => pi_rdval_cnt(2), + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\pi_rdval_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \pi_rdval_cnt[5]_i_1_n_0\, + D => \pi_rdval_cnt[3]_i_1_n_0\, + Q => pi_rdval_cnt(3), + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\pi_rdval_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \pi_rdval_cnt[5]_i_1_n_0\, + D => \pi_rdval_cnt[4]_i_1_n_0\, + Q => pi_rdval_cnt(4), + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\pi_rdval_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \pi_rdval_cnt[5]_i_1_n_0\, + D => \pi_rdval_cnt[5]_i_2_n_0\, + Q => pi_rdval_cnt(5), + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +pi_stg2_f_incdec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_f_incdec_timing, + Q => rdlvl_pi_stg2_f_incdec, + R => '0' + ); +pi_stg2_f_incdec_timing_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0008" + ) + port map ( + I0 => cal1_dlyce_cpt_r_reg_n_0, + I1 => cal1_dlyinc_cpt_r_reg_n_0, + I2 => \^pi_cnt_dec_reg_0\, + I3 => \done_cnt_reg[2]_0\, + O => pi_stg2_f_incdec_timing_i_1_n_0 + ); +pi_stg2_f_incdec_timing_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_f_incdec_timing_i_1_n_0, + Q => pi_stg2_f_incdec_timing, + R => '0' + ); +pi_stg2_load_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_load_timing, + Q => pi_counter_load_en, + R => '0' + ); +pi_stg2_load_timing_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \regl_dqs_cnt_reg_n_0_[1]\, + I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\, + I2 => \regl_rank_cnt[1]_i_2_n_0\, + O => pi_stg2_load_timing_i_1_n_0 + ); +pi_stg2_load_timing_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_load_timing_i_1_n_0, + Q => pi_stg2_load_timing, + R => '0' + ); +\pi_stg2_reg_l_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_reg_l_timing(0), + Q => pi_counter_load_val(0), + R => '0' + ); +\pi_stg2_reg_l_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_reg_l_timing(1), + Q => pi_counter_load_val(1), + R => '0' + ); +\pi_stg2_reg_l_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_reg_l_timing(2), + Q => pi_counter_load_val(2), + R => '0' + ); +\pi_stg2_reg_l_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_reg_l_timing(3), + Q => pi_counter_load_val(3), + R => '0' + ); +\pi_stg2_reg_l_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_reg_l_timing(4), + Q => pi_counter_load_val(4), + R => '0' + ); +\pi_stg2_reg_l_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_stg2_reg_l_timing(5), + Q => pi_counter_load_val(5), + R => '0' + ); +\pi_stg2_reg_l_timing[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\, + O => \pi_stg2_reg_l_timing[0]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\, + O => \pi_stg2_reg_l_timing[1]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\, + O => \pi_stg2_reg_l_timing[2]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\, + O => \pi_stg2_reg_l_timing[3]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\, + O => \pi_stg2_reg_l_timing[4]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FB" + ) + port map ( + I0 => \regl_rank_cnt[1]_i_2_n_0\, + I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\, + I2 => \regl_dqs_cnt_reg_n_0_[1]\, + O => \pi_stg2_reg_l_timing[5]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing[5]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\, + I1 => \regl_dqs_cnt_reg_n_0_[0]\, + I2 => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\, + O => \pi_stg2_reg_l_timing[5]_i_2_n_0\ + ); +\pi_stg2_reg_l_timing_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_stg2_reg_l_timing[0]_i_1_n_0\, + Q => pi_stg2_reg_l_timing(0), + R => \pi_stg2_reg_l_timing[5]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_stg2_reg_l_timing[1]_i_1_n_0\, + Q => pi_stg2_reg_l_timing(1), + R => \pi_stg2_reg_l_timing[5]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_stg2_reg_l_timing[2]_i_1_n_0\, + Q => pi_stg2_reg_l_timing(2), + R => \pi_stg2_reg_l_timing[5]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_stg2_reg_l_timing[3]_i_1_n_0\, + Q => pi_stg2_reg_l_timing(3), + R => \pi_stg2_reg_l_timing[5]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_stg2_reg_l_timing[4]_i_1_n_0\, + Q => pi_stg2_reg_l_timing(4), + R => \pi_stg2_reg_l_timing[5]_i_1_n_0\ + ); +\pi_stg2_reg_l_timing_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \pi_stg2_reg_l_timing[5]_i_2_n_0\, + Q => pi_stg2_reg_l_timing(5), + R => \pi_stg2_reg_l_timing[5]_i_1_n_0\ + ); +\rd_mux_sel_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_cnt_cpt_r_reg_n_0_[0]\, + Q => \^rd_mux_sel_r_reg[0]_0\, + R => '0' + ); +\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0002" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\, + I1 => \rnk_cnt_r_reg_n_0_[0]\, + I2 => \rnk_cnt_r_reg_n_0_[1]\, + I3 => \^rd_mux_sel_r_reg[0]_0\, + O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\ + ); +\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100000000000000" + ) + port map ( + I0 => \cal1_state_r1_reg_n_0_[4]\, + I1 => \cal1_state_r1_reg_n_0_[0]\, + I2 => \cal1_state_r1_reg_n_0_[5]\, + I3 => \cal1_state_r1_reg_n_0_[2]\, + I4 => \cal1_state_r1_reg_n_0_[3]\, + I5 => \cal1_state_r1_reg_n_0_[1]\, + O => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\ + ); +\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0200" + ) + port map ( + I0 => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0\, + I1 => \rnk_cnt_r_reg_n_0_[0]\, + I2 => \rnk_cnt_r_reg_n_0_[1]\, + I3 => \^rd_mux_sel_r_reg[0]_0\, + O => rdlvl_dqs_tap_cnt_r + ); +\rdlvl_dqs_tap_cnt_r_reg[0][0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[0]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\rdlvl_dqs_tap_cnt_r_reg[0][0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[1]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\rdlvl_dqs_tap_cnt_r_reg[0][0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[2]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\rdlvl_dqs_tap_cnt_r_reg[0][0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[3]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\rdlvl_dqs_tap_cnt_r_reg[0][0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[4]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\rdlvl_dqs_tap_cnt_r_reg[0][0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0\, + D => \tap_cnt_cpt_r_reg_n_0_[5]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5]\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +\rdlvl_dqs_tap_cnt_r_reg[0][1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rdlvl_dqs_tap_cnt_r, + D => \tap_cnt_cpt_r_reg_n_0_[0]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0]\, + R => \done_cnt_reg[1]_0\ + ); +\rdlvl_dqs_tap_cnt_r_reg[0][1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rdlvl_dqs_tap_cnt_r, + D => \tap_cnt_cpt_r_reg_n_0_[1]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1]\, + R => \done_cnt_reg[1]_0\ + ); +\rdlvl_dqs_tap_cnt_r_reg[0][1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rdlvl_dqs_tap_cnt_r, + D => \tap_cnt_cpt_r_reg_n_0_[2]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2]\, + R => \done_cnt_reg[1]_0\ + ); +\rdlvl_dqs_tap_cnt_r_reg[0][1][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rdlvl_dqs_tap_cnt_r, + D => \tap_cnt_cpt_r_reg_n_0_[3]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3]\, + R => \done_cnt_reg[1]_0\ + ); +\rdlvl_dqs_tap_cnt_r_reg[0][1][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rdlvl_dqs_tap_cnt_r, + D => \tap_cnt_cpt_r_reg_n_0_[4]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4]\, + R => \done_cnt_reg[1]_0\ + ); +\rdlvl_dqs_tap_cnt_r_reg[0][1][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rdlvl_dqs_tap_cnt_r, + D => \tap_cnt_cpt_r_reg_n_0_[5]\, + Q => \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5]\, + R => \done_cnt_reg[1]_0\ + ); +rdlvl_last_byte_done_int_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF0101FFFE0000" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r[5]_i_1_n_0\, + I1 => p_3_in4_in, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + I3 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I4 => cal1_prech_req_r, + I5 => \^rdlvl_last_byte_done\, + O => rdlvl_last_byte_done_int_i_1_n_0 + ); +rdlvl_last_byte_done_int_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_last_byte_done_int_i_1_n_0, + Q => \^rdlvl_last_byte_done\, + R => \done_cnt_reg[1]_0\ + ); +rdlvl_pi_incdec_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAEFFAAAAA200" + ) + port map ( + I0 => rdlvl_pi_incdec_i_2_n_0, + I1 => cal1_wait_r, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I3 => rdlvl_pi_incdec_i_3_n_0, + I4 => rdlvl_pi_incdec_i_4_n_0, + I5 => \^rdlvl_pi_incdec\, + O => rdlvl_pi_incdec_i_1_n_0 + ); +rdlvl_pi_incdec_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FEFEFEFEFEFEFEEE" + ) + port map ( + I0 => mpr_dec_cpt_r, + I1 => rdlvl_pi_incdec_i_5_n_0, + I2 => cal1_wait_r, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + I5 => p_3_in4_in, + O => rdlvl_pi_incdec_i_2_n_0 + ); +rdlvl_pi_incdec_i_3: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[8]\, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[31]\, + I2 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + O => rdlvl_pi_incdec_i_3_n_0 + ); +rdlvl_pi_incdec_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + I1 => p_3_in4_in, + I2 => p_37_in, + I3 => p_0_in250_in, + I4 => p_14_in, + O => rdlvl_pi_incdec_i_4_n_0 + ); +rdlvl_pi_incdec_i_5: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEFEEEE" + ) + port map ( + I0 => p_14_in, + I1 => \FSM_onehot_cal1_state_r_reg_n_0_[29]\, + I2 => mpr_rdlvl_start_r_reg_0, + I3 => mpr_rdlvl_start_r, + I4 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + O => rdlvl_pi_incdec_i_5_n_0 + ); +rdlvl_pi_incdec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_pi_incdec_i_1_n_0, + Q => \^rdlvl_pi_incdec\, + R => \FSM_onehot_cal1_state_r_reg[0]_0\(0) + ); +rdlvl_prech_req_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cal1_prech_req_r__0\, + Q => rdlvl_prech_req, + R => \done_cnt_reg[1]_0\ + ); +rdlvl_rank_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAFAAAAAAA8" + ) + port map ( + I0 => rdlvl_rank_done_r, + I1 => prech_done, + I2 => p_3_in4_in, + I3 => \FSM_onehot_cal1_state_r_reg_n_0_[7]\, + I4 => p_0_in118_in, + I5 => \^rdlvl_stg1_rank_done\, + O => rdlvl_rank_done_r_i_1_n_0 + ); +rdlvl_rank_done_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I1 => cal1_prech_req_r, + O => rdlvl_rank_done_r + ); +rdlvl_rank_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_rank_done_r_i_1_n_0, + Q => \^rdlvl_stg1_rank_done\, + R => \done_cnt_reg[1]_0\ + ); +rdlvl_stg1_done_int_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => rdlvl_stg1_done_int, + I1 => \^d\(3), + O => rdlvl_stg1_done_int_i_1_n_0 + ); +rdlvl_stg1_done_int_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_stg1_done_int_i_1_n_0, + Q => \^d\(3), + R => \done_cnt_reg[1]_0\ + ); +rdlvl_stg1_start_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rdlvl_stg1_start_r_reg_0, + Q => rdlvl_stg1_start_r, + R => '0' + ); +\regl_dqs_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000006666666E" + ) + port map ( + I0 => \regl_dqs_cnt_reg_n_0_[0]\, + I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\, + I2 => \regl_dqs_cnt_reg_n_0_[1]\, + I3 => regl_rank_cnt(0), + I4 => regl_rank_cnt(1), + I5 => \regl_rank_cnt[1]_i_2_n_0\, + O => \regl_dqs_cnt[0]_i_1_n_0\ + ); +\regl_dqs_cnt[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1500" + ) + port map ( + I0 => \regl_rank_cnt[1]_i_2_n_0\, + I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\, + I2 => \regl_dqs_cnt_reg_n_0_[0]\, + I3 => \regl_dqs_cnt_reg_n_0_[1]\, + O => \regl_dqs_cnt[1]_i_1_n_0\ + ); +\regl_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \regl_dqs_cnt_reg_n_0_[0]\, + Q => regl_dqs_cnt_r(0), + R => '0' + ); +\regl_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \regl_dqs_cnt_reg_n_0_[1]\, + Q => regl_dqs_cnt_r(1), + R => '0' + ); +\regl_dqs_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \regl_dqs_cnt[0]_i_1_n_0\, + Q => \regl_dqs_cnt_reg_n_0_[0]\, + R => '0' + ); +\regl_dqs_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \regl_dqs_cnt[1]_i_1_n_0\, + Q => \regl_dqs_cnt_reg_n_0_[1]\, + R => '0' + ); +\regl_rank_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AA6AAA2A" + ) + port map ( + I0 => regl_rank_cnt(0), + I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\, + I2 => \regl_dqs_cnt_reg_n_0_[0]\, + I3 => \regl_dqs_cnt_reg_n_0_[1]\, + I4 => regl_rank_cnt(1), + I5 => \regl_rank_cnt[1]_i_2_n_0\, + O => \regl_rank_cnt[0]_i_1_n_0\ + ); +\regl_rank_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AA6AAAAA" + ) + port map ( + I0 => regl_rank_cnt(1), + I1 => \FSM_onehot_cal1_state_r[5]_i_2_n_0\, + I2 => \regl_dqs_cnt_reg_n_0_[0]\, + I3 => \regl_dqs_cnt_reg_n_0_[1]\, + I4 => regl_rank_cnt(0), + I5 => \regl_rank_cnt[1]_i_2_n_0\, + O => \regl_rank_cnt[1]_i_1_n_0\ + ); +\regl_rank_cnt[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAAB" + ) + port map ( + I0 => \done_cnt_reg[2]_0\, + I1 => done_cnt(3), + I2 => done_cnt(1), + I3 => done_cnt(0), + I4 => done_cnt(2), + O => \regl_rank_cnt[1]_i_2_n_0\ + ); +\regl_rank_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \regl_rank_cnt[0]_i_1_n_0\, + Q => regl_rank_cnt(0), + R => '0' + ); +\regl_rank_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \regl_rank_cnt[1]_i_1_n_0\, + Q => regl_rank_cnt(1), + R => '0' + ); +reset_if_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000AE" + ) + port map ( + I0 => reset_if, + I1 => \^d\(3), + I2 => reset_if_reg_0, + I3 => reset_if_r9, + I4 => reset_if_reg_1, + O => reset_if_reg + ); +\right_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[0]\, + O => right_edge_taps_r(0) + ); +\right_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[1]\, + O => right_edge_taps_r(1) + ); +\right_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[2]\, + O => right_edge_taps_r(2) + ); +\right_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[3]\, + O => right_edge_taps_r(3) + ); +\right_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[4]\, + O => right_edge_taps_r(4) + ); +\right_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BAAA" + ) + port map ( + I0 => cal1_prech_req_r, + I1 => found_first_edge_r_reg_n_0, + I2 => found_stable_eye_last_r, + I3 => \right_edge_taps_r[5]_i_3_n_0\, + O => \right_edge_taps_r[5]_i_1_n_0\ + ); +\right_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[5]\, + O => right_edge_taps_r(5) + ); +\right_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => found_edge_r_reg_n_0, + I1 => store_sr_req_pulsed_r, + I2 => detect_edge_done_r, + I3 => tap_limit_cpt_r, + O => \right_edge_taps_r[5]_i_3_n_0\ + ); +\right_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \right_edge_taps_r[5]_i_1_n_0\, + D => right_edge_taps_r(0), + Q => \right_edge_taps_r_reg_n_0_[0]\, + R => \done_cnt_reg[1]_0\ + ); +\right_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \right_edge_taps_r[5]_i_1_n_0\, + D => right_edge_taps_r(1), + Q => \right_edge_taps_r_reg_n_0_[1]\, + R => \done_cnt_reg[1]_0\ + ); +\right_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \right_edge_taps_r[5]_i_1_n_0\, + D => right_edge_taps_r(2), + Q => \right_edge_taps_r_reg_n_0_[2]\, + R => \done_cnt_reg[1]_0\ + ); +\right_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \right_edge_taps_r[5]_i_1_n_0\, + D => right_edge_taps_r(3), + Q => \right_edge_taps_r_reg_n_0_[3]\, + R => \done_cnt_reg[1]_0\ + ); +\right_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \right_edge_taps_r[5]_i_1_n_0\, + D => right_edge_taps_r(4), + Q => \right_edge_taps_r_reg_n_0_[4]\, + R => \done_cnt_reg[1]_0\ + ); +\right_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \right_edge_taps_r[5]_i_1_n_0\, + D => right_edge_taps_r(5), + Q => \right_edge_taps_r_reg_n_0_[5]\, + R => \done_cnt_reg[1]_0\ + ); +\rnk_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1515C88855558888" + ) + port map ( + I0 => p_0_in118_in, + I1 => cal1_prech_req_r, + I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I3 => \rnk_cnt_r_reg_n_0_[1]\, + I4 => \rnk_cnt_r_reg_n_0_[0]\, + I5 => prech_done, + O => \rnk_cnt_r[0]_i_1__0_n_0\ + ); +\rnk_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"15C8DD005588DD00" + ) + port map ( + I0 => p_0_in118_in, + I1 => cal1_prech_req_r, + I2 => \cal1_cnt_cpt_r_reg_n_0_[0]\, + I3 => \rnk_cnt_r_reg_n_0_[1]\, + I4 => \rnk_cnt_r_reg_n_0_[0]\, + I5 => prech_done, + O => \rnk_cnt_r[1]_i_1__0_n_0\ + ); +\rnk_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rnk_cnt_r[0]_i_1__0_n_0\, + Q => \rnk_cnt_r_reg_n_0_[0]\, + R => \done_cnt_reg[1]_0\ + ); +\rnk_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rnk_cnt_r[1]_i_1__0_n_0\, + Q => \rnk_cnt_r_reg_n_0_[1]\, + R => \done_cnt_reg[1]_0\ + ); +samp_cnt_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAE0000" + ) + port map ( + I0 => samp_cnt_done_r_reg_n_0, + I1 => samp_cnt_done_r_i_2_n_0, + I2 => samp_cnt_done_r_i_3_n_0, + I3 => samp_cnt_done_r_i_4_n_0, + I4 => \^samp_edge_cnt0_en_r\, + I5 => \done_cnt_reg[2]_0\, + O => samp_cnt_done_r_i_1_n_0 + ); +samp_cnt_done_r_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => samp_edge_cnt1_r_reg(11), + I1 => samp_edge_cnt1_r_reg(2), + I2 => samp_edge_cnt1_r_reg(4), + I3 => samp_edge_cnt1_r_reg(1), + O => samp_cnt_done_r_i_2_n_0 + ); +samp_cnt_done_r_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => samp_edge_cnt1_r_reg(7), + I1 => samp_edge_cnt1_r_reg(5), + I2 => samp_edge_cnt1_r_reg(9), + I3 => samp_edge_cnt1_r_reg(6), + O => samp_cnt_done_r_i_3_n_0 + ); +samp_cnt_done_r_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => samp_edge_cnt1_r_reg(0), + I1 => samp_edge_cnt1_r_reg(8), + I2 => samp_edge_cnt1_r_reg(10), + I3 => samp_edge_cnt1_r_reg(3), + O => samp_cnt_done_r_i_4_n_0 + ); +samp_cnt_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => samp_cnt_done_r_i_1_n_0, + Q => samp_cnt_done_r_reg_n_0, + R => '0' + ); +samp_edge_cnt0_en_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => p_37_in, + I1 => store_sr_req_pulsed_r, + O => pb_detect_edge + ); +samp_edge_cnt0_en_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pb_detect_edge, + Q => \^samp_edge_cnt0_en_r\, + R => '0' + ); +\samp_edge_cnt0_r[0]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => samp_edge_cnt0_r_reg(0), + O => \samp_edge_cnt0_r[0]_i_3_n_0\ + ); +\samp_edge_cnt0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[0]_i_2_n_7\, + Q => samp_edge_cnt0_r_reg(0), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[0]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_0\, + CO(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_1\, + CO(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_2\, + CO(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \samp_edge_cnt0_r_reg[0]_i_2_n_4\, + O(2) => \samp_edge_cnt0_r_reg[0]_i_2_n_5\, + O(1) => \samp_edge_cnt0_r_reg[0]_i_2_n_6\, + O(0) => \samp_edge_cnt0_r_reg[0]_i_2_n_7\, + S(3 downto 1) => samp_edge_cnt0_r_reg(3 downto 1), + S(0) => \samp_edge_cnt0_r[0]_i_3_n_0\ + ); +\samp_edge_cnt0_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[8]_i_1_n_5\, + Q => samp_edge_cnt0_r_reg(10), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[8]_i_1_n_4\, + Q => samp_edge_cnt0_r_reg(11), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[0]_i_2_n_6\, + Q => samp_edge_cnt0_r_reg(1), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[0]_i_2_n_5\, + Q => samp_edge_cnt0_r_reg(2), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[0]_i_2_n_4\, + Q => samp_edge_cnt0_r_reg(3), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[4]_i_1_n_7\, + Q => samp_edge_cnt0_r_reg(4), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \samp_edge_cnt0_r_reg[0]_i_2_n_0\, + CO(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_0\, + CO(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_1\, + CO(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_2\, + CO(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \samp_edge_cnt0_r_reg[4]_i_1_n_4\, + O(2) => \samp_edge_cnt0_r_reg[4]_i_1_n_5\, + O(1) => \samp_edge_cnt0_r_reg[4]_i_1_n_6\, + O(0) => \samp_edge_cnt0_r_reg[4]_i_1_n_7\, + S(3 downto 0) => samp_edge_cnt0_r_reg(7 downto 4) + ); +\samp_edge_cnt0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[4]_i_1_n_6\, + Q => samp_edge_cnt0_r_reg(5), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[4]_i_1_n_5\, + Q => samp_edge_cnt0_r_reg(6), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[4]_i_1_n_4\, + Q => samp_edge_cnt0_r_reg(7), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[8]_i_1_n_7\, + Q => samp_edge_cnt0_r_reg(8), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt0_r_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \samp_edge_cnt0_r_reg[4]_i_1_n_0\, + CO(3) => \NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED\(3), + CO(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_1\, + CO(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_2\, + CO(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \samp_edge_cnt0_r_reg[8]_i_1_n_4\, + O(2) => \samp_edge_cnt0_r_reg[8]_i_1_n_5\, + O(1) => \samp_edge_cnt0_r_reg[8]_i_1_n_6\, + O(0) => \samp_edge_cnt0_r_reg[8]_i_1_n_7\, + S(3 downto 0) => samp_edge_cnt0_r_reg(11 downto 8) + ); +\samp_edge_cnt0_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sr_valid_r2, + D => \samp_edge_cnt0_r_reg[8]_i_1_n_6\, + Q => samp_edge_cnt0_r_reg(9), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +samp_edge_cnt1_en_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000200" + ) + port map ( + I0 => samp_edge_cnt1_en_r_i_2_n_0, + I1 => samp_edge_cnt1_en_r_i_3_n_0, + I2 => samp_edge_cnt0_r_reg(3), + I3 => samp_edge_cnt0_r_reg(0), + I4 => samp_edge_cnt0_r_reg(10), + O => samp_edge_cnt1_en_r0 + ); +samp_edge_cnt1_en_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000100" + ) + port map ( + I0 => samp_edge_cnt0_r_reg(6), + I1 => samp_edge_cnt0_r_reg(5), + I2 => samp_edge_cnt0_r_reg(7), + I3 => sr_valid_r2, + I4 => samp_edge_cnt0_r_reg(8), + I5 => samp_edge_cnt0_r_reg(11), + O => samp_edge_cnt1_en_r_i_2_n_0 + ); +samp_edge_cnt1_en_r_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => samp_edge_cnt0_r_reg(9), + I1 => samp_edge_cnt0_r_reg(4), + I2 => samp_edge_cnt0_r_reg(1), + I3 => samp_edge_cnt0_r_reg(2), + O => samp_edge_cnt1_en_r_i_3_n_0 + ); +samp_edge_cnt1_en_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => samp_edge_cnt1_en_r0, + Q => samp_edge_cnt1_en_r, + R => \done_cnt_reg[1]_0\ + ); +\samp_edge_cnt1_r[0]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => samp_edge_cnt1_r_reg(0), + O => \samp_edge_cnt1_r[0]_i_2_n_0\ + ); +\samp_edge_cnt1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[0]_i_1_n_7\, + Q => samp_edge_cnt1_r_reg(0), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[0]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_0\, + CO(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_1\, + CO(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_2\, + CO(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0001", + O(3) => \samp_edge_cnt1_r_reg[0]_i_1_n_4\, + O(2) => \samp_edge_cnt1_r_reg[0]_i_1_n_5\, + O(1) => \samp_edge_cnt1_r_reg[0]_i_1_n_6\, + O(0) => \samp_edge_cnt1_r_reg[0]_i_1_n_7\, + S(3 downto 1) => samp_edge_cnt1_r_reg(3 downto 1), + S(0) => \samp_edge_cnt1_r[0]_i_2_n_0\ + ); +\samp_edge_cnt1_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[8]_i_1_n_5\, + Q => samp_edge_cnt1_r_reg(10), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[8]_i_1_n_4\, + Q => samp_edge_cnt1_r_reg(11), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[0]_i_1_n_6\, + Q => samp_edge_cnt1_r_reg(1), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[0]_i_1_n_5\, + Q => samp_edge_cnt1_r_reg(2), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[0]_i_1_n_4\, + Q => samp_edge_cnt1_r_reg(3), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[4]_i_1_n_7\, + Q => samp_edge_cnt1_r_reg(4), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \samp_edge_cnt1_r_reg[0]_i_1_n_0\, + CO(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_0\, + CO(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_1\, + CO(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_2\, + CO(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \samp_edge_cnt1_r_reg[4]_i_1_n_4\, + O(2) => \samp_edge_cnt1_r_reg[4]_i_1_n_5\, + O(1) => \samp_edge_cnt1_r_reg[4]_i_1_n_6\, + O(0) => \samp_edge_cnt1_r_reg[4]_i_1_n_7\, + S(3 downto 0) => samp_edge_cnt1_r_reg(7 downto 4) + ); +\samp_edge_cnt1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[4]_i_1_n_6\, + Q => samp_edge_cnt1_r_reg(5), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[4]_i_1_n_5\, + Q => samp_edge_cnt1_r_reg(6), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[4]_i_1_n_4\, + Q => samp_edge_cnt1_r_reg(7), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[8]_i_1_n_7\, + Q => samp_edge_cnt1_r_reg(8), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\samp_edge_cnt1_r_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \samp_edge_cnt1_r_reg[4]_i_1_n_0\, + CO(3) => \NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED\(3), + CO(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_1\, + CO(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_2\, + CO(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \samp_edge_cnt1_r_reg[8]_i_1_n_4\, + O(2) => \samp_edge_cnt1_r_reg[8]_i_1_n_5\, + O(1) => \samp_edge_cnt1_r_reg[8]_i_1_n_6\, + O(0) => \samp_edge_cnt1_r_reg[8]_i_1_n_7\, + S(3 downto 0) => samp_edge_cnt1_r_reg(11 downto 8) + ); +\samp_edge_cnt1_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => samp_edge_cnt1_en_r, + D => \samp_edge_cnt1_r_reg[8]_i_1_n_6\, + Q => samp_edge_cnt1_r_reg(9), + R => \samp_edge_cnt1_r_reg[0]_0\ + ); +\second_edge_taps_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[0]\, + O => tap_cnt_cpt_r0(0) + ); +\second_edge_taps_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"82" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[1]\, + O => \second_edge_taps_r[1]_i_1_n_0\ + ); +\second_edge_taps_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A802" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[2]\, + O => \second_edge_taps_r[2]_i_1_n_0\ + ); +\second_edge_taps_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAA80002" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[3]\, + O => \second_edge_taps_r[3]_i_1_n_0\ + ); +\second_edge_taps_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAA800000002" + ) + port map ( + I0 => store_sr_req_pulsed_r, + I1 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I5 => \tap_cnt_cpt_r_reg_n_0_[4]\, + O => \second_edge_taps_r[4]_i_1_n_0\ + ); +\second_edge_taps_r[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \second_edge_taps_r[5]_i_2_n_0\, + I1 => store_sr_req_pulsed_r, + O => \second_edge_taps_r[5]_i_1_n_0\ + ); +\second_edge_taps_r[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00800000" + ) + port map ( + I0 => found_edge_r_reg_n_0, + I1 => store_sr_req_pulsed_r, + I2 => detect_edge_done_r, + I3 => tap_limit_cpt_r, + I4 => \first_edge_taps_r[5]_i_3_n_0\, + I5 => cal1_prech_req_r, + O => \second_edge_taps_r[5]_i_2_n_0\ + ); +\second_edge_taps_r[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFE00000001" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I1 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[4]\, + I5 => \tap_cnt_cpt_r_reg_n_0_[5]\, + O => \second_edge_taps_r[5]_i_3_n_0\ + ); +\second_edge_taps_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \second_edge_taps_r[5]_i_2_n_0\, + D => tap_cnt_cpt_r0(0), + Q => \second_edge_taps_r_reg_n_0_[0]\, + R => \second_edge_taps_r[5]_i_1_n_0\ + ); +\second_edge_taps_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \second_edge_taps_r[5]_i_2_n_0\, + D => \second_edge_taps_r[1]_i_1_n_0\, + Q => \second_edge_taps_r_reg_n_0_[1]\, + R => '0' + ); +\second_edge_taps_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \second_edge_taps_r[5]_i_2_n_0\, + D => \second_edge_taps_r[2]_i_1_n_0\, + Q => \second_edge_taps_r_reg_n_0_[2]\, + R => '0' + ); +\second_edge_taps_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \second_edge_taps_r[5]_i_2_n_0\, + D => \second_edge_taps_r[3]_i_1_n_0\, + Q => \second_edge_taps_r_reg_n_0_[3]\, + R => '0' + ); +\second_edge_taps_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \second_edge_taps_r[5]_i_2_n_0\, + D => \second_edge_taps_r[4]_i_1_n_0\, + Q => \second_edge_taps_r_reg_n_0_[4]\, + R => '0' + ); +\second_edge_taps_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \second_edge_taps_r[5]_i_2_n_0\, + D => \second_edge_taps_r[5]_i_3_n_0\, + Q => \second_edge_taps_r_reg_n_0_[5]\, + R => \second_edge_taps_r[5]_i_1_n_0\ + ); +sr_valid_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => sr_valid_r_reg_n_0, + Q => sr_valid_r1, + R => '0' + ); +sr_valid_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => sr_valid_r1, + Q => sr_valid_r2, + R => '0' + ); +sr_valid_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000008" + ) + port map ( + I0 => E(0), + I1 => rdlvl_stg1_start_r_reg_0, + I2 => cnt_shift_r_reg(2), + I3 => cnt_shift_r_reg(3), + I4 => cnt_shift_r_reg(1), + I5 => cnt_shift_r_reg(0), + O => sr_valid_r_i_1_n_0 + ); +sr_valid_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => sr_valid_r_i_1_n_0, + Q => sr_valid_r_reg_n_0, + R => sr_valid_r_reg_0 + ); +store_sr_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => store_sr_req_r_reg_n_0, + I1 => sr_valid_r_reg_n_0, + I2 => store_sr_r_reg_n_0, + O => store_sr_r_i_1_n_0 + ); +store_sr_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => store_sr_r_i_1_n_0, + Q => store_sr_r_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +store_sr_req_pulsed_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => store_sr_req_pulsed_r, + Q => \store_sr_req_pulsed_r__0\, + R => \done_cnt_reg[1]_0\ + ); +store_sr_req_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"4F444444" + ) + port map ( + I0 => \store_sr_req_pulsed_r__0\, + I1 => store_sr_req_pulsed_r, + I2 => cal1_wait_r, + I3 => store_sr_req_r_reg_0, + I4 => p_3_in4_in, + O => store_sr_req_r + ); +store_sr_req_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => store_sr_req_r, + Q => store_sr_req_r_reg_n_0, + R => \done_cnt_reg[1]_0\ + ); +\tap_cnt_cpt_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => cal1_dlyinc_cpt_r_reg_n_0, + I1 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[1]\, + O => \tap_cnt_cpt_r[1]_i_1_n_0\ + ); +\tap_cnt_cpt_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AA9" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I1 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I3 => cal1_dlyinc_cpt_r_reg_n_0, + O => \p_0_in__0\(2) + ); +\tap_cnt_cpt_r[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6CCCCCC9" + ) + port map ( + I0 => cal1_dlyinc_cpt_r_reg_n_0, + I1 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[0]\, + O => \p_0_in__0\(3) + ); +\tap_cnt_cpt_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6CCCCCCCCCCCCCC9" + ) + port map ( + I0 => cal1_dlyinc_cpt_r_reg_n_0, + I1 => \tap_cnt_cpt_r_reg_n_0_[4]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I5 => \tap_cnt_cpt_r_reg_n_0_[2]\, + O => \p_0_in__0\(4) + ); +\tap_cnt_cpt_r[5]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AA8A" + ) + port map ( + I0 => cal1_dlyce_cpt_r_reg_n_0, + I1 => \tap_cnt_cpt_r_reg_n_0_[5]\, + I2 => \tap_cnt_cpt_r[5]_i_4_n_0\, + I3 => cal1_dlyinc_cpt_r_reg_n_0, + O => tap_cnt_cpt_r + ); +\tap_cnt_cpt_r[5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1DD1" + ) + port map ( + I0 => \tap_cnt_cpt_r[5]_i_5_n_0\, + I1 => cal1_dlyinc_cpt_r_reg_n_0, + I2 => \tap_cnt_cpt_r_reg_n_0_[5]\, + I3 => \tap_cnt_cpt_r[5]_i_6_n_0\, + O => \p_0_in__0\(5) + ); +\tap_cnt_cpt_r[5]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I1 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[4]\, + O => \tap_cnt_cpt_r[5]_i_4_n_0\ + ); +\tap_cnt_cpt_r[5]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555555555556" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[5]\, + I1 => \tap_cnt_cpt_r_reg_n_0_[4]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I5 => \tap_cnt_cpt_r_reg_n_0_[3]\, + O => \tap_cnt_cpt_r[5]_i_5_n_0\ + ); +\tap_cnt_cpt_r[5]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \tap_cnt_cpt_r_reg_n_0_[3]\, + I1 => \tap_cnt_cpt_r_reg_n_0_[0]\, + I2 => \tap_cnt_cpt_r_reg_n_0_[1]\, + I3 => \tap_cnt_cpt_r_reg_n_0_[2]\, + I4 => \tap_cnt_cpt_r_reg_n_0_[4]\, + O => \tap_cnt_cpt_r[5]_i_6_n_0\ + ); +\tap_cnt_cpt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tap_cnt_cpt_r, + D => tap_cnt_cpt_r0(0), + Q => \tap_cnt_cpt_r_reg_n_0_[0]\, + R => \tap_cnt_cpt_r_reg[5]_0\(0) + ); +\tap_cnt_cpt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tap_cnt_cpt_r, + D => \tap_cnt_cpt_r[1]_i_1_n_0\, + Q => \tap_cnt_cpt_r_reg_n_0_[1]\, + R => \tap_cnt_cpt_r_reg[5]_0\(0) + ); +\tap_cnt_cpt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tap_cnt_cpt_r, + D => \p_0_in__0\(2), + Q => \tap_cnt_cpt_r_reg_n_0_[2]\, + R => \tap_cnt_cpt_r_reg[5]_0\(0) + ); +\tap_cnt_cpt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tap_cnt_cpt_r, + D => \p_0_in__0\(3), + Q => \tap_cnt_cpt_r_reg_n_0_[3]\, + R => \tap_cnt_cpt_r_reg[5]_0\(0) + ); +\tap_cnt_cpt_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tap_cnt_cpt_r, + D => \p_0_in__0\(4), + Q => \tap_cnt_cpt_r_reg_n_0_[4]\, + R => \tap_cnt_cpt_r_reg[5]_0\(0) + ); +\tap_cnt_cpt_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tap_cnt_cpt_r, + D => \p_0_in__0\(5), + Q => \tap_cnt_cpt_r_reg_n_0_[5]\, + R => \tap_cnt_cpt_r_reg[5]_0\(0) + ); +tap_limit_cpt_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000AA80" + ) + port map ( + I0 => tap_limit_cpt_r_i_2_n_0, + I1 => \tap_cnt_cpt_r_reg_n_0_[5]\, + I2 => \tap_cnt_cpt_r[5]_i_6_n_0\, + I3 => tap_limit_cpt_r, + I4 => \done_cnt_reg[2]_0\, + I5 => \^new_cnt_cpt_r_reg_0\, + O => tap_limit_cpt_r_i_1_n_0 + ); +tap_limit_cpt_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEFF" + ) + port map ( + I0 => \cal1_state_r1_reg_n_0_[4]\, + I1 => \cal1_state_r1_reg_n_0_[0]\, + I2 => \cal1_state_r1_reg_n_0_[5]\, + I3 => \cal1_state_r1_reg_n_0_[2]\, + I4 => \cal1_state_r1_reg_n_0_[3]\, + I5 => \cal1_state_r1_reg_n_0_[1]\, + O => tap_limit_cpt_r_i_2_n_0 + ); +tap_limit_cpt_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => tap_limit_cpt_r_i_1_n_0, + Q => tap_limit_cpt_r, + R => '0' + ); +\wait_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => wait_cnt_r_reg(0), + O => \wait_cnt_r0__0\(0) + ); +\wait_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => wait_cnt_r_reg(0), + I1 => wait_cnt_r_reg(1), + O => \wait_cnt_r[1]_i_1__0_n_0\ + ); +\wait_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => wait_cnt_r_reg(2), + I1 => wait_cnt_r_reg(1), + I2 => wait_cnt_r_reg(0), + O => \wait_cnt_r0__0\(2) + ); +\wait_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAA8" + ) + port map ( + I0 => dqs_po_dec_done_r2, + I1 => wait_cnt_r_reg(2), + I2 => wait_cnt_r_reg(3), + I3 => wait_cnt_r_reg(0), + I4 => wait_cnt_r_reg(1), + O => wait_cnt_r0 + ); +\wait_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => wait_cnt_r_reg(3), + I1 => wait_cnt_r_reg(2), + I2 => wait_cnt_r_reg(0), + I3 => wait_cnt_r_reg(1), + O => \wait_cnt_r0__0\(3) + ); +\wait_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r0__0\(0), + Q => wait_cnt_r_reg(0), + R => \wait_cnt_r_reg[0]_0\(0) + ); +\wait_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r[1]_i_1__0_n_0\, + Q => wait_cnt_r_reg(1), + R => \wait_cnt_r_reg[0]_0\(0) + ); +\wait_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r0__0\(2), + Q => wait_cnt_r_reg(2), + R => \wait_cnt_r_reg[0]_0\(0) + ); +\wait_cnt_r_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => wait_cnt_r0, + D => \wait_cnt_r0__0\(3), + Q => wait_cnt_r_reg(3), + S => \wait_cnt_r_reg[0]_0\(0) + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[109]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^d\(3), + O => \^d\(2) + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[123]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^d\(3), + I1 => first_wrcal_pat_r, + O => \^d\(4) + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[13]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^d\(3), + I1 => first_rdlvl_pat_r, + O => \^d\(0) + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \^d\(3), + I1 => first_wrcal_pat_r, + O => \^d\(1) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_tempmon is + port ( + pi_f_inc_reg_0 : out STD_LOGIC; + pi_f_dec_reg_0 : out STD_LOGIC; + delay_done_r4_reg : out STD_LOGIC; + rdlvl_stg1_done_int_reg : out STD_LOGIC; + calib_sel0 : out STD_LOGIC; + init_calib_complete_reg : out STD_LOGIC; + wrcal_done_reg : out STD_LOGIC; + CLK : in STD_LOGIC; + \four_inc_max_limit_reg[2]_0\ : in STD_LOGIC; + mc_ref_zq_wip : in STD_LOGIC; + \four_dec_min_limit_reg[0]_0\ : in STD_LOGIC; + pi_f_dec_reg_1 : in STD_LOGIC; + \two_inc_max_limit_reg[11]_0\ : in STD_LOGIC; + \three_dec_max_limit_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + ck_addr_cmd_delay_done : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + \calib_sel_reg[0]\ : in STD_LOGIC; + calib_complete : in STD_LOGIC; + pi_dqs_found_done : in STD_LOGIC; + \device_temp_101_reg[11]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_tempmon : entity is "mig_7series_v4_2_ddr_phy_tempmon"; +end ddr3_mig_7series_v4_2_ddr_phy_tempmon; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_tempmon is + signal device_temp_101 : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal device_temp_init : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \device_temp_init[11]_i_2_n_0\ : STD_LOGIC; + signal \device_temp_init[11]_i_3_n_0\ : STD_LOGIC; + signal four_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \four_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \four_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal four_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \four_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \four_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \four_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \four_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \four_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \four_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \four_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \four_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \four_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal four_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \four_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \four_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \four_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC; + signal \four_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC; + signal \four_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC; + signal \four_inc_max_limit[4]_i_5_n_0\ : STD_LOGIC; + signal \four_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC; + signal \four_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC; + signal four_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \four_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \four_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \four_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \four_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \four_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \four_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \four_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \four_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \four_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \four_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC; + signal neutral_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal \neutral_max_limit[1]_i_1_n_0\ : STD_LOGIC; + signal \neutral_max_limit[4]_i_2_n_0\ : STD_LOGIC; + signal \neutral_max_limit[4]_i_3_n_0\ : STD_LOGIC; + signal \neutral_max_limit[4]_i_4_n_0\ : STD_LOGIC; + signal \neutral_max_limit[8]_i_2_n_0\ : STD_LOGIC; + signal \neutral_max_limit[8]_i_3_n_0\ : STD_LOGIC; + signal neutral_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \neutral_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \neutral_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \neutral_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \neutral_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \neutral_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \neutral_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \neutral_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \neutral_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \neutral_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \neutral_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC; + signal neutral_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \neutral_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \neutral_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \neutral_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \neutral_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \neutral_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \neutral_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \neutral_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \neutral_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \neutral_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal neutral_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \neutral_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \neutral_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \neutral_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \neutral_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \neutral_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \neutral_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \neutral_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \neutral_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \neutral_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal one_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal \one_dec_max_limit[1]_i_1_n_0\ : STD_LOGIC; + signal \one_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC; + signal \one_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC; + signal \one_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC; + signal \one_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC; + signal one_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \one_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \one_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \one_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \one_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \one_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \one_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \one_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \one_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \one_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \one_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC; + signal one_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \one_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \one_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal one_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \one_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \one_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \one_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \one_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \one_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \one_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \one_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \one_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \one_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal one_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \one_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \one_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \one_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC; + signal \one_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC; + signal \one_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC; + signal \one_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC; + signal one_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \one_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \one_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \one_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \one_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \one_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \one_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \one_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \one_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \one_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \one_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC; + signal one_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \one_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \one_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal one_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \one_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \one_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \one_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \one_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \one_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \one_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \one_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \one_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \one_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal pi_f_dec_i_2_n_0 : STD_LOGIC; + signal pi_f_dec_nxt : STD_LOGIC; + signal \^pi_f_dec_reg_0\ : STD_LOGIC; + signal pi_f_inc_i_2_n_0 : STD_LOGIC; + signal pi_f_inc_i_3_n_0 : STD_LOGIC; + signal pi_f_inc_i_4_n_0 : STD_LOGIC; + signal pi_f_inc_i_5_n_0 : STD_LOGIC; + signal pi_f_inc_i_6_n_0 : STD_LOGIC; + signal pi_f_inc_i_7_n_0 : STD_LOGIC; + signal pi_f_inc_nxt : STD_LOGIC; + signal \^pi_f_inc_reg_0\ : STD_LOGIC; + signal temp_cmp_four_dec_min_101 : STD_LOGIC; + signal temp_cmp_four_dec_min_102 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_four_dec_min_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_four_inc_max_101 : STD_LOGIC; + signal temp_cmp_four_inc_max_102 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_four_inc_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_neutral_max_101 : STD_LOGIC; + signal temp_cmp_neutral_max_102 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_neutral_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_neutral_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_neutral_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_neutral_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_neutral_min_101 : STD_LOGIC; + signal temp_cmp_neutral_min_102 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_neutral_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_neutral_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_neutral_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_neutral_min_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_one_dec_max_101 : STD_LOGIC; + signal temp_cmp_one_dec_max_102 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_one_dec_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_one_dec_min_101 : STD_LOGIC; + signal temp_cmp_one_dec_min_102 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_one_dec_min_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_one_inc_max_101 : STD_LOGIC; + signal temp_cmp_one_inc_max_102 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_one_inc_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_one_inc_min_101 : STD_LOGIC; + signal temp_cmp_one_inc_min_102 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_one_inc_min_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_three_dec_max_101 : STD_LOGIC; + signal temp_cmp_three_dec_max_102 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_three_dec_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_three_dec_min_101 : STD_LOGIC; + signal temp_cmp_three_dec_min_102 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_three_dec_min_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_three_inc_max_101 : STD_LOGIC; + signal temp_cmp_three_inc_max_102 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_three_inc_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_three_inc_min_101 : STD_LOGIC; + signal temp_cmp_three_inc_min_102 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_three_inc_min_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_two_dec_max_101 : STD_LOGIC; + signal temp_cmp_two_dec_max_102 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_two_dec_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_two_dec_min_101 : STD_LOGIC; + signal temp_cmp_two_dec_min_102 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_two_dec_min_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_two_inc_max_101 : STD_LOGIC; + signal temp_cmp_two_inc_max_102 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_two_inc_max_102_reg_i_2_n_3 : STD_LOGIC; + signal temp_cmp_two_inc_min_101 : STD_LOGIC; + signal temp_cmp_two_inc_min_102 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_10_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_11_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_12_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_13_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_14_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_3_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_4_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_5_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_6_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_7_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_8_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_i_9_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_reg_i_1_n_3 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_reg_i_2_n_0 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_reg_i_2_n_1 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_reg_i_2_n_2 : STD_LOGIC; + signal temp_cmp_two_inc_min_102_reg_i_2_n_3 : STD_LOGIC; + signal tempmon_init_complete : STD_LOGIC; + signal tempmon_sample_en_101 : STD_LOGIC; + signal tempmon_sample_en_102 : STD_LOGIC; + signal tempmon_state : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal \tempmon_state[10]_i_10_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_11_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_12_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_13_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_14_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_15_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_1_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_3_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_4_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_5_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_6_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_7_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_8_n_0\ : STD_LOGIC; + signal \tempmon_state[10]_i_9_n_0\ : STD_LOGIC; + signal \tempmon_state[6]_i_2_n_0\ : STD_LOGIC; + signal tempmon_state_init : STD_LOGIC; + signal tempmon_state_nxt : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal three_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \three_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[10]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[11]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[1]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[2]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[3]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[4]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[5]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[6]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[7]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[8]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[8]_i_3_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[8]_i_4_n_0\ : STD_LOGIC; + signal \three_dec_max_limit[9]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_max_limit_reg[11]_i_2_n_2\ : STD_LOGIC; + signal \three_dec_max_limit_reg[11]_i_2_n_3\ : STD_LOGIC; + signal \three_dec_max_limit_reg[11]_i_2_n_5\ : STD_LOGIC; + signal \three_dec_max_limit_reg[11]_i_2_n_6\ : STD_LOGIC; + signal \three_dec_max_limit_reg[11]_i_2_n_7\ : STD_LOGIC; + signal \three_dec_max_limit_reg[4]_i_2_n_0\ : STD_LOGIC; + signal \three_dec_max_limit_reg[4]_i_2_n_1\ : STD_LOGIC; + signal \three_dec_max_limit_reg[4]_i_2_n_2\ : STD_LOGIC; + signal \three_dec_max_limit_reg[4]_i_2_n_3\ : STD_LOGIC; + signal \three_dec_max_limit_reg[4]_i_2_n_4\ : STD_LOGIC; + signal \three_dec_max_limit_reg[4]_i_2_n_5\ : STD_LOGIC; + signal \three_dec_max_limit_reg[4]_i_2_n_6\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_0\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_1\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_2\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_3\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_4\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_5\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_6\ : STD_LOGIC; + signal \three_dec_max_limit_reg[8]_i_2_n_7\ : STD_LOGIC; + signal three_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \three_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \three_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal three_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \three_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \three_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \three_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \three_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \three_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \three_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \three_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \three_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal three_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \three_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \three_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \three_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC; + signal \three_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC; + signal \three_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC; + signal \three_inc_max_limit[8]_i_3_n_0\ : STD_LOGIC; + signal \three_inc_max_limit[8]_i_4_n_0\ : STD_LOGIC; + signal three_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \three_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \three_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \three_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \three_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \three_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \three_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \three_inc_max_limit_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \three_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \three_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \three_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \three_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC; + signal three_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal \three_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \three_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal three_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \three_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \three_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \three_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \three_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \three_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \three_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \three_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \three_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \three_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal two_dec_max_limit : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \two_dec_max_limit[0]_i_1_n_0\ : STD_LOGIC; + signal \two_dec_max_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \two_dec_max_limit[4]_i_2_n_0\ : STD_LOGIC; + signal \two_dec_max_limit[4]_i_3_n_0\ : STD_LOGIC; + signal \two_dec_max_limit[8]_i_2_n_0\ : STD_LOGIC; + signal two_dec_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal \two_dec_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \two_dec_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \two_dec_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \two_dec_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \two_dec_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \two_dec_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \two_dec_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \two_dec_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \two_dec_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \two_dec_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC; + signal two_dec_min_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \two_dec_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \two_dec_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal two_dec_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \two_dec_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \two_dec_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \two_dec_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \two_dec_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \two_dec_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \two_dec_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \two_dec_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \two_dec_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \two_dec_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal two_inc_max_limit : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \two_inc_max_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \two_inc_max_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \two_inc_max_limit[11]_i_4_n_0\ : STD_LOGIC; + signal \two_inc_max_limit[4]_i_2_n_0\ : STD_LOGIC; + signal \two_inc_max_limit[4]_i_3_n_0\ : STD_LOGIC; + signal \two_inc_max_limit[4]_i_4_n_0\ : STD_LOGIC; + signal \two_inc_max_limit[8]_i_2_n_0\ : STD_LOGIC; + signal two_inc_max_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \two_inc_max_limit_reg[11]_i_1_n_2\ : STD_LOGIC; + signal \two_inc_max_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \two_inc_max_limit_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \two_inc_max_limit_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \two_inc_max_limit_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \two_inc_max_limit_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \two_inc_max_limit_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \two_inc_max_limit_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \two_inc_max_limit_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \two_inc_max_limit_reg[8]_i_1_n_3\ : STD_LOGIC; + signal two_inc_min_limit : STD_LOGIC_VECTOR ( 11 downto 1 ); + signal \two_inc_min_limit[11]_i_2_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[11]_i_3_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[5]_i_2_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[5]_i_3_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[5]_i_4_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[9]_i_2_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[9]_i_3_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[9]_i_4_n_0\ : STD_LOGIC; + signal \two_inc_min_limit[9]_i_5_n_0\ : STD_LOGIC; + signal two_inc_min_limit_nxt : STD_LOGIC_VECTOR ( 11 downto 2 ); + signal \two_inc_min_limit_reg[11]_i_1_n_3\ : STD_LOGIC; + signal \two_inc_min_limit_reg[5]_i_1_n_0\ : STD_LOGIC; + signal \two_inc_min_limit_reg[5]_i_1_n_1\ : STD_LOGIC; + signal \two_inc_min_limit_reg[5]_i_1_n_2\ : STD_LOGIC; + signal \two_inc_min_limit_reg[5]_i_1_n_3\ : STD_LOGIC; + signal \two_inc_min_limit_reg[9]_i_1_n_0\ : STD_LOGIC; + signal \two_inc_min_limit_reg[9]_i_1_n_1\ : STD_LOGIC; + signal \two_inc_min_limit_reg[9]_i_1_n_2\ : STD_LOGIC; + signal \two_inc_min_limit_reg[9]_i_1_n_3\ : STD_LOGIC; + signal \update_temp_101__0\ : STD_LOGIC; + signal update_temp_102 : STD_LOGIC; + signal \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 ); + signal \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); + signal \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \calib_sel[1]_i_2\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of \calib_zero_inputs[0]_i_1\ : label is "soft_lutpair173"; + attribute SOFT_HLUTNM of \device_temp_init[11]_i_3\ : label is "soft_lutpair172"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \four_dec_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \four_dec_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \four_dec_min_limit_reg[9]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \four_inc_max_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \four_inc_max_limit_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \four_inc_max_limit_reg[8]_i_1\ : label is 35; + attribute SOFT_HLUTNM of \neutral_max_limit[1]_i_1\ : label is "soft_lutpair180"; + attribute ADDER_THRESHOLD of \neutral_max_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \neutral_max_limit_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \neutral_max_limit_reg[8]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \neutral_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \neutral_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \neutral_min_limit_reg[9]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_dec_max_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_dec_max_limit_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_dec_max_limit_reg[8]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_dec_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_dec_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_dec_min_limit_reg[9]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_inc_max_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_inc_max_limit_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_inc_max_limit_reg[8]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_inc_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_inc_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \one_inc_min_limit_reg[9]_i_1\ : label is 35; + attribute SOFT_HLUTNM of pi_f_inc_i_7 : label is "soft_lutpair170"; + attribute COMPARATOR_THRESHOLD : integer; + attribute COMPARATOR_THRESHOLD of temp_cmp_four_dec_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_four_dec_min_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_four_inc_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_four_inc_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_neutral_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_neutral_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_neutral_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_neutral_min_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_dec_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_dec_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_dec_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_dec_min_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_inc_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_inc_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_inc_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_one_inc_min_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_dec_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_dec_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_dec_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_dec_min_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_inc_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_inc_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_inc_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_three_inc_min_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_dec_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_dec_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_dec_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_dec_min_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_inc_max_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_inc_max_102_reg_i_2 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_inc_min_102_reg_i_1 : label is 11; + attribute COMPARATOR_THRESHOLD of temp_cmp_two_inc_min_102_reg_i_2 : label is 11; + attribute SOFT_HLUTNM of \tempmon_state[10]_i_10\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \tempmon_state[10]_i_11\ : label is "soft_lutpair168"; + attribute SOFT_HLUTNM of \tempmon_state[10]_i_15\ : label is "soft_lutpair171"; + attribute SOFT_HLUTNM of \tempmon_state[10]_i_4\ : label is "soft_lutpair169"; + attribute SOFT_HLUTNM of \tempmon_state[10]_i_7\ : label is "soft_lutpair170"; + attribute SOFT_HLUTNM of \tempmon_state[1]_i_1\ : label is "soft_lutpair169"; + attribute SOFT_HLUTNM of \tempmon_state[6]_i_2\ : label is "soft_lutpair172"; + attribute SOFT_HLUTNM of \tempmon_state[9]_i_1\ : label is "soft_lutpair171"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[0]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[10]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[1]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[2]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[3]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[4]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[5]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[6]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[7]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[8]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute FSM_ENCODED_STATES of \tempmon_state_reg[9]\ : label is "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000"; + attribute SOFT_HLUTNM of \three_dec_max_limit[0]_i_1\ : label is "soft_lutpair177"; + attribute SOFT_HLUTNM of \three_dec_max_limit[10]_i_1\ : label is "soft_lutpair174"; + attribute SOFT_HLUTNM of \three_dec_max_limit[11]_i_1\ : label is "soft_lutpair174"; + attribute SOFT_HLUTNM of \three_dec_max_limit[1]_i_1\ : label is "soft_lutpair179"; + attribute SOFT_HLUTNM of \three_dec_max_limit[2]_i_1\ : label is "soft_lutpair179"; + attribute SOFT_HLUTNM of \three_dec_max_limit[3]_i_1\ : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of \three_dec_max_limit[4]_i_1\ : label is "soft_lutpair178"; + attribute SOFT_HLUTNM of \three_dec_max_limit[5]_i_1\ : label is "soft_lutpair177"; + attribute SOFT_HLUTNM of \three_dec_max_limit[6]_i_1\ : label is "soft_lutpair175"; + attribute SOFT_HLUTNM of \three_dec_max_limit[7]_i_1\ : label is "soft_lutpair176"; + attribute SOFT_HLUTNM of \three_dec_max_limit[8]_i_1\ : label is "soft_lutpair176"; + attribute SOFT_HLUTNM of \three_dec_max_limit[9]_i_1\ : label is "soft_lutpair175"; + attribute ADDER_THRESHOLD of \three_dec_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_dec_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_dec_min_limit_reg[9]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_inc_max_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_inc_max_limit_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_inc_max_limit_reg[8]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_inc_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_inc_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \three_inc_min_limit_reg[9]_i_1\ : label is 35; + attribute SOFT_HLUTNM of \two_dec_max_limit[0]_i_1\ : label is "soft_lutpair180"; + attribute ADDER_THRESHOLD of \two_dec_max_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_dec_max_limit_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_dec_max_limit_reg[8]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_dec_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_dec_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_dec_min_limit_reg[9]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_inc_max_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_inc_max_limit_reg[4]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_inc_max_limit_reg[8]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_inc_min_limit_reg[11]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_inc_min_limit_reg[5]_i_1\ : label is 35; + attribute ADDER_THRESHOLD of \two_inc_min_limit_reg[9]_i_1\ : label is 35; +begin + pi_f_dec_reg_0 <= \^pi_f_dec_reg_0\; + pi_f_inc_reg_0 <= \^pi_f_inc_reg_0\; +\calib_sel[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"ABAA" + ) + port map ( + I0 => \calib_sel_reg[0]\, + I1 => \^pi_f_inc_reg_0\, + I2 => \^pi_f_dec_reg_0\, + I3 => calib_complete, + O => calib_sel0 + ); +\calib_zero_inputs[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => calib_complete, + I1 => \^pi_f_dec_reg_0\, + I2 => \^pi_f_inc_reg_0\, + O => init_calib_complete_reg + ); +\device_temp_101_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(0), + Q => device_temp_101(0), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(10), + Q => device_temp_101(10), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(11), + Q => device_temp_101(11), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(1), + Q => device_temp_101(1), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(2), + Q => device_temp_101(2), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(3), + Q => device_temp_101(3), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(4), + Q => device_temp_101(4), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(5), + Q => device_temp_101(5), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(6), + Q => device_temp_101(6), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(7), + Q => device_temp_101(7), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(8), + Q => device_temp_101(8), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_101_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \device_temp_101_reg[11]_0\(9), + Q => device_temp_101(9), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => tempmon_state(9), + I1 => tempmon_state(7), + I2 => tempmon_state(8), + I3 => \device_temp_init[11]_i_2_n_0\, + I4 => \device_temp_init[11]_i_3_n_0\, + O => tempmon_state_init + ); +\device_temp_init[11]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => tempmon_state(1), + I1 => tempmon_state(2), + I2 => tempmon_state(3), + I3 => tempmon_state(10), + O => \device_temp_init[11]_i_2_n_0\ + ); +\device_temp_init[11]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => tempmon_state(0), + I1 => tempmon_state(4), + I2 => tempmon_state(5), + I3 => tempmon_state(6), + O => \device_temp_init[11]_i_3_n_0\ + ); +\device_temp_init_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(0), + Q => device_temp_init(0), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(10), + Q => device_temp_init(10), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(11), + Q => device_temp_init(11), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(1), + Q => device_temp_init(1), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(2), + Q => device_temp_init(2), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(3), + Q => device_temp_init(3), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(4), + Q => device_temp_init(4), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(5), + Q => device_temp_init(5), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(6), + Q => device_temp_init(6), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(7), + Q => device_temp_init(7), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(8), + Q => device_temp_init(8), + R => \four_inc_max_limit_reg[2]_0\ + ); +\device_temp_init_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => device_temp_101(9), + Q => device_temp_init(9), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(11), + O => \four_dec_min_limit[11]_i_2_n_0\ + ); +\four_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(10), + O => \four_dec_min_limit[11]_i_3_n_0\ + ); +\four_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(5), + O => \four_dec_min_limit[5]_i_2_n_0\ + ); +\four_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(4), + O => \four_dec_min_limit[5]_i_3_n_0\ + ); +\four_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(3), + O => \four_dec_min_limit[5]_i_4_n_0\ + ); +\four_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(9), + O => \four_dec_min_limit[9]_i_2_n_0\ + ); +\four_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(8), + O => \four_dec_min_limit[9]_i_3_n_0\ + ); +\four_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(7), + O => \four_dec_min_limit[9]_i_4_n_0\ + ); +\four_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_dec_max_limit(6), + O => \four_dec_min_limit[9]_i_5_n_0\ + ); +\four_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_max_limit(0), + Q => four_dec_min_limit(0), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(10), + Q => four_dec_min_limit(10), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(11), + Q => four_dec_min_limit(11), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \four_dec_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \four_dec_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => three_dec_max_limit(10), + O(3 downto 2) => \NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => four_dec_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \four_dec_min_limit[11]_i_2_n_0\, + S(0) => \four_dec_min_limit[11]_i_3_n_0\ + ); +\four_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_max_limit(1), + Q => four_dec_min_limit(1), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(2), + Q => four_dec_min_limit(2), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(3), + Q => four_dec_min_limit(3), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(4), + Q => four_dec_min_limit(4), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(5), + Q => four_dec_min_limit(5), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \four_dec_min_limit_reg[5]_i_1_n_0\, + CO(2) => \four_dec_min_limit_reg[5]_i_1_n_1\, + CO(1) => \four_dec_min_limit_reg[5]_i_1_n_2\, + CO(0) => \four_dec_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => three_dec_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => four_dec_min_limit_nxt(5 downto 2), + S(3) => \four_dec_min_limit[5]_i_2_n_0\, + S(2) => \four_dec_min_limit[5]_i_3_n_0\, + S(1) => \four_dec_min_limit[5]_i_4_n_0\, + S(0) => three_dec_max_limit(2) + ); +\four_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(6), + Q => four_dec_min_limit(6), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(7), + Q => four_dec_min_limit(7), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(8), + Q => four_dec_min_limit(8), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_dec_min_limit_nxt(9), + Q => four_dec_min_limit(9), + R => \four_dec_min_limit_reg[0]_0\ + ); +\four_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \four_dec_min_limit_reg[5]_i_1_n_0\, + CO(3) => \four_dec_min_limit_reg[9]_i_1_n_0\, + CO(2) => \four_dec_min_limit_reg[9]_i_1_n_1\, + CO(1) => \four_dec_min_limit_reg[9]_i_1_n_2\, + CO(0) => \four_dec_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => three_dec_max_limit(9 downto 6), + O(3 downto 0) => four_dec_min_limit_nxt(9 downto 6), + S(3) => \four_dec_min_limit[9]_i_2_n_0\, + S(2) => \four_dec_min_limit[9]_i_3_n_0\, + S(1) => \four_dec_min_limit[9]_i_4_n_0\, + S(0) => \four_dec_min_limit[9]_i_5_n_0\ + ); +\four_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(11), + O => \four_inc_max_limit[11]_i_2_n_0\ + ); +\four_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(10), + O => \four_inc_max_limit[11]_i_3_n_0\ + ); +\four_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(4), + O => \four_inc_max_limit[4]_i_2_n_0\ + ); +\four_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(3), + O => \four_inc_max_limit[4]_i_3_n_0\ + ); +\four_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(2), + O => \four_inc_max_limit[4]_i_4_n_0\ + ); +\four_inc_max_limit[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(1), + O => \four_inc_max_limit[4]_i_5_n_0\ + ); +\four_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(7), + O => \four_inc_max_limit[8]_i_2_n_0\ + ); +\four_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(5), + O => \four_inc_max_limit[8]_i_3_n_0\ + ); +\four_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(10), + Q => four_inc_max_limit(10), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(11), + Q => four_inc_max_limit(11), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \four_inc_max_limit_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \four_inc_max_limit_reg[11]_i_1_n_2\, + CO(0) => \four_inc_max_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => device_temp_init(10), + DI(0) => '0', + O(3) => \NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => four_inc_max_limit_nxt(11 downto 9), + S(3) => '0', + S(2) => \four_inc_max_limit[11]_i_2_n_0\, + S(1) => \four_inc_max_limit[11]_i_3_n_0\, + S(0) => device_temp_init(9) + ); +\four_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(2), + Q => four_inc_max_limit(2), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(3), + Q => four_inc_max_limit(3), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(4), + Q => four_inc_max_limit(4), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \four_inc_max_limit_reg[4]_i_1_n_0\, + CO(2) => \four_inc_max_limit_reg[4]_i_1_n_1\, + CO(1) => \four_inc_max_limit_reg[4]_i_1_n_2\, + CO(0) => \four_inc_max_limit_reg[4]_i_1_n_3\, + CYINIT => device_temp_init(0), + DI(3 downto 0) => device_temp_init(4 downto 1), + O(3 downto 1) => four_inc_max_limit_nxt(4 downto 2), + O(0) => two_dec_max_limit_nxt(1), + S(3) => \four_inc_max_limit[4]_i_2_n_0\, + S(2) => \four_inc_max_limit[4]_i_3_n_0\, + S(1) => \four_inc_max_limit[4]_i_4_n_0\, + S(0) => \four_inc_max_limit[4]_i_5_n_0\ + ); +\four_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(5), + Q => four_inc_max_limit(5), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(6), + Q => four_inc_max_limit(6), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(7), + Q => four_inc_max_limit(7), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(8), + Q => four_inc_max_limit(8), + R => \four_inc_max_limit_reg[2]_0\ + ); +\four_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \four_inc_max_limit_reg[4]_i_1_n_0\, + CO(3) => \four_inc_max_limit_reg[8]_i_1_n_0\, + CO(2) => \four_inc_max_limit_reg[8]_i_1_n_1\, + CO(1) => \four_inc_max_limit_reg[8]_i_1_n_2\, + CO(0) => \four_inc_max_limit_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => device_temp_init(7), + DI(1) => '0', + DI(0) => device_temp_init(5), + O(3 downto 0) => four_inc_max_limit_nxt(8 downto 5), + S(3) => device_temp_init(8), + S(2) => \four_inc_max_limit[8]_i_2_n_0\, + S(1) => device_temp_init(6), + S(0) => \four_inc_max_limit[8]_i_3_n_0\ + ); +\four_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => four_inc_max_limit_nxt(9), + Q => four_inc_max_limit(9), + R => \four_inc_max_limit_reg[2]_0\ + ); +\gen_byte_sel_div2.byte_sel_cnt[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAA2AAAAAAAAA" + ) + port map ( + I0 => ck_addr_cmd_delay_done, + I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\, + I2 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\, + I3 => \^pi_f_inc_reg_0\, + I4 => \^pi_f_dec_reg_0\, + I5 => D(0), + O => delay_done_r4_reg + ); +\gen_byte_sel_div2.calib_in_common_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88800000FFFFFFFF" + ) + port map ( + I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\, + I1 => D(0), + I2 => \^pi_f_dec_reg_0\, + I3 => \^pi_f_inc_reg_0\, + I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\, + I5 => pi_dqs_found_done, + O => wrcal_done_reg + ); +\gen_byte_sel_div2.calib_in_common_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FDFFFFFF" + ) + port map ( + I0 => D(0), + I1 => \^pi_f_dec_reg_0\, + I2 => \^pi_f_inc_reg_0\, + I3 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\, + I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\, + O => rdlvl_stg1_done_int_reg + ); +\neutral_max_limit[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => device_temp_init(0), + I1 => device_temp_init(1), + O => \neutral_max_limit[1]_i_1_n_0\ + ); +\neutral_max_limit[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(4), + O => \neutral_max_limit[4]_i_2_n_0\ + ); +\neutral_max_limit[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(2), + O => \neutral_max_limit[4]_i_3_n_0\ + ); +\neutral_max_limit[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(1), + O => \neutral_max_limit[4]_i_4_n_0\ + ); +\neutral_max_limit[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(6), + O => \neutral_max_limit[8]_i_2_n_0\ + ); +\neutral_max_limit[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(5), + O => \neutral_max_limit[8]_i_3_n_0\ + ); +\neutral_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(10), + Q => neutral_max_limit(10), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(11), + Q => neutral_max_limit(11), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \neutral_max_limit_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \neutral_max_limit_reg[11]_i_1_n_2\, + CO(0) => \neutral_max_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => neutral_max_limit_nxt(11 downto 9), + S(3) => '0', + S(2 downto 0) => device_temp_init(11 downto 9) + ); +\neutral_max_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \neutral_max_limit[1]_i_1_n_0\, + Q => neutral_max_limit(1), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(2), + Q => neutral_max_limit(2), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(3), + Q => neutral_max_limit(3), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(4), + Q => neutral_max_limit(4), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \neutral_max_limit_reg[4]_i_1_n_0\, + CO(2) => \neutral_max_limit_reg[4]_i_1_n_1\, + CO(1) => \neutral_max_limit_reg[4]_i_1_n_2\, + CO(0) => \neutral_max_limit_reg[4]_i_1_n_3\, + CYINIT => device_temp_init(0), + DI(3) => device_temp_init(4), + DI(2) => '0', + DI(1 downto 0) => device_temp_init(2 downto 1), + O(3 downto 1) => neutral_max_limit_nxt(4 downto 2), + O(0) => \NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED\(0), + S(3) => \neutral_max_limit[4]_i_2_n_0\, + S(2) => device_temp_init(3), + S(1) => \neutral_max_limit[4]_i_3_n_0\, + S(0) => \neutral_max_limit[4]_i_4_n_0\ + ); +\neutral_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(5), + Q => neutral_max_limit(5), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(6), + Q => neutral_max_limit(6), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(7), + Q => neutral_max_limit(7), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(8), + Q => neutral_max_limit(8), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \neutral_max_limit_reg[4]_i_1_n_0\, + CO(3) => \neutral_max_limit_reg[8]_i_1_n_0\, + CO(2) => \neutral_max_limit_reg[8]_i_1_n_1\, + CO(1) => \neutral_max_limit_reg[8]_i_1_n_2\, + CO(0) => \neutral_max_limit_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => device_temp_init(6 downto 5), + O(3 downto 0) => neutral_max_limit_nxt(8 downto 5), + S(3 downto 2) => device_temp_init(8 downto 7), + S(1) => \neutral_max_limit[8]_i_2_n_0\, + S(0) => \neutral_max_limit[8]_i_3_n_0\ + ); +\neutral_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit_nxt(9), + Q => neutral_max_limit(9), + R => \two_inc_max_limit_reg[11]_0\ + ); +\neutral_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(11), + O => \neutral_min_limit[11]_i_2_n_0\ + ); +\neutral_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(10), + O => \neutral_min_limit[11]_i_3_n_0\ + ); +\neutral_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(5), + O => \neutral_min_limit[5]_i_2_n_0\ + ); +\neutral_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(4), + O => \neutral_min_limit[5]_i_3_n_0\ + ); +\neutral_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(3), + O => \neutral_min_limit[5]_i_4_n_0\ + ); +\neutral_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(9), + O => \neutral_min_limit[9]_i_2_n_0\ + ); +\neutral_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(8), + O => \neutral_min_limit[9]_i_3_n_0\ + ); +\neutral_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(7), + O => \neutral_min_limit[9]_i_4_n_0\ + ); +\neutral_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_inc_max_limit(6), + O => \neutral_min_limit[9]_i_5_n_0\ + ); +\neutral_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(10), + Q => neutral_min_limit(10), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(11), + Q => neutral_min_limit(11), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \neutral_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \neutral_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => one_inc_max_limit(10), + O(3 downto 2) => \NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => neutral_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \neutral_min_limit[11]_i_2_n_0\, + S(0) => \neutral_min_limit[11]_i_3_n_0\ + ); +\neutral_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(2), + Q => neutral_min_limit(2), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(3), + Q => neutral_min_limit(3), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(4), + Q => neutral_min_limit(4), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(5), + Q => neutral_min_limit(5), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \neutral_min_limit_reg[5]_i_1_n_0\, + CO(2) => \neutral_min_limit_reg[5]_i_1_n_1\, + CO(1) => \neutral_min_limit_reg[5]_i_1_n_2\, + CO(0) => \neutral_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => one_inc_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => neutral_min_limit_nxt(5 downto 2), + S(3) => \neutral_min_limit[5]_i_2_n_0\, + S(2) => \neutral_min_limit[5]_i_3_n_0\, + S(1) => \neutral_min_limit[5]_i_4_n_0\, + S(0) => one_inc_max_limit(2) + ); +\neutral_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(6), + Q => neutral_min_limit(6), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(7), + Q => neutral_min_limit(7), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(8), + Q => neutral_min_limit(8), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_min_limit_nxt(9), + Q => neutral_min_limit(9), + R => \four_dec_min_limit_reg[0]_0\ + ); +\neutral_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \neutral_min_limit_reg[5]_i_1_n_0\, + CO(3) => \neutral_min_limit_reg[9]_i_1_n_0\, + CO(2) => \neutral_min_limit_reg[9]_i_1_n_1\, + CO(1) => \neutral_min_limit_reg[9]_i_1_n_2\, + CO(0) => \neutral_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => one_inc_max_limit(9 downto 6), + O(3 downto 0) => neutral_min_limit_nxt(9 downto 6), + S(3) => \neutral_min_limit[9]_i_2_n_0\, + S(2) => \neutral_min_limit[9]_i_3_n_0\, + S(1) => \neutral_min_limit[9]_i_4_n_0\, + S(0) => \neutral_min_limit[9]_i_5_n_0\ + ); +\one_dec_max_limit[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => device_temp_init(1), + I1 => device_temp_init(0), + O => \one_dec_max_limit[1]_i_1_n_0\ + ); +\one_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(2), + O => \one_dec_max_limit[4]_i_2_n_0\ + ); +\one_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(8), + O => \one_dec_max_limit[8]_i_2_n_0\ + ); +\one_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(6), + O => \one_dec_max_limit[8]_i_3_n_0\ + ); +\one_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(5), + O => \one_dec_max_limit[8]_i_4_n_0\ + ); +\one_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(10), + Q => one_dec_max_limit(10), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(11), + Q => one_dec_max_limit(11), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_dec_max_limit_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \one_dec_max_limit_reg[11]_i_1_n_2\, + CO(0) => \one_dec_max_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0000", + O(3) => \NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => one_dec_max_limit_nxt(11 downto 9), + S(3) => '0', + S(2 downto 0) => device_temp_init(11 downto 9) + ); +\one_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \one_dec_max_limit[1]_i_1_n_0\, + Q => one_dec_max_limit(1), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(2), + Q => one_dec_max_limit(2), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(3), + Q => one_dec_max_limit(3), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(4), + Q => one_dec_max_limit(4), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \one_dec_max_limit_reg[4]_i_1_n_0\, + CO(2) => \one_dec_max_limit_reg[4]_i_1_n_1\, + CO(1) => \one_dec_max_limit_reg[4]_i_1_n_2\, + CO(0) => \one_dec_max_limit_reg[4]_i_1_n_3\, + CYINIT => device_temp_init(0), + DI(3 downto 2) => B"00", + DI(1) => device_temp_init(2), + DI(0) => '0', + O(3 downto 1) => one_dec_max_limit_nxt(4 downto 2), + O(0) => \NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0), + S(3 downto 2) => device_temp_init(4 downto 3), + S(1) => \one_dec_max_limit[4]_i_2_n_0\, + S(0) => device_temp_init(1) + ); +\one_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(5), + Q => one_dec_max_limit(5), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(6), + Q => one_dec_max_limit(6), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(7), + Q => one_dec_max_limit(7), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(8), + Q => one_dec_max_limit(8), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_dec_max_limit_reg[4]_i_1_n_0\, + CO(3) => \one_dec_max_limit_reg[8]_i_1_n_0\, + CO(2) => \one_dec_max_limit_reg[8]_i_1_n_1\, + CO(1) => \one_dec_max_limit_reg[8]_i_1_n_2\, + CO(0) => \one_dec_max_limit_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3) => device_temp_init(8), + DI(2) => '0', + DI(1 downto 0) => device_temp_init(6 downto 5), + O(3 downto 0) => one_dec_max_limit_nxt(8 downto 5), + S(3) => \one_dec_max_limit[8]_i_2_n_0\, + S(2) => device_temp_init(7), + S(1) => \one_dec_max_limit[8]_i_3_n_0\, + S(0) => \one_dec_max_limit[8]_i_4_n_0\ + ); +\one_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit_nxt(9), + Q => one_dec_max_limit(9), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(11), + O => \one_dec_min_limit[11]_i_2_n_0\ + ); +\one_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(10), + O => \one_dec_min_limit[11]_i_3_n_0\ + ); +\one_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(5), + O => \one_dec_min_limit[5]_i_2_n_0\ + ); +\one_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(4), + O => \one_dec_min_limit[5]_i_3_n_0\ + ); +\one_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(3), + O => \one_dec_min_limit[5]_i_4_n_0\ + ); +\one_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(9), + O => \one_dec_min_limit[9]_i_2_n_0\ + ); +\one_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(8), + O => \one_dec_min_limit[9]_i_3_n_0\ + ); +\one_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(7), + O => \one_dec_min_limit[9]_i_4_n_0\ + ); +\one_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => neutral_max_limit(6), + O => \one_dec_min_limit[9]_i_5_n_0\ + ); +\one_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(10), + Q => one_dec_min_limit(10), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(11), + Q => one_dec_min_limit(11), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_dec_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \one_dec_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => neutral_max_limit(10), + O(3 downto 2) => \NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => one_dec_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \one_dec_min_limit[11]_i_2_n_0\, + S(0) => \one_dec_min_limit[11]_i_3_n_0\ + ); +\one_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(2), + Q => one_dec_min_limit(2), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(3), + Q => one_dec_min_limit(3), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(4), + Q => one_dec_min_limit(4), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(5), + Q => one_dec_min_limit(5), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \one_dec_min_limit_reg[5]_i_1_n_0\, + CO(2) => \one_dec_min_limit_reg[5]_i_1_n_1\, + CO(1) => \one_dec_min_limit_reg[5]_i_1_n_2\, + CO(0) => \one_dec_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => neutral_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => one_dec_min_limit_nxt(5 downto 2), + S(3) => \one_dec_min_limit[5]_i_2_n_0\, + S(2) => \one_dec_min_limit[5]_i_3_n_0\, + S(1) => \one_dec_min_limit[5]_i_4_n_0\, + S(0) => neutral_max_limit(2) + ); +\one_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(6), + Q => one_dec_min_limit(6), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(7), + Q => one_dec_min_limit(7), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(8), + Q => one_dec_min_limit(8), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_min_limit_nxt(9), + Q => one_dec_min_limit(9), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_dec_min_limit_reg[5]_i_1_n_0\, + CO(3) => \one_dec_min_limit_reg[9]_i_1_n_0\, + CO(2) => \one_dec_min_limit_reg[9]_i_1_n_1\, + CO(1) => \one_dec_min_limit_reg[9]_i_1_n_2\, + CO(0) => \one_dec_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => neutral_max_limit(9 downto 6), + O(3 downto 0) => one_dec_min_limit_nxt(9 downto 6), + S(3) => \one_dec_min_limit[9]_i_2_n_0\, + S(2) => \one_dec_min_limit[9]_i_3_n_0\, + S(1) => \one_dec_min_limit[9]_i_4_n_0\, + S(0) => \one_dec_min_limit[9]_i_5_n_0\ + ); +\one_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(11), + O => \one_inc_max_limit[11]_i_2_n_0\ + ); +\one_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(10), + O => \one_inc_max_limit[11]_i_3_n_0\ + ); +\one_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(9), + O => \one_inc_max_limit[11]_i_4_n_0\ + ); +\one_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(3), + O => \one_inc_max_limit[4]_i_2_n_0\ + ); +\one_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(8), + O => \one_inc_max_limit[8]_i_2_n_0\ + ); +\one_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(7), + O => \one_inc_max_limit[8]_i_3_n_0\ + ); +\one_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(10), + Q => one_inc_max_limit(10), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(11), + Q => one_inc_max_limit(11), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_inc_max_limit_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \one_inc_max_limit_reg[11]_i_1_n_2\, + CO(0) => \one_inc_max_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => device_temp_init(10 downto 9), + O(3) => \NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => one_inc_max_limit_nxt(11 downto 9), + S(3) => '0', + S(2) => \one_inc_max_limit[11]_i_2_n_0\, + S(1) => \one_inc_max_limit[11]_i_3_n_0\, + S(0) => \one_inc_max_limit[11]_i_4_n_0\ + ); +\one_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(2), + Q => one_inc_max_limit(2), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(3), + Q => one_inc_max_limit(3), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(4), + Q => one_inc_max_limit(4), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \one_inc_max_limit_reg[4]_i_1_n_0\, + CO(2) => \one_inc_max_limit_reg[4]_i_1_n_1\, + CO(1) => \one_inc_max_limit_reg[4]_i_1_n_2\, + CO(0) => \one_inc_max_limit_reg[4]_i_1_n_3\, + CYINIT => device_temp_init(0), + DI(3) => '0', + DI(2) => device_temp_init(3), + DI(1 downto 0) => B"00", + O(3 downto 1) => one_inc_max_limit_nxt(4 downto 2), + O(0) => \NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0), + S(3) => device_temp_init(4), + S(2) => \one_inc_max_limit[4]_i_2_n_0\, + S(1 downto 0) => device_temp_init(2 downto 1) + ); +\one_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(5), + Q => one_inc_max_limit(5), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(6), + Q => one_inc_max_limit(6), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(7), + Q => one_inc_max_limit(7), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(8), + Q => one_inc_max_limit(8), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_inc_max_limit_reg[4]_i_1_n_0\, + CO(3) => \one_inc_max_limit_reg[8]_i_1_n_0\, + CO(2) => \one_inc_max_limit_reg[8]_i_1_n_1\, + CO(1) => \one_inc_max_limit_reg[8]_i_1_n_2\, + CO(0) => \one_inc_max_limit_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => device_temp_init(8 downto 7), + DI(1 downto 0) => B"00", + O(3 downto 0) => one_inc_max_limit_nxt(8 downto 5), + S(3) => \one_inc_max_limit[8]_i_2_n_0\, + S(2) => \one_inc_max_limit[8]_i_3_n_0\, + S(1 downto 0) => device_temp_init(6 downto 5) + ); +\one_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_max_limit_nxt(9), + Q => one_inc_max_limit(9), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\one_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(11), + O => \one_inc_min_limit[11]_i_2_n_0\ + ); +\one_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(10), + O => \one_inc_min_limit[11]_i_3_n_0\ + ); +\one_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(5), + O => \one_inc_min_limit[5]_i_2_n_0\ + ); +\one_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(4), + O => \one_inc_min_limit[5]_i_3_n_0\ + ); +\one_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(3), + O => \one_inc_min_limit[5]_i_4_n_0\ + ); +\one_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(9), + O => \one_inc_min_limit[9]_i_2_n_0\ + ); +\one_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(8), + O => \one_inc_min_limit[9]_i_3_n_0\ + ); +\one_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(7), + O => \one_inc_min_limit[9]_i_4_n_0\ + ); +\one_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_inc_max_limit(6), + O => \one_inc_min_limit[9]_i_5_n_0\ + ); +\one_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(10), + Q => one_inc_min_limit(10), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(11), + Q => one_inc_min_limit(11), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_inc_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \one_inc_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => two_inc_max_limit(10), + O(3 downto 2) => \NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => one_inc_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \one_inc_min_limit[11]_i_2_n_0\, + S(0) => \one_inc_min_limit[11]_i_3_n_0\ + ); +\one_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(2), + Q => one_inc_min_limit(2), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(3), + Q => one_inc_min_limit(3), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(4), + Q => one_inc_min_limit(4), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(5), + Q => one_inc_min_limit(5), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \one_inc_min_limit_reg[5]_i_1_n_0\, + CO(2) => \one_inc_min_limit_reg[5]_i_1_n_1\, + CO(1) => \one_inc_min_limit_reg[5]_i_1_n_2\, + CO(0) => \one_inc_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => two_inc_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => one_inc_min_limit_nxt(5 downto 2), + S(3) => \one_inc_min_limit[5]_i_2_n_0\, + S(2) => \one_inc_min_limit[5]_i_3_n_0\, + S(1) => \one_inc_min_limit[5]_i_4_n_0\, + S(0) => two_inc_max_limit(2) + ); +\one_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(6), + Q => one_inc_min_limit(6), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(7), + Q => one_inc_min_limit(7), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(8), + Q => one_inc_min_limit(8), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_inc_min_limit_nxt(9), + Q => one_inc_min_limit(9), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\one_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \one_inc_min_limit_reg[5]_i_1_n_0\, + CO(3) => \one_inc_min_limit_reg[9]_i_1_n_0\, + CO(2) => \one_inc_min_limit_reg[9]_i_1_n_1\, + CO(1) => \one_inc_min_limit_reg[9]_i_1_n_2\, + CO(0) => \one_inc_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => two_inc_max_limit(9 downto 6), + O(3 downto 0) => one_inc_min_limit_nxt(9 downto 6), + S(3) => \one_inc_min_limit[9]_i_2_n_0\, + S(2) => \one_inc_min_limit[9]_i_3_n_0\, + S(1) => \one_inc_min_limit[9]_i_4_n_0\, + S(0) => \one_inc_min_limit[9]_i_5_n_0\ + ); +pi_f_dec_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"8A88" + ) + port map ( + I0 => \tempmon_state[10]_i_6_n_0\, + I1 => \tempmon_state[10]_i_5_n_0\, + I2 => pi_f_dec_i_2_n_0, + I3 => update_temp_102, + O => pi_f_dec_nxt + ); +pi_f_dec_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000077707770777" + ) + port map ( + I0 => tempmon_state(3), + I1 => temp_cmp_three_inc_max_102, + I2 => temp_cmp_two_inc_max_102, + I3 => tempmon_state(4), + I4 => temp_cmp_one_inc_max_102, + I5 => tempmon_state(5), + O => pi_f_dec_i_2_n_0 + ); +pi_f_dec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_f_dec_nxt, + Q => \^pi_f_dec_reg_0\, + R => pi_f_dec_reg_1 + ); +pi_f_inc_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF7555500000000" + ) + port map ( + I0 => pi_f_inc_i_2_n_0, + I1 => pi_f_inc_i_3_n_0, + I2 => pi_f_inc_i_4_n_0, + I3 => pi_f_inc_i_5_n_0, + I4 => update_temp_102, + I5 => \tempmon_state[10]_i_6_n_0\, + O => pi_f_inc_nxt + ); +pi_f_inc_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FFF7FFF7FFF7FF" + ) + port map ( + I0 => temp_cmp_one_inc_min_102, + I1 => tempmon_state(5), + I2 => temp_cmp_one_inc_max_102, + I3 => update_temp_102, + I4 => temp_cmp_four_dec_min_102, + I5 => tempmon_state(10), + O => pi_f_inc_i_2_n_0 + ); +pi_f_inc_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"F7000000F777F777" + ) + port map ( + I0 => tempmon_state(8), + I1 => temp_cmp_two_dec_min_102, + I2 => temp_cmp_two_dec_max_102, + I3 => update_temp_102, + I4 => temp_cmp_one_dec_max_102, + I5 => pi_f_inc_i_6_n_0, + O => pi_f_inc_i_3_n_0 + ); +pi_f_inc_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"40FF404040404040" + ) + port map ( + I0 => temp_cmp_three_inc_max_102, + I1 => tempmon_state(3), + I2 => temp_cmp_three_inc_min_102, + I3 => temp_cmp_two_inc_max_102, + I4 => tempmon_state(4), + I5 => temp_cmp_two_inc_min_102, + O => pi_f_inc_i_4_n_0 + ); +pi_f_inc_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"0808FF88FF08FF88" + ) + port map ( + I0 => tempmon_state(9), + I1 => temp_cmp_three_dec_min_102, + I2 => temp_cmp_three_dec_max_102, + I3 => pi_f_inc_i_7_n_0, + I4 => update_temp_102, + I5 => temp_cmp_neutral_max_102, + O => pi_f_inc_i_5_n_0 + ); +pi_f_inc_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => tempmon_state(7), + I1 => temp_cmp_one_dec_min_102, + O => pi_f_inc_i_6_n_0 + ); +pi_f_inc_i_7: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => tempmon_state(6), + I1 => temp_cmp_neutral_min_102, + O => pi_f_inc_i_7_n_0 + ); +pi_f_inc_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pi_f_inc_nxt, + Q => \^pi_f_inc_reg_0\, + R => \four_inc_max_limit_reg[2]_0\ + ); +temp_cmp_four_dec_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => four_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => four_dec_min_limit(1), + O => temp_cmp_four_dec_min_102_i_10_n_0 + ); +temp_cmp_four_dec_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => four_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => four_dec_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_four_dec_min_102_i_11_n_0 + ); +temp_cmp_four_dec_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => four_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => four_dec_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_four_dec_min_102_i_12_n_0 + ); +temp_cmp_four_dec_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => four_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => four_dec_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_four_dec_min_102_i_13_n_0 + ); +temp_cmp_four_dec_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => four_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => four_dec_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_four_dec_min_102_i_14_n_0 + ); +temp_cmp_four_dec_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => four_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => four_dec_min_limit(11), + O => temp_cmp_four_dec_min_102_i_3_n_0 + ); +temp_cmp_four_dec_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => four_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => four_dec_min_limit(9), + O => temp_cmp_four_dec_min_102_i_4_n_0 + ); +temp_cmp_four_dec_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => four_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => four_dec_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_four_dec_min_102_i_5_n_0 + ); +temp_cmp_four_dec_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => four_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => four_dec_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_four_dec_min_102_i_6_n_0 + ); +temp_cmp_four_dec_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => four_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => four_dec_min_limit(7), + O => temp_cmp_four_dec_min_102_i_7_n_0 + ); +temp_cmp_four_dec_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => four_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => four_dec_min_limit(5), + O => temp_cmp_four_dec_min_102_i_8_n_0 + ); +temp_cmp_four_dec_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => four_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => four_dec_min_limit(3), + O => temp_cmp_four_dec_min_102_i_9_n_0 + ); +temp_cmp_four_dec_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_four_dec_min_101, + Q => temp_cmp_four_dec_min_102, + R => '0' + ); +temp_cmp_four_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_four_dec_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_four_dec_min_101, + CO(0) => temp_cmp_four_dec_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_four_dec_min_102_i_3_n_0, + DI(0) => temp_cmp_four_dec_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_four_dec_min_102_i_5_n_0, + S(0) => temp_cmp_four_dec_min_102_i_6_n_0 + ); +temp_cmp_four_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_four_dec_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_four_dec_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_four_dec_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_four_dec_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_four_dec_min_102_i_7_n_0, + DI(2) => temp_cmp_four_dec_min_102_i_8_n_0, + DI(1) => temp_cmp_four_dec_min_102_i_9_n_0, + DI(0) => temp_cmp_four_dec_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_four_dec_min_102_i_11_n_0, + S(2) => temp_cmp_four_dec_min_102_i_12_n_0, + S(1) => temp_cmp_four_dec_min_102_i_13_n_0, + S(0) => temp_cmp_four_dec_min_102_i_14_n_0 + ); +temp_cmp_four_inc_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => neutral_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_four_inc_max_102_i_10_n_0 + ); +temp_cmp_four_inc_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => four_inc_max_limit(6), + I2 => device_temp_101(7), + I3 => four_inc_max_limit(7), + O => temp_cmp_four_inc_max_102_i_11_n_0 + ); +temp_cmp_four_inc_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => four_inc_max_limit(4), + I2 => device_temp_101(5), + I3 => four_inc_max_limit(5), + O => temp_cmp_four_inc_max_102_i_12_n_0 + ); +temp_cmp_four_inc_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => four_inc_max_limit(2), + I2 => device_temp_101(3), + I3 => four_inc_max_limit(3), + O => temp_cmp_four_inc_max_102_i_13_n_0 + ); +temp_cmp_four_inc_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => neutral_max_limit(1), + O => temp_cmp_four_inc_max_102_i_14_n_0 + ); +temp_cmp_four_inc_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => four_inc_max_limit(10), + I2 => four_inc_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_four_inc_max_102_i_3_n_0 + ); +temp_cmp_four_inc_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => four_inc_max_limit(8), + I2 => four_inc_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_four_inc_max_102_i_4_n_0 + ); +temp_cmp_four_inc_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => four_inc_max_limit(10), + I2 => device_temp_101(11), + I3 => four_inc_max_limit(11), + O => temp_cmp_four_inc_max_102_i_5_n_0 + ); +temp_cmp_four_inc_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => four_inc_max_limit(8), + I2 => device_temp_101(9), + I3 => four_inc_max_limit(9), + O => temp_cmp_four_inc_max_102_i_6_n_0 + ); +temp_cmp_four_inc_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => four_inc_max_limit(6), + I2 => four_inc_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_four_inc_max_102_i_7_n_0 + ); +temp_cmp_four_inc_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => four_inc_max_limit(4), + I2 => four_inc_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_four_inc_max_102_i_8_n_0 + ); +temp_cmp_four_inc_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => four_inc_max_limit(2), + I2 => four_inc_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_four_inc_max_102_i_9_n_0 + ); +temp_cmp_four_inc_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_four_inc_max_101, + Q => temp_cmp_four_inc_max_102, + R => '0' + ); +temp_cmp_four_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_four_inc_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_four_inc_max_101, + CO(0) => temp_cmp_four_inc_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_four_inc_max_102_i_3_n_0, + DI(0) => temp_cmp_four_inc_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_four_inc_max_102_i_5_n_0, + S(0) => temp_cmp_four_inc_max_102_i_6_n_0 + ); +temp_cmp_four_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_four_inc_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_four_inc_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_four_inc_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_four_inc_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_four_inc_max_102_i_7_n_0, + DI(2) => temp_cmp_four_inc_max_102_i_8_n_0, + DI(1) => temp_cmp_four_inc_max_102_i_9_n_0, + DI(0) => temp_cmp_four_inc_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_four_inc_max_102_i_11_n_0, + S(2) => temp_cmp_four_inc_max_102_i_12_n_0, + S(1) => temp_cmp_four_inc_max_102_i_13_n_0, + S(0) => temp_cmp_four_inc_max_102_i_14_n_0 + ); +temp_cmp_neutral_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => neutral_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_neutral_max_102_i_10_n_0 + ); +temp_cmp_neutral_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => neutral_max_limit(6), + I2 => device_temp_101(7), + I3 => neutral_max_limit(7), + O => temp_cmp_neutral_max_102_i_11_n_0 + ); +temp_cmp_neutral_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => neutral_max_limit(4), + I2 => device_temp_101(5), + I3 => neutral_max_limit(5), + O => temp_cmp_neutral_max_102_i_12_n_0 + ); +temp_cmp_neutral_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => neutral_max_limit(2), + I2 => device_temp_101(3), + I3 => neutral_max_limit(3), + O => temp_cmp_neutral_max_102_i_13_n_0 + ); +temp_cmp_neutral_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => neutral_max_limit(1), + O => temp_cmp_neutral_max_102_i_14_n_0 + ); +temp_cmp_neutral_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => neutral_max_limit(10), + I2 => neutral_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_neutral_max_102_i_3_n_0 + ); +temp_cmp_neutral_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => neutral_max_limit(8), + I2 => neutral_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_neutral_max_102_i_4_n_0 + ); +temp_cmp_neutral_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => neutral_max_limit(10), + I2 => device_temp_101(11), + I3 => neutral_max_limit(11), + O => temp_cmp_neutral_max_102_i_5_n_0 + ); +temp_cmp_neutral_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => neutral_max_limit(8), + I2 => device_temp_101(9), + I3 => neutral_max_limit(9), + O => temp_cmp_neutral_max_102_i_6_n_0 + ); +temp_cmp_neutral_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => neutral_max_limit(6), + I2 => neutral_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_neutral_max_102_i_7_n_0 + ); +temp_cmp_neutral_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => neutral_max_limit(4), + I2 => neutral_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_neutral_max_102_i_8_n_0 + ); +temp_cmp_neutral_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => neutral_max_limit(2), + I2 => neutral_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_neutral_max_102_i_9_n_0 + ); +temp_cmp_neutral_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_neutral_max_101, + Q => temp_cmp_neutral_max_102, + R => '0' + ); +temp_cmp_neutral_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_neutral_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_neutral_max_101, + CO(0) => temp_cmp_neutral_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_neutral_max_102_i_3_n_0, + DI(0) => temp_cmp_neutral_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_neutral_max_102_i_5_n_0, + S(0) => temp_cmp_neutral_max_102_i_6_n_0 + ); +temp_cmp_neutral_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_neutral_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_neutral_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_neutral_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_neutral_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_neutral_max_102_i_7_n_0, + DI(2) => temp_cmp_neutral_max_102_i_8_n_0, + DI(1) => temp_cmp_neutral_max_102_i_9_n_0, + DI(0) => temp_cmp_neutral_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_neutral_max_102_i_11_n_0, + S(2) => temp_cmp_neutral_max_102_i_12_n_0, + S(1) => temp_cmp_neutral_max_102_i_13_n_0, + S(0) => temp_cmp_neutral_max_102_i_14_n_0 + ); +temp_cmp_neutral_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => two_inc_min_limit(1), + O => temp_cmp_neutral_min_102_i_10_n_0 + ); +temp_cmp_neutral_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => neutral_min_limit(6), + I1 => device_temp_101(6), + I2 => neutral_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_neutral_min_102_i_11_n_0 + ); +temp_cmp_neutral_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => neutral_min_limit(4), + I1 => device_temp_101(4), + I2 => neutral_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_neutral_min_102_i_12_n_0 + ); +temp_cmp_neutral_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => neutral_min_limit(2), + I1 => device_temp_101(2), + I2 => neutral_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_neutral_min_102_i_13_n_0 + ); +temp_cmp_neutral_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => two_inc_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_neutral_min_102_i_14_n_0 + ); +temp_cmp_neutral_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => neutral_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => neutral_min_limit(11), + O => temp_cmp_neutral_min_102_i_3_n_0 + ); +temp_cmp_neutral_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => neutral_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => neutral_min_limit(9), + O => temp_cmp_neutral_min_102_i_4_n_0 + ); +temp_cmp_neutral_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => neutral_min_limit(10), + I1 => device_temp_101(10), + I2 => neutral_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_neutral_min_102_i_5_n_0 + ); +temp_cmp_neutral_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => neutral_min_limit(8), + I1 => device_temp_101(8), + I2 => neutral_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_neutral_min_102_i_6_n_0 + ); +temp_cmp_neutral_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => neutral_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => neutral_min_limit(7), + O => temp_cmp_neutral_min_102_i_7_n_0 + ); +temp_cmp_neutral_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => neutral_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => neutral_min_limit(5), + O => temp_cmp_neutral_min_102_i_8_n_0 + ); +temp_cmp_neutral_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => neutral_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => neutral_min_limit(3), + O => temp_cmp_neutral_min_102_i_9_n_0 + ); +temp_cmp_neutral_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_neutral_min_101, + Q => temp_cmp_neutral_min_102, + R => '0' + ); +temp_cmp_neutral_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_neutral_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_neutral_min_101, + CO(0) => temp_cmp_neutral_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_neutral_min_102_i_3_n_0, + DI(0) => temp_cmp_neutral_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_neutral_min_102_i_5_n_0, + S(0) => temp_cmp_neutral_min_102_i_6_n_0 + ); +temp_cmp_neutral_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_neutral_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_neutral_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_neutral_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_neutral_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_neutral_min_102_i_7_n_0, + DI(2) => temp_cmp_neutral_min_102_i_8_n_0, + DI(1) => temp_cmp_neutral_min_102_i_9_n_0, + DI(0) => temp_cmp_neutral_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_neutral_min_102_i_11_n_0, + S(2) => temp_cmp_neutral_min_102_i_12_n_0, + S(1) => temp_cmp_neutral_min_102_i_13_n_0, + S(0) => temp_cmp_neutral_min_102_i_14_n_0 + ); +temp_cmp_one_dec_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => one_dec_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_one_dec_max_102_i_10_n_0 + ); +temp_cmp_one_dec_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => one_dec_max_limit(6), + I2 => device_temp_101(7), + I3 => one_dec_max_limit(7), + O => temp_cmp_one_dec_max_102_i_11_n_0 + ); +temp_cmp_one_dec_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => one_dec_max_limit(4), + I2 => device_temp_101(5), + I3 => one_dec_max_limit(5), + O => temp_cmp_one_dec_max_102_i_12_n_0 + ); +temp_cmp_one_dec_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => one_dec_max_limit(2), + I2 => device_temp_101(3), + I3 => one_dec_max_limit(3), + O => temp_cmp_one_dec_max_102_i_13_n_0 + ); +temp_cmp_one_dec_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => one_dec_max_limit(1), + O => temp_cmp_one_dec_max_102_i_14_n_0 + ); +temp_cmp_one_dec_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => one_dec_max_limit(10), + I2 => one_dec_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_one_dec_max_102_i_3_n_0 + ); +temp_cmp_one_dec_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => one_dec_max_limit(8), + I2 => one_dec_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_one_dec_max_102_i_4_n_0 + ); +temp_cmp_one_dec_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => one_dec_max_limit(10), + I2 => device_temp_101(11), + I3 => one_dec_max_limit(11), + O => temp_cmp_one_dec_max_102_i_5_n_0 + ); +temp_cmp_one_dec_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => one_dec_max_limit(8), + I2 => device_temp_101(9), + I3 => one_dec_max_limit(9), + O => temp_cmp_one_dec_max_102_i_6_n_0 + ); +temp_cmp_one_dec_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => one_dec_max_limit(6), + I2 => one_dec_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_one_dec_max_102_i_7_n_0 + ); +temp_cmp_one_dec_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => one_dec_max_limit(4), + I2 => one_dec_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_one_dec_max_102_i_8_n_0 + ); +temp_cmp_one_dec_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => one_dec_max_limit(2), + I2 => one_dec_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_one_dec_max_102_i_9_n_0 + ); +temp_cmp_one_dec_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_one_dec_max_101, + Q => temp_cmp_one_dec_max_102, + R => '0' + ); +temp_cmp_one_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_one_dec_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_one_dec_max_101, + CO(0) => temp_cmp_one_dec_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_one_dec_max_102_i_3_n_0, + DI(0) => temp_cmp_one_dec_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_one_dec_max_102_i_5_n_0, + S(0) => temp_cmp_one_dec_max_102_i_6_n_0 + ); +temp_cmp_one_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_one_dec_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_one_dec_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_one_dec_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_one_dec_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_one_dec_max_102_i_7_n_0, + DI(2) => temp_cmp_one_dec_max_102_i_8_n_0, + DI(1) => temp_cmp_one_dec_max_102_i_9_n_0, + DI(0) => temp_cmp_one_dec_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_one_dec_max_102_i_11_n_0, + S(2) => temp_cmp_one_dec_max_102_i_12_n_0, + S(1) => temp_cmp_one_dec_max_102_i_13_n_0, + S(0) => temp_cmp_one_dec_max_102_i_14_n_0 + ); +temp_cmp_one_dec_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => three_inc_min_limit(1), + O => temp_cmp_one_dec_min_102_i_10_n_0 + ); +temp_cmp_one_dec_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => one_dec_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_one_dec_min_102_i_11_n_0 + ); +temp_cmp_one_dec_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => one_dec_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_one_dec_min_102_i_12_n_0 + ); +temp_cmp_one_dec_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => one_dec_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_one_dec_min_102_i_13_n_0 + ); +temp_cmp_one_dec_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => three_inc_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_one_dec_min_102_i_14_n_0 + ); +temp_cmp_one_dec_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => one_dec_min_limit(11), + O => temp_cmp_one_dec_min_102_i_3_n_0 + ); +temp_cmp_one_dec_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => one_dec_min_limit(9), + O => temp_cmp_one_dec_min_102_i_4_n_0 + ); +temp_cmp_one_dec_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => one_dec_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_one_dec_min_102_i_5_n_0 + ); +temp_cmp_one_dec_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => one_dec_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_one_dec_min_102_i_6_n_0 + ); +temp_cmp_one_dec_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => one_dec_min_limit(7), + O => temp_cmp_one_dec_min_102_i_7_n_0 + ); +temp_cmp_one_dec_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => one_dec_min_limit(5), + O => temp_cmp_one_dec_min_102_i_8_n_0 + ); +temp_cmp_one_dec_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => one_dec_min_limit(3), + O => temp_cmp_one_dec_min_102_i_9_n_0 + ); +temp_cmp_one_dec_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_one_dec_min_101, + Q => temp_cmp_one_dec_min_102, + R => '0' + ); +temp_cmp_one_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_one_dec_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_one_dec_min_101, + CO(0) => temp_cmp_one_dec_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_one_dec_min_102_i_3_n_0, + DI(0) => temp_cmp_one_dec_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_one_dec_min_102_i_5_n_0, + S(0) => temp_cmp_one_dec_min_102_i_6_n_0 + ); +temp_cmp_one_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_one_dec_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_one_dec_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_one_dec_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_one_dec_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_one_dec_min_102_i_7_n_0, + DI(2) => temp_cmp_one_dec_min_102_i_8_n_0, + DI(1) => temp_cmp_one_dec_min_102_i_9_n_0, + DI(0) => temp_cmp_one_dec_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_one_dec_min_102_i_11_n_0, + S(2) => temp_cmp_one_dec_min_102_i_12_n_0, + S(1) => temp_cmp_one_dec_min_102_i_13_n_0, + S(0) => temp_cmp_one_dec_min_102_i_14_n_0 + ); +temp_cmp_one_inc_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => one_dec_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_one_inc_max_102_i_10_n_0 + ); +temp_cmp_one_inc_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => one_inc_max_limit(6), + I2 => device_temp_101(7), + I3 => one_inc_max_limit(7), + O => temp_cmp_one_inc_max_102_i_11_n_0 + ); +temp_cmp_one_inc_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => one_inc_max_limit(4), + I2 => device_temp_101(5), + I3 => one_inc_max_limit(5), + O => temp_cmp_one_inc_max_102_i_12_n_0 + ); +temp_cmp_one_inc_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => one_inc_max_limit(2), + I2 => device_temp_101(3), + I3 => one_inc_max_limit(3), + O => temp_cmp_one_inc_max_102_i_13_n_0 + ); +temp_cmp_one_inc_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => one_dec_max_limit(1), + O => temp_cmp_one_inc_max_102_i_14_n_0 + ); +temp_cmp_one_inc_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => one_inc_max_limit(10), + I2 => one_inc_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_one_inc_max_102_i_3_n_0 + ); +temp_cmp_one_inc_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => one_inc_max_limit(8), + I2 => one_inc_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_one_inc_max_102_i_4_n_0 + ); +temp_cmp_one_inc_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => one_inc_max_limit(10), + I2 => device_temp_101(11), + I3 => one_inc_max_limit(11), + O => temp_cmp_one_inc_max_102_i_5_n_0 + ); +temp_cmp_one_inc_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => one_inc_max_limit(8), + I2 => device_temp_101(9), + I3 => one_inc_max_limit(9), + O => temp_cmp_one_inc_max_102_i_6_n_0 + ); +temp_cmp_one_inc_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => one_inc_max_limit(6), + I2 => one_inc_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_one_inc_max_102_i_7_n_0 + ); +temp_cmp_one_inc_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => one_inc_max_limit(4), + I2 => one_inc_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_one_inc_max_102_i_8_n_0 + ); +temp_cmp_one_inc_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => one_inc_max_limit(2), + I2 => one_inc_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_one_inc_max_102_i_9_n_0 + ); +temp_cmp_one_inc_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_one_inc_max_101, + Q => temp_cmp_one_inc_max_102, + R => '0' + ); +temp_cmp_one_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_one_inc_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_one_inc_max_101, + CO(0) => temp_cmp_one_inc_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_one_inc_max_102_i_3_n_0, + DI(0) => temp_cmp_one_inc_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_one_inc_max_102_i_5_n_0, + S(0) => temp_cmp_one_inc_max_102_i_6_n_0 + ); +temp_cmp_one_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_one_inc_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_one_inc_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_one_inc_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_one_inc_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_one_inc_max_102_i_7_n_0, + DI(2) => temp_cmp_one_inc_max_102_i_8_n_0, + DI(1) => temp_cmp_one_inc_max_102_i_9_n_0, + DI(0) => temp_cmp_one_inc_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_one_inc_max_102_i_11_n_0, + S(2) => temp_cmp_one_inc_max_102_i_12_n_0, + S(1) => temp_cmp_one_inc_max_102_i_13_n_0, + S(0) => temp_cmp_one_inc_max_102_i_14_n_0 + ); +temp_cmp_one_inc_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => three_inc_min_limit(1), + O => temp_cmp_one_inc_min_102_i_10_n_0 + ); +temp_cmp_one_inc_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_inc_min_limit(6), + I1 => device_temp_101(6), + I2 => one_inc_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_one_inc_min_102_i_11_n_0 + ); +temp_cmp_one_inc_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_inc_min_limit(4), + I1 => device_temp_101(4), + I2 => one_inc_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_one_inc_min_102_i_12_n_0 + ); +temp_cmp_one_inc_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_inc_min_limit(2), + I1 => device_temp_101(2), + I2 => one_inc_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_one_inc_min_102_i_13_n_0 + ); +temp_cmp_one_inc_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => three_inc_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_one_inc_min_102_i_14_n_0 + ); +temp_cmp_one_inc_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_inc_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => one_inc_min_limit(11), + O => temp_cmp_one_inc_min_102_i_3_n_0 + ); +temp_cmp_one_inc_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_inc_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => one_inc_min_limit(9), + O => temp_cmp_one_inc_min_102_i_4_n_0 + ); +temp_cmp_one_inc_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_inc_min_limit(10), + I1 => device_temp_101(10), + I2 => one_inc_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_one_inc_min_102_i_5_n_0 + ); +temp_cmp_one_inc_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => one_inc_min_limit(8), + I1 => device_temp_101(8), + I2 => one_inc_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_one_inc_min_102_i_6_n_0 + ); +temp_cmp_one_inc_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_inc_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => one_inc_min_limit(7), + O => temp_cmp_one_inc_min_102_i_7_n_0 + ); +temp_cmp_one_inc_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_inc_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => one_inc_min_limit(5), + O => temp_cmp_one_inc_min_102_i_8_n_0 + ); +temp_cmp_one_inc_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => one_inc_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => one_inc_min_limit(3), + O => temp_cmp_one_inc_min_102_i_9_n_0 + ); +temp_cmp_one_inc_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_one_inc_min_101, + Q => temp_cmp_one_inc_min_102, + R => '0' + ); +temp_cmp_one_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_one_inc_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_one_inc_min_101, + CO(0) => temp_cmp_one_inc_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_one_inc_min_102_i_3_n_0, + DI(0) => temp_cmp_one_inc_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_one_inc_min_102_i_5_n_0, + S(0) => temp_cmp_one_inc_min_102_i_6_n_0 + ); +temp_cmp_one_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_one_inc_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_one_inc_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_one_inc_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_one_inc_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_one_inc_min_102_i_7_n_0, + DI(2) => temp_cmp_one_inc_min_102_i_8_n_0, + DI(1) => temp_cmp_one_inc_min_102_i_9_n_0, + DI(0) => temp_cmp_one_inc_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_one_inc_min_102_i_11_n_0, + S(2) => temp_cmp_one_inc_min_102_i_12_n_0, + S(1) => temp_cmp_one_inc_min_102_i_13_n_0, + S(0) => temp_cmp_one_inc_min_102_i_14_n_0 + ); +temp_cmp_three_dec_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => three_dec_max_limit(0), + I2 => three_dec_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_three_dec_max_102_i_10_n_0 + ); +temp_cmp_three_dec_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => three_dec_max_limit(6), + I2 => device_temp_101(7), + I3 => three_dec_max_limit(7), + O => temp_cmp_three_dec_max_102_i_11_n_0 + ); +temp_cmp_three_dec_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => three_dec_max_limit(4), + I2 => device_temp_101(5), + I3 => three_dec_max_limit(5), + O => temp_cmp_three_dec_max_102_i_12_n_0 + ); +temp_cmp_three_dec_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => three_dec_max_limit(2), + I2 => device_temp_101(3), + I3 => three_dec_max_limit(3), + O => temp_cmp_three_dec_max_102_i_13_n_0 + ); +temp_cmp_three_dec_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => three_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => three_dec_max_limit(1), + O => temp_cmp_three_dec_max_102_i_14_n_0 + ); +temp_cmp_three_dec_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => three_dec_max_limit(10), + I2 => three_dec_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_three_dec_max_102_i_3_n_0 + ); +temp_cmp_three_dec_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => three_dec_max_limit(8), + I2 => three_dec_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_three_dec_max_102_i_4_n_0 + ); +temp_cmp_three_dec_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => three_dec_max_limit(10), + I2 => device_temp_101(11), + I3 => three_dec_max_limit(11), + O => temp_cmp_three_dec_max_102_i_5_n_0 + ); +temp_cmp_three_dec_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => three_dec_max_limit(8), + I2 => device_temp_101(9), + I3 => three_dec_max_limit(9), + O => temp_cmp_three_dec_max_102_i_6_n_0 + ); +temp_cmp_three_dec_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => three_dec_max_limit(6), + I2 => three_dec_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_three_dec_max_102_i_7_n_0 + ); +temp_cmp_three_dec_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => three_dec_max_limit(4), + I2 => three_dec_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_three_dec_max_102_i_8_n_0 + ); +temp_cmp_three_dec_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => three_dec_max_limit(2), + I2 => three_dec_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_three_dec_max_102_i_9_n_0 + ); +temp_cmp_three_dec_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_three_dec_max_101, + Q => temp_cmp_three_dec_max_102, + R => '0' + ); +temp_cmp_three_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_three_dec_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_three_dec_max_101, + CO(0) => temp_cmp_three_dec_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_three_dec_max_102_i_3_n_0, + DI(0) => temp_cmp_three_dec_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_three_dec_max_102_i_5_n_0, + S(0) => temp_cmp_three_dec_max_102_i_6_n_0 + ); +temp_cmp_three_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_three_dec_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_three_dec_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_three_dec_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_three_dec_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_three_dec_max_102_i_7_n_0, + DI(2) => temp_cmp_three_dec_max_102_i_8_n_0, + DI(1) => temp_cmp_three_dec_max_102_i_9_n_0, + DI(0) => temp_cmp_three_dec_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_three_dec_max_102_i_11_n_0, + S(2) => temp_cmp_three_dec_max_102_i_12_n_0, + S(1) => temp_cmp_three_dec_max_102_i_13_n_0, + S(0) => temp_cmp_three_dec_max_102_i_14_n_0 + ); +temp_cmp_three_dec_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => three_dec_min_limit(1), + O => temp_cmp_three_dec_min_102_i_10_n_0 + ); +temp_cmp_three_dec_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => three_dec_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_three_dec_min_102_i_11_n_0 + ); +temp_cmp_three_dec_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => three_dec_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_three_dec_min_102_i_12_n_0 + ); +temp_cmp_three_dec_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => three_dec_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_three_dec_min_102_i_13_n_0 + ); +temp_cmp_three_dec_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => three_dec_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_three_dec_min_102_i_14_n_0 + ); +temp_cmp_three_dec_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => three_dec_min_limit(11), + O => temp_cmp_three_dec_min_102_i_3_n_0 + ); +temp_cmp_three_dec_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => three_dec_min_limit(9), + O => temp_cmp_three_dec_min_102_i_4_n_0 + ); +temp_cmp_three_dec_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => three_dec_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_three_dec_min_102_i_5_n_0 + ); +temp_cmp_three_dec_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => three_dec_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_three_dec_min_102_i_6_n_0 + ); +temp_cmp_three_dec_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => three_dec_min_limit(7), + O => temp_cmp_three_dec_min_102_i_7_n_0 + ); +temp_cmp_three_dec_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => three_dec_min_limit(5), + O => temp_cmp_three_dec_min_102_i_8_n_0 + ); +temp_cmp_three_dec_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => three_dec_min_limit(3), + O => temp_cmp_three_dec_min_102_i_9_n_0 + ); +temp_cmp_three_dec_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_three_dec_min_101, + Q => temp_cmp_three_dec_min_102, + R => '0' + ); +temp_cmp_three_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_three_dec_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_three_dec_min_101, + CO(0) => temp_cmp_three_dec_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_three_dec_min_102_i_3_n_0, + DI(0) => temp_cmp_three_dec_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_three_dec_min_102_i_5_n_0, + S(0) => temp_cmp_three_dec_min_102_i_6_n_0 + ); +temp_cmp_three_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_three_dec_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_three_dec_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_three_dec_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_three_dec_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_three_dec_min_102_i_7_n_0, + DI(2) => temp_cmp_three_dec_min_102_i_8_n_0, + DI(1) => temp_cmp_three_dec_min_102_i_9_n_0, + DI(0) => temp_cmp_three_dec_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_three_dec_min_102_i_11_n_0, + S(2) => temp_cmp_three_dec_min_102_i_12_n_0, + S(1) => temp_cmp_three_dec_min_102_i_13_n_0, + S(0) => temp_cmp_three_dec_min_102_i_14_n_0 + ); +temp_cmp_three_inc_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => one_dec_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_three_inc_max_102_i_10_n_0 + ); +temp_cmp_three_inc_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => three_inc_max_limit(6), + I2 => device_temp_101(7), + I3 => three_inc_max_limit(7), + O => temp_cmp_three_inc_max_102_i_11_n_0 + ); +temp_cmp_three_inc_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => three_inc_max_limit(4), + I2 => device_temp_101(5), + I3 => three_inc_max_limit(5), + O => temp_cmp_three_inc_max_102_i_12_n_0 + ); +temp_cmp_three_inc_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => three_inc_max_limit(2), + I2 => device_temp_101(3), + I3 => three_inc_max_limit(3), + O => temp_cmp_three_inc_max_102_i_13_n_0 + ); +temp_cmp_three_inc_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => one_dec_max_limit(1), + O => temp_cmp_three_inc_max_102_i_14_n_0 + ); +temp_cmp_three_inc_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => three_inc_max_limit(10), + I2 => three_inc_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_three_inc_max_102_i_3_n_0 + ); +temp_cmp_three_inc_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => three_inc_max_limit(8), + I2 => three_inc_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_three_inc_max_102_i_4_n_0 + ); +temp_cmp_three_inc_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => three_inc_max_limit(10), + I2 => device_temp_101(11), + I3 => three_inc_max_limit(11), + O => temp_cmp_three_inc_max_102_i_5_n_0 + ); +temp_cmp_three_inc_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => three_inc_max_limit(8), + I2 => device_temp_101(9), + I3 => three_inc_max_limit(9), + O => temp_cmp_three_inc_max_102_i_6_n_0 + ); +temp_cmp_three_inc_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => three_inc_max_limit(6), + I2 => three_inc_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_three_inc_max_102_i_7_n_0 + ); +temp_cmp_three_inc_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => three_inc_max_limit(4), + I2 => three_inc_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_three_inc_max_102_i_8_n_0 + ); +temp_cmp_three_inc_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => three_inc_max_limit(2), + I2 => three_inc_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_three_inc_max_102_i_9_n_0 + ); +temp_cmp_three_inc_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_three_inc_max_101, + Q => temp_cmp_three_inc_max_102, + R => '0' + ); +temp_cmp_three_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_three_inc_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_three_inc_max_101, + CO(0) => temp_cmp_three_inc_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_three_inc_max_102_i_3_n_0, + DI(0) => temp_cmp_three_inc_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_three_inc_max_102_i_5_n_0, + S(0) => temp_cmp_three_inc_max_102_i_6_n_0 + ); +temp_cmp_three_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_three_inc_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_three_inc_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_three_inc_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_three_inc_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_three_inc_max_102_i_7_n_0, + DI(2) => temp_cmp_three_inc_max_102_i_8_n_0, + DI(1) => temp_cmp_three_inc_max_102_i_9_n_0, + DI(0) => temp_cmp_three_inc_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_three_inc_max_102_i_11_n_0, + S(2) => temp_cmp_three_inc_max_102_i_12_n_0, + S(1) => temp_cmp_three_inc_max_102_i_13_n_0, + S(0) => temp_cmp_three_inc_max_102_i_14_n_0 + ); +temp_cmp_three_inc_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => three_inc_min_limit(1), + O => temp_cmp_three_inc_min_102_i_10_n_0 + ); +temp_cmp_three_inc_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_inc_min_limit(6), + I1 => device_temp_101(6), + I2 => three_inc_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_three_inc_min_102_i_11_n_0 + ); +temp_cmp_three_inc_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_inc_min_limit(4), + I1 => device_temp_101(4), + I2 => three_inc_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_three_inc_min_102_i_12_n_0 + ); +temp_cmp_three_inc_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_inc_min_limit(2), + I1 => device_temp_101(2), + I2 => three_inc_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_three_inc_min_102_i_13_n_0 + ); +temp_cmp_three_inc_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => three_inc_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_three_inc_min_102_i_14_n_0 + ); +temp_cmp_three_inc_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_inc_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => three_inc_min_limit(11), + O => temp_cmp_three_inc_min_102_i_3_n_0 + ); +temp_cmp_three_inc_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_inc_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => three_inc_min_limit(9), + O => temp_cmp_three_inc_min_102_i_4_n_0 + ); +temp_cmp_three_inc_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_inc_min_limit(10), + I1 => device_temp_101(10), + I2 => three_inc_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_three_inc_min_102_i_5_n_0 + ); +temp_cmp_three_inc_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_inc_min_limit(8), + I1 => device_temp_101(8), + I2 => three_inc_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_three_inc_min_102_i_6_n_0 + ); +temp_cmp_three_inc_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_inc_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => three_inc_min_limit(7), + O => temp_cmp_three_inc_min_102_i_7_n_0 + ); +temp_cmp_three_inc_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_inc_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => three_inc_min_limit(5), + O => temp_cmp_three_inc_min_102_i_8_n_0 + ); +temp_cmp_three_inc_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_inc_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => three_inc_min_limit(3), + O => temp_cmp_three_inc_min_102_i_9_n_0 + ); +temp_cmp_three_inc_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_three_inc_min_101, + Q => temp_cmp_three_inc_min_102, + R => '0' + ); +temp_cmp_three_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_three_inc_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_three_inc_min_101, + CO(0) => temp_cmp_three_inc_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_three_inc_min_102_i_3_n_0, + DI(0) => temp_cmp_three_inc_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_three_inc_min_102_i_5_n_0, + S(0) => temp_cmp_three_inc_min_102_i_6_n_0 + ); +temp_cmp_three_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_three_inc_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_three_inc_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_three_inc_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_three_inc_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_three_inc_min_102_i_7_n_0, + DI(2) => temp_cmp_three_inc_min_102_i_8_n_0, + DI(1) => temp_cmp_three_inc_min_102_i_9_n_0, + DI(0) => temp_cmp_three_inc_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_three_inc_min_102_i_11_n_0, + S(2) => temp_cmp_three_inc_min_102_i_12_n_0, + S(1) => temp_cmp_three_inc_min_102_i_13_n_0, + S(0) => temp_cmp_three_inc_min_102_i_14_n_0 + ); +temp_cmp_two_dec_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => two_dec_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_two_dec_max_102_i_10_n_0 + ); +temp_cmp_two_dec_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => two_dec_max_limit(6), + I2 => device_temp_101(7), + I3 => two_dec_max_limit(7), + O => temp_cmp_two_dec_max_102_i_11_n_0 + ); +temp_cmp_two_dec_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => two_dec_max_limit(4), + I2 => device_temp_101(5), + I3 => two_dec_max_limit(5), + O => temp_cmp_two_dec_max_102_i_12_n_0 + ); +temp_cmp_two_dec_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => two_dec_max_limit(2), + I2 => device_temp_101(3), + I3 => two_dec_max_limit(3), + O => temp_cmp_two_dec_max_102_i_13_n_0 + ); +temp_cmp_two_dec_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => two_dec_max_limit(1), + O => temp_cmp_two_dec_max_102_i_14_n_0 + ); +temp_cmp_two_dec_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => two_dec_max_limit(10), + I2 => two_dec_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_two_dec_max_102_i_3_n_0 + ); +temp_cmp_two_dec_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => two_dec_max_limit(8), + I2 => two_dec_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_two_dec_max_102_i_4_n_0 + ); +temp_cmp_two_dec_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => two_dec_max_limit(10), + I2 => device_temp_101(11), + I3 => two_dec_max_limit(11), + O => temp_cmp_two_dec_max_102_i_5_n_0 + ); +temp_cmp_two_dec_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => two_dec_max_limit(8), + I2 => device_temp_101(9), + I3 => two_dec_max_limit(9), + O => temp_cmp_two_dec_max_102_i_6_n_0 + ); +temp_cmp_two_dec_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => two_dec_max_limit(6), + I2 => two_dec_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_two_dec_max_102_i_7_n_0 + ); +temp_cmp_two_dec_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => two_dec_max_limit(4), + I2 => two_dec_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_two_dec_max_102_i_8_n_0 + ); +temp_cmp_two_dec_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => two_dec_max_limit(2), + I2 => two_dec_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_two_dec_max_102_i_9_n_0 + ); +temp_cmp_two_dec_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_two_dec_max_101, + Q => temp_cmp_two_dec_max_102, + R => '0' + ); +temp_cmp_two_dec_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_two_dec_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_two_dec_max_101, + CO(0) => temp_cmp_two_dec_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_two_dec_max_102_i_3_n_0, + DI(0) => temp_cmp_two_dec_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_two_dec_max_102_i_5_n_0, + S(0) => temp_cmp_two_dec_max_102_i_6_n_0 + ); +temp_cmp_two_dec_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_two_dec_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_two_dec_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_two_dec_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_two_dec_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_two_dec_max_102_i_7_n_0, + DI(2) => temp_cmp_two_dec_max_102_i_8_n_0, + DI(1) => temp_cmp_two_dec_max_102_i_9_n_0, + DI(0) => temp_cmp_two_dec_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_two_dec_max_102_i_11_n_0, + S(2) => temp_cmp_two_dec_max_102_i_12_n_0, + S(1) => temp_cmp_two_dec_max_102_i_13_n_0, + S(0) => temp_cmp_two_dec_max_102_i_14_n_0 + ); +temp_cmp_two_dec_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => two_inc_min_limit(1), + O => temp_cmp_two_dec_min_102_i_10_n_0 + ); +temp_cmp_two_dec_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => two_dec_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_two_dec_min_102_i_11_n_0 + ); +temp_cmp_two_dec_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => two_dec_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_two_dec_min_102_i_12_n_0 + ); +temp_cmp_two_dec_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => two_dec_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_two_dec_min_102_i_13_n_0 + ); +temp_cmp_two_dec_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => two_inc_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_two_dec_min_102_i_14_n_0 + ); +temp_cmp_two_dec_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => two_dec_min_limit(11), + O => temp_cmp_two_dec_min_102_i_3_n_0 + ); +temp_cmp_two_dec_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => two_dec_min_limit(9), + O => temp_cmp_two_dec_min_102_i_4_n_0 + ); +temp_cmp_two_dec_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_dec_min_limit(10), + I1 => device_temp_101(10), + I2 => two_dec_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_two_dec_min_102_i_5_n_0 + ); +temp_cmp_two_dec_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_dec_min_limit(8), + I1 => device_temp_101(8), + I2 => two_dec_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_two_dec_min_102_i_6_n_0 + ); +temp_cmp_two_dec_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_dec_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => two_dec_min_limit(7), + O => temp_cmp_two_dec_min_102_i_7_n_0 + ); +temp_cmp_two_dec_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_dec_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => two_dec_min_limit(5), + O => temp_cmp_two_dec_min_102_i_8_n_0 + ); +temp_cmp_two_dec_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_dec_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => two_dec_min_limit(3), + O => temp_cmp_two_dec_min_102_i_9_n_0 + ); +temp_cmp_two_dec_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_two_dec_min_101, + Q => temp_cmp_two_dec_min_102, + R => '0' + ); +temp_cmp_two_dec_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_two_dec_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_two_dec_min_101, + CO(0) => temp_cmp_two_dec_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_two_dec_min_102_i_3_n_0, + DI(0) => temp_cmp_two_dec_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_two_dec_min_102_i_5_n_0, + S(0) => temp_cmp_two_dec_min_102_i_6_n_0 + ); +temp_cmp_two_dec_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_two_dec_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_two_dec_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_two_dec_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_two_dec_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_two_dec_min_102_i_7_n_0, + DI(2) => temp_cmp_two_dec_min_102_i_8_n_0, + DI(1) => temp_cmp_two_dec_min_102_i_9_n_0, + DI(0) => temp_cmp_two_dec_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_two_dec_min_102_i_11_n_0, + S(2) => temp_cmp_two_dec_min_102_i_12_n_0, + S(1) => temp_cmp_two_dec_min_102_i_13_n_0, + S(0) => temp_cmp_two_dec_min_102_i_14_n_0 + ); +temp_cmp_two_inc_max_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => neutral_max_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_two_inc_max_102_i_10_n_0 + ); +temp_cmp_two_inc_max_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(6), + I1 => two_inc_max_limit(6), + I2 => device_temp_101(7), + I3 => two_inc_max_limit(7), + O => temp_cmp_two_inc_max_102_i_11_n_0 + ); +temp_cmp_two_inc_max_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(4), + I1 => two_inc_max_limit(4), + I2 => device_temp_101(5), + I3 => two_inc_max_limit(5), + O => temp_cmp_two_inc_max_102_i_12_n_0 + ); +temp_cmp_two_inc_max_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(2), + I1 => two_inc_max_limit(2), + I2 => device_temp_101(3), + I3 => two_inc_max_limit(3), + O => temp_cmp_two_inc_max_102_i_13_n_0 + ); +temp_cmp_two_inc_max_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(0), + I1 => two_dec_max_limit(0), + I2 => device_temp_101(1), + I3 => neutral_max_limit(1), + O => temp_cmp_two_inc_max_102_i_14_n_0 + ); +temp_cmp_two_inc_max_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(10), + I1 => two_inc_max_limit(10), + I2 => two_inc_max_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_two_inc_max_102_i_3_n_0 + ); +temp_cmp_two_inc_max_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(8), + I1 => two_inc_max_limit(8), + I2 => two_inc_max_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_two_inc_max_102_i_4_n_0 + ); +temp_cmp_two_inc_max_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(10), + I1 => two_inc_max_limit(10), + I2 => device_temp_101(11), + I3 => two_inc_max_limit(11), + O => temp_cmp_two_inc_max_102_i_5_n_0 + ); +temp_cmp_two_inc_max_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => device_temp_101(8), + I1 => two_inc_max_limit(8), + I2 => device_temp_101(9), + I3 => two_inc_max_limit(9), + O => temp_cmp_two_inc_max_102_i_6_n_0 + ); +temp_cmp_two_inc_max_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(6), + I1 => two_inc_max_limit(6), + I2 => two_inc_max_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_two_inc_max_102_i_7_n_0 + ); +temp_cmp_two_inc_max_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(4), + I1 => two_inc_max_limit(4), + I2 => two_inc_max_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_two_inc_max_102_i_8_n_0 + ); +temp_cmp_two_inc_max_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => device_temp_101(2), + I1 => two_inc_max_limit(2), + I2 => two_inc_max_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_two_inc_max_102_i_9_n_0 + ); +temp_cmp_two_inc_max_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_two_inc_max_101, + Q => temp_cmp_two_inc_max_102, + R => '0' + ); +temp_cmp_two_inc_max_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_two_inc_max_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_two_inc_max_101, + CO(0) => temp_cmp_two_inc_max_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_two_inc_max_102_i_3_n_0, + DI(0) => temp_cmp_two_inc_max_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_two_inc_max_102_i_5_n_0, + S(0) => temp_cmp_two_inc_max_102_i_6_n_0 + ); +temp_cmp_two_inc_max_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_two_inc_max_102_reg_i_2_n_0, + CO(2) => temp_cmp_two_inc_max_102_reg_i_2_n_1, + CO(1) => temp_cmp_two_inc_max_102_reg_i_2_n_2, + CO(0) => temp_cmp_two_inc_max_102_reg_i_2_n_3, + CYINIT => '1', + DI(3) => temp_cmp_two_inc_max_102_i_7_n_0, + DI(2) => temp_cmp_two_inc_max_102_i_8_n_0, + DI(1) => temp_cmp_two_inc_max_102_i_9_n_0, + DI(0) => temp_cmp_two_inc_max_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_two_inc_max_102_i_11_n_0, + S(2) => temp_cmp_two_inc_max_102_i_12_n_0, + S(1) => temp_cmp_two_inc_max_102_i_13_n_0, + S(0) => temp_cmp_two_inc_max_102_i_14_n_0 + ); +temp_cmp_two_inc_min_102_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => device_temp_101(1), + I3 => two_inc_min_limit(1), + O => temp_cmp_two_inc_min_102_i_10_n_0 + ); +temp_cmp_two_inc_min_102_i_11: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_inc_min_limit(6), + I1 => device_temp_101(6), + I2 => two_inc_min_limit(7), + I3 => device_temp_101(7), + O => temp_cmp_two_inc_min_102_i_11_n_0 + ); +temp_cmp_two_inc_min_102_i_12: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_inc_min_limit(4), + I1 => device_temp_101(4), + I2 => two_inc_min_limit(5), + I3 => device_temp_101(5), + O => temp_cmp_two_inc_min_102_i_12_n_0 + ); +temp_cmp_two_inc_min_102_i_13: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_inc_min_limit(2), + I1 => device_temp_101(2), + I2 => two_inc_min_limit(3), + I3 => device_temp_101(3), + O => temp_cmp_two_inc_min_102_i_13_n_0 + ); +temp_cmp_two_inc_min_102_i_14: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => three_dec_min_limit(0), + I1 => device_temp_101(0), + I2 => two_inc_min_limit(1), + I3 => device_temp_101(1), + O => temp_cmp_two_inc_min_102_i_14_n_0 + ); +temp_cmp_two_inc_min_102_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_inc_min_limit(10), + I1 => device_temp_101(10), + I2 => device_temp_101(11), + I3 => two_inc_min_limit(11), + O => temp_cmp_two_inc_min_102_i_3_n_0 + ); +temp_cmp_two_inc_min_102_i_4: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_inc_min_limit(8), + I1 => device_temp_101(8), + I2 => device_temp_101(9), + I3 => two_inc_min_limit(9), + O => temp_cmp_two_inc_min_102_i_4_n_0 + ); +temp_cmp_two_inc_min_102_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_inc_min_limit(10), + I1 => device_temp_101(10), + I2 => two_inc_min_limit(11), + I3 => device_temp_101(11), + O => temp_cmp_two_inc_min_102_i_5_n_0 + ); +temp_cmp_two_inc_min_102_i_6: unisim.vcomponents.LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => two_inc_min_limit(8), + I1 => device_temp_101(8), + I2 => two_inc_min_limit(9), + I3 => device_temp_101(9), + O => temp_cmp_two_inc_min_102_i_6_n_0 + ); +temp_cmp_two_inc_min_102_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_inc_min_limit(6), + I1 => device_temp_101(6), + I2 => device_temp_101(7), + I3 => two_inc_min_limit(7), + O => temp_cmp_two_inc_min_102_i_7_n_0 + ); +temp_cmp_two_inc_min_102_i_8: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_inc_min_limit(4), + I1 => device_temp_101(4), + I2 => device_temp_101(5), + I3 => two_inc_min_limit(5), + O => temp_cmp_two_inc_min_102_i_8_n_0 + ); +temp_cmp_two_inc_min_102_i_9: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F02" + ) + port map ( + I0 => two_inc_min_limit(2), + I1 => device_temp_101(2), + I2 => device_temp_101(3), + I3 => two_inc_min_limit(3), + O => temp_cmp_two_inc_min_102_i_9_n_0 + ); +temp_cmp_two_inc_min_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => temp_cmp_two_inc_min_101, + Q => temp_cmp_two_inc_min_102, + R => '0' + ); +temp_cmp_two_inc_min_102_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => temp_cmp_two_inc_min_102_reg_i_2_n_0, + CO(3 downto 2) => NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED(3 downto 2), + CO(1) => temp_cmp_two_inc_min_101, + CO(0) => temp_cmp_two_inc_min_102_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => temp_cmp_two_inc_min_102_i_3_n_0, + DI(0) => temp_cmp_two_inc_min_102_i_4_n_0, + O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3 downto 2) => B"00", + S(1) => temp_cmp_two_inc_min_102_i_5_n_0, + S(0) => temp_cmp_two_inc_min_102_i_6_n_0 + ); +temp_cmp_two_inc_min_102_reg_i_2: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => temp_cmp_two_inc_min_102_reg_i_2_n_0, + CO(2) => temp_cmp_two_inc_min_102_reg_i_2_n_1, + CO(1) => temp_cmp_two_inc_min_102_reg_i_2_n_2, + CO(0) => temp_cmp_two_inc_min_102_reg_i_2_n_3, + CYINIT => '0', + DI(3) => temp_cmp_two_inc_min_102_i_7_n_0, + DI(2) => temp_cmp_two_inc_min_102_i_8_n_0, + DI(1) => temp_cmp_two_inc_min_102_i_9_n_0, + DI(0) => temp_cmp_two_inc_min_102_i_10_n_0, + O(3 downto 0) => NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED(3 downto 0), + S(3) => temp_cmp_two_inc_min_102_i_11_n_0, + S(2) => temp_cmp_two_inc_min_102_i_12_n_0, + S(1) => temp_cmp_two_inc_min_102_i_13_n_0, + S(0) => temp_cmp_two_inc_min_102_i_14_n_0 + ); +tempmon_init_complete_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => tempmon_state_init, + D => tempmon_state_init, + Q => tempmon_init_complete, + R => \four_inc_max_limit_reg[2]_0\ + ); +tempmon_sample_en_101_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_ref_zq_wip, + Q => tempmon_sample_en_101, + R => \four_inc_max_limit_reg[2]_0\ + ); +tempmon_sample_en_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => tempmon_sample_en_101, + Q => tempmon_sample_en_102, + R => \four_dec_min_limit_reg[0]_0\ + ); +\tempmon_state[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \tempmon_state[10]_i_6_n_0\, + O => tempmon_state_nxt(0) + ); +\tempmon_state[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFC444" + ) + port map ( + I0 => \tempmon_state[10]_i_3_n_0\, + I1 => update_temp_102, + I2 => temp_cmp_four_dec_min_102, + I3 => tempmon_state(10), + I4 => \tempmon_state[10]_i_4_n_0\, + I5 => \tempmon_state[10]_i_5_n_0\, + O => \tempmon_state[10]_i_1_n_0\ + ); +\tempmon_state[10]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010116" + ) + port map ( + I0 => tempmon_state(0), + I1 => tempmon_state(1), + I2 => tempmon_state(2), + I3 => tempmon_state(3), + I4 => tempmon_state(4), + O => \tempmon_state[10]_i_10_n_0\ + ); +\tempmon_state[10]_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEFEE8" + ) + port map ( + I0 => tempmon_state(0), + I1 => tempmon_state(1), + I2 => tempmon_state(2), + I3 => tempmon_state(3), + I4 => tempmon_state(4), + O => \tempmon_state[10]_i_11_n_0\ + ); +\tempmon_state[10]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100010116" + ) + port map ( + I0 => tempmon_state(5), + I1 => tempmon_state(6), + I2 => tempmon_state(7), + I3 => tempmon_state(8), + I4 => tempmon_state(9), + I5 => tempmon_state(10), + O => \tempmon_state[10]_i_12_n_0\ + ); +\tempmon_state[10]_i_13\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFEFFFEFEE8" + ) + port map ( + I0 => tempmon_state(5), + I1 => tempmon_state(6), + I2 => tempmon_state(7), + I3 => tempmon_state(8), + I4 => tempmon_state(9), + I5 => tempmon_state(10), + O => \tempmon_state[10]_i_13_n_0\ + ); +\tempmon_state[10]_i_14\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => temp_cmp_two_dec_min_102, + I1 => tempmon_state(8), + I2 => temp_cmp_three_inc_min_102, + I3 => tempmon_state(3), + O => \tempmon_state[10]_i_14_n_0\ + ); +\tempmon_state[10]_i_15\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => temp_cmp_two_dec_max_102, + I1 => update_temp_102, + I2 => tempmon_state(8), + O => \tempmon_state[10]_i_15_n_0\ + ); +\tempmon_state[10]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => update_temp_102, + I1 => temp_cmp_three_dec_max_102, + I2 => tempmon_state(9), + I3 => \tempmon_state[10]_i_6_n_0\, + O => tempmon_state_nxt(10) + ); +\tempmon_state[10]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000022202220222" + ) + port map ( + I0 => pi_f_dec_i_2_n_0, + I1 => \tempmon_state[10]_i_7_n_0\, + I2 => temp_cmp_one_dec_min_102, + I3 => tempmon_state(7), + I4 => temp_cmp_three_dec_min_102, + I5 => tempmon_state(9), + O => \tempmon_state[10]_i_3_n_0\ + ); +\tempmon_state[10]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEFEFEF" + ) + port map ( + I0 => \tempmon_state[10]_i_8_n_0\, + I1 => tempmon_state(1), + I2 => \tempmon_state[10]_i_6_n_0\, + I3 => tempmon_state(0), + I4 => calib_complete, + O => \tempmon_state[10]_i_4_n_0\ + ); +\tempmon_state[10]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFAAEAAAEAAAEAAA" + ) + port map ( + I0 => \tempmon_state[10]_i_9_n_0\, + I1 => tempmon_state(6), + I2 => temp_cmp_neutral_max_102, + I3 => update_temp_102, + I4 => tempmon_state(7), + I5 => temp_cmp_one_dec_max_102, + O => \tempmon_state[10]_i_5_n_0\ + ); +\tempmon_state[10]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0012" + ) + port map ( + I0 => \tempmon_state[10]_i_10_n_0\, + I1 => \tempmon_state[10]_i_11_n_0\, + I2 => \tempmon_state[10]_i_12_n_0\, + I3 => \tempmon_state[10]_i_13_n_0\, + O => \tempmon_state[10]_i_6_n_0\ + ); +\tempmon_state[10]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF888" + ) + port map ( + I0 => tempmon_state(4), + I1 => temp_cmp_two_inc_min_102, + I2 => tempmon_state(6), + I3 => temp_cmp_neutral_min_102, + I4 => \tempmon_state[10]_i_14_n_0\, + O => \tempmon_state[10]_i_7_n_0\ + ); +\tempmon_state[10]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => temp_cmp_one_inc_min_102, + I1 => tempmon_state(5), + I2 => update_temp_102, + O => \tempmon_state[10]_i_8_n_0\ + ); +\tempmon_state[10]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF8F0F0F8F8F0F0" + ) + port map ( + I0 => tempmon_state(2), + I1 => temp_cmp_four_inc_max_102, + I2 => \tempmon_state[10]_i_15_n_0\, + I3 => tempmon_state(9), + I4 => update_temp_102, + I5 => temp_cmp_three_dec_max_102, + O => \tempmon_state[10]_i_9_n_0\ + ); +\tempmon_state[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \tempmon_state[10]_i_6_n_0\, + I1 => tempmon_state(0), + O => tempmon_state_nxt(1) + ); +\tempmon_state[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7000" + ) + port map ( + I0 => temp_cmp_three_inc_max_102, + I1 => update_temp_102, + I2 => tempmon_state(3), + I3 => \tempmon_state[10]_i_6_n_0\, + O => tempmon_state_nxt(2) + ); +\tempmon_state[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8AAA8888" + ) + port map ( + I0 => \tempmon_state[10]_i_6_n_0\, + I1 => tempmon_state(2), + I2 => temp_cmp_two_inc_max_102, + I3 => update_temp_102, + I4 => tempmon_state(4), + O => tempmon_state_nxt(3) + ); +\tempmon_state[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8080F000F080F000" + ) + port map ( + I0 => temp_cmp_three_inc_max_102, + I1 => tempmon_state(3), + I2 => \tempmon_state[10]_i_6_n_0\, + I3 => tempmon_state(5), + I4 => update_temp_102, + I5 => temp_cmp_one_inc_max_102, + O => tempmon_state_nxt(4) + ); +\tempmon_state[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8080F000F080F000" + ) + port map ( + I0 => temp_cmp_two_inc_max_102, + I1 => tempmon_state(4), + I2 => \tempmon_state[10]_i_6_n_0\, + I3 => tempmon_state(6), + I4 => update_temp_102, + I5 => temp_cmp_neutral_max_102, + O => tempmon_state_nxt(5) + ); +\tempmon_state[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF0000BFA00000" + ) + port map ( + I0 => \tempmon_state[6]_i_2_n_0\, + I1 => temp_cmp_one_dec_max_102, + I2 => update_temp_102, + I3 => tempmon_state(7), + I4 => \tempmon_state[10]_i_6_n_0\, + I5 => tempmon_state(1), + O => tempmon_state_nxt(6) + ); +\tempmon_state[6]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => temp_cmp_one_inc_max_102, + I1 => tempmon_state(5), + O => \tempmon_state[6]_i_2_n_0\ + ); +\tempmon_state[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"80AAAAAA80008000" + ) + port map ( + I0 => \tempmon_state[10]_i_6_n_0\, + I1 => tempmon_state(6), + I2 => temp_cmp_neutral_max_102, + I3 => update_temp_102, + I4 => temp_cmp_two_dec_max_102, + I5 => tempmon_state(8), + O => tempmon_state_nxt(7) + ); +\tempmon_state[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8080F080F000F000" + ) + port map ( + I0 => tempmon_state(7), + I1 => temp_cmp_one_dec_max_102, + I2 => \tempmon_state[10]_i_6_n_0\, + I3 => tempmon_state(9), + I4 => temp_cmp_three_dec_max_102, + I5 => update_temp_102, + O => tempmon_state_nxt(8) + ); +\tempmon_state[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAA8000" + ) + port map ( + I0 => \tempmon_state[10]_i_6_n_0\, + I1 => temp_cmp_two_dec_max_102, + I2 => update_temp_102, + I3 => tempmon_state(8), + I4 => tempmon_state(10), + O => tempmon_state_nxt(9) + ); +\tempmon_state_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(0), + Q => tempmon_state(0), + S => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(10), + Q => tempmon_state(10), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(1), + Q => tempmon_state(1), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(2), + Q => tempmon_state(2), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(3), + Q => tempmon_state(3), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(4), + Q => tempmon_state(4), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(5), + Q => tempmon_state(5), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(6), + Q => tempmon_state(6), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(7), + Q => tempmon_state(7), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(8), + Q => tempmon_state(8), + R => \four_inc_max_limit_reg[2]_0\ + ); +\tempmon_state_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \tempmon_state[10]_i_1_n_0\, + D => tempmon_state_nxt(9), + Q => tempmon_state(9), + R => \four_inc_max_limit_reg[2]_0\ + ); +\three_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => p_0_in, + I1 => device_temp_init(0), + O => \three_dec_max_limit[0]_i_1_n_0\ + ); +\three_dec_max_limit[10]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[11]_i_2_n_6\, + I1 => p_0_in, + O => \three_dec_max_limit[10]_i_1_n_0\ + ); +\three_dec_max_limit[11]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[11]_i_2_n_5\, + I1 => p_0_in, + O => \three_dec_max_limit[11]_i_1_n_0\ + ); +\three_dec_max_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(9), + O => \three_dec_max_limit[11]_i_3_n_0\ + ); +\three_dec_max_limit[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_inc_max_limit_reg[4]_i_1_n_7\, + I1 => p_0_in, + O => \three_dec_max_limit[1]_i_1_n_0\ + ); +\three_dec_max_limit[2]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[4]_i_2_n_6\, + I1 => p_0_in, + O => \three_dec_max_limit[2]_i_1_n_0\ + ); +\three_dec_max_limit[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[4]_i_2_n_5\, + I1 => p_0_in, + O => \three_dec_max_limit[3]_i_1_n_0\ + ); +\three_dec_max_limit[4]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[4]_i_2_n_4\, + I1 => p_0_in, + O => \three_dec_max_limit[4]_i_1_n_0\ + ); +\three_dec_max_limit[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[8]_i_2_n_7\, + I1 => p_0_in, + O => \three_dec_max_limit[5]_i_1_n_0\ + ); +\three_dec_max_limit[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[8]_i_2_n_6\, + I1 => p_0_in, + O => \three_dec_max_limit[6]_i_1_n_0\ + ); +\three_dec_max_limit[7]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[8]_i_2_n_5\, + I1 => p_0_in, + O => \three_dec_max_limit[7]_i_1_n_0\ + ); +\three_dec_max_limit[8]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[8]_i_2_n_4\, + I1 => p_0_in, + O => \three_dec_max_limit[8]_i_1_n_0\ + ); +\three_dec_max_limit[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(8), + O => \three_dec_max_limit[8]_i_3_n_0\ + ); +\three_dec_max_limit[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(6), + O => \three_dec_max_limit[8]_i_4_n_0\ + ); +\three_dec_max_limit[9]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \three_dec_max_limit_reg[11]_i_2_n_7\, + I1 => p_0_in, + O => \three_dec_max_limit[9]_i_1_n_0\ + ); +\three_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[0]_i_1_n_0\, + Q => three_dec_max_limit(0), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[10]_i_1_n_0\, + Q => three_dec_max_limit(10), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[11]_i_1_n_0\, + Q => three_dec_max_limit(11), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[11]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_dec_max_limit_reg[8]_i_2_n_0\, + CO(3) => p_0_in, + CO(2) => \NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED\(2), + CO(1) => \three_dec_max_limit_reg[11]_i_2_n_2\, + CO(0) => \three_dec_max_limit_reg[11]_i_2_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => device_temp_init(9), + O(3) => \NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED\(3), + O(2) => \three_dec_max_limit_reg[11]_i_2_n_5\, + O(1) => \three_dec_max_limit_reg[11]_i_2_n_6\, + O(0) => \three_dec_max_limit_reg[11]_i_2_n_7\, + S(3) => '1', + S(2 downto 1) => device_temp_init(11 downto 10), + S(0) => \three_dec_max_limit[11]_i_3_n_0\ + ); +\three_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[1]_i_1_n_0\, + Q => three_dec_max_limit(1), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[2]_i_1_n_0\, + Q => three_dec_max_limit(2), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[3]_i_1_n_0\, + Q => three_dec_max_limit(3), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[4]_i_1_n_0\, + Q => three_dec_max_limit(4), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[4]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \three_dec_max_limit_reg[4]_i_2_n_0\, + CO(2) => \three_dec_max_limit_reg[4]_i_2_n_1\, + CO(1) => \three_dec_max_limit_reg[4]_i_2_n_2\, + CO(0) => \three_dec_max_limit_reg[4]_i_2_n_3\, + CYINIT => device_temp_init(0), + DI(3 downto 0) => B"0000", + O(3) => \three_dec_max_limit_reg[4]_i_2_n_4\, + O(2) => \three_dec_max_limit_reg[4]_i_2_n_5\, + O(1) => \three_dec_max_limit_reg[4]_i_2_n_6\, + O(0) => \NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED\(0), + S(3 downto 0) => device_temp_init(4 downto 1) + ); +\three_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[5]_i_1_n_0\, + Q => three_dec_max_limit(5), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[6]_i_1_n_0\, + Q => three_dec_max_limit(6), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[7]_i_1_n_0\, + Q => three_dec_max_limit(7), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[8]_i_1_n_0\, + Q => three_dec_max_limit(8), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_max_limit_reg[8]_i_2\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_dec_max_limit_reg[4]_i_2_n_0\, + CO(3) => \three_dec_max_limit_reg[8]_i_2_n_0\, + CO(2) => \three_dec_max_limit_reg[8]_i_2_n_1\, + CO(1) => \three_dec_max_limit_reg[8]_i_2_n_2\, + CO(0) => \three_dec_max_limit_reg[8]_i_2_n_3\, + CYINIT => '0', + DI(3) => device_temp_init(8), + DI(2) => '0', + DI(1) => device_temp_init(6), + DI(0) => '0', + O(3) => \three_dec_max_limit_reg[8]_i_2_n_4\, + O(2) => \three_dec_max_limit_reg[8]_i_2_n_5\, + O(1) => \three_dec_max_limit_reg[8]_i_2_n_6\, + O(0) => \three_dec_max_limit_reg[8]_i_2_n_7\, + S(3) => \three_dec_max_limit[8]_i_3_n_0\, + S(2) => device_temp_init(7), + S(1) => \three_dec_max_limit[8]_i_4_n_0\, + S(0) => device_temp_init(5) + ); +\three_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \three_dec_max_limit[9]_i_1_n_0\, + Q => three_dec_max_limit(9), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(11), + O => \three_dec_min_limit[11]_i_2_n_0\ + ); +\three_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(10), + O => \three_dec_min_limit[11]_i_3_n_0\ + ); +\three_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(5), + O => \three_dec_min_limit[5]_i_2_n_0\ + ); +\three_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(4), + O => \three_dec_min_limit[5]_i_3_n_0\ + ); +\three_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(3), + O => \three_dec_min_limit[5]_i_4_n_0\ + ); +\three_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(9), + O => \three_dec_min_limit[9]_i_2_n_0\ + ); +\three_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(8), + O => \three_dec_min_limit[9]_i_3_n_0\ + ); +\three_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(7), + O => \three_dec_min_limit[9]_i_4_n_0\ + ); +\three_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => two_dec_max_limit(6), + O => \three_dec_min_limit[9]_i_5_n_0\ + ); +\three_dec_min_limit_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit(0), + Q => three_dec_min_limit(0), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(10), + Q => three_dec_min_limit(10), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(11), + Q => three_dec_min_limit(11), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_dec_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \three_dec_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => two_dec_max_limit(10), + O(3 downto 2) => \NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => three_dec_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \three_dec_min_limit[11]_i_2_n_0\, + S(0) => \three_dec_min_limit[11]_i_3_n_0\ + ); +\three_dec_min_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit(1), + Q => three_dec_min_limit(1), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(2), + Q => three_dec_min_limit(2), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(3), + Q => three_dec_min_limit(3), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(4), + Q => three_dec_min_limit(4), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(5), + Q => three_dec_min_limit(5), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \three_dec_min_limit_reg[5]_i_1_n_0\, + CO(2) => \three_dec_min_limit_reg[5]_i_1_n_1\, + CO(1) => \three_dec_min_limit_reg[5]_i_1_n_2\, + CO(0) => \three_dec_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => two_dec_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => three_dec_min_limit_nxt(5 downto 2), + S(3) => \three_dec_min_limit[5]_i_2_n_0\, + S(2) => \three_dec_min_limit[5]_i_3_n_0\, + S(1) => \three_dec_min_limit[5]_i_4_n_0\, + S(0) => two_dec_max_limit(2) + ); +\three_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(6), + Q => three_dec_min_limit(6), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(7), + Q => three_dec_min_limit(7), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(8), + Q => three_dec_min_limit(8), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_dec_min_limit_nxt(9), + Q => three_dec_min_limit(9), + R => \three_dec_max_limit_reg[0]_0\(0) + ); +\three_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_dec_min_limit_reg[5]_i_1_n_0\, + CO(3) => \three_dec_min_limit_reg[9]_i_1_n_0\, + CO(2) => \three_dec_min_limit_reg[9]_i_1_n_1\, + CO(1) => \three_dec_min_limit_reg[9]_i_1_n_2\, + CO(0) => \three_dec_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => two_dec_max_limit(9 downto 6), + O(3 downto 0) => three_dec_min_limit_nxt(9 downto 6), + S(3) => \three_dec_min_limit[9]_i_2_n_0\, + S(2) => \three_dec_min_limit[9]_i_3_n_0\, + S(1) => \three_dec_min_limit[9]_i_4_n_0\, + S(0) => \three_dec_min_limit[9]_i_5_n_0\ + ); +\three_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(11), + O => \three_inc_max_limit[11]_i_2_n_0\ + ); +\three_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(10), + O => \three_inc_max_limit[11]_i_3_n_0\ + ); +\three_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(3), + O => \three_inc_max_limit[4]_i_2_n_0\ + ); +\three_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(2), + O => \three_inc_max_limit[4]_i_3_n_0\ + ); +\three_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(8), + O => \three_inc_max_limit[8]_i_2_n_0\ + ); +\three_inc_max_limit[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(7), + O => \three_inc_max_limit[8]_i_3_n_0\ + ); +\three_inc_max_limit[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(5), + O => \three_inc_max_limit[8]_i_4_n_0\ + ); +\three_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(10), + Q => three_inc_max_limit(10), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(11), + Q => three_inc_max_limit(11), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_inc_max_limit_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \three_inc_max_limit_reg[11]_i_1_n_2\, + CO(0) => \three_inc_max_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => device_temp_init(10), + DI(0) => '0', + O(3) => \NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => three_inc_max_limit_nxt(11 downto 9), + S(3) => '0', + S(2) => \three_inc_max_limit[11]_i_2_n_0\, + S(1) => \three_inc_max_limit[11]_i_3_n_0\, + S(0) => device_temp_init(9) + ); +\three_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(2), + Q => three_inc_max_limit(2), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(3), + Q => three_inc_max_limit(3), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(4), + Q => three_inc_max_limit(4), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \three_inc_max_limit_reg[4]_i_1_n_0\, + CO(2) => \three_inc_max_limit_reg[4]_i_1_n_1\, + CO(1) => \three_inc_max_limit_reg[4]_i_1_n_2\, + CO(0) => \three_inc_max_limit_reg[4]_i_1_n_3\, + CYINIT => device_temp_init(0), + DI(3) => '0', + DI(2 downto 1) => device_temp_init(3 downto 2), + DI(0) => '0', + O(3 downto 1) => three_inc_max_limit_nxt(4 downto 2), + O(0) => \three_inc_max_limit_reg[4]_i_1_n_7\, + S(3) => device_temp_init(4), + S(2) => \three_inc_max_limit[4]_i_2_n_0\, + S(1) => \three_inc_max_limit[4]_i_3_n_0\, + S(0) => device_temp_init(1) + ); +\three_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(5), + Q => three_inc_max_limit(5), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(6), + Q => three_inc_max_limit(6), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(7), + Q => three_inc_max_limit(7), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(8), + Q => three_inc_max_limit(8), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_inc_max_limit_reg[4]_i_1_n_0\, + CO(3) => \three_inc_max_limit_reg[8]_i_1_n_0\, + CO(2) => \three_inc_max_limit_reg[8]_i_1_n_1\, + CO(1) => \three_inc_max_limit_reg[8]_i_1_n_2\, + CO(0) => \three_inc_max_limit_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => device_temp_init(8 downto 7), + DI(1) => '0', + DI(0) => device_temp_init(5), + O(3 downto 0) => three_inc_max_limit_nxt(8 downto 5), + S(3) => \three_inc_max_limit[8]_i_2_n_0\, + S(2) => \three_inc_max_limit[8]_i_3_n_0\, + S(1) => device_temp_init(6), + S(0) => \three_inc_max_limit[8]_i_4_n_0\ + ); +\three_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_max_limit_nxt(9), + Q => three_inc_max_limit(9), + R => \three_dec_max_limit_reg[0]_0\(1) + ); +\three_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(11), + O => \three_inc_min_limit[11]_i_2_n_0\ + ); +\three_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(10), + O => \three_inc_min_limit[11]_i_3_n_0\ + ); +\three_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(5), + O => \three_inc_min_limit[5]_i_2_n_0\ + ); +\three_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(4), + O => \three_inc_min_limit[5]_i_3_n_0\ + ); +\three_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(3), + O => \three_inc_min_limit[5]_i_4_n_0\ + ); +\three_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(9), + O => \three_inc_min_limit[9]_i_2_n_0\ + ); +\three_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(8), + O => \three_inc_min_limit[9]_i_3_n_0\ + ); +\three_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(7), + O => \three_inc_min_limit[9]_i_4_n_0\ + ); +\three_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => four_inc_max_limit(6), + O => \three_inc_min_limit[9]_i_5_n_0\ + ); +\three_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(10), + Q => three_inc_min_limit(10), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(11), + Q => three_inc_min_limit(11), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_inc_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \three_inc_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => four_inc_max_limit(10), + O(3 downto 2) => \NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => three_inc_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \three_inc_min_limit[11]_i_2_n_0\, + S(0) => \three_inc_min_limit[11]_i_3_n_0\ + ); +\three_inc_min_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => neutral_max_limit(1), + Q => three_inc_min_limit(1), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(2), + Q => three_inc_min_limit(2), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(3), + Q => three_inc_min_limit(3), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(4), + Q => three_inc_min_limit(4), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(5), + Q => three_inc_min_limit(5), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \three_inc_min_limit_reg[5]_i_1_n_0\, + CO(2) => \three_inc_min_limit_reg[5]_i_1_n_1\, + CO(1) => \three_inc_min_limit_reg[5]_i_1_n_2\, + CO(0) => \three_inc_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => four_inc_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => three_inc_min_limit_nxt(5 downto 2), + S(3) => \three_inc_min_limit[5]_i_2_n_0\, + S(2) => \three_inc_min_limit[5]_i_3_n_0\, + S(1) => \three_inc_min_limit[5]_i_4_n_0\, + S(0) => four_inc_max_limit(2) + ); +\three_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(6), + Q => three_inc_min_limit(6), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(7), + Q => three_inc_min_limit(7), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(8), + Q => three_inc_min_limit(8), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => three_inc_min_limit_nxt(9), + Q => three_inc_min_limit(9), + R => \two_inc_max_limit_reg[11]_0\ + ); +\three_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \three_inc_min_limit_reg[5]_i_1_n_0\, + CO(3) => \three_inc_min_limit_reg[9]_i_1_n_0\, + CO(2) => \three_inc_min_limit_reg[9]_i_1_n_1\, + CO(1) => \three_inc_min_limit_reg[9]_i_1_n_2\, + CO(0) => \three_inc_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => four_inc_max_limit(9 downto 6), + O(3 downto 0) => three_inc_min_limit_nxt(9 downto 6), + S(3) => \three_inc_min_limit[9]_i_2_n_0\, + S(2) => \three_inc_min_limit[9]_i_3_n_0\, + S(1) => \three_inc_min_limit[9]_i_4_n_0\, + S(0) => \three_inc_min_limit[9]_i_5_n_0\ + ); +\two_dec_max_limit[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(0), + O => \two_dec_max_limit[0]_i_1_n_0\ + ); +\two_dec_max_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(9), + O => \two_dec_max_limit[11]_i_2_n_0\ + ); +\two_dec_max_limit[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(4), + O => \two_dec_max_limit[4]_i_2_n_0\ + ); +\two_dec_max_limit[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(1), + O => \two_dec_max_limit[4]_i_3_n_0\ + ); +\two_dec_max_limit[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(6), + O => \two_dec_max_limit[8]_i_2_n_0\ + ); +\two_dec_max_limit_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \two_dec_max_limit[0]_i_1_n_0\, + Q => two_dec_max_limit(0), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(10), + Q => two_dec_max_limit(10), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(11), + Q => two_dec_max_limit(11), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_dec_max_limit_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \two_dec_max_limit_reg[11]_i_1_n_2\, + CO(0) => \two_dec_max_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => device_temp_init(9), + O(3) => \NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => two_dec_max_limit_nxt(11 downto 9), + S(3) => '0', + S(2 downto 1) => device_temp_init(11 downto 10), + S(0) => \two_dec_max_limit[11]_i_2_n_0\ + ); +\two_dec_max_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(1), + Q => two_dec_max_limit(1), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(2), + Q => two_dec_max_limit(2), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(3), + Q => two_dec_max_limit(3), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(4), + Q => two_dec_max_limit(4), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \two_dec_max_limit_reg[4]_i_1_n_0\, + CO(2) => \two_dec_max_limit_reg[4]_i_1_n_1\, + CO(1) => \two_dec_max_limit_reg[4]_i_1_n_2\, + CO(0) => \two_dec_max_limit_reg[4]_i_1_n_3\, + CYINIT => device_temp_init(0), + DI(3) => device_temp_init(4), + DI(2 downto 1) => B"00", + DI(0) => device_temp_init(1), + O(3 downto 1) => two_dec_max_limit_nxt(4 downto 2), + O(0) => \NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED\(0), + S(3) => \two_dec_max_limit[4]_i_2_n_0\, + S(2 downto 1) => device_temp_init(3 downto 2), + S(0) => \two_dec_max_limit[4]_i_3_n_0\ + ); +\two_dec_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(5), + Q => two_dec_max_limit(5), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(6), + Q => two_dec_max_limit(6), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(7), + Q => two_dec_max_limit(7), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(8), + Q => two_dec_max_limit(8), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_dec_max_limit_reg[4]_i_1_n_0\, + CO(3) => \two_dec_max_limit_reg[8]_i_1_n_0\, + CO(2) => \two_dec_max_limit_reg[8]_i_1_n_1\, + CO(1) => \two_dec_max_limit_reg[8]_i_1_n_2\, + CO(0) => \two_dec_max_limit_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1) => device_temp_init(6), + DI(0) => '0', + O(3 downto 0) => two_dec_max_limit_nxt(8 downto 5), + S(3 downto 2) => device_temp_init(8 downto 7), + S(1) => \two_dec_max_limit[8]_i_2_n_0\, + S(0) => device_temp_init(5) + ); +\two_dec_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_max_limit_nxt(9), + Q => two_dec_max_limit(9), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_dec_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(11), + O => \two_dec_min_limit[11]_i_2_n_0\ + ); +\two_dec_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(10), + O => \two_dec_min_limit[11]_i_3_n_0\ + ); +\two_dec_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(5), + O => \two_dec_min_limit[5]_i_2_n_0\ + ); +\two_dec_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(4), + O => \two_dec_min_limit[5]_i_3_n_0\ + ); +\two_dec_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(3), + O => \two_dec_min_limit[5]_i_4_n_0\ + ); +\two_dec_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(9), + O => \two_dec_min_limit[9]_i_2_n_0\ + ); +\two_dec_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(8), + O => \two_dec_min_limit[9]_i_3_n_0\ + ); +\two_dec_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(7), + O => \two_dec_min_limit[9]_i_4_n_0\ + ); +\two_dec_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => one_dec_max_limit(6), + O => \two_dec_min_limit[9]_i_5_n_0\ + ); +\two_dec_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(10), + Q => two_dec_min_limit(10), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(11), + Q => two_dec_min_limit(11), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_dec_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \two_dec_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => one_dec_max_limit(10), + O(3 downto 2) => \NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => two_dec_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \two_dec_min_limit[11]_i_2_n_0\, + S(0) => \two_dec_min_limit[11]_i_3_n_0\ + ); +\two_dec_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(2), + Q => two_dec_min_limit(2), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(3), + Q => two_dec_min_limit(3), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(4), + Q => two_dec_min_limit(4), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(5), + Q => two_dec_min_limit(5), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \two_dec_min_limit_reg[5]_i_1_n_0\, + CO(2) => \two_dec_min_limit_reg[5]_i_1_n_1\, + CO(1) => \two_dec_min_limit_reg[5]_i_1_n_2\, + CO(0) => \two_dec_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => one_dec_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => two_dec_min_limit_nxt(5 downto 2), + S(3) => \two_dec_min_limit[5]_i_2_n_0\, + S(2) => \two_dec_min_limit[5]_i_3_n_0\, + S(1) => \two_dec_min_limit[5]_i_4_n_0\, + S(0) => one_dec_max_limit(2) + ); +\two_dec_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(6), + Q => two_dec_min_limit(6), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(7), + Q => two_dec_min_limit(7), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(8), + Q => two_dec_min_limit(8), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_dec_min_limit_nxt(9), + Q => two_dec_min_limit(9), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_dec_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_dec_min_limit_reg[5]_i_1_n_0\, + CO(3) => \two_dec_min_limit_reg[9]_i_1_n_0\, + CO(2) => \two_dec_min_limit_reg[9]_i_1_n_1\, + CO(1) => \two_dec_min_limit_reg[9]_i_1_n_2\, + CO(0) => \two_dec_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => one_dec_max_limit(9 downto 6), + O(3 downto 0) => two_dec_min_limit_nxt(9 downto 6), + S(3) => \two_dec_min_limit[9]_i_2_n_0\, + S(2) => \two_dec_min_limit[9]_i_3_n_0\, + S(1) => \two_dec_min_limit[9]_i_4_n_0\, + S(0) => \two_dec_min_limit[9]_i_5_n_0\ + ); +\two_inc_max_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(11), + O => \two_inc_max_limit[11]_i_2_n_0\ + ); +\two_inc_max_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(10), + O => \two_inc_max_limit[11]_i_3_n_0\ + ); +\two_inc_max_limit[11]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(9), + O => \two_inc_max_limit[11]_i_4_n_0\ + ); +\two_inc_max_limit[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(4), + O => \two_inc_max_limit[4]_i_2_n_0\ + ); +\two_inc_max_limit[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(3), + O => \two_inc_max_limit[4]_i_3_n_0\ + ); +\two_inc_max_limit[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(1), + O => \two_inc_max_limit[4]_i_4_n_0\ + ); +\two_inc_max_limit[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => device_temp_init(7), + O => \two_inc_max_limit[8]_i_2_n_0\ + ); +\two_inc_max_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(10), + Q => two_inc_max_limit(10), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(11), + Q => two_inc_max_limit(11), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_inc_max_limit_reg[8]_i_1_n_0\, + CO(3 downto 2) => \NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 2), + CO(1) => \two_inc_max_limit_reg[11]_i_1_n_2\, + CO(0) => \two_inc_max_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 2) => B"00", + DI(1 downto 0) => device_temp_init(10 downto 9), + O(3) => \NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED\(3), + O(2 downto 0) => two_inc_max_limit_nxt(11 downto 9), + S(3) => '0', + S(2) => \two_inc_max_limit[11]_i_2_n_0\, + S(1) => \two_inc_max_limit[11]_i_3_n_0\, + S(0) => \two_inc_max_limit[11]_i_4_n_0\ + ); +\two_inc_max_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(2), + Q => two_inc_max_limit(2), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(3), + Q => two_inc_max_limit(3), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(4), + Q => two_inc_max_limit(4), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \two_inc_max_limit_reg[4]_i_1_n_0\, + CO(2) => \two_inc_max_limit_reg[4]_i_1_n_1\, + CO(1) => \two_inc_max_limit_reg[4]_i_1_n_2\, + CO(0) => \two_inc_max_limit_reg[4]_i_1_n_3\, + CYINIT => device_temp_init(0), + DI(3 downto 2) => device_temp_init(4 downto 3), + DI(1) => '0', + DI(0) => device_temp_init(1), + O(3 downto 1) => two_inc_max_limit_nxt(4 downto 2), + O(0) => \NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED\(0), + S(3) => \two_inc_max_limit[4]_i_2_n_0\, + S(2) => \two_inc_max_limit[4]_i_3_n_0\, + S(1) => device_temp_init(2), + S(0) => \two_inc_max_limit[4]_i_4_n_0\ + ); +\two_inc_max_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(5), + Q => two_inc_max_limit(5), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(6), + Q => two_inc_max_limit(6), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(7), + Q => two_inc_max_limit(7), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(8), + Q => two_inc_max_limit(8), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_max_limit_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_inc_max_limit_reg[4]_i_1_n_0\, + CO(3) => \two_inc_max_limit_reg[8]_i_1_n_0\, + CO(2) => \two_inc_max_limit_reg[8]_i_1_n_1\, + CO(1) => \two_inc_max_limit_reg[8]_i_1_n_2\, + CO(0) => \two_inc_max_limit_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3) => '0', + DI(2) => device_temp_init(7), + DI(1 downto 0) => B"00", + O(3 downto 0) => two_inc_max_limit_nxt(8 downto 5), + S(3) => device_temp_init(8), + S(2) => \two_inc_max_limit[8]_i_2_n_0\, + S(1 downto 0) => device_temp_init(6 downto 5) + ); +\two_inc_max_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_max_limit_nxt(9), + Q => two_inc_max_limit(9), + R => \two_inc_max_limit_reg[11]_0\ + ); +\two_inc_min_limit[11]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(11), + O => \two_inc_min_limit[11]_i_2_n_0\ + ); +\two_inc_min_limit[11]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(10), + O => \two_inc_min_limit[11]_i_3_n_0\ + ); +\two_inc_min_limit[5]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(5), + O => \two_inc_min_limit[5]_i_2_n_0\ + ); +\two_inc_min_limit[5]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(4), + O => \two_inc_min_limit[5]_i_3_n_0\ + ); +\two_inc_min_limit[5]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(3), + O => \two_inc_min_limit[5]_i_4_n_0\ + ); +\two_inc_min_limit[9]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(9), + O => \two_inc_min_limit[9]_i_2_n_0\ + ); +\two_inc_min_limit[9]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(8), + O => \two_inc_min_limit[9]_i_3_n_0\ + ); +\two_inc_min_limit[9]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(7), + O => \two_inc_min_limit[9]_i_4_n_0\ + ); +\two_inc_min_limit[9]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => three_inc_max_limit(6), + O => \two_inc_min_limit[9]_i_5_n_0\ + ); +\two_inc_min_limit_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(10), + Q => two_inc_min_limit(10), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(11), + Q => two_inc_min_limit(11), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[11]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_inc_min_limit_reg[9]_i_1_n_0\, + CO(3 downto 1) => \NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED\(3 downto 1), + CO(0) => \two_inc_min_limit_reg[11]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => B"000", + DI(0) => three_inc_max_limit(10), + O(3 downto 2) => \NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED\(3 downto 2), + O(1 downto 0) => two_inc_min_limit_nxt(11 downto 10), + S(3 downto 2) => B"00", + S(1) => \two_inc_min_limit[11]_i_2_n_0\, + S(0) => \two_inc_min_limit[11]_i_3_n_0\ + ); +\two_inc_min_limit_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => one_dec_max_limit(1), + Q => two_inc_min_limit(1), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(2), + Q => two_inc_min_limit(2), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(3), + Q => two_inc_min_limit(3), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(4), + Q => two_inc_min_limit(4), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(5), + Q => two_inc_min_limit(5), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[5]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \two_inc_min_limit_reg[5]_i_1_n_0\, + CO(2) => \two_inc_min_limit_reg[5]_i_1_n_1\, + CO(1) => \two_inc_min_limit_reg[5]_i_1_n_2\, + CO(0) => \two_inc_min_limit_reg[5]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 1) => three_inc_max_limit(5 downto 3), + DI(0) => '0', + O(3 downto 0) => two_inc_min_limit_nxt(5 downto 2), + S(3) => \two_inc_min_limit[5]_i_2_n_0\, + S(2) => \two_inc_min_limit[5]_i_3_n_0\, + S(1) => \two_inc_min_limit[5]_i_4_n_0\, + S(0) => three_inc_max_limit(2) + ); +\two_inc_min_limit_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(6), + Q => two_inc_min_limit(6), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(7), + Q => two_inc_min_limit(7), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(8), + Q => two_inc_min_limit(8), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => two_inc_min_limit_nxt(9), + Q => two_inc_min_limit(9), + R => \four_dec_min_limit_reg[0]_0\ + ); +\two_inc_min_limit_reg[9]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \two_inc_min_limit_reg[5]_i_1_n_0\, + CO(3) => \two_inc_min_limit_reg[9]_i_1_n_0\, + CO(2) => \two_inc_min_limit_reg[9]_i_1_n_1\, + CO(1) => \two_inc_min_limit_reg[9]_i_1_n_2\, + CO(0) => \two_inc_min_limit_reg[9]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => three_inc_max_limit(9 downto 6), + O(3 downto 0) => two_inc_min_limit_nxt(9 downto 6), + S(3) => \two_inc_min_limit[9]_i_2_n_0\, + S(2) => \two_inc_min_limit[9]_i_3_n_0\, + S(1) => \two_inc_min_limit[9]_i_4_n_0\, + S(0) => \two_inc_min_limit[9]_i_5_n_0\ + ); +update_temp_101: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => tempmon_init_complete, + I1 => tempmon_sample_en_102, + I2 => tempmon_sample_en_101, + O => \update_temp_101__0\ + ); +update_temp_102_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \update_temp_101__0\, + Q => update_temp_102, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_wrcal is + port ( + wrcal_resume_w : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + wrcal_prech_req : out STD_LOGIC; + wrcal_done_reg_0 : out STD_LOGIC; + wrcal_sanity_chk_done_reg_0 : out STD_LOGIC; + wrlvl_byte_redo : out STD_LOGIC; + early1_data_reg_0 : out STD_LOGIC; + phy_if_reset_w : out STD_LOGIC; + wrlvl_byte_redo_reg_0 : out STD_LOGIC; + wrcal_sanity_chk_done_reg_1 : out STD_LOGIC; + wrcal_done_reg_1 : out STD_LOGIC; + wrlvl_byte_redo_reg_1 : out STD_LOGIC; + done_dqs_dec237_out : out STD_LOGIC; + early2_data_reg_0 : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \rstdiv0_sync_r1_reg_rep__15\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + cal1_dq_idel_ce_reg : out STD_LOGIC; + rdlvl_stg1_done_int_reg : out STD_LOGIC; + rdlvl_stg1_done_int_reg_0 : out STD_LOGIC; + wrlvl_byte_redo_reg_2 : out STD_LOGIC; + LD0 : out STD_LOGIC; + LD0_0 : out STD_LOGIC; + CLK : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + phy_rddata_en : in STD_LOGIC; + wrcal_sanity_chk : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + idelay_ld_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + wrlvl_byte_done : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + wrlvl_done_r1 : in STD_LOGIC; + pi_dqs_found_done : in STD_LOGIC; + D : in STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_lm_done_r : in STD_LOGIC; + \init_state_r[4]_i_15\ : in STD_LOGIC; + wrlvl_byte_redo_r : in STD_LOGIC; + \FSM_sequential_wl_state_r[4]_i_18\ : in STD_LOGIC; + \FSM_sequential_wl_state_r[4]_i_18_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \FSM_sequential_wl_state_r[4]_i_18_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC; + idelay_ce_int : in STD_LOGIC; + \idelay_tap_cnt_r_reg[0][1][4]_0\ : in STD_LOGIC; + mem_init_done_r : in STD_LOGIC; + calib_zero_inputs : in STD_LOGIC; + \input_[9].iserdes_dq_.idelay_dq.idelaye2\ : in STD_LOGIC; + \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\ : in STD_LOGIC; + \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\ : in STD_LOGIC; + idelay_ld_rst : in STD_LOGIC; + \not_empty_wait_cnt_reg[4]_0\ : in STD_LOGIC; + wrcal_rd_wait : in STD_LOGIC; + prech_done : in STD_LOGIC; + \cal2_state_r_reg[0]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_wrcal : entity is "mig_7series_v4_2_ddr_phy_wrcal"; +end ddr3_mig_7series_v4_2_ddr_phy_wrcal; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_wrcal is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal cal2_done_r : STD_LOGIC; + signal cal2_done_r_i_1_n_0 : STD_LOGIC; + signal cal2_if_reset_i_1_n_0 : STD_LOGIC; + signal cal2_if_reset_i_2_n_0 : STD_LOGIC; + signal cal2_if_reset_i_3_n_0 : STD_LOGIC; + signal cal2_if_reset_i_4_n_0 : STD_LOGIC; + signal cal2_if_reset_i_5_n_0 : STD_LOGIC; + signal cal2_prech_req_r : STD_LOGIC; + signal cal2_prech_req_r_i_1_n_0 : STD_LOGIC; + signal cal2_prech_req_r_i_2_n_0 : STD_LOGIC; + signal cal2_state_r : STD_LOGIC; + signal \cal2_state_r[0]_i_2_n_0\ : STD_LOGIC; + signal \cal2_state_r[0]_i_3_n_0\ : STD_LOGIC; + signal \cal2_state_r[0]_i_4_n_0\ : STD_LOGIC; + signal \cal2_state_r[0]_i_5_n_0\ : STD_LOGIC; + signal \cal2_state_r[1]_i_2_n_0\ : STD_LOGIC; + signal \cal2_state_r[1]_i_3_n_0\ : STD_LOGIC; + signal \cal2_state_r[1]_i_4_n_0\ : STD_LOGIC; + signal \cal2_state_r[2]_i_1_n_0\ : STD_LOGIC; + signal \cal2_state_r[2]_i_2_n_0\ : STD_LOGIC; + signal \cal2_state_r[2]_i_3_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_10_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_2_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_3_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_4_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_5_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_6_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_7_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_8_n_0\ : STD_LOGIC; + signal \cal2_state_r[3]_i_9_n_0\ : STD_LOGIC; + signal \cal2_state_r_reg[0]_i_1_n_0\ : STD_LOGIC; + signal \cal2_state_r_reg[1]_i_1_n_0\ : STD_LOGIC; + signal \cal2_state_r_reg_n_0_[0]\ : STD_LOGIC; + signal \cal2_state_r_reg_n_0_[1]\ : STD_LOGIC; + signal \cal2_state_r_reg_n_0_[2]\ : STD_LOGIC; + signal \cal2_state_r_reg_n_0_[3]\ : STD_LOGIC; + signal early1_data_i_1_n_0 : STD_LOGIC; + signal early1_data_i_2_n_0 : STD_LOGIC; + signal early1_data_i_3_n_0 : STD_LOGIC; + signal early1_data_match_r0 : STD_LOGIC; + signal \^early1_data_reg_0\ : STD_LOGIC; + signal early1_match_fall0_and_r : STD_LOGIC; + signal early1_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early1_match_fall1_and_r : STD_LOGIC; + signal early1_match_fall2_and_r : STD_LOGIC; + signal early1_match_fall3_and_r : STD_LOGIC; + signal early1_match_rise0_and_r : STD_LOGIC; + signal early1_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early1_match_rise1_and_r : STD_LOGIC; + signal early1_match_rise2_and_r : STD_LOGIC; + signal early1_match_rise3_and_r : STD_LOGIC; + signal early2_data_i_1_n_0 : STD_LOGIC; + signal early2_data_match_r0 : STD_LOGIC; + signal early2_data_reg_n_0 : STD_LOGIC; + signal early2_match_fall0_and_r : STD_LOGIC; + signal early2_match_fall0_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early2_match_fall1_and_r : STD_LOGIC; + signal early2_match_fall1_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early2_match_fall2_and_r : STD_LOGIC; + signal early2_match_fall2_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early2_match_fall3_and_r : STD_LOGIC; + signal early2_match_fall3_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early2_match_rise0_and_r : STD_LOGIC; + signal early2_match_rise0_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early2_match_rise1_and_r : STD_LOGIC; + signal early2_match_rise1_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early2_match_rise2_and_r : STD_LOGIC; + signal early2_match_rise2_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal early2_match_rise3_and_r : STD_LOGIC; + signal early2_match_rise3_r : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_data_match_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_data_match_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_data_match_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_data_match_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_data_match_r_i_2_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_data_match_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_222\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_226\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240\ : STD_LOGIC; + signal \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0\ : STD_LOGIC; + signal idelay_ld : STD_LOGIC; + signal idelay_ld_done_i_1_n_0 : STD_LOGIC; + signal idelay_ld_done_i_2_n_0 : STD_LOGIC; + signal idelay_ld_done_reg_n_0 : STD_LOGIC; + signal idelay_ld_i_1_n_0 : STD_LOGIC; + signal idelay_ld_i_2_n_0 : STD_LOGIC; + signal \not_empty_wait_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \not_empty_wait_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \not_empty_wait_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \not_empty_wait_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \not_empty_wait_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \not_empty_wait_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal p_1_in : STD_LOGIC; + signal pat_data_match_r0 : STD_LOGIC; + signal pat_match_fall0_and_r : STD_LOGIC; + signal pat_match_fall1_and_r : STD_LOGIC; + signal pat_match_fall2_and_r : STD_LOGIC; + signal pat_match_fall3_and_r : STD_LOGIC; + signal pat_match_rise0_and_r : STD_LOGIC; + signal pat_match_rise1_and_r : STD_LOGIC; + signal pat_match_rise2_and_r : STD_LOGIC; + signal pat_match_rise3_and_r : STD_LOGIC; + signal \^phy_if_reset_w\ : STD_LOGIC; + signal rd_active_r1 : STD_LOGIC; + signal rd_active_r3_reg_srl2_n_0 : STD_LOGIC; + signal \tap_inc_wait_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal tap_inc_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wrcal_done_i_1_n_0 : STD_LOGIC; + signal \^wrcal_done_reg_0\ : STD_LOGIC; + signal wrcal_dqs_cnt_r : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \wrcal_dqs_cnt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_dqs_cnt_r[0]_i_2_n_0\ : STD_LOGIC; + signal \wrcal_dqs_cnt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \wrcal_dqs_cnt_r[1]_i_2_n_0\ : STD_LOGIC; + signal \wrcal_dqs_cnt_r_reg_n_0_[0]\ : STD_LOGIC; + signal wrcal_pat_resume_r : STD_LOGIC; + signal wrcal_pat_resume_r2_reg_srl2_n_0 : STD_LOGIC; + signal wrcal_pat_resume_r_i_1_n_0 : STD_LOGIC; + signal wrcal_pat_resume_r_i_2_n_0 : STD_LOGIC; + signal wrcal_pat_resume_r_i_3_n_0 : STD_LOGIC; + signal wrcal_sanity_chk_done_i_1_n_0 : STD_LOGIC; + signal \^wrcal_sanity_chk_done_reg_0\ : STD_LOGIC; + signal wrcal_sanity_chk_r_reg_n_0 : STD_LOGIC; + signal wrlvl_byte_done_r : STD_LOGIC; + signal \^wrlvl_byte_redo\ : STD_LOGIC; + signal wrlvl_byte_redo_i_1_n_0 : STD_LOGIC; + signal wrlvl_byte_redo_i_2_n_0 : STD_LOGIC; + signal wrlvl_byte_redo_i_3_n_0 : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of cal2_done_r_i_2 : label is "soft_lutpair430"; + attribute SOFT_HLUTNM of \cal2_state_r[0]_i_4\ : label is "soft_lutpair434"; + attribute SOFT_HLUTNM of \cal2_state_r[3]_i_10\ : label is "soft_lutpair429"; + attribute SOFT_HLUTNM of \cal2_state_r[3]_i_7\ : label is "soft_lutpair433"; + attribute SOFT_HLUTNM of \cal2_state_r[3]_i_9\ : label is "soft_lutpair435"; + attribute SOFT_HLUTNM of early1_data_i_3 : label is "soft_lutpair435"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall1_and_r_i_2\ : label is "soft_lutpair428"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_fall3_and_r_i_2\ : label is "soft_lutpair424"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise1_and_r_i_2\ : label is "soft_lutpair423"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early1_match_rise2_and_r_i_1\ : label is "soft_lutpair426"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall0_and_r_i_2\ : label is "soft_lutpair425"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall1_and_r_i_1\ : label is "soft_lutpair428"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_fall3_and_r_i_1\ : label is "soft_lutpair424"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise0_and_r_i_2\ : label is "soft_lutpair427"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise1_and_r_i_1\ : label is "soft_lutpair423"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.early2_match_rise2_and_r_i_2\ : label is "soft_lutpair426"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_fall0_and_r_i_1\ : label is "soft_lutpair425"; + attribute SOFT_HLUTNM of \gen_pat_match_div4.pat_match_rise0_and_r_i_1\ : label is "soft_lutpair427"; + attribute srl_bus_name : string; + attribute srl_bus_name of \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0] "; + attribute srl_name : string; + attribute srl_name of \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 "; + attribute srl_bus_name of \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3] "; + attribute srl_name of \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 "; + attribute srl_bus_name of \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4] "; + attribute srl_name of \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 "; + attribute srl_bus_name of \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7] "; + attribute srl_name of \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 "; + attribute SOFT_HLUTNM of idelay_ld_done_i_2 : label is "soft_lutpair433"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_26\ : label is "soft_lutpair432"; + attribute SOFT_HLUTNM of \init_state_r[1]_i_27\ : label is "soft_lutpair431"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_32\ : label is "soft_lutpair431"; + attribute SOFT_HLUTNM of \init_state_r[2]_i_33\ : label is "soft_lutpair438"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_31\ : label is "soft_lutpair438"; + attribute SOFT_HLUTNM of \init_state_r[4]_i_36\ : label is "soft_lutpair432"; + attribute SOFT_HLUTNM of \not_empty_wait_cnt[0]_i_1\ : label is "soft_lutpair440"; + attribute SOFT_HLUTNM of \not_empty_wait_cnt[1]_i_1\ : label is "soft_lutpair440"; + attribute SOFT_HLUTNM of \not_empty_wait_cnt[2]_i_1\ : label is "soft_lutpair436"; + attribute SOFT_HLUTNM of \not_empty_wait_cnt[3]_i_1\ : label is "soft_lutpair436"; + attribute SOFT_HLUTNM of \not_empty_wait_cnt[4]_i_2\ : label is "soft_lutpair429"; + attribute srl_name of rd_active_r3_reg_srl2 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3_reg_srl2 "; + attribute SOFT_HLUTNM of \tap_inc_wait_cnt[0]_i_1\ : label is "soft_lutpair439"; + attribute SOFT_HLUTNM of \tap_inc_wait_cnt[1]_i_1\ : label is "soft_lutpair439"; + attribute SOFT_HLUTNM of \tap_inc_wait_cnt[2]_i_1\ : label is "soft_lutpair437"; + attribute SOFT_HLUTNM of \tap_inc_wait_cnt[3]_i_2\ : label is "soft_lutpair437"; + attribute SOFT_HLUTNM of wrcal_done_i_1 : label is "soft_lutpair430"; + attribute SOFT_HLUTNM of \wrcal_dqs_cnt_r[1]_i_1\ : label is "soft_lutpair434"; + attribute syn_maxfan : string; + attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[0]\ : label is "10"; + attribute syn_maxfan of \wrcal_dqs_cnt_r_reg[1]\ : label is "10"; + attribute srl_name of wrcal_pat_resume_r2_reg_srl2 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 "; +begin + E(0) <= \^e\(0); + Q(1 downto 0) <= \^q\(1 downto 0); + early1_data_reg_0 <= \^early1_data_reg_0\; + phy_if_reset_w <= \^phy_if_reset_w\; + wrcal_done_reg_0 <= \^wrcal_done_reg_0\; + wrcal_sanity_chk_done_reg_0 <= \^wrcal_sanity_chk_done_reg_0\; + wrlvl_byte_redo <= \^wrlvl_byte_redo\; +cal2_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFEFFF00002000" + ) + port map ( + I0 => p_1_in, + I1 => \cal2_state_r_reg_n_0_[3]\, + I2 => \cal2_state_r_reg_n_0_[2]\, + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => \cal2_state_r_reg_n_0_[0]\, + I5 => cal2_done_r, + O => cal2_done_r_i_1_n_0 + ); +cal2_done_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => wrcal_sanity_chk_r_reg_n_0, + I1 => wrcal_sanity_chk, + O => p_1_in + ); +cal2_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal2_done_r_i_1_n_0, + Q => cal2_done_r, + R => idelay_ld_reg_0(0) + ); +cal2_if_reset_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFBABF00008A80" + ) + port map ( + I0 => cal2_if_reset_i_2_n_0, + I1 => cal2_if_reset_i_3_n_0, + I2 => \cal2_state_r_reg_n_0_[0]\, + I3 => cal2_if_reset_i_4_n_0, + I4 => \cal2_state_r_reg_n_0_[3]\, + I5 => \^phy_if_reset_w\, + O => cal2_if_reset_i_1_n_0 + ); +cal2_if_reset_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"004F0040F000F000" + ) + port map ( + I0 => \^e\(0), + I1 => rd_active_r1, + I2 => \cal2_state_r_reg_n_0_[0]\, + I3 => \cal2_state_r_reg_n_0_[2]\, + I4 => wrcal_sanity_chk_r_reg_n_0, + I5 => \cal2_state_r_reg_n_0_[1]\, + O => cal2_if_reset_i_2_n_0 + ); +cal2_if_reset_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FF000040FF40FF" + ) + port map ( + I0 => \^e\(0), + I1 => wrlvl_byte_done, + I2 => rd_active_r1, + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => idelay_ld_done_i_2_n_0, + I5 => \cal2_state_r_reg_n_0_[2]\, + O => cal2_if_reset_i_3_n_0 + ); +cal2_if_reset_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80FFFFFF800000" + ) + port map ( + I0 => prech_done, + I1 => cal2_prech_req_r_i_2_n_0, + I2 => wrcal_sanity_chk_r_reg_n_0, + I3 => \cal2_state_r_reg_n_0_[2]\, + I4 => \cal2_state_r_reg_n_0_[1]\, + I5 => cal2_if_reset_i_5_n_0, + O => cal2_if_reset_i_4_n_0 + ); +cal2_if_reset_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"8000FFFF80000000" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(2), + I1 => tap_inc_wait_cnt_reg(0), + I2 => tap_inc_wait_cnt_reg(1), + I3 => tap_inc_wait_cnt_reg(3), + I4 => \cal2_state_r_reg_n_0_[2]\, + I5 => \cal2_state_r_reg[0]_0\, + O => cal2_if_reset_i_5_n_0 + ); +cal2_if_reset_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal2_if_reset_i_1_n_0, + Q => \^phy_if_reset_w\, + R => SR(0) + ); +cal2_prech_req_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000010110000" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[3]\, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => cal2_prech_req_r_i_2_n_0, + I3 => wrcal_sanity_chk_r_reg_n_0, + I4 => \cal2_state_r_reg_n_0_[1]\, + I5 => \cal2_state_r_reg_n_0_[0]\, + O => cal2_prech_req_r_i_1_n_0 + ); +cal2_prech_req_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + I1 => wrcal_dqs_cnt_r(1), + O => cal2_prech_req_r_i_2_n_0 + ); +cal2_prech_req_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal2_prech_req_r_i_1_n_0, + Q => cal2_prech_req_r, + R => idelay_ld_reg_0(0) + ); +\cal2_state_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FF5D005D" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[2]\, + I1 => idelay_ld_done_reg_n_0, + I2 => wrcal_sanity_chk_r_reg_n_0, + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => \cal2_state_r[0]_i_4_n_0\, + I5 => \cal2_state_r_reg_n_0_[3]\, + O => \cal2_state_r[0]_i_2_n_0\ + ); +\cal2_state_r[0]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CCE2" + ) + port map ( + I0 => \cal2_state_r[0]_i_5_n_0\, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => tap_inc_wait_cnt_reg(0), + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => \cal2_state_r_reg_n_0_[3]\, + O => \cal2_state_r[0]_i_3_n_0\ + ); +\cal2_state_r[0]_i_4\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00DF" + ) + port map ( + I0 => prech_done, + I1 => wrcal_dqs_cnt_r(1), + I2 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + I3 => \cal2_state_r_reg_n_0_[2]\, + O => \cal2_state_r[0]_i_4_n_0\ + ); +\cal2_state_r[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000555100000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\, + I1 => idelay_ld_done_reg_n_0, + I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + I4 => wrcal_sanity_chk_r_reg_n_0, + I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + O => \cal2_state_r[0]_i_5_n_0\ + ); +\cal2_state_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FF000055007500" + ) + port map ( + I0 => prech_done, + I1 => wrcal_dqs_cnt_r(1), + I2 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => wrcal_sanity_chk_r_reg_n_0, + I5 => \cal2_state_r_reg_n_0_[2]\, + O => \cal2_state_r[1]_i_2_n_0\ + ); +\cal2_state_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFA800A8" + ) + port map ( + I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + I1 => \cal2_state_r[1]_i_4_n_0\, + I2 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\, + I3 => \cal2_state_r_reg_n_0_[2]\, + I4 => tap_inc_wait_cnt_reg(1), + I5 => \cal2_state_r_reg_n_0_[1]\, + O => \cal2_state_r[1]_i_3_n_0\ + ); +\cal2_state_r[1]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0E" + ) + port map ( + I0 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I2 => wrcal_sanity_chk_r_reg_n_0, + O => \cal2_state_r[1]_i_4_n_0\ + ); +\cal2_state_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4F4AFFFF4F4A0000" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[1]\, + I1 => tap_inc_wait_cnt_reg(2), + I2 => \cal2_state_r_reg_n_0_[2]\, + I3 => \cal2_state_r[2]_i_2_n_0\, + I4 => \cal2_state_r_reg_n_0_[0]\, + I5 => \cal2_state_r[2]_i_3_n_0\, + O => \cal2_state_r[2]_i_1_n_0\ + ); +\cal2_state_r[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000100000000" + ) + port map ( + I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\, + I1 => idelay_ld_done_reg_n_0, + I2 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + I3 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I4 => wrcal_sanity_chk_r_reg_n_0, + I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + O => \cal2_state_r[2]_i_2_n_0\ + ); +\cal2_state_r[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00FF00005D005D00" + ) + port map ( + I0 => prech_done, + I1 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + I2 => wrcal_dqs_cnt_r(1), + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => wrcal_sanity_chk_r_reg_n_0, + I5 => \cal2_state_r_reg_n_0_[2]\, + O => \cal2_state_r[2]_i_3_n_0\ + ); +\cal2_state_r[3]_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \not_empty_wait_cnt_reg_n_0_[2]\, + I1 => \not_empty_wait_cnt_reg_n_0_[1]\, + I2 => \not_empty_wait_cnt_reg_n_0_[0]\, + I3 => \not_empty_wait_cnt_reg_n_0_[3]\, + O => \cal2_state_r[3]_i_10_n_0\ + ); +\cal2_state_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00E2FFFF00E20000" + ) + port map ( + I0 => \cal2_state_r[3]_i_5_n_0\, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => tap_inc_wait_cnt_reg(3), + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => \cal2_state_r_reg_n_0_[0]\, + I5 => \cal2_state_r_reg_n_0_[3]\, + O => \cal2_state_r[3]_i_2_n_0\ + ); +\cal2_state_r[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"45404F4F45404A4A" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[3]\, + I1 => \cal2_state_r[3]_i_6_n_0\, + I2 => \cal2_state_r_reg_n_0_[1]\, + I3 => \cal2_state_r[3]_i_7_n_0\, + I4 => \cal2_state_r_reg_n_0_[2]\, + I5 => \cal2_state_r_reg[0]_0\, + O => \cal2_state_r[3]_i_3_n_0\ + ); +\cal2_state_r[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEE222E2" + ) + port map ( + I0 => \cal2_state_r[3]_i_8_n_0\, + I1 => \cal2_state_r_reg_n_0_[1]\, + I2 => \cal2_state_r[3]_i_9_n_0\, + I3 => \cal2_state_r_reg_n_0_[2]\, + I4 => \cal2_state_r[3]_i_7_n_0\, + I5 => \cal2_state_r_reg_n_0_[3]\, + O => \cal2_state_r[3]_i_4_n_0\ + ); +\cal2_state_r[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"55550004FFFFFFFF" + ) + port map ( + I0 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\, + I1 => idelay_ld_done_reg_n_0, + I2 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + I3 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I4 => wrcal_sanity_chk_r_reg_n_0, + I5 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + O => \cal2_state_r[3]_i_5_n_0\ + ); +\cal2_state_r[3]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3B3B3B3B38083838" + ) + port map ( + I0 => wrcal_sanity_chk, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => wrcal_sanity_chk_r_reg_n_0, + I3 => wrcal_dqs_cnt_r(1), + I4 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + I5 => prech_done, + O => \cal2_state_r[3]_i_6_n_0\ + ); +\cal2_state_r[3]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(2), + I1 => tap_inc_wait_cnt_reg(0), + I2 => tap_inc_wait_cnt_reg(1), + I3 => tap_inc_wait_cnt_reg(3), + O => \cal2_state_r[3]_i_7_n_0\ + ); +\cal2_state_r[3]_i_8\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BBBBB888" + ) + port map ( + I0 => idelay_ld_done_i_2_n_0, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => \not_empty_wait_cnt_reg_n_0_[4]\, + I3 => \cal2_state_r[3]_i_10_n_0\, + I4 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + O => \cal2_state_r[3]_i_8_n_0\ + ); +\cal2_state_r[3]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => rd_active_r1, + I1 => wrlvl_byte_done, + I2 => \^e\(0), + O => \cal2_state_r[3]_i_9_n_0\ + ); +\cal2_state_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => cal2_state_r, + D => \cal2_state_r_reg[0]_i_1_n_0\, + Q => \cal2_state_r_reg_n_0_[0]\, + R => idelay_ld_reg_0(0) + ); +\cal2_state_r_reg[0]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \cal2_state_r[0]_i_2_n_0\, + I1 => \cal2_state_r[0]_i_3_n_0\, + O => \cal2_state_r_reg[0]_i_1_n_0\, + S => \cal2_state_r_reg_n_0_[0]\ + ); +\cal2_state_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => cal2_state_r, + D => \cal2_state_r_reg[1]_i_1_n_0\, + Q => \cal2_state_r_reg_n_0_[1]\, + R => idelay_ld_reg_0(0) + ); +\cal2_state_r_reg[1]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \cal2_state_r[1]_i_2_n_0\, + I1 => \cal2_state_r[1]_i_3_n_0\, + O => \cal2_state_r_reg[1]_i_1_n_0\, + S => \cal2_state_r_reg_n_0_[0]\ + ); +\cal2_state_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => cal2_state_r, + D => \cal2_state_r[2]_i_1_n_0\, + Q => \cal2_state_r_reg_n_0_[2]\, + R => idelay_ld_reg_0(0) + ); +\cal2_state_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => cal2_state_r, + D => \cal2_state_r[3]_i_2_n_0\, + Q => \cal2_state_r_reg_n_0_[3]\, + R => idelay_ld_reg_0(0) + ); +\cal2_state_r_reg[3]_i_1\: unisim.vcomponents.MUXF7 + port map ( + I0 => \cal2_state_r[3]_i_3_n_0\, + I1 => \cal2_state_r[3]_i_4_n_0\, + O => cal2_state_r, + S => \cal2_state_r_reg_n_0_[0]\ + ); +early1_data_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I1 => \cal2_state_r_reg_n_0_[1]\, + I2 => early1_data_i_2_n_0, + I3 => \^early1_data_reg_0\, + O => early1_data_i_1_n_0 + ); +early1_data_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"45400000" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[3]\, + I1 => early1_data_i_3_n_0, + I2 => \cal2_state_r_reg_n_0_[1]\, + I3 => wrlvl_byte_redo_i_3_n_0, + I4 => \cal2_state_r_reg_n_0_[0]\, + O => early1_data_i_2_n_0 + ); +early1_data_i_3: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \^e\(0), + I1 => wrlvl_byte_done, + I2 => rd_active_r1, + I3 => \cal2_state_r_reg_n_0_[2]\, + O => early1_data_i_3_n_0 + ); +early1_data_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => early1_data_i_1_n_0, + Q => \^early1_data_reg_0\, + R => idelay_ld_reg_0(0) + ); +early2_data_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"04FF0400" + ) + port map ( + I0 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + I2 => \cal2_state_r_reg_n_0_[1]\, + I3 => early1_data_i_2_n_0, + I4 => early2_data_reg_n_0, + O => early2_data_i_1_n_0 + ); +early2_data_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => early2_data_i_1_n_0, + Q => early2_data_reg_n_0, + R => idelay_ld_reg_0(0) + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\, + R => '0' + ); +\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + Q => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\, + R => '0' + ); +\gen_pat_match_div4.early1_data_match_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early1_match_rise0_and_r, + I1 => early1_match_fall3_and_r, + I2 => early1_match_fall0_and_r, + I3 => early1_match_fall2_and_r, + I4 => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\, + O => early1_data_match_r0 + ); +\gen_pat_match_div4.early1_data_match_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => early1_match_rise2_and_r, + I1 => early1_match_rise3_and_r, + I2 => early1_match_rise1_and_r, + I3 => early1_match_fall1_and_r, + O => \gen_pat_match_div4.early1_data_match_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_data_match_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => early1_data_match_r0, + Q => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.early1_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early1_match_fall0_r(2), + I1 => early1_match_fall0_r(0), + I2 => early1_match_fall0_r(6), + I3 => early1_match_fall0_r(4), + I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => early1_match_fall0_r(1), + I1 => early1_match_fall0_r(3), + I2 => early1_match_fall0_r(5), + I3 => early1_match_fall0_r(7), + O => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_fall0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0\, + Q => early1_match_fall0_and_r, + R => '0' + ); +\gen_pat_match_div4.early1_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\, + O => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_fall1_r(0), + I1 => early2_match_fall1_r(5), + I2 => early2_match_fall1_r(1), + I3 => early2_match_fall1_r(4), + O => \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_fall1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0\, + Q => early1_match_fall1_and_r, + R => '0' + ); +\gen_pat_match_div4.early1_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\, + I3 => early2_match_fall2_r(7), + I4 => early2_match_fall2_r(3), + O => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\, + I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\, + O => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_fall2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0\, + Q => early1_match_fall2_and_r, + R => '0' + ); +\gen_pat_match_div4.early1_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\, + O => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_fall3_r(1), + I1 => early2_match_fall3_r(5), + I2 => early2_match_fall3_r(3), + I3 => early2_match_fall3_r(7), + O => \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_fall3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0\, + Q => early1_match_fall3_and_r, + R => '0' + ); +\gen_pat_match_div4.early1_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early1_match_rise0_r(2), + I1 => early1_match_rise0_r(0), + I2 => early1_match_rise0_r(6), + I3 => early1_match_rise0_r(4), + I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => early1_match_rise0_r(1), + I1 => early1_match_rise0_r(3), + I2 => early1_match_rise0_r(5), + I3 => early1_match_rise0_r(7), + O => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_rise0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0\, + Q => early1_match_rise0_and_r, + R => '0' + ); +\gen_pat_match_div4.early1_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\, + O => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_rise1_r(0), + I1 => early2_match_rise1_r(5), + I2 => early2_match_rise1_r(1), + I3 => early2_match_rise1_r(4), + O => \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_rise1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0\, + Q => early1_match_rise1_and_r, + R => '0' + ); +\gen_pat_match_div4.early1_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => early2_match_rise2_r(7), + I1 => early2_match_rise2_r(6), + I2 => early2_match_rise2_r(3), + I3 => early2_match_rise2_r(2), + I4 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_rise2_r(0), + I1 => early2_match_rise2_r(4), + I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\, + O => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_rise2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0\, + Q => early1_match_rise2_and_r, + R => '0' + ); +\gen_pat_match_div4.early1_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\, + I1 => early2_match_rise3_r(5), + I2 => early2_match_rise3_r(1), + I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\, + O => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early1_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\, + I1 => early2_match_rise3_r(7), + I2 => early2_match_rise3_r(3), + I3 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\, + O => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early1_match_rise3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0\, + Q => early1_match_rise3_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_data_match_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early2_match_rise3_and_r, + I1 => early2_match_fall2_and_r, + I2 => early2_match_fall1_and_r, + I3 => early2_match_rise0_and_r, + I4 => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\, + O => early2_data_match_r0 + ); +\gen_pat_match_div4.early2_data_match_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => early2_match_fall0_and_r, + I1 => early2_match_rise2_and_r, + I2 => early2_match_rise1_and_r, + I3 => early2_match_fall3_and_r, + O => \gen_pat_match_div4.early2_data_match_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_data_match_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => early2_data_match_r0, + Q => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.early2_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\, + I1 => early2_match_fall0_r(3), + I2 => early2_match_fall0_r(1), + I3 => early2_match_fall0_r(7), + I4 => early2_match_fall0_r(5), + O => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_fall0_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_fall0_r(4), + I1 => early2_match_fall0_r(6), + I2 => early2_match_fall0_r(0), + I3 => early2_match_fall0_r(2), + O => \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_fall0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0\, + Q => early2_match_fall0_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => early2_match_fall1_r(4), + I1 => early2_match_fall1_r(1), + I2 => early2_match_fall1_r(5), + I3 => early2_match_fall1_r(0), + I4 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_fall1_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_fall1_r(2), + I1 => early2_match_fall1_r(7), + I2 => early2_match_fall1_r(3), + I3 => early2_match_fall1_r(6), + O => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_fall1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0\, + Q => early2_match_fall1_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early2_match_fall2_r(6), + I1 => early2_match_fall2_r(1), + I2 => early2_match_fall2_r(7), + I3 => early2_match_fall2_r(0), + I4 => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_fall2_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => early2_match_fall2_r(2), + I1 => early2_match_fall2_r(5), + I2 => early2_match_fall2_r(3), + I3 => early2_match_fall2_r(4), + O => \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_fall2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0\, + Q => early2_match_fall2_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => early2_match_fall3_r(7), + I1 => early2_match_fall3_r(3), + I2 => early2_match_fall3_r(5), + I3 => early2_match_fall3_r(1), + I4 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_fall3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_fall3_r(0), + I1 => early2_match_fall3_r(6), + I2 => early2_match_fall3_r(4), + I3 => early2_match_fall3_r(2), + O => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_fall3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0\, + Q => early2_match_fall3_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\, + I1 => early2_match_rise0_r(3), + I2 => early2_match_rise0_r(1), + I3 => early2_match_rise0_r(7), + I4 => early2_match_rise0_r(5), + O => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_rise0_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_rise0_r(4), + I1 => early2_match_rise0_r(6), + I2 => early2_match_rise0_r(0), + I3 => early2_match_rise0_r(2), + O => \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_rise0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0\, + Q => early2_match_rise0_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => early2_match_rise1_r(4), + I1 => early2_match_rise1_r(1), + I2 => early2_match_rise1_r(5), + I3 => early2_match_rise1_r(0), + I4 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_rise1_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_rise1_r(2), + I1 => early2_match_rise1_r(7), + I2 => early2_match_rise1_r(3), + I3 => early2_match_rise1_r(6), + O => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_rise1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0\, + Q => early2_match_rise1_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\, + I1 => early2_match_rise2_r(4), + I2 => early2_match_rise2_r(0), + I3 => early2_match_rise2_r(5), + I4 => early2_match_rise2_r(1), + O => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_rise2_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => early2_match_rise2_r(2), + I1 => early2_match_rise2_r(3), + I2 => early2_match_rise2_r(6), + I3 => early2_match_rise2_r(7), + O => \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_rise2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0\, + Q => early2_match_rise2_and_r, + R => '0' + ); +\gen_pat_match_div4.early2_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early2_match_rise3_r(6), + I1 => early2_match_rise3_r(5), + I2 => early2_match_rise3_r(7), + I3 => early2_match_rise3_r(4), + I4 => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\, + O => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.early2_match_rise3_and_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => early2_match_rise3_r(0), + I1 => early2_match_rise3_r(3), + I2 => early2_match_rise3_r(1), + I3 => early2_match_rise3_r(2), + O => \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0\ + ); +\gen_pat_match_div4.early2_match_rise3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0\, + Q => early2_match_rise3_and_r, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227\, + Q => early1_match_fall0_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263\, + O => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0\, + Q => early2_match_fall1_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219\, + Q => \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255\, + O => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0\, + Q => early1_match_rise0_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211\, + Q => early2_match_rise1_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241\, + Q => early2_match_fall2_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249\, + O => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0\, + Q => early2_match_rise3_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227\, + O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0\, + Q => early2_match_fall0_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263\, + Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241\, + O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219\, + O => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0\, + Q => early2_match_fall3_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255\, + Q => early2_match_rise0_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211\, + O => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0\, + Q => early2_match_rise2_r(0), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249\, + Q => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264\, + Q => early2_match_fall1_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220\, + O => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0\, + Q => early2_match_fall3_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212\, + O => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0\, + Q => early2_match_rise1_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250\, + Q => early2_match_rise3_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228\, + Q => early2_match_fall0_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242\, + O => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0\, + Q => early2_match_fall2_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256\, + O => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0\, + Q => early2_match_rise0_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235\, + Q => early2_match_rise2_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228\, + O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0\, + Q => early1_match_fall0_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264\, + O => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242\, + Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220\, + Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256\, + Q => early1_match_rise0_r(1), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212\, + Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235\, + O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250\, + O => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229\, + Q => early1_match_fall0_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265\, + O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243\, + Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221\, + O => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257\, + O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0\, + Q => early1_match_rise0_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213\, + Q => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236\, + O => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0\, + Q => early2_match_rise2_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251\, + Q => early2_match_rise3_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229\, + O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0\, + Q => early2_match_fall0_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265\, + Q => early2_match_fall1_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243\, + O => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0\, + Q => early2_match_fall2_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221\, + Q => early2_match_fall3_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257\, + Q => early2_match_rise0_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213\, + O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0\, + Q => early2_match_rise1_r(2), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236\, + Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251\, + O => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266\, + Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244\, + O => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0\, + Q => early2_match_fall2_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214\, + O => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237\, + Q => early2_match_rise2_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230\, + Q => early2_match_fall0_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258\, + O => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0\, + Q => early2_match_rise0_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230\, + O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0\, + Q => early1_match_fall0_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266\, + O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0\, + Q => early2_match_fall1_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244\, + Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_222\, + O => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0\, + Q => early2_match_fall3_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258\, + Q => early1_match_rise0_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214\, + Q => early2_match_rise1_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237\, + O => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0\, + Q => early2_match_rise3_r(3), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231\, + Q => early1_match_fall0_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267\, + O => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0\, + Q => early2_match_fall1_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223\, + Q => \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259\, + O => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0\, + Q => early1_match_rise0_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215\, + Q => early2_match_rise1_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245\, + Q => early2_match_fall2_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252\, + O => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0\, + Q => early2_match_rise3_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231\, + O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0\, + Q => early2_match_fall0_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267\, + Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245\, + O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223\, + O => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0\, + Q => early2_match_fall3_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259\, + Q => early2_match_rise0_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215\, + O => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0\, + Q => early2_match_rise2_r(4), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252\, + Q => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268\, + Q => early2_match_fall1_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224\, + O => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0\, + Q => early2_match_fall3_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216\, + O => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0\, + Q => early2_match_rise1_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253\, + Q => early2_match_rise3_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232\, + Q => early2_match_fall0_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246\, + O => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0\, + Q => early2_match_fall2_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260\, + O => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0\, + Q => early2_match_rise0_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238\, + Q => early2_match_rise2_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232\, + O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0\, + Q => early1_match_fall0_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268\, + O => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246\, + Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224\, + Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260\, + Q => early1_match_rise0_r(5), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216\, + Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238\, + O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253\, + O => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233\, + Q => early1_match_fall0_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269\, + O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247\, + Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225\, + O => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261\, + O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0\, + Q => early1_match_rise0_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217\, + Q => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239\, + O => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0\, + Q => early2_match_rise2_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254\, + Q => early2_match_rise3_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233\, + O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0\, + Q => early2_match_fall0_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269\, + Q => early2_match_fall1_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247\, + O => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0\, + Q => early2_match_fall2_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225\, + Q => early2_match_fall3_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261\, + Q => early2_match_rise0_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217\, + O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0\, + Q => early2_match_rise1_r(6), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239\, + Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254\, + O => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270\, + Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248\, + O => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0\, + Q => early2_match_fall2_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218\, + O => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240\, + Q => early2_match_rise2_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234\, + Q => early2_match_fall0_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262\, + O => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0\, + Q => early2_match_rise0_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234\, + O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0\, + Q => early1_match_fall0_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270\, + O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0\, + Q => early2_match_fall1_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248\, + Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_226\, + O => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0\, + Q => early2_match_fall3_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262\, + Q => early1_match_rise0_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218\, + Q => early2_match_rise1_r(7), + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240\, + O => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\ + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0\, + Q => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\, + R => '0' + ); +\gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0\, + Q => early2_match_rise3_r(7), + R => '0' + ); +\gen_pat_match_div4.pat_data_match_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => pat_match_fall0_and_r, + I1 => pat_match_rise2_and_r, + I2 => pat_match_rise1_and_r, + I3 => pat_match_fall1_and_r, + I4 => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\, + O => pat_data_match_r0 + ); +\gen_pat_match_div4.pat_data_match_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => pat_match_rise0_and_r, + I1 => pat_match_rise3_and_r, + I2 => pat_match_fall3_and_r, + I3 => pat_match_fall2_and_r, + O => \gen_pat_match_div4.pat_data_match_r_i_2_n_0\ + ); +\gen_pat_match_div4.pat_data_match_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => pat_data_match_r0, + Q => \gen_pat_match_div4.pat_data_match_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.pat_data_match_valid_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_active_r3_reg_srl2_n_0, + Q => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + R => '0' + ); +\gen_pat_match_div4.pat_match_fall0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early2_match_fall0_r(2), + I1 => early2_match_fall0_r(0), + I2 => early2_match_fall0_r(6), + I3 => early2_match_fall0_r(4), + I4 => \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0\, + O => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_fall0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0\, + Q => pat_match_fall0_and_r, + R => '0' + ); +\gen_pat_match_div4.pat_match_fall1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg\, + O => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_fall1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0\, + Q => pat_match_fall1_and_r, + R => '0' + ); +\gen_pat_match_div4.pat_match_fall2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg\, + I3 => early2_match_fall2_r(6), + I4 => early2_match_fall2_r(2), + O => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_fall2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0\, + Q => pat_match_fall2_and_r, + R => '0' + ); +\gen_pat_match_div4.pat_match_fall3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg\, + I3 => early2_match_fall3_r(7), + I4 => early2_match_fall3_r(3), + O => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_fall3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0\, + Q => pat_match_fall3_and_r, + R => '0' + ); +\gen_pat_match_div4.pat_match_rise0_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00008000" + ) + port map ( + I0 => early2_match_rise0_r(2), + I1 => early2_match_rise0_r(0), + I2 => early2_match_rise0_r(6), + I3 => early2_match_rise0_r(4), + I4 => \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0\, + O => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_rise0_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0\, + Q => pat_match_rise0_and_r, + R => '0' + ); +\gen_pat_match_div4.pat_match_rise1_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg\, + O => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_rise1_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0\, + Q => pat_match_rise1_and_r, + R => '0' + ); +\gen_pat_match_div4.pat_match_rise2_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg\, + O => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_rise2_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0\, + Q => pat_match_rise2_and_r, + R => '0' + ); +\gen_pat_match_div4.pat_match_rise3_and_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80000000" + ) + port map ( + I0 => \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0\, + I1 => \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg\, + I2 => \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg\, + I3 => \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg\, + I4 => \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg\, + O => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\ + ); +\gen_pat_match_div4.pat_match_rise3_and_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0\, + Q => pat_match_rise3_and_r, + R => '0' + ); +\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227\, + R => '0' + ); +\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263\, + R => '0' + ); +\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241\, + R => '0' + ); +\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219\, + R => '0' + ); +\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255\, + R => '0' + ); +\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211\, + R => '0' + ); +\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + Q => \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0\ + ); +\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0]\, + Q => \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235\, + R => '0' + ); +\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1]\, + Q => \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236\, + R => '0' + ); +\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2]\, + Q => \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_222\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3]\, + Q => \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237\, + R => '0' + ); +\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + Q => \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0\ + ); +\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231\, + R => '0' + ); +\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267\, + R => '0' + ); +\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245\, + R => '0' + ); +\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223\, + R => '0' + ); +\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259\, + R => '0' + ); +\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215\, + R => '0' + ); +\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + Q => \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0\ + ); +\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4]\, + Q => \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238\, + R => '0' + ); +\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5]\, + Q => \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239\, + R => '0' + ); +\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6]\, + Q => \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_226\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7]\, + Q => \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240\, + R => '0' + ); +\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2\: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + Q => \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0\ + ); +idelay_ld_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFCFF00000080" + ) + port map ( + I0 => idelay_ld_done_i_2_n_0, + I1 => \cal2_state_r_reg_n_0_[0]\, + I2 => \cal2_state_r_reg_n_0_[2]\, + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => \cal2_state_r_reg_n_0_[3]\, + I5 => idelay_ld_done_reg_n_0, + O => idelay_ld_done_i_1_n_0 + ); +idelay_ld_done_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0002" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(2), + I1 => tap_inc_wait_cnt_reg(0), + I2 => tap_inc_wait_cnt_reg(1), + I3 => tap_inc_wait_cnt_reg(3), + O => idelay_ld_done_i_2_n_0 + ); +idelay_ld_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_ld_done_i_1_n_0, + Q => idelay_ld_done_reg_n_0, + R => idelay_ld_reg_0(0) + ); +idelay_ld_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => idelay_ld_i_2_n_0, + I3 => idelay_ld, + O => idelay_ld_i_1_n_0 + ); +idelay_ld_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000540400000000" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[3]\, + I1 => \cal2_state_r[2]_i_2_n_0\, + I2 => \cal2_state_r_reg_n_0_[2]\, + I3 => idelay_ld_done_i_2_n_0, + I4 => \cal2_state_r_reg_n_0_[1]\, + I5 => \cal2_state_r_reg_n_0_[0]\, + O => idelay_ld_i_2_n_0 + ); +idelay_ld_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_ld_i_1_n_0, + Q => idelay_ld, + R => idelay_ld_reg_0(0) + ); +\idelay_tap_cnt_r[0][0][4]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FB" + ) + port map ( + I0 => idelay_ce_int, + I1 => idelay_ld, + I2 => \^q\(1), + O => cal1_dq_idel_ce_reg + ); +\idelay_tap_cnt_r[0][1][4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAEAAFFFFAEAA" + ) + port map ( + I0 => \idelay_tap_cnt_r_reg[0][1][4]\, + I1 => \^q\(0), + I2 => \^q\(1), + I3 => idelay_ld, + I4 => idelay_ce_int, + I5 => \idelay_tap_cnt_r_reg[0][1][4]_0\, + O => \rstdiv0_sync_r1_reg_rep__15\(0) + ); +\init_state_r[0]_i_26\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5555555515555555" + ) + port map ( + I0 => \^wrcal_sanity_chk_done_reg_0\, + I1 => \^wrcal_done_reg_0\, + I2 => wrlvl_done_r1, + I3 => D(0), + I4 => pi_dqs_found_done, + I5 => ddr3_lm_done_r, + O => wrcal_sanity_chk_done_reg_1 + ); +\init_state_r[1]_i_26\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7077" + ) + port map ( + I0 => D(0), + I1 => mem_init_done_r, + I2 => \^wrcal_done_reg_0\, + I3 => \^wrlvl_byte_redo\, + O => rdlvl_stg1_done_int_reg + ); +\init_state_r[1]_i_27\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \^wrcal_done_reg_0\, + I1 => wrlvl_done_r1, + I2 => D(0), + I3 => pi_dqs_found_done, + O => wrcal_done_reg_1 + ); +\init_state_r[2]_i_32\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EF" + ) + port map ( + I0 => \^wrlvl_byte_redo\, + I1 => wrlvl_done_r1, + I2 => pi_dqs_found_done, + O => wrlvl_byte_redo_reg_0 + ); +\init_state_r[2]_i_33\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^wrlvl_byte_redo\, + I1 => \^wrcal_done_reg_0\, + O => wrlvl_byte_redo_reg_2 + ); +\init_state_r[4]_i_31\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \^wrlvl_byte_redo\, + I1 => \init_state_r[4]_i_15\, + I2 => \^wrcal_done_reg_0\, + O => wrlvl_byte_redo_reg_1 + ); +\init_state_r[4]_i_36\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4F44" + ) + port map ( + I0 => D(0), + I1 => mem_init_done_r, + I2 => \^wrcal_done_reg_0\, + I3 => \^wrlvl_byte_redo\, + O => rdlvl_stg1_done_int_reg_0 + ); +\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF54440000" + ) + port map ( + I0 => calib_zero_inputs, + I1 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\, + I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\, + I3 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\, + I4 => idelay_ld, + I5 => idelay_ld_rst, + O => LD0_0 + ); +\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF45004400" + ) + port map ( + I0 => calib_zero_inputs, + I1 => \input_[9].iserdes_dq_.idelay_dq.idelaye2\, + I2 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\, + I3 => idelay_ld, + I4 => \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\, + I5 => idelay_ld_rst, + O => LD0 + ); +\not_empty_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \not_empty_wait_cnt_reg_n_0_[0]\, + O => p_0_in(0) + ); +\not_empty_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \not_empty_wait_cnt_reg_n_0_[0]\, + I1 => \not_empty_wait_cnt_reg_n_0_[1]\, + O => p_0_in(1) + ); +\not_empty_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \not_empty_wait_cnt_reg_n_0_[2]\, + I1 => \not_empty_wait_cnt_reg_n_0_[0]\, + I2 => \not_empty_wait_cnt_reg_n_0_[1]\, + O => p_0_in(2) + ); +\not_empty_wait_cnt[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \not_empty_wait_cnt_reg_n_0_[3]\, + I1 => \not_empty_wait_cnt_reg_n_0_[0]\, + I2 => \not_empty_wait_cnt_reg_n_0_[1]\, + I3 => \not_empty_wait_cnt_reg_n_0_[2]\, + O => p_0_in(3) + ); +\not_empty_wait_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFEFFFFFFFFFFFF" + ) + port map ( + I0 => \not_empty_wait_cnt_reg[4]_0\, + I1 => \cal2_state_r_reg_n_0_[3]\, + I2 => \cal2_state_r_reg_n_0_[1]\, + I3 => \cal2_state_r_reg_n_0_[2]\, + I4 => \cal2_state_r_reg_n_0_[0]\, + I5 => wrcal_rd_wait, + O => \not_empty_wait_cnt[4]_i_1_n_0\ + ); +\not_empty_wait_cnt[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"6AAAAAAA" + ) + port map ( + I0 => \not_empty_wait_cnt_reg_n_0_[4]\, + I1 => \not_empty_wait_cnt_reg_n_0_[2]\, + I2 => \not_empty_wait_cnt_reg_n_0_[1]\, + I3 => \not_empty_wait_cnt_reg_n_0_[0]\, + I4 => \not_empty_wait_cnt_reg_n_0_[3]\, + O => p_0_in(4) + ); +\not_empty_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(0), + Q => \not_empty_wait_cnt_reg_n_0_[0]\, + R => \not_empty_wait_cnt[4]_i_1_n_0\ + ); +\not_empty_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(1), + Q => \not_empty_wait_cnt_reg_n_0_[1]\, + R => \not_empty_wait_cnt[4]_i_1_n_0\ + ); +\not_empty_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(2), + Q => \not_empty_wait_cnt_reg_n_0_[2]\, + R => \not_empty_wait_cnt[4]_i_1_n_0\ + ); +\not_empty_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(3), + Q => \not_empty_wait_cnt_reg_n_0_[3]\, + R => \not_empty_wait_cnt[4]_i_1_n_0\ + ); +\not_empty_wait_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(4), + Q => \not_empty_wait_cnt_reg_n_0_[4]\, + R => \not_empty_wait_cnt[4]_i_1_n_0\ + ); +\po_stg2_wrcal_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + Q => \^q\(0), + R => '0' + ); +\po_stg2_wrcal_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_dqs_cnt_r(1), + Q => \^q\(1), + R => '0' + ); +rd_active_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^e\(0), + Q => rd_active_r1, + R => '0' + ); +rd_active_r3_reg_srl2: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => rd_active_r1, + Q => rd_active_r3_reg_srl2_n_0 + ); +rd_active_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_rddata_en, + Q => \^e\(0), + R => '0' + ); +\tap_inc_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(0), + O => \p_0_in__0\(0) + ); +\tap_inc_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(1), + I1 => tap_inc_wait_cnt_reg(0), + O => \p_0_in__0\(1) + ); +\tap_inc_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(2), + I1 => tap_inc_wait_cnt_reg(1), + I2 => tap_inc_wait_cnt_reg(0), + O => \p_0_in__0\(2) + ); +\tap_inc_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFAFEF" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[3]\, + I1 => \cal2_state_r_reg_n_0_[1]\, + I2 => \cal2_state_r_reg_n_0_[2]\, + I3 => \cal2_state_r_reg_n_0_[0]\, + I4 => \not_empty_wait_cnt_reg[4]_0\, + O => \tap_inc_wait_cnt[3]_i_1_n_0\ + ); +\tap_inc_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(3), + I1 => tap_inc_wait_cnt_reg(1), + I2 => tap_inc_wait_cnt_reg(0), + I3 => tap_inc_wait_cnt_reg(2), + O => \p_0_in__0\(3) + ); +\tap_inc_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(0), + Q => tap_inc_wait_cnt_reg(0), + R => \tap_inc_wait_cnt[3]_i_1_n_0\ + ); +\tap_inc_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(1), + Q => tap_inc_wait_cnt_reg(1), + R => \tap_inc_wait_cnt[3]_i_1_n_0\ + ); +\tap_inc_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(2), + Q => tap_inc_wait_cnt_reg(2), + R => \tap_inc_wait_cnt[3]_i_1_n_0\ + ); +\tap_inc_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\(3), + Q => tap_inc_wait_cnt_reg(3), + R => \tap_inc_wait_cnt[3]_i_1_n_0\ + ); +\wl_tap_count_r[5]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \^wrlvl_byte_redo\, + I1 => wrlvl_byte_redo_r, + O => done_dqs_dec237_out + ); +wrcal_done_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"45454500" + ) + port map ( + I0 => \not_empty_wait_cnt_reg[4]_0\, + I1 => wrcal_sanity_chk_r_reg_n_0, + I2 => wrcal_sanity_chk, + I3 => \^wrcal_done_reg_0\, + I4 => cal2_done_r, + O => wrcal_done_i_1_n_0 + ); +wrcal_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_done_i_1_n_0, + Q => \^wrcal_done_reg_0\, + R => '0' + ); +\wrcal_dqs_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFCFFF00001000" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[2]\, + I1 => \cal2_state_r_reg_n_0_[3]\, + I2 => \wrcal_dqs_cnt_r[0]_i_2_n_0\, + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => \cal2_state_r_reg_n_0_[0]\, + I5 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + O => \wrcal_dqs_cnt_r[0]_i_1_n_0\ + ); +\wrcal_dqs_cnt_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"33330033B8B888B8" + ) + port map ( + I0 => wrcal_sanity_chk, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => prech_done, + I3 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + I4 => wrcal_dqs_cnt_r(1), + I5 => wrcal_sanity_chk_r_reg_n_0, + O => \wrcal_dqs_cnt_r[0]_i_2_n_0\ + ); +\wrcal_dqs_cnt_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"1F20" + ) + port map ( + I0 => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => \wrcal_dqs_cnt_r[1]_i_2_n_0\, + I3 => wrcal_dqs_cnt_r(1), + O => \wrcal_dqs_cnt_r[1]_i_1_n_0\ + ); +\wrcal_dqs_cnt_r[1]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[3]\, + I1 => \wrcal_dqs_cnt_r[0]_i_2_n_0\, + I2 => \cal2_state_r_reg_n_0_[1]\, + I3 => \cal2_state_r_reg_n_0_[0]\, + O => \wrcal_dqs_cnt_r[1]_i_2_n_0\ + ); +\wrcal_dqs_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wrcal_dqs_cnt_r[0]_i_1_n_0\, + Q => \wrcal_dqs_cnt_r_reg_n_0_[0]\, + R => idelay_ld_reg_0(0) + ); +\wrcal_dqs_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wrcal_dqs_cnt_r[1]_i_1_n_0\, + Q => wrcal_dqs_cnt_r(1), + R => idelay_ld_reg_0(0) + ); +wrcal_pat_resume_r2_reg_srl2: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '0', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => wrcal_pat_resume_r, + Q => wrcal_pat_resume_r2_reg_srl2_n_0 + ); +wrcal_pat_resume_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8FFF800" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[2]\, + I1 => idelay_ld_done_reg_n_0, + I2 => \cal2_state_r_reg_n_0_[1]\, + I3 => wrcal_pat_resume_r_i_2_n_0, + I4 => wrcal_pat_resume_r, + O => wrcal_pat_resume_r_i_1_n_0 + ); +wrcal_pat_resume_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"08000800033C003C" + ) + port map ( + I0 => \cal2_state_r[3]_i_7_n_0\, + I1 => \cal2_state_r_reg_n_0_[0]\, + I2 => \cal2_state_r_reg_n_0_[3]\, + I3 => \cal2_state_r_reg_n_0_[2]\, + I4 => wrcal_pat_resume_r_i_3_n_0, + I5 => \cal2_state_r_reg_n_0_[1]\, + O => wrcal_pat_resume_r_i_2_n_0 + ); +wrcal_pat_resume_r_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000800000000000" + ) + port map ( + I0 => tap_inc_wait_cnt_reg(2), + I1 => idelay_ld_done_reg_n_0, + I2 => tap_inc_wait_cnt_reg(0), + I3 => tap_inc_wait_cnt_reg(1), + I4 => wrcal_sanity_chk_r_reg_n_0, + I5 => tap_inc_wait_cnt_reg(3), + O => wrcal_pat_resume_r_i_3_n_0 + ); +wrcal_pat_resume_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_pat_resume_r_i_1_n_0, + Q => wrcal_pat_resume_r, + R => idelay_ld_reg_0(0) + ); +wrcal_pat_resume_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_pat_resume_r2_reg_srl2_n_0, + Q => wrcal_resume_w, + R => '0' + ); +wrcal_prech_req_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => cal2_prech_req_r, + Q => wrcal_prech_req, + R => idelay_ld_reg_0(0) + ); +wrcal_sanity_chk_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF00004000" + ) + port map ( + I0 => \cal2_state_r_reg_n_0_[3]\, + I1 => \cal2_state_r_reg_n_0_[2]\, + I2 => wrcal_sanity_chk_r_reg_n_0, + I3 => \cal2_state_r_reg_n_0_[1]\, + I4 => \cal2_state_r_reg_n_0_[0]\, + I5 => \^wrcal_sanity_chk_done_reg_0\, + O => wrcal_sanity_chk_done_i_1_n_0 + ); +wrcal_sanity_chk_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_sanity_chk_done_i_1_n_0, + Q => \^wrcal_sanity_chk_done_reg_0\, + R => idelay_ld_reg_0(0) + ); +wrcal_sanity_chk_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrcal_sanity_chk, + Q => wrcal_sanity_chk_r_reg_n_0, + R => '0' + ); +wrlvl_byte_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_byte_done, + Q => wrlvl_byte_done_r, + R => '0' + ); +wrlvl_byte_redo_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0EFFFFFF0E000000" + ) + port map ( + I0 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + I1 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I2 => \cal2_state_r_reg_n_0_[1]\, + I3 => wrlvl_byte_redo_i_2_n_0, + I4 => \cal2_state_r_reg_n_0_[0]\, + I5 => \^wrlvl_byte_redo\, + O => wrlvl_byte_redo_i_1_n_0 + ); +wrlvl_byte_redo_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000022222E22" + ) + port map ( + I0 => wrlvl_byte_redo_i_3_n_0, + I1 => \cal2_state_r_reg_n_0_[1]\, + I2 => \cal2_state_r_reg_n_0_[2]\, + I3 => wrlvl_byte_done, + I4 => wrlvl_byte_done_r, + I5 => \cal2_state_r_reg_n_0_[3]\, + O => wrlvl_byte_redo_i_2_n_0 + ); +wrlvl_byte_redo_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000002220" + ) + port map ( + I0 => \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0\, + I1 => wrcal_sanity_chk_r_reg_n_0, + I2 => \gen_pat_match_div4.early1_data_match_r_reg_n_0\, + I3 => \gen_pat_match_div4.early2_data_match_r_reg_n_0\, + I4 => \gen_pat_match_div4.pat_data_match_r_reg_n_0\, + I5 => \cal2_state_r_reg_n_0_[2]\, + O => wrlvl_byte_redo_i_3_n_0 + ); +wrlvl_byte_redo_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_byte_redo_i_1_n_0, + Q => \^wrlvl_byte_redo\, + R => idelay_ld_reg_0(0) + ); +\wrlvl_redo_corse_inc[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"CCC000C0DDDDDDDD" + ) + port map ( + I0 => early2_data_reg_n_0, + I1 => \FSM_sequential_wl_state_r[4]_i_18\, + I2 => \FSM_sequential_wl_state_r[4]_i_18_0\(0), + I3 => \^q\(0), + I4 => \FSM_sequential_wl_state_r[4]_i_18_1\(0), + I5 => \^early1_data_reg_0\, + O => early2_data_reg_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_wrlvl is + port ( + wrlvl_byte_redo_r : out STD_LOGIC; + dqs_po_dec_done_reg_0 : out STD_LOGIC; + dqs_po_en_stg2_f : out STD_LOGIC; + po_cnt_dec_reg_0 : out STD_LOGIC; + wr_level_done_reg_0 : out STD_LOGIC; + wrlvl_rank_done : out STD_LOGIC; + dqs_po_stg2_f_incdec : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_0\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_1\ : out STD_LOGIC; + dqs_wl_po_stg2_c_incdec_reg_0 : out STD_LOGIC; + \calib_sel_reg[1]\ : out STD_LOGIC; + \calib_sel_reg[1]_0\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_2\ : out STD_LOGIC; + \calib_sel_reg[0]\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_3\ : out STD_LOGIC; + \final_coarse_tap_reg[1][1]_0\ : out STD_LOGIC; + \final_coarse_tap_reg[1][0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \final_coarse_tap_reg[0][0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + done_dqs_tap_inc : out STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ : out STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ : out STD_LOGIC; + \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ : out STD_LOGIC; + cmd_delay_start0 : out STD_LOGIC; + wrlvl_byte_done : out STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + wrlvl_byte_redo : in STD_LOGIC; + wr_level_start_r_reg_0 : in STD_LOGIC; + dqs_po_en_stg2_f_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dqs_count_r_reg[0]_0\ : in STD_LOGIC; + wl_edge_detect_valid_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + phaser_out : in STD_LOGIC; + phaser_out_0 : in STD_LOGIC; + phaser_out_1 : in STD_LOGIC; + calib_zero_inputs : in STD_LOGIC; + po_enstg2_f : in STD_LOGIC_VECTOR ( 0 to 0 ); + ck_po_stg2_f_indec : in STD_LOGIC; + wl_sm_start : in STD_LOGIC; + done_dqs_dec237_out : in STD_LOGIC; + \rd_data_edge_detect_r_reg[1]_0\ : in STD_LOGIC; + \dqs_count_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \FSM_sequential_wl_state_r[4]_i_13_0\ : in STD_LOGIC; + \po_rdval_cnt_reg[8]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \wrlvl_redo_corse_inc[1]_i_2_0\ : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\ : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_2\ : in STD_LOGIC; + RSTB : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ : in STD_LOGIC; + \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1\ : in STD_LOGIC; + \calib_sel_reg[0]_0\ : in STD_LOGIC; + calib_sel15_out : in STD_LOGIC; + \calib_sel_reg[0]_1\ : in STD_LOGIC; + \calib_sel_reg[0]_2\ : in STD_LOGIC; + calib_sel0 : in STD_LOGIC; + \calib_sel_reg[0]_3\ : in STD_LOGIC; + \dqs_count_r_reg[0]_rep_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\ : in STD_LOGIC; + \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\ : in STD_LOGIC; + \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \single_rank.done_dqs_dec_reg_0\ : in STD_LOGIC; + SS : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_wrlvl : entity is "mig_7series_v4_2_ddr_phy_wrlvl"; +end ddr3_mig_7series_v4_2_ddr_phy_wrlvl; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_wrlvl is + signal \FSM_sequential_wl_state_r[0]_i_10_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_11_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_12_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_7_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_8_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[0]_i_9_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_10_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_11_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_7_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_8_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[1]_i_9_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_10_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_11_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_12_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_13_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_14_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_7_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_8_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[2]_i_9_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_7_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_8_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[3]_i_9_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_10_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_11_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_12_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_13_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_14_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_15_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_16_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_17_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_18_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_19_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_1_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_20_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_2_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_3_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_4_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_5_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_6_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_7_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_8_n_0\ : STD_LOGIC; + signal \FSM_sequential_wl_state_r[4]_i_9_n_0\ : STD_LOGIC; + signal \^cmd_delay_start0\ : STD_LOGIC; + signal corse_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \corse_cnt[0][0]_i_1_n_0\ : STD_LOGIC; + signal \corse_cnt[0][0]_i_3_n_0\ : STD_LOGIC; + signal \corse_cnt[0][0]_i_4_n_0\ : STD_LOGIC; + signal \corse_cnt[0][0]_i_5_n_0\ : STD_LOGIC; + signal \corse_cnt[0][1]_i_1_n_0\ : STD_LOGIC; + signal \corse_cnt[0][1]_i_3_n_0\ : STD_LOGIC; + signal \corse_cnt[0][1]_i_4_n_0\ : STD_LOGIC; + signal \corse_cnt[0][2]_i_1_n_0\ : STD_LOGIC; + signal \corse_cnt[0][2]_i_3_n_0\ : STD_LOGIC; + signal \corse_cnt[0][2]_i_4_n_0\ : STD_LOGIC; + signal \corse_cnt[0][2]_i_5_n_0\ : STD_LOGIC; + signal \corse_cnt[0][2]_i_6_n_0\ : STD_LOGIC; + signal \corse_cnt[0][2]_i_7_n_0\ : STD_LOGIC; + signal \corse_cnt[0][2]_i_8_n_0\ : STD_LOGIC; + signal \corse_cnt[1][0]_i_1_n_0\ : STD_LOGIC; + signal \corse_cnt[1][1]_i_1_n_0\ : STD_LOGIC; + signal \corse_cnt[1][2]_i_1_n_0\ : STD_LOGIC; + signal \corse_cnt[1][2]_i_2_n_0\ : STD_LOGIC; + signal \corse_cnt[1][2]_i_3_n_0\ : STD_LOGIC; + signal \corse_cnt_reg_n_0_[0][0]\ : STD_LOGIC; + signal \corse_cnt_reg_n_0_[0][1]\ : STD_LOGIC; + signal \corse_cnt_reg_n_0_[0][2]\ : STD_LOGIC; + signal \corse_cnt_reg_n_0_[1][0]\ : STD_LOGIC; + signal \corse_cnt_reg_n_0_[1][1]\ : STD_LOGIC; + signal \corse_cnt_reg_n_0_[1][2]\ : STD_LOGIC; + signal corse_dec : STD_LOGIC_VECTOR ( 2 to 2 ); + signal \corse_dec[0][0]_i_1_n_0\ : STD_LOGIC; + signal \corse_dec[0][1]_i_1_n_0\ : STD_LOGIC; + signal \corse_dec[0][2]_i_1_n_0\ : STD_LOGIC; + signal \corse_dec[0][2]_i_2_n_0\ : STD_LOGIC; + signal \corse_dec[1][0]_i_1_n_0\ : STD_LOGIC; + signal \corse_dec[1][1]_i_1_n_0\ : STD_LOGIC; + signal \corse_dec[1][1]_i_2_n_0\ : STD_LOGIC; + signal \corse_dec[1][1]_i_3_n_0\ : STD_LOGIC; + signal \corse_dec[1][2]_i_1_n_0\ : STD_LOGIC; + signal \corse_dec[1][2]_i_3_n_0\ : STD_LOGIC; + signal \corse_dec[1][2]_i_4_n_0\ : STD_LOGIC; + signal \corse_dec_reg[0]_7\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \corse_dec_reg[1]_6\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \corse_inc[0][0]_i_1_n_0\ : STD_LOGIC; + signal \corse_inc[0][1]_i_1_n_0\ : STD_LOGIC; + signal \corse_inc[0][2]_i_1_n_0\ : STD_LOGIC; + signal \corse_inc[0][2]_i_2_n_0\ : STD_LOGIC; + signal \corse_inc[1][0]_i_1_n_0\ : STD_LOGIC; + signal \corse_inc[1][0]_i_2_n_0\ : STD_LOGIC; + signal \corse_inc[1][1]_i_1_n_0\ : STD_LOGIC; + signal \corse_inc[1][1]_i_2_n_0\ : STD_LOGIC; + signal \corse_inc[1][2]_i_1_n_0\ : STD_LOGIC; + signal \corse_inc[1][2]_i_2_n_0\ : STD_LOGIC; + signal \corse_inc[1][2]_i_3_n_0\ : STD_LOGIC; + signal \corse_inc[1][2]_i_4_n_0\ : STD_LOGIC; + signal \corse_inc[1][2]_i_5_n_0\ : STD_LOGIC; + signal \corse_inc[1][2]_i_6_n_0\ : STD_LOGIC; + signal \corse_inc[1][2]_i_7_n_0\ : STD_LOGIC; + signal \corse_inc_reg_n_0_[0][0]\ : STD_LOGIC; + signal \corse_inc_reg_n_0_[0][1]\ : STD_LOGIC; + signal \corse_inc_reg_n_0_[0][2]\ : STD_LOGIC; + signal \corse_inc_reg_n_0_[1][0]\ : STD_LOGIC; + signal \corse_inc_reg_n_0_[1][1]\ : STD_LOGIC; + signal \corse_inc_reg_n_0_[1][2]\ : STD_LOGIC; + signal \^done_dqs_tap_inc\ : STD_LOGIC; + signal dq_cnt_inc_i_1_n_0 : STD_LOGIC; + signal dq_cnt_inc_i_2_n_0 : STD_LOGIC; + signal dq_cnt_inc_i_3_n_0 : STD_LOGIC; + signal dqs_count_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \dqs_count_r[0]_i_1_n_0\ : STD_LOGIC; + signal \dqs_count_r[0]_i_2_n_0\ : STD_LOGIC; + signal \dqs_count_r[0]_i_3_n_0\ : STD_LOGIC; + signal \dqs_count_r[0]_i_4_n_0\ : STD_LOGIC; + signal \dqs_count_r[0]_i_5_n_0\ : STD_LOGIC; + signal \dqs_count_r[0]_i_6_n_0\ : STD_LOGIC; + signal \dqs_count_r[0]_i_7_n_0\ : STD_LOGIC; + signal \dqs_count_r[0]_i_8_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_10_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_1_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_2_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_3_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_4_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_5_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_6_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_7_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_8_n_0\ : STD_LOGIC; + signal \dqs_count_r[1]_i_9_n_0\ : STD_LOGIC; + signal \dqs_count_r_reg[0]_rep_n_0\ : STD_LOGIC; + signal \^dqs_po_dec_done_reg_0\ : STD_LOGIC; + signal dqs_po_en_stg2_f_i_1_n_0 : STD_LOGIC; + signal \^dqs_po_stg2_f_incdec\ : STD_LOGIC; + signal dqs_po_stg2_f_incdec_i_1_n_0 : STD_LOGIC; + signal dqs_po_stg2_f_incdec_i_2_n_0 : STD_LOGIC; + signal dqs_wl_po_stg2_c_incdec_i_1_n_0 : STD_LOGIC; + signal \^final_coarse_tap_reg[0][0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^final_coarse_tap_reg[1][0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^final_coarse_tap_reg[1][1]_0\ : STD_LOGIC; + signal \final_coarse_tap_reg_n_0_[0][1]\ : STD_LOGIC; + signal \final_coarse_tap_reg_n_0_[0][2]\ : STD_LOGIC; + signal \final_coarse_tap_reg_n_0_[1][1]\ : STD_LOGIC; + signal \final_coarse_tap_reg_n_0_[1][2]\ : STD_LOGIC; + signal fine_dec_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \fine_dec_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[4]_i_2_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_10_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_3_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_4_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_5_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_6_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_7_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_8_n_0\ : STD_LOGIC; + signal \fine_dec_cnt[5]_i_9_n_0\ : STD_LOGIC; + signal \fine_dec_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \fine_dec_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \fine_dec_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \fine_dec_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \fine_dec_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \fine_dec_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal fine_inc : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \fine_inc[0][5]_i_1_n_0\ : STD_LOGIC; + signal \fine_inc[0][5]_i_2_n_0\ : STD_LOGIC; + signal \fine_inc[0][5]_i_3_n_0\ : STD_LOGIC; + signal \fine_inc[1][0]_i_1_n_0\ : STD_LOGIC; + signal \fine_inc[1][0]_i_2_n_0\ : STD_LOGIC; + signal \fine_inc[1][1]_i_1_n_0\ : STD_LOGIC; + signal \fine_inc[1][1]_i_2_n_0\ : STD_LOGIC; + signal \fine_inc[1][2]_i_1_n_0\ : STD_LOGIC; + signal \fine_inc[1][2]_i_2_n_0\ : STD_LOGIC; + signal \fine_inc[1][2]_i_3_n_0\ : STD_LOGIC; + signal \fine_inc[1][3]_i_1_n_0\ : STD_LOGIC; + signal \fine_inc[1][3]_i_2_n_0\ : STD_LOGIC; + signal \fine_inc[1][3]_i_3_n_0\ : STD_LOGIC; + signal \fine_inc[1][3]_i_4_n_0\ : STD_LOGIC; + signal \fine_inc[1][4]_i_1_n_0\ : STD_LOGIC; + signal \fine_inc[1][4]_i_2_n_0\ : STD_LOGIC; + signal \fine_inc[1][4]_i_3_n_0\ : STD_LOGIC; + signal \fine_inc[1][5]_i_1_n_0\ : STD_LOGIC; + signal \fine_inc[1][5]_i_2_n_0\ : STD_LOGIC; + signal \fine_inc[1][5]_i_3_n_0\ : STD_LOGIC; + signal \fine_inc[1][5]_i_4_n_0\ : STD_LOGIC; + signal \fine_inc[1][5]_i_5_n_0\ : STD_LOGIC; + signal \fine_inc[1][5]_i_6_n_0\ : STD_LOGIC; + signal \fine_inc[1][5]_i_7_n_0\ : STD_LOGIC; + signal \fine_inc_reg[0]_3\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \fine_inc_reg[1]_2\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal flag_ck_negedge09_out : STD_LOGIC; + signal flag_ck_negedge_i_1_n_0 : STD_LOGIC; + signal flag_ck_negedge_i_2_n_0 : STD_LOGIC; + signal flag_ck_negedge_i_3_n_0 : STD_LOGIC; + signal flag_ck_negedge_i_5_n_0 : STD_LOGIC; + signal flag_ck_negedge_i_6_n_0 : STD_LOGIC; + signal flag_ck_negedge_i_7_n_0 : STD_LOGIC; + signal flag_ck_negedge_reg_n_0 : STD_LOGIC; + signal flag_init : STD_LOGIC; + signal flag_init_i_1_n_0 : STD_LOGIC; + signal flag_init_i_2_n_0 : STD_LOGIC; + signal \gen_final_tap[0].final_val_reg_n_0_[0][0]\ : STD_LOGIC; + signal \gen_final_tap[0].final_val_reg_n_0_[0][1]\ : STD_LOGIC; + signal \gen_final_tap[0].final_val_reg_n_0_[0][2]\ : STD_LOGIC; + signal \gen_final_tap[0].final_val_reg_n_0_[0][3]\ : STD_LOGIC; + signal \gen_final_tap[0].final_val_reg_n_0_[0][4]\ : STD_LOGIC; + signal \gen_final_tap[0].final_val_reg_n_0_[0][5]\ : STD_LOGIC; + signal \gen_final_tap[1].final_val_reg_n_0_[1][0]\ : STD_LOGIC; + signal \gen_final_tap[1].final_val_reg_n_0_[1][1]\ : STD_LOGIC; + signal \gen_final_tap[1].final_val_reg_n_0_[1][2]\ : STD_LOGIC; + signal \gen_final_tap[1].final_val_reg_n_0_[1][3]\ : STD_LOGIC; + signal \gen_final_tap[1].final_val_reg_n_0_[1][4]\ : STD_LOGIC; + signal \gen_final_tap[1].final_val_reg_n_0_[1][5]\ : STD_LOGIC; + signal \gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\ : STD_LOGIC; + signal \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\ : STD_LOGIC; + signal \gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\ : STD_LOGIC; + signal \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\ : STD_LOGIC; + signal \incdec_wait_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal incdec_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal inhibit_edge_detect_r_i_1_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_2_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_3_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_4_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_5_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_6_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_7_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_8_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_i_9_n_0 : STD_LOGIC; + signal inhibit_edge_detect_r_reg_n_0 : STD_LOGIC; + signal largest : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal p_0_in : STD_LOGIC; + signal \p_0_in__0\ : STD_LOGIC; + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal p_45_out : STD_LOGIC; + signal phy_ctl_ready_r4_reg_srl4_n_0 : STD_LOGIC; + signal phy_ctl_ready_r5 : STD_LOGIC; + signal phy_ctl_ready_r6_reg_n_0 : STD_LOGIC; + signal po_cnt_dec_i_1_n_0 : STD_LOGIC; + signal po_cnt_dec_i_2_n_0 : STD_LOGIC; + signal \^po_cnt_dec_reg_0\ : STD_LOGIC; + signal po_dec_done : STD_LOGIC; + signal po_dec_done_i_1_n_0 : STD_LOGIC; + signal po_dec_done_i_2_n_0 : STD_LOGIC; + signal po_rdval_cnt : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \po_rdval_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[3]_i_2_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[4]_i_2_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[6]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[6]_i_2_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[6]_i_3_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[7]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[7]_i_2_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[7]_i_3_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[8]_i_1_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[8]_i_2_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[8]_i_3_n_0\ : STD_LOGIC; + signal \po_rdval_cnt[8]_i_4_n_0\ : STD_LOGIC; + signal po_stg2_cincdec : STD_LOGIC_VECTOR ( 2 to 2 ); + signal rank_cnt_r : STD_LOGIC; + signal \rank_cnt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \rank_cnt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \rank_cnt_r_reg_n_0_[0]\ : STD_LOGIC; + signal \rank_cnt_r_reg_n_0_[1]\ : STD_LOGIC; + signal \rd_data_edge_detect_r[0]_i_1_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r[0]_i_2_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r[1]_i_1_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r[1]_i_2_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r[1]_i_3_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r[1]_i_4_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r[1]_i_5_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r[1]_i_6_n_0\ : STD_LOGIC; + signal \rd_data_edge_detect_r_reg_n_0_[0]\ : STD_LOGIC; + signal \rd_data_edge_detect_r_reg_n_0_[1]\ : STD_LOGIC; + signal rd_data_previous_r0 : STD_LOGIC; + signal \rd_data_previous_r[0]_i_1_n_0\ : STD_LOGIC; + signal \rd_data_previous_r[1]_i_1_n_0\ : STD_LOGIC; + signal \rd_data_previous_r_reg_n_0_[0]\ : STD_LOGIC; + signal \rd_data_previous_r_reg_n_0_[1]\ : STD_LOGIC; + signal \single_rank.done_dqs_dec_i_1_n_0\ : STD_LOGIC; + signal \smallest[0][5]_i_1_n_0\ : STD_LOGIC; + signal \smallest[1][5]_i_1_n_0\ : STD_LOGIC; + signal \smallest_reg[0]_4\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \smallest_reg[1]_5\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal stable_cnt : STD_LOGIC; + signal stable_cnt0 : STD_LOGIC; + signal \stable_cnt[3]_i_10_n_0\ : STD_LOGIC; + signal \stable_cnt[3]_i_4_n_0\ : STD_LOGIC; + signal \stable_cnt[3]_i_5_n_0\ : STD_LOGIC; + signal \stable_cnt[3]_i_6_n_0\ : STD_LOGIC; + signal \stable_cnt[3]_i_7_n_0\ : STD_LOGIC; + signal \stable_cnt[3]_i_8_n_0\ : STD_LOGIC; + signal \stable_cnt[3]_i_9_n_0\ : STD_LOGIC; + signal \stable_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \stable_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \stable_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \stable_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal wait_cnt0 : STD_LOGIC; + signal \wait_cnt0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wait_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wl_corse_cnt[0][0][0]_i_1_n_0\ : STD_LOGIC; + signal \wl_corse_cnt[0][0][1]_i_1_n_0\ : STD_LOGIC; + signal \wl_corse_cnt[0][0][2]_i_1_n_0\ : STD_LOGIC; + signal \wl_corse_cnt_reg[0][0]_8\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \wl_corse_cnt_reg[0][1]_9\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\ : STD_LOGIC; + signal \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\ : STD_LOGIC; + signal \wl_dqs_tap_count_r[0][0][5]_i_3_n_0\ : STD_LOGIC; + signal \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\ : STD_LOGIC; + signal \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\ : STD_LOGIC; + signal \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\ : STD_LOGIC; + signal \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\ : STD_LOGIC; + signal \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\ : STD_LOGIC; + signal \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\ : STD_LOGIC; + signal \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\ : STD_LOGIC; + signal wl_edge_detect_valid_r : STD_LOGIC; + signal wl_edge_detect_valid_r_i_1_n_0 : STD_LOGIC; + signal wl_edge_detect_valid_r_reg_n_0 : STD_LOGIC; + signal \wl_state_r1[0]_i_1_n_0\ : STD_LOGIC; + signal \wl_state_r1[1]_i_1_n_0\ : STD_LOGIC; + signal \wl_state_r1[2]_i_1_n_0\ : STD_LOGIC; + signal \wl_state_r1[3]_i_1_n_0\ : STD_LOGIC; + signal \wl_state_r1[4]_i_1_n_0\ : STD_LOGIC; + signal \wl_state_r1_reg_n_0_[0]\ : STD_LOGIC; + signal \wl_state_r1_reg_n_0_[1]\ : STD_LOGIC; + signal \wl_state_r1_reg_n_0_[2]\ : STD_LOGIC; + signal \wl_state_r1_reg_n_0_[3]\ : STD_LOGIC; + signal \wl_state_r1_reg_n_0_[4]\ : STD_LOGIC; + signal \wl_state_r__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal wl_tap_count_r : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \wl_tap_count_r[0]_i_2_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[1]_i_2_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[2]_i_2_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[3]_i_2_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[4]_i_2_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[4]_i_3_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[5]_i_1_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[5]_i_4_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[5]_i_5_n_0\ : STD_LOGIC; + signal \wl_tap_count_r[5]_i_6_n_0\ : STD_LOGIC; + signal \wl_tap_count_r_reg_n_0_[0]\ : STD_LOGIC; + signal \wl_tap_count_r_reg_n_0_[1]\ : STD_LOGIC; + signal \wl_tap_count_r_reg_n_0_[2]\ : STD_LOGIC; + signal \wl_tap_count_r_reg_n_0_[3]\ : STD_LOGIC; + signal \wl_tap_count_r_reg_n_0_[4]\ : STD_LOGIC; + signal \wl_tap_count_r_reg_n_0_[5]\ : STD_LOGIC; + signal wr_level_done_i_1_n_0 : STD_LOGIC; + signal wr_level_done_r1 : STD_LOGIC; + signal wr_level_done_r2 : STD_LOGIC; + signal wr_level_done_r3 : STD_LOGIC; + signal wr_level_done_r4 : STD_LOGIC; + signal wr_level_done_r5 : STD_LOGIC; + signal wr_level_done_r_i_1_n_0 : STD_LOGIC; + signal wr_level_done_r_i_2_n_0 : STD_LOGIC; + signal wr_level_done_r_reg_n_0 : STD_LOGIC; + signal \^wr_level_done_reg_0\ : STD_LOGIC; + signal wr_level_start_r : STD_LOGIC; + signal \^wrlvl_byte_done\ : STD_LOGIC; + signal wrlvl_byte_done_i_1_n_0 : STD_LOGIC; + signal \^wrlvl_byte_redo_r\ : STD_LOGIC; + signal \^wrlvl_rank_done\ : STD_LOGIC; + signal wrlvl_rank_done_r_i_1_n_0 : STD_LOGIC; + signal wrlvl_rank_done_r_i_2_n_0 : STD_LOGIC; + signal \wrlvl_redo_corse_inc[0]_i_1_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc[1]_i_1_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc[1]_i_2_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc[1]_i_3_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc[2]_i_1_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc[2]_i_2_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc[2]_i_3_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc[2]_i_4_n_0\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc_reg_n_0_[0]\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc_reg_n_0_[1]\ : STD_LOGIC; + signal \wrlvl_redo_corse_inc_reg_n_0_[2]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_10\ : label is "soft_lutpair274"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_11\ : label is "soft_lutpair267"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_12\ : label is "soft_lutpair232"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[0]_i_3\ : label is "soft_lutpair285"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_10\ : label is "soft_lutpair286"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_11\ : label is "soft_lutpair265"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_6\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[1]_i_9\ : label is "soft_lutpair266"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_12\ : label is "soft_lutpair286"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_13\ : label is "soft_lutpair265"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_14\ : label is "soft_lutpair237"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_6\ : label is "soft_lutpair285"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_8\ : label is "soft_lutpair261"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[2]_i_9\ : label is "soft_lutpair287"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_6\ : label is "soft_lutpair232"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_7\ : label is "soft_lutpair264"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[3]_i_9\ : label is "soft_lutpair266"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_14\ : label is "soft_lutpair260"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_15\ : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_19\ : label is "soft_lutpair268"; + attribute SOFT_HLUTNM of \FSM_sequential_wl_state_r[4]_i_9\ : label is "soft_lutpair274"; + attribute FSM_ENCODED_STATES : string; + attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[0]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001"; + attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[1]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001"; + attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[2]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001"; + attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[3]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001"; + attribute FSM_ENCODED_STATES of \FSM_sequential_wl_state_r_reg[4]\ : label is "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001"; + attribute SOFT_HLUTNM of \corse_cnt[0][0]_i_4\ : label is "soft_lutpair269"; + attribute SOFT_HLUTNM of \corse_cnt[0][0]_i_5\ : label is "soft_lutpair270"; + attribute SOFT_HLUTNM of \corse_cnt[0][0]_i_6\ : label is "soft_lutpair231"; + attribute SOFT_HLUTNM of \corse_cnt[0][1]_i_1\ : label is "soft_lutpair279"; + attribute SOFT_HLUTNM of \corse_cnt[0][1]_i_4\ : label is "soft_lutpair237"; + attribute SOFT_HLUTNM of \corse_cnt[0][1]_i_5\ : label is "soft_lutpair269"; + attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_1\ : label is "soft_lutpair279"; + attribute SOFT_HLUTNM of \corse_cnt[0][2]_i_4\ : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of \corse_cnt[1][0]_i_1\ : label is "soft_lutpair271"; + attribute SOFT_HLUTNM of \corse_cnt[1][1]_i_1\ : label is "soft_lutpair278"; + attribute SOFT_HLUTNM of \corse_cnt[1][2]_i_1\ : label is "soft_lutpair277"; + attribute SOFT_HLUTNM of \corse_dec[0][0]_i_1\ : label is "soft_lutpair250"; + attribute SOFT_HLUTNM of \corse_dec[0][2]_i_1\ : label is "soft_lutpair280"; + attribute SOFT_HLUTNM of \corse_dec[1][0]_i_1\ : label is "soft_lutpair249"; + attribute SOFT_HLUTNM of \corse_dec[1][1]_i_3\ : label is "soft_lutpair250"; + attribute SOFT_HLUTNM of \corse_dec[1][2]_i_1\ : label is "soft_lutpair280"; + attribute SOFT_HLUTNM of \corse_dec[1][2]_i_4\ : label is "soft_lutpair276"; + attribute SOFT_HLUTNM of \corse_inc[1][0]_i_2\ : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of \corse_inc[1][2]_i_3\ : label is "soft_lutpair270"; + attribute SOFT_HLUTNM of \corse_inc[1][2]_i_5\ : label is "soft_lutpair245"; + attribute SOFT_HLUTNM of \corse_inc[1][2]_i_6\ : label is "soft_lutpair256"; + attribute SOFT_HLUTNM of \corse_inc[1][2]_i_7\ : label is "soft_lutpair258"; + attribute SOFT_HLUTNM of dq_cnt_inc_i_3 : label is "soft_lutpair287"; + attribute SOFT_HLUTNM of \dqs_count_r[0]_i_1\ : label is "soft_lutpair259"; + attribute SOFT_HLUTNM of \dqs_count_r[0]_i_5\ : label is "soft_lutpair224"; + attribute SOFT_HLUTNM of \dqs_count_r[0]_i_7\ : label is "soft_lutpair272"; + attribute SOFT_HLUTNM of \dqs_count_r[0]_i_8\ : label is "soft_lutpair272"; + attribute SOFT_HLUTNM of \dqs_count_r[1]_i_5\ : label is "soft_lutpair251"; + attribute SOFT_HLUTNM of \dqs_count_r[1]_i_6\ : label is "soft_lutpair259"; + attribute SOFT_HLUTNM of \dqs_count_r[1]_i_7\ : label is "soft_lutpair262"; + attribute SOFT_HLUTNM of \dqs_count_r[1]_i_8\ : label is "soft_lutpair223"; + attribute SOFT_HLUTNM of \dqs_count_r[1]_i_9\ : label is "soft_lutpair258"; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of \dqs_count_r_reg[0]\ : label is "50"; + attribute ORIG_CELL_NAME : string; + attribute ORIG_CELL_NAME of \dqs_count_r_reg[0]\ : label is "dqs_count_r_reg[0]"; + attribute IS_FANOUT_CONSTRAINED : integer; + attribute IS_FANOUT_CONSTRAINED of \dqs_count_r_reg[0]_rep\ : label is 1; + attribute MAX_FANOUT of \dqs_count_r_reg[0]_rep\ : label is "50"; + attribute ORIG_CELL_NAME of \dqs_count_r_reg[0]_rep\ : label is "dqs_count_r_reg[0]"; + attribute MAX_FANOUT of \dqs_count_r_reg[1]\ : label is "50"; + attribute syn_maxfan : string; + attribute syn_maxfan of dqs_po_dec_done_reg : label is "2"; + attribute SOFT_HLUTNM of dqs_wl_po_stg2_c_incdec_i_1 : label is "soft_lutpair256"; + attribute SOFT_HLUTNM of \fine_dec_cnt[4]_i_2\ : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_4\ : label is "soft_lutpair263"; + attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_7\ : label is "soft_lutpair253"; + attribute SOFT_HLUTNM of \fine_dec_cnt[5]_i_8\ : label is "soft_lutpair273"; + attribute SOFT_HLUTNM of \fine_inc[0][3]_i_1\ : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of \fine_inc[0][4]_i_1\ : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of \fine_inc[0][5]_i_2\ : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of \fine_inc[0][5]_i_3\ : label is "soft_lutpair276"; + attribute SOFT_HLUTNM of \fine_inc[1][0]_i_2\ : label is "soft_lutpair238"; + attribute SOFT_HLUTNM of \fine_inc[1][2]_i_3\ : label is "soft_lutpair242"; + attribute SOFT_HLUTNM of \fine_inc[1][3]_i_1\ : label is "soft_lutpair238"; + attribute SOFT_HLUTNM of \fine_inc[1][3]_i_4\ : label is "soft_lutpair242"; + attribute SOFT_HLUTNM of \fine_inc[1][4]_i_1\ : label is "soft_lutpair239"; + attribute SOFT_HLUTNM of \fine_inc[1][5]_i_2\ : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of \fine_inc[1][5]_i_3\ : label is "soft_lutpair257"; + attribute SOFT_HLUTNM of \fine_inc[1][5]_i_5\ : label is "soft_lutpair224"; + attribute SOFT_HLUTNM of \fine_inc[1][5]_i_6\ : label is "soft_lutpair262"; + attribute SOFT_HLUTNM of flag_ck_negedge_i_2 : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of flag_ck_negedge_i_3 : label is "soft_lutpair240"; + attribute SOFT_HLUTNM of flag_ck_negedge_i_6 : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of flag_ck_negedge_i_7 : label is "soft_lutpair227"; + attribute SOFT_HLUTNM of flag_init_i_2 : label is "soft_lutpair251"; + attribute SOFT_HLUTNM of \incdec_wait_cnt[1]_i_1\ : label is "soft_lutpair283"; + attribute SOFT_HLUTNM of \incdec_wait_cnt[2]_i_1\ : label is "soft_lutpair283"; + attribute SOFT_HLUTNM of \incdec_wait_cnt[3]_i_2\ : label is "soft_lutpair260"; + attribute SOFT_HLUTNM of inhibit_edge_detect_r_i_2 : label is "soft_lutpair248"; + attribute SOFT_HLUTNM of inhibit_edge_detect_r_i_4 : label is "soft_lutpair248"; + attribute SOFT_HLUTNM of inhibit_edge_detect_r_i_6 : label is "soft_lutpair243"; + attribute SOFT_HLUTNM of inhibit_edge_detect_r_i_7 : label is "soft_lutpair229"; + attribute SOFT_HLUTNM of inhibit_edge_detect_r_i_8 : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of phaser_out_i_1 : label is "soft_lutpair235"; + attribute SOFT_HLUTNM of \phaser_out_i_1__0\ : label is "soft_lutpair235"; + attribute SOFT_HLUTNM of \phaser_out_i_1__1\ : label is "soft_lutpair236"; + attribute SOFT_HLUTNM of \phaser_out_i_1__2\ : label is "soft_lutpair236"; + attribute SOFT_HLUTNM of \phaser_out_i_2__0\ : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \phaser_out_i_2__1\ : label is "soft_lutpair226"; + attribute SOFT_HLUTNM of phaser_out_i_3 : label is "soft_lutpair225"; + attribute SOFT_HLUTNM of \phaser_out_i_3__1\ : label is "soft_lutpair226"; + attribute srl_name : string; + attribute srl_name of phy_ctl_ready_r4_reg_srl4 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 "; + attribute SOFT_HLUTNM of \po_rdval_cnt[0]_i_1\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of \po_rdval_cnt[4]_i_2\ : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of \po_rdval_cnt[6]_i_2\ : label is "soft_lutpair221"; + attribute SOFT_HLUTNM of \po_rdval_cnt[6]_i_3\ : label is "soft_lutpair233"; + attribute SOFT_HLUTNM of \po_rdval_cnt[7]_i_3\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \po_rdval_cnt[8]_i_3\ : label is "soft_lutpair222"; + attribute SOFT_HLUTNM of \rank_cnt_r[0]_i_1\ : label is "soft_lutpair281"; + attribute SOFT_HLUTNM of \rank_cnt_r[1]_i_1\ : label is "soft_lutpair281"; + attribute SOFT_HLUTNM of \rd_data_edge_detect_r[1]_i_5\ : label is "soft_lutpair244"; + attribute SOFT_HLUTNM of \rd_data_edge_detect_r[1]_i_6\ : label is "soft_lutpair264"; + attribute SOFT_HLUTNM of \rd_data_previous_r[0]_i_1\ : label is "soft_lutpair275"; + attribute SOFT_HLUTNM of \rd_data_previous_r[1]_i_1\ : label is "soft_lutpair275"; + attribute SOFT_HLUTNM of \stable_cnt[0]_i_1\ : label is "soft_lutpair230"; + attribute SOFT_HLUTNM of \stable_cnt[1]_i_1\ : label is "soft_lutpair282"; + attribute SOFT_HLUTNM of \stable_cnt[2]_i_1\ : label is "soft_lutpair282"; + attribute SOFT_HLUTNM of \stable_cnt[3]_i_10\ : label is "soft_lutpair239"; + attribute SOFT_HLUTNM of \stable_cnt[3]_i_3\ : label is "soft_lutpair268"; + attribute SOFT_HLUTNM of \stable_cnt[3]_i_5\ : label is "soft_lutpair243"; + attribute SOFT_HLUTNM of \stable_cnt[3]_i_8\ : label is "soft_lutpair263"; + attribute SOFT_HLUTNM of \stable_cnt[3]_i_9\ : label is "soft_lutpair273"; + attribute SOFT_HLUTNM of \wait_cnt[1]_i_1\ : label is "soft_lutpair284"; + attribute SOFT_HLUTNM of \wait_cnt[2]_i_1\ : label is "soft_lutpair284"; + attribute SOFT_HLUTNM of \wl_corse_cnt[0][0][0]_i_1\ : label is "soft_lutpair271"; + attribute SOFT_HLUTNM of \wl_corse_cnt[0][0][1]_i_1\ : label is "soft_lutpair278"; + attribute SOFT_HLUTNM of \wl_corse_cnt[0][0][2]_i_1\ : label is "soft_lutpair277"; + attribute SOFT_HLUTNM of \wl_dqs_tap_count_r[0][0][5]_i_3\ : label is "soft_lutpair234"; + attribute SOFT_HLUTNM of \wl_state_r1[0]_i_1\ : label is "soft_lutpair254"; + attribute SOFT_HLUTNM of \wl_state_r1[1]_i_1\ : label is "soft_lutpair254"; + attribute SOFT_HLUTNM of \wl_state_r1[2]_i_1\ : label is "soft_lutpair255"; + attribute SOFT_HLUTNM of \wl_state_r1[3]_i_1\ : label is "soft_lutpair257"; + attribute SOFT_HLUTNM of \wl_state_r1[4]_i_1\ : label is "soft_lutpair255"; + attribute SOFT_HLUTNM of \wl_tap_count_r[0]_i_2\ : label is "soft_lutpair267"; + attribute SOFT_HLUTNM of \wl_tap_count_r[1]_i_2\ : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \wl_tap_count_r[3]_i_2\ : label is "soft_lutpair247"; + attribute SOFT_HLUTNM of \wl_tap_count_r[4]_i_3\ : label is "soft_lutpair252"; + attribute SOFT_HLUTNM of \wl_tap_count_r[5]_i_4\ : label is "soft_lutpair249"; + attribute SOFT_HLUTNM of \wl_tap_count_r[5]_i_6\ : label is "soft_lutpair247"; + attribute SOFT_HLUTNM of wr_level_done_r_i_1 : label is "soft_lutpair234"; + attribute syn_maxfan of wr_level_done_reg : label is "2"; + attribute SOFT_HLUTNM of wrlvl_rank_done_r_i_2 : label is "soft_lutpair241"; + attribute SOFT_HLUTNM of \wrlvl_redo_corse_inc[1]_i_2\ : label is "soft_lutpair246"; + attribute SOFT_HLUTNM of \wrlvl_redo_corse_inc[2]_i_2\ : label is "soft_lutpair228"; + attribute SOFT_HLUTNM of \wrlvl_redo_corse_inc[2]_i_3\ : label is "soft_lutpair261"; +begin + cmd_delay_start0 <= \^cmd_delay_start0\; + done_dqs_tap_inc <= \^done_dqs_tap_inc\; + dqs_po_dec_done_reg_0 <= \^dqs_po_dec_done_reg_0\; + dqs_po_stg2_f_incdec <= \^dqs_po_stg2_f_incdec\; + \final_coarse_tap_reg[0][0]_0\(0) <= \^final_coarse_tap_reg[0][0]_0\(0); + \final_coarse_tap_reg[1][0]_0\(0) <= \^final_coarse_tap_reg[1][0]_0\(0); + \final_coarse_tap_reg[1][1]_0\ <= \^final_coarse_tap_reg[1][1]_0\; + po_cnt_dec_reg_0 <= \^po_cnt_dec_reg_0\; + wr_level_done_reg_0 <= \^wr_level_done_reg_0\; + wrlvl_byte_done <= \^wrlvl_byte_done\; + wrlvl_byte_redo_r <= \^wrlvl_byte_redo_r\; + wrlvl_rank_done <= \^wrlvl_rank_done\; +\FSM_sequential_wl_state_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFFEAAA" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[0]_i_2_n_0\, + I1 => \wl_state_r__0\(1), + I2 => \FSM_sequential_wl_state_r[0]_i_3_n_0\, + I3 => \FSM_sequential_wl_state_r[0]_i_4_n_0\, + I4 => \FSM_sequential_wl_state_r[0]_i_5_n_0\, + I5 => \FSM_sequential_wl_state_r[0]_i_6_n_0\, + O => \FSM_sequential_wl_state_r[0]_i_1_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_10\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(0), + I2 => inhibit_edge_detect_r_i_3_n_0, + O => \FSM_sequential_wl_state_r[0]_i_10_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_11\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(1), + O => \FSM_sequential_wl_state_r[0]_i_11_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_12\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[5]\, + I1 => \wl_tap_count_r_reg_n_0_[4]\, + I2 => \wl_tap_count_r_reg_n_0_[3]\, + O => \FSM_sequential_wl_state_r[0]_i_12_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2000022200000222" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[0]_i_7_n_0\, + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(2), + I4 => \wl_state_r__0\(0), + I5 => wr_level_done_r5, + O => \FSM_sequential_wl_state_r[0]_i_2_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(2), + O => \FSM_sequential_wl_state_r[0]_i_3_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF4000" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => wrlvl_byte_redo, + I2 => \rd_data_edge_detect_r[1]_i_3_n_0\, + I3 => \FSM_sequential_wl_state_r[2]_i_10_n_0\, + I4 => \FSM_sequential_wl_state_r[0]_i_8_n_0\, + O => \FSM_sequential_wl_state_r[0]_i_4_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000C0C0EFE" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \FSM_sequential_wl_state_r[0]_i_9_n_0\, + I2 => \FSM_sequential_wl_state_r[0]_i_10_n_0\, + I3 => \FSM_sequential_wl_state_r[0]_i_3_n_0\, + I4 => \wl_state_r__0\(0), + I5 => \wl_state_r__0\(1), + O => \FSM_sequential_wl_state_r[0]_i_5_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000002C00" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[1]_i_6_n_0\, + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(3), + I3 => \fine_inc[1][5]_i_4_n_0\, + I4 => \FSM_sequential_wl_state_r[0]_i_11_n_0\, + I5 => \fine_inc[1][5]_i_5_n_0\, + O => \FSM_sequential_wl_state_r[0]_i_6_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFEFFFFFFFFFF" + ) + port map ( + I0 => \wrlvl_redo_corse_inc_reg_n_0_[2]\, + I1 => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + I2 => \wrlvl_redo_corse_inc_reg_n_0_[1]\, + I3 => wrlvl_byte_redo, + I4 => \wl_state_r__0\(0), + I5 => \wl_state_r__0\(3), + O => \FSM_sequential_wl_state_r[0]_i_7_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF44FFFF000F0000" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[3]_i_7_n_0\, + I1 => \FSM_sequential_wl_state_r[0]_i_12_n_0\, + I2 => \FSM_sequential_wl_state_r[4]_i_17_n_0\, + I3 => \wl_state_r__0\(2), + I4 => \wl_state_r__0\(3), + I5 => \wl_state_r__0\(0), + O => \FSM_sequential_wl_state_r[0]_i_8_n_0\ + ); +\FSM_sequential_wl_state_r[0]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFBBF0FFFF00F0FF" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[2]_i_10_n_0\, + I1 => wrlvl_byte_redo, + I2 => \fine_dec_cnt[5]_i_5_n_0\, + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(4), + I5 => inhibit_edge_detect_r_i_3_n_0, + O => \FSM_sequential_wl_state_r[0]_i_9_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF05C5" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[1]_i_2_n_0\, + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(1), + I4 => \FSM_sequential_wl_state_r[1]_i_3_n_0\, + I5 => \FSM_sequential_wl_state_r[1]_i_4_n_0\, + O => \FSM_sequential_wl_state_r[1]_i_1_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_10\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => \wl_state_r__0\(2), + O => \FSM_sequential_wl_state_r[1]_i_10_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_11\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \wrlvl_redo_corse_inc_reg_n_0_[1]\, + I1 => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + O => \FSM_sequential_wl_state_r[1]_i_11_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFF4F4F4" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_17_n_0\, + I1 => \wl_state_r__0\(4), + I2 => \FSM_sequential_wl_state_r[1]_i_5_n_0\, + I3 => \fine_inc[1][5]_i_5_n_0\, + I4 => \FSM_sequential_wl_state_r[1]_i_6_n_0\, + I5 => \FSM_sequential_wl_state_r[1]_i_7_n_0\, + O => \FSM_sequential_wl_state_r[1]_i_2_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A0A0A0AC00000F0" + ) + port map ( + I0 => inhibit_edge_detect_r_i_3_n_0, + I1 => \FSM_sequential_wl_state_r[4]_i_12_n_0\, + I2 => \wl_state_r__0\(1), + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(2), + I5 => \wl_state_r__0\(4), + O => \FSM_sequential_wl_state_r[1]_i_3_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AEAEAE0000000000" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[1]_i_8_n_0\, + I1 => \FSM_sequential_wl_state_r[1]_i_9_n_0\, + I2 => \fine_inc[1][5]_i_5_n_0\, + I3 => \wl_state_r__0\(4), + I4 => \FSM_sequential_wl_state_r[3]_i_8_n_0\, + I5 => \FSM_sequential_wl_state_r[1]_i_10_n_0\, + O => \FSM_sequential_wl_state_r[1]_i_4_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"77777777777777F7" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(3), + I2 => wrlvl_byte_redo, + I3 => \FSM_sequential_wl_state_r[1]_i_11_n_0\, + I4 => \wrlvl_redo_corse_inc_reg_n_0_[2]\, + I5 => \wl_state_r__0\(4), + O => \FSM_sequential_wl_state_r[1]_i_5_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000000D" + ) + port map ( + I0 => wl_sm_start, + I1 => wr_level_done_r5, + I2 => wrlvl_byte_redo, + I3 => \FSM_sequential_wl_state_r[4]_i_12_n_0\, + I4 => \wl_state_r__0\(4), + O => \FSM_sequential_wl_state_r[1]_i_6_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888FBBB8888" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(1), + I2 => wrlvl_byte_redo, + I3 => \rd_data_edge_detect_r[1]_i_3_n_0\, + I4 => \wl_state_r__0\(4), + I5 => \wl_state_r__0\(3), + O => \FSM_sequential_wl_state_r[1]_i_7_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5D00FF000000FF00" + ) + port map ( + I0 => wl_edge_detect_valid_r_reg_n_0, + I1 => \fine_dec_cnt[5]_i_10_n_0\, + I2 => \fine_dec_cnt[5]_i_9_n_0\, + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(1), + I5 => \wl_state_r__0\(4), + O => \FSM_sequential_wl_state_r[1]_i_8_n_0\ + ); +\FSM_sequential_wl_state_r[1]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(3), + O => \FSM_sequential_wl_state_r[1]_i_9_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FAFAAAEAFAFAFAFA" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[2]_i_2_n_0\, + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(1), + I3 => \FSM_sequential_wl_state_r[2]_i_3_n_0\, + I4 => \FSM_sequential_wl_state_r[2]_i_4_n_0\, + I5 => \FSM_sequential_wl_state_r[2]_i_5_n_0\, + O => \FSM_sequential_wl_state_r[2]_i_1_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000017771777FFFF" + ) + port map ( + I0 => \wl_corse_cnt[0][0][1]_i_1_n_0\, + I1 => \wrlvl_redo_corse_inc_reg_n_0_[1]\, + I2 => \wl_corse_cnt[0][0][0]_i_1_n_0\, + I3 => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + I4 => \wrlvl_redo_corse_inc_reg_n_0_[2]\, + I5 => \wl_corse_cnt[0][0][2]_i_1_n_0\, + O => \FSM_sequential_wl_state_r[2]_i_10_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF4500" + ) + port map ( + I0 => wrlvl_byte_redo, + I1 => wr_level_done_r5, + I2 => wl_sm_start, + I3 => \FSM_sequential_wl_state_r[4]_i_12_n_0\, + I4 => \FSM_sequential_wl_state_r[2]_i_13_n_0\, + I5 => \FSM_sequential_wl_state_r[2]_i_14_n_0\, + O => \FSM_sequential_wl_state_r[2]_i_11_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_12\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(0), + O => \FSM_sequential_wl_state_r[2]_i_12_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_13\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA8" + ) + port map ( + I0 => wrlvl_byte_redo, + I1 => \wrlvl_redo_corse_inc_reg_n_0_[1]\, + I2 => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + I3 => \wrlvl_redo_corse_inc_reg_n_0_[2]\, + O => \FSM_sequential_wl_state_r[2]_i_13_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_14\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(2), + O => \FSM_sequential_wl_state_r[2]_i_14_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1F1F0F0F111F0000" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[2]_i_6_n_0\, + I1 => \wl_state_r__0\(3), + I2 => \FSM_sequential_wl_state_r[2]_i_7_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(0), + I5 => \FSM_sequential_wl_state_r[2]_i_8_n_0\, + O => \FSM_sequential_wl_state_r[2]_i_2_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0F0F000F2F2FF0F" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[3]_i_6_n_0\, + I1 => \FSM_sequential_wl_state_r[3]_i_7_n_0\, + I2 => \wl_state_r__0\(2), + I3 => \FSM_sequential_wl_state_r[4]_i_12_n_0\, + I4 => \wl_state_r__0\(4), + I5 => \FSM_sequential_wl_state_r[2]_i_9_n_0\, + O => \FSM_sequential_wl_state_r[2]_i_3_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000030002000300" + ) + port map ( + I0 => \rd_data_edge_detect_r[1]_i_3_n_0\, + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(3), + I3 => inhibit_edge_detect_r_i_2_n_0, + I4 => wrlvl_byte_redo, + I5 => \FSM_sequential_wl_state_r[2]_i_10_n_0\, + O => \FSM_sequential_wl_state_r[2]_i_4_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"ACAF0000FFFFFFFF" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_17_n_0\, + I1 => \FSM_sequential_wl_state_r[4]_i_10_n_0\, + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(2), + I4 => \FSM_sequential_wl_state_r[2]_i_11_n_0\, + I5 => \FSM_sequential_wl_state_r[2]_i_12_n_0\, + O => \FSM_sequential_wl_state_r[2]_i_5_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(2), + O => \FSM_sequential_wl_state_r[2]_i_6_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000DF00FF00FF" + ) + port map ( + I0 => inhibit_edge_detect_r_i_3_n_0, + I1 => \FSM_sequential_wl_state_r[2]_i_10_n_0\, + I2 => wrlvl_byte_redo, + I3 => \FSM_sequential_wl_state_r[4]_i_15_n_0\, + I4 => \wl_state_r__0\(3), + I5 => \wl_state_r__0\(4), + O => \FSM_sequential_wl_state_r[2]_i_7_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(4), + I2 => inhibit_edge_detect_r_i_3_n_0, + I3 => \wl_state_r__0\(3), + O => \FSM_sequential_wl_state_r[2]_i_8_n_0\ + ); +\FSM_sequential_wl_state_r[2]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => p_0_in, + O => \FSM_sequential_wl_state_r[2]_i_9_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFF04" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[3]_i_2_n_0\, + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(2), + I3 => \FSM_sequential_wl_state_r[3]_i_3_n_0\, + I4 => \FSM_sequential_wl_state_r[3]_i_4_n_0\, + I5 => \FSM_sequential_wl_state_r[3]_i_5_n_0\, + O => \FSM_sequential_wl_state_r[3]_i_1_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFACFF0CFFACFF0" + ) + port map ( + I0 => inhibit_edge_detect_r_i_3_n_0, + I1 => \FSM_sequential_wl_state_r[3]_i_6_n_0\, + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(3), + I5 => \FSM_sequential_wl_state_r[3]_i_7_n_0\, + O => \FSM_sequential_wl_state_r[3]_i_2_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000003700" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[3]_i_8_n_0\, + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(1), + I3 => \wl_tap_count_r[5]_i_4_n_0\, + I4 => \wl_state_r__0\(2), + I5 => \FSM_sequential_wl_state_r[3]_i_9_n_0\, + O => \FSM_sequential_wl_state_r[3]_i_3_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C07000C0C0700CC0" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_10_n_0\, + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(3), + I5 => p_0_in, + O => \FSM_sequential_wl_state_r[3]_i_4_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C8CCC8CC44440000" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \corse_dec[1][1]_i_3_n_0\, + I2 => \rd_data_edge_detect_r[1]_i_3_n_0\, + I3 => wrlvl_byte_redo, + I4 => inhibit_edge_detect_r_i_3_n_0, + I5 => \wl_state_r__0\(1), + O => \FSM_sequential_wl_state_r[3]_i_5_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_6\: unisim.vcomponents.LUT5 + generic map( + INIT => X"40000000" + ) + port map ( + I0 => \fine_dec_cnt[5]_i_10_n_0\, + I1 => \wl_state_r__0\(3), + I2 => \wl_tap_count_r_reg_n_0_[5]\, + I3 => \wl_tap_count_r_reg_n_0_[4]\, + I4 => \wl_tap_count_r_reg_n_0_[3]\, + O => \FSM_sequential_wl_state_r[3]_i_6_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E2FF" + ) + port map ( + I0 => \rd_data_edge_detect_r_reg_n_0_[0]\, + I1 => dqs_count_r(0), + I2 => \rd_data_edge_detect_r_reg_n_0_[1]\, + I3 => wl_edge_detect_valid_r_reg_n_0, + O => \FSM_sequential_wl_state_r[3]_i_7_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1D00000000000000" + ) + port map ( + I0 => \rd_data_previous_r_reg_n_0_[0]\, + I1 => dqs_count_r(0), + I2 => \rd_data_previous_r_reg_n_0_[1]\, + I3 => \stable_cnt_reg_n_0_[1]\, + I4 => \stable_cnt_reg_n_0_[3]\, + I5 => \stable_cnt_reg_n_0_[2]\, + O => \FSM_sequential_wl_state_r[3]_i_8_n_0\ + ); +\FSM_sequential_wl_state_r[3]_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => wr_level_done_r5, + I1 => wl_sm_start, + I2 => \wl_state_r__0\(1), + I3 => wrlvl_byte_redo, + O => \FSM_sequential_wl_state_r[3]_i_9_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF0FFF4F4" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_3_n_0\, + I1 => \FSM_sequential_wl_state_r[4]_i_4_n_0\, + I2 => \FSM_sequential_wl_state_r[4]_i_5_n_0\, + I3 => \FSM_sequential_wl_state_r[4]_i_6_n_0\, + I4 => \wl_state_r__0\(4), + I5 => \FSM_sequential_wl_state_r[4]_i_7_n_0\, + O => \FSM_sequential_wl_state_r[4]_i_1_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_10\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => wr_level_start_r, + I1 => wl_sm_start, + I2 => wr_level_done_r_reg_n_0, + O => \FSM_sequential_wl_state_r[4]_i_10_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_11\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0008000800088088" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(1), + I3 => inhibit_edge_detect_r_i_3_n_0, + I4 => \FSM_sequential_wl_state_r[4]_i_17_n_0\, + I5 => \wl_state_r__0\(0), + O => \FSM_sequential_wl_state_r[4]_i_11_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFCFAFAFFFC" + ) + port map ( + I0 => \corse_inc_reg_n_0_[1][1]\, + I1 => \corse_inc_reg_n_0_[0][1]\, + I2 => \corse_inc[1][0]_i_2_n_0\, + I3 => \corse_inc_reg_n_0_[0][2]\, + I4 => \dqs_count_r_reg[0]_rep_n_0\, + I5 => \corse_inc_reg_n_0_[1][2]\, + O => \FSM_sequential_wl_state_r[4]_i_12_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_13\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BAFFFFFFFFFFFFBB" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_18_n_0\, + I1 => \wl_state_r__0\(0), + I2 => \FSM_sequential_wl_state_r[4]_i_10_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(3), + I5 => \wl_state_r__0\(2), + O => \FSM_sequential_wl_state_r[4]_i_13_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_14\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => incdec_wait_cnt_reg(0), + I1 => incdec_wait_cnt_reg(1), + I2 => incdec_wait_cnt_reg(3), + I3 => incdec_wait_cnt_reg(2), + O => \FSM_sequential_wl_state_r[4]_i_14_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_15\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0FB0FFB0" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_19_n_0\, + I1 => inhibit_edge_detect_r_i_6_n_0, + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(2), + I4 => wr_level_done_r5, + O => \FSM_sequential_wl_state_r[4]_i_15_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_16\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFF0000E0" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => p_0_in, + I2 => \wl_state_r__0\(1), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(2), + I5 => \FSM_sequential_wl_state_r[4]_i_20_n_0\, + O => \FSM_sequential_wl_state_r[4]_i_16_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_17\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000305050003" + ) + port map ( + I0 => \corse_dec_reg[1]_6\(2), + I1 => \corse_dec_reg[0]_7\(2), + I2 => \corse_dec[1][2]_i_4_n_0\, + I3 => \corse_dec_reg[0]_7\(0), + I4 => dqs_count_r(0), + I5 => \corse_dec_reg[1]_6\(0), + O => \FSM_sequential_wl_state_r[4]_i_17_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_18\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4440444444404040" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => done_dqs_dec237_out, + I2 => \FSM_sequential_wl_state_r[4]_i_13_0\, + I3 => \final_coarse_tap_reg_n_0_[1][2]\, + I4 => \dqs_count_r_reg[1]_0\(0), + I5 => \final_coarse_tap_reg_n_0_[0][2]\, + O => \FSM_sequential_wl_state_r[4]_i_18_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_19\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \stable_cnt_reg_n_0_[2]\, + I1 => \stable_cnt_reg_n_0_[3]\, + I2 => \stable_cnt_reg_n_0_[1]\, + O => \FSM_sequential_wl_state_r[4]_i_19_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFF444F4F4" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_8_n_0\, + I1 => \wl_state_r__0\(0), + I2 => \FSM_sequential_wl_state_r[4]_i_9_n_0\, + I3 => \FSM_sequential_wl_state_r[4]_i_10_n_0\, + I4 => \wl_state_r__0\(3), + I5 => \FSM_sequential_wl_state_r[4]_i_11_n_0\, + O => \FSM_sequential_wl_state_r[4]_i_2_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_20\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E200000000000000" + ) + port map ( + I0 => \rd_data_edge_detect_r_reg_n_0_[0]\, + I1 => dqs_count_r(0), + I2 => \rd_data_edge_detect_r_reg_n_0_[1]\, + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(4), + I5 => wl_edge_detect_valid_r_reg_n_0, + O => \FSM_sequential_wl_state_r[4]_i_20_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000FF00F100FF0" + ) + port map ( + I0 => wr_level_done_r5, + I1 => wrlvl_byte_redo, + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(2), + I4 => \wl_state_r__0\(1), + I5 => wl_sm_start, + O => \FSM_sequential_wl_state_r[4]_i_3_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF80808000" + ) + port map ( + I0 => wr_level_done_r5, + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(1), + I3 => \fine_inc[1][5]_i_5_n_0\, + I4 => \FSM_sequential_wl_state_r[4]_i_12_n_0\, + I5 => \FSM_sequential_wl_state_r[4]_i_13_n_0\, + O => \FSM_sequential_wl_state_r[4]_i_4_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000FF0E00000000" + ) + port map ( + I0 => wrlvl_byte_redo, + I1 => wl_sm_start, + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(2), + I5 => \wl_state_r__0\(1), + O => \FSM_sequential_wl_state_r[4]_i_5_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF00708A8A7575" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => \FSM_sequential_wl_state_r[4]_i_14_n_0\, + I2 => \wl_state_r__0\(1), + I3 => wl_sm_start, + I4 => \wl_state_r__0\(2), + I5 => \wl_state_r__0\(3), + O => \FSM_sequential_wl_state_r[4]_i_6_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0450000004550005" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(2), + I4 => wl_sm_start, + I5 => \FSM_sequential_wl_state_r[4]_i_14_n_0\, + O => \FSM_sequential_wl_state_r[4]_i_7_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3032333233323332" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_15_n_0\, + I1 => \FSM_sequential_wl_state_r[4]_i_16_n_0\, + I2 => \wl_state_r__0\(1), + I3 => \wl_state_r__0\(4), + I4 => inhibit_edge_detect_r_i_3_n_0, + I5 => \wl_state_r__0\(3), + O => \FSM_sequential_wl_state_r[4]_i_8_n_0\ + ); +\FSM_sequential_wl_state_r[4]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(2), + O => \FSM_sequential_wl_state_r[4]_i_9_n_0\ + ); +\FSM_sequential_wl_state_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\, + D => \FSM_sequential_wl_state_r[0]_i_1_n_0\, + Q => \wl_state_r__0\(0), + R => \dqs_count_r_reg[0]_0\ + ); +\FSM_sequential_wl_state_r_reg[1]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\, + D => \FSM_sequential_wl_state_r[1]_i_1_n_0\, + Q => \wl_state_r__0\(1), + S => \dqs_count_r_reg[0]_0\ + ); +\FSM_sequential_wl_state_r_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\, + D => \FSM_sequential_wl_state_r[2]_i_1_n_0\, + Q => \wl_state_r__0\(2), + S => \dqs_count_r_reg[0]_0\ + ); +\FSM_sequential_wl_state_r_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\, + D => \FSM_sequential_wl_state_r[3]_i_1_n_0\, + Q => \wl_state_r__0\(3), + S => \dqs_count_r_reg[0]_0\ + ); +\FSM_sequential_wl_state_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \FSM_sequential_wl_state_r[4]_i_1_n_0\, + D => \FSM_sequential_wl_state_r[4]_i_2_n_0\, + Q => \wl_state_r__0\(4), + R => \dqs_count_r_reg[0]_0\ + ); +\calib_sel[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000002AEA2A2A" + ) + port map ( + I0 => \calib_sel_reg[0]_0\, + I1 => \^cmd_delay_start0\, + I2 => calib_sel15_out, + I3 => \calib_sel_reg[0]_1\, + I4 => \calib_sel_reg[0]_2\, + I5 => calib_sel0, + O => \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ + ); +\corse_cnt[0][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_cnt(0), + I1 => \corse_cnt[0][2]_i_3_n_0\, + I2 => \corse_cnt_reg_n_0_[0][0]\, + O => \corse_cnt[0][0]_i_1_n_0\ + ); +\corse_cnt[0][0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAA88A88888" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \corse_cnt[0][0]_i_3_n_0\, + I2 => \corse_cnt[0][0]_i_4_n_0\, + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(2), + I5 => \corse_cnt[0][0]_i_5_n_0\, + O => corse_cnt(0) + ); +\corse_cnt[0][0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F4F444F4F4444444" + ) + port map ( + I0 => \wl_corse_cnt[0][0][0]_i_1_n_0\, + I1 => wl_edge_detect_valid_r, + I2 => inhibit_edge_detect_r_i_2_n_0, + I3 => dqs_count_r(0), + I4 => \^final_coarse_tap_reg[1][0]_0\(0), + I5 => \^final_coarse_tap_reg[0][0]_0\(0), + O => \corse_cnt[0][0]_i_3_n_0\ + ); +\corse_cnt[0][0]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \^final_coarse_tap_reg[1][0]_0\(0), + I1 => \dqs_count_r_reg[1]_0\(0), + I2 => \^final_coarse_tap_reg[0][0]_0\(0), + O => \corse_cnt[0][0]_i_4_n_0\ + ); +\corse_cnt[0][0]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => p_0_in, + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(3), + O => \corse_cnt[0][0]_i_5_n_0\ + ); +\corse_cnt[0][0]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(2), + O => wl_edge_detect_valid_r + ); +\corse_cnt[0][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_cnt(1), + I1 => \corse_cnt[0][2]_i_3_n_0\, + I2 => \corse_cnt_reg_n_0_[0][1]\, + O => \corse_cnt[0][1]_i_1_n_0\ + ); +\corse_cnt[0][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"888A8A8888888888" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \corse_cnt[0][1]_i_3_n_0\, + I2 => \wl_state_r__0\(2), + I3 => \wl_corse_cnt[0][0][1]_i_1_n_0\, + I4 => \wl_corse_cnt[0][0][0]_i_1_n_0\, + I5 => \wl_state_r__0\(3), + O => corse_cnt(1) + ); +\corse_cnt[0][1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAEAAAEAAAFFAAEA" + ) + port map ( + I0 => \corse_cnt[0][1]_i_4_n_0\, + I1 => \^final_coarse_tap_reg[1][1]_0\, + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(4), + I4 => p_0_in, + I5 => \wl_state_r__0\(3), + O => \corse_cnt[0][1]_i_3_n_0\ + ); +\corse_cnt[0][1]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CA00" + ) + port map ( + I0 => \final_coarse_tap_reg_n_0_[0][1]\, + I1 => \final_coarse_tap_reg_n_0_[1][1]\, + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(2), + O => \corse_cnt[0][1]_i_4_n_0\ + ); +\corse_cnt[0][1]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \final_coarse_tap_reg_n_0_[1][1]\, + I1 => \dqs_count_r_reg[1]_0\(0), + I2 => \final_coarse_tap_reg_n_0_[0][1]\, + O => \^final_coarse_tap_reg[1][1]_0\ + ); +\corse_cnt[0][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_cnt(2), + I1 => \corse_cnt[0][2]_i_3_n_0\, + I2 => \corse_cnt_reg_n_0_[0][2]\, + O => \corse_cnt[0][2]_i_1_n_0\ + ); +\corse_cnt[0][2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAA2000AAAA2A0A" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(2), + I3 => \corse_cnt[0][2]_i_4_n_0\, + I4 => \corse_cnt[0][2]_i_5_n_0\, + I5 => \corse_cnt[0][2]_i_6_n_0\, + O => corse_cnt(2) + ); +\corse_cnt[0][2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF4040FF40" + ) + port map ( + I0 => \corse_cnt[0][2]_i_7_n_0\, + I1 => done_dqs_dec237_out, + I2 => \wl_state_r__0\(3), + I3 => \fine_inc[0][5]_i_3_n_0\, + I4 => \corse_cnt[0][2]_i_8_n_0\, + I5 => rank_cnt_r, + O => \corse_cnt[0][2]_i_3_n_0\ + ); +\corse_cnt[0][2]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \final_coarse_tap_reg_n_0_[1][2]\, + I1 => \dqs_count_r_reg[1]_0\(0), + I2 => \final_coarse_tap_reg_n_0_[0][2]\, + O => \corse_cnt[0][2]_i_4_n_0\ + ); +\corse_cnt[0][2]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAEFEAAAAA" + ) + port map ( + I0 => \corse_cnt[0][0]_i_5_n_0\, + I1 => \final_coarse_tap_reg_n_0_[1][2]\, + I2 => dqs_count_r(0), + I3 => \final_coarse_tap_reg_n_0_[0][2]\, + I4 => \wl_state_r__0\(4), + I5 => \wl_state_r__0\(2), + O => \corse_cnt[0][2]_i_5_n_0\ + ); +\corse_cnt[0][2]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A9595555FFFFFFFF" + ) + port map ( + I0 => \wl_corse_cnt[0][0][2]_i_1_n_0\, + I1 => \corse_cnt_reg_n_0_[0][1]\, + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \corse_cnt_reg_n_0_[1][1]\, + I4 => \wl_corse_cnt[0][0][0]_i_1_n_0\, + I5 => \wl_state_r__0\(3), + O => \corse_cnt[0][2]_i_6_n_0\ + ); +\corse_cnt[0][2]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFDFFFF" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + I2 => \dqs_count_r_reg[1]_0\(1), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(2), + I5 => \dqs_count_r_reg[1]_0\(0), + O => \corse_cnt[0][2]_i_7_n_0\ + ); +\corse_cnt[0][2]_i_8\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FDFFFDFFFFFFFDFF" + ) + port map ( + I0 => flag_ck_negedge_i_3_n_0, + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(3), + I4 => wr_level_done_r5, + I5 => wrlvl_byte_redo, + O => \corse_cnt[0][2]_i_8_n_0\ + ); +\corse_cnt[1][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_cnt(0), + I1 => \corse_cnt[1][2]_i_2_n_0\, + I2 => \corse_cnt_reg_n_0_[1][0]\, + O => \corse_cnt[1][0]_i_1_n_0\ + ); +\corse_cnt[1][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_cnt(1), + I1 => \corse_cnt[1][2]_i_2_n_0\, + I2 => \corse_cnt_reg_n_0_[1][1]\, + O => \corse_cnt[1][1]_i_1_n_0\ + ); +\corse_cnt[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_cnt(2), + I1 => \corse_cnt[1][2]_i_2_n_0\, + I2 => \corse_cnt_reg_n_0_[1][2]\, + O => \corse_cnt[1][2]_i_1_n_0\ + ); +\corse_cnt[1][2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF0404FF04" + ) + port map ( + I0 => \corse_cnt[0][2]_i_8_n_0\, + I1 => dqs_count_r(0), + I2 => dqs_count_r(1), + I3 => \corse_inc[1][2]_i_3_n_0\, + I4 => \corse_cnt[1][2]_i_3_n_0\, + I5 => rank_cnt_r, + O => \corse_cnt[1][2]_i_2_n_0\ + ); +\corse_cnt[1][2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFDFFFFFFFFFF" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + I2 => \dqs_count_r_reg[1]_0\(1), + I3 => wrlvl_byte_redo, + I4 => \^wrlvl_byte_redo_r\, + I5 => \dqs_count_r_reg[1]_0\(0), + O => \corse_cnt[1][2]_i_3_n_0\ + ); +\corse_cnt_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_cnt[0][0]_i_1_n_0\, + Q => \corse_cnt_reg_n_0_[0][0]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_cnt_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_cnt[0][1]_i_1_n_0\, + Q => \corse_cnt_reg_n_0_[0][1]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_cnt_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_cnt[0][2]_i_1_n_0\, + Q => \corse_cnt_reg_n_0_[0][2]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_cnt_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_cnt[1][0]_i_1_n_0\, + Q => \corse_cnt_reg_n_0_[1][0]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_cnt_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_cnt[1][1]_i_1_n_0\, + Q => \corse_cnt_reg_n_0_[1][1]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_cnt_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_cnt[1][2]_i_1_n_0\, + Q => \corse_cnt_reg_n_0_[1][2]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_dec[0][0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20FF2000" + ) + port map ( + I0 => \corse_dec[1][1]_i_2_n_0\, + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(4), + I3 => \corse_dec[0][2]_i_2_n_0\, + I4 => \corse_dec_reg[0]_7\(0), + O => \corse_dec[0][0]_i_1_n_0\ + ); +\corse_dec[0][1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"6500FFFF6A000000" + ) + port map ( + I0 => \corse_dec[1][1]_i_2_n_0\, + I1 => \corse_dec_reg[1]_6\(1), + I2 => dqs_count_r(0), + I3 => \corse_dec[1][1]_i_3_n_0\, + I4 => \corse_dec[0][2]_i_2_n_0\, + I5 => \corse_dec_reg[0]_7\(1), + O => \corse_dec[0][1]_i_1_n_0\ + ); +\corse_dec[0][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_dec(2), + I1 => \corse_dec[0][2]_i_2_n_0\, + I2 => \corse_dec_reg[0]_7\(2), + O => \corse_dec[0][2]_i_1_n_0\ + ); +\corse_dec[0][2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000800000" + ) + port map ( + I0 => \fine_inc[0][5]_i_3_n_0\, + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(1), + I5 => \wl_state_r__0\(0), + O => \corse_dec[0][2]_i_2_n_0\ + ); +\corse_dec[1][0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"20FF2000" + ) + port map ( + I0 => \corse_dec[1][1]_i_2_n_0\, + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(4), + I3 => \corse_dec[1][2]_i_3_n_0\, + I4 => \corse_dec_reg[1]_6\(0), + O => \corse_dec[1][0]_i_1_n_0\ + ); +\corse_dec[1][1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5600FFFF9A000000" + ) + port map ( + I0 => \corse_dec[1][1]_i_2_n_0\, + I1 => dqs_count_r(0), + I2 => \corse_dec_reg[0]_7\(1), + I3 => \corse_dec[1][1]_i_3_n_0\, + I4 => \corse_dec[1][2]_i_3_n_0\, + I5 => \corse_dec_reg[1]_6\(1), + O => \corse_dec[1][1]_i_1_n_0\ + ); +\corse_dec[1][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000FCFAFA00FC" + ) + port map ( + I0 => \corse_dec_reg[1]_6\(2), + I1 => \corse_dec_reg[0]_7\(2), + I2 => \corse_dec[1][2]_i_4_n_0\, + I3 => \corse_dec_reg[0]_7\(0), + I4 => dqs_count_r(0), + I5 => \corse_dec_reg[1]_6\(0), + O => \corse_dec[1][1]_i_2_n_0\ + ); +\corse_dec[1][1]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(3), + O => \corse_dec[1][1]_i_3_n_0\ + ); +\corse_dec[1][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => corse_dec(2), + I1 => \corse_dec[1][2]_i_3_n_0\, + I2 => \corse_dec_reg[1]_6\(2), + O => \corse_dec[1][2]_i_1_n_0\ + ); +\corse_dec[1][2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"D000D0D0D0000000" + ) + port map ( + I0 => \corse_dec[1][1]_i_2_n_0\, + I1 => \corse_dec[1][2]_i_4_n_0\, + I2 => \corse_dec[1][1]_i_3_n_0\, + I3 => \corse_dec_reg[1]_6\(2), + I4 => dqs_count_r(0), + I5 => \corse_dec_reg[0]_7\(2), + O => corse_dec(2) + ); +\corse_dec[1][2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000800000" + ) + port map ( + I0 => \fine_inc[1][5]_i_4_n_0\, + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(1), + I5 => \wl_state_r__0\(0), + O => \corse_dec[1][2]_i_3_n_0\ + ); +\corse_dec[1][2]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \corse_dec_reg[1]_6\(1), + I1 => dqs_count_r(0), + I2 => \corse_dec_reg[0]_7\(1), + O => \corse_dec[1][2]_i_4_n_0\ + ); +\corse_dec_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_dec[0][0]_i_1_n_0\, + Q => \corse_dec_reg[0]_7\(0), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_dec_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_dec[0][1]_i_1_n_0\, + Q => \corse_dec_reg[0]_7\(1), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_dec_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_dec[0][2]_i_1_n_0\, + Q => \corse_dec_reg[0]_7\(2), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_dec_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_dec[1][0]_i_1_n_0\, + Q => \corse_dec_reg[1]_6\(0), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_dec_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_dec[1][1]_i_1_n_0\, + Q => \corse_dec_reg[1]_6\(1), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_dec_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_dec[1][2]_i_1_n_0\, + Q => \corse_dec_reg[1]_6\(2), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\corse_inc[0][0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"888FFFFF888F0000" + ) + port map ( + I0 => \corse_inc[1][2]_i_3_n_0\, + I1 => \^final_coarse_tap_reg[0][0]_0\(0), + I2 => \corse_inc[1][0]_i_2_n_0\, + I3 => \wl_state_r__0\(2), + I4 => \corse_inc[0][2]_i_2_n_0\, + I5 => \corse_inc_reg_n_0_[0][0]\, + O => \corse_inc[0][0]_i_1_n_0\ + ); +\corse_inc[0][1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8FFF800" + ) + port map ( + I0 => \corse_inc[1][2]_i_3_n_0\, + I1 => \final_coarse_tap_reg_n_0_[0][1]\, + I2 => \corse_inc[1][1]_i_2_n_0\, + I3 => \corse_inc[0][2]_i_2_n_0\, + I4 => \corse_inc_reg_n_0_[0][1]\, + O => \corse_inc[0][1]_i_1_n_0\ + ); +\corse_inc[0][2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F8FFF800" + ) + port map ( + I0 => \corse_inc[1][2]_i_3_n_0\, + I1 => \final_coarse_tap_reg_n_0_[0][2]\, + I2 => \corse_inc[1][2]_i_2_n_0\, + I3 => \corse_inc[0][2]_i_2_n_0\, + I4 => \corse_inc_reg_n_0_[0][2]\, + O => \corse_inc[0][2]_i_1_n_0\ + ); +\corse_inc[0][2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0808AA0808080808" + ) + port map ( + I0 => \corse_inc[1][2]_i_6_n_0\, + I1 => \fine_inc[0][5]_i_3_n_0\, + I2 => \corse_inc[1][2]_i_7_n_0\, + I3 => wr_level_done_r4, + I4 => wr_level_done_r5, + I5 => \wl_state_r__0\(2), + O => \corse_inc[0][2]_i_2_n_0\ + ); +\corse_inc[1][0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F111FFFFF1110000" + ) + port map ( + I0 => \corse_inc[1][0]_i_2_n_0\, + I1 => \wl_state_r__0\(2), + I2 => \corse_inc[1][2]_i_3_n_0\, + I3 => \^final_coarse_tap_reg[1][0]_0\(0), + I4 => \corse_inc[1][2]_i_4_n_0\, + I5 => \corse_inc_reg_n_0_[1][0]\, + O => \corse_inc[1][0]_i_1_n_0\ + ); +\corse_inc[1][0]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \corse_inc_reg_n_0_[1][0]\, + I1 => \dqs_count_r_reg[0]_rep_n_0\, + I2 => \corse_inc_reg_n_0_[0][0]\, + O => \corse_inc[1][0]_i_2_n_0\ + ); +\corse_inc[1][1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAFFEA00" + ) + port map ( + I0 => \corse_inc[1][1]_i_2_n_0\, + I1 => \corse_inc[1][2]_i_3_n_0\, + I2 => \final_coarse_tap_reg_n_0_[1][1]\, + I3 => \corse_inc[1][2]_i_4_n_0\, + I4 => \corse_inc_reg_n_0_[1][1]\, + O => \corse_inc[1][1]_i_1_n_0\ + ); +\corse_inc[1][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4540151040451015" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \corse_inc_reg_n_0_[1][1]\, + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \corse_inc_reg_n_0_[0][1]\, + I4 => \corse_inc_reg_n_0_[1][0]\, + I5 => \corse_inc_reg_n_0_[0][0]\, + O => \corse_inc[1][1]_i_2_n_0\ + ); +\corse_inc[1][2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"EAFFEA00" + ) + port map ( + I0 => \corse_inc[1][2]_i_2_n_0\, + I1 => \corse_inc[1][2]_i_3_n_0\, + I2 => \final_coarse_tap_reg_n_0_[1][2]\, + I3 => \corse_inc[1][2]_i_4_n_0\, + I4 => \corse_inc_reg_n_0_[1][2]\, + O => \corse_inc[1][2]_i_1_n_0\ + ); +\corse_inc[1][2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45401015" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \corse_inc_reg_n_0_[1][2]\, + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \corse_inc_reg_n_0_[0][2]\, + I4 => \corse_inc[1][2]_i_5_n_0\, + O => \corse_inc[1][2]_i_2_n_0\ + ); +\corse_inc[1][2]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(2), + O => \corse_inc[1][2]_i_3_n_0\ + ); +\corse_inc[1][2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0808AA0808080808" + ) + port map ( + I0 => \corse_inc[1][2]_i_6_n_0\, + I1 => \fine_inc[1][5]_i_4_n_0\, + I2 => \corse_inc[1][2]_i_7_n_0\, + I3 => wr_level_done_r4, + I4 => wr_level_done_r5, + I5 => \wl_state_r__0\(2), + O => \corse_inc[1][2]_i_4_n_0\ + ); +\corse_inc[1][2]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFACCFA" + ) + port map ( + I0 => \corse_inc_reg_n_0_[0][0]\, + I1 => \corse_inc_reg_n_0_[1][0]\, + I2 => \corse_inc_reg_n_0_[0][1]\, + I3 => \dqs_count_r_reg[0]_rep_n_0\, + I4 => \corse_inc_reg_n_0_[1][1]\, + O => \corse_inc[1][2]_i_5_n_0\ + ); +\corse_inc[1][2]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(3), + O => \corse_inc[1][2]_i_6_n_0\ + ); +\corse_inc[1][2]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFDF" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_12_n_0\, + I1 => \wl_state_r__0\(2), + I2 => wr_level_done_r5, + I3 => wrlvl_byte_redo, + O => \corse_inc[1][2]_i_7_n_0\ + ); +\corse_inc_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_inc[0][0]_i_1_n_0\, + Q => \corse_inc_reg_n_0_[0][0]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\corse_inc_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_inc[0][1]_i_1_n_0\, + Q => \corse_inc_reg_n_0_[0][1]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\corse_inc_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_inc[0][2]_i_1_n_0\, + Q => \corse_inc_reg_n_0_[0][2]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\corse_inc_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_inc[1][0]_i_1_n_0\, + Q => \corse_inc_reg_n_0_[1][0]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\corse_inc_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_inc[1][1]_i_1_n_0\, + Q => \corse_inc_reg_n_0_[1][1]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\corse_inc_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \corse_inc[1][2]_i_1_n_0\, + Q => \corse_inc_reg_n_0_[1][2]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +delay_dec_done_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^dqs_po_dec_done_reg_0\, + I1 => \calib_sel_reg[0]_3\, + O => \^cmd_delay_start0\ + ); +dq_cnt_inc_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFEFBFFF00208000" + ) + port map ( + I0 => dq_cnt_inc_i_2_n_0, + I1 => \wl_state_r__0\(2), + I2 => dq_cnt_inc_i_3_n_0, + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(1), + I5 => p_0_in, + O => dq_cnt_inc_i_1_n_0 + ); +dq_cnt_inc_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000B00BBBBBBBB" + ) + port map ( + I0 => dqs_count_r(1), + I1 => dqs_count_r(0), + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(4), + I4 => wrlvl_byte_redo, + I5 => \wl_state_r__0\(2), + O => dq_cnt_inc_i_2_n_0 + ); +dq_cnt_inc_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(0), + O => dq_cnt_inc_i_3_n_0 + ); +dq_cnt_inc_reg: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => dq_cnt_inc_i_1_n_0, + Q => p_0_in, + S => \dqs_count_r_reg[0]_0\ + ); +\dqs_count_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"EFE0" + ) + port map ( + I0 => \dqs_count_r[0]_i_2_n_0\, + I1 => \dqs_count_r[0]_i_3_n_0\, + I2 => \dqs_count_r[1]_i_5_n_0\, + I3 => \dqs_count_r_reg[0]_rep_n_0\, + O => \dqs_count_r[0]_i_1_n_0\ + ); +\dqs_count_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAEAAAEAAAE0000" + ) + port map ( + I0 => \dqs_count_r[0]_i_4_n_0\, + I1 => \dqs_count_r[0]_i_5_n_0\, + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(3), + I4 => \dqs_count_r[0]_i_6_n_0\, + I5 => \wl_state_r__0\(4), + O => \dqs_count_r[0]_i_2_n_0\ + ); +\dqs_count_r[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A8FFFFFFA8A82020" + ) + port map ( + I0 => \dqs_count_r[0]_i_7_n_0\, + I1 => \dqs_count_r[1]_i_8_n_0\, + I2 => \dqs_count_r[0]_i_5_n_0\, + I3 => dqs_count_r(1), + I4 => dqs_count_r(0), + I5 => \dqs_count_r[0]_i_8_n_0\, + O => \dqs_count_r[0]_i_3_n_0\ + ); +\dqs_count_r[0]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"40044404FFFFFFFF" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(2), + I2 => wrlvl_byte_redo, + I3 => dqs_count_r(0), + I4 => dqs_count_r(1), + I5 => \wl_state_r__0\(4), + O => \dqs_count_r[0]_i_4_n_0\ + ); +\dqs_count_r[0]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF03F503" + ) + port map ( + I0 => dqs_count_r(1), + I1 => \fine_inc_reg[0]_3\(5), + I2 => \fine_inc[1][5]_i_7_n_0\, + I3 => \dqs_count_r_reg[0]_rep_n_0\, + I4 => \fine_inc_reg[1]_2\(5), + O => \dqs_count_r[0]_i_5_n_0\ + ); +\dqs_count_r[0]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF80B080B080B080" + ) + port map ( + I0 => \dqs_count_r_reg[1]_0\(0), + I1 => done_dqs_dec237_out, + I2 => \FSM_sequential_wl_state_r[4]_i_9_n_0\, + I3 => dqs_count_r(0), + I4 => flag_ck_negedge_i_3_n_0, + I5 => \dqs_count_r[1]_i_10_n_0\, + O => \dqs_count_r[0]_i_6_n_0\ + ); +\dqs_count_r[0]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(0), + O => \dqs_count_r[0]_i_7_n_0\ + ); +\dqs_count_r[0]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(3), + O => \dqs_count_r[0]_i_8_n_0\ + ); +\dqs_count_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEFFFFFEEEF0000" + ) + port map ( + I0 => \dqs_count_r[1]_i_2_n_0\, + I1 => \dqs_count_r[1]_i_3_n_0\, + I2 => \wl_state_r__0\(4), + I3 => \dqs_count_r[1]_i_4_n_0\, + I4 => \dqs_count_r[1]_i_5_n_0\, + I5 => dqs_count_r(1), + O => \dqs_count_r[1]_i_1_n_0\ + ); +\dqs_count_r[1]_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFBFBFB0" + ) + port map ( + I0 => wr_level_done_r5, + I1 => wr_level_done_r4, + I2 => \wl_state_r__0\(2), + I3 => wrlvl_byte_redo, + I4 => p_0_in, + O => \dqs_count_r[1]_i_10_n_0\ + ); +\dqs_count_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"1504000000000000" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(2), + I2 => \dqs_count_r[1]_i_6_n_0\, + I3 => \dqs_count_r[1]_i_7_n_0\, + I4 => dqs_count_r(1), + I5 => \wl_state_r__0\(4), + O => \dqs_count_r[1]_i_2_n_0\ + ); +\dqs_count_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E000E0F000000000" + ) + port map ( + I0 => \dqs_count_r[1]_i_8_n_0\, + I1 => \dqs_count_r[1]_i_7_n_0\, + I2 => dqs_count_r(1), + I3 => \wl_state_r__0\(3), + I4 => dqs_count_r(0), + I5 => \dqs_count_r[1]_i_9_n_0\, + O => \dqs_count_r[1]_i_3_n_0\ + ); +\dqs_count_r[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"007F4F7F4F7F4F7F" + ) + port map ( + I0 => \dqs_count_r_reg[1]_0\(1), + I1 => done_dqs_dec237_out, + I2 => \FSM_sequential_wl_state_r[4]_i_9_n_0\, + I3 => dqs_count_r(1), + I4 => flag_ck_negedge_i_3_n_0, + I5 => \dqs_count_r[1]_i_10_n_0\, + O => \dqs_count_r[1]_i_4_n_0\ + ); +\dqs_count_r[1]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00C4180C" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(3), + O => \dqs_count_r[1]_i_5_n_0\ + ); +\dqs_count_r[1]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \dqs_count_r_reg[0]_rep_n_0\, + I1 => wrlvl_byte_redo, + O => \dqs_count_r[1]_i_6_n_0\ + ); +\dqs_count_r[1]_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FB" + ) + port map ( + I0 => \fine_inc[1][5]_i_7_n_0\, + I1 => \dqs_count_r_reg[0]_rep_n_0\, + I2 => \fine_inc_reg[1]_2\(5), + O => \dqs_count_r[1]_i_7_n_0\ + ); +\dqs_count_r[1]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EF" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[4]_i_12_n_0\, + I1 => wrlvl_byte_redo, + I2 => wr_level_done_r5, + O => \dqs_count_r[1]_i_8_n_0\ + ); +\dqs_count_r[1]_i_9\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(0), + O => \dqs_count_r[1]_i_9_n_0\ + ); +\dqs_count_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \dqs_count_r[0]_i_1_n_0\, + Q => dqs_count_r(0), + R => \dqs_count_r_reg[0]_0\ + ); +\dqs_count_r_reg[0]_rep\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \dqs_count_r[0]_i_1_n_0\, + Q => \dqs_count_r_reg[0]_rep_n_0\, + R => \dqs_count_r_reg[0]_rep_0\(0) + ); +\dqs_count_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \dqs_count_r[1]_i_1_n_0\, + Q => dqs_count_r(1), + R => \dqs_count_r_reg[0]_0\ + ); +dqs_po_dec_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => po_dec_done, + Q => \^dqs_po_dec_done_reg_0\, + R => '0' + ); +dqs_po_en_stg2_f_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAABAAAEAEB" + ) + port map ( + I0 => \^po_cnt_dec_reg_0\, + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(4), + I5 => \wl_state_r__0\(1), + O => dqs_po_en_stg2_f_i_1_n_0 + ); +dqs_po_en_stg2_f_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_po_en_stg2_f_i_1_n_0, + Q => dqs_po_en_stg2_f, + R => dqs_po_en_stg2_f_reg_0(0) + ); +dqs_po_stg2_f_incdec_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000002000000" + ) + port map ( + I0 => dqs_po_stg2_f_incdec_i_2_n_0, + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(2), + I4 => \wl_state_r__0\(3), + I5 => \rd_data_edge_detect_r_reg[1]_0\, + O => dqs_po_stg2_f_incdec_i_1_n_0 + ); +dqs_po_stg2_f_incdec_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFFFBFFE" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(2), + I5 => \^po_cnt_dec_reg_0\, + O => dqs_po_stg2_f_incdec_i_2_n_0 + ); +dqs_po_stg2_f_incdec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_po_stg2_f_incdec_i_1_n_0, + Q => \^dqs_po_stg2_f_incdec\, + R => '0' + ); +dqs_wl_po_stg2_c_incdec_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(1), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(2), + O => dqs_wl_po_stg2_c_incdec_i_1_n_0 + ); +dqs_wl_po_stg2_c_incdec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => dqs_wl_po_stg2_c_incdec_i_1_n_0, + Q => po_stg2_cincdec(2), + R => \dqs_count_r_reg[0]_0\ + ); +\final_coarse_tap_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_corse_cnt_reg[0][0]_8\(0), + Q => \^final_coarse_tap_reg[0][0]_0\(0), + R => '0' + ); +\final_coarse_tap_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_corse_cnt_reg[0][0]_8\(1), + Q => \final_coarse_tap_reg_n_0_[0][1]\, + R => '0' + ); +\final_coarse_tap_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_corse_cnt_reg[0][0]_8\(2), + Q => \final_coarse_tap_reg_n_0_[0][2]\, + R => '0' + ); +\final_coarse_tap_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_corse_cnt_reg[0][1]_9\(0), + Q => \^final_coarse_tap_reg[1][0]_0\(0), + R => '0' + ); +\final_coarse_tap_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_corse_cnt_reg[0][1]_9\(1), + Q => \final_coarse_tap_reg_n_0_[1][1]\, + R => '0' + ); +\final_coarse_tap_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_corse_cnt_reg[0][1]_9\(2), + Q => \final_coarse_tap_reg_n_0_[1][2]\, + R => '0' + ); +\fine_dec_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000CCCC55C5" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[0]\, + I1 => \wl_tap_count_r_reg_n_0_[0]\, + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(1), + I5 => \wl_state_r__0\(2), + O => fine_dec_cnt(0) + ); +\fine_dec_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000E22E" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[1]\, + I1 => \fine_dec_cnt[5]_i_8_n_0\, + I2 => \fine_dec_cnt_reg_n_0_[0]\, + I3 => \fine_dec_cnt_reg_n_0_[1]\, + I4 => \wl_state_r__0\(2), + O => fine_dec_cnt(1) + ); +\fine_dec_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000A9A9FF00" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[2]\, + I1 => \fine_dec_cnt_reg_n_0_[0]\, + I2 => \fine_dec_cnt_reg_n_0_[1]\, + I3 => \wl_tap_count_r_reg_n_0_[2]\, + I4 => \fine_dec_cnt[5]_i_8_n_0\, + I5 => \wl_state_r__0\(2), + O => fine_dec_cnt(2) + ); +\fine_dec_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000099F0" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[3]\, + I1 => \fine_dec_cnt[3]_i_2_n_0\, + I2 => \wl_tap_count_r_reg_n_0_[3]\, + I3 => \fine_dec_cnt[5]_i_8_n_0\, + I4 => \wl_state_r__0\(2), + O => fine_dec_cnt(3) + ); +\fine_dec_cnt[3]_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[2]\, + I1 => \fine_dec_cnt_reg_n_0_[0]\, + I2 => \fine_dec_cnt_reg_n_0_[1]\, + O => \fine_dec_cnt[3]_i_2_n_0\ + ); +\fine_dec_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000099F0" + ) + port map ( + I0 => \fine_dec_cnt[4]_i_2_n_0\, + I1 => \fine_dec_cnt_reg_n_0_[4]\, + I2 => \wl_tap_count_r_reg_n_0_[4]\, + I3 => \fine_dec_cnt[5]_i_8_n_0\, + I4 => \wl_state_r__0\(2), + O => fine_dec_cnt(4) + ); +\fine_dec_cnt[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[3]\, + I1 => \fine_dec_cnt_reg_n_0_[1]\, + I2 => \fine_dec_cnt_reg_n_0_[0]\, + I3 => \fine_dec_cnt_reg_n_0_[2]\, + O => \fine_dec_cnt[4]_i_2_n_0\ + ); +\fine_dec_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EEEEEAAAAAAAAAAA" + ) + port map ( + I0 => \fine_dec_cnt[5]_i_3_n_0\, + I1 => \fine_dec_cnt[5]_i_4_n_0\, + I2 => \fine_dec_cnt[5]_i_5_n_0\, + I3 => wl_sm_start, + I4 => \wl_state_r__0\(4), + I5 => \fine_dec_cnt[5]_i_6_n_0\, + O => \fine_dec_cnt[5]_i_1_n_0\ + ); +\fine_dec_cnt[5]_i_10\: unisim.vcomponents.LUT6 + generic map( + INIT => X"C000A0A0C0000000" + ) + port map ( + I0 => \corse_cnt_reg_n_0_[0][2]\, + I1 => \corse_cnt_reg_n_0_[1][2]\, + I2 => \wl_corse_cnt[0][0][0]_i_1_n_0\, + I3 => \corse_cnt_reg_n_0_[1][1]\, + I4 => \dqs_count_r_reg[0]_rep_n_0\, + I5 => \corse_cnt_reg_n_0_[0][1]\, + O => \fine_dec_cnt[5]_i_10_n_0\ + ); +\fine_dec_cnt[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000099F0" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[5]\, + I1 => \fine_dec_cnt[5]_i_7_n_0\, + I2 => \wl_tap_count_r_reg_n_0_[5]\, + I3 => \fine_dec_cnt[5]_i_8_n_0\, + I4 => \wl_state_r__0\(2), + O => fine_dec_cnt(5) + ); +\fine_dec_cnt[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0002808200020002" + ) + port map ( + I0 => \dqs_count_r[0]_i_8_n_0\, + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(4), + I3 => inhibit_edge_detect_r_i_3_n_0, + I4 => \rd_data_edge_detect_r[1]_i_3_n_0\, + I5 => wrlvl_byte_redo, + O => \fine_dec_cnt[5]_i_3_n_0\ + ); +\fine_dec_cnt[5]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"40" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(0), + O => \fine_dec_cnt[5]_i_4_n_0\ + ); +\fine_dec_cnt[5]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E200000000000000" + ) + port map ( + I0 => \rd_data_previous_r_reg_n_0_[0]\, + I1 => dqs_count_r(0), + I2 => \rd_data_previous_r_reg_n_0_[1]\, + I3 => \stable_cnt_reg_n_0_[1]\, + I4 => \stable_cnt_reg_n_0_[3]\, + I5 => \stable_cnt_reg_n_0_[2]\, + O => \fine_dec_cnt[5]_i_5_n_0\ + ); +\fine_dec_cnt[5]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"020002FF00FF00FF" + ) + port map ( + I0 => wl_edge_detect_valid_r_reg_n_0, + I1 => \fine_dec_cnt[5]_i_9_n_0\, + I2 => \fine_dec_cnt[5]_i_10_n_0\, + I3 => \wl_state_r__0\(1), + I4 => inhibit_edge_detect_r_i_3_n_0, + I5 => \wl_state_r__0\(4), + O => \fine_dec_cnt[5]_i_6_n_0\ + ); +\fine_dec_cnt[5]_i_7\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[4]\, + I1 => \fine_dec_cnt_reg_n_0_[2]\, + I2 => \fine_dec_cnt_reg_n_0_[0]\, + I3 => \fine_dec_cnt_reg_n_0_[1]\, + I4 => \fine_dec_cnt_reg_n_0_[3]\, + O => \fine_dec_cnt[5]_i_7_n_0\ + ); +\fine_dec_cnt[5]_i_8\: unisim.vcomponents.LUT3 + generic map( + INIT => X"45" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(3), + O => \fine_dec_cnt[5]_i_8_n_0\ + ); +\fine_dec_cnt[5]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E2FFFFFFFFFFFFFF" + ) + port map ( + I0 => \rd_data_edge_detect_r_reg_n_0_[0]\, + I1 => dqs_count_r(0), + I2 => \rd_data_edge_detect_r_reg_n_0_[1]\, + I3 => \wl_tap_count_r_reg_n_0_[3]\, + I4 => \wl_tap_count_r_reg_n_0_[4]\, + I5 => \wl_tap_count_r_reg_n_0_[5]\, + O => \fine_dec_cnt[5]_i_9_n_0\ + ); +\fine_dec_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_dec_cnt[5]_i_1_n_0\, + D => fine_dec_cnt(0), + Q => \fine_dec_cnt_reg_n_0_[0]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\fine_dec_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_dec_cnt[5]_i_1_n_0\, + D => fine_dec_cnt(1), + Q => \fine_dec_cnt_reg_n_0_[1]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\fine_dec_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_dec_cnt[5]_i_1_n_0\, + D => fine_dec_cnt(2), + Q => \fine_dec_cnt_reg_n_0_[2]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\fine_dec_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_dec_cnt[5]_i_1_n_0\, + D => fine_dec_cnt(3), + Q => \fine_dec_cnt_reg_n_0_[3]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\fine_dec_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_dec_cnt[5]_i_1_n_0\, + D => fine_dec_cnt(4), + Q => \fine_dec_cnt_reg_n_0_[4]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\fine_dec_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_dec_cnt[5]_i_1_n_0\, + D => fine_dec_cnt(5), + Q => \fine_dec_cnt_reg_n_0_[5]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\fine_inc[0][0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"888AAA8A00022202" + ) + port map ( + I0 => \fine_inc[1][0]_i_2_n_0\, + I1 => \wl_state_r__0\(1), + I2 => \fine_inc_reg[0]_3\(0), + I3 => \dqs_count_r_reg[0]_rep_n_0\, + I4 => \fine_inc_reg[1]_2\(0), + I5 => \gen_final_tap[0].final_val_reg_n_0_[0][0]\, + O => fine_inc(0) + ); +\fine_inc[0][1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][1]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[0].final_val_reg_n_0_[0][1]\, + O => fine_inc(1) + ); +\fine_inc[0][2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][2]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[0].final_val_reg_n_0_[0][2]\, + O => fine_inc(2) + ); +\fine_inc[0][3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][3]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[0].final_val_reg_n_0_[0][3]\, + O => fine_inc(3) + ); +\fine_inc[0][4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][4]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[0].final_val_reg_n_0_[0][4]\, + O => fine_inc(4) + ); +\fine_inc[0][5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A800A0000800000" + ) + port map ( + I0 => \fine_inc[1][5]_i_3_n_0\, + I1 => \fine_inc[0][5]_i_3_n_0\, + I2 => wr_level_done_r5, + I3 => \wl_state_r__0\(1), + I4 => \fine_inc[1][5]_i_5_n_0\, + I5 => wr_level_done_r4, + O => \fine_inc[0][5]_i_1_n_0\ + ); +\fine_inc[0][5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00E20000" + ) + port map ( + I0 => \fine_inc[1][5]_i_6_n_0\, + I1 => \wl_state_r__0\(1), + I2 => \gen_final_tap[0].final_val_reg_n_0_[0][5]\, + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(0), + O => \fine_inc[0][5]_i_2_n_0\ + ); +\fine_inc[0][5]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => dqs_count_r(1), + I1 => dqs_count_r(0), + O => \fine_inc[0][5]_i_3_n_0\ + ); +\fine_inc[1][0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"888AAA8A00022202" + ) + port map ( + I0 => \fine_inc[1][0]_i_2_n_0\, + I1 => \wl_state_r__0\(1), + I2 => \fine_inc_reg[0]_3\(0), + I3 => \dqs_count_r_reg[0]_rep_n_0\, + I4 => \fine_inc_reg[1]_2\(0), + I5 => \gen_final_tap[1].final_val_reg_n_0_[1][0]\, + O => \fine_inc[1][0]_i_1_n_0\ + ); +\fine_inc[1][0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => \wl_state_r__0\(4), + O => \fine_inc[1][0]_i_2_n_0\ + ); +\fine_inc[1][1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][1]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[1].final_val_reg_n_0_[1][1]\, + O => \fine_inc[1][1]_i_1_n_0\ + ); +\fine_inc[1][1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4540151040451015" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \fine_inc_reg[1]_2\(1), + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \fine_inc_reg[0]_3\(1), + I4 => \fine_inc_reg[1]_2\(0), + I5 => \fine_inc_reg[0]_3\(0), + O => \fine_inc[1][1]_i_2_n_0\ + ); +\fine_inc[1][2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][2]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[1].final_val_reg_n_0_[1][2]\, + O => \fine_inc[1][2]_i_1_n_0\ + ); +\fine_inc[1][2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45401015" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \fine_inc_reg[1]_2\(2), + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \fine_inc_reg[0]_3\(2), + I4 => \fine_inc[1][2]_i_3_n_0\, + O => \fine_inc[1][2]_i_2_n_0\ + ); +\fine_inc[1][2]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFACCFA" + ) + port map ( + I0 => \fine_inc_reg[0]_3\(0), + I1 => \fine_inc_reg[1]_2\(0), + I2 => \fine_inc_reg[0]_3\(1), + I3 => \dqs_count_r_reg[0]_rep_n_0\, + I4 => \fine_inc_reg[1]_2\(1), + O => \fine_inc[1][2]_i_3_n_0\ + ); +\fine_inc[1][3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][3]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[1].final_val_reg_n_0_[1][3]\, + O => \fine_inc[1][3]_i_1_n_0\ + ); +\fine_inc[1][3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45401015" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \fine_inc_reg[1]_2\(3), + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \fine_inc_reg[0]_3\(3), + I4 => \fine_inc[1][3]_i_3_n_0\, + O => \fine_inc[1][3]_i_2_n_0\ + ); +\fine_inc[1][3]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFCFAFAFFFC" + ) + port map ( + I0 => \fine_inc_reg[1]_2\(1), + I1 => \fine_inc_reg[0]_3\(1), + I2 => \fine_inc[1][3]_i_4_n_0\, + I3 => \fine_inc_reg[0]_3\(2), + I4 => \dqs_count_r_reg[0]_rep_n_0\, + I5 => \fine_inc_reg[1]_2\(2), + O => \fine_inc[1][3]_i_3_n_0\ + ); +\fine_inc[1][3]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \fine_inc_reg[1]_2\(0), + I1 => \dqs_count_r_reg[0]_rep_n_0\, + I2 => \fine_inc_reg[0]_3\(0), + O => \fine_inc[1][3]_i_4_n_0\ + ); +\fine_inc[1][4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"44404040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \fine_inc[1][4]_i_2_n_0\, + I3 => \wl_state_r__0\(1), + I4 => \gen_final_tap[1].final_val_reg_n_0_[1][4]\, + O => \fine_inc[1][4]_i_1_n_0\ + ); +\fine_inc[1][4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45401015" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \fine_inc_reg[1]_2\(4), + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \fine_inc_reg[0]_3\(4), + I4 => \fine_inc[1][4]_i_3_n_0\, + O => \fine_inc[1][4]_i_2_n_0\ + ); +\fine_inc[1][4]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFCFAFAFFFC" + ) + port map ( + I0 => \fine_inc_reg[1]_2\(2), + I1 => \fine_inc_reg[0]_3\(2), + I2 => \fine_inc[1][2]_i_3_n_0\, + I3 => \fine_inc_reg[0]_3\(3), + I4 => \dqs_count_r_reg[0]_rep_n_0\, + I5 => \fine_inc_reg[1]_2\(3), + O => \fine_inc[1][4]_i_3_n_0\ + ); +\fine_inc[1][5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0A800A0000800000" + ) + port map ( + I0 => \fine_inc[1][5]_i_3_n_0\, + I1 => \fine_inc[1][5]_i_4_n_0\, + I2 => wr_level_done_r5, + I3 => \wl_state_r__0\(1), + I4 => \fine_inc[1][5]_i_5_n_0\, + I5 => wr_level_done_r4, + O => \fine_inc[1][5]_i_1_n_0\ + ); +\fine_inc[1][5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00E20000" + ) + port map ( + I0 => \fine_inc[1][5]_i_6_n_0\, + I1 => \wl_state_r__0\(1), + I2 => \gen_final_tap[1].final_val_reg_n_0_[1][5]\, + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(0), + O => \fine_inc[1][5]_i_2_n_0\ + ); +\fine_inc[1][5]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4000" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(3), + O => \fine_inc[1][5]_i_3_n_0\ + ); +\fine_inc[1][5]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => dqs_count_r(0), + I1 => dqs_count_r(1), + O => \fine_inc[1][5]_i_4_n_0\ + ); +\fine_inc[1][5]_i_5\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAE" + ) + port map ( + I0 => \fine_inc[1][5]_i_7_n_0\, + I1 => \fine_inc_reg[0]_3\(5), + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \fine_inc_reg[1]_2\(5), + O => \fine_inc[1][5]_i_5_n_0\ + ); +\fine_inc[1][5]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A965" + ) + port map ( + I0 => \fine_inc[1][5]_i_7_n_0\, + I1 => \dqs_count_r_reg[0]_rep_n_0\, + I2 => \fine_inc_reg[0]_3\(5), + I3 => \fine_inc_reg[1]_2\(5), + O => \fine_inc[1][5]_i_6_n_0\ + ); +\fine_inc[1][5]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFCFAFAFFFC" + ) + port map ( + I0 => \fine_inc_reg[1]_2\(3), + I1 => \fine_inc_reg[0]_3\(3), + I2 => \fine_inc[1][3]_i_3_n_0\, + I3 => \fine_inc_reg[0]_3\(4), + I4 => \dqs_count_r_reg[0]_rep_n_0\, + I5 => \fine_inc_reg[1]_2\(4), + O => \fine_inc[1][5]_i_7_n_0\ + ); +\fine_inc_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[0][5]_i_1_n_0\, + D => fine_inc(0), + Q => \fine_inc_reg[0]_3\(0), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[0][5]_i_1_n_0\, + D => fine_inc(1), + Q => \fine_inc_reg[0]_3\(1), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[0][5]_i_1_n_0\, + D => fine_inc(2), + Q => \fine_inc_reg[0]_3\(2), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[0][5]_i_1_n_0\, + D => fine_inc(3), + Q => \fine_inc_reg[0]_3\(3), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[0][5]_i_1_n_0\, + D => fine_inc(4), + Q => \fine_inc_reg[0]_3\(4), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[0][5]_i_1_n_0\, + D => \fine_inc[0][5]_i_2_n_0\, + Q => \fine_inc_reg[0]_3\(5), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[1][5]_i_1_n_0\, + D => \fine_inc[1][0]_i_1_n_0\, + Q => \fine_inc_reg[1]_2\(0), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[1][5]_i_1_n_0\, + D => \fine_inc[1][1]_i_1_n_0\, + Q => \fine_inc_reg[1]_2\(1), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[1][5]_i_1_n_0\, + D => \fine_inc[1][2]_i_1_n_0\, + Q => \fine_inc_reg[1]_2\(2), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[1][5]_i_1_n_0\, + D => \fine_inc[1][3]_i_1_n_0\, + Q => \fine_inc_reg[1]_2\(3), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[1][5]_i_1_n_0\, + D => \fine_inc[1][4]_i_1_n_0\, + Q => \fine_inc_reg[1]_2\(4), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\fine_inc_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \fine_inc[1][5]_i_1_n_0\, + D => \fine_inc[1][5]_i_2_n_0\, + Q => \fine_inc_reg[1]_2\(5), + R => wl_edge_detect_valid_r_reg_0(0) + ); +flag_ck_negedge_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"2222222222222022" + ) + port map ( + I0 => \stable_cnt[3]_i_4_n_0\, + I1 => flag_ck_negedge_i_2_n_0, + I2 => \wl_state_r__0\(3), + I3 => flag_ck_negedge_i_3_n_0, + I4 => \wl_state_r__0\(4), + I5 => \wl_state_r__0\(2), + O => flag_ck_negedge_i_1_n_0 + ); +flag_ck_negedge_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAABBFB" + ) + port map ( + I0 => wr_level_done_r_reg_n_0, + I1 => flag_ck_negedge_reg_n_0, + I2 => \FSM_sequential_wl_state_r[3]_i_8_n_0\, + I3 => \stable_cnt_reg_n_0_[0]\, + I4 => flag_ck_negedge09_out, + O => flag_ck_negedge_i_2_n_0 + ); +flag_ck_negedge_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + O => flag_ck_negedge_i_3_n_0 + ); +flag_ck_negedge_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"4000FFFF40004000" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wrlvl_redo_corse_inc[2]_i_2_n_0\, + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(3), + I4 => flag_ck_negedge_i_5_n_0, + I5 => inhibit_edge_detect_r_i_6_n_0, + O => flag_ck_negedge09_out + ); +flag_ck_negedge_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => flag_ck_negedge_i_6_n_0, + I1 => \stable_cnt_reg_n_0_[0]\, + I2 => \stable_cnt_reg_n_0_[1]\, + I3 => \stable_cnt_reg_n_0_[2]\, + I4 => \stable_cnt_reg_n_0_[3]\, + I5 => flag_ck_negedge_i_7_n_0, + O => flag_ck_negedge_i_5_n_0 + ); +flag_ck_negedge_i_6: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFBFE" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(1), + O => flag_ck_negedge_i_6_n_0 + ); +flag_ck_negedge_i_7: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(4), + O => flag_ck_negedge_i_7_n_0 + ); +flag_ck_negedge_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => flag_ck_negedge_i_1_n_0, + Q => flag_ck_negedge_reg_n_0, + R => '0' + ); +flag_init_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA8AAAAAAAAAA" + ) + port map ( + I0 => flag_init, + I1 => \wl_state_r1_reg_n_0_[0]\, + I2 => \wl_state_r1_reg_n_0_[3]\, + I3 => \wl_state_r1_reg_n_0_[2]\, + I4 => \wl_state_r1_reg_n_0_[4]\, + I5 => flag_init_i_2_n_0, + O => flag_init_i_1_n_0 + ); +flag_init_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000008" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(3), + O => flag_init_i_2_n_0 + ); +flag_init_reg: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => flag_init_i_1_n_0, + Q => flag_init, + S => \dqs_count_r_reg[0]_0\ + ); +\gen_byte_sel_div2.byte_sel_cnt[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEE222E2" + ) + port map ( + I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\, + I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\, + I2 => \dqs_count_r_reg[0]_rep_n_0\, + I3 => \^wr_level_done_reg_0\, + I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1\, + I5 => RSTB, + O => \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ + ); +\gen_byte_sel_div2.byte_sel_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000EEE222E2" + ) + port map ( + I0 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\, + I1 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\, + I2 => dqs_count_r(1), + I3 => \^wr_level_done_reg_0\, + I4 => \gen_byte_sel_div2.byte_sel_cnt_reg[1]_2\, + I5 => RSTB, + O => \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ + ); +\gen_final_tap[0].final_val[0][5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => wr_level_done_r2, + I1 => wr_level_done_r3, + O => p_45_out + ); +\gen_final_tap[0].final_val_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[0]_4\(0), + Q => \gen_final_tap[0].final_val_reg_n_0_[0][0]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[0].final_val_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[0]_4\(1), + Q => \gen_final_tap[0].final_val_reg_n_0_[0][1]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[0].final_val_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[0]_4\(2), + Q => \gen_final_tap[0].final_val_reg_n_0_[0][2]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[0].final_val_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[0]_4\(3), + Q => \gen_final_tap[0].final_val_reg_n_0_[0][3]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[0].final_val_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[0]_4\(4), + Q => \gen_final_tap[0].final_val_reg_n_0_[0][4]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[0].final_val_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[0]_4\(5), + Q => \gen_final_tap[0].final_val_reg_n_0_[0][5]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[1].final_val_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[1]_5\(0), + Q => \gen_final_tap[1].final_val_reg_n_0_[1][0]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[1].final_val_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[1]_5\(1), + Q => \gen_final_tap[1].final_val_reg_n_0_[1][1]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[1].final_val_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[1]_5\(2), + Q => \gen_final_tap[1].final_val_reg_n_0_[1][2]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[1].final_val_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[1]_5\(3), + Q => \gen_final_tap[1].final_val_reg_n_0_[1][3]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[1].final_val_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[1]_5\(4), + Q => \gen_final_tap[1].final_val_reg_n_0_[1][4]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_final_tap[1].final_val_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => p_45_out, + D => \smallest_reg[1]_5\(5), + Q => \gen_final_tap[1].final_val_reg_n_0_[1][5]\, + R => \dqs_count_r_reg[0]_0\ + ); +\gen_rd[0].rd_data_rise_wl_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\(0), + I1 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\(1), + I2 => DIC(0), + I3 => DIC(1), + I4 => \gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\, + O => \p_0_in__0\ + ); +\gen_rd[0].rd_data_rise_wl_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEEFA" + ) + port map ( + I0 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\(0), + I1 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\(0), + I2 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\(0), + I3 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\, + I4 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\(1), + I5 => \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\(0), + O => \gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0\ + ); +\gen_rd[0].rd_data_rise_wl_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0\, + Q => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\, + R => '0' + ); +\gen_rd[1].rd_data_rise_wl_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\(0), + I1 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\(1), + I2 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\(0), + I3 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\(1), + I4 => \gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\, + O => \gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\ + ); +\gen_rd[1].rd_data_rise_wl_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEEFA" + ) + port map ( + I0 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\(0), + I1 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\(0), + I2 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\(0), + I3 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\, + I4 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\(1), + I5 => \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\(0), + O => \gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0\ + ); +\gen_rd[1].rd_data_rise_wl_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0\, + Q => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\, + R => '0' + ); +\incdec_wait_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => incdec_wait_cnt_reg(0), + O => \p_0_in__0__0\(0) + ); +\incdec_wait_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => incdec_wait_cnt_reg(1), + I1 => incdec_wait_cnt_reg(0), + O => \p_0_in__0__0\(1) + ); +\incdec_wait_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => incdec_wait_cnt_reg(2), + I1 => incdec_wait_cnt_reg(0), + I2 => incdec_wait_cnt_reg(1), + O => \p_0_in__0__0\(2) + ); +\incdec_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFBFFFFEFB" + ) + port map ( + I0 => \rd_data_edge_detect_r_reg[1]_0\, + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(1), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(2), + I5 => \wl_state_r__0\(3), + O => \incdec_wait_cnt[3]_i_1_n_0\ + ); +\incdec_wait_cnt[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => incdec_wait_cnt_reg(3), + I1 => incdec_wait_cnt_reg(1), + I2 => incdec_wait_cnt_reg(0), + I3 => incdec_wait_cnt_reg(2), + O => \p_0_in__0__0\(3) + ); +\incdec_wait_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(0), + Q => incdec_wait_cnt_reg(0), + R => \incdec_wait_cnt[3]_i_1_n_0\ + ); +\incdec_wait_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(1), + Q => incdec_wait_cnt_reg(1), + R => \incdec_wait_cnt[3]_i_1_n_0\ + ); +\incdec_wait_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(2), + Q => incdec_wait_cnt_reg(2), + R => \incdec_wait_cnt[3]_i_1_n_0\ + ); +\incdec_wait_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_in__0__0\(3), + Q => incdec_wait_cnt_reg(3), + R => \incdec_wait_cnt[3]_i_1_n_0\ + ); +inhibit_edge_detect_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"007FFFFF007F0000" + ) + port map ( + I0 => inhibit_edge_detect_r_i_2_n_0, + I1 => \wl_state_r__0\(3), + I2 => inhibit_edge_detect_r_i_3_n_0, + I3 => inhibit_edge_detect_r_i_4_n_0, + I4 => inhibit_edge_detect_r_i_5_n_0, + I5 => inhibit_edge_detect_r_reg_n_0, + O => inhibit_edge_detect_r_i_1_n_0 + ); +inhibit_edge_detect_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(2), + O => inhibit_edge_detect_r_i_2_n_0 + ); +inhibit_edge_detect_r_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \fine_dec_cnt_reg_n_0_[5]\, + I1 => \fine_dec_cnt_reg_n_0_[3]\, + I2 => \fine_dec_cnt_reg_n_0_[1]\, + I3 => \fine_dec_cnt_reg_n_0_[0]\, + I4 => \fine_dec_cnt_reg_n_0_[2]\, + I5 => \fine_dec_cnt_reg_n_0_[4]\, + O => inhibit_edge_detect_r_i_3_n_0 + ); +inhibit_edge_detect_r_i_4: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000001D" + ) + port map ( + I0 => inhibit_edge_detect_r_i_6_n_0, + I1 => \wl_state_r__0\(1), + I2 => wrlvl_byte_redo, + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(2), + O => inhibit_edge_detect_r_i_4_n_0 + ); +inhibit_edge_detect_r_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFF8000" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[3]_i_8_n_0\, + I1 => inhibit_edge_detect_r_i_7_n_0, + I2 => wl_sm_start, + I3 => \fine_dec_cnt[5]_i_4_n_0\, + I4 => inhibit_edge_detect_r_i_8_n_0, + I5 => inhibit_edge_detect_r_i_9_n_0, + O => inhibit_edge_detect_r_i_5_n_0 + ); +inhibit_edge_detect_r_i_6: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rd_data_previous_r_reg_n_0_[1]\, + I1 => dqs_count_r(0), + I2 => \rd_data_previous_r_reg_n_0_[0]\, + O => inhibit_edge_detect_r_i_6_n_0 + ); +inhibit_edge_detect_r_i_7: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(1), + O => inhibit_edge_detect_r_i_7_n_0 + ); +inhibit_edge_detect_r_i_8: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002400" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(0), + O => inhibit_edge_detect_r_i_8_n_0 + ); +inhibit_edge_detect_r_i_9: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000555500300000" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[0]_i_7_n_0\, + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(3), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(4), + I5 => \wl_state_r__0\(1), + O => inhibit_edge_detect_r_i_9_n_0 + ); +inhibit_edge_detect_r_reg: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => inhibit_edge_detect_r_i_1_n_0, + Q => inhibit_edge_detect_r_reg_n_0, + S => \dqs_count_r_reg[0]_0\ + ); +phaser_out_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => phaser_out, + I1 => po_stg2_cincdec(2), + I2 => phaser_out_0, + I3 => phaser_out_1, + I4 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg\ + ); +\phaser_out_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => phaser_out, + I1 => phaser_out_0, + I2 => po_stg2_cincdec(2), + I3 => phaser_out_1, + I4 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg_1\ + ); +\phaser_out_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => po_stg2_cincdec(2), + I1 => phaser_out_0, + I2 => phaser_out_1, + I3 => phaser_out, + I4 => calib_zero_inputs, + O => dqs_wl_po_stg2_c_incdec_reg_0 + ); +\phaser_out_i_1__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => phaser_out_1, + I1 => po_stg2_cincdec(2), + I2 => phaser_out_0, + I3 => phaser_out, + I4 => calib_zero_inputs, + O => \calib_sel_reg[1]\ + ); +\phaser_out_i_2__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => phaser_out_1, + I1 => po_enstg2_f(0), + I2 => phaser_out_0, + I3 => phaser_out, + I4 => calib_zero_inputs, + O => \calib_sel_reg[1]_0\ + ); +\phaser_out_i_2__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => po_enstg2_f(0), + I1 => phaser_out_0, + I2 => phaser_out_1, + I3 => phaser_out, + I4 => calib_zero_inputs, + O => \calib_sel_reg[0]\ + ); +phaser_out_i_3: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => phaser_out, + I1 => po_enstg2_f(0), + I2 => phaser_out_0, + I3 => phaser_out_1, + I4 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg_0\ + ); +\phaser_out_i_3__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000040" + ) + port map ( + I0 => phaser_out, + I1 => phaser_out_0, + I2 => po_enstg2_f(0), + I3 => phaser_out_1, + I4 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg_2\ + ); +\phaser_out_i_4__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000004440" + ) + port map ( + I0 => phaser_out, + I1 => phaser_out_0, + I2 => \^dqs_po_stg2_f_incdec\, + I3 => ck_po_stg2_f_indec, + I4 => phaser_out_1, + I5 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg_3\ + ); +phy_ctl_ready_r4_reg_srl4: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '1', + A2 => '0', + A3 => '0', + CE => '1', + CLK => CLK, + D => Q(0), + Q => phy_ctl_ready_r4_reg_srl4_n_0 + ); +phy_ctl_ready_r5_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_ready_r4_reg_srl4_n_0, + Q => phy_ctl_ready_r5, + R => '0' + ); +phy_ctl_ready_r6_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_ready_r5, + Q => phy_ctl_ready_r6_reg_n_0, + R => '0' + ); +po_cnt_dec_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \po_rdval_cnt[8]_i_3_n_0\, + I1 => po_cnt_dec_i_2_n_0, + O => po_cnt_dec_i_1_n_0 + ); +po_cnt_dec_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFEFFF" + ) + port map ( + I0 => wait_cnt_reg(3), + I1 => wait_cnt_reg(2), + I2 => phy_ctl_ready_r6_reg_n_0, + I3 => wait_cnt_reg(0), + I4 => \rd_data_edge_detect_r_reg[1]_0\, + I5 => wait_cnt_reg(1), + O => po_cnt_dec_i_2_n_0 + ); +po_cnt_dec_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => po_cnt_dec_i_1_n_0, + Q => \^po_cnt_dec_reg_0\, + R => '0' + ); +po_dec_done_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFAE" + ) + port map ( + I0 => po_dec_done_i_2_n_0, + I1 => phy_ctl_ready_r6_reg_n_0, + I2 => \po_rdval_cnt[8]_i_3_n_0\, + I3 => po_dec_done, + O => po_dec_done_i_1_n_0 + ); +po_dec_done_i_2: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000080" + ) + port map ( + I0 => \po_rdval_cnt[7]_i_2_n_0\, + I1 => \^po_cnt_dec_reg_0\, + I2 => po_rdval_cnt(0), + I3 => po_rdval_cnt(6), + I4 => po_rdval_cnt(5), + O => po_dec_done_i_2_n_0 + ); +po_dec_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => po_dec_done_i_1_n_0, + Q => po_dec_done, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\po_rdval_cnt[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0808FB08" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(0), + I1 => phy_ctl_ready_r5, + I2 => phy_ctl_ready_r6_reg_n_0, + I3 => \po_rdval_cnt[8]_i_3_n_0\, + I4 => po_rdval_cnt(0), + O => \po_rdval_cnt[0]_i_1_n_0\ + ); +\po_rdval_cnt[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FB0808080808FB08" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(1), + I1 => phy_ctl_ready_r5, + I2 => phy_ctl_ready_r6_reg_n_0, + I3 => \po_rdval_cnt[8]_i_3_n_0\, + I4 => po_rdval_cnt(1), + I5 => po_rdval_cnt(0), + O => \po_rdval_cnt[1]_i_1_n_0\ + ); +\po_rdval_cnt[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8B8B888888888B8" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(2), + I1 => \po_rdval_cnt[6]_i_3_n_0\, + I2 => \po_rdval_cnt[8]_i_3_n_0\, + I3 => po_rdval_cnt(0), + I4 => po_rdval_cnt(1), + I5 => po_rdval_cnt(2), + O => \po_rdval_cnt[2]_i_1_n_0\ + ); +\po_rdval_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"B8B8B888888888B8" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(3), + I1 => \po_rdval_cnt[6]_i_3_n_0\, + I2 => \po_rdval_cnt[8]_i_3_n_0\, + I3 => po_rdval_cnt(2), + I4 => \po_rdval_cnt[3]_i_2_n_0\, + I5 => po_rdval_cnt(3), + O => \po_rdval_cnt[3]_i_1_n_0\ + ); +\po_rdval_cnt[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => po_rdval_cnt(0), + I1 => po_rdval_cnt(1), + O => \po_rdval_cnt[3]_i_2_n_0\ + ); +\po_rdval_cnt[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FB0808080808FB08" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(4), + I1 => phy_ctl_ready_r5, + I2 => phy_ctl_ready_r6_reg_n_0, + I3 => \po_rdval_cnt[8]_i_3_n_0\, + I4 => \po_rdval_cnt[4]_i_2_n_0\, + I5 => po_rdval_cnt(4), + O => \po_rdval_cnt[4]_i_1_n_0\ + ); +\po_rdval_cnt[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => po_rdval_cnt(2), + I1 => po_rdval_cnt(3), + I2 => po_rdval_cnt(1), + I3 => po_rdval_cnt(0), + O => \po_rdval_cnt[4]_i_2_n_0\ + ); +\po_rdval_cnt[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0808FB08FB080808" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(5), + I1 => phy_ctl_ready_r5, + I2 => phy_ctl_ready_r6_reg_n_0, + I3 => \po_rdval_cnt[8]_i_3_n_0\, + I4 => \po_rdval_cnt[6]_i_2_n_0\, + I5 => po_rdval_cnt(5), + O => \po_rdval_cnt[5]_i_1_n_0\ + ); +\po_rdval_cnt[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFA6000000A600" + ) + port map ( + I0 => po_rdval_cnt(6), + I1 => \po_rdval_cnt[6]_i_2_n_0\, + I2 => po_rdval_cnt(5), + I3 => \po_rdval_cnt[8]_i_3_n_0\, + I4 => \po_rdval_cnt[6]_i_3_n_0\, + I5 => \po_rdval_cnt_reg[8]_0\(6), + O => \po_rdval_cnt[6]_i_1_n_0\ + ); +\po_rdval_cnt[6]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000001" + ) + port map ( + I0 => po_rdval_cnt(4), + I1 => po_rdval_cnt(0), + I2 => po_rdval_cnt(1), + I3 => po_rdval_cnt(3), + I4 => po_rdval_cnt(2), + O => \po_rdval_cnt[6]_i_2_n_0\ + ); +\po_rdval_cnt[6]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => phy_ctl_ready_r5, + I1 => phy_ctl_ready_r6_reg_n_0, + O => \po_rdval_cnt[6]_i_3_n_0\ + ); +\po_rdval_cnt[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFB0808080808FB" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(7), + I1 => phy_ctl_ready_r5, + I2 => phy_ctl_ready_r6_reg_n_0, + I3 => \po_rdval_cnt[7]_i_2_n_0\, + I4 => \po_rdval_cnt[7]_i_3_n_0\, + I5 => po_rdval_cnt(7), + O => \po_rdval_cnt[7]_i_1_n_0\ + ); +\po_rdval_cnt[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => po_rdval_cnt(3), + I1 => po_rdval_cnt(2), + I2 => po_rdval_cnt(4), + I3 => po_rdval_cnt(7), + I4 => po_rdval_cnt(8), + I5 => po_rdval_cnt(1), + O => \po_rdval_cnt[7]_i_2_n_0\ + ); +\po_rdval_cnt[7]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EF" + ) + port map ( + I0 => po_rdval_cnt(5), + I1 => po_rdval_cnt(6), + I2 => \po_rdval_cnt[6]_i_2_n_0\, + O => \po_rdval_cnt[7]_i_3_n_0\ + ); +\po_rdval_cnt[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBFB" + ) + port map ( + I0 => \^po_cnt_dec_reg_0\, + I1 => \po_rdval_cnt[8]_i_3_n_0\, + I2 => phy_ctl_ready_r5, + I3 => phy_ctl_ready_r6_reg_n_0, + O => \po_rdval_cnt[8]_i_1_n_0\ + ); +\po_rdval_cnt[8]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0808FB08" + ) + port map ( + I0 => \po_rdval_cnt_reg[8]_0\(8), + I1 => phy_ctl_ready_r5, + I2 => phy_ctl_ready_r6_reg_n_0, + I3 => po_rdval_cnt(8), + I4 => \po_rdval_cnt[8]_i_4_n_0\, + O => \po_rdval_cnt[8]_i_2_n_0\ + ); +\po_rdval_cnt[8]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFD" + ) + port map ( + I0 => \po_rdval_cnt[6]_i_2_n_0\, + I1 => po_rdval_cnt(7), + I2 => po_rdval_cnt(8), + I3 => po_rdval_cnt(6), + I4 => po_rdval_cnt(5), + O => \po_rdval_cnt[8]_i_3_n_0\ + ); +\po_rdval_cnt[8]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00010000" + ) + port map ( + I0 => po_rdval_cnt(7), + I1 => \po_rdval_cnt[7]_i_2_n_0\, + I2 => po_rdval_cnt(5), + I3 => po_rdval_cnt(6), + I4 => \po_rdval_cnt[6]_i_2_n_0\, + O => \po_rdval_cnt[8]_i_4_n_0\ + ); +\po_rdval_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[0]_i_1_n_0\, + Q => po_rdval_cnt(0), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[1]_i_1_n_0\, + Q => po_rdval_cnt(1), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[2]_i_1_n_0\, + Q => po_rdval_cnt(2), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[3]_i_1_n_0\, + Q => po_rdval_cnt(3), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[4]_i_1_n_0\, + Q => po_rdval_cnt(4), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[5]_i_1_n_0\, + Q => po_rdval_cnt(5), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[6]_i_1_n_0\, + Q => po_rdval_cnt(6), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[7]_i_1_n_0\, + Q => po_rdval_cnt(7), + R => \dqs_count_r_reg[0]_0\ + ); +\po_rdval_cnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \po_rdval_cnt[8]_i_1_n_0\, + D => \po_rdval_cnt[8]_i_2_n_0\, + Q => po_rdval_cnt(8), + R => \dqs_count_r_reg[0]_0\ + ); +\rank_cnt_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"38" + ) + port map ( + I0 => \rank_cnt_r_reg_n_0_[1]\, + I1 => rank_cnt_r, + I2 => \rank_cnt_r_reg_n_0_[0]\, + O => \rank_cnt_r[0]_i_1_n_0\ + ); +\rank_cnt_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \rank_cnt_r_reg_n_0_[0]\, + I1 => rank_cnt_r, + I2 => \rank_cnt_r_reg_n_0_[1]\, + O => \rank_cnt_r[1]_i_1_n_0\ + ); +\rank_cnt_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000001000" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(3), + I5 => p_0_in, + O => rank_cnt_r + ); +\rank_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rank_cnt_r[0]_i_1_n_0\, + Q => \rank_cnt_r_reg_n_0_[0]\, + R => \dqs_count_r_reg[0]_0\ + ); +\rank_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rank_cnt_r[1]_i_1_n_0\, + Q => \rank_cnt_r_reg_n_0_[1]\, + R => \dqs_count_r_reg[0]_0\ + ); +\rd_data_edge_detect_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => \rd_data_edge_detect_r[0]_i_2_n_0\, + I1 => inhibit_edge_detect_r_reg_n_0, + I2 => \rd_data_edge_detect_r_reg[1]_0\, + I3 => flag_ck_negedge_reg_n_0, + I4 => flag_init, + I5 => \rd_data_edge_detect_r[1]_i_3_n_0\, + O => \rd_data_edge_detect_r[0]_i_1_n_0\ + ); +\rd_data_edge_detect_r[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00202000002020" + ) + port map ( + I0 => \rd_data_edge_detect_r[1]_i_4_n_0\, + I1 => \rd_data_previous_r_reg_n_0_[0]\, + I2 => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\, + I3 => \rd_data_edge_detect_r[1]_i_5_n_0\, + I4 => \rd_data_edge_detect_r[1]_i_6_n_0\, + I5 => \rd_data_edge_detect_r_reg_n_0_[0]\, + O => \rd_data_edge_detect_r[0]_i_2_n_0\ + ); +\rd_data_edge_detect_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000002" + ) + port map ( + I0 => \rd_data_edge_detect_r[1]_i_2_n_0\, + I1 => inhibit_edge_detect_r_reg_n_0, + I2 => \rd_data_edge_detect_r_reg[1]_0\, + I3 => flag_ck_negedge_reg_n_0, + I4 => flag_init, + I5 => \rd_data_edge_detect_r[1]_i_3_n_0\, + O => \rd_data_edge_detect_r[1]_i_1_n_0\ + ); +\rd_data_edge_detect_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00202000002020" + ) + port map ( + I0 => \rd_data_edge_detect_r[1]_i_4_n_0\, + I1 => \rd_data_previous_r_reg_n_0_[1]\, + I2 => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\, + I3 => \rd_data_edge_detect_r[1]_i_5_n_0\, + I4 => \rd_data_edge_detect_r[1]_i_6_n_0\, + I5 => \rd_data_edge_detect_r_reg_n_0_[1]\, + O => \rd_data_edge_detect_r[1]_i_2_n_0\ + ); +\rd_data_edge_detect_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[0]\, + I1 => \wl_tap_count_r_reg_n_0_[1]\, + I2 => \wl_tap_count_r_reg_n_0_[2]\, + I3 => \wl_tap_count_r_reg_n_0_[3]\, + I4 => \wl_tap_count_r_reg_n_0_[4]\, + I5 => \wl_tap_count_r_reg_n_0_[5]\, + O => \rd_data_edge_detect_r[1]_i_3_n_0\ + ); +\rd_data_edge_detect_r[1]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF1D1D1D1D1D1D1D" + ) + port map ( + I0 => \rd_data_previous_r_reg_n_0_[0]\, + I1 => dqs_count_r(0), + I2 => \rd_data_previous_r_reg_n_0_[1]\, + I3 => \stable_cnt_reg_n_0_[1]\, + I4 => \stable_cnt_reg_n_0_[3]\, + I5 => \stable_cnt_reg_n_0_[2]\, + O => \rd_data_edge_detect_r[1]_i_4_n_0\ + ); +\rd_data_edge_detect_r[1]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FDFDCAFA" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(3), + O => \rd_data_edge_detect_r[1]_i_5_n_0\ + ); +\rd_data_edge_detect_r[1]_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \rd_data_edge_detect_r_reg_n_0_[1]\, + I1 => dqs_count_r(0), + I2 => \rd_data_edge_detect_r_reg_n_0_[0]\, + O => \rd_data_edge_detect_r[1]_i_6_n_0\ + ); +\rd_data_edge_detect_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_data_edge_detect_r[0]_i_1_n_0\, + Q => \rd_data_edge_detect_r_reg_n_0_[0]\, + R => '0' + ); +\rd_data_edge_detect_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_data_edge_detect_r[1]_i_1_n_0\, + Q => \rd_data_edge_detect_r_reg_n_0_[1]\, + R => '0' + ); +\rd_data_previous_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\, + I1 => rd_data_previous_r0, + I2 => \rd_data_previous_r_reg_n_0_[0]\, + O => \rd_data_previous_r[0]_i_1_n_0\ + ); +\rd_data_previous_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\, + I1 => rd_data_previous_r0, + I2 => \rd_data_previous_r_reg_n_0_[1]\, + O => \rd_data_previous_r[1]_i_1_n_0\ + ); +\rd_data_previous_r[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAABABABBEAEBBAB" + ) + port map ( + I0 => \stable_cnt[3]_i_6_n_0\, + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(1), + I5 => \wl_state_r__0\(4), + O => rd_data_previous_r0 + ); +\rd_data_previous_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_data_previous_r[0]_i_1_n_0\, + Q => \rd_data_previous_r_reg_n_0_[0]\, + R => '0' + ); +\rd_data_previous_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_data_previous_r[1]_i_1_n_0\, + Q => \rd_data_previous_r_reg_n_0_[1]\, + R => '0' + ); +\single_rank.done_dqs_dec_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000BA" + ) + port map ( + I0 => \^done_dqs_tap_inc\, + I1 => wr_level_done_r4, + I2 => wr_level_done_r3, + I3 => done_dqs_dec237_out, + I4 => \single_rank.done_dqs_dec_reg_0\, + O => \single_rank.done_dqs_dec_i_1_n_0\ + ); +\single_rank.done_dqs_dec_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \single_rank.done_dqs_dec_i_1_n_0\, + Q => \^done_dqs_tap_inc\, + R => '0' + ); +\smallest[0][5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(3), + I4 => dqs_count_r(0), + I5 => dqs_count_r(1), + O => \smallest[0][5]_i_1_n_0\ + ); +\smallest[1][5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000001000000000" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(3), + I4 => dqs_count_r(1), + I5 => dqs_count_r(0), + O => \smallest[1][5]_i_1_n_0\ + ); +\smallest_reg[0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[0][5]_i_1_n_0\, + D => largest(0), + Q => \smallest_reg[0]_4\(0), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[0][5]_i_1_n_0\, + D => largest(1), + Q => \smallest_reg[0]_4\(1), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[0][5]_i_1_n_0\, + D => largest(2), + Q => \smallest_reg[0]_4\(2), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[0][5]_i_1_n_0\, + D => largest(3), + Q => \smallest_reg[0]_4\(3), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[0][5]_i_1_n_0\, + D => largest(4), + Q => \smallest_reg[0]_4\(4), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[0][5]_i_1_n_0\, + D => largest(5), + Q => \smallest_reg[0]_4\(5), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[1][5]_i_1_n_0\, + D => \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\, + Q => \smallest_reg[1]_5\(0), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[1][5]_i_1_n_0\, + D => \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\, + Q => \smallest_reg[1]_5\(1), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[1][5]_i_1_n_0\, + D => \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\, + Q => \smallest_reg[1]_5\(2), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[1][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[1][5]_i_1_n_0\, + D => \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\, + Q => \smallest_reg[1]_5\(3), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[1][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[1][5]_i_1_n_0\, + D => \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\, + Q => \smallest_reg[1]_5\(4), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\smallest_reg[1][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \smallest[1][5]_i_1_n_0\, + D => \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\, + Q => \smallest_reg[1]_5\(5), + R => wl_edge_detect_valid_r_reg_0(0) + ); +\stable_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \stable_cnt_reg_n_0_[0]\, + O => \p_0_in__1\(0) + ); +\stable_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \stable_cnt_reg_n_0_[1]\, + I1 => \stable_cnt_reg_n_0_[0]\, + O => \p_0_in__1\(1) + ); +\stable_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => \stable_cnt_reg_n_0_[2]\, + I1 => \stable_cnt_reg_n_0_[0]\, + I2 => \stable_cnt_reg_n_0_[1]\, + O => \p_0_in__1\(2) + ); +\stable_cnt[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DDDDDDDDDDDDDDDF" + ) + port map ( + I0 => \stable_cnt[3]_i_4_n_0\, + I1 => \stable_cnt[3]_i_5_n_0\, + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(0), + I5 => \wl_state_r__0\(1), + O => stable_cnt0 + ); +\stable_cnt[3]_i_10\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + O => \stable_cnt[3]_i_10_n_0\ + ); +\stable_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00002AAA" + ) + port map ( + I0 => \stable_cnt[3]_i_6_n_0\, + I1 => \stable_cnt_reg_n_0_[1]\, + I2 => \stable_cnt_reg_n_0_[3]\, + I3 => \stable_cnt_reg_n_0_[2]\, + I4 => \rd_data_edge_detect_r[1]_i_3_n_0\, + O => stable_cnt + ); +\stable_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \stable_cnt_reg_n_0_[3]\, + I1 => \stable_cnt_reg_n_0_[1]\, + I2 => \stable_cnt_reg_n_0_[0]\, + I3 => \stable_cnt_reg_n_0_[2]\, + O => \p_0_in__1\(3) + ); +\stable_cnt[3]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000777" + ) + port map ( + I0 => \stable_cnt[3]_i_7_n_0\, + I1 => \wl_state_r1_reg_n_0_[0]\, + I2 => \stable_cnt[3]_i_8_n_0\, + I3 => \wl_state_r__0\(4), + I4 => \rd_data_edge_detect_r_reg[1]_0\, + O => \stable_cnt[3]_i_4_n_0\ + ); +\stable_cnt[3]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"335ACC5A" + ) + port map ( + I0 => \rd_data_previous_r_reg_n_0_[0]\, + I1 => \rd_data_previous_r_reg_n_0_[1]\, + I2 => \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0]\, + I3 => dqs_count_r(0), + I4 => \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1]\, + O => \stable_cnt[3]_i_5_n_0\ + ); +\stable_cnt[3]_i_6\: unisim.vcomponents.LUT6 + generic map( + INIT => X"44F4444444444444" + ) + port map ( + I0 => \stable_cnt[3]_i_9_n_0\, + I1 => \fine_dec_cnt[5]_i_4_n_0\, + I2 => \corse_inc[1][2]_i_3_n_0\, + I3 => \wl_state_r1_reg_n_0_[0]\, + I4 => \stable_cnt[3]_i_10_n_0\, + I5 => \stable_cnt[3]_i_7_n_0\, + O => \stable_cnt[3]_i_6_n_0\ + ); +\stable_cnt[3]_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0010" + ) + port map ( + I0 => \wl_state_r1_reg_n_0_[1]\, + I1 => \wl_state_r1_reg_n_0_[3]\, + I2 => \wl_state_r1_reg_n_0_[2]\, + I3 => \wl_state_r1_reg_n_0_[4]\, + O => \stable_cnt[3]_i_7_n_0\ + ); +\stable_cnt[3]_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(1), + O => \stable_cnt[3]_i_8_n_0\ + ); +\stable_cnt[3]_i_9\: unisim.vcomponents.LUT3 + generic map( + INIT => X"7F" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => wl_edge_detect_valid_r_reg_n_0, + I2 => \wl_state_r__0\(4), + O => \stable_cnt[3]_i_9_n_0\ + ); +\stable_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_cnt, + D => \p_0_in__1\(0), + Q => \stable_cnt_reg_n_0_[0]\, + R => stable_cnt0 + ); +\stable_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_cnt, + D => \p_0_in__1\(1), + Q => \stable_cnt_reg_n_0_[1]\, + R => stable_cnt0 + ); +\stable_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_cnt, + D => \p_0_in__1\(2), + Q => \stable_cnt_reg_n_0_[2]\, + R => stable_cnt0 + ); +\stable_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => stable_cnt, + D => \p_0_in__1\(3), + Q => \stable_cnt_reg_n_0_[3]\, + R => stable_cnt0 + ); +\wait_cnt[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => wait_cnt_reg(0), + O => \wait_cnt0__0\(0) + ); +\wait_cnt[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => wait_cnt_reg(1), + I1 => wait_cnt_reg(0), + O => \wait_cnt[1]_i_1_n_0\ + ); +\wait_cnt[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => wait_cnt_reg(2), + I1 => wait_cnt_reg(0), + I2 => wait_cnt_reg(1), + O => \wait_cnt0__0\(2) + ); +\wait_cnt[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAA8" + ) + port map ( + I0 => phy_ctl_ready_r6_reg_n_0, + I1 => wait_cnt_reg(3), + I2 => wait_cnt_reg(0), + I3 => wait_cnt_reg(1), + I4 => wait_cnt_reg(2), + O => wait_cnt0 + ); +\wait_cnt[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => wait_cnt_reg(3), + I1 => wait_cnt_reg(2), + I2 => wait_cnt_reg(1), + I3 => wait_cnt_reg(0), + O => \wait_cnt0__0\(3) + ); +\wait_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt0, + D => \wait_cnt0__0\(0), + Q => wait_cnt_reg(0), + R => SS(0) + ); +\wait_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt0, + D => \wait_cnt[1]_i_1_n_0\, + Q => wait_cnt_reg(1), + R => SS(0) + ); +\wait_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wait_cnt0, + D => \wait_cnt0__0\(2), + Q => wait_cnt_reg(2), + R => SS(0) + ); +\wait_cnt_reg[3]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => wait_cnt0, + D => \wait_cnt0__0\(3), + Q => wait_cnt_reg(3), + S => SS(0) + ); +\wl_corse_cnt[0][0][0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \corse_cnt_reg_n_0_[1][0]\, + I1 => \dqs_count_r_reg[0]_rep_n_0\, + I2 => \corse_cnt_reg_n_0_[0][0]\, + O => \wl_corse_cnt[0][0][0]_i_1_n_0\ + ); +\wl_corse_cnt[0][0][1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \corse_cnt_reg_n_0_[1][1]\, + I1 => \dqs_count_r_reg[0]_rep_n_0\, + I2 => \corse_cnt_reg_n_0_[0][1]\, + O => \wl_corse_cnt[0][0][1]_i_1_n_0\ + ); +\wl_corse_cnt[0][0][2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \corse_cnt_reg_n_0_[1][2]\, + I1 => \dqs_count_r_reg[0]_rep_n_0\, + I2 => \corse_cnt_reg_n_0_[0][2]\, + O => \wl_corse_cnt[0][0][2]_i_1_n_0\ + ); +\wl_corse_cnt_reg[0][0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_corse_cnt[0][0][0]_i_1_n_0\, + Q => \wl_corse_cnt_reg[0][0]_8\(0), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_corse_cnt_reg[0][0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_corse_cnt[0][0][1]_i_1_n_0\, + Q => \wl_corse_cnt_reg[0][0]_8\(1), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_corse_cnt_reg[0][0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_corse_cnt[0][0][2]_i_1_n_0\, + Q => \wl_corse_cnt_reg[0][0]_8\(2), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_corse_cnt_reg[0][1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_corse_cnt[0][0][0]_i_1_n_0\, + Q => \wl_corse_cnt_reg[0][1]_9\(0), + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_corse_cnt_reg[0][1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_corse_cnt[0][0][1]_i_1_n_0\, + Q => \wl_corse_cnt_reg[0][1]_9\(1), + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_corse_cnt_reg[0][1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_corse_cnt[0][0][2]_i_1_n_0\, + Q => \wl_corse_cnt_reg[0][1]_9\(2), + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_dqs_tap_count_r[0][0][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\, + I1 => dqs_count_r(0), + I2 => dqs_count_r(1), + O => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\ + ); +\wl_dqs_tap_count_r[0][0][5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000800080028" + ) + port map ( + I0 => \wl_dqs_tap_count_r[0][0][5]_i_3_n_0\, + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(3), + I4 => \wl_state_r__0\(1), + I5 => \wl_state_r__0\(4), + O => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\ + ); +\wl_dqs_tap_count_r[0][0][5]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \rank_cnt_r_reg_n_0_[1]\, + I1 => \rank_cnt_r_reg_n_0_[0]\, + O => \wl_dqs_tap_count_r[0][0][5]_i_3_n_0\ + ); +\wl_dqs_tap_count_r[0][1][5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"20" + ) + port map ( + I0 => \wl_dqs_tap_count_r[0][0][5]_i_2_n_0\, + I1 => dqs_count_r(1), + I2 => dqs_count_r(0), + O => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\ + ); +\wl_dqs_tap_count_r_reg[0][0][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[0]\, + Q => largest(0), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_dqs_tap_count_r_reg[0][0][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[1]\, + Q => largest(1), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_dqs_tap_count_r_reg[0][0][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[2]\, + Q => largest(2), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_dqs_tap_count_r_reg[0][0][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[3]\, + Q => largest(3), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_dqs_tap_count_r_reg[0][0][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[4]\, + Q => largest(4), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_dqs_tap_count_r_reg[0][0][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][0][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[5]\, + Q => largest(5), + R => \dqs_count_r_reg[0]_0\ + ); +\wl_dqs_tap_count_r_reg[0][1][0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[0]\, + Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][0]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_dqs_tap_count_r_reg[0][1][1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[1]\, + Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][1]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_dqs_tap_count_r_reg[0][1][2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[2]\, + Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][2]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_dqs_tap_count_r_reg[0][1][3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[3]\, + Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][3]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_dqs_tap_count_r_reg[0][1][4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[4]\, + Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][4]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_dqs_tap_count_r_reg[0][1][5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_dqs_tap_count_r[0][1][5]_i_1_n_0\, + D => \wl_tap_count_r_reg_n_0_[5]\, + Q => \wl_dqs_tap_count_r_reg_n_0_[0][1][5]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +wl_edge_detect_valid_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF00BD00FC80FE00" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(0), + I2 => \wl_state_r__0\(3), + I3 => wl_edge_detect_valid_r_reg_n_0, + I4 => \wl_state_r__0\(1), + I5 => \wl_state_r__0\(2), + O => wl_edge_detect_valid_r_i_1_n_0 + ); +wl_edge_detect_valid_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wl_edge_detect_valid_r_i_1_n_0, + Q => wl_edge_detect_valid_r_reg_n_0, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_state_r1[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"F05A55B6" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(0), + O => \wl_state_r1[0]_i_1_n_0\ + ); +\wl_state_r1[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"50557F55" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(0), + I4 => \wl_state_r__0\(3), + O => \wl_state_r1[1]_i_1_n_0\ + ); +\wl_state_r1[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0E4EC099" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(4), + I2 => \wl_state_r__0\(1), + I3 => \wl_state_r__0\(2), + I4 => \wl_state_r__0\(0), + O => \wl_state_r1[2]_i_1_n_0\ + ); +\wl_state_r1[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"E91103B1" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(0), + O => \wl_state_r1[3]_i_1_n_0\ + ); +\wl_state_r1[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FCD14998" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(0), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(2), + O => \wl_state_r1[4]_i_1_n_0\ + ); +\wl_state_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_state_r1[0]_i_1_n_0\, + Q => \wl_state_r1_reg_n_0_[0]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_state_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_state_r1[1]_i_1_n_0\, + Q => \wl_state_r1_reg_n_0_[1]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_state_r1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_state_r1[2]_i_1_n_0\, + Q => \wl_state_r1_reg_n_0_[2]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_state_r1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_state_r1[3]_i_1_n_0\, + Q => \wl_state_r1_reg_n_0_[3]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_state_r1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wl_state_r1[4]_i_1_n_0\, + Q => \wl_state_r1_reg_n_0_[4]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wl_tap_count_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"88888888888A8A8A" + ) + port map ( + I0 => \wl_tap_count_r[5]_i_4_n_0\, + I1 => \wl_tap_count_r[0]_i_2_n_0\, + I2 => \wl_tap_count_r_reg_n_0_[0]\, + I3 => \wl_state_r__0\(0), + I4 => wr_level_done_r5, + I5 => \wl_state_r__0\(1), + O => wl_tap_count_r(0) + ); +\wl_tap_count_r[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8C80" + ) + port map ( + I0 => \smallest_reg[1]_5\(0), + I1 => \wl_state_r__0\(1), + I2 => \dqs_count_r_reg[1]_0\(0), + I3 => \smallest_reg[0]_4\(0), + O => \wl_tap_count_r[0]_i_2_n_0\ + ); +\wl_tap_count_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA88A8888888A888" + ) + port map ( + I0 => \wl_tap_count_r[5]_i_4_n_0\, + I1 => \wl_tap_count_r[1]_i_2_n_0\, + I2 => \smallest_reg[0]_4\(1), + I3 => \wl_state_r__0\(1), + I4 => \dqs_count_r_reg[1]_0\(0), + I5 => \smallest_reg[1]_5\(1), + O => wl_tap_count_r(1) + ); +\wl_tap_count_r[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000666" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[0]\, + I1 => \wl_tap_count_r_reg_n_0_[1]\, + I2 => \wl_state_r__0\(0), + I3 => wr_level_done_r5, + I4 => \wl_state_r__0\(1), + O => \wl_tap_count_r[1]_i_2_n_0\ + ); +\wl_tap_count_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA88A8888888A888" + ) + port map ( + I0 => \wl_tap_count_r[5]_i_4_n_0\, + I1 => \wl_tap_count_r[2]_i_2_n_0\, + I2 => \smallest_reg[0]_4\(2), + I3 => \wl_state_r__0\(1), + I4 => \dqs_count_r_reg[1]_0\(0), + I5 => \smallest_reg[1]_5\(2), + O => wl_tap_count_r(2) + ); +\wl_tap_count_r[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000787878" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[1]\, + I1 => \wl_tap_count_r_reg_n_0_[0]\, + I2 => \wl_tap_count_r_reg_n_0_[2]\, + I3 => \wl_state_r__0\(0), + I4 => wr_level_done_r5, + I5 => \wl_state_r__0\(1), + O => \wl_tap_count_r[2]_i_2_n_0\ + ); +\wl_tap_count_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"80A08000AAAAAAAA" + ) + port map ( + I0 => \wl_tap_count_r[5]_i_4_n_0\, + I1 => \smallest_reg[1]_5\(3), + I2 => \wl_state_r__0\(1), + I3 => \dqs_count_r_reg[1]_0\(0), + I4 => \smallest_reg[0]_4\(3), + I5 => \wl_tap_count_r[3]_i_2_n_0\, + O => wl_tap_count_r(3) + ); +\wl_tap_count_r[3]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF9555" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[3]\, + I1 => \wl_tap_count_r_reg_n_0_[2]\, + I2 => \wl_tap_count_r_reg_n_0_[1]\, + I3 => \wl_tap_count_r_reg_n_0_[0]\, + I4 => \wl_tap_count_r[4]_i_3_n_0\, + O => \wl_tap_count_r[3]_i_2_n_0\ + ); +\wl_tap_count_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"80A08000AAAAAAAA" + ) + port map ( + I0 => \wl_tap_count_r[5]_i_4_n_0\, + I1 => \smallest_reg[1]_5\(4), + I2 => \wl_state_r__0\(1), + I3 => \dqs_count_r_reg[1]_0\(0), + I4 => \smallest_reg[0]_4\(4), + I5 => \wl_tap_count_r[4]_i_2_n_0\, + O => wl_tap_count_r(4) + ); +\wl_tap_count_r[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF95555555" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[4]\, + I1 => \wl_tap_count_r_reg_n_0_[3]\, + I2 => \wl_tap_count_r_reg_n_0_[0]\, + I3 => \wl_tap_count_r_reg_n_0_[1]\, + I4 => \wl_tap_count_r_reg_n_0_[2]\, + I5 => \wl_tap_count_r[4]_i_3_n_0\, + O => \wl_tap_count_r[4]_i_2_n_0\ + ); +\wl_tap_count_r[4]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => wr_level_done_r5, + I2 => \wl_state_r__0\(0), + O => \wl_tap_count_r[4]_i_3_n_0\ + ); +\wl_tap_count_r[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"003C080C03000003" + ) + port map ( + I0 => done_dqs_dec237_out, + I1 => \wl_state_r__0\(2), + I2 => \wl_state_r__0\(4), + I3 => \wl_state_r__0\(1), + I4 => \wl_state_r__0\(0), + I5 => \wl_state_r__0\(3), + O => \wl_tap_count_r[5]_i_1_n_0\ + ); +\wl_tap_count_r[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA88A8888888A888" + ) + port map ( + I0 => \wl_tap_count_r[5]_i_4_n_0\, + I1 => \wl_tap_count_r[5]_i_5_n_0\, + I2 => \smallest_reg[0]_4\(5), + I3 => \wl_state_r__0\(1), + I4 => \dqs_count_r_reg[1]_0\(0), + I5 => \smallest_reg[1]_5\(5), + O => wl_tap_count_r(5) + ); +\wl_tap_count_r[5]_i_4\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(3), + I1 => \wl_state_r__0\(4), + O => \wl_tap_count_r[5]_i_4_n_0\ + ); +\wl_tap_count_r[5]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000787878" + ) + port map ( + I0 => \wl_tap_count_r[5]_i_6_n_0\, + I1 => \wl_tap_count_r_reg_n_0_[4]\, + I2 => \wl_tap_count_r_reg_n_0_[5]\, + I3 => \wl_state_r__0\(0), + I4 => wr_level_done_r5, + I5 => \wl_state_r__0\(1), + O => \wl_tap_count_r[5]_i_5_n_0\ + ); +\wl_tap_count_r[5]_i_6\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => \wl_tap_count_r_reg_n_0_[2]\, + I1 => \wl_tap_count_r_reg_n_0_[1]\, + I2 => \wl_tap_count_r_reg_n_0_[0]\, + I3 => \wl_tap_count_r_reg_n_0_[3]\, + O => \wl_tap_count_r[5]_i_6_n_0\ + ); +\wl_tap_count_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_tap_count_r[5]_i_1_n_0\, + D => wl_tap_count_r(0), + Q => \wl_tap_count_r_reg_n_0_[0]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_tap_count_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_tap_count_r[5]_i_1_n_0\, + D => wl_tap_count_r(1), + Q => \wl_tap_count_r_reg_n_0_[1]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_tap_count_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_tap_count_r[5]_i_1_n_0\, + D => wl_tap_count_r(2), + Q => \wl_tap_count_r_reg_n_0_[2]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_tap_count_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_tap_count_r[5]_i_1_n_0\, + D => wl_tap_count_r(3), + Q => \wl_tap_count_r_reg_n_0_[3]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_tap_count_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_tap_count_r[5]_i_1_n_0\, + D => wl_tap_count_r(4), + Q => \wl_tap_count_r_reg_n_0_[4]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +\wl_tap_count_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \wl_tap_count_r[5]_i_1_n_0\, + D => wl_tap_count_r(5), + Q => \wl_tap_count_r_reg_n_0_[5]\, + R => wl_edge_detect_valid_r_reg_0(0) + ); +wr_level_done_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => \^done_dqs_tap_inc\, + I1 => \^wrlvl_byte_redo_r\, + I2 => wrlvl_byte_redo, + O => wr_level_done_i_1_n_0 + ); +wr_level_done_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_done_r_reg_n_0, + Q => wr_level_done_r1, + R => '0' + ); +wr_level_done_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_done_r1, + Q => wr_level_done_r2, + R => '0' + ); +wr_level_done_r3_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_done_r2, + Q => wr_level_done_r3, + R => '0' + ); +wr_level_done_r4_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_done_r3, + Q => wr_level_done_r4, + R => '0' + ); +wr_level_done_r5_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_done_r4, + Q => wr_level_done_r5, + R => '0' + ); +wr_level_done_r_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"01FF0100" + ) + port map ( + I0 => \rank_cnt_r_reg_n_0_[0]\, + I1 => \rank_cnt_r_reg_n_0_[1]\, + I2 => \wl_state_r__0\(2), + I3 => wr_level_done_r_i_2_n_0, + I4 => wr_level_done_r_reg_n_0, + O => wr_level_done_r_i_1_n_0 + ); +wr_level_done_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"4000400000002020" + ) + port map ( + I0 => \wl_state_r__0\(0), + I1 => \wl_state_r__0\(2), + I2 => \wrlvl_redo_corse_inc[2]_i_2_n_0\, + I3 => done_dqs_dec237_out, + I4 => p_0_in, + I5 => \wl_state_r__0\(3), + O => wr_level_done_r_i_2_n_0 + ); +wr_level_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_done_r_i_1_n_0, + Q => wr_level_done_r_reg_n_0, + R => wl_edge_detect_valid_r_reg_0(0) + ); +wr_level_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_done_i_1_n_0, + Q => \^wr_level_done_reg_0\, + R => '0' + ); +wr_level_start_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_level_start_r_reg_0, + Q => wr_level_start_r, + R => '0' + ); +wrlvl_byte_done_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000BAAA00AA" + ) + port map ( + I0 => \^wrlvl_byte_done\, + I1 => wr_level_done_r4, + I2 => wr_level_done_r3, + I3 => wrlvl_byte_redo, + I4 => \^wrlvl_byte_redo_r\, + I5 => \rd_data_edge_detect_r_reg[1]_0\, + O => wrlvl_byte_done_i_1_n_0 + ); +wrlvl_byte_done_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_byte_done_i_1_n_0, + Q => \^wrlvl_byte_done\, + R => '0' + ); +wrlvl_byte_redo_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_byte_redo, + Q => \^wrlvl_byte_redo_r\, + R => '0' + ); +wrlvl_rank_done_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"551F515F000A000A" + ) + port map ( + I0 => rank_cnt_r, + I1 => wrlvl_rank_done_r_i_2_n_0, + I2 => \wl_state_r__0\(2), + I3 => \wl_state_r__0\(4), + I4 => \wl_state_r__0\(3), + I5 => \^wrlvl_rank_done\, + O => wrlvl_rank_done_r_i_1_n_0 + ); +wrlvl_rank_done_r_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(0), + O => wrlvl_rank_done_r_i_2_n_0 + ); +wrlvl_rank_done_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wrlvl_rank_done_r_i_1_n_0, + Q => \^wrlvl_rank_done\, + R => \dqs_count_r_reg[0]_0\ + ); +\wrlvl_redo_corse_inc[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0044FFFF04440000" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(1), + I2 => \wl_state_r__0\(2), + I3 => \wrlvl_redo_corse_inc[1]_i_2_n_0\, + I4 => \wrlvl_redo_corse_inc[2]_i_3_n_0\, + I5 => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + O => \wrlvl_redo_corse_inc[0]_i_1_n_0\ + ); +\wrlvl_redo_corse_inc[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8880FFFF88080000" + ) + port map ( + I0 => \wrlvl_redo_corse_inc[1]_i_2_n_0\, + I1 => \wrlvl_redo_corse_inc[2]_i_2_n_0\, + I2 => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + I3 => \wl_state_r__0\(2), + I4 => \wrlvl_redo_corse_inc[2]_i_3_n_0\, + I5 => \wrlvl_redo_corse_inc_reg_n_0_[1]\, + O => \wrlvl_redo_corse_inc[1]_i_1_n_0\ + ); +\wrlvl_redo_corse_inc[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"DFD5FFFF" + ) + port map ( + I0 => \wl_state_r__0\(2), + I1 => \final_coarse_tap_reg_n_0_[1][2]\, + I2 => \dqs_count_r_reg[1]_0\(0), + I3 => \final_coarse_tap_reg_n_0_[0][2]\, + I4 => \wrlvl_redo_corse_inc[1]_i_3_n_0\, + O => \wrlvl_redo_corse_inc[1]_i_2_n_0\ + ); +\wrlvl_redo_corse_inc[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"202AA0AA2A2AAAAA" + ) + port map ( + I0 => \wrlvl_redo_corse_inc[1]_i_2_0\, + I1 => \^final_coarse_tap_reg[1][0]_0\(0), + I2 => \dqs_count_r_reg[1]_0\(0), + I3 => \^final_coarse_tap_reg[0][0]_0\(0), + I4 => \final_coarse_tap_reg_n_0_[1][1]\, + I5 => \final_coarse_tap_reg_n_0_[0][1]\, + O => \wrlvl_redo_corse_inc[1]_i_3_n_0\ + ); +\wrlvl_redo_corse_inc[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAA8FFFFAA020000" + ) + port map ( + I0 => \wrlvl_redo_corse_inc[2]_i_2_n_0\, + I1 => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + I2 => \wrlvl_redo_corse_inc_reg_n_0_[1]\, + I3 => \wl_state_r__0\(2), + I4 => \wrlvl_redo_corse_inc[2]_i_3_n_0\, + I5 => \wrlvl_redo_corse_inc_reg_n_0_[2]\, + O => \wrlvl_redo_corse_inc[2]_i_1_n_0\ + ); +\wrlvl_redo_corse_inc[2]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \wl_state_r__0\(1), + I1 => \wl_state_r__0\(4), + O => \wrlvl_redo_corse_inc[2]_i_2_n_0\ + ); +\wrlvl_redo_corse_inc[2]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \wl_state_r__0\(4), + I1 => \wl_state_r__0\(3), + I2 => \wl_state_r__0\(1), + I3 => \wrlvl_redo_corse_inc[2]_i_4_n_0\, + O => \wrlvl_redo_corse_inc[2]_i_3_n_0\ + ); +\wrlvl_redo_corse_inc[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFF5F5FFCFF5F5F" + ) + port map ( + I0 => \FSM_sequential_wl_state_r[2]_i_13_n_0\, + I1 => \FSM_sequential_wl_state_r[4]_i_13_0\, + I2 => \wl_state_r__0\(0), + I3 => done_dqs_dec237_out, + I4 => \wl_state_r__0\(2), + I5 => \corse_cnt[0][2]_i_4_n_0\, + O => \wrlvl_redo_corse_inc[2]_i_4_n_0\ + ); +\wrlvl_redo_corse_inc_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wrlvl_redo_corse_inc[0]_i_1_n_0\, + Q => \wrlvl_redo_corse_inc_reg_n_0_[0]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wrlvl_redo_corse_inc_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wrlvl_redo_corse_inc[1]_i_1_n_0\, + Q => \wrlvl_redo_corse_inc_reg_n_0_[1]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +\wrlvl_redo_corse_inc_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wrlvl_redo_corse_inc[2]_i_1_n_0\, + Q => \wrlvl_redo_corse_inc_reg_n_0_[2]\, + R => dqs_po_en_stg2_f_reg_0(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_infrastructure is + port ( + \gen_mmcm.mmcm_i_i_1_0\ : out STD_LOGIC; + CLK : out STD_LOGIC; + freq_refclk : out STD_LOGIC; + mem_refclk : out STD_LOGIC; + sync_pulse : out STD_LOGIC; + ui_clk_sync_rst : out STD_LOGIC; + SR : out STD_LOGIC_VECTOR ( 0 to 0 ); + rstdiv0_sync_r1_reg_rep_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__0_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__1_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__2_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__3_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__4_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__5_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__6_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__7_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__8_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \rstdiv0_sync_r1_reg_rep__9_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__10_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__12_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__14_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__15_0\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__16_0\ : out STD_LOGIC; + RST0 : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__16_1\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__16_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + pll_locked : out STD_LOGIC; + SS : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__14_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__15_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__15_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__15_3\ : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__15_4\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rstdiv0_sync_r1_reg_rep__16_3\ : out STD_LOGIC; + mmcm_clk : in STD_LOGIC; + AS : in STD_LOGIC_VECTOR ( 0 to 0 ); + rst_tmp : in STD_LOGIC; + insert_maint_r : in STD_LOGIC; + device_temp_sync_r4_neq_r3 : in STD_LOGIC; + po_cnt_dec : in STD_LOGIC; + po_cnt_dec_0 : in STD_LOGIC; + \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC; + \cnt_shift_r_reg[0]\ : in STD_LOGIC; + samp_edge_cnt0_en_r : in STD_LOGIC; + pi_cnt_dec : in STD_LOGIC; + prbs_rdlvl_done_pulse : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_infrastructure : entity is "mig_7series_v4_2_infrastructure"; +end ddr3_mig_7series_v4_2_infrastructure; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_infrastructure is + signal \^clk\ : STD_LOGIC; + signal RST0_0 : STD_LOGIC; + signal clk_div2_bufg_in : STD_LOGIC; + signal clk_pll_i : STD_LOGIC; + signal \^gen_mmcm.mmcm_i_i_1_0\ : STD_LOGIC; + signal \gen_mmcm.mmcm_i_n_17\ : STD_LOGIC; + signal \gen_mmcm.u_bufg_clk_div2_n_0\ : STD_LOGIC; + signal \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\ : STD_LOGIC; + signal mmcm_ps_clk_bufg_in : STD_LOGIC; + signal p_0_in : STD_LOGIC; + signal pll_clk3 : STD_LOGIC; + signal pll_clk3_out : STD_LOGIC; + signal pll_clkfbout : STD_LOGIC; + signal pll_locked_i : STD_LOGIC; + signal rst_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal rst_sync_r1 : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of rst_sync_r1 : signal is "10"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of rst_sync_r1 : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of rst_sync_r1 : signal is "10"; + signal rstdiv0_sync_r : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \^rstdiv0_sync_r1_reg_rep__14_0\ : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__15_0\ : STD_LOGIC; + signal \^rstdiv0_sync_r1_reg_rep__16_0\ : STD_LOGIC; + signal rstdiv2_sync_r1 : STD_LOGIC; + attribute MAX_FANOUT of rstdiv2_sync_r1 : signal is "10"; + attribute RTL_MAX_FANOUT of rstdiv2_sync_r1 : signal is "found"; + attribute syn_maxfan of rstdiv2_sync_r1 : signal is "10"; + signal \rstdiv2_sync_r_reg_n_0_[0]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[10]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[1]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[2]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[3]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[4]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[5]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[6]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[7]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[8]\ : STD_LOGIC; + signal \rstdiv2_sync_r_reg_n_0_[9]\ : STD_LOGIC; + signal \^ui_clk_sync_rst\ : STD_LOGIC; + attribute MAX_FANOUT of ui_clk_sync_rst : signal is "50"; + attribute RTL_MAX_FANOUT of ui_clk_sync_rst : signal is "found"; + attribute syn_maxfan of ui_clk_sync_rst : signal is "50"; + signal \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\ : STD_LOGIC; + signal \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal NLW_plle2_i_CLKOUT4_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_i_CLKOUT5_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_i_DRDY_UNCONNECTED : STD_LOGIC; + signal NLW_plle2_i_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cnt_shift_r[3]_i_1\ : label is "soft_lutpair4"; + attribute SOFT_HLUTNM of complex_row0_rd_done_i_2 : label is "soft_lutpair2"; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \gen_mmcm.mmcm_i\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_mmcm.u_bufg_clk_div2\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_mmcm.u_bufg_mmcm_ps_clk\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of phaser_ref_i_i_1 : label is "soft_lutpair6"; + attribute SOFT_HLUTNM of phy_control_i_i_1 : label is "soft_lutpair6"; + attribute BOX_TYPE of plle2_i : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1\ : label is "soft_lutpair2"; + attribute RTL_MAX_FANOUT of rst_sync_r1_reg : label is "found"; + attribute syn_maxfan of rst_sync_r1_reg : label is "10"; + attribute ORIG_CELL_NAME : string; + attribute ORIG_CELL_NAME of rstdiv0_sync_r1_reg : label is "rstdiv0_sync_r1_reg"; + attribute RTL_MAX_FANOUT of rstdiv0_sync_r1_reg : label is "found"; + attribute syn_maxfan of rstdiv0_sync_r1_reg : label is "50"; + attribute IS_FANOUT_CONSTRAINED : integer; + attribute IS_FANOUT_CONSTRAINED of rstdiv0_sync_r1_reg_rep : label is 1; + attribute ORIG_CELL_NAME of rstdiv0_sync_r1_reg_rep : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__0\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__0\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__1\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__1\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__10\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__10\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__11\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__11\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__12\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__12\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__13\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__13\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__14\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__14\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__15\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__15\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__16\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__16\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__2\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__2\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__3\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__3\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__4\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__4\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__5\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__5\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__6\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__6\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__7\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__7\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__8\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__8\ : label is "rstdiv0_sync_r1_reg"; + attribute IS_FANOUT_CONSTRAINED of \rstdiv0_sync_r1_reg_rep__9\ : label is 1; + attribute ORIG_CELL_NAME of \rstdiv0_sync_r1_reg_rep__9\ : label is "rstdiv0_sync_r1_reg"; + attribute RTL_MAX_FANOUT of rstdiv2_sync_r1_reg : label is "found"; + attribute syn_maxfan of rstdiv2_sync_r1_reg : label is "10"; + attribute SOFT_HLUTNM of \samp_edge_cnt0_r[0]_i_1\ : label is "soft_lutpair5"; + attribute SOFT_HLUTNM of \tap_cnt_cpt_r[5]_i_1\ : label is "soft_lutpair4"; + attribute BOX_TYPE of u_bufg_clkdiv0 : label is "PRIMITIVE"; + attribute BOX_TYPE of u_bufh_pll_clk3 : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of \wait_cnt[3]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_1\ : label is "soft_lutpair3"; + attribute SOFT_HLUTNM of \wait_cnt_r[3]_i_1__0\ : label is "soft_lutpair5"; +begin + CLK <= \^clk\; + SR(0) <= \^ui_clk_sync_rst\; + \gen_mmcm.mmcm_i_i_1_0\ <= \^gen_mmcm.mmcm_i_i_1_0\; + \rstdiv0_sync_r1_reg_rep__14_0\ <= \^rstdiv0_sync_r1_reg_rep__14_0\; + \rstdiv0_sync_r1_reg_rep__15_0\ <= \^rstdiv0_sync_r1_reg_rep__15_0\; + \rstdiv0_sync_r1_reg_rep__16_0\ <= \^rstdiv0_sync_r1_reg_rep__16_0\; + ui_clk_sync_rst <= \^ui_clk_sync_rst\; +\cnt_shift_r[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__15_0\, + I1 => \cnt_shift_r_reg[0]\, + O => \rstdiv0_sync_r1_reg_rep__15_2\(0) + ); +complex_row0_rd_done_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__16_0\, + I1 => prbs_rdlvl_done_pulse, + O => \rstdiv0_sync_r1_reg_rep__16_3\ + ); +\gen_mmcm.mmcm_i\: unisim.vcomponents.MMCME2_ADV + generic map( + BANDWIDTH => "HIGH", + CLKFBOUT_MULT_F => 8.000000, + CLKFBOUT_PHASE => 0.000000, + CLKFBOUT_USE_FINE_PS => false, + CLKIN1_PERIOD => 12.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE_F => 16.000000, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT0_USE_FINE_PS => true, + CLKOUT1_DIVIDE => 4, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT1_USE_FINE_PS => false, + CLKOUT2_DIVIDE => 1, + CLKOUT2_DUTY_CYCLE => 0.500000, + CLKOUT2_PHASE => 0.000000, + CLKOUT2_USE_FINE_PS => false, + CLKOUT3_DIVIDE => 1, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT3_USE_FINE_PS => false, + CLKOUT4_CASCADE => false, + CLKOUT4_DIVIDE => 1, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 0.000000, + CLKOUT4_USE_FINE_PS => false, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + CLKOUT5_USE_FINE_PS => false, + CLKOUT6_DIVIDE => 1, + CLKOUT6_DUTY_CYCLE => 0.500000, + CLKOUT6_PHASE => 0.000000, + CLKOUT6_USE_FINE_PS => false, + COMPENSATION => "BUF_IN", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PSEN_INVERTED => '0', + IS_PSINCDEC_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.000000, + REF_JITTER2 => 0.010000, + SS_EN => "FALSE", + SS_MODE => "CENTER_HIGH", + SS_MOD_PERIOD => 10000, + STARTUP_WAIT => false + ) + port map ( + CLKFBIN => \^clk\, + CLKFBOUT => clk_pll_i, + CLKFBOUTB => \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED\, + CLKFBSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED\, + CLKIN1 => pll_clk3, + CLKIN2 => '0', + CLKINSEL => '1', + CLKINSTOPPED => \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED\, + CLKOUT0 => mmcm_ps_clk_bufg_in, + CLKOUT0B => \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED\, + CLKOUT1 => clk_div2_bufg_in, + CLKOUT1B => \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED\, + CLKOUT2 => \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED\, + CLKOUT2B => \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED\, + CLKOUT3 => \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED\, + CLKOUT3B => \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED\, + CLKOUT4 => \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED\, + CLKOUT5 => \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED\, + CLKOUT6 => \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED\, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => \NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED\(15 downto 0), + DRDY => \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED\, + DWE => '0', + LOCKED => \^gen_mmcm.mmcm_i_i_1_0\, + PSCLK => \^clk\, + PSDONE => \gen_mmcm.mmcm_i_n_17\, + PSEN => '0', + PSINCDEC => '0', + PWRDWN => '0', + RST => RST0_0 + ); +\gen_mmcm.mmcm_i_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => pll_locked_i, + O => RST0_0 + ); +\gen_mmcm.u_bufg_clk_div2\: unisim.vcomponents.BUFG + port map ( + I => clk_div2_bufg_in, + O => \gen_mmcm.u_bufg_clk_div2_n_0\ + ); +\gen_mmcm.u_bufg_mmcm_ps_clk\: unisim.vcomponents.BUFG + port map ( + I => mmcm_ps_clk_bufg_in, + O => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\ + ); +phaser_ref_i_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \^gen_mmcm.mmcm_i_i_1_0\, + I1 => pll_locked_i, + O => RST0 + ); +phy_control_i_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => pll_locked_i, + I1 => \^gen_mmcm.mmcm_i_i_1_0\, + O => pll_locked + ); +plle2_i: unisim.vcomponents.PLLE2_ADV + generic map( + BANDWIDTH => "OPTIMIZED", + CLKFBOUT_MULT => 4, + CLKFBOUT_PHASE => 0.000000, + CLKIN1_PERIOD => 3.000000, + CLKIN2_PERIOD => 0.000000, + CLKOUT0_DIVIDE => 2, + CLKOUT0_DUTY_CYCLE => 0.500000, + CLKOUT0_PHASE => 0.000000, + CLKOUT1_DIVIDE => 4, + CLKOUT1_DUTY_CYCLE => 0.500000, + CLKOUT1_PHASE => 0.000000, + CLKOUT2_DIVIDE => 64, + CLKOUT2_DUTY_CYCLE => 0.062500, + CLKOUT2_PHASE => 9.843750, + CLKOUT3_DIVIDE => 16, + CLKOUT3_DUTY_CYCLE => 0.500000, + CLKOUT3_PHASE => 0.000000, + CLKOUT4_DIVIDE => 8, + CLKOUT4_DUTY_CYCLE => 0.500000, + CLKOUT4_PHASE => 168.750000, + CLKOUT5_DIVIDE => 1, + CLKOUT5_DUTY_CYCLE => 0.500000, + CLKOUT5_PHASE => 0.000000, + COMPENSATION => "INTERNAL", + DIVCLK_DIVIDE => 1, + IS_CLKINSEL_INVERTED => '0', + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0', + REF_JITTER1 => 0.010000, + REF_JITTER2 => 0.010000, + STARTUP_WAIT => "FALSE" + ) + port map ( + CLKFBIN => pll_clkfbout, + CLKFBOUT => pll_clkfbout, + CLKIN1 => mmcm_clk, + CLKIN2 => '0', + CLKINSEL => '1', + CLKOUT0 => freq_refclk, + CLKOUT1 => mem_refclk, + CLKOUT2 => sync_pulse, + CLKOUT3 => pll_clk3_out, + CLKOUT4 => NLW_plle2_i_CLKOUT4_UNCONNECTED, + CLKOUT5 => NLW_plle2_i_CLKOUT5_UNCONNECTED, + DADDR(6 downto 0) => B"0000000", + DCLK => '0', + DEN => '0', + DI(15 downto 0) => B"0000000000000000", + DO(15 downto 0) => NLW_plle2_i_DO_UNCONNECTED(15 downto 0), + DRDY => NLW_plle2_i_DRDY_UNCONNECTED, + DWE => '0', + LOCKED => pll_locked_i, + PWRDWN => '0', + RST => AS(0) + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__16_0\, + I1 => insert_maint_r, + O => \rstdiv0_sync_r1_reg_rep__16_1\ + ); +rst_sync_r1_reg: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(11), + PRE => rst_tmp, + Q => rst_sync_r1 + ); +\rst_sync_r_reg[0]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => '0', + PRE => rst_tmp, + Q => rst_sync_r(0) + ); +\rst_sync_r_reg[10]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(9), + PRE => rst_tmp, + Q => rst_sync_r(10) + ); +\rst_sync_r_reg[11]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(10), + PRE => rst_tmp, + Q => rst_sync_r(11) + ); +\rst_sync_r_reg[1]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(0), + PRE => rst_tmp, + Q => rst_sync_r(1) + ); +\rst_sync_r_reg[2]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(1), + PRE => rst_tmp, + Q => rst_sync_r(2) + ); +\rst_sync_r_reg[3]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(2), + PRE => rst_tmp, + Q => rst_sync_r(3) + ); +\rst_sync_r_reg[4]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(3), + PRE => rst_tmp, + Q => rst_sync_r(4) + ); +\rst_sync_r_reg[5]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(4), + PRE => rst_tmp, + Q => rst_sync_r(5) + ); +\rst_sync_r_reg[6]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(5), + PRE => rst_tmp, + Q => rst_sync_r(6) + ); +\rst_sync_r_reg[7]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(6), + PRE => rst_tmp, + Q => rst_sync_r(7) + ); +\rst_sync_r_reg[8]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(7), + PRE => rst_tmp, + Q => rst_sync_r(8) + ); +\rst_sync_r_reg[9]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_mmcm_ps_clk_n_0\, + CE => '1', + D => rst_sync_r(8), + PRE => rst_tmp, + Q => rst_sync_r(9) + ); +rstdiv0_sync_r1_reg: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \^ui_clk_sync_rst\ + ); +rstdiv0_sync_r1_reg_rep: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => rstdiv0_sync_r1_reg_rep_0(0) + ); +\rstdiv0_sync_r1_reg_rep__0\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__0_0\(0) + ); +\rstdiv0_sync_r1_reg_rep__1\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__1_0\(0) + ); +\rstdiv0_sync_r1_reg_rep__10\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__10_0\ + ); +\rstdiv0_sync_r1_reg_rep__11\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__8_0\(0) + ); +\rstdiv0_sync_r1_reg_rep__12\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__12_0\ + ); +\rstdiv0_sync_r1_reg_rep__13\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__13_0\ + ); +\rstdiv0_sync_r1_reg_rep__14\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \^rstdiv0_sync_r1_reg_rep__14_0\ + ); +\rstdiv0_sync_r1_reg_rep__15\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \^rstdiv0_sync_r1_reg_rep__15_0\ + ); +\rstdiv0_sync_r1_reg_rep__16\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \^rstdiv0_sync_r1_reg_rep__16_0\ + ); +\rstdiv0_sync_r1_reg_rep__2\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__2_0\(0) + ); +\rstdiv0_sync_r1_reg_rep__3\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__3_0\ + ); +\rstdiv0_sync_r1_reg_rep__4\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__4_0\ + ); +\rstdiv0_sync_r1_reg_rep__5\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__5_0\(0) + ); +\rstdiv0_sync_r1_reg_rep__6\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__6_0\ + ); +\rstdiv0_sync_r1_reg_rep__7\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__7_0\ + ); +\rstdiv0_sync_r1_reg_rep__8\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__8_0\(1) + ); +\rstdiv0_sync_r1_reg_rep__9\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(11), + PRE => rst_tmp, + Q => \rstdiv0_sync_r1_reg_rep__9_0\ + ); +\rstdiv0_sync_r_reg[0]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => '0', + PRE => rst_tmp, + Q => rstdiv0_sync_r(0) + ); +\rstdiv0_sync_r_reg[10]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(9), + PRE => rst_tmp, + Q => rstdiv0_sync_r(10) + ); +\rstdiv0_sync_r_reg[11]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(10), + PRE => rst_tmp, + Q => rstdiv0_sync_r(11) + ); +\rstdiv0_sync_r_reg[1]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(0), + PRE => rst_tmp, + Q => rstdiv0_sync_r(1) + ); +\rstdiv0_sync_r_reg[2]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(1), + PRE => rst_tmp, + Q => rstdiv0_sync_r(2) + ); +\rstdiv0_sync_r_reg[3]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(2), + PRE => rst_tmp, + Q => rstdiv0_sync_r(3) + ); +\rstdiv0_sync_r_reg[4]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(3), + PRE => rst_tmp, + Q => rstdiv0_sync_r(4) + ); +\rstdiv0_sync_r_reg[5]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(4), + PRE => rst_tmp, + Q => rstdiv0_sync_r(5) + ); +\rstdiv0_sync_r_reg[6]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(5), + PRE => rst_tmp, + Q => rstdiv0_sync_r(6) + ); +\rstdiv0_sync_r_reg[7]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(6), + PRE => rst_tmp, + Q => rstdiv0_sync_r(7) + ); +\rstdiv0_sync_r_reg[8]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(7), + PRE => rst_tmp, + Q => rstdiv0_sync_r(8) + ); +\rstdiv0_sync_r_reg[9]\: unisim.vcomponents.FDPE + port map ( + C => \^clk\, + CE => '1', + D => rstdiv0_sync_r(8), + PRE => rst_tmp, + Q => rstdiv0_sync_r(9) + ); +rstdiv2_sync_r1_reg: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => p_0_in, + PRE => rst_tmp, + Q => rstdiv2_sync_r1 + ); +\rstdiv2_sync_r_reg[0]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => '0', + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[0]\ + ); +\rstdiv2_sync_r_reg[10]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[9]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[10]\ + ); +\rstdiv2_sync_r_reg[11]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[10]\, + PRE => rst_tmp, + Q => p_0_in + ); +\rstdiv2_sync_r_reg[1]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[0]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[1]\ + ); +\rstdiv2_sync_r_reg[2]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[1]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[2]\ + ); +\rstdiv2_sync_r_reg[3]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[2]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[3]\ + ); +\rstdiv2_sync_r_reg[4]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[3]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[4]\ + ); +\rstdiv2_sync_r_reg[5]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[4]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[5]\ + ); +\rstdiv2_sync_r_reg[6]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[5]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[6]\ + ); +\rstdiv2_sync_r_reg[7]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[6]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[7]\ + ); +\rstdiv2_sync_r_reg[8]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[7]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[8]\ + ); +\rstdiv2_sync_r_reg[9]\: unisim.vcomponents.FDPE + port map ( + C => \gen_mmcm.u_bufg_clk_div2_n_0\, + CE => '1', + D => \rstdiv2_sync_r_reg_n_0_[8]\, + PRE => rst_tmp, + Q => \rstdiv2_sync_r_reg_n_0_[9]\ + ); +\samp_edge_cnt0_r[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__15_0\, + I1 => samp_edge_cnt0_en_r, + O => \rstdiv0_sync_r1_reg_rep__15_3\ + ); +\sync_cntr[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__16_0\, + I1 => device_temp_sync_r4_neq_r3, + O => \rstdiv0_sync_r1_reg_rep__16_2\(0) + ); +\tap_cnt_cpt_r[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__15_0\, + I1 => \tap_cnt_cpt_r_reg[5]\, + O => \rstdiv0_sync_r1_reg_rep__15_1\(0) + ); +u_bufg_clkdiv0: unisim.vcomponents.BUFG + port map ( + I => clk_pll_i, + O => \^clk\ + ); +u_bufh_pll_clk3: unisim.vcomponents.BUFH + port map ( + I => pll_clk3_out, + O => pll_clk3 + ); +\wait_cnt[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__14_0\, + I1 => po_cnt_dec, + O => SS(0) + ); +\wait_cnt_r[3]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__14_0\, + I1 => po_cnt_dec_0, + O => \rstdiv0_sync_r1_reg_rep__14_1\(0) + ); +\wait_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^rstdiv0_sync_r1_reg_rep__15_0\, + I1 => pi_cnt_dec, + O => \rstdiv0_sync_r1_reg_rep__15_4\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_iodelay_ctrl is + port ( + rst_tmp : out STD_LOGIC; + AS : out STD_LOGIC_VECTOR ( 0 to 0 ); + clk_ref_i : in STD_LOGIC; + sys_rst : in STD_LOGIC; + \rstdiv2_sync_r_reg[11]\ : in STD_LOGIC; + ref_dll_lock : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_iodelay_ctrl : entity is "mig_7series_v4_2_iodelay_ctrl"; +end ddr3_mig_7series_v4_2_iodelay_ctrl; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_iodelay_ctrl is + signal \^as\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal iodelay_ctrl_rdy : STD_LOGIC_VECTOR ( 0 to 0 ); + signal rst_ref : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \rst_ref_sync_r_reg_n_0_[0][0]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][10]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][11]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][12]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][13]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][1]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][2]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][3]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][4]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][5]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][6]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][7]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][8]\ : STD_LOGIC; + signal \rst_ref_sync_r_reg_n_0_[0][9]\ : STD_LOGIC; + signal sys_rst_i : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of sys_rst_i : signal is "true"; + attribute syn_maxfan : string; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][0]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][10]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][11]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][12]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][13]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][14]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][1]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][2]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][3]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][4]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][5]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][6]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][7]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][8]\ : label is "10"; + attribute syn_maxfan of \rst_ref_sync_r_reg[0][9]\ : label is "10"; + attribute BOX_TYPE : string; + attribute BOX_TYPE of u_idelayctrl_200 : label is "PRIMITIVE"; + attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP of u_idelayctrl_200 : label is "DDR3_IODELAY_MIG0"; +begin + AS(0) <= \^as\(0); + sys_rst_i <= sys_rst; +plle2_i_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sys_rst_i, + O => \^as\(0) + ); +\rst_ref_sync_r_reg[0][0]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => '0', + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][0]\ + ); +\rst_ref_sync_r_reg[0][10]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][9]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][10]\ + ); +\rst_ref_sync_r_reg[0][11]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][10]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][11]\ + ); +\rst_ref_sync_r_reg[0][12]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][11]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][12]\ + ); +\rst_ref_sync_r_reg[0][13]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][12]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][13]\ + ); +\rst_ref_sync_r_reg[0][14]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][13]\, + PRE => \^as\(0), + Q => rst_ref(0) + ); +\rst_ref_sync_r_reg[0][1]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][0]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][1]\ + ); +\rst_ref_sync_r_reg[0][2]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][1]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][2]\ + ); +\rst_ref_sync_r_reg[0][3]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][2]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][3]\ + ); +\rst_ref_sync_r_reg[0][4]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][3]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][4]\ + ); +\rst_ref_sync_r_reg[0][5]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][4]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][5]\ + ); +\rst_ref_sync_r_reg[0][6]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][5]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][6]\ + ); +\rst_ref_sync_r_reg[0][7]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][6]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][7]\ + ); +\rst_ref_sync_r_reg[0][8]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][7]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][8]\ + ); +\rst_ref_sync_r_reg[0][9]\: unisim.vcomponents.FDPE + port map ( + C => clk_ref_i, + CE => '1', + D => \rst_ref_sync_r_reg_n_0_[0][8]\, + PRE => \^as\(0), + Q => \rst_ref_sync_r_reg_n_0_[0][9]\ + ); +\rstdiv2_sync_r[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => \rstdiv2_sync_r_reg[11]\, + I1 => iodelay_ctrl_rdy(0), + I2 => sys_rst_i, + I3 => ref_dll_lock, + O => rst_tmp + ); +u_idelayctrl_200: unisim.vcomponents.IDELAYCTRL + generic map( + SIM_DEVICE => "7SERIES" + ) + port map ( + RDY => iodelay_ctrl_rdy(0), + REFCLK => clk_ref_i, + RST => rst_ref(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_rank_cntrl is + port ( + \periodic_rd_generation.read_this_rank_r\ : out STD_LOGIC; + inhbt_act_faw_r : out STD_LOGIC; + \periodic_rd_generation.periodic_rd_request_r\ : out STD_LOGIC; + \periodic_rd_generation.periodic_rd_cntr1_r\ : out STD_LOGIC; + \refresh_generation.refresh_bank_r\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + app_ref_req_0 : out STD_LOGIC; + act_this_rank : in STD_LOGIC; + CLK : in STD_LOGIC; + \periodic_rd_generation.read_this_rank\ : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_request_r_reg_0\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ : in STD_LOGIC; + \refresh_generation.refresh_bank_r_reg[0]_0\ : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ : in STD_LOGIC; + clear_periodic_rd_request : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_request_r_reg_1\ : in STD_LOGIC; + \wtr_timer.wtr_cnt_r_reg[1]_0\ : in STD_LOGIC; + \wtr_timer.wtr_cnt_r_reg[0]_0\ : in STD_LOGIC; + \inhbt_act_faw.inhbt_act_faw_r_reg_0\ : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + app_ref_r : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\ : in STD_LOGIC; + maint_prescaler_tick_r : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_rank_cntrl : entity is "mig_7series_v4_2_rank_cntrl"; +end ddr3_mig_7series_v4_2_rank_cntrl; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_rank_cntrl is + signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \inhbt_act_faw.act_delayed\ : STD_LOGIC; + signal \inhbt_act_faw.faw_cnt_r\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \inhbt_act_faw.faw_cnt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \inhbt_act_faw.faw_cnt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \inhbt_act_faw.faw_cnt_r[2]_i_1_n_0\ : STD_LOGIC; + signal \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\ : STD_LOGIC; + signal \^periodic_rd_generation.periodic_rd_cntr1_r\ : STD_LOGIC; + signal \^periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC; + signal \periodic_rd_generation.periodic_rd_request_r_i_1_n_0\ : STD_LOGIC; + signal \periodic_rd_generation.periodic_rd_request_r_i_2_n_0\ : STD_LOGIC; + signal \periodic_rd_generation.periodic_rd_timer_r\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\ : STD_LOGIC; + signal \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\ : STD_LOGIC; + signal \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\ : STD_LOGIC; + signal \^refresh_generation.refresh_bank_r\ : STD_LOGIC; + signal \wtr_timer.wtr_cnt_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \wtr_timer.wtr_cnt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \wtr_timer.wtr_cnt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\ : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \inhbt_act_faw.SRLC32E0\ : label is "PRIMITIVE"; + attribute srl_bus_name : string; + attribute srl_bus_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl "; + attribute srl_name : string; + attribute srl_name of \inhbt_act_faw.SRLC32E0\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 "; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \inhbt_act_faw.faw_cnt_r[0]_i_1\ : label is "soft_lutpair545"; + attribute SOFT_HLUTNM of \inhbt_act_faw.faw_cnt_r[1]_i_1\ : label is "soft_lutpair545"; + attribute SOFT_HLUTNM of \wtr_timer.wtr_cnt_r[0]_i_1\ : label is "soft_lutpair546"; + attribute SOFT_HLUTNM of \wtr_timer.wtr_cnt_r[1]_i_1\ : label is "soft_lutpair546"; +begin + Q(0) <= \^q\(0); + \periodic_rd_generation.periodic_rd_cntr1_r\ <= \^periodic_rd_generation.periodic_rd_cntr1_r\; + \periodic_rd_generation.periodic_rd_request_r\ <= \^periodic_rd_generation.periodic_rd_request_r\; + \refresh_generation.refresh_bank_r\ <= \^refresh_generation.refresh_bank_r\; +app_ref_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => app_ref_req, + I1 => \^refresh_generation.refresh_bank_r\, + I2 => app_ref_r, + O => app_ref_req_0 + ); +\inhbt_act_faw.SRLC32E0\: unisim.vcomponents.SRLC32E + generic map( + INIT => X"00000000", + IS_CLK_INVERTED => '0' + ) + port map ( + A(4 downto 0) => B"00001", + CE => '1', + CLK => CLK, + D => act_this_rank, + Q => \inhbt_act_faw.act_delayed\, + Q31 => \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED\ + ); +\inhbt_act_faw.faw_cnt_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4114" + ) + port map ( + I0 => \inhbt_act_faw.inhbt_act_faw_r_reg_0\, + I1 => \inhbt_act_faw.act_delayed\, + I2 => act_this_rank, + I3 => \inhbt_act_faw.faw_cnt_r\(0), + O => \inhbt_act_faw.faw_cnt_r[0]_i_1_n_0\ + ); +\inhbt_act_faw.faw_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"41444414" + ) + port map ( + I0 => \inhbt_act_faw.inhbt_act_faw_r_reg_0\, + I1 => \inhbt_act_faw.faw_cnt_r\(1), + I2 => \inhbt_act_faw.act_delayed\, + I3 => act_this_rank, + I4 => \inhbt_act_faw.faw_cnt_r\(0), + O => \inhbt_act_faw.faw_cnt_r[1]_i_1_n_0\ + ); +\inhbt_act_faw.faw_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5155554504000010" + ) + port map ( + I0 => \inhbt_act_faw.inhbt_act_faw_r_reg_0\, + I1 => \inhbt_act_faw.faw_cnt_r\(0), + I2 => \inhbt_act_faw.act_delayed\, + I3 => act_this_rank, + I4 => \inhbt_act_faw.faw_cnt_r\(1), + I5 => \inhbt_act_faw.faw_cnt_r\(2), + O => \inhbt_act_faw.faw_cnt_r[2]_i_1_n_0\ + ); +\inhbt_act_faw.faw_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \inhbt_act_faw.faw_cnt_r[0]_i_1_n_0\, + Q => \inhbt_act_faw.faw_cnt_r\(0), + R => '0' + ); +\inhbt_act_faw.faw_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \inhbt_act_faw.faw_cnt_r[1]_i_1_n_0\, + Q => \inhbt_act_faw.faw_cnt_r\(1), + R => '0' + ); +\inhbt_act_faw.faw_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \inhbt_act_faw.faw_cnt_r[2]_i_1_n_0\, + Q => \inhbt_act_faw.faw_cnt_r\(2), + R => '0' + ); +\inhbt_act_faw.inhbt_act_faw_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0100000000202002" + ) + port map ( + I0 => \inhbt_act_faw.faw_cnt_r\(2), + I1 => \inhbt_act_faw.inhbt_act_faw_r_reg_0\, + I2 => \inhbt_act_faw.act_delayed\, + I3 => act_this_rank, + I4 => \inhbt_act_faw.faw_cnt_r\(0), + I5 => \inhbt_act_faw.faw_cnt_r\(1), + O => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\ + ); +\inhbt_act_faw.inhbt_act_faw_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0\, + Q => inhbt_act_faw_r, + R => '0' + ); +\periodic_rd_generation.periodic_rd_cntr1_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\, + Q => \^periodic_rd_generation.periodic_rd_cntr1_r\, + R => SR(0) + ); +\periodic_rd_generation.periodic_rd_request_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00545454FFFFFFFF" + ) + port map ( + I0 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\, + I1 => \periodic_rd_generation.periodic_rd_request_r_i_2_n_0\, + I2 => \^periodic_rd_generation.periodic_rd_request_r\, + I3 => clear_periodic_rd_request, + I4 => \^periodic_rd_generation.periodic_rd_cntr1_r\, + I5 => \periodic_rd_generation.periodic_rd_request_r_reg_1\, + O => \periodic_rd_generation.periodic_rd_request_r_i_1_n_0\ + ); +\periodic_rd_generation.periodic_rd_request_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => \periodic_rd_generation.periodic_rd_timer_r\(2), + I1 => \periodic_rd_generation.periodic_rd_timer_r\(0), + I2 => maint_prescaler_tick_r, + I3 => \periodic_rd_generation.periodic_rd_timer_r\(1), + O => \periodic_rd_generation.periodic_rd_request_r_i_2_n_0\ + ); +\periodic_rd_generation.periodic_rd_request_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_rd_generation.periodic_rd_request_r_i_1_n_0\, + Q => \^periodic_rd_generation.periodic_rd_request_r\, + R => \periodic_rd_generation.periodic_rd_request_r_reg_0\ + ); +\periodic_rd_generation.periodic_rd_timer_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BBFFFFBBBFFBFFBB" + ) + port map ( + I0 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\, + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\, + I2 => \periodic_rd_generation.periodic_rd_timer_r\(2), + I3 => \periodic_rd_generation.periodic_rd_timer_r\(0), + I4 => maint_prescaler_tick_r, + I5 => \periodic_rd_generation.periodic_rd_timer_r\(1), + O => \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\ + ); +\periodic_rd_generation.periodic_rd_timer_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4400444400400000" + ) + port map ( + I0 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\, + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\, + I2 => \periodic_rd_generation.periodic_rd_timer_r\(2), + I3 => \periodic_rd_generation.periodic_rd_timer_r\(0), + I4 => maint_prescaler_tick_r, + I5 => \periodic_rd_generation.periodic_rd_timer_r\(1), + O => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\ + ); +\periodic_rd_generation.periodic_rd_timer_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FBFBFBFBFFBBFBFB" + ) + port map ( + I0 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\, + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\, + I2 => \periodic_rd_generation.periodic_rd_timer_r\(2), + I3 => \periodic_rd_generation.periodic_rd_timer_r\(0), + I4 => maint_prescaler_tick_r, + I5 => \periodic_rd_generation.periodic_rd_timer_r\(1), + O => \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\ + ); +\periodic_rd_generation.periodic_rd_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0\, + Q => \periodic_rd_generation.periodic_rd_timer_r\(0), + R => '0' + ); +\periodic_rd_generation.periodic_rd_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0\, + Q => \periodic_rd_generation.periodic_rd_timer_r\(1), + R => '0' + ); +\periodic_rd_generation.periodic_rd_timer_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0\, + Q => \periodic_rd_generation.periodic_rd_timer_r\(2), + R => '0' + ); +\periodic_rd_generation.read_this_rank_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_rd_generation.read_this_rank\, + Q => \periodic_rd_generation.read_this_rank_r\, + R => '0' + ); +\refresh_generation.refresh_bank_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \refresh_generation.refresh_bank_r_reg[0]_0\, + Q => \^refresh_generation.refresh_bank_r\, + R => '0' + ); +\wtr_timer.wtr_cnt_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0455" + ) + port map ( + I0 => \wtr_timer.wtr_cnt_r_reg[1]_0\, + I1 => \^q\(0), + I2 => \wtr_timer.wtr_cnt_r\(0), + I3 => \wtr_timer.wtr_cnt_r_reg[0]_0\, + O => \wtr_timer.wtr_cnt_r[0]_i_1_n_0\ + ); +\wtr_timer.wtr_cnt_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4055" + ) + port map ( + I0 => \wtr_timer.wtr_cnt_r_reg[1]_0\, + I1 => \^q\(0), + I2 => \wtr_timer.wtr_cnt_r\(0), + I3 => \wtr_timer.wtr_cnt_r_reg[0]_0\, + O => \wtr_timer.wtr_cnt_r[1]_i_1_n_0\ + ); +\wtr_timer.wtr_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wtr_timer.wtr_cnt_r[0]_i_1_n_0\, + Q => \wtr_timer.wtr_cnt_r\(0), + R => '0' + ); +\wtr_timer.wtr_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wtr_timer.wtr_cnt_r[1]_i_1_n_0\, + Q => \^q\(0), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_round_robin_arb is + port ( + \maintenance_request.maint_rank_r_lcl_reg[0]\ : out STD_LOGIC; + \maintenance_request.maint_sre_ns\ : out STD_LOGIC; + \maintenance_request.maint_sre_r_lcl_reg\ : out STD_LOGIC; + \grant_r_reg[1]_0\ : out STD_LOGIC; + maint_rank_r : in STD_LOGIC; + \last_master_r_reg[2]_0\ : in STD_LOGIC; + \maintenance_request.new_maint_rank_r\ : in STD_LOGIC; + \maintenance_request.upd_last_master_r\ : in STD_LOGIC; + maint_sre_r : in STD_LOGIC; + app_sr_req : in STD_LOGIC; + \sr_cntrl.ckesr_timer.ckesr_timer_r\ : in STD_LOGIC; + \maintenance_request.maint_srx_r_lcl_reg\ : in STD_LOGIC; + \grant_r_reg[0]_0\ : in STD_LOGIC; + \refresh_generation.refresh_bank_r\ : in STD_LOGIC; + \zq_cntrl.zq_request_logic.zq_request_r\ : in STD_LOGIC; + \sr_cntrl.sre_request_logic.sre_request_r\ : in STD_LOGIC; + \maintenance_request.maint_zq_r_lcl_reg\ : in STD_LOGIC; + CLK : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_round_robin_arb : entity is "mig_7series_v4_2_round_robin_arb"; +end ddr3_mig_7series_v4_2_round_robin_arb; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_round_robin_arb is + signal \grant_r[0]_i_1__1_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_1__0_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_2__0_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_3_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_1__1_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_2__3_n_0\ : STD_LOGIC; + signal last_master_r : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \last_master_r[0]_i_1__3_n_0\ : STD_LOGIC; + signal \last_master_r[1]_i_1__3_n_0\ : STD_LOGIC; + signal \last_master_r[2]_i_1_n_0\ : STD_LOGIC; + signal \maintenance_request.maint_grant_r\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0\ : STD_LOGIC; + signal \maintenance_request.maint_rank_r_lcl[0]_i_3_n_0\ : STD_LOGIC; + signal \^maintenance_request.maint_sre_ns\ : STD_LOGIC; + signal \maintenance_request.maint_sre_r_lcl_i_2_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \grant_r[1]_i_2__0\ : label is "soft_lutpair548"; + attribute SOFT_HLUTNM of \grant_r[2]_i_2__3\ : label is "soft_lutpair549"; + attribute SOFT_HLUTNM of \last_master_r[0]_i_1__3\ : label is "soft_lutpair547"; + attribute SOFT_HLUTNM of \last_master_r[1]_i_1__3\ : label is "soft_lutpair548"; + attribute SOFT_HLUTNM of \last_master_r[2]_i_1\ : label is "soft_lutpair549"; + attribute SOFT_HLUTNM of \maintenance_request.maint_sre_r_lcl_i_2\ : label is "soft_lutpair547"; +begin + \maintenance_request.maint_sre_ns\ <= \^maintenance_request.maint_sre_ns\; +\grant_r[0]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000C04040C0C" + ) + port map ( + I0 => \last_master_r[1]_i_1__3_n_0\, + I1 => \grant_r_reg[0]_0\, + I2 => \refresh_generation.refresh_bank_r\, + I3 => \zq_cntrl.zq_request_logic.zq_request_r\, + I4 => \sr_cntrl.sre_request_logic.sre_request_r\, + I5 => \last_master_r[0]_i_1__3_n_0\, + O => \grant_r[0]_i_1__1_n_0\ + ); +\grant_r[1]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA80000080800000" + ) + port map ( + I0 => \zq_cntrl.zq_request_logic.zq_request_r\, + I1 => \grant_r[2]_i_2__3_n_0\, + I2 => \grant_r[1]_i_2__0_n_0\, + I3 => \refresh_generation.refresh_bank_r\, + I4 => \grant_r_reg[0]_0\, + I5 => \grant_r[1]_i_3_n_0\, + O => \grant_r[1]_i_1__0_n_0\ + ); +\grant_r[1]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"04F7" + ) + port map ( + I0 => \maintenance_request.maint_grant_r\(1), + I1 => \maintenance_request.upd_last_master_r\, + I2 => \maintenance_request.new_maint_rank_r\, + I3 => last_master_r(1), + O => \grant_r[1]_i_2__0_n_0\ + ); +\grant_r[1]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF7F777FFF" + ) + port map ( + I0 => \sr_cntrl.sre_request_logic.sre_request_r\, + I1 => \grant_r_reg[0]_0\, + I2 => \maintenance_request.maint_grant_r\(1), + I3 => \maintenance_request.maint_sre_r_lcl_i_2_n_0\, + I4 => last_master_r(1), + I5 => \last_master_r_reg[2]_0\, + O => \grant_r[1]_i_3_n_0\ + ); +\grant_r[2]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"4C4C0C0000000000" + ) + port map ( + I0 => \last_master_r[0]_i_1__3_n_0\, + I1 => \grant_r_reg[0]_0\, + I2 => \zq_cntrl.zq_request_logic.zq_request_r\, + I3 => \refresh_generation.refresh_bank_r\, + I4 => \grant_r[2]_i_2__3_n_0\, + I5 => \sr_cntrl.sre_request_logic.sre_request_r\, + O => \grant_r[2]_i_1__1_n_0\ + ); +\grant_r[2]_i_2__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"10111511" + ) + port map ( + I0 => \last_master_r_reg[2]_0\, + I1 => last_master_r(2), + I2 => \maintenance_request.new_maint_rank_r\, + I3 => \maintenance_request.upd_last_master_r\, + I4 => \maintenance_request.maint_grant_r\(2), + O => \grant_r[2]_i_2__3_n_0\ + ); +\grant_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[0]_i_1__1_n_0\, + Q => \maintenance_request.maint_grant_r\(0), + R => '0' + ); +\grant_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[1]_i_1__0_n_0\, + Q => \maintenance_request.maint_grant_r\(1), + R => '0' + ); +\grant_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[2]_i_1__1_n_0\, + Q => \maintenance_request.maint_grant_r\(2), + R => '0' + ); +\last_master_r[0]_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"54550400" + ) + port map ( + I0 => \last_master_r_reg[2]_0\, + I1 => \maintenance_request.maint_grant_r\(0), + I2 => \maintenance_request.new_maint_rank_r\, + I3 => \maintenance_request.upd_last_master_r\, + I4 => last_master_r(0), + O => \last_master_r[0]_i_1__3_n_0\ + ); +\last_master_r[1]_i_1__3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"45444044" + ) + port map ( + I0 => \last_master_r_reg[2]_0\, + I1 => last_master_r(1), + I2 => \maintenance_request.new_maint_rank_r\, + I3 => \maintenance_request.upd_last_master_r\, + I4 => \maintenance_request.maint_grant_r\(1), + O => \last_master_r[1]_i_1__3_n_0\ + ); +\last_master_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFB08" + ) + port map ( + I0 => \maintenance_request.maint_grant_r\(2), + I1 => \maintenance_request.upd_last_master_r\, + I2 => \maintenance_request.new_maint_rank_r\, + I3 => last_master_r(2), + I4 => \last_master_r_reg[2]_0\, + O => \last_master_r[2]_i_1_n_0\ + ); +\last_master_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[0]_i_1__3_n_0\, + Q => last_master_r(0), + R => '0' + ); +\last_master_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[1]_i_1__3_n_0\, + Q => last_master_r(1), + R => '0' + ); +\last_master_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[2]_i_1_n_0\, + Q => last_master_r(2), + R => '0' + ); +\maintenance_request.maint_rank_r_lcl[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => maint_rank_r, + I1 => \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0\, + I2 => \maintenance_request.maint_rank_r_lcl[0]_i_3_n_0\, + I3 => \^maintenance_request.maint_sre_ns\, + O => \maintenance_request.maint_rank_r_lcl_reg[0]\ + ); +\maintenance_request.maint_rank_r_lcl[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFF005D5D5D5D" + ) + port map ( + I0 => \maintenance_request.maint_srx_r_lcl_reg\, + I1 => \maintenance_request.maint_sre_r_lcl_i_2_n_0\, + I2 => \maintenance_request.maint_grant_r\(2), + I3 => \sr_cntrl.ckesr_timer.ckesr_timer_r\, + I4 => app_sr_req, + I5 => maint_sre_r, + O => \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0\ + ); +\maintenance_request.maint_rank_r_lcl[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055035555" + ) + port map ( + I0 => \maintenance_request.maint_zq_r_lcl_reg\, + I1 => \maintenance_request.maint_grant_r\(1), + I2 => \maintenance_request.maint_grant_r\(0), + I3 => \maintenance_request.new_maint_rank_r\, + I4 => \maintenance_request.upd_last_master_r\, + I5 => \last_master_r_reg[2]_0\, + O => \maintenance_request.maint_rank_r_lcl[0]_i_3_n_0\ + ); +\maintenance_request.maint_sre_r_lcl_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000FFA800A8" + ) + port map ( + I0 => maint_sre_r, + I1 => app_sr_req, + I2 => \sr_cntrl.ckesr_timer.ckesr_timer_r\, + I3 => \maintenance_request.maint_sre_r_lcl_i_2_n_0\, + I4 => \maintenance_request.maint_grant_r\(2), + I5 => \last_master_r_reg[2]_0\, + O => \^maintenance_request.maint_sre_ns\ + ); +\maintenance_request.maint_sre_r_lcl_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \maintenance_request.upd_last_master_r\, + I1 => \maintenance_request.new_maint_rank_r\, + O => \maintenance_request.maint_sre_r_lcl_i_2_n_0\ + ); +\maintenance_request.maint_srx_r_lcl_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5702575702020202" + ) + port map ( + I0 => maint_sre_r, + I1 => app_sr_req, + I2 => \sr_cntrl.ckesr_timer.ckesr_timer_r\, + I3 => \maintenance_request.maint_grant_r\(2), + I4 => \maintenance_request.maint_sre_r_lcl_i_2_n_0\, + I5 => \maintenance_request.maint_srx_r_lcl_reg\, + O => \maintenance_request.maint_sre_r_lcl_reg\ + ); +\maintenance_request.maint_zq_r_lcl_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FB08" + ) + port map ( + I0 => \maintenance_request.maint_grant_r\(1), + I1 => \maintenance_request.upd_last_master_r\, + I2 => \maintenance_request.new_maint_rank_r\, + I3 => \maintenance_request.maint_zq_r_lcl_reg\, + O => \grant_r_reg[1]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1\ is + port ( + I121 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[3]_0\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + granted_col_r_reg : out STD_LOGIC; + \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC; + \periodic_rd_generation.read_this_rank\ : out STD_LOGIC; + granted_col_ns : out STD_LOGIC; + \last_master_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC; + \grant_r_reg[1]_0\ : out STD_LOGIC; + I119 : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_aux_out0_1 : out STD_LOGIC; + rd_wr_r_lcl_reg : out STD_LOGIC; + granted_col_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + DIC : out STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[0]_0\ : out STD_LOGIC; + \genblk3[1].rnk_config_strobe_r_reg[1]\ : out STD_LOGIC; + col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + granted_col_r_reg_1 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + granted_col_r_reg_2 : out STD_LOGIC_VECTOR ( 10 downto 0 ); + col_wait_r : in STD_LOGIC; + \grant_r_reg[0]_1\ : in STD_LOGIC; + \grant_r_reg[0]_2\ : in STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[0]\ : in STD_LOGIC; + \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC; + rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[1]_1\ : in STD_LOGIC; + \grant_r_reg[1]_2\ : in STD_LOGIC; + granted_col_r_reg_3 : in STD_LOGIC; + \grant_r_reg[2]_0\ : in STD_LOGIC; + col_wait_r_0 : in STD_LOGIC; + \grant_r_reg[2]_1\ : in STD_LOGIC; + rd_wr_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + col_wait_r_2 : in STD_LOGIC; + \grant_r_reg[3]_1\ : in STD_LOGIC; + \grant_r_reg[3]_2\ : in STD_LOGIC; + \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC; + \col_mux.col_periodic_rd_r_reg\ : in STD_LOGIC; + O : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \col_mux.col_periodic_rd_r\ : in STD_LOGIC; + col_rd_wr_r : in STD_LOGIC; + wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \genblk3[1].rnk_config_strobe_r_reg\ : in STD_LOGIC; + \genblk3[2].rnk_config_strobe_r_reg\ : in STD_LOGIC; + rnk_config_strobe : in STD_LOGIC; + \last_master_r_reg[1]_1\ : in STD_LOGIC; + req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 19 downto 0 ); + \col_mux.col_data_buf_addr_r\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[5]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[5]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + auto_pre_r : in STD_LOGIC; + auto_pre_r_7 : in STD_LOGIC; + auto_pre_r_8 : in STD_LOGIC; + auto_pre_r_9 : in STD_LOGIC; + \grant_r[3]_i_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r[3]_i_4_0\ : in STD_LOGIC; + CLK : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1\ : entity is "mig_7series_v4_2_round_robin_arb"; +end \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1\ is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \cmd_pipe_plus.mc_address[15]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[16]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[17]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[18]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[19]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[20]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[21]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[22]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[23]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[24]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[25]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[3]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[4]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[5]_i_2_n_0\ : STD_LOGIC; + signal \col_mux.col_data_buf_addr_r[4]_i_2_n_0\ : STD_LOGIC; + signal \col_mux.col_periodic_rd_r_i_2_n_0\ : STD_LOGIC; + signal \col_mux.col_rd_wr_r_i_2_n_0\ : STD_LOGIC; + signal \col_mux.col_rd_wr_r_i_3_n_0\ : STD_LOGIC; + signal \grant_r[0]_i_1_n_0\ : STD_LOGIC; + signal \grant_r[0]_i_2_n_0\ : STD_LOGIC; + signal \grant_r[0]_i_3_n_0\ : STD_LOGIC; + signal \grant_r[0]_i_4_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_1_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_3__0_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_1_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_2_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_3_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_4_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_5_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_11_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_16_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_1_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_2__1_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_3__0_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_5__0_n_0\ : STD_LOGIC; + signal \^grant_r_reg[0]_0\ : STD_LOGIC; + signal \^grant_r_reg[1]_0\ : STD_LOGIC; + signal \^grant_r_reg[3]_0\ : STD_LOGIC; + signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \last_master_r[0]_i_1_n_0\ : STD_LOGIC; + signal \last_master_r[2]_i_1__0_n_0\ : STD_LOGIC; + signal \last_master_r[3]_i_1_n_0\ : STD_LOGIC; + signal \^last_master_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \periodic_rd_generation.read_this_rank_r_i_2_n_0\ : STD_LOGIC; + signal \read_fifo.fifo_ram[0].RAM32M0_i_10_n_0\ : STD_LOGIC; + signal \read_fifo.fifo_ram[0].RAM32M0_i_11_n_0\ : STD_LOGIC; + signal \read_fifo.fifo_ram[0].RAM32M0_i_12_n_0\ : STD_LOGIC; + signal \read_fifo.fifo_ram[0].RAM32M0_i_13_n_0\ : STD_LOGIC; + signal \wtr_timer.wtr_cnt_r[1]_i_3_n_0\ : STD_LOGIC; + signal \^wtr_timer.wtr_cnt_r_reg[1]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_aux_out0[1]_i_1\ : label is "soft_lutpair494"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cmd[1]_i_1\ : label is "soft_lutpair492"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[3]_i_1\ : label is "soft_lutpair495"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_data_offset[5]_i_1\ : label is "soft_lutpair493"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_odt[0]_i_1\ : label is "soft_lutpair495"; + attribute SOFT_HLUTNM of \col_mux.col_rd_wr_r_i_1\ : label is "soft_lutpair491"; + attribute SOFT_HLUTNM of \col_mux.col_rd_wr_r_i_3\ : label is "soft_lutpair491"; + attribute SOFT_HLUTNM of \last_master_r[0]_i_1\ : label is "soft_lutpair493"; + attribute SOFT_HLUTNM of \last_master_r[1]_i_1\ : label is "soft_lutpair492"; + attribute SOFT_HLUTNM of \last_master_r[3]_i_1\ : label is "soft_lutpair494"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); + \grant_r_reg[0]_0\ <= \^grant_r_reg[0]_0\; + \grant_r_reg[1]_0\ <= \^grant_r_reg[1]_0\; + \grant_r_reg[3]_0\ <= \^grant_r_reg[3]_0\; + \last_master_r_reg[1]_0\(0) <= \^last_master_r_reg[1]_0\(0); + \wtr_timer.wtr_cnt_r_reg[1]\ <= \^wtr_timer.wtr_cnt_r_reg[1]\; +\cmd_pipe_plus.mc_address[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[15]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(0), + O => granted_col_r_reg_2(0) + ); +\cmd_pipe_plus.mc_address[15]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(0), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(0), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(0), + O => \cmd_pipe_plus.mc_address[15]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[16]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[16]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(1), + O => granted_col_r_reg_2(1) + ); +\cmd_pipe_plus.mc_address[16]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(1), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(1), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(1), + O => \cmd_pipe_plus.mc_address[16]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[17]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[17]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(2), + O => granted_col_r_reg_2(2) + ); +\cmd_pipe_plus.mc_address[17]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(2), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(2), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(2), + O => \cmd_pipe_plus.mc_address[17]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[18]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[18]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(3), + O => granted_col_r_reg_2(3) + ); +\cmd_pipe_plus.mc_address[18]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(3), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(3), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(3), + O => \cmd_pipe_plus.mc_address[18]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[19]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[19]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(4), + O => granted_col_r_reg_2(4) + ); +\cmd_pipe_plus.mc_address[19]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(4), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(4), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(4), + O => \cmd_pipe_plus.mc_address[19]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[20]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[20]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(5), + O => granted_col_r_reg_2(5) + ); +\cmd_pipe_plus.mc_address[20]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(5), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(5), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(5), + O => \cmd_pipe_plus.mc_address[20]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[21]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[21]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(6), + O => granted_col_r_reg_2(6) + ); +\cmd_pipe_plus.mc_address[21]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(6), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(6), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(6), + O => \cmd_pipe_plus.mc_address[21]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[22]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[22]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(7), + O => granted_col_r_reg_2(7) + ); +\cmd_pipe_plus.mc_address[22]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(7), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(7), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(7), + O => \cmd_pipe_plus.mc_address[22]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[23]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[23]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(8), + O => granted_col_r_reg_2(8) + ); +\cmd_pipe_plus.mc_address[23]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(8), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(8), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(8), + O => \cmd_pipe_plus.mc_address[23]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[24]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[24]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_address_reg[24]\(9), + O => granted_col_r_reg_2(9) + ); +\cmd_pipe_plus.mc_address[24]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[24]_0\(9), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_address_reg[24]_1\(9), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_address_reg[24]_2\(9), + O => \cmd_pipe_plus.mc_address[24]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[25]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[25]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => auto_pre_r, + O => granted_col_r_reg_2(10) + ); +\cmd_pipe_plus.mc_address[25]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => auto_pre_r_7, + I1 => \^q\(0), + I2 => auto_pre_r_8, + I3 => \^q\(1), + I4 => \^q\(2), + I5 => auto_pre_r_9, + O => \cmd_pipe_plus.mc_address[25]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_aux_out0[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I1 => \^grant_r_reg[3]_0\, + O => mc_aux_out0_1 + ); +\cmd_pipe_plus.mc_bank[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_bank_reg[5]\(0), + O => granted_col_r_reg_1(0) + ); +\cmd_pipe_plus.mc_bank[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(0), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_bank_reg[5]_1\(0), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(0), + O => \cmd_pipe_plus.mc_bank[3]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_bank_reg[5]\(1), + O => granted_col_r_reg_1(1) + ); +\cmd_pipe_plus.mc_bank[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(1), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_bank_reg[5]_1\(1), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(1), + O => \cmd_pipe_plus.mc_bank[4]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_bank_reg[5]\(2), + O => granted_col_r_reg_1(2) + ); +\cmd_pipe_plus.mc_bank[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank_reg[5]_0\(2), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_bank_reg[5]_1\(2), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_bank_reg[5]_2\(2), + O => \cmd_pipe_plus.mc_bank[5]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_cmd[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^grant_r_reg[3]_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + O => I121(0) + ); +\cmd_pipe_plus.mc_data_offset[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I1 => O(0), + I2 => \^grant_r_reg[3]_0\, + O => granted_col_r_reg_0(0) + ); +\cmd_pipe_plus.mc_data_offset[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => \^grant_r_reg[3]_0\, + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + O => granted_col_r_reg + ); +\cmd_pipe_plus.mc_odt[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => \cmd_pipe_plus.mc_odt_reg[0]\, + I1 => \^grant_r_reg[3]_0\, + I2 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + O => I119(0) + ); +\cmd_pipe_plus.mc_we_n[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFE0000FFFFFFFF" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(3), + I3 => \^q\(2), + I4 => \^grant_r_reg[3]_0\, + I5 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + O => D(0) + ); +\col_mux.col_data_buf_addr_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(19), + I1 => \^q\(3), + I2 => req_data_buf_addr_r(14), + I3 => \^q\(2), + I4 => \col_mux.col_data_buf_addr_r[4]_i_2_n_0\, + O => col_data_buf_addr(4) + ); +\col_mux.col_data_buf_addr_r[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(9), + I1 => \^q\(1), + I2 => req_data_buf_addr_r(4), + I3 => \^q\(0), + I4 => \col_mux.col_data_buf_addr_r\(0), + O => \col_mux.col_data_buf_addr_r[4]_i_2_n_0\ + ); +\col_mux.col_periodic_rd_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFCA00CA" + ) + port map ( + I0 => \col_mux.col_periodic_rd_r_i_2_n_0\, + I1 => req_periodic_rd_r(2), + I2 => \^q\(2), + I3 => \^q\(3), + I4 => req_periodic_rd_r(3), + O => DIC(0) + ); +\col_mux.col_periodic_rd_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAFF00AAAA3030" + ) + port map ( + I0 => req_periodic_rd_r(1), + I1 => \col_mux.col_periodic_rd_r_reg\, + I2 => \col_mux.col_periodic_rd_r\, + I3 => req_periodic_rd_r(0), + I4 => \^q\(1), + I5 => \^q\(0), + O => \col_mux.col_periodic_rd_r_i_2_n_0\ + ); +\col_mux.col_rd_wr_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AA8A2202" + ) + port map ( + I0 => \col_mux.col_rd_wr_r_i_2_n_0\, + I1 => \^q\(3), + I2 => \^q\(2), + I3 => rd_wr_r(2), + I4 => rd_wr_r(3), + O => \^grant_r_reg[3]_0\ + ); +\col_mux.col_rd_wr_r_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFAACCAAF0" + ) + port map ( + I0 => rd_wr_r(1), + I1 => rd_wr_r(0), + I2 => col_rd_wr_r, + I3 => \^q\(1), + I4 => \^q\(0), + I5 => \col_mux.col_rd_wr_r_i_3_n_0\, + O => \col_mux.col_rd_wr_r_i_2_n_0\ + ); +\col_mux.col_rd_wr_r_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(3), + O => \col_mux.col_rd_wr_r_i_3_n_0\ + ); +\grant_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000044CC00C0" + ) + port map ( + I0 => \last_master_r[2]_i_1__0_n_0\, + I1 => \grant_r[0]_i_2_n_0\, + I2 => granted_col_r_reg_3, + I3 => \grant_r_reg[1]_2\, + I4 => \grant_r[0]_i_3_n_0\, + I5 => \grant_r[2]_i_3_n_0\, + O => \grant_r[0]_i_1_n_0\ + ); +\grant_r[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFF1FFFF" + ) + port map ( + I0 => col_wait_r, + I1 => \grant_r_reg[0]_1\, + I2 => \grant_r[0]_i_4_n_0\, + I3 => \grant_r_reg[0]_2\, + I4 => \last_master_r[0]_i_1_n_0\, + O => \grant_r[0]_i_2_n_0\ + ); +\grant_r[0]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0F5F0F0F0F5F3F3" + ) + port map ( + I0 => \^q\(1), + I1 => last_master_r(1), + I2 => \last_master_r_reg[1]_1\, + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I5 => last_master_r(0), + O => \grant_r[0]_i_3_n_0\ + ); +\grant_r[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"888888B8" + ) + port map ( + I0 => \^wtr_timer.wtr_cnt_r_reg[1]\, + I1 => rd_wr_r(1), + I2 => \^grant_r_reg[3]_0\, + I3 => \grant_r[3]_i_16_n_0\, + I4 => \col_mux.col_periodic_rd_r_reg\, + O => \grant_r[0]_i_4_n_0\ + ); +\grant_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000C4C400C0" + ) + port map ( + I0 => \last_master_r[3]_i_1_n_0\, + I1 => \grant_r_reg[1]_1\, + I2 => \grant_r[2]_i_3_n_0\, + I3 => \grant_r_reg[1]_2\, + I4 => \grant_r[1]_i_3__0_n_0\, + I5 => \grant_r[3]_i_3__0_n_0\, + O => \grant_r[1]_i_1_n_0\ + ); +\grant_r[1]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0F5F0F0F0F5F3F3" + ) + port map ( + I0 => \^q\(1), + I1 => last_master_r(1), + I2 => \last_master_r_reg[1]_1\, + I3 => \^q\(2), + I4 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I5 => last_master_r(2), + O => \grant_r[1]_i_3__0_n_0\ + ); +\grant_r[1]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"888888B8" + ) + port map ( + I0 => \^wtr_timer.wtr_cnt_r_reg[1]\, + I1 => rd_wr_r(2), + I2 => \^grant_r_reg[3]_0\, + I3 => \grant_r[3]_i_16_n_0\, + I4 => \col_mux.col_periodic_rd_r_reg\, + O => rd_wr_r_lcl_reg + ); +\grant_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000055115000" + ) + port map ( + I0 => \grant_r[2]_i_2_n_0\, + I1 => \last_master_r[0]_i_1_n_0\, + I2 => \grant_r[2]_i_3_n_0\, + I3 => \grant_r[3]_i_3__0_n_0\, + I4 => \grant_r[2]_i_4_n_0\, + I5 => granted_col_r_reg_3, + O => \grant_r[2]_i_1_n_0\ + ); +\grant_r[2]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"02020200" + ) + port map ( + I0 => \last_master_r[2]_i_1__0_n_0\, + I1 => \grant_r_reg[2]_0\, + I2 => \grant_r[2]_i_5_n_0\, + I3 => col_wait_r_0, + I4 => \grant_r_reg[2]_1\, + O => \grant_r[2]_i_2_n_0\ + ); +\grant_r[2]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEAEFEAEFEAFFFF" + ) + port map ( + I0 => \grant_r_reg[3]_2\, + I1 => \^wtr_timer.wtr_cnt_r_reg[1]\, + I2 => rd_wr_r(0), + I3 => \^grant_r_reg[1]_0\, + I4 => \grant_r_reg[3]_1\, + I5 => col_wait_r_2, + O => \grant_r[2]_i_3_n_0\ + ); +\grant_r[2]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0005000000050303" + ) + port map ( + I0 => \^q\(3), + I1 => last_master_r(3), + I2 => \last_master_r_reg[1]_1\, + I3 => \^q\(2), + I4 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I5 => last_master_r(2), + O => \grant_r[2]_i_4_n_0\ + ); +\grant_r[2]_i_5\: unisim.vcomponents.LUT5 + generic map( + INIT => X"888888B8" + ) + port map ( + I0 => \^wtr_timer.wtr_cnt_r_reg[1]\, + I1 => rd_wr_r(3), + I2 => \^grant_r_reg[3]_0\, + I3 => \grant_r[3]_i_16_n_0\, + I4 => \col_mux.col_periodic_rd_r_reg\, + O => \grant_r[2]_i_5_n_0\ + ); +\grant_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000DD0500000000" + ) + port map ( + I0 => \grant_r[3]_i_2__1_n_0\, + I1 => \grant_r[3]_i_3__0_n_0\, + I2 => \^last_master_r_reg[1]_0\(0), + I3 => granted_col_r_reg_3, + I4 => \grant_r[3]_i_5__0_n_0\, + I5 => \grant_r_reg[1]_2\, + O => \grant_r[3]_i_1_n_0\ + ); +\grant_r[3]_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"888888B8" + ) + port map ( + I0 => \^wtr_timer.wtr_cnt_r_reg[1]\, + I1 => rd_wr_r(0), + I2 => \^grant_r_reg[3]_0\, + I3 => \grant_r[3]_i_16_n_0\, + I4 => \col_mux.col_periodic_rd_r_reg\, + O => \grant_r[3]_i_11_n_0\ + ); +\grant_r[3]_i_16\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(3), + I3 => \^q\(2), + O => \grant_r[3]_i_16_n_0\ + ); +\grant_r[3]_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFAFFFACC" + ) + port map ( + I0 => \^q\(0), + I1 => last_master_r(0), + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I4 => last_master_r(3), + I5 => \last_master_r_reg[1]_1\, + O => \grant_r[3]_i_2__1_n_0\ + ); +\grant_r[3]_i_3__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EFEAEFEAEFEAFFFF" + ) + port map ( + I0 => \grant_r_reg[0]_2\, + I1 => \^wtr_timer.wtr_cnt_r_reg[1]\, + I2 => rd_wr_r(1), + I3 => \^grant_r_reg[1]_0\, + I4 => \grant_r_reg[0]_1\, + I5 => col_wait_r, + O => \grant_r[3]_i_3__0_n_0\ + ); +\grant_r[3]_i_5__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000000A8" + ) + port map ( + I0 => \last_master_r[3]_i_1_n_0\, + I1 => col_wait_r_2, + I2 => \grant_r_reg[3]_1\, + I3 => \grant_r[3]_i_11_n_0\, + I4 => \grant_r_reg[3]_2\, + O => \grant_r[3]_i_5__0_n_0\ + ); +\grant_r[3]_i_8__1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"0D" + ) + port map ( + I0 => \^grant_r_reg[0]_0\, + I1 => \grant_r[3]_i_4\(0), + I2 => \grant_r[3]_i_4_0\, + O => \^wtr_timer.wtr_cnt_r_reg[1]\ + ); +\grant_r[3]_i_9\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000AAAAAAA8" + ) + port map ( + I0 => \^grant_r_reg[3]_0\, + I1 => \^q\(1), + I2 => \^q\(0), + I3 => \^q\(3), + I4 => \^q\(2), + I5 => \col_mux.col_periodic_rd_r_reg\, + O => \^grant_r_reg[1]_0\ + ); +\grant_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[0]_i_1_n_0\, + Q => \^q\(0), + R => '0' + ); +\grant_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[1]_i_1_n_0\, + Q => \^q\(1), + R => '0' + ); +\grant_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[2]_i_1_n_0\, + Q => \^q\(2), + R => '0' + ); +\grant_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[3]_i_1_n_0\, + Q => \^q\(3), + R => '0' + ); +granted_col_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF7F" + ) + port map ( + I0 => granted_col_r_reg_3, + I1 => \grant_r[3]_i_3__0_n_0\, + I2 => \grant_r[2]_i_3_n_0\, + I3 => \grant_r_reg[1]_2\, + O => granted_col_ns + ); +\last_master_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(0), + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(0), + I3 => \last_master_r_reg[1]_1\, + O => \last_master_r[0]_i_1_n_0\ + ); +\last_master_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(1), + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(1), + I3 => \last_master_r_reg[1]_1\, + O => \^last_master_r_reg[1]_0\(0) + ); +\last_master_r[2]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(2), + I1 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I2 => \^q\(2), + I3 => \last_master_r_reg[1]_1\, + O => \last_master_r[2]_i_1__0_n_0\ + ); +\last_master_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAE" + ) + port map ( + I0 => \last_master_r_reg[1]_1\, + I1 => last_master_r(3), + I2 => \cmd_pipe_plus.mc_data_offset_reg[0]\, + I3 => \^q\(3), + O => \last_master_r[3]_i_1_n_0\ + ); +\last_master_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[0]_i_1_n_0\, + Q => last_master_r(0), + R => '0' + ); +\last_master_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^last_master_r_reg[1]_0\(0), + Q => last_master_r(1), + R => '0' + ); +\last_master_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[2]_i_1__0_n_0\, + Q => last_master_r(2), + R => '0' + ); +\last_master_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[3]_i_1_n_0\, + Q => last_master_r(3), + R => '0' + ); +override_demand_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => \genblk3[1].rnk_config_strobe_r_reg\, + I1 => \genblk3[2].rnk_config_strobe_r_reg\, + I2 => rnk_config_strobe, + O => \genblk3[1].rnk_config_strobe_r_reg[1]\ + ); +\periodic_rd_generation.periodic_rd_timer_r[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAA888A888A888" + ) + port map ( + I0 => \periodic_rd_generation.read_this_rank_r\, + I1 => \periodic_rd_generation.read_this_rank_r_i_2_n_0\, + I2 => rd_this_rank_r(2), + I3 => \^q\(2), + I4 => rd_this_rank_r(0), + I5 => \^q\(0), + O => \periodic_rd_generation.read_this_rank_r_reg\ + ); +\periodic_rd_generation.read_this_rank_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFEAEAEA" + ) + port map ( + I0 => \periodic_rd_generation.read_this_rank_r_i_2_n_0\, + I1 => rd_this_rank_r(2), + I2 => \^q\(2), + I3 => rd_this_rank_r(0), + I4 => \^q\(0), + O => \periodic_rd_generation.read_this_rank\ + ); +\periodic_rd_generation.read_this_rank_r_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => rd_this_rank_r(3), + I1 => \^q\(3), + I2 => rd_this_rank_r(1), + I3 => \^q\(1), + O => \periodic_rd_generation.read_this_rank_r_i_2_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(18), + I1 => \^q\(3), + I2 => req_data_buf_addr_r(13), + I3 => \^q\(2), + I4 => \read_fifo.fifo_ram[0].RAM32M0_i_10_n_0\, + O => col_data_buf_addr(3) + ); +\read_fifo.fifo_ram[0].RAM32M0_i_10\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(8), + I1 => \^q\(1), + I2 => req_data_buf_addr_r(3), + I3 => \^q\(0), + I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3), + O => \read_fifo.fifo_ram[0].RAM32M0_i_10_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(7), + I1 => \^q\(1), + I2 => req_data_buf_addr_r(2), + I3 => \^q\(0), + I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(2), + O => \read_fifo.fifo_ram[0].RAM32M0_i_11_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_12\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(6), + I1 => \^q\(1), + I2 => req_data_buf_addr_r(1), + I3 => \^q\(0), + I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(1), + O => \read_fifo.fifo_ram[0].RAM32M0_i_12_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_13\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(5), + I1 => \^q\(1), + I2 => req_data_buf_addr_r(0), + I3 => \^q\(0), + I4 => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(0), + O => \read_fifo.fifo_ram[0].RAM32M0_i_13_n_0\ + ); +\read_fifo.fifo_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(17), + I1 => \^q\(3), + I2 => req_data_buf_addr_r(12), + I3 => \^q\(2), + I4 => \read_fifo.fifo_ram[0].RAM32M0_i_11_n_0\, + O => col_data_buf_addr(2) + ); +\read_fifo.fifo_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(16), + I1 => \^q\(3), + I2 => req_data_buf_addr_r(11), + I3 => \^q\(2), + I4 => \read_fifo.fifo_ram[0].RAM32M0_i_12_n_0\, + O => col_data_buf_addr(1) + ); +\read_fifo.fifo_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"B8BBB888" + ) + port map ( + I0 => req_data_buf_addr_r(15), + I1 => \^q\(3), + I2 => req_data_buf_addr_r(10), + I3 => \^q\(2), + I4 => \read_fifo.fifo_ram[0].RAM32M0_i_13_n_0\, + O => col_data_buf_addr(0) + ); +\wtr_timer.wtr_cnt_r[1]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000777" + ) + port map ( + I0 => \^q\(0), + I1 => wr_this_rank_r(0), + I2 => \^q\(3), + I3 => wr_this_rank_r(3), + I4 => \wtr_timer.wtr_cnt_r[1]_i_3_n_0\, + O => \^grant_r_reg[0]_0\ + ); +\wtr_timer.wtr_cnt_r[1]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => wr_this_rank_r(1), + I1 => \^q\(1), + I2 => wr_this_rank_r(2), + I3 => \^q\(2), + O => \wtr_timer.wtr_cnt_r[1]_i_3_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_3\ is + port ( + \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC; + ofs_rdy_r_reg : out STD_LOGIC; + ofs_rdy_r_reg_0 : out STD_LOGIC; + ofs_rdy_r_reg_1 : out STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : out STD_LOGIC; + rnk_config_0 : out STD_LOGIC; + rnk_config_strobe : in STD_LOGIC; + rnk_config_valid_r : in STD_LOGIC; + \grant_r_reg[0]_0\ : in STD_LOGIC; + \grant_r_reg[0]_1\ : in STD_LOGIC; + \grant_r_reg[2]_0\ : in STD_LOGIC; + \grant_r_reg[0]_2\ : in STD_LOGIC; + \grant_r[3]_i_6\ : in STD_LOGIC; + \grant_r[2]_i_3\ : in STD_LOGIC; + ofs_rdy_r : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \grant_r[3]_i_6_0\ : in STD_LOGIC; + \grant_r[3]_i_3__0\ : in STD_LOGIC; + ofs_rdy_r_1 : in STD_LOGIC; + \grant_r[3]_i_3__0_0\ : in STD_LOGIC; + \grant_r[2]_i_3_0\ : in STD_LOGIC; + ofs_rdy_r_3 : in STD_LOGIC; + \grant_r[2]_i_3_1\ : in STD_LOGIC; + \genblk3[2].rnk_config_strobe_r_reg\ : in STD_LOGIC; + \genblk3[1].rnk_config_strobe_r_reg\ : in STD_LOGIC; + rnk_config_r : in STD_LOGIC; + \rnk_config_r_reg[0]\ : in STD_LOGIC; + \last_master_r_reg[1]_0\ : in STD_LOGIC; + CLK : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_3\ : entity is "mig_7series_v4_2_round_robin_arb"; +end \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_3\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_3\ is + signal grant_config_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \grant_r[0]_i_1__0_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_1__2_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_1__0_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_2__0_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_4__0_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_1__1_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_4__0_n_0\ : STD_LOGIC; + signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \last_master_r[0]_i_1__0_n_0\ : STD_LOGIC; + signal \last_master_r[1]_i_1__0_n_0\ : STD_LOGIC; + signal \last_master_r[2]_i_1__1_n_0\ : STD_LOGIC; + signal \last_master_r[3]_i_1__0_n_0\ : STD_LOGIC; + signal \rnk_config_r[0]_i_2_n_0\ : STD_LOGIC; + signal \^rnk_config_strobe_r_reg[0]\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \grant_r[2]_i_4__0\ : label is "soft_lutpair496"; + attribute SOFT_HLUTNM of \rnk_config_r[0]_i_2\ : label is "soft_lutpair496"; +begin + \rnk_config_strobe_r_reg[0]\ <= \^rnk_config_strobe_r_reg[0]\; +\grant_r[0]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0202AA0200000000" + ) + port map ( + I0 => \grant_r[2]_i_2__0_n_0\, + I1 => \last_master_r[0]_i_1__0_n_0\, + I2 => \last_master_r[1]_i_1__0_n_0\, + I3 => \grant_r_reg[0]_2\, + I4 => \grant_r_reg[0]_0\, + I5 => \grant_r_reg[0]_1\, + O => \grant_r[0]_i_1__0_n_0\ + ); +\grant_r[1]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"100010001000F000" + ) + port map ( + I0 => \grant_r_reg[0]_0\, + I1 => \grant_r_reg[0]_1\, + I2 => \grant_r[3]_i_4__0_n_0\, + I3 => \grant_r_reg[2]_0\, + I4 => \last_master_r[2]_i_1__1_n_0\, + I5 => \last_master_r[1]_i_1__0_n_0\, + O => \grant_r[1]_i_1__2_n_0\ + ); +\grant_r[2]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000020202AA" + ) + port map ( + I0 => \grant_r[2]_i_2__0_n_0\, + I1 => \grant_r_reg[0]_1\, + I2 => \grant_r_reg[2]_0\, + I3 => \grant_r[2]_i_4__0_n_0\, + I4 => \last_master_r[3]_i_1__0_n_0\, + I5 => \grant_r_reg[0]_2\, + O => \grant_r[2]_i_1__0_n_0\ + ); +\grant_r[2]_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0777" + ) + port map ( + I0 => \grant_r_reg[2]_0\, + I1 => \last_master_r[0]_i_1__0_n_0\, + I2 => \grant_r_reg[0]_0\, + I3 => \last_master_r[2]_i_1__1_n_0\, + O => \grant_r[2]_i_2__0_n_0\ + ); +\grant_r[2]_i_4__0\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => grant_config_r(2), + I1 => rnk_config_strobe, + I2 => last_master_r(2), + O => \grant_r[2]_i_4__0_n_0\ + ); +\grant_r[3]_i_10__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"11111115FFFFFFFF" + ) + port map ( + I0 => \rnk_config_r[0]_i_2_n_0\, + I1 => rnk_config_strobe, + I2 => grant_config_r(0), + I3 => grant_config_r(3), + I4 => grant_config_r(1), + I5 => rnk_config_valid_r, + O => \^rnk_config_strobe_r_reg[0]\ + ); +\grant_r[3]_i_12\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEFF" + ) + port map ( + I0 => \grant_r[2]_i_3_0\, + I1 => \^rnk_config_strobe_r_reg[0]\, + I2 => \grant_r[2]_i_3\, + I3 => ofs_rdy_r_3, + I4 => Q(0), + I5 => \grant_r[2]_i_3_1\, + O => ofs_rdy_r_reg_1 + ); +\grant_r[3]_i_13\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEFF" + ) + port map ( + I0 => \grant_r[3]_i_6\, + I1 => \^rnk_config_strobe_r_reg[0]\, + I2 => \grant_r[2]_i_3\, + I3 => ofs_rdy_r, + I4 => Q(2), + I5 => \grant_r[3]_i_6_0\, + O => ofs_rdy_r_reg + ); +\grant_r[3]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"444F000000000000" + ) + port map ( + I0 => \grant_r_reg[2]_0\, + I1 => \grant_r_reg[0]_2\, + I2 => \last_master_r[0]_i_1__0_n_0\, + I3 => \last_master_r[3]_i_1__0_n_0\, + I4 => \grant_r[3]_i_4__0_n_0\, + I5 => \grant_r_reg[0]_0\, + O => \grant_r[3]_i_1__1_n_0\ + ); +\grant_r[3]_i_4__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0DDD" + ) + port map ( + I0 => \last_master_r[1]_i_1__0_n_0\, + I1 => \grant_r_reg[0]_2\, + I2 => \grant_r_reg[0]_1\, + I3 => \last_master_r[3]_i_1__0_n_0\, + O => \grant_r[3]_i_4__0_n_0\ + ); +\grant_r[3]_i_7\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFEFF" + ) + port map ( + I0 => \grant_r[3]_i_3__0\, + I1 => \^rnk_config_strobe_r_reg[0]\, + I2 => \grant_r[2]_i_3\, + I3 => ofs_rdy_r_1, + I4 => Q(1), + I5 => \grant_r[3]_i_3__0_0\, + O => ofs_rdy_r_reg_0 + ); +\grant_r[3]_i_7__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEFF" + ) + port map ( + I0 => rnk_config_strobe, + I1 => \genblk3[2].rnk_config_strobe_r_reg\, + I2 => \genblk3[1].rnk_config_strobe_r_reg\, + I3 => \^rnk_config_strobe_r_reg[0]\, + O => \rnk_config_strobe_r_reg[0]_0\ + ); +\grant_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[0]_i_1__0_n_0\, + Q => grant_config_r(0), + R => '0' + ); +\grant_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[1]_i_1__2_n_0\, + Q => grant_config_r(1), + R => '0' + ); +\grant_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[2]_i_1__0_n_0\, + Q => grant_config_r(2), + R => '0' + ); +\grant_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[3]_i_1__1_n_0\, + Q => grant_config_r(3), + R => '0' + ); +\last_master_r[0]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(0), + I1 => rnk_config_strobe, + I2 => grant_config_r(0), + I3 => \last_master_r_reg[1]_0\, + O => \last_master_r[0]_i_1__0_n_0\ + ); +\last_master_r[1]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(1), + I1 => rnk_config_strobe, + I2 => grant_config_r(1), + I3 => \last_master_r_reg[1]_0\, + O => \last_master_r[1]_i_1__0_n_0\ + ); +\last_master_r[2]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(2), + I1 => rnk_config_strobe, + I2 => grant_config_r(2), + I3 => \last_master_r_reg[1]_0\, + O => \last_master_r[2]_i_1__1_n_0\ + ); +\last_master_r[3]_i_1__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAE" + ) + port map ( + I0 => \last_master_r_reg[1]_0\, + I1 => last_master_r(3), + I2 => rnk_config_strobe, + I3 => grant_config_r(3), + O => \last_master_r[3]_i_1__0_n_0\ + ); +\last_master_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[0]_i_1__0_n_0\, + Q => last_master_r(0), + R => '0' + ); +\last_master_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[1]_i_1__0_n_0\, + Q => last_master_r(1), + R => '0' + ); +\last_master_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[2]_i_1__1_n_0\, + Q => last_master_r(2), + R => '0' + ); +\last_master_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[3]_i_1__0_n_0\, + Q => last_master_r(3), + R => '0' + ); +\rnk_config_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000001FF" + ) + port map ( + I0 => grant_config_r(1), + I1 => grant_config_r(3), + I2 => grant_config_r(0), + I3 => rnk_config_strobe, + I4 => \rnk_config_r[0]_i_2_n_0\, + O => rnk_config_0 + ); +\rnk_config_r[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FDDD" + ) + port map ( + I0 => rnk_config_r, + I1 => \rnk_config_r_reg[0]\, + I2 => grant_config_r(2), + I3 => rnk_config_strobe, + O => \rnk_config_r[0]_i_2_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_4\ is + port ( + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + \last_master_r_reg[1]_0\ : in STD_LOGIC; + cs_en2 : in STD_LOGIC; + \grant_r_reg[0]_0\ : in STD_LOGIC; + \grant_r_reg[0]_1\ : in STD_LOGIC; + \grant_r_reg[0]_2\ : in STD_LOGIC; + \grant_r_reg[1]_0\ : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[40]\ : in STD_LOGIC; + req_row_r : in STD_LOGIC_VECTOR ( 42 downto 0 ); + row_cmd_wr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_address_reg[44]\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[8]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[8]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[8]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + CLK : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_4\ : entity is "mig_7series_v4_2_round_robin_arb"; +end \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_4\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_4\ is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \cmd_pipe_plus.mc_address[30]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[31]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[32]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[33]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[34]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[35]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[36]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[37]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[38]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[39]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[40]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[41]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[42]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[43]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[44]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[6]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[7]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[8]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\ : STD_LOGIC; + signal \grant_r[0]_i_1__3_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_1__1_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_1__3_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_2__2_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_1__0_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_2__2_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_5__1_n_0\ : STD_LOGIC; + signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \last_master_r[0]_i_1__2_n_0\ : STD_LOGIC; + signal \last_master_r[1]_i_1__2_n_0\ : STD_LOGIC; + signal \last_master_r[2]_i_1__3_n_0\ : STD_LOGIC; + signal \last_master_r[3]_i_1__2_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \grant_r[3]_i_2__2\ : label is "soft_lutpair497"; + attribute SOFT_HLUTNM of \last_master_r[3]_i_1__2\ : label is "soft_lutpair497"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); +\cmd_pipe_plus.mc_address[30]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[30]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(28), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(0) + ); +\cmd_pipe_plus.mc_address[30]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(0), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(0), + I4 => \^q\(2), + I5 => req_row_r(14), + O => \cmd_pipe_plus.mc_address[30]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[31]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[31]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(29), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(1) + ); +\cmd_pipe_plus.mc_address[31]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(1), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(1), + I4 => \^q\(2), + I5 => req_row_r(15), + O => \cmd_pipe_plus.mc_address[31]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[32]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[32]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(30), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(2) + ); +\cmd_pipe_plus.mc_address[32]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(2), + I4 => \^q\(2), + I5 => req_row_r(16), + O => \cmd_pipe_plus.mc_address[32]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[33]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[33]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(31), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(3) + ); +\cmd_pipe_plus.mc_address[33]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(3), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(3), + I4 => \^q\(2), + I5 => req_row_r(17), + O => \cmd_pipe_plus.mc_address[33]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[34]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[34]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(32), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(4) + ); +\cmd_pipe_plus.mc_address[34]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(4), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(4), + I4 => \^q\(2), + I5 => req_row_r(18), + O => \cmd_pipe_plus.mc_address[34]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[35]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[35]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(33), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(5) + ); +\cmd_pipe_plus.mc_address[35]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(5), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(5), + I4 => \^q\(2), + I5 => req_row_r(19), + O => \cmd_pipe_plus.mc_address[35]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[36]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[36]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(34), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(6) + ); +\cmd_pipe_plus.mc_address[36]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(6), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(6), + I4 => \^q\(2), + I5 => req_row_r(20), + O => \cmd_pipe_plus.mc_address[36]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[37]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[37]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(35), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(7) + ); +\cmd_pipe_plus.mc_address[37]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(7), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(7), + I4 => \^q\(2), + I5 => req_row_r(21), + O => \cmd_pipe_plus.mc_address[37]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[38]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[38]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(36), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(8) + ); +\cmd_pipe_plus.mc_address[38]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(8), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(8), + I4 => \^q\(2), + I5 => req_row_r(22), + O => \cmd_pipe_plus.mc_address[38]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[39]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[39]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(37), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(9) + ); +\cmd_pipe_plus.mc_address[39]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(9), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(9), + I4 => \^q\(2), + I5 => req_row_r(23), + O => \cmd_pipe_plus.mc_address[39]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[40]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FF0FDFDF0F0FDFDF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[40]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address_reg[40]\, + I2 => cs_en2, + I3 => req_row_r(38), + I4 => \^q\(3), + I5 => row_cmd_wr(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(10) + ); +\cmd_pipe_plus.mc_address[40]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFF7F" + ) + port map ( + I0 => row_cmd_wr(0), + I1 => \cmd_pipe_plus.mc_address_reg[44]\(10), + I2 => \^q\(0), + I3 => \^q\(1), + I4 => \^q\(2), + O => \cmd_pipe_plus.mc_address[40]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[41]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[41]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(39), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(11) + ); +\cmd_pipe_plus.mc_address[41]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(11), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(10), + I4 => \^q\(2), + I5 => req_row_r(24), + O => \cmd_pipe_plus.mc_address[41]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[42]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[42]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(40), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(12) + ); +\cmd_pipe_plus.mc_address[42]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(12), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(11), + I4 => \^q\(2), + I5 => req_row_r(25), + O => \cmd_pipe_plus.mc_address[42]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[43]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[43]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(41), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(13) + ); +\cmd_pipe_plus.mc_address[43]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(13), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(12), + I4 => \^q\(2), + I5 => req_row_r(26), + O => \cmd_pipe_plus.mc_address[43]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[44]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[44]_i_2_n_0\, + I1 => cs_en2, + I2 => req_row_r(42), + I3 => \^q\(3), + O => \pre_4_1_1T_arb.granted_pre_r_reg\(14) + ); +\cmd_pipe_plus.mc_address[44]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000007F7FFFF07F7" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[44]\(14), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => req_row_r(13), + I4 => \^q\(2), + I5 => req_row_r(27), + O => \cmd_pipe_plus.mc_address[44]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\, + I1 => cs_en2, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_bank_reg[8]\(0), + O => \pre_4_1_1T_arb.granted_pre_r_reg_0\(0) + ); +\cmd_pipe_plus.mc_bank[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank_reg[8]_0\(0), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_bank_reg[8]_1\(0), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_bank_reg[8]_2\(0), + O => \cmd_pipe_plus.mc_bank[6]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\, + I1 => cs_en2, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_bank_reg[8]\(1), + O => \pre_4_1_1T_arb.granted_pre_r_reg_0\(1) + ); +\cmd_pipe_plus.mc_bank[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank_reg[8]_0\(1), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_bank_reg[8]_1\(1), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_bank_reg[8]_2\(1), + O => \cmd_pipe_plus.mc_bank[7]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F737" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\, + I1 => cs_en2, + I2 => \^q\(3), + I3 => \cmd_pipe_plus.mc_bank_reg[8]\(2), + O => \pre_4_1_1T_arb.granted_pre_r_reg_0\(2) + ); +\cmd_pipe_plus.mc_bank[8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank_reg[8]_0\(2), + I1 => \^q\(0), + I2 => \cmd_pipe_plus.mc_bank_reg[8]_1\(2), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => \cmd_pipe_plus.mc_bank_reg[8]_2\(2), + O => \cmd_pipe_plus.mc_bank[8]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_cas_n[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFD" + ) + port map ( + I0 => cs_en2, + I1 => \^q\(3), + I2 => \^q\(1), + I3 => \^q\(2), + I4 => \^q\(0), + O => mc_cas_n_ns(0) + ); +\cmd_pipe_plus.mc_we_n[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F377" + ) + port map ( + I0 => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\, + I1 => cs_en2, + I2 => row_cmd_wr(3), + I3 => \^q\(3), + O => D(0) + ); +\cmd_pipe_plus.mc_we_n[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000F77FFFF0F77" + ) + port map ( + I0 => row_cmd_wr(0), + I1 => \^q\(0), + I2 => row_cmd_wr(1), + I3 => \^q\(1), + I4 => \^q\(2), + I5 => row_cmd_wr(2), + O => \cmd_pipe_plus.mc_we_n[2]_i_2_n_0\ + ); +\grant_r[0]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"020202AA00000000" + ) + port map ( + I0 => \grant_r[2]_i_2__2_n_0\, + I1 => \last_master_r[0]_i_1__2_n_0\, + I2 => \last_master_r[1]_i_1__2_n_0\, + I3 => \grant_r_reg[0]_0\, + I4 => \grant_r_reg[0]_1\, + I5 => \grant_r_reg[0]_2\, + O => \grant_r[0]_i_1__3_n_0\ + ); +\grant_r[1]_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"020202AA00000000" + ) + port map ( + I0 => \grant_r[3]_i_5__1_n_0\, + I1 => \last_master_r[2]_i_1__3_n_0\, + I2 => \last_master_r[1]_i_1__2_n_0\, + I3 => \grant_r_reg[0]_2\, + I4 => \grant_r_reg[0]_0\, + I5 => \grant_r_reg[1]_0\, + O => \grant_r[1]_i_1__1_n_0\ + ); +\grant_r[2]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"202020AA00000000" + ) + port map ( + I0 => \grant_r[2]_i_2__2_n_0\, + I1 => \last_master_r[2]_i_1__3_n_0\, + I2 => \grant_r[3]_i_2__2_n_0\, + I3 => \grant_r_reg[0]_2\, + I4 => \grant_r_reg[1]_0\, + I5 => \grant_r_reg[0]_1\, + O => \grant_r[2]_i_1__3_n_0\ + ); +\grant_r[2]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0777" + ) + port map ( + I0 => \grant_r_reg[1]_0\, + I1 => \last_master_r[0]_i_1__2_n_0\, + I2 => \grant_r_reg[0]_0\, + I3 => \last_master_r[2]_i_1__3_n_0\, + O => \grant_r[2]_i_2__2_n_0\ + ); +\grant_r[3]_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"222F000000000000" + ) + port map ( + I0 => \grant_r[3]_i_2__2_n_0\, + I1 => \last_master_r[0]_i_1__2_n_0\, + I2 => \grant_r_reg[0]_1\, + I3 => \grant_r_reg[1]_0\, + I4 => \grant_r[3]_i_5__1_n_0\, + I5 => \grant_r_reg[0]_0\, + O => \grant_r[3]_i_1__0_n_0\ + ); +\grant_r[3]_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0151" + ) + port map ( + I0 => \last_master_r_reg[1]_0\, + I1 => last_master_r(3), + I2 => cs_en2, + I3 => \^q\(3), + O => \grant_r[3]_i_2__2_n_0\ + ); +\grant_r[3]_i_5__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7077" + ) + port map ( + I0 => \grant_r_reg[0]_1\, + I1 => \last_master_r[1]_i_1__2_n_0\, + I2 => \grant_r[3]_i_2__2_n_0\, + I3 => \grant_r_reg[0]_2\, + O => \grant_r[3]_i_5__1_n_0\ + ); +\grant_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[0]_i_1__3_n_0\, + Q => \^q\(0), + R => '0' + ); +\grant_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[1]_i_1__1_n_0\, + Q => \^q\(1), + R => '0' + ); +\grant_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[2]_i_1__3_n_0\, + Q => \^q\(2), + R => '0' + ); +\grant_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[3]_i_1__0_n_0\, + Q => \^q\(3), + R => '0' + ); +\last_master_r[0]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(0), + I1 => cs_en2, + I2 => \^q\(0), + I3 => \last_master_r_reg[1]_0\, + O => \last_master_r[0]_i_1__2_n_0\ + ); +\last_master_r[1]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(1), + I1 => cs_en2, + I2 => \^q\(1), + I3 => \last_master_r_reg[1]_0\, + O => \last_master_r[1]_i_1__2_n_0\ + ); +\last_master_r[2]_i_1__3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(2), + I1 => cs_en2, + I2 => \^q\(2), + I3 => \last_master_r_reg[1]_0\, + O => \last_master_r[2]_i_1__3_n_0\ + ); +\last_master_r[3]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFB8" + ) + port map ( + I0 => \^q\(3), + I1 => cs_en2, + I2 => last_master_r(3), + I3 => \last_master_r_reg[1]_0\, + O => \last_master_r[3]_i_1__2_n_0\ + ); +\last_master_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[0]_i_1__2_n_0\, + Q => last_master_r(0), + R => '0' + ); +\last_master_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[1]_i_1__2_n_0\, + Q => last_master_r(1), + R => '0' + ); +\last_master_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[2]_i_1__3_n_0\, + Q => last_master_r(2), + R => '0' + ); +\last_master_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[3]_i_1__2_n_0\, + Q => last_master_r(3), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_5\ is + port ( + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[3]_0\ : out STD_LOGIC; + granted_row_ns : out STD_LOGIC; + mc_cas_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_ras_n_ns : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + act_this_rank : out STD_LOGIC; + insert_maint_r1_lcl_reg : out STD_LOGIC_VECTOR ( 2 downto 0 ); + demand_act_priority_r : in STD_LOGIC; + granted_row_r_reg : in STD_LOGIC; + granted_row_r_reg_0 : in STD_LOGIC; + demand_act_priority_r_4 : in STD_LOGIC; + \grant_r_reg[3]_1\ : in STD_LOGIC; + \grant_r_reg[3]_2\ : in STD_LOGIC; + demand_act_priority_r_5 : in STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[0]\ : in STD_LOGIC; + \grant_r_reg[3]_3\ : in STD_LOGIC; + demand_act_priority_r_6 : in STD_LOGIC; + \grant_r_reg[3]_4\ : in STD_LOGIC; + \grant_r_reg[3]_5\ : in STD_LOGIC; + \cmd_pipe_plus.mc_cas_n_reg[0]\ : in STD_LOGIC; + \cmd_pipe_plus.mc_ras_n_reg[0]\ : in STD_LOGIC; + maint_zq_r : in STD_LOGIC; + maint_srx_r : in STD_LOGIC; + \cmd_pipe_plus.mc_bank_reg[2]\ : in STD_LOGIC; + sent_row : in STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[0]_0\ : in STD_LOGIC; + row_cmd_wr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r[2]_i_3__1_0\ : in STD_LOGIC; + inhbt_act_faw_r : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC; + req_row_r : in STD_LOGIC_VECTOR ( 42 downto 0 ); + \last_master_r_reg[0]_0\ : in STD_LOGIC; + act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_address_reg[14]\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + CLK : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_5\ : entity is "mig_7series_v4_2_round_robin_arb"; +end \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_5\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_5\ is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \cmd_pipe_plus.mc_address[0]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[10]_i_3_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[11]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[12]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[13]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[14]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[14]_i_3_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[1]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[2]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[3]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[4]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[5]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[6]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[7]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[8]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_address[9]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[0]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[1]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_bank[2]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_we_n[0]_i_4_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_we_n[0]_i_5_n_0\ : STD_LOGIC; + signal \grant_r[0]_i_1__2_n_0\ : STD_LOGIC; + signal \grant_r[1]_i_1__3_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_1__2_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_2__1_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_3__1_n_0\ : STD_LOGIC; + signal \grant_r[2]_i_4__1_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_10__0_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_13__0_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_1__2_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_2__0_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_3__1_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_4__1_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_5__2_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_6__2_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_7__1_n_0\ : STD_LOGIC; + signal \grant_r[3]_i_9__1_n_0\ : STD_LOGIC; + signal \^grant_r_reg[3]_0\ : STD_LOGIC; + signal \inhbt_act_faw.SRLC32E0_i_2_n_0\ : STD_LOGIC; + signal last_master_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \last_master_r[0]_i_1__1_n_0\ : STD_LOGIC; + signal \last_master_r[1]_i_1__1_n_0\ : STD_LOGIC; + signal \last_master_r[2]_i_1__2_n_0\ : STD_LOGIC; + signal \last_master_r[3]_i_1__1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_address[14]_i_3\ : label is "soft_lutpair499"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cas_n[0]_i_1\ : label is "soft_lutpair498"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_ras_n[0]_i_2\ : label is "soft_lutpair498"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_we_n[0]_i_3\ : label is "soft_lutpair500"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_we_n[0]_i_4\ : label is "soft_lutpair500"; + attribute SOFT_HLUTNM of \inhbt_act_faw.SRLC32E0_i_2\ : label is "soft_lutpair499"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); + \grant_r_reg[3]_0\ <= \^grant_r_reg[3]_0\; +\cmd_pipe_plus.mc_address[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[0]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(0), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(0) + ); +\cmd_pipe_plus.mc_address[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(0), + I2 => req_row_r(14), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(29), + O => \cmd_pipe_plus.mc_address[0]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[10]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFAEAAAAAA" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address_reg[10]\, + I1 => req_row_r(24), + I2 => \^q\(3), + I3 => \^q\(2), + I4 => row_cmd_wr(2), + I5 => \cmd_pipe_plus.mc_address[10]_i_3_n_0\, + O => \req_row_r_lcl_reg[14]\(10) + ); +\cmd_pipe_plus.mc_address[10]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F111111111111111" + ) + port map ( + I0 => sent_row, + I1 => \cmd_pipe_plus.mc_bank_reg[2]\, + I2 => row_cmd_wr(0), + I3 => \cmd_pipe_plus.mc_address_reg[14]\(10), + I4 => \^q\(0), + I5 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + O => \cmd_pipe_plus.mc_address[10]_i_3_n_0\ + ); +\cmd_pipe_plus.mc_address[11]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[11]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(11), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(11) + ); +\cmd_pipe_plus.mc_address[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(10), + I2 => req_row_r(25), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(39), + O => \cmd_pipe_plus.mc_address[11]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[12]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[12]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(12), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(12) + ); +\cmd_pipe_plus.mc_address[12]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(11), + I2 => req_row_r(26), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(40), + O => \cmd_pipe_plus.mc_address[12]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[13]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[13]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(13), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(13) + ); +\cmd_pipe_plus.mc_address[13]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(12), + I2 => req_row_r(27), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(41), + O => \cmd_pipe_plus.mc_address[13]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[14]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[14]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(14), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(14) + ); +\cmd_pipe_plus.mc_address[14]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(13), + I2 => req_row_r(28), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(42), + O => \cmd_pipe_plus.mc_address[14]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[14]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(2), + I2 => \^q\(1), + O => \cmd_pipe_plus.mc_address[14]_i_3_n_0\ + ); +\cmd_pipe_plus.mc_address[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[1]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(1), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(1) + ); +\cmd_pipe_plus.mc_address[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(1), + I2 => req_row_r(15), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(30), + O => \cmd_pipe_plus.mc_address[1]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[2]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(2), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(2) + ); +\cmd_pipe_plus.mc_address[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(2), + I2 => req_row_r(16), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(31), + O => \cmd_pipe_plus.mc_address[2]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[3]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(3), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(3) + ); +\cmd_pipe_plus.mc_address[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(3), + I2 => req_row_r(17), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(32), + O => \cmd_pipe_plus.mc_address[3]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[4]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(4), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(4) + ); +\cmd_pipe_plus.mc_address[4]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(4), + I2 => req_row_r(18), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(33), + O => \cmd_pipe_plus.mc_address[4]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[5]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(5), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(5) + ); +\cmd_pipe_plus.mc_address[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(5), + I2 => req_row_r(19), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(34), + O => \cmd_pipe_plus.mc_address[5]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[6]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(6), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(6) + ); +\cmd_pipe_plus.mc_address[6]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(6), + I2 => req_row_r(20), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(35), + O => \cmd_pipe_plus.mc_address[6]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[7]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(7), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(7) + ); +\cmd_pipe_plus.mc_address[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(7), + I2 => req_row_r(21), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(36), + O => \cmd_pipe_plus.mc_address[7]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[8]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(8), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(8) + ); +\cmd_pipe_plus.mc_address[8]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(8), + I2 => req_row_r(22), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(37), + O => \cmd_pipe_plus.mc_address[8]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_address[9]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[9]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_address_reg[14]\(9), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => \req_row_r_lcl_reg[14]\(9) + ); +\cmd_pipe_plus.mc_address[9]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => req_row_r(9), + I2 => req_row_r(23), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => req_row_r(38), + O => \cmd_pipe_plus.mc_address[9]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAEAAAEAAAFFFF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I2 => \cmd_pipe_plus.mc_bank_reg[2]_0\(0), + I3 => \^q\(0), + I4 => \cmd_pipe_plus.mc_bank_reg[2]\, + I5 => sent_row, + O => insert_maint_r1_lcl_reg(0) + ); +\cmd_pipe_plus.mc_bank[0]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => \cmd_pipe_plus.mc_bank_reg[2]_1\(0), + I2 => \cmd_pipe_plus.mc_bank_reg[2]_2\(0), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => \cmd_pipe_plus.mc_bank_reg[2]_3\(0), + O => \cmd_pipe_plus.mc_bank[0]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFF1F1F1F1F1F1F1" + ) + port map ( + I0 => sent_row, + I1 => \cmd_pipe_plus.mc_bank_reg[2]\, + I2 => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\, + I3 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I4 => \cmd_pipe_plus.mc_bank_reg[2]_0\(1), + I5 => \^q\(0), + O => insert_maint_r1_lcl_reg(1) + ); +\cmd_pipe_plus.mc_bank[1]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"E2E2F3C0E2E2C0C0" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank_reg[2]_2\(1), + I1 => \^q\(3), + I2 => \cmd_pipe_plus.mc_bank_reg[2]_3\(1), + I3 => \cmd_pipe_plus.mc_bank_reg[2]_1\(1), + I4 => \^q\(2), + I5 => \^q\(1), + O => \cmd_pipe_plus.mc_bank[1]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_bank[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFABABABABABABAB" + ) + port map ( + I0 => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\, + I1 => \cmd_pipe_plus.mc_bank_reg[2]\, + I2 => sent_row, + I3 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I4 => \cmd_pipe_plus.mc_bank_reg[2]_0\(2), + I5 => \^q\(0), + O => insert_maint_r1_lcl_reg(2) + ); +\cmd_pipe_plus.mc_bank[2]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFF0880000F088" + ) + port map ( + I0 => \^q\(1), + I1 => \cmd_pipe_plus.mc_bank_reg[2]_1\(2), + I2 => \cmd_pipe_plus.mc_bank_reg[2]_2\(2), + I3 => \^q\(2), + I4 => \^q\(3), + I5 => \cmd_pipe_plus.mc_bank_reg[2]_3\(2), + O => \cmd_pipe_plus.mc_bank[2]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_cas_n[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \cmd_pipe_plus.mc_cas_n_reg[0]\, + I1 => \^q\(3), + I2 => \^q\(2), + I3 => \^q\(1), + I4 => \^q\(0), + O => mc_cas_n_ns(0) + ); +\cmd_pipe_plus.mc_ras_n[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000FF540054FF" + ) + port map ( + I0 => \cmd_pipe_plus.mc_ras_n_reg[0]\, + I1 => maint_zq_r, + I2 => maint_srx_r, + I3 => \cmd_pipe_plus.mc_bank_reg[2]\, + I4 => sent_row, + I5 => \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\, + O => mc_ras_n_ns(0) + ); +\cmd_pipe_plus.mc_ras_n[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + I3 => \^q\(3), + O => \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_we_n[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFEA" + ) + port map ( + I0 => \cmd_pipe_plus.mc_we_n_reg[0]_0\, + I1 => row_cmd_wr(1), + I2 => \^grant_r_reg[3]_0\, + I3 => \cmd_pipe_plus.mc_we_n[0]_i_4_n_0\, + I4 => \cmd_pipe_plus.mc_we_n_reg[0]\, + I5 => \cmd_pipe_plus.mc_we_n[0]_i_5_n_0\, + O => D(0) + ); +\cmd_pipe_plus.mc_we_n[0]_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"04" + ) + port map ( + I0 => \^q\(3), + I1 => \^q\(1), + I2 => \^q\(2), + O => \^grant_r_reg[3]_0\ + ); +\cmd_pipe_plus.mc_we_n[0]_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => row_cmd_wr(2), + I1 => \^q\(2), + I2 => \^q\(3), + O => \cmd_pipe_plus.mc_we_n[0]_i_4_n_0\ + ); +\cmd_pipe_plus.mc_we_n[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8080808A80808080" + ) + port map ( + I0 => \cmd_pipe_plus.mc_address[14]_i_3_n_0\, + I1 => row_cmd_wr(0), + I2 => \^q\(0), + I3 => \cmd_pipe_plus.mc_ras_n_reg[0]\, + I4 => maint_zq_r, + I5 => \cmd_pipe_plus.mc_bank_reg[2]\, + O => \cmd_pipe_plus.mc_we_n[0]_i_5_n_0\ + ); +\grant_r[0]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AA02020200000000" + ) + port map ( + I0 => \grant_r[2]_i_2__1_n_0\, + I1 => \last_master_r[1]_i_1__1_n_0\, + I2 => \last_master_r[0]_i_1__1_n_0\, + I3 => \grant_r[3]_i_5__2_n_0\, + I4 => \grant_r[3]_i_2__0_n_0\, + I5 => \grant_r[2]_i_3__1_n_0\, + O => \grant_r[0]_i_1__2_n_0\ + ); +\grant_r[1]_i_1__3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000444F0000" + ) + port map ( + I0 => \grant_r[2]_i_3__1_n_0\, + I1 => \grant_r[3]_i_5__2_n_0\, + I2 => \last_master_r[1]_i_1__1_n_0\, + I3 => \last_master_r[2]_i_1__2_n_0\, + I4 => \grant_r[3]_i_3__1_n_0\, + I5 => \grant_r[3]_i_4__1_n_0\, + O => \grant_r[1]_i_1__3_n_0\ + ); +\grant_r[2]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000000020202AA" + ) + port map ( + I0 => \grant_r[2]_i_2__1_n_0\, + I1 => \grant_r[2]_i_3__1_n_0\, + I2 => \grant_r[3]_i_3__1_n_0\, + I3 => \last_master_r[2]_i_1__2_n_0\, + I4 => \last_master_r[3]_i_1__1_n_0\, + I5 => \grant_r[3]_i_2__0_n_0\, + O => \grant_r[2]_i_1__2_n_0\ + ); +\grant_r[2]_i_2__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7077" + ) + port map ( + I0 => \grant_r[3]_i_3__1_n_0\, + I1 => \last_master_r[0]_i_1__1_n_0\, + I2 => \grant_r[3]_i_5__2_n_0\, + I3 => \last_master_r[2]_i_1__2_n_0\, + O => \grant_r[2]_i_2__1_n_0\ + ); +\grant_r[2]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000000E" + ) + port map ( + I0 => \grant_r[2]_i_4__1_n_0\, + I1 => demand_act_priority_r, + I2 => granted_row_r_reg, + I3 => granted_row_r_reg_0, + I4 => \^q\(0), + I5 => \grant_r[3]_i_10__0_n_0\, + O => \grant_r[2]_i_3__1_n_0\ + ); +\grant_r[2]_i_4__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB0BBB0B0000BB0B" + ) + port map ( + I0 => \^q\(3), + I1 => demand_act_priority_r_6, + I2 => demand_act_priority_r_5, + I3 => \^q\(2), + I4 => demand_act_priority_r_4, + I5 => \^q\(1), + O => \grant_r[2]_i_4__1_n_0\ + ); +\grant_r[3]_i_10__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF8FFF8FFF8" + ) + port map ( + I0 => \^q\(2), + I1 => row_cmd_wr(2), + I2 => \grant_r[2]_i_3__1_0\, + I3 => inhbt_act_faw_r, + I4 => row_cmd_wr(3), + I5 => \^q\(3), + O => \grant_r[3]_i_10__0_n_0\ + ); +\grant_r[3]_i_13__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"BB0BBB0B0000BB0B" + ) + port map ( + I0 => \^q\(0), + I1 => demand_act_priority_r, + I2 => demand_act_priority_r_5, + I3 => \^q\(2), + I4 => demand_act_priority_r_4, + I5 => \^q\(1), + O => \grant_r[3]_i_13__0_n_0\ + ); +\grant_r[3]_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000222F" + ) + port map ( + I0 => \grant_r[3]_i_2__0_n_0\, + I1 => \grant_r[3]_i_3__1_n_0\, + I2 => \last_master_r[0]_i_1__1_n_0\, + I3 => \last_master_r[3]_i_1__1_n_0\, + I4 => \grant_r[3]_i_4__1_n_0\, + I5 => \grant_r[3]_i_5__2_n_0\, + O => \grant_r[3]_i_1__2_n_0\ + ); +\grant_r[3]_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFF1" + ) + port map ( + I0 => \grant_r[3]_i_6__2_n_0\, + I1 => demand_act_priority_r_5, + I2 => \grant_r[3]_i_7__1_n_0\, + I3 => \cmd_pipe_plus.mc_we_n_reg[0]\, + I4 => \^q\(2), + I5 => \grant_r_reg[3]_3\, + O => \grant_r[3]_i_2__0_n_0\ + ); +\grant_r[3]_i_3__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"000000000000000E" + ) + port map ( + I0 => \grant_r[3]_i_9__1_n_0\, + I1 => demand_act_priority_r_4, + I2 => \grant_r[3]_i_10__0_n_0\, + I3 => \grant_r_reg[3]_1\, + I4 => \^q\(1), + I5 => \grant_r_reg[3]_2\, + O => \grant_r[3]_i_3__1_n_0\ + ); +\grant_r[3]_i_4__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F444" + ) + port map ( + I0 => \grant_r[3]_i_2__0_n_0\, + I1 => \last_master_r[1]_i_1__1_n_0\, + I2 => \grant_r[2]_i_3__1_n_0\, + I3 => \last_master_r[3]_i_1__1_n_0\, + O => \grant_r[3]_i_4__1_n_0\ + ); +\grant_r[3]_i_5__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFFFFFFFFF1" + ) + port map ( + I0 => \grant_r[3]_i_13__0_n_0\, + I1 => demand_act_priority_r_6, + I2 => \grant_r[3]_i_7__1_n_0\, + I3 => \grant_r_reg[3]_4\, + I4 => \^q\(3), + I5 => \grant_r_reg[3]_5\, + O => \grant_r[3]_i_5__2_n_0\ + ); +\grant_r[3]_i_6__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DD0D0000DD0DDD0D" + ) + port map ( + I0 => demand_act_priority_r_6, + I1 => \^q\(3), + I2 => demand_act_priority_r, + I3 => \^q\(0), + I4 => \^q\(1), + I5 => demand_act_priority_r_4, + O => \grant_r[3]_i_6__2_n_0\ + ); +\grant_r[3]_i_7__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFF8FFF8FFF8" + ) + port map ( + I0 => \^q\(0), + I1 => row_cmd_wr(0), + I2 => \grant_r[2]_i_3__1_0\, + I3 => inhbt_act_faw_r, + I4 => row_cmd_wr(1), + I5 => \^q\(1), + O => \grant_r[3]_i_7__1_n_0\ + ); +\grant_r[3]_i_9__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"DD0D0000DD0DDD0D" + ) + port map ( + I0 => demand_act_priority_r_6, + I1 => \^q\(3), + I2 => demand_act_priority_r, + I3 => \^q\(0), + I4 => \^q\(2), + I5 => demand_act_priority_r_5, + O => \grant_r[3]_i_9__1_n_0\ + ); +\grant_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[0]_i_1__2_n_0\, + Q => \^q\(0), + R => '0' + ); +\grant_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[1]_i_1__3_n_0\, + Q => \^q\(1), + R => '0' + ); +\grant_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[2]_i_1__2_n_0\, + Q => \^q\(2), + R => '0' + ); +\grant_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \grant_r[3]_i_1__2_n_0\, + Q => \^q\(3), + R => '0' + ); +granted_row_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"FDFF" + ) + port map ( + I0 => \grant_r[3]_i_2__0_n_0\, + I1 => \grant_r[3]_i_3__1_n_0\, + I2 => \grant_r[2]_i_3__1_n_0\, + I3 => \grant_r[3]_i_5__2_n_0\, + O => granted_row_ns + ); +\inhbt_act_faw.SRLC32E0_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFF888" + ) + port map ( + I0 => \^q\(0), + I1 => act_this_rank_r(0), + I2 => \^q\(3), + I3 => act_this_rank_r(3), + I4 => \inhbt_act_faw.SRLC32E0_i_2_n_0\, + O => act_this_rank + ); +\inhbt_act_faw.SRLC32E0_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => act_this_rank_r(2), + I1 => \^q\(2), + I2 => act_this_rank_r(1), + I3 => \^q\(1), + O => \inhbt_act_faw.SRLC32E0_i_2_n_0\ + ); +\last_master_r[0]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(0), + I1 => sent_row, + I2 => \^q\(0), + I3 => \last_master_r_reg[0]_0\, + O => \last_master_r[0]_i_1__1_n_0\ + ); +\last_master_r[1]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(1), + I1 => sent_row, + I2 => \^q\(1), + I3 => \last_master_r_reg[0]_0\, + O => \last_master_r[1]_i_1__1_n_0\ + ); +\last_master_r[2]_i_1__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => last_master_r(2), + I1 => sent_row, + I2 => \^q\(2), + I3 => \last_master_r_reg[0]_0\, + O => \last_master_r[2]_i_1__2_n_0\ + ); +\last_master_r[3]_i_1__1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FEAE" + ) + port map ( + I0 => \last_master_r_reg[0]_0\, + I1 => last_master_r(3), + I2 => sent_row, + I3 => \^q\(3), + O => \last_master_r[3]_i_1__1_n_0\ + ); +\last_master_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[0]_i_1__1_n_0\, + Q => last_master_r(0), + R => '0' + ); +\last_master_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[1]_i_1__1_n_0\, + Q => last_master_r(1), + R => '0' + ); +\last_master_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[2]_i_1__2_n_0\, + Q => last_master_r(2), + R => '0' + ); +\last_master_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \last_master_r[3]_i_1__1_n_0\, + Q => last_master_r(3), + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_tempmon is + port ( + \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + device_temp_sync_r4_neq_r3 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 11 downto 0 ); + device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 ); + \device_temp_r_reg[11]_0\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_tempmon : entity is "mig_7series_v4_2_tempmon"; +end ddr3_mig_7series_v4_2_tempmon; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_tempmon is + signal \device_temp_101[11]_i_2_n_0\ : STD_LOGIC; + signal \device_temp_101[11]_i_4_n_0\ : STD_LOGIC; + signal \device_temp_101[11]_i_5_n_0\ : STD_LOGIC; + signal device_temp_lcl : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal device_temp_r : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg : string; + attribute async_reg of device_temp_r : signal is "true"; + signal \device_temp_r[11]_i_1_n_0\ : STD_LOGIC; + signal device_temp_sync_r1 : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg of device_temp_sync_r1 : signal is "true"; + signal device_temp_sync_r2 : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg of device_temp_sync_r2 : signal is "true"; + signal device_temp_sync_r3 : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg of device_temp_sync_r3 : signal is "true"; + attribute syn_srlstyle : string; + attribute syn_srlstyle of device_temp_sync_r3 : signal is "registers"; + signal device_temp_sync_r4 : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg of device_temp_sync_r4 : signal is "true"; + signal device_temp_sync_r4_neq_r3_i_2_n_0 : STD_LOGIC; + signal device_temp_sync_r4_neq_r3_i_3_n_0 : STD_LOGIC; + signal device_temp_sync_r4_neq_r3_i_4_n_0 : STD_LOGIC; + signal device_temp_sync_r4_neq_r3_i_5_n_0 : STD_LOGIC; + signal device_temp_sync_r4_neq_r3_reg_i_1_n_0 : STD_LOGIC; + signal device_temp_sync_r4_neq_r3_reg_i_1_n_1 : STD_LOGIC; + signal device_temp_sync_r4_neq_r3_reg_i_1_n_2 : STD_LOGIC; + signal device_temp_sync_r4_neq_r3_reg_i_1_n_3 : STD_LOGIC; + signal device_temp_sync_r5 : STD_LOGIC_VECTOR ( 11 downto 0 ); + attribute async_reg of device_temp_sync_r5 : signal is "true"; + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \sync_cntr[2]_i_1_n_0\ : STD_LOGIC; + signal \sync_cntr[3]_i_2_n_0\ : STD_LOGIC; + signal sync_cntr_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\ : STD_LOGIC; + signal NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + attribute ASYNC_REG_boolean : boolean; + attribute ASYNC_REG_boolean of \device_temp_r_reg[0]\ : label is std.standard.true; + attribute KEEP : string; + attribute KEEP of \device_temp_r_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[10]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[11]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[1]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[2]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[3]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[4]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[5]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[6]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[7]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[8]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_r_reg[9]\ : label is std.standard.true; + attribute KEEP of \device_temp_r_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[0]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[10]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[11]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[1]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[2]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[3]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[4]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[5]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[6]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[7]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[8]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r1_reg[9]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r1_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[0]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[10]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[11]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[1]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[2]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[3]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[4]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[5]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[6]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[7]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[8]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r2_reg[9]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r2_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[0]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[0]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[0]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[10]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[10]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[10]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[11]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[11]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[11]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[1]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[1]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[1]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[2]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[2]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[2]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[3]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[3]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[3]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[4]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[4]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[4]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[5]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[5]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[5]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[6]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[6]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[6]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[7]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[7]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[7]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[8]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[8]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[8]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r3_reg[9]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r3_reg[9]\ : label is "yes"; + attribute syn_srlstyle of \device_temp_sync_r3_reg[9]\ : label is "registers"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[0]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[10]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[11]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[1]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[2]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[3]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[4]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[5]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[6]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[7]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[8]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r4_reg[9]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r4_reg[9]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[0]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[0]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[10]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[10]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[11]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[11]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[1]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[1]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[2]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[2]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[3]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[3]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[4]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[4]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[5]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[5]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[6]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[6]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[7]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[7]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[8]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[8]\ : label is "yes"; + attribute ASYNC_REG_boolean of \device_temp_sync_r5_reg[9]\ : label is std.standard.true; + attribute KEEP of \device_temp_sync_r5_reg[9]\ : label is "yes"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \sync_cntr[0]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \sync_cntr[1]_i_1\ : label is "soft_lutpair1"; + attribute SOFT_HLUTNM of \sync_cntr[2]_i_1\ : label is "soft_lutpair0"; + attribute SOFT_HLUTNM of \sync_cntr[3]_i_3\ : label is "soft_lutpair0"; +begin + device_temp_lcl(11 downto 0) <= device_temp_i(11 downto 0); + \out\(11 downto 0) <= device_temp_r(11 downto 0); +\device_temp_101[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0700" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(0), + O => D(0) + ); +\device_temp_101[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + O => D(10) + ); +\device_temp_101[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF8" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(11), + O => D(11) + ); +\device_temp_101[11]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAA88888" + ) + port map ( + I0 => device_temp_r(11), + I1 => device_temp_r(9), + I2 => device_temp_r(6), + I3 => \device_temp_101[11]_i_4_n_0\, + I4 => device_temp_r(7), + I5 => device_temp_r(8), + O => \device_temp_101[11]_i_2_n_0\ + ); +\device_temp_101[11]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0100FFFF" + ) + port map ( + I0 => device_temp_r(8), + I1 => device_temp_r(10), + I2 => device_temp_r(9), + I3 => \device_temp_101[11]_i_5_n_0\, + I4 => device_temp_r(11), + O => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\ + ); +\device_temp_101[11]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAA88888" + ) + port map ( + I0 => device_temp_r(5), + I1 => device_temp_r(4), + I2 => device_temp_r(1), + I3 => device_temp_r(0), + I4 => device_temp_r(2), + I5 => device_temp_r(3), + O => \device_temp_101[11]_i_4_n_0\ + ); +\device_temp_101[11]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00155555FFFFFFFF" + ) + port map ( + I0 => device_temp_r(6), + I1 => device_temp_r(2), + I2 => device_temp_r(3), + I3 => device_temp_r(4), + I4 => device_temp_r(5), + I5 => device_temp_r(7), + O => \device_temp_101[11]_i_5_n_0\ + ); +\device_temp_101[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0700" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(1), + O => D(1) + ); +\device_temp_101[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF8" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(2), + O => D(2) + ); +\device_temp_101[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"F7F0" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(3), + O => D(3) + ); +\device_temp_101[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0700" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(4), + O => D(4) + ); +\device_temp_101[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF8" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(5), + O => D(5) + ); +\device_temp_101[6]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0700" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(6), + O => D(6) + ); +\device_temp_101[7]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFF8" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(7), + O => D(7) + ); +\device_temp_101[8]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0700" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(8), + O => D(8) + ); +\device_temp_101[9]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0700" + ) + port map ( + I0 => device_temp_r(10), + I1 => \device_temp_101[11]_i_2_n_0\, + I2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low\, + I3 => device_temp_r(9), + O => D(9) + ); +\device_temp_r[11]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => sync_cntr_reg(1), + I1 => sync_cntr_reg(0), + I2 => sync_cntr_reg(3), + I3 => sync_cntr_reg(2), + O => \device_temp_r[11]_i_1_n_0\ + ); +\device_temp_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(0), + Q => device_temp_r(0), + R => '0' + ); +\device_temp_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(10), + Q => device_temp_r(10), + R => '0' + ); +\device_temp_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(11), + Q => device_temp_r(11), + R => '0' + ); +\device_temp_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(1), + Q => device_temp_r(1), + R => '0' + ); +\device_temp_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(2), + Q => device_temp_r(2), + R => '0' + ); +\device_temp_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(3), + Q => device_temp_r(3), + R => '0' + ); +\device_temp_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(4), + Q => device_temp_r(4), + R => '0' + ); +\device_temp_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(5), + Q => device_temp_r(5), + R => '0' + ); +\device_temp_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(6), + Q => device_temp_r(6), + R => '0' + ); +\device_temp_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(7), + Q => device_temp_r(7), + R => '0' + ); +\device_temp_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(8), + Q => device_temp_r(8), + R => '0' + ); +\device_temp_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \device_temp_r[11]_i_1_n_0\, + D => device_temp_sync_r5(9), + Q => device_temp_r(9), + R => '0' + ); +\device_temp_sync_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(0), + Q => device_temp_sync_r1(0), + R => '0' + ); +\device_temp_sync_r1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(10), + Q => device_temp_sync_r1(10), + R => '0' + ); +\device_temp_sync_r1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(11), + Q => device_temp_sync_r1(11), + R => '0' + ); +\device_temp_sync_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(1), + Q => device_temp_sync_r1(1), + R => '0' + ); +\device_temp_sync_r1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(2), + Q => device_temp_sync_r1(2), + R => '0' + ); +\device_temp_sync_r1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(3), + Q => device_temp_sync_r1(3), + R => '0' + ); +\device_temp_sync_r1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(4), + Q => device_temp_sync_r1(4), + R => '0' + ); +\device_temp_sync_r1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(5), + Q => device_temp_sync_r1(5), + R => '0' + ); +\device_temp_sync_r1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(6), + Q => device_temp_sync_r1(6), + R => '0' + ); +\device_temp_sync_r1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(7), + Q => device_temp_sync_r1(7), + R => '0' + ); +\device_temp_sync_r1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(8), + Q => device_temp_sync_r1(8), + R => '0' + ); +\device_temp_sync_r1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_lcl(9), + Q => device_temp_sync_r1(9), + R => '0' + ); +\device_temp_sync_r2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(0), + Q => device_temp_sync_r2(0), + R => '0' + ); +\device_temp_sync_r2_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(10), + Q => device_temp_sync_r2(10), + R => '0' + ); +\device_temp_sync_r2_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(11), + Q => device_temp_sync_r2(11), + R => '0' + ); +\device_temp_sync_r2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(1), + Q => device_temp_sync_r2(1), + R => '0' + ); +\device_temp_sync_r2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(2), + Q => device_temp_sync_r2(2), + R => '0' + ); +\device_temp_sync_r2_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(3), + Q => device_temp_sync_r2(3), + R => '0' + ); +\device_temp_sync_r2_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(4), + Q => device_temp_sync_r2(4), + R => '0' + ); +\device_temp_sync_r2_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(5), + Q => device_temp_sync_r2(5), + R => '0' + ); +\device_temp_sync_r2_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(6), + Q => device_temp_sync_r2(6), + R => '0' + ); +\device_temp_sync_r2_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(7), + Q => device_temp_sync_r2(7), + R => '0' + ); +\device_temp_sync_r2_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(8), + Q => device_temp_sync_r2(8), + R => '0' + ); +\device_temp_sync_r2_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r1(9), + Q => device_temp_sync_r2(9), + R => '0' + ); +\device_temp_sync_r3_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(0), + Q => device_temp_sync_r3(0), + R => '0' + ); +\device_temp_sync_r3_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(10), + Q => device_temp_sync_r3(10), + R => '0' + ); +\device_temp_sync_r3_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(11), + Q => device_temp_sync_r3(11), + R => '0' + ); +\device_temp_sync_r3_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(1), + Q => device_temp_sync_r3(1), + R => '0' + ); +\device_temp_sync_r3_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(2), + Q => device_temp_sync_r3(2), + R => '0' + ); +\device_temp_sync_r3_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(3), + Q => device_temp_sync_r3(3), + R => '0' + ); +\device_temp_sync_r3_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(4), + Q => device_temp_sync_r3(4), + R => '0' + ); +\device_temp_sync_r3_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(5), + Q => device_temp_sync_r3(5), + R => '0' + ); +\device_temp_sync_r3_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(6), + Q => device_temp_sync_r3(6), + R => '0' + ); +\device_temp_sync_r3_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(7), + Q => device_temp_sync_r3(7), + R => '0' + ); +\device_temp_sync_r3_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(8), + Q => device_temp_sync_r3(8), + R => '0' + ); +\device_temp_sync_r3_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r2(9), + Q => device_temp_sync_r3(9), + R => '0' + ); +device_temp_sync_r4_neq_r3_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => device_temp_sync_r4(9), + I1 => device_temp_sync_r3(9), + I2 => device_temp_sync_r3(11), + I3 => device_temp_sync_r4(11), + I4 => device_temp_sync_r3(10), + I5 => device_temp_sync_r4(10), + O => device_temp_sync_r4_neq_r3_i_2_n_0 + ); +device_temp_sync_r4_neq_r3_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => device_temp_sync_r4(6), + I1 => device_temp_sync_r3(6), + I2 => device_temp_sync_r3(8), + I3 => device_temp_sync_r4(8), + I4 => device_temp_sync_r3(7), + I5 => device_temp_sync_r4(7), + O => device_temp_sync_r4_neq_r3_i_3_n_0 + ); +device_temp_sync_r4_neq_r3_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => device_temp_sync_r4(3), + I1 => device_temp_sync_r3(3), + I2 => device_temp_sync_r3(5), + I3 => device_temp_sync_r4(5), + I4 => device_temp_sync_r3(4), + I5 => device_temp_sync_r4(4), + O => device_temp_sync_r4_neq_r3_i_4_n_0 + ); +device_temp_sync_r4_neq_r3_i_5: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => device_temp_sync_r4(0), + I1 => device_temp_sync_r3(0), + I2 => device_temp_sync_r3(2), + I3 => device_temp_sync_r4(2), + I4 => device_temp_sync_r3(1), + I5 => device_temp_sync_r4(1), + O => device_temp_sync_r4_neq_r3_i_5_n_0 + ); +device_temp_sync_r4_neq_r3_reg: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4_neq_r3_reg_i_1_n_0, + Q => device_temp_sync_r4_neq_r3, + R => '0' + ); +device_temp_sync_r4_neq_r3_reg_i_1: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => device_temp_sync_r4_neq_r3_reg_i_1_n_0, + CO(2) => device_temp_sync_r4_neq_r3_reg_i_1_n_1, + CO(1) => device_temp_sync_r4_neq_r3_reg_i_1_n_2, + CO(0) => device_temp_sync_r4_neq_r3_reg_i_1_n_3, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3 downto 0) => NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED(3 downto 0), + S(3) => device_temp_sync_r4_neq_r3_i_2_n_0, + S(2) => device_temp_sync_r4_neq_r3_i_3_n_0, + S(1) => device_temp_sync_r4_neq_r3_i_4_n_0, + S(0) => device_temp_sync_r4_neq_r3_i_5_n_0 + ); +\device_temp_sync_r4_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(0), + Q => device_temp_sync_r4(0), + R => '0' + ); +\device_temp_sync_r4_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(10), + Q => device_temp_sync_r4(10), + R => '0' + ); +\device_temp_sync_r4_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(11), + Q => device_temp_sync_r4(11), + R => '0' + ); +\device_temp_sync_r4_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(1), + Q => device_temp_sync_r4(1), + R => '0' + ); +\device_temp_sync_r4_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(2), + Q => device_temp_sync_r4(2), + R => '0' + ); +\device_temp_sync_r4_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(3), + Q => device_temp_sync_r4(3), + R => '0' + ); +\device_temp_sync_r4_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(4), + Q => device_temp_sync_r4(4), + R => '0' + ); +\device_temp_sync_r4_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(5), + Q => device_temp_sync_r4(5), + R => '0' + ); +\device_temp_sync_r4_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(6), + Q => device_temp_sync_r4(6), + R => '0' + ); +\device_temp_sync_r4_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(7), + Q => device_temp_sync_r4(7), + R => '0' + ); +\device_temp_sync_r4_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(8), + Q => device_temp_sync_r4(8), + R => '0' + ); +\device_temp_sync_r4_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r3(9), + Q => device_temp_sync_r4(9), + R => '0' + ); +\device_temp_sync_r5_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(0), + Q => device_temp_sync_r5(0), + R => '0' + ); +\device_temp_sync_r5_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(10), + Q => device_temp_sync_r5(10), + R => '0' + ); +\device_temp_sync_r5_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(11), + Q => device_temp_sync_r5(11), + R => '0' + ); +\device_temp_sync_r5_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(1), + Q => device_temp_sync_r5(1), + R => '0' + ); +\device_temp_sync_r5_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(2), + Q => device_temp_sync_r5(2), + R => '0' + ); +\device_temp_sync_r5_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(3), + Q => device_temp_sync_r5(3), + R => '0' + ); +\device_temp_sync_r5_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(4), + Q => device_temp_sync_r5(4), + R => '0' + ); +\device_temp_sync_r5_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(5), + Q => device_temp_sync_r5(5), + R => '0' + ); +\device_temp_sync_r5_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(6), + Q => device_temp_sync_r5(6), + R => '0' + ); +\device_temp_sync_r5_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(7), + Q => device_temp_sync_r5(7), + R => '0' + ); +\device_temp_sync_r5_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(8), + Q => device_temp_sync_r5(8), + R => '0' + ); +\device_temp_sync_r5_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => \device_temp_r_reg[11]_0\, + CE => '1', + D => device_temp_sync_r4(9), + Q => device_temp_sync_r5(9), + R => '0' + ); +\sync_cntr[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => sync_cntr_reg(0), + O => \p_0_in__0\(0) + ); +\sync_cntr[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => sync_cntr_reg(0), + I1 => sync_cntr_reg(1), + O => \p_0_in__0\(1) + ); +\sync_cntr[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => sync_cntr_reg(1), + I1 => sync_cntr_reg(0), + I2 => sync_cntr_reg(2), + O => \sync_cntr[2]_i_1_n_0\ + ); +\sync_cntr[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7FFF" + ) + port map ( + I0 => sync_cntr_reg(2), + I1 => sync_cntr_reg(3), + I2 => sync_cntr_reg(0), + I3 => sync_cntr_reg(1), + O => \sync_cntr[3]_i_2_n_0\ + ); +\sync_cntr[3]_i_3\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => sync_cntr_reg(0), + I1 => sync_cntr_reg(1), + I2 => sync_cntr_reg(2), + I3 => sync_cntr_reg(3), + O => \p_0_in__0\(3) + ); +\sync_cntr_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \sync_cntr[3]_i_2_n_0\, + D => \p_0_in__0\(0), + Q => sync_cntr_reg(0), + R => SR(0) + ); +\sync_cntr_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \sync_cntr[3]_i_2_n_0\, + D => \p_0_in__0\(1), + Q => sync_cntr_reg(1), + R => SR(0) + ); +\sync_cntr_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \sync_cntr[3]_i_2_n_0\, + D => \sync_cntr[2]_i_1_n_0\, + Q => sync_cntr_reg(2), + R => SR(0) + ); +\sync_cntr_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => \device_temp_r_reg[11]_0\, + CE => \sync_cntr[3]_i_2_n_0\, + D => \p_0_in__0\(3), + Q => sync_cntr_reg(3), + R => SR(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ui_cmd is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + app_en_r2_reg_0 : out STD_LOGIC; + \app_cmd_r2_reg[0]_0\ : out STD_LOGIC; + \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC; + \req_bank_r_lcl_reg[0]\ : out STD_LOGIC; + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC; + \req_bank_r_lcl_reg[0]_0\ : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + row : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + was_wr0 : out STD_LOGIC; + \app_addr_r1_reg[26]_0\ : out STD_LOGIC; + req_wr_r_lcl0 : out STD_LOGIC; + \wr_req_counter.wr_req_cnt_r_reg[0]\ : out STD_LOGIC; + wr_accepted : out STD_LOGIC; + \not_strict_mode.occ_cnt_r_reg[1]\ : out STD_LOGIC; + rd_accepted : out STD_LOGIC; + \app_addr_r1_reg[27]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \app_addr_r1_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + app_rdy_ns : in STD_LOGIC; + CLK : in STD_LOGIC; + app_en_r2_reg_1 : in STD_LOGIC; + app_en : in STD_LOGIC; + periodic_rd_ack_r : in STD_LOGIC; + periodic_rd_cntr_r : in STD_LOGIC; + periodic_rd_r : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); + rb_hit_busy_r_reg : in STD_LOGIC; + req_bank_r : in STD_LOGIC_VECTOR ( 11 downto 0 ); + rb_hit_busy_r_reg_0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + rb_hit_busy_r_reg_2 : in STD_LOGIC; + row_hit_r_reg : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \wr_req_counter.wr_req_cnt_r\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.occ_cnt_r\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + wr_data_buf_addr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + app_addr : in STD_LOGIC_VECTOR ( 27 downto 0 ); + app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ui_cmd : entity is "mig_7series_v4_2_ui_cmd"; +end ddr3_mig_7series_v4_2_ui_cmd; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ui_cmd is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal app_addr_r10 : STD_LOGIC; + signal \^app_addr_r1_reg[26]_0\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[0]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[10]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[11]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[12]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[13]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[14]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[15]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[16]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[17]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[18]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[19]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[1]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[20]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[21]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[22]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[23]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[24]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[2]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[3]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[4]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[5]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[6]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[7]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[8]\ : STD_LOGIC; + signal \app_addr_r1_reg_n_0_[9]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[0]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[10]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[11]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[12]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[13]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[14]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[15]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[16]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[17]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[18]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[19]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[1]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[20]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[21]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[22]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[23]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[24]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[2]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[3]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[4]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[5]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[6]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[7]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[8]\ : STD_LOGIC; + signal \app_addr_r2_reg_n_0_[9]\ : STD_LOGIC; + signal app_cmd_r1 : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal app_cmd_r2 : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^app_cmd_r2_reg[0]_0\ : STD_LOGIC; + signal app_en_r1 : STD_LOGIC; + signal \^app_en_r2_reg_0\ : STD_LOGIC; + signal p_0_in_0 : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal p_1_in : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \rb_hit_busy_r_i_2__0_n_0\ : STD_LOGIC; + signal \rb_hit_busy_r_i_2__1_n_0\ : STD_LOGIC; + signal \rb_hit_busy_r_i_2__2_n_0\ : STD_LOGIC; + signal rb_hit_busy_r_i_2_n_0 : STD_LOGIC; + signal req_wr_r_lcl_i_2_n_0 : STD_LOGIC; + signal \^row\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + attribute syn_maxfan : string; + attribute syn_maxfan of app_rdy_r_reg : label is "10"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\ : label is "soft_lutpair561"; + attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_1\ : label is "soft_lutpair561"; + attribute SOFT_HLUTNM of \req_bank_r_lcl[0]_i_1\ : label is "soft_lutpair571"; + attribute SOFT_HLUTNM of \req_bank_r_lcl[1]_i_1\ : label is "soft_lutpair569"; + attribute SOFT_HLUTNM of \req_bank_r_lcl[2]_i_1\ : label is "soft_lutpair571"; + attribute SOFT_HLUTNM of \req_col_r[0]_i_1\ : label is "soft_lutpair572"; + attribute SOFT_HLUTNM of \req_col_r[1]_i_1\ : label is "soft_lutpair572"; + attribute SOFT_HLUTNM of \req_col_r[2]_i_1\ : label is "soft_lutpair573"; + attribute SOFT_HLUTNM of \req_col_r[3]_i_1\ : label is "soft_lutpair573"; + attribute SOFT_HLUTNM of \req_col_r[4]_i_1\ : label is "soft_lutpair574"; + attribute SOFT_HLUTNM of \req_col_r[5]_i_1\ : label is "soft_lutpair574"; + attribute SOFT_HLUTNM of \req_col_r[6]_i_1\ : label is "soft_lutpair575"; + attribute SOFT_HLUTNM of \req_col_r[7]_i_1\ : label is "soft_lutpair575"; + attribute SOFT_HLUTNM of \req_col_r[8]_i_1\ : label is "soft_lutpair576"; + attribute SOFT_HLUTNM of \req_col_r[9]_i_1\ : label is "soft_lutpair576"; + attribute SOFT_HLUTNM of \req_data_buf_addr_r[0]_i_1\ : label is "soft_lutpair562"; + attribute SOFT_HLUTNM of \req_data_buf_addr_r[4]_i_1\ : label is "soft_lutpair562"; + attribute SOFT_HLUTNM of \req_row_r_lcl[0]_i_1\ : label is "soft_lutpair564"; + attribute SOFT_HLUTNM of \req_row_r_lcl[10]_i_1\ : label is "soft_lutpair566"; + attribute SOFT_HLUTNM of \req_row_r_lcl[11]_i_1\ : label is "soft_lutpair567"; + attribute SOFT_HLUTNM of \req_row_r_lcl[12]_i_1\ : label is "soft_lutpair569"; + attribute SOFT_HLUTNM of \req_row_r_lcl[13]_i_1\ : label is "soft_lutpair570"; + attribute SOFT_HLUTNM of \req_row_r_lcl[14]_i_1\ : label is "soft_lutpair570"; + attribute SOFT_HLUTNM of \req_row_r_lcl[1]_i_1\ : label is "soft_lutpair565"; + attribute SOFT_HLUTNM of \req_row_r_lcl[2]_i_1\ : label is "soft_lutpair565"; + attribute SOFT_HLUTNM of \req_row_r_lcl[3]_i_1\ : label is "soft_lutpair563"; + attribute SOFT_HLUTNM of \req_row_r_lcl[4]_i_1\ : label is "soft_lutpair563"; + attribute SOFT_HLUTNM of \req_row_r_lcl[5]_i_1\ : label is "soft_lutpair564"; + attribute SOFT_HLUTNM of \req_row_r_lcl[6]_i_1\ : label is "soft_lutpair567"; + attribute SOFT_HLUTNM of \req_row_r_lcl[7]_i_1\ : label is "soft_lutpair568"; + attribute SOFT_HLUTNM of \req_row_r_lcl[8]_i_1\ : label is "soft_lutpair568"; + attribute SOFT_HLUTNM of \req_row_r_lcl[9]_i_1\ : label is "soft_lutpair566"; +begin + E(0) <= \^e\(0); + \app_addr_r1_reg[26]_0\ <= \^app_addr_r1_reg[26]_0\; + \app_cmd_r2_reg[0]_0\ <= \^app_cmd_r2_reg[0]_0\; + app_en_r2_reg_0 <= \^app_en_r2_reg_0\; + row(14 downto 0) <= \^row\(14 downto 0); +\app_addr_r1[27]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^e\(0), + I1 => app_en, + O => app_addr_r10 + ); +\app_addr_r1_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(0), + Q => \app_addr_r1_reg_n_0_[0]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(10), + Q => \app_addr_r1_reg_n_0_[10]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(11), + Q => \app_addr_r1_reg_n_0_[11]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(12), + Q => \app_addr_r1_reg_n_0_[12]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(13), + Q => \app_addr_r1_reg_n_0_[13]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(14), + Q => \app_addr_r1_reg_n_0_[14]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(15), + Q => \app_addr_r1_reg_n_0_[15]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(16), + Q => \app_addr_r1_reg_n_0_[16]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(17), + Q => \app_addr_r1_reg_n_0_[17]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(18), + Q => \app_addr_r1_reg_n_0_[18]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(19), + Q => \app_addr_r1_reg_n_0_[19]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(1), + Q => \app_addr_r1_reg_n_0_[1]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(20), + Q => \app_addr_r1_reg_n_0_[20]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(21), + Q => \app_addr_r1_reg_n_0_[21]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(22), + Q => \app_addr_r1_reg_n_0_[22]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(23), + Q => \app_addr_r1_reg_n_0_[23]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(24), + Q => \app_addr_r1_reg_n_0_[24]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(25), + Q => p_1_in(0), + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(26), + Q => p_1_in(1), + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(27), + Q => p_1_in(2), + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(2), + Q => \app_addr_r1_reg_n_0_[2]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(3), + Q => \app_addr_r1_reg_n_0_[3]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(4), + Q => \app_addr_r1_reg_n_0_[4]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(5), + Q => \app_addr_r1_reg_n_0_[5]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(6), + Q => \app_addr_r1_reg_n_0_[6]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(7), + Q => \app_addr_r1_reg_n_0_[7]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(8), + Q => \app_addr_r1_reg_n_0_[8]\, + R => app_en_r2_reg_1 + ); +\app_addr_r1_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => app_addr_r10, + D => app_addr(9), + Q => \app_addr_r1_reg_n_0_[9]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[0]\, + Q => \app_addr_r2_reg_n_0_[0]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[10]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[10]\, + Q => \app_addr_r2_reg_n_0_[10]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[11]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[11]\, + Q => \app_addr_r2_reg_n_0_[11]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[12]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[12]\, + Q => \app_addr_r2_reg_n_0_[12]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[13]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[13]\, + Q => \app_addr_r2_reg_n_0_[13]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[14]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[14]\, + Q => \app_addr_r2_reg_n_0_[14]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[15]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[15]\, + Q => \app_addr_r2_reg_n_0_[15]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[16]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[16]\, + Q => \app_addr_r2_reg_n_0_[16]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[17]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[17]\, + Q => \app_addr_r2_reg_n_0_[17]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[18]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[18]\, + Q => \app_addr_r2_reg_n_0_[18]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[19]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[19]\, + Q => \app_addr_r2_reg_n_0_[19]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[1]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[1]\, + Q => \app_addr_r2_reg_n_0_[1]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[20]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[20]\, + Q => \app_addr_r2_reg_n_0_[20]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[21]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[21]\, + Q => \app_addr_r2_reg_n_0_[21]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[22]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[22]\, + Q => \app_addr_r2_reg_n_0_[22]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[23]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[23]\, + Q => \app_addr_r2_reg_n_0_[23]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[24]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[24]\, + Q => \app_addr_r2_reg_n_0_[24]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[25]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => p_1_in(0), + Q => p_0_in_0(0), + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[26]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => p_1_in(1), + Q => p_0_in_0(1), + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[27]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => p_1_in(2), + Q => p_0_in_0(2), + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[2]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[2]\, + Q => \app_addr_r2_reg_n_0_[2]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[3]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[3]\, + Q => \app_addr_r2_reg_n_0_[3]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[4]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[4]\, + Q => \app_addr_r2_reg_n_0_[4]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[5]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[5]\, + Q => \app_addr_r2_reg_n_0_[5]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[6]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[6]\, + Q => \app_addr_r2_reg_n_0_[6]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[7]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[7]\, + Q => \app_addr_r2_reg_n_0_[7]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[8]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[8]\, + Q => \app_addr_r2_reg_n_0_[8]\, + R => app_en_r2_reg_1 + ); +\app_addr_r2_reg[9]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => \^e\(0), + D => \app_addr_r1_reg_n_0_[9]\, + Q => \app_addr_r2_reg_n_0_[9]\, + R => app_en_r2_reg_1 + ); +\app_cmd_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \^e\(0), + D => app_cmd(0), + Q => app_cmd_r1(0), + R => '0' + ); +\app_cmd_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \^e\(0), + D => app_cmd(1), + Q => app_cmd_r1(1), + R => '0' + ); +\app_cmd_r2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \^e\(0), + D => app_cmd_r1(0), + Q => app_cmd_r2(0), + R => '0' + ); +\app_cmd_r2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \^e\(0), + D => app_cmd_r1(1), + Q => app_cmd_r2(1), + R => '0' + ); +app_en_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \^e\(0), + D => app_en, + Q => app_en_r1, + R => app_en_r2_reg_1 + ); +app_en_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \^e\(0), + D => app_en_r1, + Q => \^app_en_r2_reg_0\, + R => app_en_r2_reg_1 + ); +app_rdy_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => app_rdy_ns, + Q => \^e\(0), + R => '0' + ); +\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8008" + ) + port map ( + I0 => \^e\(0), + I1 => \^app_en_r2_reg_0\, + I2 => app_cmd_r2(0), + I3 => app_cmd_r2(1), + O => wr_accepted + ); +\not_strict_mode.occ_cnt_r[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"5D55555504000000" + ) + port map ( + I0 => \not_strict_mode.occ_cnt_r\(1), + I1 => app_cmd_r2(0), + I2 => app_cmd_r2(1), + I3 => \^app_en_r2_reg_0\, + I4 => \^e\(0), + I5 => \not_strict_mode.occ_cnt_r\(0), + O => \not_strict_mode.occ_cnt_r_reg[1]\ + ); +\not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0800" + ) + port map ( + I0 => \^e\(0), + I1 => \^app_en_r2_reg_0\, + I2 => app_cmd_r2(1), + I3 => app_cmd_r2(0), + O => rd_accepted + ); +rb_hit_busy_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020200202022002" + ) + port map ( + I0 => rb_hit_busy_r_reg, + I1 => rb_hit_busy_r_i_2_n_0, + I2 => req_bank_r(2), + I3 => p_0_in_0(2), + I4 => \^e\(0), + I5 => p_1_in(2), + O => \req_bank_r_lcl_reg[2]\ + ); +\rb_hit_busy_r_i_1__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020200202022002" + ) + port map ( + I0 => rb_hit_busy_r_reg_0, + I1 => \rb_hit_busy_r_i_2__2_n_0\, + I2 => req_bank_r(9), + I3 => p_0_in_0(0), + I4 => \^e\(0), + I5 => p_1_in(0), + O => \req_bank_r_lcl_reg[0]\ + ); +\rb_hit_busy_r_i_1__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020200202022002" + ) + port map ( + I0 => rb_hit_busy_r_reg_1, + I1 => \rb_hit_busy_r_i_2__1_n_0\, + I2 => req_bank_r(8), + I3 => p_0_in_0(2), + I4 => \^e\(0), + I5 => p_1_in(2), + O => \req_bank_r_lcl_reg[2]_0\ + ); +\rb_hit_busy_r_i_1__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"2020200202022002" + ) + port map ( + I0 => rb_hit_busy_r_reg_2, + I1 => \rb_hit_busy_r_i_2__0_n_0\, + I2 => req_bank_r(3), + I3 => p_0_in_0(0), + I4 => \^e\(0), + I5 => p_1_in(0), + O => \req_bank_r_lcl_reg[0]_0\ + ); +rb_hit_busy_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"47B8FFFFFFFF47B8" + ) + port map ( + I0 => p_1_in(0), + I1 => \^e\(0), + I2 => p_0_in_0(0), + I3 => req_bank_r(0), + I4 => \^app_addr_r1_reg[26]_0\, + I5 => req_bank_r(1), + O => rb_hit_busy_r_i_2_n_0 + ); +\rb_hit_busy_r_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"47B8FFFFFFFF47B8" + ) + port map ( + I0 => p_1_in(2), + I1 => \^e\(0), + I2 => p_0_in_0(2), + I3 => req_bank_r(5), + I4 => \^app_addr_r1_reg[26]_0\, + I5 => req_bank_r(4), + O => \rb_hit_busy_r_i_2__0_n_0\ + ); +\rb_hit_busy_r_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"47B8FFFFFFFF47B8" + ) + port map ( + I0 => p_1_in(0), + I1 => \^e\(0), + I2 => p_0_in_0(0), + I3 => req_bank_r(6), + I4 => \^app_addr_r1_reg[26]_0\, + I5 => req_bank_r(7), + O => \rb_hit_busy_r_i_2__1_n_0\ + ); +\rb_hit_busy_r_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"47B8FFFFFFFF47B8" + ) + port map ( + I0 => p_1_in(2), + I1 => \^e\(0), + I2 => p_0_in_0(2), + I3 => req_bank_r(11), + I4 => \^app_addr_r1_reg[26]_0\, + I5 => req_bank_r(10), + O => \rb_hit_busy_r_i_2__2_n_0\ + ); +rd_wr_r_lcl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"E2FFFFFFE2E2E2E2" + ) + port map ( + I0 => app_cmd_r2(0), + I1 => \^e\(0), + I2 => app_cmd_r1(0), + I3 => periodic_rd_ack_r, + I4 => periodic_rd_cntr_r, + I5 => periodic_rd_r, + O => \^app_cmd_r2_reg[0]_0\ + ); +\req_bank_r_lcl[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => p_1_in(0), + I1 => \^e\(0), + I2 => p_0_in_0(0), + O => \app_addr_r1_reg[27]_0\(0) + ); +\req_bank_r_lcl[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => p_1_in(1), + I1 => \^e\(0), + I2 => p_0_in_0(1), + O => \^app_addr_r1_reg[26]_0\ + ); +\req_bank_r_lcl[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => p_1_in(2), + I1 => \^e\(0), + I2 => p_0_in_0(2), + O => \app_addr_r1_reg[27]_0\(1) + ); +\req_col_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[0]\, + I1 => \app_addr_r2_reg_n_0_[0]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(0) + ); +\req_col_r[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[1]\, + I1 => \app_addr_r2_reg_n_0_[1]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(1) + ); +\req_col_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[2]\, + I1 => \app_addr_r2_reg_n_0_[2]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(2) + ); +\req_col_r[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[3]\, + I1 => \app_addr_r2_reg_n_0_[3]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(3) + ); +\req_col_r[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[4]\, + I1 => \app_addr_r2_reg_n_0_[4]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(4) + ); +\req_col_r[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[5]\, + I1 => \app_addr_r2_reg_n_0_[5]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(5) + ); +\req_col_r[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[6]\, + I1 => \app_addr_r2_reg_n_0_[6]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(6) + ); +\req_col_r[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[7]\, + I1 => \app_addr_r2_reg_n_0_[7]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(7) + ); +\req_col_r[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[8]\, + I1 => \app_addr_r2_reg_n_0_[8]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(8) + ); +\req_col_r[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[9]\, + I1 => \app_addr_r2_reg_n_0_[9]\, + I2 => \^e\(0), + O => \app_addr_r1_reg[9]_0\(9) + ); +\req_data_buf_addr_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BE82" + ) + port map ( + I0 => wr_data_buf_addr(0), + I1 => app_cmd_r2(1), + I2 => app_cmd_r2(0), + I3 => Q(0), + O => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(0) + ); +\req_data_buf_addr_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BE82" + ) + port map ( + I0 => wr_data_buf_addr(1), + I1 => app_cmd_r2(1), + I2 => app_cmd_r2(0), + I3 => Q(1), + O => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(1) + ); +\req_data_buf_addr_r[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BE82" + ) + port map ( + I0 => wr_data_buf_addr(2), + I1 => app_cmd_r2(1), + I2 => app_cmd_r2(0), + I3 => Q(2), + O => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(2) + ); +\req_data_buf_addr_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BE82" + ) + port map ( + I0 => wr_data_buf_addr(3), + I1 => app_cmd_r2(1), + I2 => app_cmd_r2(0), + I3 => Q(3), + O => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(3) + ); +\req_data_buf_addr_r[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"28" + ) + port map ( + I0 => Q(4), + I1 => app_cmd_r2(0), + I2 => app_cmd_r2(1), + O => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4) + ); +\req_row_r_lcl[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[10]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[10]\, + O => \^row\(0) + ); +\req_row_r_lcl[10]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[20]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[20]\, + O => \^row\(10) + ); +\req_row_r_lcl[11]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[21]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[21]\, + O => \^row\(11) + ); +\req_row_r_lcl[12]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[22]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[22]\, + O => \^row\(12) + ); +\req_row_r_lcl[13]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[23]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[23]\, + O => \^row\(13) + ); +\req_row_r_lcl[14]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[24]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[24]\, + O => \^row\(14) + ); +\req_row_r_lcl[1]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[11]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[11]\, + O => \^row\(1) + ); +\req_row_r_lcl[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[12]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[12]\, + O => \^row\(2) + ); +\req_row_r_lcl[3]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[13]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[13]\, + O => \^row\(3) + ); +\req_row_r_lcl[4]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[14]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[14]\, + O => \^row\(4) + ); +\req_row_r_lcl[5]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[15]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[15]\, + O => \^row\(5) + ); +\req_row_r_lcl[6]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[16]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[16]\, + O => \^row\(6) + ); +\req_row_r_lcl[7]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[17]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[17]\, + O => \^row\(7) + ); +\req_row_r_lcl[8]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[18]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[18]\, + O => \^row\(8) + ); +\req_row_r_lcl[9]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \app_addr_r1_reg_n_0_[19]\, + I1 => \^e\(0), + I2 => \app_addr_r2_reg_n_0_[19]\, + O => \^row\(9) + ); +req_wr_r_lcl_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => req_wr_r_lcl_i_2_n_0, + I1 => \^app_cmd_r2_reg[0]_0\, + O => req_wr_r_lcl0 + ); +req_wr_r_lcl_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"E2000000E2E2E2E2" + ) + port map ( + I0 => app_cmd_r2(1), + I1 => \^e\(0), + I2 => app_cmd_r1(1), + I3 => periodic_rd_ack_r, + I4 => periodic_rd_cntr_r, + I5 => periodic_rd_r, + O => req_wr_r_lcl_i_2_n_0 + ); +\row_hit_ns_carry__0_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^row\(13), + I1 => row_hit_r_reg(13), + I2 => row_hit_r_reg(14), + I3 => \^row\(14), + I4 => row_hit_r_reg(12), + I5 => \^row\(12), + O => \req_row_r_lcl_reg[13]\(0) + ); +row_hit_ns_carry_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^row\(9), + I1 => row_hit_r_reg(9), + I2 => row_hit_r_reg(11), + I3 => \^row\(11), + I4 => row_hit_r_reg(10), + I5 => \^row\(10), + O => S(3) + ); +row_hit_ns_carry_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^row\(7), + I1 => row_hit_r_reg(7), + I2 => row_hit_r_reg(8), + I3 => \^row\(8), + I4 => row_hit_r_reg(6), + I5 => \^row\(6), + O => S(2) + ); +row_hit_ns_carry_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^row\(3), + I1 => row_hit_r_reg(3), + I2 => row_hit_r_reg(5), + I3 => \^row\(5), + I4 => row_hit_r_reg(4), + I5 => \^row\(4), + O => S(1) + ); +row_hit_ns_carry_i_4: unisim.vcomponents.LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => \^row\(0), + I1 => row_hit_r_reg(0), + I2 => row_hit_r_reg(2), + I3 => \^row\(2), + I4 => row_hit_r_reg(1), + I5 => \^row\(1), + O => S(0) + ); +was_wr_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"E200E2E2" + ) + port map ( + I0 => app_cmd_r2(0), + I1 => \^e\(0), + I2 => app_cmd_r1(0), + I3 => periodic_rd_ack_r, + I4 => periodic_rd_r, + O => was_wr0 + ); +\wr_req_counter.wr_req_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"955555956AAAAA6A" + ) + port map ( + I0 => \wr_req_counter.wr_req_cnt_r\(0), + I1 => \^e\(0), + I2 => \^app_en_r2_reg_0\, + I3 => app_cmd_r2(0), + I4 => app_cmd_r2(1), + I5 => p_0_in(0), + O => \wr_req_counter.wr_req_cnt_r_reg[0]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ui_rd_data is + port ( + \not_strict_mode.status_ram.rd_buf_we_r1_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + ADDRA : out STD_LOGIC_VECTOR ( 4 downto 0 ); + DOA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DOB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DOC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_end_reg_0\ : out STD_LOGIC; + \rd_buf_indx.ram_init_done_r_lcl_reg_0\ : out STD_LOGIC; + app_rd_data_valid : out STD_LOGIC; + \not_strict_mode.occ_cnt_r_reg[5]_0\ : out STD_LOGIC; + \not_strict_mode.occ_cnt_r_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 4 downto 0 ); + ADDRD : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \pointer_ram.pointer_wr_data\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 ); + CLK : in STD_LOGIC; + \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[5]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[5]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_end_ns\ : in STD_LOGIC; + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ : in STD_LOGIC; + \not_strict_mode.bypass__0\ : in STD_LOGIC; + rd_accepted : in STD_LOGIC; + \not_strict_mode.occ_cnt_r_reg[5]_1\ : in STD_LOGIC; + \write_data_control.wb_wr_data_addr_r_reg[2]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + wr_data_addr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + D : in STD_LOGIC_VECTOR ( 127 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ui_rd_data : entity is "mig_7series_v4_2_ui_rd_data"; +end ddr3_mig_7series_v4_2_ui_rd_data; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ui_rd_data is + signal \^addra\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal app_rd_data_valid_ns0 : STD_LOGIC; + signal \^not_strict_mode.app_rd_data_end_reg_0\ : STD_LOGIC; + signal \not_strict_mode.app_rd_data_valid_copy\ : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r\ : STD_LOGIC_VECTOR ( 5 downto 2 ); + signal \not_strict_mode.occ_cnt_r[0]_i_1_n_0\ : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r[2]_i_1_n_0\ : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r[3]_i_1_n_0\ : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r[4]_i_1_n_0\ : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r[4]_i_2_n_0\ : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r[5]_i_2_n_0\ : STD_LOGIC; + signal \^not_strict_mode.occ_cnt_r_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^not_strict_mode.occ_cnt_r_reg[5]_0\ : STD_LOGIC; + signal \not_strict_mode.rd_buf.rd_buf_indx_copy_r\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + attribute RTL_KEEP : string; + attribute RTL_KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r\ : signal is "true"; + attribute syn_keep : string; + attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r\ : signal is "true"; + signal \not_strict_mode.rd_status\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \not_strict_mode.status_ram.rd_buf_we_r1\ : STD_LOGIC; + signal \not_strict_mode.status_ram.status_ram_wr_addr_ns\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \not_strict_mode.status_ram.status_ram_wr_addr_r\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \not_strict_mode.status_ram.status_ram_wr_data_r\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \not_strict_mode.status_ram.wr_status\ : STD_LOGIC; + signal \not_strict_mode.status_ram.wr_status_r1\ : STD_LOGIC; + signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \p_0_out__0__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \rd_buf_indx.ram_init_done_ns0\ : STD_LOGIC; + signal \^rd_buf_indx.ram_init_done_r_lcl_reg_0\ : STD_LOGIC; + signal \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0\ : STD_LOGIC; + signal \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5]\ : STD_LOGIC; + signal \rd_buf_indx.upd_rd_buf_indx0\ : STD_LOGIC; + signal rd_buf_indx_ns : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of \not_strict_mode.app_rd_data_valid_copy_reg\ : label is "no"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \not_strict_mode.app_rd_data_valid_i_2\ : label is "soft_lutpair578"; + attribute syn_maxfan : string; + attribute syn_maxfan of \not_strict_mode.app_rd_data_valid_reg\ : label is "10"; + attribute SOFT_HLUTNM of \not_strict_mode.occ_cnt_r[0]_i_1\ : label is "soft_lutpair580"; + attribute SOFT_HLUTNM of \not_strict_mode.occ_cnt_r[1]_i_1\ : label is "soft_lutpair580"; + attribute SOFT_HLUTNM of \not_strict_mode.occ_cnt_r[3]_i_2\ : label is "soft_lutpair579"; + attribute SOFT_HLUTNM of \not_strict_mode.occ_cnt_r[5]_i_1\ : label is "soft_lutpair579"; + attribute KEEP : string; + attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]\ : label is "yes"; + attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]\ : label is "true"; + attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1]\ : label is "yes"; + attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1]\ : label is "true"; + attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2]\ : label is "yes"; + attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2]\ : label is "true"; + attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3]\ : label is "yes"; + attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3]\ : label is "true"; + attribute KEEP of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : label is "yes"; + attribute syn_keep of \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : label is "true"; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[1]_i_1\ : label is "soft_lutpair582"; + attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[2]_i_1\ : label is "soft_lutpair582"; + attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[3]_i_1\ : label is "soft_lutpair581"; + attribute SOFT_HLUTNM of \not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_2\ : label is "soft_lutpair581"; + attribute BOX_TYPE of \not_strict_mode.status_ram.RAM32M0\ : label is "PRIMITIVE"; + attribute syn_maxfan of \rd_buf_indx.ram_init_done_r_lcl_reg\ : label is "10"; + attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[0]_i_1\ : label is "soft_lutpair578"; + attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[4]_i_1\ : label is "soft_lutpair577"; + attribute SOFT_HLUTNM of \rd_buf_indx.rd_buf_indx_r[5]_i_1\ : label is "soft_lutpair577"; +begin + ADDRA(4 downto 0) <= \^addra\(4 downto 0); + Q(4 downto 0) <= \^q\(4 downto 0); + \not_strict_mode.app_rd_data_end_reg_0\ <= \^not_strict_mode.app_rd_data_end_reg_0\; + \not_strict_mode.occ_cnt_r_reg[1]_0\(1 downto 0) <= \^not_strict_mode.occ_cnt_r_reg[1]_0\(1 downto 0); + \not_strict_mode.occ_cnt_r_reg[5]_0\ <= \^not_strict_mode.occ_cnt_r_reg[5]_0\; + \rd_buf_indx.ram_init_done_r_lcl_reg_0\ <= \^rd_buf_indx.ram_init_done_r_lcl_reg_0\; +\not_strict_mode.app_rd_data_end_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.app_rd_data_end_ns\, + Q => \^not_strict_mode.app_rd_data_end_reg_0\, + R => '0' + ); +\not_strict_mode.app_rd_data_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(0), + Q => app_rd_data(0), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[100]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(100), + Q => app_rd_data(100), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[101]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(101), + Q => app_rd_data(101), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[102]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(102), + Q => app_rd_data(102), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[103]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(103), + Q => app_rd_data(103), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[104]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(104), + Q => app_rd_data(104), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[105]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(105), + Q => app_rd_data(105), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[106]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(106), + Q => app_rd_data(106), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[107]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(107), + Q => app_rd_data(107), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[108]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(108), + Q => app_rd_data(108), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[109]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(109), + Q => app_rd_data(109), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(10), + Q => app_rd_data(10), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[110]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(110), + Q => app_rd_data(110), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[111]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(111), + Q => app_rd_data(111), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[112]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(112), + Q => app_rd_data(112), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[113]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(113), + Q => app_rd_data(113), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[114]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(114), + Q => app_rd_data(114), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[115]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(115), + Q => app_rd_data(115), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[116]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(116), + Q => app_rd_data(116), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[117]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(117), + Q => app_rd_data(117), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[118]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(118), + Q => app_rd_data(118), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[119]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(119), + Q => app_rd_data(119), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(11), + Q => app_rd_data(11), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[120]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(120), + Q => app_rd_data(120), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[121]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(121), + Q => app_rd_data(121), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[122]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(122), + Q => app_rd_data(122), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[123]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(123), + Q => app_rd_data(123), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[124]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(124), + Q => app_rd_data(124), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[125]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(125), + Q => app_rd_data(125), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[126]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(126), + Q => app_rd_data(126), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[127]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(127), + Q => app_rd_data(127), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(12), + Q => app_rd_data(12), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(13), + Q => app_rd_data(13), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(14), + Q => app_rd_data(14), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(15), + Q => app_rd_data(15), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(16), + Q => app_rd_data(16), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(17), + Q => app_rd_data(17), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(18), + Q => app_rd_data(18), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(19), + Q => app_rd_data(19), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(1), + Q => app_rd_data(1), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(20), + Q => app_rd_data(20), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(21), + Q => app_rd_data(21), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(22), + Q => app_rd_data(22), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(23), + Q => app_rd_data(23), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(24), + Q => app_rd_data(24), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(25), + Q => app_rd_data(25), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(26), + Q => app_rd_data(26), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(27), + Q => app_rd_data(27), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(28), + Q => app_rd_data(28), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(29), + Q => app_rd_data(29), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(2), + Q => app_rd_data(2), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(30), + Q => app_rd_data(30), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(31), + Q => app_rd_data(31), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(32), + Q => app_rd_data(32), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(33), + Q => app_rd_data(33), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(34), + Q => app_rd_data(34), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(35), + Q => app_rd_data(35), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(36), + Q => app_rd_data(36), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(37), + Q => app_rd_data(37), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(38), + Q => app_rd_data(38), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(39), + Q => app_rd_data(39), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(3), + Q => app_rd_data(3), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(40), + Q => app_rd_data(40), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(41), + Q => app_rd_data(41), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(42), + Q => app_rd_data(42), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(43), + Q => app_rd_data(43), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(44), + Q => app_rd_data(44), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(45), + Q => app_rd_data(45), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(46), + Q => app_rd_data(46), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(47), + Q => app_rd_data(47), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(48), + Q => app_rd_data(48), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(49), + Q => app_rd_data(49), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(4), + Q => app_rd_data(4), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(50), + Q => app_rd_data(50), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(51), + Q => app_rd_data(51), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(52), + Q => app_rd_data(52), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(53), + Q => app_rd_data(53), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(54), + Q => app_rd_data(54), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(55), + Q => app_rd_data(55), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(56), + Q => app_rd_data(56), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(57), + Q => app_rd_data(57), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(58), + Q => app_rd_data(58), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(59), + Q => app_rd_data(59), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(5), + Q => app_rd_data(5), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(60), + Q => app_rd_data(60), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(61), + Q => app_rd_data(61), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(62), + Q => app_rd_data(62), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(63), + Q => app_rd_data(63), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(64), + Q => app_rd_data(64), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(65), + Q => app_rd_data(65), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(66), + Q => app_rd_data(66), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[67]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(67), + Q => app_rd_data(67), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[68]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(68), + Q => app_rd_data(68), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[69]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(69), + Q => app_rd_data(69), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(6), + Q => app_rd_data(6), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[70]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(70), + Q => app_rd_data(70), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[71]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(71), + Q => app_rd_data(71), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[72]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(72), + Q => app_rd_data(72), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[73]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(73), + Q => app_rd_data(73), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[74]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(74), + Q => app_rd_data(74), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[75]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(75), + Q => app_rd_data(75), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[76]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(76), + Q => app_rd_data(76), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[77]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(77), + Q => app_rd_data(77), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[78]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(78), + Q => app_rd_data(78), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[79]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(79), + Q => app_rd_data(79), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(7), + Q => app_rd_data(7), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[80]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(80), + Q => app_rd_data(80), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[81]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(81), + Q => app_rd_data(81), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[82]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(82), + Q => app_rd_data(82), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[83]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(83), + Q => app_rd_data(83), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[84]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(84), + Q => app_rd_data(84), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[85]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(85), + Q => app_rd_data(85), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[86]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(86), + Q => app_rd_data(86), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[87]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(87), + Q => app_rd_data(87), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[88]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(88), + Q => app_rd_data(88), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[89]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(89), + Q => app_rd_data(89), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(8), + Q => app_rd_data(8), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[90]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(90), + Q => app_rd_data(90), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[91]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(91), + Q => app_rd_data(91), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[92]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(92), + Q => app_rd_data(92), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[93]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(93), + Q => app_rd_data(93), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[94]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(94), + Q => app_rd_data(94), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[95]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(95), + Q => app_rd_data(95), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[96]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(96), + Q => app_rd_data(96), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[97]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(97), + Q => app_rd_data(97), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[98]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(98), + Q => app_rd_data(98), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[99]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(99), + Q => app_rd_data(99), + R => '0' + ); +\not_strict_mode.app_rd_data_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => D(9), + Q => app_rd_data(9), + R => '0' + ); +\not_strict_mode.app_rd_data_valid_copy_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => app_rd_data_valid_ns0, + Q => \not_strict_mode.app_rd_data_valid_copy\, + R => \rd_buf_indx.upd_rd_buf_indx0\ + ); +\not_strict_mode.app_rd_data_valid_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + O => \rd_buf_indx.upd_rd_buf_indx0\ + ); +\not_strict_mode.app_rd_data_valid_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"EB" + ) + port map ( + I0 => \not_strict_mode.bypass__0\, + I1 => \not_strict_mode.rd_status\(0), + I2 => \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5]\, + O => app_rd_data_valid_ns0 + ); +\not_strict_mode.app_rd_data_valid_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => app_rd_data_valid_ns0, + Q => app_rd_data_valid, + R => \rd_buf_indx.upd_rd_buf_indx0\ + ); +\not_strict_mode.occ_cnt_r[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"9666" + ) + port map ( + I0 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0), + I1 => rd_accepted, + I2 => \not_strict_mode.app_rd_data_valid_copy\, + I3 => \^not_strict_mode.app_rd_data_end_reg_0\, + O => \not_strict_mode.occ_cnt_r[0]_i_1_n_0\ + ); +\not_strict_mode.occ_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A6669AAA" + ) + port map ( + I0 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1), + I1 => rd_accepted, + I2 => \not_strict_mode.app_rd_data_valid_copy\, + I3 => \^not_strict_mode.app_rd_data_end_reg_0\, + I4 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0), + O => \not_strict_mode.occ_cnt_r[1]_i_1_n_0\ + ); +\not_strict_mode.occ_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A666AAAAAAAA9AAA" + ) + port map ( + I0 => \not_strict_mode.occ_cnt_r\(2), + I1 => rd_accepted, + I2 => \not_strict_mode.app_rd_data_valid_copy\, + I3 => \^not_strict_mode.app_rd_data_end_reg_0\, + I4 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1), + I5 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0), + O => \not_strict_mode.occ_cnt_r[2]_i_1_n_0\ + ); +\not_strict_mode.occ_cnt_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A6AAAAAAAAAAAA9A" + ) + port map ( + I0 => \not_strict_mode.occ_cnt_r\(3), + I1 => rd_accepted, + I2 => \p_0_out__0\(0), + I3 => \not_strict_mode.occ_cnt_r\(2), + I4 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1), + I5 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0), + O => \not_strict_mode.occ_cnt_r[3]_i_1_n_0\ + ); +\not_strict_mode.occ_cnt_r[3]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \not_strict_mode.app_rd_data_valid_copy\, + I1 => \^not_strict_mode.app_rd_data_end_reg_0\, + O => \p_0_out__0\(0) + ); +\not_strict_mode.occ_cnt_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"9666AAAAAAAA9666" + ) + port map ( + I0 => \not_strict_mode.occ_cnt_r\(4), + I1 => rd_accepted, + I2 => \not_strict_mode.app_rd_data_valid_copy\, + I3 => \^not_strict_mode.app_rd_data_end_reg_0\, + I4 => \not_strict_mode.occ_cnt_r\(3), + I5 => \not_strict_mode.occ_cnt_r[4]_i_2_n_0\, + O => \not_strict_mode.occ_cnt_r[4]_i_1_n_0\ + ); +\not_strict_mode.occ_cnt_r[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"D5555554" + ) + port map ( + I0 => \not_strict_mode.occ_cnt_r\(3), + I1 => \not_strict_mode.occ_cnt_r\(2), + I2 => rd_accepted, + I3 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0), + I4 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1), + O => \not_strict_mode.occ_cnt_r[4]_i_2_n_0\ + ); +\not_strict_mode.occ_cnt_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BEEE8222" + ) + port map ( + I0 => \not_strict_mode.occ_cnt_r\(5), + I1 => rd_accepted, + I2 => \not_strict_mode.app_rd_data_valid_copy\, + I3 => \^not_strict_mode.app_rd_data_end_reg_0\, + I4 => \not_strict_mode.occ_cnt_r[5]_i_2_n_0\, + O => \^not_strict_mode.occ_cnt_r_reg[5]_0\ + ); +\not_strict_mode.occ_cnt_r[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7FFF8000FFFE0001" + ) + port map ( + I0 => \not_strict_mode.occ_cnt_r\(2), + I1 => \not_strict_mode.occ_cnt_r_reg[5]_1\, + I2 => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1), + I3 => \not_strict_mode.occ_cnt_r\(3), + I4 => \not_strict_mode.occ_cnt_r\(5), + I5 => \not_strict_mode.occ_cnt_r\(4), + O => \not_strict_mode.occ_cnt_r[5]_i_2_n_0\ + ); +\not_strict_mode.occ_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.occ_cnt_r[0]_i_1_n_0\, + Q => \^not_strict_mode.occ_cnt_r_reg[1]_0\(0), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.occ_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.occ_cnt_r[1]_i_1_n_0\, + Q => \^not_strict_mode.occ_cnt_r_reg[1]_0\(1), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.occ_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.occ_cnt_r[2]_i_1_n_0\, + Q => \not_strict_mode.occ_cnt_r\(2), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.occ_cnt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.occ_cnt_r[3]_i_1_n_0\, + Q => \not_strict_mode.occ_cnt_r\(3), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.occ_cnt_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.occ_cnt_r[4]_i_1_n_0\, + Q => \not_strict_mode.occ_cnt_r\(4), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.occ_cnt_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^not_strict_mode.occ_cnt_r_reg[5]_0\, + Q => \not_strict_mode.occ_cnt_r\(5), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(0), + Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(0), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(1), + Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(1), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(2), + Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(2), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(3), + Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(3), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(4), + Q => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[5]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[5]_1\(1 downto 0), + DIC(1 downto 0) => DIC(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]_0\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]_1\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]_0\(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]_1\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRB(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRC(4 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5 downto 1), + DIA(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]_0\(1 downto 0), + DIB(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]_1\(1 downto 0), + DIC(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]_2\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0), + DOB(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0), + DOC(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0), + DOD(1 downto 0) => \NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ + ); +\not_strict_mode.rd_data_buf_addr_r_lcl[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^q\(0), + O => \p_0_in__2\(0) + ); +\not_strict_mode.rd_data_buf_addr_r_lcl[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => \p_0_in__2\(1) + ); +\not_strict_mode.rd_data_buf_addr_r_lcl[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + O => \p_0_in__2\(2) + ); +\not_strict_mode.rd_data_buf_addr_r_lcl[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + I3 => \^q\(3), + O => \p_0_in__2\(3) + ); +\not_strict_mode.rd_data_buf_addr_r_lcl[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \^q\(2), + I1 => \^q\(0), + I2 => \^q\(1), + I3 => \^q\(3), + I4 => \^q\(4), + O => \p_0_in__2\(4) + ); +\not_strict_mode.rd_data_buf_addr_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_accepted, + D => \p_0_in__2\(0), + Q => \^q\(0), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_data_buf_addr_r_lcl_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_accepted, + D => \p_0_in__2\(1), + Q => \^q\(1), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_data_buf_addr_r_lcl_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_accepted, + D => \p_0_in__2\(2), + Q => \^q\(2), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_data_buf_addr_r_lcl_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_accepted, + D => \p_0_in__2\(3), + Q => \^q\(3), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => rd_accepted, + D => \p_0_in__2\(4), + Q => \^q\(4), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\not_strict_mode.status_ram.RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => \^addra\(4 downto 0), + ADDRB(4 downto 0) => B"00000", + ADDRC(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(4 downto 0), + ADDRD(4 downto 0) => \not_strict_mode.status_ram.status_ram_wr_addr_r\(4 downto 0), + DIA(1 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r\(1 downto 0), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r\(1 downto 0), + DID(1 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r\(1 downto 0), + DOA(1) => \not_strict_mode.status_ram.rd_buf_we_r1_reg_0\(0), + DOA(0) => \not_strict_mode.rd_status\(0), + DOB(1 downto 0) => \NLW_not_strict_mode.status_ram.RAM32M0_DOB_UNCONNECTED\(1 downto 0), + DOC(1) => \NLW_not_strict_mode.status_ram.RAM32M0_DOC_UNCONNECTED\(1), + DOC(0) => \not_strict_mode.status_ram.wr_status\, + DOD(1 downto 0) => \NLW_not_strict_mode.status_ram.RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \not_strict_mode.status_ram.rd_buf_we_r1\ + ); +\not_strict_mode.status_ram.RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(5), + I1 => \^addra\(4), + I2 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(4) + ); +\not_strict_mode.status_ram.RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(4), + I1 => \^addra\(3), + I2 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(3) + ); +\not_strict_mode.status_ram.RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(3), + I1 => \^addra\(2), + I2 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(2) + ); +\not_strict_mode.status_ram.RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(2), + I1 => \^addra\(1), + I2 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(1) + ); +\not_strict_mode.status_ram.RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(1), + I1 => \^addra\(0), + I2 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + O => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(0) + ); +\not_strict_mode.status_ram.rd_buf_we_r1_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\, + Q => \not_strict_mode.status_ram.rd_buf_we_r1\, + R => '0' + ); +\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(0), + Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(0), + R => '0' + ); +\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(1), + Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(1), + R => '0' + ); +\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(2), + Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(2), + R => '0' + ); +\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(3), + Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(3), + R => '0' + ); +\not_strict_mode.status_ram.status_ram_wr_addr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.status_ram_wr_addr_ns\(4), + Q => \not_strict_mode.status_ram.status_ram_wr_addr_r\(4), + R => '0' + ); +\not_strict_mode.status_ram.status_ram_wr_data_r[0]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"1D" + ) + port map ( + I0 => \not_strict_mode.status_ram.wr_status\, + I1 => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(0), + I2 => \not_strict_mode.status_ram.wr_status_r1\, + O => \p_0_out__0__0\(0) + ); +\not_strict_mode.status_ram.status_ram_wr_data_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \p_0_out__0__0\(0), + Q => \not_strict_mode.status_ram.status_ram_wr_data_r\(0), + R => \rd_buf_indx.upd_rd_buf_indx0\ + ); +\not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(6), + Q => \not_strict_mode.status_ram.status_ram_wr_data_r\(1), + R => \rd_buf_indx.upd_rd_buf_indx0\ + ); +\not_strict_mode.status_ram.wr_status_r1_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \not_strict_mode.status_ram.wr_status\, + Q => \not_strict_mode.status_ram.wr_status_r1\, + R => '0' + ); +\pointer_ram.rams[0].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => wr_data_addr(1), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(1), + O => \pointer_ram.pointer_wr_data\(1) + ); +\pointer_ram.rams[0].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => wr_data_addr(0), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(0), + O => \pointer_ram.pointer_wr_data\(0) + ); +\pointer_ram.rams[0].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r_reg[2]\(3), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(3), + O => ADDRD(3) + ); +\pointer_ram.rams[0].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r_reg[2]\(2), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(2), + O => ADDRD(2) + ); +\pointer_ram.rams[0].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r_reg[2]\(1), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(1), + O => ADDRD(1) + ); +\pointer_ram.rams[0].RAM32M0_i_7\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r_reg[2]\(0), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(0), + O => ADDRD(0) + ); +\pointer_ram.rams[1].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => wr_data_addr(3), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(3), + O => \pointer_ram.pointer_wr_data\(3) + ); +\pointer_ram.rams[1].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => wr_data_addr(2), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \^addra\(2), + O => \pointer_ram.pointer_wr_data\(2) + ); +\rd_buf_indx.ram_init_done_r_lcl_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"EAAAAAAAAAAAAAAA" + ) + port map ( + I0 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I1 => \^addra\(2), + I2 => \^addra\(4), + I3 => \^addra\(0), + I4 => \^addra\(1), + I5 => \^addra\(3), + O => \rd_buf_indx.ram_init_done_ns0\ + ); +\rd_buf_indx.ram_init_done_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rd_buf_indx.ram_init_done_ns0\, + Q => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\rd_buf_indx.rd_buf_indx_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"55555995" + ) + port map ( + I0 => \^addra\(0), + I1 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I2 => \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5]\, + I3 => \not_strict_mode.rd_status\(0), + I4 => \not_strict_mode.bypass__0\, + O => rd_buf_indx_ns(0) + ); +\rd_buf_indx.rd_buf_indx_r[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"57755555A88AAAAA" + ) + port map ( + I0 => \^addra\(0), + I1 => \not_strict_mode.bypass__0\, + I2 => \not_strict_mode.rd_status\(0), + I3 => \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5]\, + I4 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I5 => \^addra\(1), + O => rd_buf_indx_ns(1) + ); +\rd_buf_indx.rd_buf_indx_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"2FFFD000" + ) + port map ( + I0 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I1 => app_rd_data_valid_ns0, + I2 => \^addra\(0), + I3 => \^addra\(1), + I4 => \^addra\(2), + O => rd_buf_indx_ns(2) + ); +\rd_buf_indx.rd_buf_indx_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"7F77FFFF80880000" + ) + port map ( + I0 => \^addra\(1), + I1 => \^addra\(0), + I2 => app_rd_data_valid_ns0, + I3 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + I4 => \^addra\(2), + I5 => \^addra\(3), + O => rd_buf_indx_ns(3) + ); +\rd_buf_indx.rd_buf_indx_r[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^addra\(2), + I1 => \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0\, + I2 => \^addra\(3), + I3 => \^addra\(4), + O => rd_buf_indx_ns(4) + ); +\rd_buf_indx.rd_buf_indx_r[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"7FFF8000" + ) + port map ( + I0 => \^addra\(3), + I1 => \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0\, + I2 => \^addra\(2), + I3 => \^addra\(4), + I4 => \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5]\, + O => rd_buf_indx_ns(5) + ); +\rd_buf_indx.rd_buf_indx_r[5]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"8880808888888888" + ) + port map ( + I0 => \^addra\(1), + I1 => \^addra\(0), + I2 => \not_strict_mode.bypass__0\, + I3 => \not_strict_mode.rd_status\(0), + I4 => \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5]\, + I5 => \^rd_buf_indx.ram_init_done_r_lcl_reg_0\, + O => \rd_buf_indx.rd_buf_indx_r[5]_i_2_n_0\ + ); +\rd_buf_indx.rd_buf_indx_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(0), + Q => \^addra\(0), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\rd_buf_indx.rd_buf_indx_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(1), + Q => \^addra\(1), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\rd_buf_indx.rd_buf_indx_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(2), + Q => \^addra\(2), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\rd_buf_indx.rd_buf_indx_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(3), + Q => \^addra\(3), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\rd_buf_indx.rd_buf_indx_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(4), + Q => \^addra\(4), + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +\rd_buf_indx.rd_buf_indx_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_buf_indx_ns(5), + Q => \rd_buf_indx.rd_buf_indx_r_reg_n_0_[5]\, + R => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ui_wr_data is + port ( + wr_data_buf_addr : out STD_LOGIC_VECTOR ( 3 downto 0 ); + p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 ); + app_wdf_rdy : out STD_LOGIC; + app_rdy_ns : out STD_LOGIC; + \wr_req_counter.wr_req_cnt_r_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \write_buffer.wr_buf_out_data_reg[37]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + \write_buffer.wr_buf_out_data_reg[143]_0\ : out STD_LOGIC_VECTOR ( 143 downto 0 ); + \write_buffer.wr_buf_out_data_reg[95]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + CLK : in STD_LOGIC; + \write_data_control.wb_wr_data_addr_r_reg[2]_0\ : in STD_LOGIC; + \pointer_ram.pointer_wr_data\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + ADDRD : in STD_LOGIC_VECTOR ( 3 downto 0 ); + wr_data_addr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + app_wdf_end_r1_reg_0 : in STD_LOGIC; + app_wdf_wren : in STD_LOGIC; + app_wdf_end : in STD_LOGIC; + accept_ns : in STD_LOGIC; + app_rdy_r_reg : in STD_LOGIC; + wr_accepted : in STD_LOGIC; + ram_init_done_r : in STD_LOGIC; + app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 ); + app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : in STD_LOGIC; + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : in STD_LOGIC; + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\ : in STD_LOGIC; + \wr_req_counter.wr_req_cnt_r_reg[0]_1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ui_wr_data : entity is "mig_7series_v4_2_ui_wr_data"; +end ddr3_mig_7series_v4_2_ui_wr_data; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ui_wr_data is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal app_rdy_r_i_2_n_0 : STD_LOGIC; + signal app_wdf_data_r1 : STD_LOGIC_VECTOR ( 127 downto 0 ); + signal app_wdf_end_r1 : STD_LOGIC; + signal app_wdf_end_r1_i_1_n_0 : STD_LOGIC; + signal app_wdf_mask_r1 : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal app_wdf_rdy_r_copy1 : STD_LOGIC; + signal app_wdf_rdy_r_copy2 : STD_LOGIC; + signal app_wdf_rdy_r_copy3 : STD_LOGIC; + signal app_wdf_wren_r1 : STD_LOGIC; + signal app_wdf_wren_r1_i_1_n_0 : STD_LOGIC; + signal \data_buf_address_counter.data_buf_addr_cnt_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \occupied_counter.occ_cnt[0]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[10]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[11]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[12]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[13]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[14]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[15]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[15]_i_2_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[1]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[2]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[3]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[4]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[5]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[6]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[7]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[8]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt[9]_i_1_n_0\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[10]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[11]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[12]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[13]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[15]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[2]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[3]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[4]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[5]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[6]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[7]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[8]\ : STD_LOGIC; + signal \occupied_counter.occ_cnt_reg_n_0_[9]\ : STD_LOGIC; + signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__0_0\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \p_0_in__0__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal p_4_in : STD_LOGIC; + signal wdf_rdy_ns : STD_LOGIC; + signal wr_buf_out_data_w : STD_LOGIC_VECTOR ( 143 downto 0 ); + signal wr_data_pntr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 4 downto 1 ); + signal \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\ : STD_LOGIC; + signal \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\ : STD_LOGIC; + signal \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\ : STD_LOGIC; + signal \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\ : STD_LOGIC; + signal \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\ : STD_LOGIC; + signal \^wr_req_counter.wr_req_cnt_r_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \write_buffer.wr_buf_in_data\ : STD_LOGIC_VECTOR ( 143 downto 0 ); + signal \^write_buffer.wr_buf_out_data_reg[143]_0\ : STD_LOGIC_VECTOR ( 143 downto 0 ); + signal \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\ : STD_LOGIC; + signal \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\ : STD_LOGIC; + signal \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\ : STD_LOGIC; + signal \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\ : STD_LOGIC; + signal \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\ : STD_LOGIC; + signal \write_data_control.wb_wr_data_addr0_ns02_in\ : STD_LOGIC; + signal \write_data_control.wb_wr_data_addr0_r\ : STD_LOGIC; + signal \write_data_control.wb_wr_data_addr_r\ : STD_LOGIC_VECTOR ( 4 downto 1 ); + signal \write_data_control.wr_data_addr_le__2\ : STD_LOGIC; + signal \write_data_control.wr_data_indx_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of app_wdf_end_r1_i_1 : label is "soft_lutpair590"; + attribute equivalent_register_removal : string; + attribute equivalent_register_removal of app_wdf_rdy_r_copy1_reg : label is "no"; + attribute equivalent_register_removal of app_wdf_rdy_r_copy2_reg : label is "no"; + attribute equivalent_register_removal of app_wdf_rdy_r_copy3_reg : label is "no"; + attribute SOFT_HLUTNM of app_wdf_wren_r1_i_1 : label is "soft_lutpair590"; + attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\ : label is "soft_lutpair591"; + attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\ : label is "soft_lutpair591"; + attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\ : label is "soft_lutpair587"; + attribute SOFT_HLUTNM of \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\ : label is "soft_lutpair587"; + attribute SOFT_HLUTNM of \occupied_counter.app_wdf_rdy_r_i_2\ : label is "soft_lutpair584"; + attribute equivalent_register_removal of \occupied_counter.app_wdf_rdy_r_reg\ : label is "no"; + attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[0]_i_1\ : label is "soft_lutpair585"; + attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[13]_i_1\ : label is "soft_lutpair586"; + attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[15]_i_2\ : label is "soft_lutpair586"; + attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[1]_i_1\ : label is "soft_lutpair584"; + attribute SOFT_HLUTNM of \occupied_counter.occ_cnt[2]_i_1\ : label is "soft_lutpair585"; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \pointer_ram.rams[0].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \pointer_ram.rams[1].RAM32M0\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[0]_i_1\ : label is "soft_lutpair592"; + attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[1]_i_1\ : label is "soft_lutpair592"; + attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[2]_i_1\ : label is "soft_lutpair589"; + attribute SOFT_HLUTNM of \read_data_indx.rd_data_indx_r[3]_i_1\ : label is "soft_lutpair589"; + attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[2]_i_1\ : label is "soft_lutpair583"; + attribute SOFT_HLUTNM of \wr_req_counter.wr_req_cnt_r[4]_i_2\ : label is "soft_lutpair583"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[0].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[10].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[11].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[12].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[13].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[14].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[15].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[16].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[17].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[18].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[19].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[1].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[20].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[21].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[22].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[23].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[2].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[3].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[4].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[5].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[6].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[7].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[8].RAM32M0\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \write_buffer.wr_buffer_ram[9].RAM32M0\ : label is "PRIMITIVE"; + attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[2]_i_1\ : label is "soft_lutpair588"; + attribute SOFT_HLUTNM of \write_data_control.wr_data_indx_r[3]_i_1\ : label is "soft_lutpair588"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); + p_0_in(0) <= \^p_0_in\(0); + \wr_req_counter.wr_req_cnt_r_reg[0]_0\(0) <= \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0); + \write_buffer.wr_buf_out_data_reg[143]_0\(143 downto 0) <= \^write_buffer.wr_buf_out_data_reg[143]_0\(143 downto 0); +app_rdy_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"A2A2A2A202020200" + ) + port map ( + I0 => accept_ns, + I1 => app_rdy_r_reg, + I2 => app_wdf_end_r1_reg_0, + I3 => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\, + I4 => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\, + I5 => app_rdy_r_i_2_n_0, + O => app_rdy_ns + ); +app_rdy_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFDBBEFFFFFFFF" + ) + port map ( + I0 => \wr_req_counter.wr_req_cnt_r\(1), + I1 => \^p_0_in\(0), + I2 => wr_accepted, + I3 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0), + I4 => app_wdf_end_r1_reg_0, + I5 => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\, + O => app_rdy_r_i_2_n_0 + ); +\app_wdf_data_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(0), + Q => app_wdf_data_r1(0), + R => '0' + ); +\app_wdf_data_r1_reg[100]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(100), + Q => app_wdf_data_r1(100), + R => '0' + ); +\app_wdf_data_r1_reg[101]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(101), + Q => app_wdf_data_r1(101), + R => '0' + ); +\app_wdf_data_r1_reg[102]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(102), + Q => app_wdf_data_r1(102), + R => '0' + ); +\app_wdf_data_r1_reg[103]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(103), + Q => app_wdf_data_r1(103), + R => '0' + ); +\app_wdf_data_r1_reg[104]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(104), + Q => app_wdf_data_r1(104), + R => '0' + ); +\app_wdf_data_r1_reg[105]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(105), + Q => app_wdf_data_r1(105), + R => '0' + ); +\app_wdf_data_r1_reg[106]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(106), + Q => app_wdf_data_r1(106), + R => '0' + ); +\app_wdf_data_r1_reg[107]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(107), + Q => app_wdf_data_r1(107), + R => '0' + ); +\app_wdf_data_r1_reg[108]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(108), + Q => app_wdf_data_r1(108), + R => '0' + ); +\app_wdf_data_r1_reg[109]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(109), + Q => app_wdf_data_r1(109), + R => '0' + ); +\app_wdf_data_r1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(10), + Q => app_wdf_data_r1(10), + R => '0' + ); +\app_wdf_data_r1_reg[110]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(110), + Q => app_wdf_data_r1(110), + R => '0' + ); +\app_wdf_data_r1_reg[111]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(111), + Q => app_wdf_data_r1(111), + R => '0' + ); +\app_wdf_data_r1_reg[112]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(112), + Q => app_wdf_data_r1(112), + R => '0' + ); +\app_wdf_data_r1_reg[113]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(113), + Q => app_wdf_data_r1(113), + R => '0' + ); +\app_wdf_data_r1_reg[114]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(114), + Q => app_wdf_data_r1(114), + R => '0' + ); +\app_wdf_data_r1_reg[115]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(115), + Q => app_wdf_data_r1(115), + R => '0' + ); +\app_wdf_data_r1_reg[116]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(116), + Q => app_wdf_data_r1(116), + R => '0' + ); +\app_wdf_data_r1_reg[117]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(117), + Q => app_wdf_data_r1(117), + R => '0' + ); +\app_wdf_data_r1_reg[118]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(118), + Q => app_wdf_data_r1(118), + R => '0' + ); +\app_wdf_data_r1_reg[119]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(119), + Q => app_wdf_data_r1(119), + R => '0' + ); +\app_wdf_data_r1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(11), + Q => app_wdf_data_r1(11), + R => '0' + ); +\app_wdf_data_r1_reg[120]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(120), + Q => app_wdf_data_r1(120), + R => '0' + ); +\app_wdf_data_r1_reg[121]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(121), + Q => app_wdf_data_r1(121), + R => '0' + ); +\app_wdf_data_r1_reg[122]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(122), + Q => app_wdf_data_r1(122), + R => '0' + ); +\app_wdf_data_r1_reg[123]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(123), + Q => app_wdf_data_r1(123), + R => '0' + ); +\app_wdf_data_r1_reg[124]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(124), + Q => app_wdf_data_r1(124), + R => '0' + ); +\app_wdf_data_r1_reg[125]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(125), + Q => app_wdf_data_r1(125), + R => '0' + ); +\app_wdf_data_r1_reg[126]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(126), + Q => app_wdf_data_r1(126), + R => '0' + ); +\app_wdf_data_r1_reg[127]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(127), + Q => app_wdf_data_r1(127), + R => '0' + ); +\app_wdf_data_r1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(12), + Q => app_wdf_data_r1(12), + R => '0' + ); +\app_wdf_data_r1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(13), + Q => app_wdf_data_r1(13), + R => '0' + ); +\app_wdf_data_r1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(14), + Q => app_wdf_data_r1(14), + R => '0' + ); +\app_wdf_data_r1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(15), + Q => app_wdf_data_r1(15), + R => '0' + ); +\app_wdf_data_r1_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(16), + Q => app_wdf_data_r1(16), + R => '0' + ); +\app_wdf_data_r1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(17), + Q => app_wdf_data_r1(17), + R => '0' + ); +\app_wdf_data_r1_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(18), + Q => app_wdf_data_r1(18), + R => '0' + ); +\app_wdf_data_r1_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(19), + Q => app_wdf_data_r1(19), + R => '0' + ); +\app_wdf_data_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(1), + Q => app_wdf_data_r1(1), + R => '0' + ); +\app_wdf_data_r1_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(20), + Q => app_wdf_data_r1(20), + R => '0' + ); +\app_wdf_data_r1_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(21), + Q => app_wdf_data_r1(21), + R => '0' + ); +\app_wdf_data_r1_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(22), + Q => app_wdf_data_r1(22), + R => '0' + ); +\app_wdf_data_r1_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(23), + Q => app_wdf_data_r1(23), + R => '0' + ); +\app_wdf_data_r1_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(24), + Q => app_wdf_data_r1(24), + R => '0' + ); +\app_wdf_data_r1_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(25), + Q => app_wdf_data_r1(25), + R => '0' + ); +\app_wdf_data_r1_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(26), + Q => app_wdf_data_r1(26), + R => '0' + ); +\app_wdf_data_r1_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(27), + Q => app_wdf_data_r1(27), + R => '0' + ); +\app_wdf_data_r1_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(28), + Q => app_wdf_data_r1(28), + R => '0' + ); +\app_wdf_data_r1_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(29), + Q => app_wdf_data_r1(29), + R => '0' + ); +\app_wdf_data_r1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(2), + Q => app_wdf_data_r1(2), + R => '0' + ); +\app_wdf_data_r1_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(30), + Q => app_wdf_data_r1(30), + R => '0' + ); +\app_wdf_data_r1_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(31), + Q => app_wdf_data_r1(31), + R => '0' + ); +\app_wdf_data_r1_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(32), + Q => app_wdf_data_r1(32), + R => '0' + ); +\app_wdf_data_r1_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(33), + Q => app_wdf_data_r1(33), + R => '0' + ); +\app_wdf_data_r1_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(34), + Q => app_wdf_data_r1(34), + R => '0' + ); +\app_wdf_data_r1_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(35), + Q => app_wdf_data_r1(35), + R => '0' + ); +\app_wdf_data_r1_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(36), + Q => app_wdf_data_r1(36), + R => '0' + ); +\app_wdf_data_r1_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(37), + Q => app_wdf_data_r1(37), + R => '0' + ); +\app_wdf_data_r1_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(38), + Q => app_wdf_data_r1(38), + R => '0' + ); +\app_wdf_data_r1_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(39), + Q => app_wdf_data_r1(39), + R => '0' + ); +\app_wdf_data_r1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(3), + Q => app_wdf_data_r1(3), + R => '0' + ); +\app_wdf_data_r1_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(40), + Q => app_wdf_data_r1(40), + R => '0' + ); +\app_wdf_data_r1_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(41), + Q => app_wdf_data_r1(41), + R => '0' + ); +\app_wdf_data_r1_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(42), + Q => app_wdf_data_r1(42), + R => '0' + ); +\app_wdf_data_r1_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(43), + Q => app_wdf_data_r1(43), + R => '0' + ); +\app_wdf_data_r1_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(44), + Q => app_wdf_data_r1(44), + R => '0' + ); +\app_wdf_data_r1_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(45), + Q => app_wdf_data_r1(45), + R => '0' + ); +\app_wdf_data_r1_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(46), + Q => app_wdf_data_r1(46), + R => '0' + ); +\app_wdf_data_r1_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(47), + Q => app_wdf_data_r1(47), + R => '0' + ); +\app_wdf_data_r1_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(48), + Q => app_wdf_data_r1(48), + R => '0' + ); +\app_wdf_data_r1_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(49), + Q => app_wdf_data_r1(49), + R => '0' + ); +\app_wdf_data_r1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(4), + Q => app_wdf_data_r1(4), + R => '0' + ); +\app_wdf_data_r1_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(50), + Q => app_wdf_data_r1(50), + R => '0' + ); +\app_wdf_data_r1_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(51), + Q => app_wdf_data_r1(51), + R => '0' + ); +\app_wdf_data_r1_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(52), + Q => app_wdf_data_r1(52), + R => '0' + ); +\app_wdf_data_r1_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(53), + Q => app_wdf_data_r1(53), + R => '0' + ); +\app_wdf_data_r1_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(54), + Q => app_wdf_data_r1(54), + R => '0' + ); +\app_wdf_data_r1_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(55), + Q => app_wdf_data_r1(55), + R => '0' + ); +\app_wdf_data_r1_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(56), + Q => app_wdf_data_r1(56), + R => '0' + ); +\app_wdf_data_r1_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(57), + Q => app_wdf_data_r1(57), + R => '0' + ); +\app_wdf_data_r1_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(58), + Q => app_wdf_data_r1(58), + R => '0' + ); +\app_wdf_data_r1_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(59), + Q => app_wdf_data_r1(59), + R => '0' + ); +\app_wdf_data_r1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(5), + Q => app_wdf_data_r1(5), + R => '0' + ); +\app_wdf_data_r1_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(60), + Q => app_wdf_data_r1(60), + R => '0' + ); +\app_wdf_data_r1_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(61), + Q => app_wdf_data_r1(61), + R => '0' + ); +\app_wdf_data_r1_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(62), + Q => app_wdf_data_r1(62), + R => '0' + ); +\app_wdf_data_r1_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(63), + Q => app_wdf_data_r1(63), + R => '0' + ); +\app_wdf_data_r1_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(64), + Q => app_wdf_data_r1(64), + R => '0' + ); +\app_wdf_data_r1_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(65), + Q => app_wdf_data_r1(65), + R => '0' + ); +\app_wdf_data_r1_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(66), + Q => app_wdf_data_r1(66), + R => '0' + ); +\app_wdf_data_r1_reg[67]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(67), + Q => app_wdf_data_r1(67), + R => '0' + ); +\app_wdf_data_r1_reg[68]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(68), + Q => app_wdf_data_r1(68), + R => '0' + ); +\app_wdf_data_r1_reg[69]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(69), + Q => app_wdf_data_r1(69), + R => '0' + ); +\app_wdf_data_r1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(6), + Q => app_wdf_data_r1(6), + R => '0' + ); +\app_wdf_data_r1_reg[70]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(70), + Q => app_wdf_data_r1(70), + R => '0' + ); +\app_wdf_data_r1_reg[71]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(71), + Q => app_wdf_data_r1(71), + R => '0' + ); +\app_wdf_data_r1_reg[72]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(72), + Q => app_wdf_data_r1(72), + R => '0' + ); +\app_wdf_data_r1_reg[73]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(73), + Q => app_wdf_data_r1(73), + R => '0' + ); +\app_wdf_data_r1_reg[74]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(74), + Q => app_wdf_data_r1(74), + R => '0' + ); +\app_wdf_data_r1_reg[75]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(75), + Q => app_wdf_data_r1(75), + R => '0' + ); +\app_wdf_data_r1_reg[76]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(76), + Q => app_wdf_data_r1(76), + R => '0' + ); +\app_wdf_data_r1_reg[77]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(77), + Q => app_wdf_data_r1(77), + R => '0' + ); +\app_wdf_data_r1_reg[78]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(78), + Q => app_wdf_data_r1(78), + R => '0' + ); +\app_wdf_data_r1_reg[79]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(79), + Q => app_wdf_data_r1(79), + R => '0' + ); +\app_wdf_data_r1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(7), + Q => app_wdf_data_r1(7), + R => '0' + ); +\app_wdf_data_r1_reg[80]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(80), + Q => app_wdf_data_r1(80), + R => '0' + ); +\app_wdf_data_r1_reg[81]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(81), + Q => app_wdf_data_r1(81), + R => '0' + ); +\app_wdf_data_r1_reg[82]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(82), + Q => app_wdf_data_r1(82), + R => '0' + ); +\app_wdf_data_r1_reg[83]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(83), + Q => app_wdf_data_r1(83), + R => '0' + ); +\app_wdf_data_r1_reg[84]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(84), + Q => app_wdf_data_r1(84), + R => '0' + ); +\app_wdf_data_r1_reg[85]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(85), + Q => app_wdf_data_r1(85), + R => '0' + ); +\app_wdf_data_r1_reg[86]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(86), + Q => app_wdf_data_r1(86), + R => '0' + ); +\app_wdf_data_r1_reg[87]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(87), + Q => app_wdf_data_r1(87), + R => '0' + ); +\app_wdf_data_r1_reg[88]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(88), + Q => app_wdf_data_r1(88), + R => '0' + ); +\app_wdf_data_r1_reg[89]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(89), + Q => app_wdf_data_r1(89), + R => '0' + ); +\app_wdf_data_r1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(8), + Q => app_wdf_data_r1(8), + R => '0' + ); +\app_wdf_data_r1_reg[90]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(90), + Q => app_wdf_data_r1(90), + R => '0' + ); +\app_wdf_data_r1_reg[91]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(91), + Q => app_wdf_data_r1(91), + R => '0' + ); +\app_wdf_data_r1_reg[92]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(92), + Q => app_wdf_data_r1(92), + R => '0' + ); +\app_wdf_data_r1_reg[93]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(93), + Q => app_wdf_data_r1(93), + R => '0' + ); +\app_wdf_data_r1_reg[94]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(94), + Q => app_wdf_data_r1(94), + R => '0' + ); +\app_wdf_data_r1_reg[95]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(95), + Q => app_wdf_data_r1(95), + R => '0' + ); +\app_wdf_data_r1_reg[96]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(96), + Q => app_wdf_data_r1(96), + R => '0' + ); +\app_wdf_data_r1_reg[97]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(97), + Q => app_wdf_data_r1(97), + R => '0' + ); +\app_wdf_data_r1_reg[98]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(98), + Q => app_wdf_data_r1(98), + R => '0' + ); +\app_wdf_data_r1_reg[99]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(99), + Q => app_wdf_data_r1(99), + R => '0' + ); +\app_wdf_data_r1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_data(9), + Q => app_wdf_data_r1(9), + R => '0' + ); +app_wdf_end_r1_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => app_wdf_end, + I1 => app_wdf_rdy_r_copy2, + I2 => app_wdf_end_r1, + O => app_wdf_end_r1_i_1_n_0 + ); +app_wdf_end_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => app_wdf_end_r1_i_1_n_0, + Q => app_wdf_end_r1, + R => app_wdf_end_r1_reg_0 + ); +\app_wdf_mask_r1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(0), + Q => app_wdf_mask_r1(0), + R => '0' + ); +\app_wdf_mask_r1_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(10), + Q => app_wdf_mask_r1(10), + R => '0' + ); +\app_wdf_mask_r1_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(11), + Q => app_wdf_mask_r1(11), + R => '0' + ); +\app_wdf_mask_r1_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(12), + Q => app_wdf_mask_r1(12), + R => '0' + ); +\app_wdf_mask_r1_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(13), + Q => app_wdf_mask_r1(13), + R => '0' + ); +\app_wdf_mask_r1_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(14), + Q => app_wdf_mask_r1(14), + R => '0' + ); +\app_wdf_mask_r1_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(15), + Q => app_wdf_mask_r1(15), + R => '0' + ); +\app_wdf_mask_r1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(1), + Q => app_wdf_mask_r1(1), + R => '0' + ); +\app_wdf_mask_r1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(2), + Q => app_wdf_mask_r1(2), + R => '0' + ); +\app_wdf_mask_r1_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(3), + Q => app_wdf_mask_r1(3), + R => '0' + ); +\app_wdf_mask_r1_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(4), + Q => app_wdf_mask_r1(4), + R => '0' + ); +\app_wdf_mask_r1_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(5), + Q => app_wdf_mask_r1(5), + R => '0' + ); +\app_wdf_mask_r1_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(6), + Q => app_wdf_mask_r1(6), + R => '0' + ); +\app_wdf_mask_r1_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(7), + Q => app_wdf_mask_r1(7), + R => '0' + ); +\app_wdf_mask_r1_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(8), + Q => app_wdf_mask_r1(8), + R => '0' + ); +\app_wdf_mask_r1_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => app_wdf_rdy_r_copy2, + D => app_wdf_mask(9), + Q => app_wdf_mask_r1(9), + R => '0' + ); +app_wdf_rdy_r_copy1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wdf_rdy_ns, + Q => app_wdf_rdy_r_copy1, + R => '0' + ); +app_wdf_rdy_r_copy2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wdf_rdy_ns, + Q => app_wdf_rdy_r_copy2, + R => '0' + ); +app_wdf_rdy_r_copy3_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wdf_rdy_ns, + Q => app_wdf_rdy_r_copy3, + R => '0' + ); +app_wdf_wren_r1_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"B8" + ) + port map ( + I0 => app_wdf_wren, + I1 => app_wdf_rdy_r_copy2, + I2 => app_wdf_wren_r1, + O => app_wdf_wren_r1_i_1_n_0 + ); +app_wdf_wren_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => app_wdf_wren_r1_i_1_n_0, + Q => app_wdf_wren_r1, + R => app_wdf_end_r1_reg_0 + ); +\data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0), + O => \p_0_in__0\(0) + ); +\data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0), + I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1), + O => \p_0_in__0\(1) + ); +\data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0), + I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1), + I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2), + O => \p_0_in__0\(2) + ); +\data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1), + I1 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0), + I2 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2), + I3 => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3), + O => \p_0_in__0\(3) + ); +\data_buf_address_counter.data_buf_addr_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_accepted, + D => \p_0_in__0\(0), + Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(0), + R => app_wdf_end_r1_reg_0 + ); +\data_buf_address_counter.data_buf_addr_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_accepted, + D => \p_0_in__0\(1), + Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(1), + R => app_wdf_end_r1_reg_0 + ); +\data_buf_address_counter.data_buf_addr_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_accepted, + D => \p_0_in__0\(2), + Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(2), + R => app_wdf_end_r1_reg_0 + ); +\data_buf_address_counter.data_buf_addr_cnt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => wr_accepted, + D => \p_0_in__0\(3), + Q => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3), + R => app_wdf_end_r1_reg_0 + ); +\mem_reg_0_15_0_5_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(8), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(0) + ); +mem_reg_0_15_12_17_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(0), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(1) + ); +\mem_reg_0_15_18_23_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(58), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(1) + ); +\mem_reg_0_15_18_23_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(74), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(2) + ); +\mem_reg_0_15_24_29_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(4), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(2) + ); +\mem_reg_0_15_30_35_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(11), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(3) + ); +\mem_reg_0_15_36_41_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(91), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(4) + ); +mem_reg_0_15_36_41_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(7), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(3) + ); +\mem_reg_0_15_42_47_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(62), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(5) + ); +mem_reg_0_15_42_47_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(87), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(4) + ); +\mem_reg_0_15_42_47_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(78), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(6) + ); +\mem_reg_0_15_48_53_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(12), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(7) + ); +mem_reg_0_15_48_53_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(50), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(5) + ); +mem_reg_0_15_48_53_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(66), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(6) + ); +\mem_reg_0_15_54_59_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(54), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(7) + ); +\mem_reg_0_15_54_59_i_6__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(41), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(8) + ); +\mem_reg_0_15_60_65_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(70), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(8) + ); +mem_reg_0_15_60_65_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(3), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(9) + ); +\mem_reg_0_15_66_71_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(45), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(9) + ); +mem_reg_0_15_66_71_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(83), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(10) + ); +mem_reg_0_15_6_11_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(33), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(0) + ); +\mem_reg_0_15_72_77_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(15), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(10) + ); +mem_reg_0_15_72_77_i_4: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(37), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + O => \write_buffer.wr_buf_out_data_reg[37]_0\(11) + ); +\mem_reg_0_15_72_77_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^write_buffer.wr_buf_out_data_reg[143]_0\(95), + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + O => \write_buffer.wr_buf_out_data_reg[95]_0\(11) + ); +\occupied_counter.app_wdf_rdy_r_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"3030001030301010" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[15]\, + I1 => app_wdf_end_r1_reg_0, + I2 => ram_init_done_r, + I3 => p_4_in, + I4 => \^p_0_in\(0), + I5 => \p_0_in__0_0\(1), + O => wdf_rdy_ns + ); +\occupied_counter.app_wdf_rdy_r_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => app_wdf_end_r1, + I1 => app_wdf_rdy_r_copy1, + I2 => app_wdf_wren_r1, + O => \p_0_in__0_0\(1) + ); +\occupied_counter.app_wdf_rdy_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wdf_rdy_ns, + Q => app_wdf_rdy, + R => '0' + ); +\occupied_counter.occ_cnt[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF80" + ) + port map ( + I0 => app_wdf_wren_r1, + I1 => app_wdf_rdy_r_copy1, + I2 => app_wdf_end_r1, + I3 => \occupied_counter.occ_cnt_reg_n_0_[1]\, + O => \occupied_counter.occ_cnt[0]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[10]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[9]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[11]\, + O => \occupied_counter.occ_cnt[10]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[11]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[10]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[12]\, + O => \occupied_counter.occ_cnt[11]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[12]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[11]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[13]\, + O => \occupied_counter.occ_cnt[12]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[13]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[12]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => p_4_in, + O => \occupied_counter.occ_cnt[13]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[14]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[13]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[15]\, + O => \occupied_counter.occ_cnt[14]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[15]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => \^p_0_in\(0), + I1 => app_wdf_wren_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_end_r1, + O => \occupied_counter.occ_cnt[15]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[15]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => app_wdf_wren_r1, + I1 => app_wdf_rdy_r_copy1, + I2 => app_wdf_end_r1, + I3 => p_4_in, + O => \occupied_counter.occ_cnt[15]_i_2_n_0\ + ); +\occupied_counter.occ_cnt[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[0]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[2]\, + O => \occupied_counter.occ_cnt[1]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[1]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[3]\, + O => \occupied_counter.occ_cnt[2]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[3]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[2]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[4]\, + O => \occupied_counter.occ_cnt[3]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[3]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[5]\, + O => \occupied_counter.occ_cnt[4]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[5]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[4]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[6]\, + O => \occupied_counter.occ_cnt[5]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[6]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[5]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[7]\, + O => \occupied_counter.occ_cnt[6]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[7]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[6]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[8]\, + O => \occupied_counter.occ_cnt[7]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[8]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[7]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[9]\, + O => \occupied_counter.occ_cnt[8]_i_1_n_0\ + ); +\occupied_counter.occ_cnt[9]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8000" + ) + port map ( + I0 => \occupied_counter.occ_cnt_reg_n_0_[8]\, + I1 => app_wdf_end_r1, + I2 => app_wdf_rdy_r_copy1, + I3 => app_wdf_wren_r1, + I4 => \occupied_counter.occ_cnt_reg_n_0_[10]\, + O => \occupied_counter.occ_cnt[9]_i_1_n_0\ + ); +\occupied_counter.occ_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[0]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[0]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[10]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[10]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[11]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[11]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[12]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[12]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[13]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[13]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[14]_i_1_n_0\, + Q => p_4_in, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[15]_i_2_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[15]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[1]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[1]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[2]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[2]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[3]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[3]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[4]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[4]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[5]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[5]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[6]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[6]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[7]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[7]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[8]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[8]\, + R => app_wdf_end_r1_reg_0 + ); +\occupied_counter.occ_cnt_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \occupied_counter.occ_cnt[15]_i_1_n_0\, + D => \occupied_counter.occ_cnt[9]_i_1_n_0\, + Q => \occupied_counter.occ_cnt_reg_n_0_[9]\, + R => app_wdf_end_r1_reg_0 + ); +\pointer_ram.rams[0].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => B"00000", + ADDRB(4) => '0', + ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => ADDRD(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0), + DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => wr_data_buf_addr(1 downto 0), + DOC(1 downto 0) => wr_data_pntr(1 downto 0), + DOD(1 downto 0) => \NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \write_data_control.wb_wr_data_addr_r_reg[2]_0\ + ); +\pointer_ram.rams[1].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 0) => B"00000", + ADDRB(4) => '0', + ADDRB(3 downto 0) => \data_buf_address_counter.data_buf_addr_cnt_r_reg\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \write_data_control.wr_data_indx_r_reg\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => ADDRD(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2), + DIC(1 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 2), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => wr_data_buf_addr(3 downto 2), + DOC(1 downto 0) => wr_data_pntr(3 downto 2), + DOD(1 downto 0) => \NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => \write_data_control.wb_wr_data_addr_r_reg[2]_0\ + ); +\read_data_indx.rd_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^q\(0), + O => \p_0_in__1\(0) + ); +\read_data_indx.rd_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + O => \p_0_in__1\(1) + ); +\read_data_indx.rd_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^q\(0), + I1 => \^q\(1), + I2 => \^q\(2), + O => \p_0_in__1\(2) + ); +\read_data_indx.rd_data_indx_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \^q\(1), + I1 => \^q\(0), + I2 => \^q\(2), + I3 => \^q\(3), + O => \p_0_in__1\(3) + ); +\read_data_indx.rd_data_indx_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(0), + Q => \^q\(0), + R => app_wdf_end_r1_reg_0 + ); +\read_data_indx.rd_data_indx_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(1), + Q => \^q\(1), + R => app_wdf_end_r1_reg_0 + ); +\read_data_indx.rd_data_indx_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(2), + Q => \^q\(2), + R => app_wdf_end_r1_reg_0 + ); +\read_data_indx.rd_data_indx_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => E(0), + D => \p_0_in__1\(3), + Q => \^q\(3), + R => app_wdf_end_r1_reg_0 + ); +\read_data_indx.rd_data_upd_indx_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => E(0), + Q => \^p_0_in\(0), + R => '0' + ); +\wr_req_counter.wr_req_cnt_r[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A69A" + ) + port map ( + I0 => \wr_req_counter.wr_req_cnt_r\(1), + I1 => wr_accepted, + I2 => \^p_0_in\(0), + I3 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0), + O => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\ + ); +\wr_req_counter.wr_req_cnt_r[2]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"A6AAAA9A" + ) + port map ( + I0 => \wr_req_counter.wr_req_cnt_r\(2), + I1 => wr_accepted, + I2 => \^p_0_in\(0), + I3 => \wr_req_counter.wr_req_cnt_r\(1), + I4 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0), + O => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\ + ); +\wr_req_counter.wr_req_cnt_r[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"A6AAAAAAAAAAAA9A" + ) + port map ( + I0 => \wr_req_counter.wr_req_cnt_r\(3), + I1 => wr_accepted, + I2 => \^p_0_in\(0), + I3 => \wr_req_counter.wr_req_cnt_r\(2), + I4 => \wr_req_counter.wr_req_cnt_r\(1), + I5 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0), + O => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\ + ); +\wr_req_counter.wr_req_cnt_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"96AAAAAAAAAAAA96" + ) + port map ( + I0 => \wr_req_counter.wr_req_cnt_r\(4), + I1 => wr_accepted, + I2 => \^p_0_in\(0), + I3 => \wr_req_counter.wr_req_cnt_r\(3), + I4 => \wr_req_counter.wr_req_cnt_r\(2), + I5 => \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\, + O => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\ + ); +\wr_req_counter.wr_req_cnt_r[4]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"D554" + ) + port map ( + I0 => \wr_req_counter.wr_req_cnt_r\(2), + I1 => \wr_req_counter.wr_req_cnt_r\(1), + I2 => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0), + I3 => wr_accepted, + O => \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0\ + ); +\wr_req_counter.wr_req_cnt_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_req_counter.wr_req_cnt_r_reg[0]_1\, + Q => \^wr_req_counter.wr_req_cnt_r_reg[0]_0\(0), + R => app_wdf_end_r1_reg_0 + ); +\wr_req_counter.wr_req_cnt_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0\, + Q => \wr_req_counter.wr_req_cnt_r\(1), + R => app_wdf_end_r1_reg_0 + ); +\wr_req_counter.wr_req_cnt_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0\, + Q => \wr_req_counter.wr_req_cnt_r\(2), + R => app_wdf_end_r1_reg_0 + ); +\wr_req_counter.wr_req_cnt_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0\, + Q => \wr_req_counter.wr_req_cnt_r\(3), + R => app_wdf_end_r1_reg_0 + ); +\wr_req_counter.wr_req_cnt_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0\, + Q => \wr_req_counter.wr_req_cnt_r\(4), + R => app_wdf_end_r1_reg_0 + ); +\write_buffer.wr_buf_out_data_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(0), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(0), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[100]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(100), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(100), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[101]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(101), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(101), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[102]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(102), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(102), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[103]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(103), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(103), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[104]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(104), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(104), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[105]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(105), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(105), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[106]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(106), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(106), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[107]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(107), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(107), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[108]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(108), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(108), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[109]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(109), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(109), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(10), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(10), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[110]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(110), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(110), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[111]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(111), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(111), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[112]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(112), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(112), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[113]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(113), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(113), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[114]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(114), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(114), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[115]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(115), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(115), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[116]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(116), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(116), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[117]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(117), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(117), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[118]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(118), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(118), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[119]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(119), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(119), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(11), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(11), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[120]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(120), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(120), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[121]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(121), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(121), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[122]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(122), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(122), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[123]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(123), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(123), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[124]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(124), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(124), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[125]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(125), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(125), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[126]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(126), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(126), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[127]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(127), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(127), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[128]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(128), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(128), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[129]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(129), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(129), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(12), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(12), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[130]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(130), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(130), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[131]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(131), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(131), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[132]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(132), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(132), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[133]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(133), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(133), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[134]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(134), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(134), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[135]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(135), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(135), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[136]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(136), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(136), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[137]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(137), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(137), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[138]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(138), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(138), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[139]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(139), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(139), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(13), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(13), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[140]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(140), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(140), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[141]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(141), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(141), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[142]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(142), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(142), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[143]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(143), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(143), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(14), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(14), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(15), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(15), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(16), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(16), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(17), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(17), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(18), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(18), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(19), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(19), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(1), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(1), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(20), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(20), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(21), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(21), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(22), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(22), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(23), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(23), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(24), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(24), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(25), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(25), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(26), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(26), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(27), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(27), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(28), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(28), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(29), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(29), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(2), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(2), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(30), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(30), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(31), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(31), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(32), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(32), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(33), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(33), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(34), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(34), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(35), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(35), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(36), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(36), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(37), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(37), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(38), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(38), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(39), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(39), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(3), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(3), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(40), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(40), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(41), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(41), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(42), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(42), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(43), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(43), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(44), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(44), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(45), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(45), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(46), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(46), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(47), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(47), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(48), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(48), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(49), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(49), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(4), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(4), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(50), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(50), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(51), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(51), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(52), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(52), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(53), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(53), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(54), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(54), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(55), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(55), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(56), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(56), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(57), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(57), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(58), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(58), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(59), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(59), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(5), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(5), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(60), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(60), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(61), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(61), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(62), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(62), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(63), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(63), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(64), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(64), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(65), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(65), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(66), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(66), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[67]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(67), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(67), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[68]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(68), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(68), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[69]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(69), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(69), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(6), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(6), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[70]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(70), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(70), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[71]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(71), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(71), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[72]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(72), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(72), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[73]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(73), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(73), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[74]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(74), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(74), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[75]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(75), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(75), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[76]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(76), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(76), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[77]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(77), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(77), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[78]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(78), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(78), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[79]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(79), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(79), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(7), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(7), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[80]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(80), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(80), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[81]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(81), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(81), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[82]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(82), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(82), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[83]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(83), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(83), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[84]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(84), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(84), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[85]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(85), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(85), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[86]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(86), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(86), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[87]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(87), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(87), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[88]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(88), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(88), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[89]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(89), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(89), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(8), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(8), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[90]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(90), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(90), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[91]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(91), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(91), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[92]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(92), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(92), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[93]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(93), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(93), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[94]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(94), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(94), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[95]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(95), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(95), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[96]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(96), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(96), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[97]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(97), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(97), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[98]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(98), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(98), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[99]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(99), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(99), + R => '0' + ); +\write_buffer.wr_buf_out_data_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_buf_out_data_w(9), + Q => \^write_buffer.wr_buf_out_data_reg[143]_0\(9), + R => '0' + ); +\write_buffer.wr_buffer_ram[0].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(5 downto 4), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(3 downto 2), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(1 downto 0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(5 downto 4), + DOB(1 downto 0) => wr_buf_out_data_w(3 downto 2), + DOC(1 downto 0) => wr_buf_out_data_w(1 downto 0), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(5), + I1 => app_wdf_data_r1(5), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(5) + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r\(1), + I1 => \write_data_control.wr_data_addr_le__2\, + I2 => wr_data_pntr(0), + I3 => app_wdf_end_r1_reg_0, + O => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\ + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_11\: unisim.vcomponents.LUT5 + generic map( + INIT => X"000022E2" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr0_r\, + I1 => app_wdf_wren_r1, + I2 => app_wdf_rdy_r_copy3, + I3 => app_wdf_end_r1, + I4 => app_wdf_end_r1_reg_0, + O => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\ + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(4), + I1 => app_wdf_data_r1(4), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(4) + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(3), + I1 => app_wdf_data_r1(3), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(3) + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(2), + I1 => app_wdf_data_r1(2), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(2) + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(1), + I1 => app_wdf_data_r1(1), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(1) + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(0), + I1 => app_wdf_data_r1(0), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(0) + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_7\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r\(4), + I1 => \write_data_control.wr_data_addr_le__2\, + I2 => wr_data_pntr(3), + I3 => app_wdf_end_r1_reg_0, + O => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\ + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_8\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r\(3), + I1 => \write_data_control.wr_data_addr_le__2\, + I2 => wr_data_pntr(2), + I3 => app_wdf_end_r1_reg_0, + O => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\ + ); +\write_buffer.wr_buffer_ram[0].RAM32M0_i_9\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00E2" + ) + port map ( + I0 => \write_data_control.wb_wr_data_addr_r\(2), + I1 => \write_data_control.wr_data_addr_le__2\, + I2 => wr_data_pntr(1), + I3 => app_wdf_end_r1_reg_0, + O => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\ + ); +\write_buffer.wr_buffer_ram[10].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(65 downto 64), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(63 downto 62), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(61 downto 60), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(65 downto 64), + DOB(1 downto 0) => wr_buf_out_data_w(63 downto 62), + DOC(1 downto 0) => wr_buf_out_data_w(61 downto 60), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[10].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(65), + I1 => app_wdf_data_r1(65), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(65) + ); +\write_buffer.wr_buffer_ram[10].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(64), + I1 => app_wdf_data_r1(64), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(64) + ); +\write_buffer.wr_buffer_ram[10].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(63), + I1 => app_wdf_data_r1(63), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(63) + ); +\write_buffer.wr_buffer_ram[10].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(62), + I1 => app_wdf_data_r1(62), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(62) + ); +\write_buffer.wr_buffer_ram[10].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(61), + I1 => app_wdf_data_r1(61), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(61) + ); +\write_buffer.wr_buffer_ram[10].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(60), + I1 => app_wdf_data_r1(60), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(60) + ); +\write_buffer.wr_buffer_ram[11].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(71 downto 70), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(69 downto 68), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(67 downto 66), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(71 downto 70), + DOB(1 downto 0) => wr_buf_out_data_w(69 downto 68), + DOC(1 downto 0) => wr_buf_out_data_w(67 downto 66), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[11].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(71), + I1 => app_wdf_data_r1(71), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(71) + ); +\write_buffer.wr_buffer_ram[11].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(70), + I1 => app_wdf_data_r1(70), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(70) + ); +\write_buffer.wr_buffer_ram[11].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(69), + I1 => app_wdf_data_r1(69), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(69) + ); +\write_buffer.wr_buffer_ram[11].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(68), + I1 => app_wdf_data_r1(68), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(68) + ); +\write_buffer.wr_buffer_ram[11].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(67), + I1 => app_wdf_data_r1(67), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(67) + ); +\write_buffer.wr_buffer_ram[11].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(66), + I1 => app_wdf_data_r1(66), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(66) + ); +\write_buffer.wr_buffer_ram[12].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(77 downto 76), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(75 downto 74), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(73 downto 72), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(77 downto 76), + DOB(1 downto 0) => wr_buf_out_data_w(75 downto 74), + DOC(1 downto 0) => wr_buf_out_data_w(73 downto 72), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[12].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(77), + I1 => app_wdf_data_r1(77), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(77) + ); +\write_buffer.wr_buffer_ram[12].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(76), + I1 => app_wdf_data_r1(76), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(76) + ); +\write_buffer.wr_buffer_ram[12].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(75), + I1 => app_wdf_data_r1(75), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(75) + ); +\write_buffer.wr_buffer_ram[12].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(74), + I1 => app_wdf_data_r1(74), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(74) + ); +\write_buffer.wr_buffer_ram[12].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(73), + I1 => app_wdf_data_r1(73), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(73) + ); +\write_buffer.wr_buffer_ram[12].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(72), + I1 => app_wdf_data_r1(72), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(72) + ); +\write_buffer.wr_buffer_ram[13].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(83 downto 82), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(81 downto 80), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(79 downto 78), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(83 downto 82), + DOB(1 downto 0) => wr_buf_out_data_w(81 downto 80), + DOC(1 downto 0) => wr_buf_out_data_w(79 downto 78), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[13].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(83), + I1 => app_wdf_data_r1(83), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(83) + ); +\write_buffer.wr_buffer_ram[13].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(82), + I1 => app_wdf_data_r1(82), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(82) + ); +\write_buffer.wr_buffer_ram[13].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(81), + I1 => app_wdf_data_r1(81), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(81) + ); +\write_buffer.wr_buffer_ram[13].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(80), + I1 => app_wdf_data_r1(80), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(80) + ); +\write_buffer.wr_buffer_ram[13].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(79), + I1 => app_wdf_data_r1(79), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(79) + ); +\write_buffer.wr_buffer_ram[13].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(78), + I1 => app_wdf_data_r1(78), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(78) + ); +\write_buffer.wr_buffer_ram[14].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(89 downto 88), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(87 downto 86), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(85 downto 84), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(89 downto 88), + DOB(1 downto 0) => wr_buf_out_data_w(87 downto 86), + DOC(1 downto 0) => wr_buf_out_data_w(85 downto 84), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[14].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(89), + I1 => app_wdf_data_r1(89), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(89) + ); +\write_buffer.wr_buffer_ram[14].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(88), + I1 => app_wdf_data_r1(88), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(88) + ); +\write_buffer.wr_buffer_ram[14].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(87), + I1 => app_wdf_data_r1(87), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(87) + ); +\write_buffer.wr_buffer_ram[14].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(86), + I1 => app_wdf_data_r1(86), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(86) + ); +\write_buffer.wr_buffer_ram[14].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(85), + I1 => app_wdf_data_r1(85), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(85) + ); +\write_buffer.wr_buffer_ram[14].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(84), + I1 => app_wdf_data_r1(84), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(84) + ); +\write_buffer.wr_buffer_ram[15].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(95 downto 94), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(93 downto 92), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(91 downto 90), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(95 downto 94), + DOB(1 downto 0) => wr_buf_out_data_w(93 downto 92), + DOC(1 downto 0) => wr_buf_out_data_w(91 downto 90), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[15].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(95), + I1 => app_wdf_data_r1(95), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(95) + ); +\write_buffer.wr_buffer_ram[15].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(94), + I1 => app_wdf_data_r1(94), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(94) + ); +\write_buffer.wr_buffer_ram[15].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(93), + I1 => app_wdf_data_r1(93), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(93) + ); +\write_buffer.wr_buffer_ram[15].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(92), + I1 => app_wdf_data_r1(92), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(92) + ); +\write_buffer.wr_buffer_ram[15].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(91), + I1 => app_wdf_data_r1(91), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(91) + ); +\write_buffer.wr_buffer_ram[15].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(90), + I1 => app_wdf_data_r1(90), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(90) + ); +\write_buffer.wr_buffer_ram[16].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(101 downto 100), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(99 downto 98), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(97 downto 96), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(101 downto 100), + DOB(1 downto 0) => wr_buf_out_data_w(99 downto 98), + DOC(1 downto 0) => wr_buf_out_data_w(97 downto 96), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[16].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(101), + I1 => app_wdf_data_r1(101), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(101) + ); +\write_buffer.wr_buffer_ram[16].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(100), + I1 => app_wdf_data_r1(100), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(100) + ); +\write_buffer.wr_buffer_ram[16].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(99), + I1 => app_wdf_data_r1(99), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(99) + ); +\write_buffer.wr_buffer_ram[16].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(98), + I1 => app_wdf_data_r1(98), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(98) + ); +\write_buffer.wr_buffer_ram[16].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(97), + I1 => app_wdf_data_r1(97), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(97) + ); +\write_buffer.wr_buffer_ram[16].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(96), + I1 => app_wdf_data_r1(96), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(96) + ); +\write_buffer.wr_buffer_ram[17].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(107 downto 106), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(105 downto 104), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(103 downto 102), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(107 downto 106), + DOB(1 downto 0) => wr_buf_out_data_w(105 downto 104), + DOC(1 downto 0) => wr_buf_out_data_w(103 downto 102), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[17].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(107), + I1 => app_wdf_data_r1(107), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(107) + ); +\write_buffer.wr_buffer_ram[17].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(106), + I1 => app_wdf_data_r1(106), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(106) + ); +\write_buffer.wr_buffer_ram[17].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(105), + I1 => app_wdf_data_r1(105), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(105) + ); +\write_buffer.wr_buffer_ram[17].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(104), + I1 => app_wdf_data_r1(104), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(104) + ); +\write_buffer.wr_buffer_ram[17].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(103), + I1 => app_wdf_data_r1(103), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(103) + ); +\write_buffer.wr_buffer_ram[17].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(102), + I1 => app_wdf_data_r1(102), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(102) + ); +\write_buffer.wr_buffer_ram[18].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(113 downto 112), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(111 downto 110), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(109 downto 108), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(113 downto 112), + DOB(1 downto 0) => wr_buf_out_data_w(111 downto 110), + DOC(1 downto 0) => wr_buf_out_data_w(109 downto 108), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[18].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(113), + I1 => app_wdf_data_r1(113), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(113) + ); +\write_buffer.wr_buffer_ram[18].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(112), + I1 => app_wdf_data_r1(112), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(112) + ); +\write_buffer.wr_buffer_ram[18].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(111), + I1 => app_wdf_data_r1(111), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(111) + ); +\write_buffer.wr_buffer_ram[18].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(110), + I1 => app_wdf_data_r1(110), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(110) + ); +\write_buffer.wr_buffer_ram[18].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(109), + I1 => app_wdf_data_r1(109), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(109) + ); +\write_buffer.wr_buffer_ram[18].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(108), + I1 => app_wdf_data_r1(108), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(108) + ); +\write_buffer.wr_buffer_ram[19].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(119 downto 118), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(117 downto 116), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(115 downto 114), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(119 downto 118), + DOB(1 downto 0) => wr_buf_out_data_w(117 downto 116), + DOC(1 downto 0) => wr_buf_out_data_w(115 downto 114), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[19].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(119), + I1 => app_wdf_data_r1(119), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(119) + ); +\write_buffer.wr_buffer_ram[19].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(118), + I1 => app_wdf_data_r1(118), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(118) + ); +\write_buffer.wr_buffer_ram[19].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(117), + I1 => app_wdf_data_r1(117), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(117) + ); +\write_buffer.wr_buffer_ram[19].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(116), + I1 => app_wdf_data_r1(116), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(116) + ); +\write_buffer.wr_buffer_ram[19].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(115), + I1 => app_wdf_data_r1(115), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(115) + ); +\write_buffer.wr_buffer_ram[19].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(114), + I1 => app_wdf_data_r1(114), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(114) + ); +\write_buffer.wr_buffer_ram[1].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(11 downto 10), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(9 downto 8), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(7 downto 6), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(11 downto 10), + DOB(1 downto 0) => wr_buf_out_data_w(9 downto 8), + DOC(1 downto 0) => wr_buf_out_data_w(7 downto 6), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[1].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(11), + I1 => app_wdf_data_r1(11), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(11) + ); +\write_buffer.wr_buffer_ram[1].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(10), + I1 => app_wdf_data_r1(10), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(10) + ); +\write_buffer.wr_buffer_ram[1].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(9), + I1 => app_wdf_data_r1(9), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(9) + ); +\write_buffer.wr_buffer_ram[1].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(8), + I1 => app_wdf_data_r1(8), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(8) + ); +\write_buffer.wr_buffer_ram[1].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(7), + I1 => app_wdf_data_r1(7), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(7) + ); +\write_buffer.wr_buffer_ram[1].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(6), + I1 => app_wdf_data_r1(6), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(6) + ); +\write_buffer.wr_buffer_ram[20].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(125 downto 124), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(123 downto 122), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(121 downto 120), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(125 downto 124), + DOB(1 downto 0) => wr_buf_out_data_w(123 downto 122), + DOC(1 downto 0) => wr_buf_out_data_w(121 downto 120), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[20].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(125), + I1 => app_wdf_data_r1(125), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(125) + ); +\write_buffer.wr_buffer_ram[20].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(124), + I1 => app_wdf_data_r1(124), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(124) + ); +\write_buffer.wr_buffer_ram[20].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(123), + I1 => app_wdf_data_r1(123), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(123) + ); +\write_buffer.wr_buffer_ram[20].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(122), + I1 => app_wdf_data_r1(122), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(122) + ); +\write_buffer.wr_buffer_ram[20].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(121), + I1 => app_wdf_data_r1(121), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(121) + ); +\write_buffer.wr_buffer_ram[20].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(120), + I1 => app_wdf_data_r1(120), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(120) + ); +\write_buffer.wr_buffer_ram[21].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(131 downto 130), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(129 downto 128), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(127 downto 126), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(131 downto 130), + DOB(1 downto 0) => wr_buf_out_data_w(129 downto 128), + DOC(1 downto 0) => wr_buf_out_data_w(127 downto 126), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[21].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(3), + I1 => app_wdf_mask_r1(3), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(131) + ); +\write_buffer.wr_buffer_ram[21].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(2), + I1 => app_wdf_mask_r1(2), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(130) + ); +\write_buffer.wr_buffer_ram[21].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(1), + I1 => app_wdf_mask_r1(1), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(129) + ); +\write_buffer.wr_buffer_ram[21].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(0), + I1 => app_wdf_mask_r1(0), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(128) + ); +\write_buffer.wr_buffer_ram[21].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(127), + I1 => app_wdf_data_r1(127), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(127) + ); +\write_buffer.wr_buffer_ram[21].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(126), + I1 => app_wdf_data_r1(126), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(126) + ); +\write_buffer.wr_buffer_ram[22].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(137 downto 136), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(135 downto 134), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(133 downto 132), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(137 downto 136), + DOB(1 downto 0) => wr_buf_out_data_w(135 downto 134), + DOC(1 downto 0) => wr_buf_out_data_w(133 downto 132), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[22].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(9), + I1 => app_wdf_mask_r1(9), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(137) + ); +\write_buffer.wr_buffer_ram[22].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(8), + I1 => app_wdf_mask_r1(8), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(136) + ); +\write_buffer.wr_buffer_ram[22].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(7), + I1 => app_wdf_mask_r1(7), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(135) + ); +\write_buffer.wr_buffer_ram[22].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(6), + I1 => app_wdf_mask_r1(6), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(134) + ); +\write_buffer.wr_buffer_ram[22].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(5), + I1 => app_wdf_mask_r1(5), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(133) + ); +\write_buffer.wr_buffer_ram[22].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(4), + I1 => app_wdf_mask_r1(4), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(132) + ); +\write_buffer.wr_buffer_ram[23].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(143 downto 142), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(141 downto 140), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(139 downto 138), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(143 downto 142), + DOB(1 downto 0) => wr_buf_out_data_w(141 downto 140), + DOC(1 downto 0) => wr_buf_out_data_w(139 downto 138), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[23].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(15), + I1 => app_wdf_mask_r1(15), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(143) + ); +\write_buffer.wr_buffer_ram[23].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(14), + I1 => app_wdf_mask_r1(14), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(142) + ); +\write_buffer.wr_buffer_ram[23].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(13), + I1 => app_wdf_mask_r1(13), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(141) + ); +\write_buffer.wr_buffer_ram[23].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(12), + I1 => app_wdf_mask_r1(12), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(140) + ); +\write_buffer.wr_buffer_ram[23].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(11), + I1 => app_wdf_mask_r1(11), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(139) + ); +\write_buffer.wr_buffer_ram[23].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_mask(10), + I1 => app_wdf_mask_r1(10), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(138) + ); +\write_buffer.wr_buffer_ram[2].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(17 downto 16), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(15 downto 14), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(13 downto 12), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(17 downto 16), + DOB(1 downto 0) => wr_buf_out_data_w(15 downto 14), + DOC(1 downto 0) => wr_buf_out_data_w(13 downto 12), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[2].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(17), + I1 => app_wdf_data_r1(17), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(17) + ); +\write_buffer.wr_buffer_ram[2].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(16), + I1 => app_wdf_data_r1(16), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(16) + ); +\write_buffer.wr_buffer_ram[2].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(15), + I1 => app_wdf_data_r1(15), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(15) + ); +\write_buffer.wr_buffer_ram[2].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(14), + I1 => app_wdf_data_r1(14), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(14) + ); +\write_buffer.wr_buffer_ram[2].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(13), + I1 => app_wdf_data_r1(13), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(13) + ); +\write_buffer.wr_buffer_ram[2].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(12), + I1 => app_wdf_data_r1(12), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(12) + ); +\write_buffer.wr_buffer_ram[3].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(23 downto 22), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(21 downto 20), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(19 downto 18), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(23 downto 22), + DOB(1 downto 0) => wr_buf_out_data_w(21 downto 20), + DOC(1 downto 0) => wr_buf_out_data_w(19 downto 18), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[3].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(23), + I1 => app_wdf_data_r1(23), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(23) + ); +\write_buffer.wr_buffer_ram[3].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(22), + I1 => app_wdf_data_r1(22), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(22) + ); +\write_buffer.wr_buffer_ram[3].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(21), + I1 => app_wdf_data_r1(21), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(21) + ); +\write_buffer.wr_buffer_ram[3].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(20), + I1 => app_wdf_data_r1(20), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(20) + ); +\write_buffer.wr_buffer_ram[3].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(19), + I1 => app_wdf_data_r1(19), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(19) + ); +\write_buffer.wr_buffer_ram[3].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(18), + I1 => app_wdf_data_r1(18), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(18) + ); +\write_buffer.wr_buffer_ram[4].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(29 downto 28), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(27 downto 26), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(25 downto 24), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(29 downto 28), + DOB(1 downto 0) => wr_buf_out_data_w(27 downto 26), + DOC(1 downto 0) => wr_buf_out_data_w(25 downto 24), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[4].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(29), + I1 => app_wdf_data_r1(29), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(29) + ); +\write_buffer.wr_buffer_ram[4].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(28), + I1 => app_wdf_data_r1(28), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(28) + ); +\write_buffer.wr_buffer_ram[4].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(27), + I1 => app_wdf_data_r1(27), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(27) + ); +\write_buffer.wr_buffer_ram[4].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(26), + I1 => app_wdf_data_r1(26), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(26) + ); +\write_buffer.wr_buffer_ram[4].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(25), + I1 => app_wdf_data_r1(25), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(25) + ); +\write_buffer.wr_buffer_ram[4].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(24), + I1 => app_wdf_data_r1(24), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(24) + ); +\write_buffer.wr_buffer_ram[5].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(35 downto 34), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(33 downto 32), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(31 downto 30), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(35 downto 34), + DOB(1 downto 0) => wr_buf_out_data_w(33 downto 32), + DOC(1 downto 0) => wr_buf_out_data_w(31 downto 30), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[5].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(35), + I1 => app_wdf_data_r1(35), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(35) + ); +\write_buffer.wr_buffer_ram[5].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(34), + I1 => app_wdf_data_r1(34), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(34) + ); +\write_buffer.wr_buffer_ram[5].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(33), + I1 => app_wdf_data_r1(33), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(33) + ); +\write_buffer.wr_buffer_ram[5].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(32), + I1 => app_wdf_data_r1(32), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(32) + ); +\write_buffer.wr_buffer_ram[5].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(31), + I1 => app_wdf_data_r1(31), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(31) + ); +\write_buffer.wr_buffer_ram[5].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(30), + I1 => app_wdf_data_r1(30), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(30) + ); +\write_buffer.wr_buffer_ram[6].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(41 downto 40), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(39 downto 38), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(37 downto 36), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(41 downto 40), + DOB(1 downto 0) => wr_buf_out_data_w(39 downto 38), + DOC(1 downto 0) => wr_buf_out_data_w(37 downto 36), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[6].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(41), + I1 => app_wdf_data_r1(41), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(41) + ); +\write_buffer.wr_buffer_ram[6].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(40), + I1 => app_wdf_data_r1(40), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(40) + ); +\write_buffer.wr_buffer_ram[6].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(39), + I1 => app_wdf_data_r1(39), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(39) + ); +\write_buffer.wr_buffer_ram[6].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(38), + I1 => app_wdf_data_r1(38), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(38) + ); +\write_buffer.wr_buffer_ram[6].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(37), + I1 => app_wdf_data_r1(37), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(37) + ); +\write_buffer.wr_buffer_ram[6].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(36), + I1 => app_wdf_data_r1(36), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(36) + ); +\write_buffer.wr_buffer_ram[7].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(47 downto 46), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(45 downto 44), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(43 downto 42), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(47 downto 46), + DOB(1 downto 0) => wr_buf_out_data_w(45 downto 44), + DOC(1 downto 0) => wr_buf_out_data_w(43 downto 42), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[7].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(47), + I1 => app_wdf_data_r1(47), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(47) + ); +\write_buffer.wr_buffer_ram[7].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(46), + I1 => app_wdf_data_r1(46), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(46) + ); +\write_buffer.wr_buffer_ram[7].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(45), + I1 => app_wdf_data_r1(45), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(45) + ); +\write_buffer.wr_buffer_ram[7].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(44), + I1 => app_wdf_data_r1(44), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(44) + ); +\write_buffer.wr_buffer_ram[7].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(43), + I1 => app_wdf_data_r1(43), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(43) + ); +\write_buffer.wr_buffer_ram[7].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(42), + I1 => app_wdf_data_r1(42), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(42) + ); +\write_buffer.wr_buffer_ram[8].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(53 downto 52), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(51 downto 50), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(49 downto 48), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(53 downto 52), + DOB(1 downto 0) => wr_buf_out_data_w(51 downto 50), + DOC(1 downto 0) => wr_buf_out_data_w(49 downto 48), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[8].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(53), + I1 => app_wdf_data_r1(53), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(53) + ); +\write_buffer.wr_buffer_ram[8].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(52), + I1 => app_wdf_data_r1(52), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(52) + ); +\write_buffer.wr_buffer_ram[8].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(51), + I1 => app_wdf_data_r1(51), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(51) + ); +\write_buffer.wr_buffer_ram[8].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(50), + I1 => app_wdf_data_r1(50), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(50) + ); +\write_buffer.wr_buffer_ram[8].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(49), + I1 => app_wdf_data_r1(49), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(49) + ); +\write_buffer.wr_buffer_ram[8].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(48), + I1 => app_wdf_data_r1(48), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(48) + ); +\write_buffer.wr_buffer_ram[9].RAM32M0\: unisim.vcomponents.RAM32M + generic map( + INIT_A => X"0000000000000000", + INIT_B => X"0000000000000000", + INIT_C => X"0000000000000000", + INIT_D => X"0000000000000000", + IS_WCLK_INVERTED => '0' + ) + port map ( + ADDRA(4 downto 1) => wr_data_addr(3 downto 0), + ADDRA(0) => '0', + ADDRB(4 downto 1) => wr_data_addr(3 downto 0), + ADDRB(0) => '0', + ADDRC(4 downto 1) => wr_data_addr(3 downto 0), + ADDRC(0) => '0', + ADDRD(4) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_7_n_0\, + ADDRD(3) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_8_n_0\, + ADDRD(2) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_9_n_0\, + ADDRD(1) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_10_n_0\, + ADDRD(0) => \write_buffer.wr_buffer_ram[0].RAM32M0_i_11_n_0\, + DIA(1 downto 0) => \write_buffer.wr_buf_in_data\(59 downto 58), + DIB(1 downto 0) => \write_buffer.wr_buf_in_data\(57 downto 56), + DIC(1 downto 0) => \write_buffer.wr_buf_in_data\(55 downto 54), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => wr_buf_out_data_w(59 downto 58), + DOB(1 downto 0) => wr_buf_out_data_w(57 downto 56), + DOC(1 downto 0) => wr_buf_out_data_w(55 downto 54), + DOD(1 downto 0) => \NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED\(1 downto 0), + WCLK => CLK, + WE => wdf_rdy_ns + ); +\write_buffer.wr_buffer_ram[9].RAM32M0_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(59), + I1 => app_wdf_data_r1(59), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(59) + ); +\write_buffer.wr_buffer_ram[9].RAM32M0_i_2\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(58), + I1 => app_wdf_data_r1(58), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(58) + ); +\write_buffer.wr_buffer_ram[9].RAM32M0_i_3\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(57), + I1 => app_wdf_data_r1(57), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(57) + ); +\write_buffer.wr_buffer_ram[9].RAM32M0_i_4\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(56), + I1 => app_wdf_data_r1(56), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(56) + ); +\write_buffer.wr_buffer_ram[9].RAM32M0_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(55), + I1 => app_wdf_data_r1(55), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(55) + ); +\write_buffer.wr_buffer_ram[9].RAM32M0_i_6\: unisim.vcomponents.LUT3 + generic map( + INIT => X"AC" + ) + port map ( + I0 => app_wdf_data(54), + I1 => app_wdf_data_r1(54), + I2 => app_wdf_rdy_r_copy2, + O => \write_buffer.wr_buf_in_data\(54) + ); +\write_data_control.wb_wr_data_addr0_r_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"4F40" + ) + port map ( + I0 => app_wdf_end_r1, + I1 => app_wdf_rdy_r_copy3, + I2 => app_wdf_wren_r1, + I3 => \write_data_control.wb_wr_data_addr0_r\, + O => \write_data_control.wb_wr_data_addr0_ns02_in\ + ); +\write_data_control.wb_wr_data_addr0_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \write_data_control.wb_wr_data_addr0_ns02_in\, + Q => \write_data_control.wb_wr_data_addr0_r\, + R => app_wdf_end_r1_reg_0 + ); +\write_data_control.wb_wr_data_addr_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"80FF8000" + ) + port map ( + I0 => wdf_rdy_ns, + I1 => app_wdf_end_r1, + I2 => app_wdf_wren_r1, + I3 => app_wdf_rdy_r_copy1, + I4 => \^p_0_in\(0), + O => \write_data_control.wr_data_addr_le__2\ + ); +\write_data_control.wb_wr_data_addr_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => wr_data_pntr(0), + Q => \write_data_control.wb_wr_data_addr_r\(1), + R => app_wdf_end_r1_reg_0 + ); +\write_data_control.wb_wr_data_addr_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => wr_data_pntr(1), + Q => \write_data_control.wb_wr_data_addr_r\(2), + R => app_wdf_end_r1_reg_0 + ); +\write_data_control.wb_wr_data_addr_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => wr_data_pntr(2), + Q => \write_data_control.wb_wr_data_addr_r\(3), + R => app_wdf_end_r1_reg_0 + ); +\write_data_control.wb_wr_data_addr_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => wr_data_pntr(3), + Q => \write_data_control.wb_wr_data_addr_r\(4), + R => app_wdf_end_r1_reg_0 + ); +\write_data_control.wr_data_indx_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \write_data_control.wr_data_indx_r_reg\(0), + O => \p_0_in__0__0\(0) + ); +\write_data_control.wr_data_indx_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => \write_data_control.wr_data_indx_r_reg\(0), + I1 => \write_data_control.wr_data_indx_r_reg\(1), + O => \p_0_in__0__0\(1) + ); +\write_data_control.wr_data_indx_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \write_data_control.wr_data_indx_r_reg\(0), + I1 => \write_data_control.wr_data_indx_r_reg\(1), + I2 => \write_data_control.wr_data_indx_r_reg\(2), + O => \p_0_in__0__0\(2) + ); +\write_data_control.wr_data_indx_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"7F80" + ) + port map ( + I0 => \write_data_control.wr_data_indx_r_reg\(1), + I1 => \write_data_control.wr_data_indx_r_reg\(0), + I2 => \write_data_control.wr_data_indx_r_reg\(2), + I3 => \write_data_control.wr_data_indx_r_reg\(3), + O => \p_0_in__0__0\(3) + ); +\write_data_control.wr_data_indx_r_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => \p_0_in__0__0\(0), + Q => \write_data_control.wr_data_indx_r_reg\(0), + S => app_wdf_end_r1_reg_0 + ); +\write_data_control.wr_data_indx_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => \p_0_in__0__0\(1), + Q => \write_data_control.wr_data_indx_r_reg\(1), + R => app_wdf_end_r1_reg_0 + ); +\write_data_control.wr_data_indx_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => \p_0_in__0__0\(2), + Q => \write_data_control.wr_data_indx_r_reg\(2), + R => app_wdf_end_r1_reg_0 + ); +\write_data_control.wr_data_indx_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \write_data_control.wr_data_addr_le__2\, + D => \p_0_in__0__0\(3), + Q => \write_data_control.wr_data_indx_r_reg\(3), + R => app_wdf_end_r1_reg_0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_arb_row_col is + port ( + granted_col_r_reg_0 : out STD_LOGIC; + insert_maint_r1_lcl_reg_0 : out STD_LOGIC; + rnk_config_valid_r : out STD_LOGIC; + I121 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[3]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \rnk_config_strobe_r_reg[0]_0\ : out STD_LOGIC; + \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[3]_2\ : out STD_LOGIC; + granted_col_r_reg_1 : out STD_LOGIC; + \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC; + \periodic_rd_generation.read_this_rank\ : out STD_LOGIC; + ofs_rdy_r_reg : out STD_LOGIC; + \last_master_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \genblk3[1].rnk_config_strobe_r_reg[1]_0\ : out STD_LOGIC; + \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC; + \grant_r_reg[1]\ : out STD_LOGIC; + I119 : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_aux_out0_1 : out STD_LOGIC; + rd_wr_r_lcl_reg : out STD_LOGIC; + granted_col_r_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + DIC : out STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[0]\ : out STD_LOGIC; + \rnk_config_strobe_r_reg[0]_1\ : out STD_LOGIC; + mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 ); + rnk_config_0 : out STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + act_this_rank : out STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg_1\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + CLK : in STD_LOGIC; + rnk_config_strobe_ns : in STD_LOGIC; + insert_maint_r1_lcl_reg_1 : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_ns\ : in STD_LOGIC; + rnk_config_valid_r_lcl_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + rnk_config_valid_r_lcl_reg_1 : in STD_LOGIC; + col_wait_r : in STD_LOGIC; + \grant_r_reg[0]_0\ : in STD_LOGIC; + \last_master_r_reg[0]\ : in STD_LOGIC; + \grant_r_reg[0]_1\ : in STD_LOGIC; + \grant_r_reg[0]_2\ : in STD_LOGIC; + \grant_r_reg[2]\ : in STD_LOGIC; + \grant_r_reg[0]_3\ : in STD_LOGIC; + \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC; + rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[1]_0\ : in STD_LOGIC; + \grant_r_reg[1]_1\ : in STD_LOGIC; + granted_col_r_reg_3 : in STD_LOGIC; + col_wait_r_0 : in STD_LOGIC; + \grant_r_reg[2]_0\ : in STD_LOGIC; + \grant_r[3]_i_6\ : in STD_LOGIC; + ofs_rdy_r : in STD_LOGIC; + \grant_r[3]_i_6_0\ : in STD_LOGIC; + rd_wr_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r[3]_i_3__0\ : in STD_LOGIC; + ofs_rdy_r_1 : in STD_LOGIC; + \grant_r[3]_i_3__0_0\ : in STD_LOGIC; + col_wait_r_2 : in STD_LOGIC; + \grant_r_reg[3]_3\ : in STD_LOGIC; + \grant_r[2]_i_3\ : in STD_LOGIC; + ofs_rdy_r_3 : in STD_LOGIC; + \grant_r[2]_i_3_0\ : in STD_LOGIC; + \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC; + \col_mux.col_periodic_rd_r_reg\ : in STD_LOGIC; + O : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \col_mux.col_periodic_rd_r\ : in STD_LOGIC; + col_rd_wr_r : in STD_LOGIC; + wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + demand_act_priority_r : in STD_LOGIC; + granted_row_r_reg_0 : in STD_LOGIC; + granted_row_r_reg_1 : in STD_LOGIC; + \grant_r_reg[0]_4\ : in STD_LOGIC; + \grant_r_reg[0]_5\ : in STD_LOGIC; + \grant_r_reg[0]_6\ : in STD_LOGIC; + \grant_r_reg[1]_2\ : in STD_LOGIC; + demand_act_priority_r_4 : in STD_LOGIC; + \grant_r_reg[3]_4\ : in STD_LOGIC; + \grant_r_reg[3]_5\ : in STD_LOGIC; + demand_act_priority_r_5 : in STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[0]\ : in STD_LOGIC; + \grant_r_reg[3]_6\ : in STD_LOGIC; + demand_act_priority_r_6 : in STD_LOGIC; + \grant_r_reg[3]_7\ : in STD_LOGIC; + \grant_r_reg[3]_8\ : in STD_LOGIC; + \cmd_pipe_plus.mc_ras_n_reg[0]\ : in STD_LOGIC; + maint_zq_r : in STD_LOGIC; + maint_srx_r : in STD_LOGIC; + rnk_config_r : in STD_LOGIC; + row_cmd_wr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + inhbt_act_faw_r : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC; + req_row_r : in STD_LOGIC_VECTOR ( 43 downto 0 ); + req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 19 downto 0 ); + \col_mux.col_data_buf_addr_r\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + auto_pre_r : in STD_LOGIC; + auto_pre_r_7 : in STD_LOGIC; + auto_pre_r_8 : in STD_LOGIC; + auto_pre_r_9 : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[14]\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \cmd_pipe_plus.mc_address_reg[40]\ : in STD_LOGIC; + \grant_r[3]_i_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r[3]_i_4_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_arb_row_col : entity is "mig_7series_v4_2_arb_row_col"; +end ddr3_mig_7series_v4_2_arb_row_col; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_arb_row_col is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \cmd_pipe_plus.mc_cas_n[0]_i_2_n_0\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\ : STD_LOGIC; + signal config_arb0_n_2 : STD_LOGIC; + signal config_arb0_n_3 : STD_LOGIC; + signal cs_en2 : STD_LOGIC; + signal \genblk3[1].rnk_config_strobe_r_reg\ : STD_LOGIC; + signal \^genblk3[1].rnk_config_strobe_r_reg[1]_0\ : STD_LOGIC; + signal \genblk3[2].rnk_config_strobe_r_reg\ : STD_LOGIC; + signal granted_col_ns : STD_LOGIC; + signal \^granted_col_r_reg_0\ : STD_LOGIC; + signal granted_row_ns : STD_LOGIC; + signal \^insert_maint_r1_lcl_reg_0\ : STD_LOGIC; + signal \^ofs_rdy_r_reg\ : STD_LOGIC; + signal rnk_config_strobe : STD_LOGIC; + signal \^rnk_config_valid_r\ : STD_LOGIC; + signal sent_row : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_cas_n[0]_i_2\ : label is "soft_lutpair501"; + attribute SOFT_HLUTNM of \cmd_pipe_plus.mc_we_n[0]_i_2\ : label is "soft_lutpair501"; +begin + Q(3 downto 0) <= \^q\(3 downto 0); + \genblk3[1].rnk_config_strobe_r_reg[1]_0\ <= \^genblk3[1].rnk_config_strobe_r_reg[1]_0\; + granted_col_r_reg_0 <= \^granted_col_r_reg_0\; + insert_maint_r1_lcl_reg_0 <= \^insert_maint_r1_lcl_reg_0\; + ofs_rdy_r_reg <= \^ofs_rdy_r_reg\; + rnk_config_valid_r <= \^rnk_config_valid_r\; +\cmd_pipe_plus.mc_cas_n[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0055FC55" + ) + port map ( + I0 => sent_row, + I1 => maint_srx_r, + I2 => maint_zq_r, + I3 => \^insert_maint_r1_lcl_reg_0\, + I4 => \cmd_pipe_plus.mc_ras_n_reg[0]\, + O => \cmd_pipe_plus.mc_cas_n[0]_i_2_n_0\ + ); +\cmd_pipe_plus.mc_cas_n[1]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^granted_col_r_reg_0\, + O => mc_cas_n_ns(1) + ); +\cmd_pipe_plus.mc_ras_n[2]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => cs_en2, + O => mc_ras_n_ns(1) + ); +\cmd_pipe_plus.mc_we_n[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^insert_maint_r1_lcl_reg_0\, + I1 => sent_row, + O => \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\ + ); +col_arb0: entity work.\ddr3_mig_7series_v4_2_round_robin_arb__parameterized1\ + port map ( + CLK => CLK, + D(0) => D(1), + DIC(0) => DIC(0), + I119(0) => I119(0), + I121(0) => I121(0), + O(0) => O(0), + Q(3 downto 0) => \^q\(3 downto 0), + auto_pre_r => auto_pre_r, + auto_pre_r_7 => auto_pre_r_7, + auto_pre_r_8 => auto_pre_r_8, + auto_pre_r_9 => auto_pre_r_9, + \cmd_pipe_plus.mc_address_reg[24]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_0\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]_0\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_1\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]_1\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_2\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]_2\(9 downto 0), + \cmd_pipe_plus.mc_bank_reg[5]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[5]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[5]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[5]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0), + \cmd_pipe_plus.mc_data_offset_reg[0]\ => \^granted_col_r_reg_0\, + \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\, + col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0), + \col_mux.col_data_buf_addr_r\(0) => \col_mux.col_data_buf_addr_r\(0), + \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\, + \col_mux.col_periodic_rd_r_reg\ => \col_mux.col_periodic_rd_r_reg\, + col_rd_wr_r => col_rd_wr_r, + col_wait_r => col_wait_r, + col_wait_r_0 => col_wait_r_0, + col_wait_r_2 => col_wait_r_2, + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0), + \genblk3[1].rnk_config_strobe_r_reg\ => \genblk3[1].rnk_config_strobe_r_reg\, + \genblk3[1].rnk_config_strobe_r_reg[1]\ => \^genblk3[1].rnk_config_strobe_r_reg[1]_0\, + \genblk3[2].rnk_config_strobe_r_reg\ => \genblk3[2].rnk_config_strobe_r_reg\, + \grant_r[3]_i_4\(0) => \grant_r[3]_i_4\(0), + \grant_r[3]_i_4_0\ => \grant_r[3]_i_4_0\, + \grant_r_reg[0]_0\ => \grant_r_reg[0]\, + \grant_r_reg[0]_1\ => \grant_r_reg[0]_0\, + \grant_r_reg[0]_2\ => config_arb0_n_2, + \grant_r_reg[1]_0\ => \grant_r_reg[1]\, + \grant_r_reg[1]_1\ => \grant_r_reg[1]_0\, + \grant_r_reg[1]_2\ => \grant_r_reg[1]_1\, + \grant_r_reg[2]_0\ => \^ofs_rdy_r_reg\, + \grant_r_reg[2]_1\ => \grant_r_reg[2]_0\, + \grant_r_reg[3]_0\ => \grant_r_reg[3]\, + \grant_r_reg[3]_1\ => \grant_r_reg[3]_3\, + \grant_r_reg[3]_2\ => config_arb0_n_3, + granted_col_ns => granted_col_ns, + granted_col_r_reg => granted_col_r_reg_1, + granted_col_r_reg_0(0) => granted_col_r_reg_2(0), + granted_col_r_reg_1(2 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_1\(5 downto 3), + granted_col_r_reg_2(10 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(25 downto 15), + granted_col_r_reg_3 => granted_col_r_reg_3, + \last_master_r_reg[1]_0\(0) => \last_master_r_reg[1]\(0), + \last_master_r_reg[1]_1\ => \last_master_r_reg[0]\, + mc_aux_out0_1 => mc_aux_out0_1, + \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\, + \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\, + \periodic_rd_generation.read_this_rank_r_reg\ => \periodic_rd_generation.read_this_rank_r_reg\, + rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0), + rd_wr_r(3 downto 0) => rd_wr_r(3 downto 0), + rd_wr_r_lcl_reg => rd_wr_r_lcl_reg, + req_data_buf_addr_r(19 downto 0) => req_data_buf_addr_r(19 downto 0), + req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0), + rnk_config_strobe => rnk_config_strobe, + wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0), + \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\ + ); +config_arb0: entity work.\ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_3\ + port map ( + CLK => CLK, + Q(2) => \^q\(3), + Q(1 downto 0) => \^q\(1 downto 0), + \genblk3[1].rnk_config_strobe_r_reg\ => \genblk3[1].rnk_config_strobe_r_reg\, + \genblk3[2].rnk_config_strobe_r_reg\ => \genblk3[2].rnk_config_strobe_r_reg\, + \grant_r[2]_i_3\ => \^genblk3[1].rnk_config_strobe_r_reg[1]_0\, + \grant_r[2]_i_3_0\ => \grant_r[2]_i_3\, + \grant_r[2]_i_3_1\ => \grant_r[2]_i_3_0\, + \grant_r[3]_i_3__0\ => \grant_r[3]_i_3__0\, + \grant_r[3]_i_3__0_0\ => \grant_r[3]_i_3__0_0\, + \grant_r[3]_i_6\ => \grant_r[3]_i_6\, + \grant_r[3]_i_6_0\ => \grant_r[3]_i_6_0\, + \grant_r_reg[0]_0\ => \grant_r_reg[0]_1\, + \grant_r_reg[0]_1\ => \grant_r_reg[0]_2\, + \grant_r_reg[0]_2\ => \grant_r_reg[0]_3\, + \grant_r_reg[2]_0\ => \grant_r_reg[2]\, + \last_master_r_reg[1]_0\ => \last_master_r_reg[0]\, + ofs_rdy_r => ofs_rdy_r, + ofs_rdy_r_1 => ofs_rdy_r_1, + ofs_rdy_r_3 => ofs_rdy_r_3, + ofs_rdy_r_reg => \^ofs_rdy_r_reg\, + ofs_rdy_r_reg_0 => config_arb0_n_2, + ofs_rdy_r_reg_1 => config_arb0_n_3, + rnk_config_0 => rnk_config_0, + rnk_config_r => rnk_config_r, + \rnk_config_r_reg[0]\ => \cmd_pipe_plus.mc_ras_n_reg[0]\, + rnk_config_strobe => rnk_config_strobe, + \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]_0\, + \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_1\, + rnk_config_valid_r => \^rnk_config_valid_r\ + ); +\genblk3[1].rnk_config_strobe_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rnk_config_strobe, + Q => \genblk3[1].rnk_config_strobe_r_reg\, + R => '0' + ); +\genblk3[2].rnk_config_strobe_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \genblk3[1].rnk_config_strobe_r_reg\, + Q => \genblk3[2].rnk_config_strobe_r_reg\, + R => '0' + ); +granted_col_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => granted_col_ns, + Q => \^granted_col_r_reg_0\, + R => '0' + ); +granted_row_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => granted_row_ns, + Q => sent_row, + R => '0' + ); +insert_maint_r1_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => insert_maint_r1_lcl_reg_1, + Q => \^insert_maint_r1_lcl_reg_0\, + R => '0' + ); +\pre_4_1_1T_arb.granted_pre_r_reg\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \pre_4_1_1T_arb.granted_pre_ns\, + Q => cs_en2, + R => '0' + ); +\pre_4_1_1T_arb.pre_arb0\: entity work.\ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_4\ + port map ( + CLK => CLK, + D(0) => D(2), + Q(3 downto 0) => \grant_r_reg[3]_0\(3 downto 0), + \cmd_pipe_plus.mc_address_reg[40]\ => \cmd_pipe_plus.mc_address_reg[40]\, + \cmd_pipe_plus.mc_address_reg[44]\(14 downto 0) => \cmd_pipe_plus.mc_address_reg[14]\(14 downto 0), + \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[8]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[8]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[8]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0), + cs_en2 => cs_en2, + \grant_r_reg[0]_0\ => \grant_r_reg[0]_4\, + \grant_r_reg[0]_1\ => \grant_r_reg[0]_5\, + \grant_r_reg[0]_2\ => \grant_r_reg[0]_6\, + \grant_r_reg[1]_0\ => \grant_r_reg[1]_2\, + \last_master_r_reg[1]_0\ => \last_master_r_reg[0]\, + mc_cas_n_ns(0) => mc_cas_n_ns(2), + \pre_4_1_1T_arb.granted_pre_r_reg\(14 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(40 downto 26), + \pre_4_1_1T_arb.granted_pre_r_reg_0\(2 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_1\(8 downto 6), + req_row_r(42 downto 24) => req_row_r(43 downto 25), + req_row_r(23 downto 0) => req_row_r(23 downto 0), + row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0) + ); +\rnk_config_strobe_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rnk_config_strobe_ns, + Q => rnk_config_strobe, + R => '0' + ); +rnk_config_valid_r_lcl_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rnk_config_valid_r_lcl_reg_1, + Q => \^rnk_config_valid_r\, + R => rnk_config_valid_r_lcl_reg_0(0) + ); +row_arb0: entity work.\ddr3_mig_7series_v4_2_round_robin_arb__parameterized1_5\ + port map ( + CLK => CLK, + D(0) => D(0), + Q(3 downto 0) => \grant_r_reg[3]_1\(3 downto 0), + act_this_rank => act_this_rank, + act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0), + \cmd_pipe_plus.mc_address_reg[10]\ => \cmd_pipe_plus.mc_address_reg[10]\, + \cmd_pipe_plus.mc_address_reg[14]\(14 downto 0) => \cmd_pipe_plus.mc_address_reg[14]\(14 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]\ => \^insert_maint_r1_lcl_reg_0\, + \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]_2\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]_3\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0), + \cmd_pipe_plus.mc_cas_n_reg[0]\ => \cmd_pipe_plus.mc_cas_n[0]_i_2_n_0\, + \cmd_pipe_plus.mc_ras_n_reg[0]\ => \cmd_pipe_plus.mc_ras_n_reg[0]\, + \cmd_pipe_plus.mc_we_n_reg[0]\ => \cmd_pipe_plus.mc_we_n_reg[0]\, + \cmd_pipe_plus.mc_we_n_reg[0]_0\ => \cmd_pipe_plus.mc_we_n[0]_i_2_n_0\, + demand_act_priority_r => demand_act_priority_r, + demand_act_priority_r_4 => demand_act_priority_r_4, + demand_act_priority_r_5 => demand_act_priority_r_5, + demand_act_priority_r_6 => demand_act_priority_r_6, + \grant_r[2]_i_3__1_0\ => insert_maint_r1_lcl_reg_1, + \grant_r_reg[3]_0\ => \grant_r_reg[3]_2\, + \grant_r_reg[3]_1\ => \grant_r_reg[3]_4\, + \grant_r_reg[3]_2\ => \grant_r_reg[3]_5\, + \grant_r_reg[3]_3\ => \grant_r_reg[3]_6\, + \grant_r_reg[3]_4\ => \grant_r_reg[3]_7\, + \grant_r_reg[3]_5\ => \grant_r_reg[3]_8\, + granted_row_ns => granted_row_ns, + granted_row_r_reg => granted_row_r_reg_0, + granted_row_r_reg_0 => granted_row_r_reg_1, + inhbt_act_faw_r => inhbt_act_faw_r, + insert_maint_r1_lcl_reg(2 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_1\(2 downto 0), + \last_master_r_reg[0]_0\ => \last_master_r_reg[0]\, + maint_srx_r => maint_srx_r, + maint_zq_r => maint_zq_r, + mc_cas_n_ns(0) => mc_cas_n_ns(0), + mc_ras_n_ns(0) => mc_ras_n_ns(0), + req_row_r(42 downto 39) => req_row_r(43 downto 40), + req_row_r(38 downto 0) => req_row_r(38 downto 0), + \req_row_r_lcl_reg[14]\(14 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(14 downto 0), + row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0), + sent_row => sent_row + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_cntrl is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rb_hit_busy_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + bm_end : out STD_LOGIC_VECTOR ( 0 to 0 ); + row_cmd_wr : out STD_LOGIC_VECTOR ( 0 to 0 ); + col_wait_r : out STD_LOGIC; + demand_act_priority_r : out STD_LOGIC; + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + demand_priority_r : out STD_LOGIC; + demanded_prior_r : out STD_LOGIC; + ofs_rdy_r : out STD_LOGIC; + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + q_has_rd : out STD_LOGIC; + wait_for_maint_r_lcl_reg : out STD_LOGIC; + head_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + auto_pre_r : out STD_LOGIC; + ordered_r : out STD_LOGIC; + idle_r_lcl_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg_0 : out STD_LOGIC; + pre_bm_end_r_reg : out STD_LOGIC; + \q_entry_r_reg[1]\ : out STD_LOGIC; + override_demand_r_reg : out STD_LOGIC; + idle_r_lcl_reg_1 : out STD_LOGIC; + bm_end_r1_reg : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + \order_q_r_reg[1]\ : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + pre_passing_open_bank_r_reg : out STD_LOGIC; + idle_r_lcl_reg_2 : out STD_LOGIC; + p_9_in : out STD_LOGIC; + idle_r_lcl_reg_3 : out STD_LOGIC; + idle_r_lcl_reg_4 : out STD_LOGIC; + pre_bm_end_r_reg_0 : out STD_LOGIC; + pre_bm_end_r_reg_1 : out STD_LOGIC; + idle_r_lcl_reg_5 : out STD_LOGIC; + rb_hit_busy_r_reg : out STD_LOGIC; + rb_hit_busy_r_reg_0 : out STD_LOGIC; + act_wait_r_lcl_reg : out STD_LOGIC; + act_wait_r_lcl_reg_0 : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + demand_priority_r_reg : out STD_LOGIC; + ofs_rdy_r0 : out STD_LOGIC; + ofs_rdy_r0_0 : out STD_LOGIC; + ofs_rdy_r0_1 : out STD_LOGIC; + \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + CLK : in STD_LOGIC; + periodic_rd_insert : in STD_LOGIC; + req_wr_r_lcl0 : in STD_LOGIC; + req_priority_r_reg : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_mc_ctl_full : in STD_LOGIC; + phy_mc_cmd_full : in STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + pre_wait_r_reg : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[0]\ : in STD_LOGIC; + q_has_rd_r_reg : in STD_LOGIC; + was_wr : in STD_LOGIC; + q_has_priority_r_reg : in STD_LOGIC; + was_priority : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC; + col_wait_r_reg_0 : in STD_LOGIC; + demanded_prior_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); + override_demand_r : in STD_LOGIC; + demanded_prior_r_reg_0 : in STD_LOGIC; + demand_priority_r_2 : in STD_LOGIC; + \q_entry_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + act_wait_r_lcl_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \q_entry_r_reg[1]_3\ : in STD_LOGIC; + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + pre_bm_end_r_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + accept_internal_r_reg : in STD_LOGIC; + accept_internal_r_reg_0 : in STD_LOGIC; + accept_internal_r_reg_1 : in STD_LOGIC; + accept_internal_r_reg_2 : in STD_LOGIC; + rd_wr_r_lcl_reg : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + \starve_limit_cntr_r_reg[0]\ : in STD_LOGIC; + demanded_prior_r_3 : in STD_LOGIC; + phy_mc_data_full : in STD_LOGIC; + ofs_rdy_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rtp_timer_r_reg[0]\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \q_entry_r_reg[0]_1\ : in STD_LOGIC; + \q_entry_r_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]_0\ : in STD_LOGIC; + \order_q_r_reg[0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_cntrl : entity is "mig_7series_v4_2_bank_cntrl"; +end ddr3_mig_7series_v4_2_bank_cntrl; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_cntrl is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal act_wait_ns : STD_LOGIC; + signal \^auto_pre_r\ : STD_LOGIC; + signal bank_compare0_n_11 : STD_LOGIC; + signal bank_compare0_n_7 : STD_LOGIC; + signal bank_compare0_n_8 : STD_LOGIC; + signal bank_state0_n_19 : STD_LOGIC; + signal bank_state0_n_21 : STD_LOGIC; + signal bank_state0_n_5 : STD_LOGIC; + signal \^bm_end\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal bm_end_r1 : STD_LOGIC; + signal \^bm_end_r1_reg\ : STD_LOGIC; + signal \^bm_end_r1_reg_0\ : STD_LOGIC; + signal \^col_wait_r\ : STD_LOGIC; + signal demand_priority_ns : STD_LOGIC; + signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal idle_ns : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^idle_r_lcl_reg_0\ : STD_LOGIC; + signal \^ordered_r\ : STD_LOGIC; + signal pass_open_bank_ns : STD_LOGIC; + signal pass_open_bank_r : STD_LOGIC; + signal pre_bm_end_ns : STD_LOGIC; + signal pre_bm_end_r : STD_LOGIC; + signal pre_passing_open_bank_ns : STD_LOGIC; + signal pre_wait_r : STD_LOGIC; + signal \^q_entry_r_reg[1]\ : STD_LOGIC; + signal \^q_has_rd\ : STD_LOGIC; + signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ras_timer_zero_r : STD_LOGIC; + signal \^rb_hit_busy_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rb_hit_busy_r_reg\ : STD_LOGIC; + signal \^rb_hit_busy_r_reg_0\ : STD_LOGIC; + signal \^rd_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal req_bank_rdy_ns : STD_LOGIC; + signal req_priority_r : STD_LOGIC; + signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal row_hit_r : STD_LOGIC; + signal set_order_q : STD_LOGIC; + signal start_wtp_timer0 : STD_LOGIC; + signal tail_r : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg\ : STD_LOGIC; +begin + E(0) <= \^e\(0); + auto_pre_r <= \^auto_pre_r\; + bm_end(0) <= \^bm_end\(0); + bm_end_r1_reg <= \^bm_end_r1_reg\; + bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\; + col_wait_r <= \^col_wait_r\; + head_r(0) <= \^head_r\(0); + idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\; + ordered_r <= \^ordered_r\; + \q_entry_r_reg[1]\ <= \^q_entry_r_reg[1]\; + q_has_rd <= \^q_has_rd\; + rb_hit_busy_r(0) <= \^rb_hit_busy_r\(0); + rb_hit_busy_r_reg <= \^rb_hit_busy_r_reg\; + rb_hit_busy_r_reg_0 <= \^rb_hit_busy_r_reg_0\; + rd_wr_r(0) <= \^rd_wr_r\(0); + req_wr_r(0) <= \^req_wr_r\(0); + row_cmd_wr(0) <= \^row_cmd_wr\(0); + wait_for_maint_r_lcl_reg <= \^wait_for_maint_r_lcl_reg\; +bank_compare0: entity work.ddr3_mig_7series_v4_2_bank_compare_2 + port map ( + CLK => CLK, + E(0) => idle_ns(0), + S(3 downto 0) => S(3 downto 0), + maint_req_r => maint_req_r, + ordered_r => \^ordered_r\, + ordered_r_lcl_reg => col_wait_r_reg_0, + ordered_r_lcl_reg_0 => \q_entry_r_reg[0]\, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pass_open_bank_r_lcl_reg => \compute_tail.tail_r_lcl_reg_0\, + pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0, + pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_lcl_reg_1, + pass_open_bank_r_lcl_reg_3 => \^wait_for_maint_r_lcl_reg\, + periodic_rd_insert => periodic_rd_insert, + pre_bm_end_r => pre_bm_end_r, + pre_wait_r => pre_wait_r, + \q_entry_r[1]_i_4__0\(2 downto 0) => \q_entry_r_reg[0]_0\(2 downto 0), + rb_hit_busy_r_reg_0 => \^rb_hit_busy_r\(0), + rb_hit_busy_r_reg_1 => \^rb_hit_busy_r_reg_0\, + rb_hit_busy_r_reg_2 => \^rb_hit_busy_r_reg\, + rb_hit_busy_r_reg_3 => rb_hit_busy_r_reg_1, + rd_wr_r_lcl_reg_0 => \^rd_wr_r\(0), + rd_wr_r_lcl_reg_1 => bank_compare0_n_11, + rd_wr_r_lcl_reg_2(0) => demanded_prior_r_reg(0), + rd_wr_r_lcl_reg_3 => \^idle_r_lcl_reg_0\, + rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg, + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0), + \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0), + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + \req_data_buf_addr_r_reg[4]_1\ => \^e\(0), + \req_data_buf_addr_r_reg[4]_2\(4 downto 0) => \req_data_buf_addr_r_reg[4]_0\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(0), + req_priority_r => req_priority_r, + req_priority_r_reg_0 => req_priority_r_reg, + \req_row_r_lcl_reg[14]_0\(14 downto 0) => \req_row_r_lcl_reg[14]\(14 downto 0), + req_wr_r_lcl0 => req_wr_r_lcl0, + req_wr_r_lcl_reg_0 => \^req_wr_r\(0), + row(14 downto 0) => row(14 downto 0), + row_hit_r => row_hit_r, + row_hit_r_reg_0(0) => row_hit_r_reg(0), + \rstdiv0_sync_r1_reg_rep__13\ => bank_compare0_n_7, + \rstdiv0_sync_r1_reg_rep__13_0\ => bank_compare0_n_8, + set_order_q => set_order_q, + start_wtp_timer0 => start_wtp_timer0, + tail_r => tail_r + ); +bank_queue0: entity work.ddr3_mig_7series_v4_2_bank_queue + port map ( + CLK => CLK, + D(0) => D(0), + E(0) => idle_ns(0), + Q(0) => Q(0), + SR(0) => SR(0), + accept_internal_r_reg => accept_internal_r_reg, + accept_internal_r_reg_0 => accept_internal_r_reg_0, + accept_internal_r_reg_1 => accept_internal_r_reg_1, + accept_internal_r_reg_2 => accept_internal_r_reg_2, + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg => act_wait_r_lcl_reg, + act_wait_r_lcl_reg_0(0) => act_wait_r_lcl_reg_1(0), + act_wait_r_lcl_reg_1 => \^row_cmd_wr\(0), + auto_pre_r_lcl_reg_0 => \^auto_pre_r\, + auto_pre_r_lcl_reg_1 => bank_state0_n_19, + auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_0, + auto_pre_r_lcl_reg_3 => bank_compare0_n_7, + bm_end_r1 => bm_end_r1, + bm_end_r1_reg => \^rd_wr_r\(0), + bm_end_r1_reg_0(0) => demanded_prior_r_reg(0), + bm_end_r1_reg_1 => \^req_wr_r\(0), + col_wait_r_reg => col_wait_r_reg, + \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\, + \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\, + demand_priority_ns => demand_priority_ns, + demand_priority_r_reg => bank_state0_n_5, + demand_priority_r_reg_0 => bank_state0_n_21, + head_r_lcl_reg_0 => \^head_r\(0), + head_r_lcl_reg_1 => \^rb_hit_busy_r_reg\, + head_r_lcl_reg_2 => \^rb_hit_busy_r_reg_0\, + idle_r_lcl_reg_0 => \^e\(0), + idle_r_lcl_reg_1 => idle_r_lcl_reg, + idle_r_lcl_reg_2 => \^idle_r_lcl_reg_0\, + idle_r_lcl_reg_3 => idle_r_lcl_reg_1, + idle_r_lcl_reg_4 => idle_r_lcl_reg_2, + idle_r_lcl_reg_5 => idle_r_lcl_reg_3, + idle_r_lcl_reg_6 => idle_r_lcl_reg_4, + idle_r_lcl_reg_7 => idle_r_lcl_reg_5, + \maint_controller.maint_hit_busies_r_reg[0]\ => \maint_controller.maint_hit_busies_r_reg[0]\, + \order_q_r_reg[0]_0\ => \order_q_r_reg[0]\, + \order_q_r_reg[1]_0\ => \order_q_r_reg[1]\, + \order_q_r_reg[1]_1\ => \order_q_r_reg[1]_0\, + ordered_r => \^ordered_r\, + ordered_r_lcl_reg_0 => bank_compare0_n_8, + p_9_in => p_9_in, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pre_bm_end_ns => pre_bm_end_ns, + pre_bm_end_r => pre_bm_end_r, + pre_bm_end_r_reg_0 => \^bm_end\(0), + pre_bm_end_r_reg_1 => pre_bm_end_r_reg, + pre_bm_end_r_reg_2 => pre_bm_end_r_reg_0, + pre_bm_end_r_reg_3 => pre_bm_end_r_reg_1, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg, + \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\, + \q_entry_r_reg[0]_1\(2 downto 0) => \q_entry_r_reg[0]_0\(2 downto 0), + \q_entry_r_reg[0]_2\ => \q_entry_r_reg[0]_1\, + \q_entry_r_reg[1]_0\ => \^q_entry_r_reg[1]\, + \q_entry_r_reg[1]_1\(1 downto 0) => ras_timer_passed_ns(1 downto 0), + \q_entry_r_reg[1]_2\(0) => \q_entry_r_reg[1]_0\(0), + \q_entry_r_reg[1]_3\(0) => \q_entry_r_reg[1]_1\(0), + \q_entry_r_reg[1]_4\(0) => \q_entry_r_reg[1]_2\(0), + \q_entry_r_reg[1]_5\ => \q_entry_r_reg[1]_3\, + \q_entry_r_reg[1]_6\(0) => \q_entry_r_reg[1]_4\(0), + q_has_priority_r_reg_0 => pre_wait_r_reg, + q_has_priority_r_reg_1 => \^rb_hit_busy_r\(0), + q_has_priority_r_reg_2 => q_has_priority_r_reg, + q_has_rd => \^q_has_rd\, + q_has_rd_r_reg_0 => q_has_rd_r_reg, + \ras_timer_r_reg[0]\ => \^bm_end_r1_reg_0\, + \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\, + \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\, + \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\, + \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\, + \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\, + \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\, + \ras_timer_r_reg[1]\ => \^bm_end_r1_reg\, + \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]\, + \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_0\, + \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_1\, + ras_timer_zero_r => ras_timer_zero_r, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => col_wait_r_reg_0, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2\(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0), + req_bank_rdy_ns => req_bank_rdy_ns, + req_bank_rdy_r_reg => \^col_wait_r\, + req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg, + req_priority_r => req_priority_r, + \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\, + \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\, + row_hit_r => row_hit_r, + set_order_q => set_order_q, + tail_r => tail_r, + wait_for_maint_r_lcl_reg_0 => \^wait_for_maint_r_lcl_reg\, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0, + wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_1, + was_priority => was_priority, + was_wr => was_wr + ); +bank_state0: entity work.ddr3_mig_7series_v4_2_bank_state + port map ( + CLK => CLK, + D(1 downto 0) => ras_timer_passed_ns(1 downto 0), + E(0) => \^e\(0), + SR(0) => SR(0), + act_this_rank_r(0) => act_this_rank_r(0), + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0), + act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_0, + auto_pre_r_lcl_reg => auto_pre_r_lcl_reg, + auto_pre_r_lcl_reg_0 => q_has_priority_r_reg, + bm_end(0) => \^bm_end\(0), + bm_end_r1 => bm_end_r1, + bm_end_r1_reg_0 => \^bm_end_r1_reg_0\, + bm_end_r1_reg_1 => \^bm_end_r1_reg\, + col_wait_r_reg_0 => \^col_wait_r\, + col_wait_r_reg_1 => col_wait_r_reg_0, + col_wait_r_reg_2 => \^q_entry_r_reg[1]\, + \compute_tail.tail_r_lcl_reg\ => bank_state0_n_19, + demand_act_priority_r => demand_act_priority_r, + demand_act_priority_r_reg_0 => \^wait_for_maint_r_lcl_reg\, + demand_priority_ns => demand_priority_ns, + demand_priority_r_2 => demand_priority_r_2, + demand_priority_r_reg_0 => demand_priority_r, + demand_priority_r_reg_1 => bank_state0_n_21, + demand_priority_r_reg_2 => demand_priority_r_reg, + demanded_prior_r_3 => demanded_prior_r_3, + demanded_prior_r_reg_0 => demanded_prior_r, + demanded_prior_r_reg_1(1 downto 0) => demanded_prior_r_reg(1 downto 0), + demanded_prior_r_reg_2 => demanded_prior_r_reg_0, + \grant_r[3]_i_3__1\(0) => act_wait_r_lcl_reg_1(0), + head_r(0) => \^head_r\(0), + ofs_rdy_r => ofs_rdy_r, + ofs_rdy_r0 => ofs_rdy_r0, + ofs_rdy_r0_0 => ofs_rdy_r0_0, + ofs_rdy_r0_1 => ofs_rdy_r0_1, + ofs_rdy_r_reg_0(2 downto 0) => ofs_rdy_r_reg(2 downto 0), + override_demand_r => override_demand_r, + override_demand_r_reg => override_demand_r_reg, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_data_full => phy_mc_data_full, + pre_bm_end_ns => pre_bm_end_ns, + pre_bm_end_r_reg(0) => pre_bm_end_r_reg_2(0), + pre_bm_end_r_reg_0 => \^auto_pre_r\, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_wait_r => pre_wait_r, + pre_wait_r_reg_0 => pre_wait_r_reg, + q_has_rd => \^q_has_rd\, + ras_timer_zero_r => ras_timer_zero_r, + ras_timer_zero_r_reg_0 => bank_compare0_n_11, + rb_hit_busy_r(0) => \^rb_hit_busy_r\(0), + rd_this_rank_r(0) => rd_this_rank_r(0), + \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r\(0), + req_bank_rdy_ns => req_bank_rdy_ns, + req_wr_r(0) => \^req_wr_r\(0), + \rstdiv0_sync_r1_reg_rep__13\ => bank_state0_n_5, + \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\, + start_wtp_timer0 => start_wtp_timer0, + \starve_limit_cntr_r_reg[0]_0\ => \starve_limit_cntr_r_reg[0]\, + tail_r => tail_r, + wr_this_rank_r(0) => wr_this_rank_r(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_cntrl__parameterized0\ is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + rb_hit_busy_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + row_cmd_wr : out STD_LOGIC_VECTOR ( 0 to 0 ); + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + col_wait_r : out STD_LOGIC; + demand_act_priority_r : out STD_LOGIC; + demand_priority_r : out STD_LOGIC; + demanded_prior_r : out STD_LOGIC; + ofs_rdy_r : out STD_LOGIC; + q_has_rd_0 : out STD_LOGIC; + wait_for_maint_r_lcl_reg : out STD_LOGIC; + head_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + ordered_r_lcl : out STD_LOGIC; + auto_pre_r : out STD_LOGIC; + pre_bm_end_r_reg : out STD_LOGIC; + \q_entry_r_reg[1]\ : out STD_LOGIC; + idle_r_lcl_reg : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg_0 : out STD_LOGIC; + rnk_config_valid_r_lcl_reg : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + rnk_config_strobe_ns : out STD_LOGIC; + bm_end_r1_reg : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + \order_q_r_reg[1]\ : out STD_LOGIC; + req_wr_r_lcl_reg : out STD_LOGIC; + rd_wr_r_lcl_reg_0 : out STD_LOGIC; + act_wait_r_lcl_reg : out STD_LOGIC; + pre_passing_open_bank_r_reg : out STD_LOGIC; + act_wait_r_lcl_reg_0 : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_row_r_lcl_reg[10]\ : out STD_LOGIC; + demand_priority_r_reg : out STD_LOGIC; + demanded_prior_r_reg : out STD_LOGIC; + \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + CLK : in STD_LOGIC; + periodic_rd_insert : in STD_LOGIC; + req_bank_rdy_r_i_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg_0 : in STD_LOGIC; + req_priority_r_reg : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ofs_rdy_r0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + head_r_lcl_reg : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC; + col_wait_r_reg_0 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + q_has_priority_r_reg : in STD_LOGIC; + \q_entry_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + pre_wait_r_reg : in STD_LOGIC; + \maint_controller.maint_hit_busies_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[1]_0\ : in STD_LOGIC; + q_has_rd_r_reg : in STD_LOGIC; + was_wr : in STD_LOGIC; + was_priority : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_1\ : in STD_LOGIC; + rnk_config_valid_r : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \rnk_config_strobe_r_reg[0]_2\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_3\ : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \q_entry_r_reg[1]_0\ : in STD_LOGIC; + \q_entry_r_reg[1]_1\ : in STD_LOGIC; + head_r_lcl_reg_0 : in STD_LOGIC; + \q_entry_r_reg[0]_2\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ : in STD_LOGIC; + rd_wr_r_lcl_reg_1 : in STD_LOGIC; + rd_wr_r : in STD_LOGIC_VECTOR ( 0 to 0 ); + pre_bm_end_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \cmd_pipe_plus.mc_address_reg[10]_0\ : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[10]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_address_reg[10]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + demand_priority_r_0 : in STD_LOGIC; + demanded_prior_r_reg_0 : in STD_LOGIC; + demanded_prior_r_1 : in STD_LOGIC; + \starve_limit_cntr_r_reg[0]\ : in STD_LOGIC; + \rtp_timer_r_reg[0]\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \q_entry_r_reg[0]_3\ : in STD_LOGIC; + \q_entry_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]_0\ : in STD_LOGIC; + \order_q_r_reg[0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_cntrl__parameterized0\ : entity is "mig_7series_v4_2_bank_cntrl"; +end \ddr3_mig_7series_v4_2_bank_cntrl__parameterized0\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_cntrl__parameterized0\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal act_wait_ns : STD_LOGIC; + signal \^auto_pre_r\ : STD_LOGIC; + signal bank_compare0_n_11 : STD_LOGIC; + signal bank_compare0_n_6 : STD_LOGIC; + signal bank_compare0_n_8 : STD_LOGIC; + signal bank_state0_n_18 : STD_LOGIC; + signal bank_state0_n_22 : STD_LOGIC; + signal bank_state0_n_8 : STD_LOGIC; + signal bm_end : STD_LOGIC_VECTOR ( 1 to 1 ); + signal bm_end_r1 : STD_LOGIC; + signal \^bm_end_r1_reg\ : STD_LOGIC; + signal \^bm_end_r1_reg_0\ : STD_LOGIC; + signal \^col_wait_r\ : STD_LOGIC; + signal demand_priority_ns : STD_LOGIC; + signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal idle_ns : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^idle_r_lcl_reg_0\ : STD_LOGIC; + signal \^ordered_r_lcl\ : STD_LOGIC; + signal pass_open_bank_ns : STD_LOGIC; + signal pass_open_bank_r : STD_LOGIC; + signal pre_bm_end_ns : STD_LOGIC; + signal pre_bm_end_r : STD_LOGIC; + signal pre_passing_open_bank_ns : STD_LOGIC; + signal pre_wait_r : STD_LOGIC; + signal \^q_entry_r_reg[1]\ : STD_LOGIC; + signal \^q_has_rd_0\ : STD_LOGIC; + signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ras_timer_zero_r : STD_LOGIC; + signal \^rb_hit_busy_r_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rd_wr_r_lcl_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal req_bank_rdy_ns : STD_LOGIC; + signal req_priority_r : STD_LOGIC; + signal req_wr_r : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal row_hit_r : STD_LOGIC; + signal set_order_q : STD_LOGIC; + signal start_wtp_timer0 : STD_LOGIC; + signal tail_r : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg\ : STD_LOGIC; +begin + E(0) <= \^e\(0); + auto_pre_r <= \^auto_pre_r\; + bm_end_r1_reg <= \^bm_end_r1_reg\; + bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\; + col_wait_r <= \^col_wait_r\; + head_r(0) <= \^head_r\(0); + idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\; + ordered_r_lcl <= \^ordered_r_lcl\; + \q_entry_r_reg[1]\ <= \^q_entry_r_reg[1]\; + q_has_rd_0 <= \^q_has_rd_0\; + rb_hit_busy_r_reg(0) <= \^rb_hit_busy_r_reg\(0); + rd_wr_r_lcl_reg(0) <= \^rd_wr_r_lcl_reg\(0); + row_cmd_wr(0) <= \^row_cmd_wr\(0); + wait_for_maint_r_lcl_reg <= \^wait_for_maint_r_lcl_reg\; +bank_compare0: entity work.ddr3_mig_7series_v4_2_bank_compare_1 + port map ( + CLK => CLK, + E(0) => idle_ns(1), + Q(1 downto 0) => Q(1 downto 0), + bm_end(0) => bm_end(1), + \cmd_pipe_plus.mc_address_reg[10]\ => \^row_cmd_wr\(0), + \cmd_pipe_plus.mc_address_reg[10]_0\ => \cmd_pipe_plus.mc_address_reg[10]_0\, + \cmd_pipe_plus.mc_address_reg[10]_1\(0) => \cmd_pipe_plus.mc_address_reg[10]_1\(0), + \cmd_pipe_plus.mc_address_reg[10]_2\(0) => \cmd_pipe_plus.mc_address_reg[10]\(1), + \cmd_pipe_plus.mc_address_reg[10]_3\(0) => \cmd_pipe_plus.mc_address_reg[10]_2\(0), + head_r_lcl_reg(0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0), + maint_req_r => maint_req_r, + ordered_r_lcl => \^ordered_r_lcl\, + ordered_r_lcl_reg => pre_wait_r_reg, + ordered_r_lcl_reg_0 => \compute_tail.tail_r_lcl_reg\, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pass_open_bank_r_lcl_reg => \compute_tail.tail_r_lcl_reg_0\, + pass_open_bank_r_lcl_reg_0 => pass_open_bank_r_lcl_reg, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg_0, + pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_lcl_reg_1, + pass_open_bank_r_lcl_reg_3 => \^wait_for_maint_r_lcl_reg\, + periodic_rd_insert => periodic_rd_insert, + pre_bm_end_r => pre_bm_end_r, + pre_wait_r => pre_wait_r, + rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\(0), + rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_0, + rd_wr_r(0) => rd_wr_r(0), + rd_wr_r_lcl_reg_0 => \^rd_wr_r_lcl_reg\(0), + rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg_0, + rd_wr_r_lcl_reg_2 => bank_compare0_n_11, + rd_wr_r_lcl_reg_3 => \^idle_r_lcl_reg_0\, + rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg_1, + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0), + \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0), + req_bank_rdy_r_i_2(0) => req_bank_rdy_r_i_2(0), + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + \req_data_buf_addr_r_reg[4]_1\ => \^e\(0), + \req_data_buf_addr_r_reg[4]_2\(4 downto 0) => \req_data_buf_addr_r_reg[4]_0\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(0), + req_priority_r => req_priority_r, + req_priority_r_reg_0 => req_priority_r_reg, + \req_row_r_lcl_reg[10]_0\ => \req_row_r_lcl_reg[10]\, + \req_row_r_lcl_reg[14]_0\(14 downto 0) => \req_row_r_lcl_reg[14]\(14 downto 0), + req_wr_r(0) => req_wr_r(1), + req_wr_r_lcl0 => req_wr_r_lcl0, + req_wr_r_lcl_reg_0 => req_wr_r_lcl_reg, + row(14 downto 0) => row(14 downto 0), + row_hit_r => row_hit_r, + \rstdiv0_sync_r1_reg_rep__13\ => bank_compare0_n_6, + \rstdiv0_sync_r1_reg_rep__13_0\ => bank_compare0_n_8, + set_order_q => set_order_q, + start_wtp_timer0 => start_wtp_timer0, + tail_r => tail_r + ); +bank_queue0: entity work.\ddr3_mig_7series_v4_2_bank_queue__parameterized0\ + port map ( + CLK => CLK, + D(0) => D(0), + E(0) => idle_ns(1), + Q(0) => Q(1), + SR(0) => SR(0), + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg => act_wait_r_lcl_reg_0, + act_wait_r_lcl_reg_0(0) => \cmd_pipe_plus.mc_address_reg[10]\(0), + act_wait_r_lcl_reg_1 => \^row_cmd_wr\(0), + auto_pre_r_lcl_reg_0 => \^auto_pre_r\, + auto_pre_r_lcl_reg_1 => bank_state0_n_18, + auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_0, + auto_pre_r_lcl_reg_3 => bank_compare0_n_6, + bm_end_r1 => bm_end_r1, + col_wait_r_reg => col_wait_r_reg, + \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\, + \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\, + \compute_tail.tail_r_lcl_reg_2\ => \compute_tail.tail_r_lcl_reg_1\, + demand_priority_ns => demand_priority_ns, + demand_priority_r_reg => bank_state0_n_8, + demand_priority_r_reg_0 => bank_state0_n_22, + head_r_lcl_reg_0 => \^head_r\(0), + head_r_lcl_reg_1 => head_r_lcl_reg, + head_r_lcl_reg_2 => head_r_lcl_reg_0, + idle_r_lcl_reg_0 => \^e\(0), + idle_r_lcl_reg_1 => idle_r_lcl_reg, + idle_r_lcl_reg_2 => \^idle_r_lcl_reg_0\, + \maint_controller.maint_hit_busies_r_reg[1]\(0) => \maint_controller.maint_hit_busies_r_reg[1]\(0), + \maint_controller.maint_hit_busies_r_reg[1]_0\ => \maint_controller.maint_hit_busies_r_reg[1]_0\, + \order_q_r_reg[0]_0\ => \order_q_r_reg[0]\, + \order_q_r_reg[1]_0\ => \order_q_r_reg[1]\, + \order_q_r_reg[1]_1\ => \order_q_r_reg[1]_0\, + ordered_r_lcl => \^ordered_r_lcl\, + ordered_r_lcl_reg_0 => bank_compare0_n_8, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pre_bm_end_ns => pre_bm_end_ns, + pre_bm_end_r => pre_bm_end_r, + pre_bm_end_r_reg_0 => pre_bm_end_r_reg, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg, + \q_entry_r_reg[0]_0\(0) => \q_entry_r_reg[0]\(0), + \q_entry_r_reg[0]_1\(0) => \q_entry_r_reg[0]_0\(0), + \q_entry_r_reg[0]_2\(0) => \q_entry_r_reg[0]_1\(0), + \q_entry_r_reg[0]_3\ => \q_entry_r_reg[0]_2\, + \q_entry_r_reg[0]_4\ => \q_entry_r_reg[0]_3\, + \q_entry_r_reg[1]_0\ => \^q_entry_r_reg[1]\, + \q_entry_r_reg[1]_1\(1 downto 0) => ras_timer_passed_ns(1 downto 0), + \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_0\, + \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_1\, + \q_entry_r_reg[1]_4\(0) => \q_entry_r_reg[1]_2\(0), + q_has_priority_r_reg_0 => q_has_priority_r_reg, + q_has_priority_r_reg_1 => pre_wait_r_reg, + q_has_priority_r_reg_2 => \^rb_hit_busy_r_reg\(0), + q_has_rd_0 => \^q_has_rd_0\, + q_has_rd_r_reg_0 => q_has_rd_r_reg, + \ras_timer_r_reg[0]\ => \^bm_end_r1_reg_0\, + \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\, + \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\, + \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\, + \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\, + \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\, + \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\, + \ras_timer_r_reg[1]\ => \^bm_end_r1_reg\, + \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]\, + \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_0\, + \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_1\, + ras_timer_zero_r => ras_timer_zero_r, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(1 downto 0), + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => col_wait_r_reg_0, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\, + req_bank_rdy_ns => req_bank_rdy_ns, + req_bank_rdy_r_reg => \^col_wait_r\, + req_bank_rdy_r_reg_0 => \^rd_wr_r_lcl_reg\(0), + req_bank_rdy_r_reg_1 => req_bank_rdy_r_reg, + req_priority_r => req_priority_r, + req_wr_r(0) => req_wr_r(1), + rnk_config_strobe_ns => rnk_config_strobe_ns, + \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\, + \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\, + \rnk_config_strobe_r_reg[0]_1\ => \rnk_config_strobe_r_reg[0]_1\, + \rnk_config_strobe_r_reg[0]_2\ => \rnk_config_strobe_r_reg[0]_2\, + \rnk_config_strobe_r_reg[0]_3\ => \rnk_config_strobe_r_reg[0]_3\, + rnk_config_valid_r => rnk_config_valid_r, + rnk_config_valid_r_lcl_reg => rnk_config_valid_r_lcl_reg, + row_hit_r => row_hit_r, + set_order_q => set_order_q, + tail_r => tail_r, + wait_for_maint_r_lcl_reg_0 => \^wait_for_maint_r_lcl_reg\, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0, + wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_1, + was_priority => was_priority, + was_wr => was_wr + ); +bank_state0: entity work.\ddr3_mig_7series_v4_2_bank_state__parameterized0\ + port map ( + CLK => CLK, + D(1 downto 0) => ras_timer_passed_ns(1 downto 0), + E(0) => \^e\(0), + Q(1 downto 0) => Q(2 downto 1), + SR(0) => SR(0), + act_this_rank_r(0) => act_this_rank_r(0), + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0), + act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg, + auto_pre_r_lcl_reg => auto_pre_r_lcl_reg, + auto_pre_r_lcl_reg_0 => q_has_priority_r_reg, + auto_pre_r_lcl_reg_1(0) => \^rb_hit_busy_r_reg\(0), + bm_end(0) => bm_end(1), + bm_end_r1 => bm_end_r1, + bm_end_r1_reg_0 => \^bm_end_r1_reg_0\, + bm_end_r1_reg_1 => \^bm_end_r1_reg\, + col_wait_r_reg_0 => \^col_wait_r\, + col_wait_r_reg_1 => col_wait_r_reg_0, + col_wait_r_reg_2 => \^q_entry_r_reg[1]\, + \compute_tail.tail_r_lcl_reg\ => bank_state0_n_18, + demand_act_priority_r => demand_act_priority_r, + demand_act_priority_r_reg_0 => \^wait_for_maint_r_lcl_reg\, + demand_priority_ns => demand_priority_ns, + demand_priority_r_0 => demand_priority_r_0, + demand_priority_r_reg_0 => demand_priority_r, + demand_priority_r_reg_1 => demand_priority_r_reg, + demand_priority_r_reg_2 => bank_state0_n_22, + demanded_prior_r_1 => demanded_prior_r_1, + demanded_prior_r_reg_0 => demanded_prior_r, + demanded_prior_r_reg_1 => demanded_prior_r_reg, + demanded_prior_r_reg_2 => demanded_prior_r_reg_0, + \grant_r[2]_i_3__1\(0) => \cmd_pipe_plus.mc_address_reg[10]\(0), + head_r(0) => \^head_r\(0), + ofs_rdy_r => ofs_rdy_r, + ofs_rdy_r0 => ofs_rdy_r0, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pre_bm_end_ns => pre_bm_end_ns, + pre_bm_end_r_reg(0) => pre_bm_end_r_reg_0(0), + pre_bm_end_r_reg_0 => \^auto_pre_r\, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_wait_r => pre_wait_r, + pre_wait_r_reg_0 => pre_wait_r_reg, + q_has_rd_0 => \^q_has_rd_0\, + ras_timer_zero_r => ras_timer_zero_r, + ras_timer_zero_r_reg_0 => bank_compare0_n_11, + rd_this_rank_r(0) => rd_this_rank_r(0), + \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r_lcl_reg\(0), + req_bank_rdy_ns => req_bank_rdy_ns, + req_wr_r(0) => req_wr_r(1), + \rstdiv0_sync_r1_reg_rep__12\ => bank_state0_n_8, + \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\, + start_wtp_timer0 => start_wtp_timer0, + \starve_limit_cntr_r_reg[0]_0\ => \starve_limit_cntr_r_reg[0]\, + tail_r => tail_r, + wr_this_rank_r(0) => wr_this_rank_r(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_cntrl__parameterized1\ is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rb_hit_busy_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + row_cmd_wr : out STD_LOGIC_VECTOR ( 0 to 0 ); + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + demand_act_priority_r : out STD_LOGIC; + demand_priority_r : out STD_LOGIC; + demanded_prior_r : out STD_LOGIC; + override_demand_r : out STD_LOGIC; + q_has_rd_1 : out STD_LOGIC; + wait_for_maint_r_lcl_reg : out STD_LOGIC; + head_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + ordered_r_lcl_reg : out STD_LOGIC; + auto_pre_r : out STD_LOGIC; + pre_bm_end_r_reg : out STD_LOGIC; + pre_bm_end_r_reg_0 : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg : out STD_LOGIC; + override_demand_r_reg : out STD_LOGIC; + bm_end_r1_reg : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + rd_wr_r_lcl_reg_0 : out STD_LOGIC; + col_wait_r_reg_0 : out STD_LOGIC; + act_wait_r_lcl_reg : out STD_LOGIC; + \maint_controller.maint_rdy\ : out STD_LOGIC; + pre_passing_open_bank_r_reg : out STD_LOGIC; + ras_timer_zero_r_reg : out STD_LOGIC; + act_wait_r_lcl_reg_0 : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + demand_priority_r_reg : out STD_LOGIC; + act_wait_r_lcl_reg_1 : out STD_LOGIC; + \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + CLK : in STD_LOGIC; + periodic_rd_insert : in STD_LOGIC; + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg_0 : in STD_LOGIC; + req_priority_r_reg : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + override_demand_ns : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ofs_rdy_r0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + head_r_lcl_reg : in STD_LOGIC; + head_r_lcl_reg_0 : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC; + col_wait_r_reg_1 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); + q_has_priority_r_reg : in STD_LOGIC; + pre_wait_r_reg : in STD_LOGIC; + \maint_controller.maint_hit_busies_r_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[2]_0\ : in STD_LOGIC; + q_has_rd_r_reg : in STD_LOGIC; + was_wr : in STD_LOGIC; + was_priority : in STD_LOGIC; + demanded_prior_r_0 : in STD_LOGIC; + demand_priority_r_1 : in STD_LOGIC; + demanded_prior_r_reg : in STD_LOGIC; + act_wait_r_lcl_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[1]\ : in STD_LOGIC; + \grant_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + granted_col_r_reg : in STD_LOGIC; + granted_col_r_reg_0 : in STD_LOGIC; + \grant_r[1]_i_2\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \q_entry_r_reg[1]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC; + \q_entry_r_reg[1]_0\ : in STD_LOGIC; + head_r_lcl_reg_1 : in STD_LOGIC; + \q_entry_r_reg[0]\ : in STD_LOGIC; + \maint_controller.maint_rdy_r1_reg\ : in STD_LOGIC; + \maint_controller.maint_rdy_r1_reg_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC; + rd_wr_r_lcl_reg_1 : in STD_LOGIC; + pre_bm_end_r_reg_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \starve_limit_cntr_r_reg[0]\ : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[40]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_address_reg[40]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rtp_timer_r_reg[0]\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \q_entry_r_reg[1]_1\ : in STD_LOGIC; + \q_entry_r_reg[0]_0\ : in STD_LOGIC; + \q_entry_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]\ : in STD_LOGIC; + \order_q_r_reg[0]\ : in STD_LOGIC; + \order_q_r_reg[0]_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_cntrl__parameterized1\ : entity is "mig_7series_v4_2_bank_cntrl"; +end \ddr3_mig_7series_v4_2_bank_cntrl__parameterized1\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_cntrl__parameterized1\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal act_wait_ns : STD_LOGIC; + signal \^auto_pre_r\ : STD_LOGIC; + signal bank_compare0_n_6 : STD_LOGIC; + signal bank_compare0_n_7 : STD_LOGIC; + signal bank_compare0_n_8 : STD_LOGIC; + signal bank_queue0_n_14 : STD_LOGIC; + signal bank_queue0_n_18 : STD_LOGIC; + signal bank_state0_n_21 : STD_LOGIC; + signal bank_state0_n_25 : STD_LOGIC; + signal bank_state0_n_8 : STD_LOGIC; + signal bm_end : STD_LOGIC_VECTOR ( 2 to 2 ); + signal bm_end_r1 : STD_LOGIC; + signal \^bm_end_r1_reg\ : STD_LOGIC; + signal \^bm_end_r1_reg_0\ : STD_LOGIC; + signal col_wait_r : STD_LOGIC; + signal demand_priority_ns : STD_LOGIC; + signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal idle_ns : STD_LOGIC_VECTOR ( 2 to 2 ); + signal \^idle_r_lcl_reg\ : STD_LOGIC; + signal \^ordered_r_lcl_reg\ : STD_LOGIC; + signal pass_open_bank_ns : STD_LOGIC; + signal pass_open_bank_r : STD_LOGIC; + signal pre_bm_end_ns : STD_LOGIC; + signal pre_bm_end_r : STD_LOGIC; + signal pre_passing_open_bank_ns : STD_LOGIC; + signal pre_wait_r : STD_LOGIC; + signal \^q_has_rd_1\ : STD_LOGIC; + signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ras_timer_zero_r : STD_LOGIC; + signal \^rb_hit_busy_r_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rd_wr_r_lcl_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal req_bank_rdy_ns : STD_LOGIC; + signal req_priority_r : STD_LOGIC; + signal \^req_row_r_lcl_reg[14]\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal \^req_wr_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^row_cmd_wr\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal row_hit_r : STD_LOGIC; + signal start_wtp_timer0 : STD_LOGIC; + signal tail_r : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg\ : STD_LOGIC; +begin + E(0) <= \^e\(0); + auto_pre_r <= \^auto_pre_r\; + bm_end_r1_reg <= \^bm_end_r1_reg\; + bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\; + head_r(0) <= \^head_r\(0); + idle_r_lcl_reg <= \^idle_r_lcl_reg\; + ordered_r_lcl_reg <= \^ordered_r_lcl_reg\; + q_has_rd_1 <= \^q_has_rd_1\; + rb_hit_busy_r_reg(0) <= \^rb_hit_busy_r_reg\(0); + rd_wr_r_lcl_reg(0) <= \^rd_wr_r_lcl_reg\(0); + \req_row_r_lcl_reg[14]\(14 downto 0) <= \^req_row_r_lcl_reg[14]\(14 downto 0); + req_wr_r(0) <= \^req_wr_r\(0); + row_cmd_wr(0) <= \^row_cmd_wr\(0); + wait_for_maint_r_lcl_reg <= \^wait_for_maint_r_lcl_reg\; +bank_compare0: entity work.ddr3_mig_7series_v4_2_bank_compare_0 + port map ( + CLK => CLK, + E(0) => idle_ns(2), + Q(0) => Q(1), + bm_end(0) => bm_end(2), + maint_req_r => maint_req_r, + ordered_r_lcl_reg => \compute_tail.tail_r_lcl_reg\, + ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\, + ordered_r_lcl_reg_1 => col_wait_r_reg_1, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pass_open_bank_r_lcl_reg => pre_wait_r_reg, + pass_open_bank_r_lcl_reg_0 => \compute_tail.tail_r_lcl_reg_1\, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg, + pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_lcl_reg_0, + pass_open_bank_r_lcl_reg_3 => pass_open_bank_r_lcl_reg_1, + pass_open_bank_r_lcl_reg_4 => \^wait_for_maint_r_lcl_reg\, + periodic_rd_insert => periodic_rd_insert, + pre_bm_end_r => pre_bm_end_r, + pre_wait_r => pre_wait_r, + rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\(0), + rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_0, + rd_wr_r_lcl_reg_0 => \^rd_wr_r_lcl_reg\(0), + rd_wr_r_lcl_reg_1 => bank_compare0_n_7, + rd_wr_r_lcl_reg_2 => bank_compare0_n_8, + rd_wr_r_lcl_reg_3 => \^idle_r_lcl_reg\, + rd_wr_r_lcl_reg_4 => rd_wr_r_lcl_reg_1, + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0), + \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0), + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + \req_data_buf_addr_r_reg[4]_1\ => \^e\(0), + \req_data_buf_addr_r_reg[4]_2\(4 downto 0) => \req_data_buf_addr_r_reg[4]_0\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(0), + req_priority_r => req_priority_r, + req_priority_r_reg_0 => req_priority_r_reg, + \req_row_r_lcl_reg[14]_0\(14 downto 0) => \^req_row_r_lcl_reg[14]\(14 downto 0), + req_wr_r_lcl0 => req_wr_r_lcl0, + req_wr_r_lcl_reg_0 => \^req_wr_r\(0), + row(14 downto 0) => row(14 downto 0), + row_hit_r => row_hit_r, + \rstdiv0_sync_r1_reg_rep__13\ => bank_compare0_n_6, + start_wtp_timer0 => start_wtp_timer0, + tail_r => tail_r + ); +bank_queue0: entity work.\ddr3_mig_7series_v4_2_bank_queue__parameterized1\ + port map ( + CLK => CLK, + D(0) => D(0), + E(0) => idle_ns(2), + Q(0) => Q(1), + SR(0) => SR(0), + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg => act_wait_r_lcl_reg_0, + act_wait_r_lcl_reg_0(0) => act_wait_r_lcl_reg_2(0), + act_wait_r_lcl_reg_1 => \^row_cmd_wr\(0), + auto_pre_r_lcl_reg_0 => \^auto_pre_r\, + auto_pre_r_lcl_reg_1 => bank_state0_n_21, + auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_0, + auto_pre_r_lcl_reg_3 => bank_compare0_n_6, + bm_end_r1 => bm_end_r1, + col_wait_r => col_wait_r, + col_wait_r_reg => col_wait_r_reg_0, + \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\, + \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\, + \compute_tail.tail_r_lcl_reg_2\ => \compute_tail.tail_r_lcl_reg_1\, + demand_priority_ns => demand_priority_ns, + demand_priority_r_reg => bank_state0_n_8, + demand_priority_r_reg_0 => bank_state0_n_25, + head_r_lcl_reg_0 => \^head_r\(0), + head_r_lcl_reg_1 => head_r_lcl_reg, + head_r_lcl_reg_2 => head_r_lcl_reg_0, + head_r_lcl_reg_3 => head_r_lcl_reg_1, + idle_r_lcl_reg_0 => \^e\(0), + idle_r_lcl_reg_1 => \^idle_r_lcl_reg\, + \maint_controller.maint_hit_busies_r_reg[2]\(0) => \maint_controller.maint_hit_busies_r_reg[2]\(0), + \maint_controller.maint_hit_busies_r_reg[2]_0\ => \maint_controller.maint_hit_busies_r_reg[2]_0\, + \maint_controller.maint_rdy\ => \maint_controller.maint_rdy\, + \maint_controller.maint_rdy_r1_reg\ => \maint_controller.maint_rdy_r1_reg\, + \maint_controller.maint_rdy_r1_reg_0\(2 downto 0) => \maint_controller.maint_rdy_r1_reg_0\(2 downto 0), + \order_q_r_reg[0]_0\ => \order_q_r_reg[0]\, + \order_q_r_reg[0]_1\ => \order_q_r_reg[0]_0\, + \order_q_r_reg[1]_0\ => bank_queue0_n_18, + \order_q_r_reg[1]_1\ => \order_q_r_reg[1]\, + ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg\, + ordered_r_lcl_reg_1 => bank_compare0_n_7, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pre_bm_end_ns => pre_bm_end_ns, + pre_bm_end_r => pre_bm_end_r, + pre_bm_end_r_reg_0 => pre_bm_end_r_reg, + pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg, + \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\, + \q_entry_r_reg[0]_1\ => \q_entry_r_reg[0]_0\, + \q_entry_r_reg[1]_0\ => bank_queue0_n_14, + \q_entry_r_reg[1]_1\(1 downto 0) => ras_timer_passed_ns(1 downto 0), + \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]\, + \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_0\, + \q_entry_r_reg[1]_4\ => \q_entry_r_reg[1]_1\, + \q_entry_r_reg[1]_5\(0) => \q_entry_r_reg[1]_2\(0), + q_has_priority_r_reg_0 => q_has_priority_r_reg, + q_has_priority_r_reg_1 => pre_wait_r_reg, + q_has_priority_r_reg_2 => \^rb_hit_busy_r_reg\(0), + q_has_priority_r_reg_3 => \^req_wr_r\(0), + q_has_rd_1 => \^q_has_rd_1\, + q_has_rd_r_reg_0 => q_has_rd_r_reg, + \ras_timer_r_reg[0]\ => \^bm_end_r1_reg_0\, + \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\, + \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\, + \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\, + \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\, + \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\, + \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\, + \ras_timer_r_reg[1]\ => \^bm_end_r1_reg\, + \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]\, + \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_0\, + \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_1\, + ras_timer_zero_r => ras_timer_zero_r, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(1 downto 0) => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(1 downto 0), + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => col_wait_r_reg_1, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + req_bank_rdy_ns => req_bank_rdy_ns, + req_bank_rdy_r_reg => \^rd_wr_r_lcl_reg\(0), + req_bank_rdy_r_reg_0 => req_bank_rdy_r_reg, + req_priority_r => req_priority_r, + \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\, + \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\, + row_hit_r => row_hit_r, + tail_r => tail_r, + wait_for_maint_r_lcl_reg_0 => \^wait_for_maint_r_lcl_reg\, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0, + wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_1, + was_priority => was_priority, + was_wr => was_wr + ); +bank_state0: entity work.\ddr3_mig_7series_v4_2_bank_state__parameterized1\ + port map ( + CLK => CLK, + D(1 downto 0) => ras_timer_passed_ns(1 downto 0), + E(0) => \^e\(0), + Q(1 downto 0) => Q(1 downto 0), + SR(0) => SR(0), + act_this_rank_r(0) => act_this_rank_r(0), + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg_0 => \^row_cmd_wr\(0), + act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg, + act_wait_r_lcl_reg_2 => act_wait_r_lcl_reg_1, + auto_pre_r_lcl_reg => auto_pre_r_lcl_reg, + auto_pre_r_lcl_reg_0 => q_has_priority_r_reg, + auto_pre_r_lcl_reg_1(0) => \^rb_hit_busy_r_reg\(0), + bm_end(0) => bm_end(2), + bm_end_r1 => bm_end_r1, + bm_end_r1_reg_0 => \^bm_end_r1_reg_0\, + bm_end_r1_reg_1 => \^bm_end_r1_reg\, + \cmd_pipe_plus.mc_address_reg[40]\(0) => \^req_row_r_lcl_reg[14]\(10), + \cmd_pipe_plus.mc_address_reg[40]_0\(0) => \cmd_pipe_plus.mc_address_reg[40]\(0), + \cmd_pipe_plus.mc_address_reg[40]_1\(0) => \cmd_pipe_plus.mc_address_reg[40]_0\(0), + col_wait_r => col_wait_r, + col_wait_r_reg_0 => col_wait_r_reg, + col_wait_r_reg_1 => col_wait_r_reg_1, + col_wait_r_reg_2 => bank_queue0_n_14, + \compute_tail.tail_r_lcl_reg\ => bank_state0_n_21, + demand_act_priority_r => demand_act_priority_r, + demand_act_priority_r_reg_0 => \^wait_for_maint_r_lcl_reg\, + demand_priority_ns => demand_priority_ns, + demand_priority_r_1 => demand_priority_r_1, + demand_priority_r_reg_0 => demand_priority_r, + demand_priority_r_reg_1 => demand_priority_r_reg, + demand_priority_r_reg_2 => bank_state0_n_25, + demanded_prior_r_0 => demanded_prior_r_0, + demanded_prior_r_reg_0 => demanded_prior_r, + demanded_prior_r_reg_1 => demanded_prior_r_reg, + \grant_r[1]_i_2_0\ => \grant_r[1]_i_2\, + \grant_r[1]_i_2_1\ => bank_queue0_n_18, + \grant_r[3]_i_5__2\(0) => act_wait_r_lcl_reg_2(0), + \grant_r_reg[1]\ => \grant_r_reg[1]\, + \grant_r_reg[1]_0\(0) => \grant_r_reg[1]_0\(0), + granted_col_r_reg => granted_col_r_reg, + granted_col_r_reg_0 => granted_col_r_reg_0, + head_r(0) => \^head_r\(0), + ofs_rdy_r0 => ofs_rdy_r0, + override_demand_ns => override_demand_ns, + override_demand_r => override_demand_r, + override_demand_r_reg_0 => override_demand_r_reg, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + \pre_4_1_1T_arb.granted_pre_r_reg\ => \pre_4_1_1T_arb.granted_pre_r_reg\, + pre_bm_end_ns => pre_bm_end_ns, + pre_bm_end_r_reg(1 downto 0) => pre_bm_end_r_reg_1(1 downto 0), + pre_bm_end_r_reg_0 => \^auto_pre_r\, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_wait_r => pre_wait_r, + pre_wait_r_reg_0 => pre_wait_r_reg, + q_has_rd_1 => \^q_has_rd_1\, + ras_timer_zero_r => ras_timer_zero_r, + ras_timer_zero_r_reg_0 => ras_timer_zero_r_reg, + ras_timer_zero_r_reg_1 => bank_compare0_n_8, + rd_this_rank_r(0) => rd_this_rank_r(0), + \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r_lcl_reg\(0), + rd_wr_r_lcl_reg => rd_wr_r_lcl_reg_0, + req_bank_rdy_ns => req_bank_rdy_ns, + req_wr_r(0) => \^req_wr_r\(0), + \rstdiv0_sync_r1_reg_rep__12\ => bank_state0_n_8, + \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\, + start_wtp_timer0 => start_wtp_timer0, + \starve_limit_cntr_r_reg[0]_0\ => \starve_limit_cntr_r_reg[0]\, + tail_r => tail_r, + wr_this_rank_r(0) => wr_this_rank_r(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_bank_cntrl__parameterized2\ is + port ( + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + req_periodic_rd_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_wr_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + rb_hit_busy_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + act_wait_r_lcl_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + act_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + wr_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + rd_this_rank_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + pre_bm_end_r_reg : out STD_LOGIC_VECTOR ( 0 to 0 ); + col_wait_r : out STD_LOGIC; + demand_act_priority_r : out STD_LOGIC; + demand_priority_r : out STD_LOGIC; + demanded_prior_r : out STD_LOGIC; + ofs_rdy_r : out STD_LOGIC; + q_has_rd_2 : out STD_LOGIC; + wait_for_maint_r_lcl_reg : out STD_LOGIC; + head_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + auto_pre_r : out STD_LOGIC; + \q_entry_r_reg[1]\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idle_r_lcl_reg : out STD_LOGIC; + pre_bm_end_r_reg_0 : out STD_LOGIC; + override_demand_r_reg : out STD_LOGIC; + bm_end_r1_reg : out STD_LOGIC; + bm_end_r1_reg_0 : out STD_LOGIC; + ordered_r_lcl_reg : out STD_LOGIC; + req_wr_r_lcl_reg : out STD_LOGIC; + ordered_r_lcl_reg_0 : out STD_LOGIC; + col_wait_r_reg : out STD_LOGIC; + \order_q_r_reg[1]\ : out STD_LOGIC; + col_wait_r_reg_0 : out STD_LOGIC; + act_wait_r_lcl_reg_0 : out STD_LOGIC; + pre_passing_open_bank_r_reg : out STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_ns\ : out STD_LOGIC; + act_wait_r_lcl_reg_1 : out STD_LOGIC; + auto_pre_r_lcl_reg : out STD_LOGIC; + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + demand_priority_r_reg : out STD_LOGIC; + demanded_prior_r_reg : out STD_LOGIC; + idle_r_lcl_reg_0 : out STD_LOGIC; + \req_data_buf_addr_r_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + CLK : in STD_LOGIC; + periodic_rd_insert : in STD_LOGIC; + req_bank_rdy_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg_0 : in STD_LOGIC; + req_priority_r_reg : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + ofs_rdy_r0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + head_r_lcl_reg : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_0\ : in STD_LOGIC; + \compute_tail.tail_r_lcl_reg_1\ : in STD_LOGIC; + col_wait_r_reg_1 : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); + rb_hit_busy_r : in STD_LOGIC_VECTOR ( 2 downto 0 ); + pre_wait_r_reg : in STD_LOGIC; + \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \maint_controller.maint_hit_busies_r_reg[3]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ : in STD_LOGIC; + q_has_rd_r_reg : in STD_LOGIC; + was_wr : in STD_LOGIC; + q_has_priority_r_reg : in STD_LOGIC; + was_priority : in STD_LOGIC; + override_demand_r : in STD_LOGIC; + demanded_prior_r_reg_0 : in STD_LOGIC; + demand_priority_r_0 : in STD_LOGIC; + ras_timer_zero_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \order_q_r_reg[1]_0\ : in STD_LOGIC; + ordered_r_lcl : in STD_LOGIC; + ordered_r : in STD_LOGIC; + \grant_r_reg[1]\ : in STD_LOGIC; + \grant_r_reg[1]_0\ : in STD_LOGIC; + \grant_r_reg[1]_1\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]\ : in STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : in STD_LOGIC; + req_bank_rdy_r_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_bank_rdy_r_reg_1 : in STD_LOGIC; + \ras_timer_r_reg[0]\ : in STD_LOGIC; + \ras_timer_r_reg[0]_0\ : in STD_LOGIC; + \ras_timer_r_reg[0]_1\ : in STD_LOGIC; + \ras_timer_r_reg[1]\ : in STD_LOGIC; + \ras_timer_r_reg[1]_0\ : in STD_LOGIC; + \ras_timer_r_reg[1]_1\ : in STD_LOGIC; + \ras_timer_r_reg[0]_2\ : in STD_LOGIC; + \ras_timer_r_reg[0]_3\ : in STD_LOGIC; + \ras_timer_r_reg[0]_4\ : in STD_LOGIC; + \q_entry_r_reg[1]_0\ : in STD_LOGIC; + head_r_lcl_reg_0 : in STD_LOGIC; + head_r_lcl_reg_1 : in STD_LOGIC; + bm_end : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ : in STD_LOGIC; + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ : in STD_LOGIC; + rd_wr_r_lcl_reg_0 : in STD_LOGIC; + auto_pre_r_lcl_reg_0 : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + maint_req_r : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + pass_open_bank_r_lcl_reg_0 : in STD_LOGIC; + pass_open_bank_r_lcl_reg_1 : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg_0\ : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg_1\ : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + demanded_prior_r_1 : in STD_LOGIC; + \q_entry_r[1]_i_2__0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r[1]_i_2__0_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \q_entry_r[1]_i_2__0_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \starve_limit_cntr_r_reg[0]\ : in STD_LOGIC; + \rtp_timer_r_reg[0]\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \q_entry_r_reg[1]_1\ : in STD_LOGIC; + \q_entry_r_reg[0]\ : in STD_LOGIC; + \q_entry_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_bank_cntrl__parameterized2\ : entity is "mig_7series_v4_2_bank_cntrl"; +end \ddr3_mig_7series_v4_2_bank_cntrl__parameterized2\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_bank_cntrl__parameterized2\ is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal act_wait_ns : STD_LOGIC; + signal \^act_wait_r_lcl_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^auto_pre_r\ : STD_LOGIC; + signal bank_compare0_n_12 : STD_LOGIC; + signal bank_compare0_n_13 : STD_LOGIC; + signal bank_compare0_n_16 : STD_LOGIC; + signal bank_queue0_n_8 : STD_LOGIC; + signal bank_state0_n_18 : STD_LOGIC; + signal bm_end_r1 : STD_LOGIC; + signal \^bm_end_r1_reg\ : STD_LOGIC; + signal \^bm_end_r1_reg_0\ : STD_LOGIC; + signal \^col_wait_r\ : STD_LOGIC; + signal \^head_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal idle_ns : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \^idle_r_lcl_reg\ : STD_LOGIC; + signal order_q_r : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^order_q_r_reg[1]\ : STD_LOGIC; + signal \^ordered_r_lcl_reg\ : STD_LOGIC; + signal \^ordered_r_lcl_reg_0\ : STD_LOGIC; + signal pass_open_bank_ns : STD_LOGIC; + signal pass_open_bank_r : STD_LOGIC; + signal pre_bm_end_ns : STD_LOGIC; + signal pre_bm_end_r : STD_LOGIC; + signal \^pre_bm_end_r_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal pre_passing_open_bank_ns : STD_LOGIC; + signal pre_wait_r : STD_LOGIC; + signal \^q_entry_r_reg[1]\ : STD_LOGIC; + signal q_has_priority : STD_LOGIC; + signal \^q_has_rd_2\ : STD_LOGIC; + signal ras_timer_passed_ns : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal ras_timer_zero_r : STD_LOGIC; + signal \^rb_hit_busy_r_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^rd_wr_r_lcl_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal req_bank_rdy_ns : STD_LOGIC; + signal req_priority_r : STD_LOGIC; + signal req_wr_r : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \^req_wr_r_lcl_reg\ : STD_LOGIC; + signal row_hit_r : STD_LOGIC; + signal set_order_q : STD_LOGIC; + signal start_wtp_timer0 : STD_LOGIC; + signal tail_r : STD_LOGIC; + signal \^wait_for_maint_r_lcl_reg\ : STD_LOGIC; +begin + E(0) <= \^e\(0); + act_wait_r_lcl_reg(0) <= \^act_wait_r_lcl_reg\(0); + auto_pre_r <= \^auto_pre_r\; + bm_end_r1_reg <= \^bm_end_r1_reg\; + bm_end_r1_reg_0 <= \^bm_end_r1_reg_0\; + col_wait_r <= \^col_wait_r\; + head_r(0) <= \^head_r\(0); + idle_r_lcl_reg <= \^idle_r_lcl_reg\; + \order_q_r_reg[1]\ <= \^order_q_r_reg[1]\; + ordered_r_lcl_reg <= \^ordered_r_lcl_reg\; + ordered_r_lcl_reg_0 <= \^ordered_r_lcl_reg_0\; + pre_bm_end_r_reg(0) <= \^pre_bm_end_r_reg\(0); + \q_entry_r_reg[1]\ <= \^q_entry_r_reg[1]\; + q_has_rd_2 <= \^q_has_rd_2\; + rb_hit_busy_r_reg(0) <= \^rb_hit_busy_r_reg\(0); + rd_wr_r_lcl_reg(0) <= \^rd_wr_r_lcl_reg\(0); + req_wr_r_lcl_reg <= \^req_wr_r_lcl_reg\; + wait_for_maint_r_lcl_reg <= \^wait_for_maint_r_lcl_reg\; +bank_compare0: entity work.ddr3_mig_7series_v4_2_bank_compare + port map ( + CLK => CLK, + E(0) => idle_ns(3), + Q(1 downto 0) => Q(2 downto 1), + col_wait_r_reg => col_wait_r_reg_0, + maint_req_r => maint_req_r, + order_q_r(1 downto 0) => order_q_r(1 downto 0), + \order_q_r_reg[1]\ => \^order_q_r_reg[1]\, + \order_q_r_reg[1]_0\ => \order_q_r_reg[1]_0\, + ordered_r => ordered_r, + ordered_r_lcl => ordered_r_lcl, + ordered_r_lcl_reg => \^ordered_r_lcl_reg\, + ordered_r_lcl_reg_0 => \^ordered_r_lcl_reg_0\, + ordered_r_lcl_reg_1 => bank_queue0_n_8, + ordered_r_lcl_reg_2 => col_wait_r_reg_1, + ordered_r_lcl_reg_3 => \compute_tail.tail_r_lcl_reg_0\, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pass_open_bank_r_lcl_reg => \compute_tail.tail_r_lcl_reg_1\, + pass_open_bank_r_lcl_reg_0 => pre_wait_r_reg, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg, + pass_open_bank_r_lcl_reg_2 => pass_open_bank_r_lcl_reg_0, + pass_open_bank_r_lcl_reg_3 => pass_open_bank_r_lcl_reg_1, + pass_open_bank_r_lcl_reg_4 => \^wait_for_maint_r_lcl_reg\, + periodic_rd_insert => periodic_rd_insert, + pre_bm_end_r => pre_bm_end_r, + pre_wait_r => pre_wait_r, + rb_hit_busy_r_reg_0 => \^rb_hit_busy_r_reg\(0), + rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_0, + rd_wr_r_lcl_reg_0 => \^rd_wr_r_lcl_reg\(0), + rd_wr_r_lcl_reg_1 => bank_compare0_n_12, + rd_wr_r_lcl_reg_2 => \^idle_r_lcl_reg\, + rd_wr_r_lcl_reg_3 => rd_wr_r_lcl_reg_0, + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0), + \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0), + req_bank_rdy_ns => req_bank_rdy_ns, + req_bank_rdy_r_reg => \^col_wait_r\, + req_bank_rdy_r_reg_0(0) => req_bank_rdy_r_reg_0(0), + req_bank_rdy_r_reg_1(0) => req_bank_rdy_r_reg(0), + req_bank_rdy_r_reg_2 => req_bank_rdy_r_reg_1, + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_col_r_reg[9]_1\(9 downto 0) => \req_col_r_reg[9]_0\(9 downto 0), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + \req_data_buf_addr_r_reg[4]_1\ => \^e\(0), + \req_data_buf_addr_r_reg[4]_2\(4 downto 0) => \req_data_buf_addr_r_reg[4]_0\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(0), + req_priority_r => req_priority_r, + req_priority_r_reg_0 => req_priority_r_reg, + \req_row_r_lcl_reg[14]_0\(14 downto 0) => \req_row_r_lcl_reg[14]\(14 downto 0), + req_wr_r(0) => req_wr_r(3), + req_wr_r_lcl0 => req_wr_r_lcl0, + req_wr_r_lcl_reg_0 => \^req_wr_r_lcl_reg\, + \rnk_config_strobe_r_reg[0]\ => \rnk_config_strobe_r_reg[0]\, + \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]_0\, + row(14 downto 0) => row(14 downto 0), + row_hit_r => row_hit_r, + \rstdiv0_sync_r1_reg_rep__12\ => bank_compare0_n_13, + \rstdiv0_sync_r1_reg_rep__13\ => bank_compare0_n_16, + set_order_q => set_order_q, + start_wtp_timer0 => start_wtp_timer0, + tail_r => tail_r + ); +bank_queue0: entity work.\ddr3_mig_7series_v4_2_bank_queue__parameterized2\ + port map ( + CLK => CLK, + D(0) => D(0), + E(0) => idle_ns(3), + Q(0) => Q(2), + SR(0) => SR(0), + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg => act_wait_r_lcl_reg_1, + act_wait_r_lcl_reg_0(0) => ras_timer_zero_r_reg(0), + act_wait_r_lcl_reg_1 => \^act_wait_r_lcl_reg\(0), + auto_pre_r_lcl_reg_0 => \^auto_pre_r\, + auto_pre_r_lcl_reg_1 => bank_state0_n_18, + auto_pre_r_lcl_reg_2 => auto_pre_r_lcl_reg_0, + auto_pre_r_lcl_reg_3 => bank_compare0_n_16, + bm_end(0) => bm_end(0), + bm_end_r1 => bm_end_r1, + bm_end_r1_reg => \^rd_wr_r_lcl_reg\(0), + col_wait_r_reg => col_wait_r_reg, + \compute_tail.tail_r_lcl_reg_0\ => \compute_tail.tail_r_lcl_reg\, + \compute_tail.tail_r_lcl_reg_1\ => \compute_tail.tail_r_lcl_reg_0\, + \compute_tail.tail_r_lcl_reg_2\ => \compute_tail.tail_r_lcl_reg_1\, + \grant_r_reg[1]\ => \^col_wait_r\, + \grant_r_reg[1]_0\ => \grant_r_reg[1]\, + \grant_r_reg[1]_1\ => \grant_r_reg[1]_0\, + \grant_r_reg[1]_2\ => \grant_r_reg[1]_1\, + head_r_lcl_reg_0 => \^head_r\(0), + head_r_lcl_reg_1 => head_r_lcl_reg, + head_r_lcl_reg_2 => head_r_lcl_reg_0, + head_r_lcl_reg_3 => head_r_lcl_reg_1, + idle_r_lcl_reg_0 => \^e\(0), + idle_r_lcl_reg_1 => \^idle_r_lcl_reg\, + idle_r_lcl_reg_2 => idle_r_lcl_reg_0, + \maint_controller.maint_hit_busies_r_reg[3]\(0) => \maint_controller.maint_hit_busies_r_reg[3]\(0), + \maint_controller.maint_hit_busies_r_reg[3]_0\ => \maint_controller.maint_hit_busies_r_reg[3]_0\, + order_q_r(1 downto 0) => order_q_r(1 downto 0), + \order_q_r_reg[0]_0\ => \^req_wr_r_lcl_reg\, + \order_q_r_reg[0]_1\ => \^ordered_r_lcl_reg\, + \order_q_r_reg[1]_0\ => \^ordered_r_lcl_reg_0\, + ordered_r_lcl_reg_0 => bank_queue0_n_8, + ordered_r_lcl_reg_1 => bank_compare0_n_13, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + pre_bm_end_ns => pre_bm_end_ns, + pre_bm_end_r => pre_bm_end_r, + pre_bm_end_r_reg_0 => \^pre_bm_end_r_reg\(0), + pre_bm_end_r_reg_1 => pre_bm_end_r_reg_0, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_passing_open_bank_r_reg_0 => pre_passing_open_bank_r_reg, + \q_entry_r[1]_i_2__0\(0) => \q_entry_r[1]_i_2__0\(0), + \q_entry_r[1]_i_2__0_0\(0) => \q_entry_r[1]_i_2__0_0\(0), + \q_entry_r[1]_i_2__0_1\(0) => \q_entry_r[1]_i_2__0_1\(0), + \q_entry_r_reg[0]_0\ => \q_entry_r_reg[0]\, + \q_entry_r_reg[0]_1\(0) => \q_entry_r_reg[0]_0\(0), + \q_entry_r_reg[1]_0\ => \^q_entry_r_reg[1]\, + \q_entry_r_reg[1]_1\(1 downto 0) => ras_timer_passed_ns(1 downto 0), + \q_entry_r_reg[1]_2\ => \q_entry_r_reg[1]_0\, + \q_entry_r_reg[1]_3\ => \q_entry_r_reg[1]_1\, + q_has_priority => q_has_priority, + q_has_priority_r_reg_0 => \^rb_hit_busy_r_reg\(0), + q_has_priority_r_reg_1 => pre_wait_r_reg, + q_has_priority_r_reg_2 => q_has_priority_r_reg, + q_has_rd_2 => \^q_has_rd_2\, + q_has_rd_r_reg_0 => q_has_rd_r_reg, + \ras_timer_r_reg[0]\ => \^bm_end_r1_reg_0\, + \ras_timer_r_reg[0]_0\ => \ras_timer_r_reg[0]\, + \ras_timer_r_reg[0]_1\ => \ras_timer_r_reg[0]_0\, + \ras_timer_r_reg[0]_2\ => \ras_timer_r_reg[0]_1\, + \ras_timer_r_reg[0]_3\ => \ras_timer_r_reg[0]_2\, + \ras_timer_r_reg[0]_4\ => \ras_timer_r_reg[0]_3\, + \ras_timer_r_reg[0]_5\ => \ras_timer_r_reg[0]_4\, + \ras_timer_r_reg[1]\ => \^bm_end_r1_reg\, + \ras_timer_r_reg[1]_0\ => \ras_timer_r_reg[1]\, + \ras_timer_r_reg[1]_1\ => \ras_timer_r_reg[1]_0\, + \ras_timer_r_reg[1]_2\ => \ras_timer_r_reg[1]_1\, + ras_timer_zero_r => ras_timer_zero_r, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0\ => col_wait_r_reg_1, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1\ => \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\, + rb_hit_busy_r(2 downto 0) => rb_hit_busy_r(2 downto 0), + req_wr_r(0) => req_wr_r(3), + row_hit_r => row_hit_r, + set_order_q => set_order_q, + tail_r => tail_r, + wait_for_maint_r_lcl_reg_0 => \^wait_for_maint_r_lcl_reg\, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0, + wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_1, + was_priority => was_priority, + was_wr => was_wr + ); +bank_state0: entity work.\ddr3_mig_7series_v4_2_bank_state__parameterized2\ + port map ( + CLK => CLK, + D(1 downto 0) => ras_timer_passed_ns(1 downto 0), + E(0) => \^e\(0), + Q(1) => Q(2), + Q(0) => Q(0), + SR(0) => SR(0), + act_this_rank_r(0) => act_this_rank_r(0), + act_wait_ns => act_wait_ns, + act_wait_r_lcl_reg_0 => \^act_wait_r_lcl_reg\(0), + act_wait_r_lcl_reg_1 => act_wait_r_lcl_reg_0, + auto_pre_r_lcl_reg => auto_pre_r_lcl_reg, + auto_pre_r_lcl_reg_0 => q_has_priority_r_reg, + auto_pre_r_lcl_reg_1(0) => \^rb_hit_busy_r_reg\(0), + bm_end_r1 => bm_end_r1, + bm_end_r1_reg_0 => \^bm_end_r1_reg_0\, + bm_end_r1_reg_1 => \^bm_end_r1_reg\, + bm_end_r1_reg_2(0) => \^pre_bm_end_r_reg\(0), + col_wait_r_reg_0 => \^col_wait_r\, + col_wait_r_reg_1 => col_wait_r_reg_1, + col_wait_r_reg_2 => \^q_entry_r_reg[1]\, + \compute_tail.tail_r_lcl_reg\ => bank_state0_n_18, + demand_act_priority_r => demand_act_priority_r, + demand_act_priority_r_reg_0 => \^wait_for_maint_r_lcl_reg\, + demand_priority_r_0 => demand_priority_r_0, + demand_priority_r_reg_0 => demand_priority_r, + demand_priority_r_reg_1 => demand_priority_r_reg, + demand_priority_r_reg_2 => \^idle_r_lcl_reg\, + demand_priority_r_reg_3 => \^order_q_r_reg[1]\, + demanded_prior_r_1 => demanded_prior_r_1, + demanded_prior_r_reg_0 => demanded_prior_r, + demanded_prior_r_reg_1 => demanded_prior_r_reg, + demanded_prior_r_reg_2 => demanded_prior_r_reg_0, + head_r(0) => \^head_r\(0), + ofs_rdy_r => ofs_rdy_r, + ofs_rdy_r0 => ofs_rdy_r0, + override_demand_r => override_demand_r, + override_demand_r_reg => override_demand_r_reg, + pass_open_bank_ns => pass_open_bank_ns, + pass_open_bank_r => pass_open_bank_r, + \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\, + \pre_4_1_1T_arb.granted_pre_r_reg\(0) => \pre_4_1_1T_arb.granted_pre_r_reg\(0), + \pre_4_1_1T_arb.granted_pre_r_reg_0\ => \^auto_pre_r\, + \pre_4_1_1T_arb.granted_pre_r_reg_1\ => \pre_4_1_1T_arb.granted_pre_r_reg_0\, + \pre_4_1_1T_arb.granted_pre_r_reg_2\ => \pre_4_1_1T_arb.granted_pre_r_reg_1\, + pre_bm_end_ns => pre_bm_end_ns, + pre_passing_open_bank_ns => pre_passing_open_bank_ns, + pre_wait_r => pre_wait_r, + pre_wait_r_reg_0 => pre_wait_r_reg, + q_has_priority => q_has_priority, + q_has_rd_2 => \^q_has_rd_2\, + ras_timer_zero_r => ras_timer_zero_r, + ras_timer_zero_r_reg_0 => bank_compare0_n_12, + ras_timer_zero_r_reg_1(0) => ras_timer_zero_r_reg(0), + rd_this_rank_r(0) => rd_this_rank_r(0), + \rd_this_rank_r_reg[0]_0\ => \^rd_wr_r_lcl_reg\(0), + req_bank_rdy_ns => req_bank_rdy_ns, + req_priority_r => req_priority_r, + req_wr_r(0) => req_wr_r(3), + \rtp_timer_r_reg[0]_0\ => \rtp_timer_r_reg[0]\, + start_wtp_timer0 => start_wtp_timer0, + \starve_limit_cntr_r_reg[0]_0\ => \starve_limit_cntr_r_reg[0]\, + tail_r => tail_r, + wr_this_rank_r(0) => wr_this_rank_r(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_byte_lane is + port ( + ofifo_rst : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + COUNTERREADVAL : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \my_empty_reg[1]\ : out STD_LOGIC; + phy_mc_cmd_full : out STD_LOGIC; + mem_dq_out : out STD_LOGIC_VECTOR ( 10 downto 0 ); + \rd_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + ofifo_rst_reg_0 : in STD_LOGIC; + CLK : in STD_LOGIC; + OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 ); + \po_counter_read_val_reg[8]\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_0\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_1\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_2\ : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + calib_cmd_wren : in STD_LOGIC; + B_of_full : in STD_LOGIC; + mux_cmd_wren : in STD_LOGIC; + mc_address : in STD_LOGIC_VECTOR ( 5 downto 0 ); + mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + out_fifo_0 : in STD_LOGIC; + phy_dout : in STD_LOGIC_VECTOR ( 39 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_byte_lane : entity is "mig_7series_v4_2_ddr_byte_lane"; +end ddr3_mig_7series_v4_2_ddr_byte_lane; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_byte_lane is + signal A_of_full : STD_LOGIC; + signal ddr_ck_out_q : STD_LOGIC_VECTOR ( 0 to 0 ); + signal of_d0 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_d6 : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal of_d9 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ : STD_LOGIC; + signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^ofifo_rst\ : STD_LOGIC; + signal oserdes_clk : STD_LOGIC; + signal oserdes_clk_delayed : STD_LOGIC; + signal oserdes_clkdiv : STD_LOGIC; + signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal out_fifo_n_0 : STD_LOGIC; + signal out_fifo_n_1 : STD_LOGIC; + signal out_fifo_n_2 : STD_LOGIC; + signal phaser_out_n_0 : STD_LOGIC; + signal phaser_out_n_1 : STD_LOGIC; + signal po_oserdes_rst : STD_LOGIC; + signal po_rd_enable : STD_LOGIC; + signal \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\ : STD_LOGIC; + signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "PRIMITIVE"; + attribute \__SRVAL\ : string; + attribute \__SRVAL\ of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\ : label is "FALSE"; + attribute BOX_TYPE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "DONT_CARE"; + attribute XILINX_LEGACY_PRIM : string; + attribute XILINX_LEGACY_PRIM of \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\ : label is "OBUFDS"; + attribute BOX_TYPE of out_fifo : label is "PRIMITIVE"; + attribute BOX_TYPE of phaser_out : label is "PRIMITIVE"; +begin + ofifo_rst <= \^ofifo_rst\; +ddr_byte_group_io: entity work.ddr3_mig_7series_v4_2_ddr_byte_group_io + port map ( + mem_dq_out(10 downto 0) => mem_dq_out(10 downto 0), + oserdes_clk => oserdes_clk, + oserdes_clkdiv => oserdes_clkdiv, + oserdes_dq(43 downto 40) => of_q6(7 downto 4), + oserdes_dq(39 downto 36) => of_q9(3 downto 0), + oserdes_dq(35 downto 32) => of_q8(3 downto 0), + oserdes_dq(31 downto 28) => of_q7(3 downto 0), + oserdes_dq(27 downto 24) => of_q6(3 downto 0), + oserdes_dq(23 downto 20) => of_q5(3 downto 0), + oserdes_dq(19 downto 16) => of_q4(3 downto 0), + oserdes_dq(15 downto 12) => of_q3(3 downto 0), + oserdes_dq(11 downto 8) => of_q2(3 downto 0), + oserdes_dq(7 downto 4) => of_q1(3 downto 0), + oserdes_dq(3 downto 0) => of_q0(3 downto 0), + po_oserdes_rst => po_oserdes_rst + ); +\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck\: unisim.vcomponents.ODDR + generic map( + DDR_CLK_EDGE => "SAME_EDGE", + INIT => '0', + IS_C_INVERTED => '0', + IS_D1_INVERTED => '0', + IS_D2_INVERTED => '0', + SRTYPE => "SYNC" + ) + port map ( + C => oserdes_clk, + CE => '1', + D1 => '0', + D2 => '1', + Q => ddr_ck_out_q(0), + R => '0', + S => \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED\ + ); +\ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf\: unisim.vcomponents.OBUFDS + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => ddr_ck_out_q(0), + O => ddr_ck_out(0), + OB => ddr_ck_out(1) + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10\ + port map ( + A_of_full => A_of_full, + CLK => CLK, + D0(3 downto 0) => of_d0(3 downto 0), + D6(3 downto 0) => of_d6(7 downto 4), + D9(3 downto 0) => of_d9(3 downto 0), + SR(0) => \^ofifo_rst\, + calib_cmd_wren => calib_cmd_wren, + mc_address(5 downto 0) => mc_address(5 downto 0), + mc_cas_n(0) => mc_cas_n(0), + mux_cmd_wren => mux_cmd_wren, + \my_empty_reg[1]_0\ => \my_empty_reg[1]\, + \my_empty_reg[1]_1\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\, + out_fifo => out_fifo_0, + phy_dout(39 downto 0) => phy_dout(39 downto 0), + \rd_ptr_reg[3]_0\(31 downto 0) => \rd_ptr_reg[3]\(31 downto 0), + \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\ + ); +ofifo_rst_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => ofifo_rst_reg_0, + Q => \^ofifo_rst\, + R => '0' + ); +out_fifo: unisim.vcomponents.OUT_FIFO + generic map( + ALMOST_EMPTY_VALUE => 1, + ALMOST_FULL_VALUE => 1, + ARRAY_MODE => "ARRAY_MODE_4_X_4", + OUTPUT_DISABLE => "FALSE", + SYNCHRONOUS_MODE => "FALSE" + ) + port map ( + ALMOSTEMPTY => out_fifo_n_0, + ALMOSTFULL => out_fifo_n_1, + D0(7 downto 4) => B"0000", + D0(3 downto 0) => of_d0(3 downto 0), + D1(7 downto 4) => B"0000", + D1(3 downto 0) => \my_empty_reg[7]\(3 downto 0), + D2(7 downto 4) => B"0000", + D2(3 downto 0) => \my_empty_reg[7]_0\(3 downto 0), + D3(7 downto 4) => B"0000", + D3(3 downto 0) => \my_empty_reg[7]_1\(3 downto 0), + D4(7 downto 4) => B"0000", + D4(3 downto 0) => \my_empty_reg[7]_2\(3 downto 0), + D5(7 downto 4) => B"0000", + D5(3 downto 0) => \my_empty_reg[7]_3\(3 downto 0), + D6(7 downto 4) => of_d6(7 downto 4), + D6(3 downto 0) => \my_empty_reg[7]_4\(3 downto 0), + D7(7 downto 4) => B"0000", + D7(3 downto 0) => \my_empty_reg[7]_5\(3 downto 0), + D8(7 downto 4) => B"0000", + D8(3 downto 0) => \my_empty_reg[7]_6\(3 downto 0), + D9(7 downto 4) => B"0000", + D9(3 downto 0) => of_d9(3 downto 0), + EMPTY => out_fifo_n_2, + FULL => A_of_full, + Q0(3 downto 0) => of_q0(3 downto 0), + Q1(3 downto 0) => of_q1(3 downto 0), + Q2(3 downto 0) => of_q2(3 downto 0), + Q3(3 downto 0) => of_q3(3 downto 0), + Q4(3 downto 0) => of_q4(3 downto 0), + Q5(7 downto 0) => of_q5(7 downto 0), + Q6(7 downto 0) => of_q6(7 downto 0), + Q7(3 downto 0) => of_q7(3 downto 0), + Q8(3 downto 0) => of_q8(3 downto 0), + Q9(3 downto 0) => of_q9(3 downto 0), + RDCLK => oserdes_clkdiv, + RDEN => po_rd_enable, + RESET => \^ofifo_rst\, + WRCLK => CLK, + WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13\ + ); +phaser_out: unisim.vcomponents.PHASER_OUT_PHY + generic map( + CLKOUT_DIV => 4, + COARSE_BYPASS => "FALSE", + COARSE_DELAY => 0, + DATA_CTL_N => "FALSE", + DATA_RD_CYCLES => "FALSE", + FINE_DELAY => 60, + IS_RST_INVERTED => '0', + MEMREFCLK_PERIOD => 3.000000, + OCLKDELAY_INV => "FALSE", + OCLK_DELAY => 0, + OUTPUT_CLK_SRC => "DELAYED_REF", + PHASEREFCLK_PERIOD => 1.000000, + PO => B"111", + REFCLK_PERIOD => 1.500000, + SYNC_IN_DIV_RST => "TRUE" + ) + port map ( + BURSTPENDINGPHY => OUTBURSTPENDING(0), + COARSEENABLE => \po_counter_read_val_reg[8]\, + COARSEINC => \po_counter_read_val_reg[8]\, + COARSEOVERFLOW => phaser_out_n_0, + COUNTERLOADEN => '0', + COUNTERLOADVAL(8 downto 0) => B"000000000", + COUNTERREADEN => \po_counter_read_val_reg[8]_0\, + COUNTERREADVAL(8 downto 0) => COUNTERREADVAL(8 downto 0), + CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0), + DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0), + DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0), + ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0), + FINEENABLE => \po_counter_read_val_reg[8]_1\, + FINEINC => \po_counter_read_val_reg[8]_2\, + FINEOVERFLOW => phaser_out_n_1, + FREQREFCLK => freq_refclk, + MEMREFCLK => mem_refclk, + OCLK => oserdes_clk, + OCLKDELAYED => oserdes_clk_delayed, + OCLKDIV => oserdes_clkdiv, + OSERDESRST => po_oserdes_rst, + PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED, + RDENABLE => po_rd_enable, + RST => ofifo_rst_reg_0, + SELFINEOCLKDELAY => '0', + SYNCIN => sync_pulse, + SYSCLK => CLK + ); +phy_mc_cmd_full_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => A_of_full, + I1 => B_of_full, + O => phy_mc_cmd_full + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized0\ is + port ( + B_of_full : out STD_LOGIC; + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + \my_empty_reg[1]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + mem_dq_out : out STD_LOGIC_VECTOR ( 11 downto 0 ); + D : out STD_LOGIC_VECTOR ( 8 downto 0 ); + OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 ); + \po_counter_read_val_reg[8]\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_0\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_1\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_2\ : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + \po_counter_read_val_reg[8]_3\ : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + CLK : in STD_LOGIC; + PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + ofifo_rst : in STD_LOGIC; + \rd_ptr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + calib_cmd_wren : in STD_LOGIC; + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mux_cmd_wren : in STD_LOGIC; + COUNTERREADVAL : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \po_counter_read_val_reg[8]_4\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \po_counter_read_val_reg[8]_5\ : in STD_LOGIC_VECTOR ( 8 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized0\ : entity is "mig_7series_v4_2_ddr_byte_lane"; +end \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized0\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized0\ is + signal B_of_a_full : STD_LOGIC; + signal \^b_of_full\ : STD_LOGIC; + signal B_po_coarse_overflow : STD_LOGIC; + signal B_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal B_po_fine_overflow : STD_LOGIC; + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ : STD_LOGIC; + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\ : STD_LOGIC; + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\ : STD_LOGIC; + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\ : STD_LOGIC; + signal of_q0 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q3 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q4 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q5 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal of_q6 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal of_q7 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q8 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal of_q9 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal oserdes_clk : STD_LOGIC; + signal oserdes_clk_delayed : STD_LOGIC; + signal oserdes_clkdiv : STD_LOGIC; + signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal out_fifo_n_0 : STD_LOGIC; + signal out_fifo_n_2 : STD_LOGIC; + signal po_oserdes_rst : STD_LOGIC; + signal po_rd_enable : STD_LOGIC; + signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of out_fifo : label is "PRIMITIVE"; + attribute BOX_TYPE of phaser_out : label is "PRIMITIVE"; +begin + B_of_full <= \^b_of_full\; +ddr_byte_group_io: entity work.\ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized0\ + port map ( + mem_dq_out(11 downto 0) => mem_dq_out(11 downto 0), + oserdes_clk => oserdes_clk, + oserdes_clkdiv => oserdes_clkdiv, + oserdes_dq(47 downto 44) => of_q6(7 downto 4), + oserdes_dq(43 downto 40) => of_q5(7 downto 4), + oserdes_dq(39 downto 36) => of_q9(3 downto 0), + oserdes_dq(35 downto 32) => of_q8(3 downto 0), + oserdes_dq(31 downto 28) => of_q7(3 downto 0), + oserdes_dq(27 downto 24) => of_q6(3 downto 0), + oserdes_dq(23 downto 20) => of_q5(3 downto 0), + oserdes_dq(19 downto 16) => of_q4(3 downto 0), + oserdes_dq(15 downto 12) => of_q3(3 downto 0), + oserdes_dq(11 downto 8) => of_q2(3 downto 0), + oserdes_dq(7 downto 4) => of_q1(3 downto 0), + oserdes_dq(3 downto 0) => of_q0(3 downto 0), + po_oserdes_rst => po_oserdes_rst + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_9\ + port map ( + CLK => CLK, + D2(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\, + D6(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\, + D9(0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\, + Q(3 downto 0) => Q(3 downto 0), + calib_cmd_wren => calib_cmd_wren, + mem_out(2 downto 0) => mem_out(2 downto 0), + mux_cmd_wren => mux_cmd_wren, + \my_empty_reg[1]_0\ => \my_empty_reg[1]\, + \my_empty_reg[1]_1\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\, + ofifo_rst => ofifo_rst, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_1\ => \^b_of_full\, + wr_en_3 => wr_en_3, + \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\ + ); +out_fifo: unisim.vcomponents.OUT_FIFO + generic map( + ALMOST_EMPTY_VALUE => 1, + ALMOST_FULL_VALUE => 1, + ARRAY_MODE => "ARRAY_MODE_4_X_4", + OUTPUT_DISABLE => "FALSE", + SYNCHRONOUS_MODE => "FALSE" + ) + port map ( + ALMOSTEMPTY => out_fifo_n_0, + ALMOSTFULL => B_of_a_full, + D0(7 downto 4) => B"0000", + D0(3 downto 0) => \rd_ptr_reg[3]_0\(3 downto 0), + D1(7 downto 4) => B"0000", + D1(3 downto 0) => \rd_ptr_reg[3]_1\(3 downto 0), + D2(7 downto 4) => B"0000", + D2(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7\, + D2(2 downto 0) => \rd_ptr_reg[3]_2\(2 downto 0), + D3(7 downto 4) => B"0000", + D3(3 downto 0) => \rd_ptr_reg[3]_3\(3 downto 0), + D4(7 downto 4) => B"0000", + D4(3 downto 0) => \rd_ptr_reg[3]_4\(3 downto 0), + D5(7 downto 0) => \rd_ptr_reg[3]_5\(7 downto 0), + D6(7 downto 4) => \rd_ptr_reg[3]_6\(6 downto 3), + D6(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8\, + D6(2 downto 0) => \rd_ptr_reg[3]_6\(2 downto 0), + D7(7 downto 4) => B"0000", + D7(3 downto 0) => \rd_ptr_reg[3]_7\(3 downto 0), + D8(7 downto 4) => B"0000", + D8(3 downto 0) => \rd_ptr_reg[3]_8\(3 downto 0), + D9(7 downto 4) => B"0000", + D9(3) => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9\, + D9(2 downto 0) => \rd_ptr_reg[3]_9\(2 downto 0), + EMPTY => out_fifo_n_2, + FULL => \^b_of_full\, + Q0(3 downto 0) => of_q0(3 downto 0), + Q1(3 downto 0) => of_q1(3 downto 0), + Q2(3 downto 0) => of_q2(3 downto 0), + Q3(3 downto 0) => of_q3(3 downto 0), + Q4(3 downto 0) => of_q4(3 downto 0), + Q5(7 downto 0) => of_q5(7 downto 0), + Q6(7 downto 0) => of_q6(7 downto 0), + Q7(3 downto 0) => of_q7(3 downto 0), + Q8(3 downto 0) => of_q8(3 downto 0), + Q9(3 downto 0) => of_q9(3 downto 0), + RDCLK => oserdes_clkdiv, + RDEN => po_rd_enable, + RESET => ofifo_rst, + WRCLK => CLK, + WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6\ + ); +phaser_out: unisim.vcomponents.PHASER_OUT_PHY + generic map( + CLKOUT_DIV => 4, + COARSE_BYPASS => "FALSE", + COARSE_DELAY => 0, + DATA_CTL_N => "FALSE", + DATA_RD_CYCLES => "FALSE", + FINE_DELAY => 60, + IS_RST_INVERTED => '0', + MEMREFCLK_PERIOD => 3.000000, + OCLKDELAY_INV => "FALSE", + OCLK_DELAY => 0, + OUTPUT_CLK_SRC => "DELAYED_REF", + PHASEREFCLK_PERIOD => 1.000000, + PO => B"111", + REFCLK_PERIOD => 1.500000, + SYNC_IN_DIV_RST => "TRUE" + ) + port map ( + BURSTPENDINGPHY => OUTBURSTPENDING(0), + COARSEENABLE => \po_counter_read_val_reg[8]\, + COARSEINC => \po_counter_read_val_reg[8]\, + COARSEOVERFLOW => B_po_coarse_overflow, + COUNTERLOADEN => '0', + COUNTERLOADVAL(8 downto 0) => B"000000000", + COUNTERREADEN => \po_counter_read_val_reg[8]_0\, + COUNTERREADVAL(8 downto 0) => B_po_counter_read_val(8 downto 0), + CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0), + DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0), + DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0), + ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0), + FINEENABLE => \po_counter_read_val_reg[8]_1\, + FINEINC => \po_counter_read_val_reg[8]_2\, + FINEOVERFLOW => B_po_fine_overflow, + FREQREFCLK => freq_refclk, + MEMREFCLK => mem_refclk, + OCLK => oserdes_clk, + OCLKDELAYED => oserdes_clk_delayed, + OCLKDIV => oserdes_clkdiv, + OSERDESRST => po_oserdes_rst, + PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED, + RDENABLE => po_rd_enable, + RST => \po_counter_read_val_reg[8]_3\, + SELFINEOCLKDELAY => '0', + SYNCIN => sync_pulse, + SYSCLK => CLK + ); +\po_counter_read_val[0]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(0), + I1 => COUNTERREADVAL(0), + I2 => \po_counter_read_val_reg[8]_4\(0), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(0), + O => D(0) + ); +\po_counter_read_val[1]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(1), + I1 => COUNTERREADVAL(1), + I2 => \po_counter_read_val_reg[8]_4\(1), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(1), + O => D(1) + ); +\po_counter_read_val[2]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(2), + I1 => COUNTERREADVAL(2), + I2 => \po_counter_read_val_reg[8]_4\(2), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(2), + O => D(2) + ); +\po_counter_read_val[3]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(3), + I1 => COUNTERREADVAL(3), + I2 => \po_counter_read_val_reg[8]_4\(3), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(3), + O => D(3) + ); +\po_counter_read_val[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(4), + I1 => COUNTERREADVAL(4), + I2 => \po_counter_read_val_reg[8]_4\(4), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(4), + O => D(4) + ); +\po_counter_read_val[5]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(5), + I1 => COUNTERREADVAL(5), + I2 => \po_counter_read_val_reg[8]_4\(5), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(5), + O => D(5) + ); +\po_counter_read_val[6]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(6), + I1 => COUNTERREADVAL(6), + I2 => \po_counter_read_val_reg[8]_4\(6), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(6), + O => D(6) + ); +\po_counter_read_val[7]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(7), + I1 => COUNTERREADVAL(7), + I2 => \po_counter_read_val_reg[8]_4\(7), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(7), + O => D(7) + ); +\po_counter_read_val[8]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"F0AAFFCCF0AA00CC" + ) + port map ( + I0 => B_po_counter_read_val(8), + I1 => COUNTERREADVAL(8), + I2 => \po_counter_read_val_reg[8]_4\(8), + I3 => calib_sel(1), + I4 => calib_sel(0), + I5 => \po_counter_read_val_reg[8]_5\(8), + O => D(8) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized1\ is + port ( + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg : out STD_LOGIC; + mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); + mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 ); + out_dqs_0 : out STD_LOGIC; + ts_dqs_0 : out STD_LOGIC; + pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 ); + A_rst_primitives_reg_0 : out STD_LOGIC_VECTOR ( 8 downto 0 ); + if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + idelay_ld_rst : out STD_LOGIC; + init_complete_r1_timing_reg : out STD_LOGIC; + \my_empty_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[1]\ : out STD_LOGIC; + phy_rddata_en : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 73 downto 0 ); + in0 : out STD_LOGIC; + phy_mc_data_full : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[0]\ : out STD_LOGIC; + DIC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[4]_rep__0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ : out STD_LOGIC; + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + CLK : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC; + mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); + idelay_inc : in STD_LOGIC; + LD0 : in STD_LOGIC; + idelay_ld_rst_reg : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + INBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + INRANKC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 ); + OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 ); + \po_counter_read_val_reg[8]\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_0\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_1\ : in STD_LOGIC; + D1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D4 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D5 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D6 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D7 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D8 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0 : in STD_LOGIC; + ofifo_rst_reg0 : in STD_LOGIC; + \read_fifo.tail_r_reg[1]\ : in STD_LOGIC; + if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + my_empty : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mux_wrdata_en : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + calib_wrdata_en : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DOC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[0]\ : in STD_LOGIC; + DOB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[81]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[87]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[97]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[99]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[103]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[115]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + pi_phase_locked_all_r1_reg : in STD_LOGIC; + ofs_rdy_r_reg : in STD_LOGIC_VECTOR ( 2 downto 0 ); + calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 ); + COUNTERREADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized1\ : entity is "mig_7series_v4_2_ddr_byte_lane"; +end \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized1\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized1\ is + signal \^a_rst_primitives_reg\ : STD_LOGIC; + signal C_if_a_empty : STD_LOGIC; + signal C_of_a_full : STD_LOGIC; + signal C_of_full : STD_LOGIC; + signal C_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal C_pi_dqs_out_of_range : STD_LOGIC; + signal C_pi_fine_overflow : STD_LOGIC; + signal C_po_coarse_overflow : STD_LOGIC; + signal C_po_fine_overflow : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 73 downto 0 ); + signal if_d1 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d3 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \if_empty_\ : STD_LOGIC; + signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal ififo_rst : STD_LOGIC; + signal ififo_wr_enable : STD_LOGIC; + signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC; + signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC; + signal iserdes_clkdiv : STD_LOGIC; + signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 ); + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC; + signal ofifo_rst : STD_LOGIC; + signal oserdes_clk : STD_LOGIC; + signal oserdes_clk_delayed : STD_LOGIC; + signal oserdes_clkdiv : STD_LOGIC; + signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal out_fifo_n_0 : STD_LOGIC; + signal out_fifo_n_2 : STD_LOGIC; + signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC; + signal \phaser_in_gen.phaser_in_n_6\ : STD_LOGIC; + signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC; + signal po_oserdes_rst : STD_LOGIC; + signal po_rd_enable : STD_LOGIC; + signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 ); + signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC; + attribute syn_maxfan : string; + attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3"; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE"; + attribute BOX_TYPE of out_fifo : label is "PRIMITIVE"; + attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE"; + attribute BOX_TYPE of phaser_out : label is "PRIMITIVE"; +begin + A_rst_primitives_reg <= \^a_rst_primitives_reg\; + Q(73 downto 0) <= \^q\(73 downto 0); + if_empty_r(0) <= \^if_empty_r\(0); +ddr_byte_group_io: entity work.\ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized1\ + port map ( + CLK => CLK, + CLKB0 => CLKB0, + CTSBUS(0) => oserdes_dqs_ts(0), + D1(3 downto 0) => if_d1(3 downto 0), + D2(3 downto 0) => if_d2(3 downto 0), + D3(3 downto 0) => if_d3(3 downto 0), + D5(3 downto 0) => if_d5(3 downto 0), + D6(3 downto 0) => if_d6(3 downto 0), + D7(3 downto 0) => if_d7(3 downto 0), + D8(3 downto 0) => if_d8(3 downto 0), + D9(3 downto 0) => if_d9(3 downto 0), + DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0), + DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0), + LD0 => LD0, + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\, + idelay_inc => idelay_inc, + idelay_ld_rst => idelay_ld_rst, + idelay_ld_rst_reg_0 => idelay_ld_rst_reg, + \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\, + iserdes_clkdiv => iserdes_clkdiv, + mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0), + mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0), + mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0), + of_dqbus(35 downto 0) => of_dqbus(39 downto 4), + oserdes_clk => oserdes_clk, + oserdes_clk_delayed => oserdes_clk_delayed, + oserdes_clkdiv => oserdes_clkdiv, + out_dqs_0 => out_dqs_0, + po_oserdes_rst => po_oserdes_rst, + ts_dqs_0 => ts_dqs_0 + ); +\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \if_empty_\, + Q => \^if_empty_r\(0), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(10), + Q => \^q\(4), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(11), + Q => \^q\(5), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(12), + Q => \^q\(6), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(13), + Q => \^q\(7), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(14), + Q => \^q\(8), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(15), + Q => \^q\(9), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(16), + Q => \^q\(10), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(17), + Q => \^q\(11), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(18), + Q => \^q\(12), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(19), + Q => \^q\(13), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(20), + Q => \^q\(14), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(21), + Q => \^q\(15), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(22), + Q => \^q\(16), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(23), + Q => \^q\(17), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(24), + Q => \^q\(18), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(25), + Q => \^q\(19), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(26), + Q => \^q\(20), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(27), + Q => \^q\(21), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(28), + Q => \^q\(22), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(29), + Q => \^q\(23), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(30), + Q => \^q\(24), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(31), + Q => \^q\(25), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(32), + Q => \^q\(26), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(33), + Q => \^q\(27), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(34), + Q => \^q\(28), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(35), + Q => \^q\(29), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(36), + Q => \^q\(30), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(37), + Q => \^q\(31), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(38), + Q => \^q\(32), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(39), + Q => \^q\(33), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(40), + Q => \^q\(34), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(41), + Q => \^q\(35), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(42), + Q => \^q\(36), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(43), + Q => \^q\(37), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(44), + Q => \^q\(38), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(45), + Q => \^q\(39), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(46), + Q => \^q\(40), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(47), + Q => \^q\(41), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(48), + Q => \^q\(42), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(49), + Q => \^q\(43), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(50), + Q => \^q\(44), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(51), + Q => \^q\(45), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(52), + Q => \^q\(46), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(53), + Q => \^q\(47), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(54), + Q => \^q\(48), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(55), + Q => \^q\(49), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(56), + Q => \^q\(50), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(57), + Q => \^q\(51), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(58), + Q => \^q\(52), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(59), + Q => \^q\(53), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(60), + Q => \^q\(54), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(61), + Q => \^q\(55), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(62), + Q => \^q\(56), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(63), + Q => \^q\(57), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(64), + Q => \^q\(58), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(65), + Q => \^q\(59), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(66), + Q => \^q\(60), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(67), + Q => \^q\(61), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(68), + Q => \^q\(62), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(69), + Q => \^q\(63), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(6), + Q => \^q\(0), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(70), + Q => \^q\(64), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(71), + Q => \^q\(65), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(72), + Q => \^q\(66), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(73), + Q => \^q\(67), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(74), + Q => \^q\(68), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(75), + Q => \^q\(69), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(76), + Q => \^q\(70), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(77), + Q => \^q\(71), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(78), + Q => \^q\(72), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(79), + Q => \^q\(73), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(7), + Q => \^q\(1), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(8), + Q => \^q\(2), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(9), + Q => \^q\(3), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.ddr3_mig_7series_v4_2_ddr_if_post_fifo_7 + port map ( + CLK => CLK, + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => DIC(1 downto 0), + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + Q(63 downto 24) => \^q\(73 downto 34), + Q(23 downto 0) => \^q\(25 downto 2), + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(63 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(63 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1 downto 0) => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\(1 downto 0) => \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\(1 downto 0), + \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\(1 downto 0) => \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\(1 downto 0), + if_empty_r_0(0) => if_empty_r_0(0), + ififo_rst => ififo_rst, + init_complete_r1_timing_reg => init_complete_r1_timing_reg, + my_empty(1 downto 0) => my_empty(1 downto 0), + \my_empty_reg[0]_0\ => \my_empty_reg[3]\(0), + \my_empty_reg[3]_0\ => \my_empty_reg[3]\(1), + \my_empty_reg[4]_rep__0_0\ => \my_empty_reg[4]_rep__0\, + \my_empty_reg[4]_rep__2_0\ => \^if_empty_r\(0), + \not_strict_mode.app_rd_data_reg[0]\ => \not_strict_mode.app_rd_data_reg[0]\, + \not_strict_mode.app_rd_data_reg[101]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[103]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[115]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[19]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[21]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[33]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[37]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[39]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[49]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[51]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[55]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[67]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[69]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[7]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[81]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[85]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[87]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[97]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[99]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]\(1 downto 0), + \out\(1 downto 0) => \out\(1 downto 0), + phy_rddata_en => phy_rddata_en, + \read_fifo.tail_r_reg[1]\ => \read_fifo.tail_r_reg[1]\, + \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]\ + ); +ififo_rst_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => ififo_rst_reg0, + Q => ififo_rst, + R => '0' + ); +\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO + generic map( + ALMOST_EMPTY_VALUE => 1, + ALMOST_FULL_VALUE => 1, + ARRAY_MODE => "ARRAY_MODE_4_X_8", + SYNCHRONOUS_MODE => "FALSE" + ) + port map ( + ALMOSTEMPTY => C_if_a_empty, + ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\, + D0(3 downto 0) => B"0000", + D1(3 downto 0) => if_d1(3 downto 0), + D2(3 downto 0) => if_d2(3 downto 0), + D3(3 downto 0) => if_d3(3 downto 0), + D4(3 downto 0) => B"0000", + D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4), + D5(3 downto 0) => if_d5(3 downto 0), + D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4), + D6(3 downto 0) => if_d6(3 downto 0), + D7(3 downto 0) => if_d7(3 downto 0), + D8(3 downto 0) => if_d8(3 downto 0), + D9(3 downto 0) => if_d9(3 downto 0), + EMPTY => \if_empty_\, + FULL => \in_fifo_gen.in_fifo_n_3\, + Q0(7 downto 0) => rd_data(7 downto 0), + Q1(7 downto 0) => rd_data(15 downto 8), + Q2(7 downto 0) => rd_data(23 downto 16), + Q3(7 downto 0) => rd_data(31 downto 24), + Q4(7 downto 0) => rd_data(39 downto 32), + Q5(7 downto 0) => rd_data(47 downto 40), + Q6(7 downto 0) => rd_data(55 downto 48), + Q7(7 downto 0) => rd_data(63 downto 56), + Q8(7 downto 0) => rd_data(71 downto 64), + Q9(7 downto 0) => rd_data(79 downto 72), + RDCLK => CLK, + RDEN => '1', + RESET => ififo_rst, + WRCLK => iserdes_clkdiv, + WREN => ififo_wr_enable + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8\ + port map ( + CLK => CLK, + C_of_full => C_of_full, + Q(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + calib_wrdata_en => calib_wrdata_en, + mc_wrdata_en => mc_wrdata_en, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\, + \my_empty_reg[1]_1\ => \my_empty_reg[1]\, + ofifo_rst => ofifo_rst, + ofs_rdy_r_reg(2 downto 0) => ofs_rdy_r_reg(2 downto 0), + phy_mc_data_full => phy_mc_data_full, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]\, + wr_en_2 => wr_en_2, + \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\ + ); +ofifo_rst_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => ofifo_rst_reg0, + Q => ofifo_rst, + R => '0' + ); +out_fifo: unisim.vcomponents.OUT_FIFO + generic map( + ALMOST_EMPTY_VALUE => 1, + ALMOST_FULL_VALUE => 1, + ARRAY_MODE => "ARRAY_MODE_8_X_4", + OUTPUT_DISABLE => "FALSE", + SYNCHRONOUS_MODE => "FALSE" + ) + port map ( + ALMOSTEMPTY => out_fifo_n_0, + ALMOSTFULL => C_of_a_full, + D0(7 downto 0) => B"00000000", + D1(7 downto 0) => D1(7 downto 0), + D2(7 downto 0) => D2(7 downto 0), + D3(7 downto 0) => D3(7 downto 0), + D4(7 downto 0) => D4(7 downto 0), + D5(7 downto 0) => D5(7 downto 0), + D6(7 downto 0) => D6(7 downto 0), + D7(7 downto 0) => D7(7 downto 0), + D8(7 downto 0) => D8(7 downto 0), + D9(7 downto 0) => D9(7 downto 0), + EMPTY => out_fifo_n_2, + FULL => C_of_full, + Q0(3 downto 0) => of_dqbus(3 downto 0), + Q1(3 downto 0) => of_dqbus(7 downto 4), + Q2(3 downto 0) => of_dqbus(11 downto 8), + Q3(3 downto 0) => of_dqbus(15 downto 12), + Q4(3 downto 0) => of_dqbus(19 downto 16), + Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4), + Q5(3 downto 0) => of_dqbus(23 downto 20), + Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4), + Q6(3 downto 0) => of_dqbus(27 downto 24), + Q7(3 downto 0) => of_dqbus(31 downto 28), + Q8(3 downto 0) => of_dqbus(35 downto 32), + Q9(3 downto 0) => of_dqbus(39 downto 36), + RDCLK => oserdes_clkdiv, + RDEN => po_rd_enable, + RESET => ofifo_rst, + WRCLK => CLK, + WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ + ); +\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY + generic map( + BURST_MODE => "TRUE", + CLKOUT_DIV => 2, + DQS_AUTO_RECAL => '1', + DQS_BIAS_MODE => "FALSE", + DQS_FIND_PATTERN => B"001", + FINE_DELAY => 33, + FREQ_REF_DIV => "DIV2", + IS_RST_INVERTED => '0', + MEMREFCLK_PERIOD => 3.000000, + OUTPUT_CLK_SRC => "DELAYED_REF", + PHASEREFCLK_PERIOD => 3.000000, + REFCLK_PERIOD => 1.500000, + SEL_CLK_OFFSET => 6, + SYNC_IN_DIV_RST => "TRUE", + WR_CYCLES => "FALSE" + ) + port map ( + BURSTPENDINGPHY => INBURSTPENDING(0), + COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[2]\, + COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0), + COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[2]_0\, + COUNTERREADVAL(5 downto 0) => C_pi_counter_read_val(5 downto 0), + DQSFOUND => pi_dqs_found_lanes(0), + DQSOUTOFRANGE => C_pi_dqs_out_of_range, + ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0), + FINEENABLE => \pi_dqs_found_lanes_r1_reg[2]_1\, + FINEINC => \pi_dqs_found_lanes_r1_reg[2]_2\, + FINEOVERFLOW => C_pi_fine_overflow, + FREQREFCLK => freq_refclk, + ICLK => \^a_rst_primitives_reg\, + ICLKDIV => iserdes_clkdiv, + ISERDESRST => \phaser_in_gen.phaser_in_n_5\, + MEMREFCLK => mem_refclk, + PHASELOCKED => \phaser_in_gen.phaser_in_n_6\, + PHASEREFCLK => mem_dqs_in(0), + RANKSELPHY(1 downto 0) => INRANKC(1 downto 0), + RCLK => \phaser_in_gen.phaser_in_n_7\, + RST => idelay_ld_rst_reg, + RSTDQSFIND => \pi_dqs_found_lanes_r1_reg[2]_3\, + SYNCIN => sync_pulse, + SYSCLK => CLK, + WRENABLE => ififo_wr_enable + ); +phaser_out: unisim.vcomponents.PHASER_OUT_PHY + generic map( + CLKOUT_DIV => 2, + COARSE_BYPASS => "FALSE", + COARSE_DELAY => 0, + DATA_CTL_N => "TRUE", + DATA_RD_CYCLES => "FALSE", + FINE_DELAY => 60, + IS_RST_INVERTED => '0', + MEMREFCLK_PERIOD => 3.000000, + OCLKDELAY_INV => "FALSE", + OCLK_DELAY => 0, + OUTPUT_CLK_SRC => "DELAYED_REF", + PHASEREFCLK_PERIOD => 1.000000, + PO => B"111", + REFCLK_PERIOD => 1.500000, + SYNC_IN_DIV_RST => "TRUE" + ) + port map ( + BURSTPENDINGPHY => OUTBURSTPENDING(0), + COARSEENABLE => \po_counter_read_val_reg[8]\, + COARSEINC => \po_counter_read_val_reg[8]\, + COARSEOVERFLOW => C_po_coarse_overflow, + COUNTERLOADEN => '0', + COUNTERLOADVAL(8 downto 0) => B"000000000", + COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[2]_0\, + COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_0(8 downto 0), + CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0), + DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0), + DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0), + ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0), + FINEENABLE => \po_counter_read_val_reg[8]_0\, + FINEINC => \po_counter_read_val_reg[8]_1\, + FINEOVERFLOW => C_po_fine_overflow, + FREQREFCLK => freq_refclk, + MEMREFCLK => mem_refclk, + OCLK => oserdes_clk, + OCLKDELAYED => oserdes_clk_delayed, + OCLKDIV => oserdes_clkdiv, + OSERDESRST => po_oserdes_rst, + PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED, + RDENABLE => po_rd_enable, + RST => idelay_ld_rst_reg, + SELFINEOCLKDELAY => '0', + SYNCIN => sync_pulse, + SYSCLK => CLK + ); +\pi_counter_read_val[0]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E020" + ) + port map ( + I0 => C_pi_counter_read_val(0), + I1 => calib_sel(0), + I2 => calib_sel(1), + I3 => COUNTERREADVAL(0), + O => D(0) + ); +\pi_counter_read_val[1]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E020" + ) + port map ( + I0 => C_pi_counter_read_val(1), + I1 => calib_sel(0), + I2 => calib_sel(1), + I3 => COUNTERREADVAL(1), + O => D(1) + ); +\pi_counter_read_val[2]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E020" + ) + port map ( + I0 => C_pi_counter_read_val(2), + I1 => calib_sel(0), + I2 => calib_sel(1), + I3 => COUNTERREADVAL(2), + O => D(2) + ); +\pi_counter_read_val[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E020" + ) + port map ( + I0 => C_pi_counter_read_val(3), + I1 => calib_sel(0), + I2 => calib_sel(1), + I3 => COUNTERREADVAL(3), + O => D(3) + ); +\pi_counter_read_val[4]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E020" + ) + port map ( + I0 => C_pi_counter_read_val(4), + I1 => calib_sel(0), + I2 => calib_sel(1), + I3 => COUNTERREADVAL(4), + O => D(4) + ); +\pi_counter_read_val[5]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"E020" + ) + port map ( + I0 => C_pi_counter_read_val(5), + I1 => calib_sel(0), + I2 => calib_sel(1), + I3 => COUNTERREADVAL(5), + O => D(5) + ); +pi_phase_locked_all_inferred_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \phaser_in_gen.phaser_in_n_6\, + I1 => pi_phase_locked_all_r1_reg, + O => in0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized2\ is + port ( + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg : out STD_LOGIC; + mem_dq_out : out STD_LOGIC_VECTOR ( 8 downto 0 ); + mem_dq_ts : out STD_LOGIC_VECTOR ( 8 downto 0 ); + out_dqs_1 : out STD_LOGIC; + ts_dqs_1 : out STD_LOGIC; + pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 0 to 0 ); + A_rst_primitives_reg_0 : out STD_LOGIC; + COUNTERREADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 ); + A_rst_primitives_reg_1 : out STD_LOGIC_VECTOR ( 8 downto 0 ); + if_empty_r : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \my_empty_reg[1]\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 73 downto 0 ); + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \my_empty_reg[4]_rep__1\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + rd_data_en : out STD_LOGIC; + \my_empty_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[0]\ : out STD_LOGIC; + \my_empty_reg[0]_0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); + \entry_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + wr_en : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[0]\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + p_1_in : out STD_LOGIC; + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + CLK : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC; + mem_dq_in : in STD_LOGIC_VECTOR ( 7 downto 0 ); + idelay_inc : in STD_LOGIC; + LD0_0 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + INBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + mem_dqs_in : in STD_LOGIC_VECTOR ( 0 to 0 ); + \pi_dqs_found_lanes_r1_reg[3]_4\ : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + PCENABLECALIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + INRANKD : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pi_dqs_found_lanes_r1_reg[3]_5\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + OUTBURSTPENDING : in STD_LOGIC_VECTOR ( 0 to 0 ); + \po_counter_read_val_reg[8]\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_0\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_1\ : in STD_LOGIC; + D0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0_1 : in STD_LOGIC; + ofifo_rst_reg0_2 : in STD_LOGIC; + mux_wrdata_en : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + out_fifo_0 : in STD_LOGIC; + calib_wrdata_en : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC; + DIC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[4]_rep__2\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + if_empty_r_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg_0_sp_1\ : in STD_LOGIC; + \not_strict_mode.app_rd_data[127]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[8]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[73]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[75]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[79]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[91]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[93]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[105]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[109]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[111]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[121]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[123]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \wr_ptr_timing_reg[0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized2\ : entity is "mig_7series_v4_2_ddr_byte_lane"; +end \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized2\; + +architecture STRUCTURE of \ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized2\ is + signal \^a_rst_primitives_reg\ : STD_LOGIC; + signal D_if_a_empty : STD_LOGIC; + signal D_of_a_full : STD_LOGIC; + signal D_of_full : STD_LOGIC; + signal D_pi_dqs_out_of_range : STD_LOGIC; + signal D_pi_fine_overflow : STD_LOGIC; + signal D_po_coarse_overflow : STD_LOGIC; + signal D_po_fine_overflow : STD_LOGIC; + signal \^q\ : STD_LOGIC_VECTOR ( 73 downto 0 ); + signal if_d0 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d2 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d4 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d5 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d6 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d7 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d8 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_d9 : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \if_empty_\ : STD_LOGIC; + signal \^if_empty_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal ififo_rst : STD_LOGIC; + signal ififo_wr_enable : STD_LOGIC; + signal \in_fifo_gen.in_fifo_n_1\ : STD_LOGIC; + signal \in_fifo_gen.in_fifo_n_3\ : STD_LOGIC; + signal iserdes_clkdiv : STD_LOGIC; + signal of_dqbus : STD_LOGIC_VECTOR ( 39 downto 0 ); + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ : STD_LOGIC; + signal ofifo_rst : STD_LOGIC; + signal oserdes_clk : STD_LOGIC; + signal oserdes_clk_delayed : STD_LOGIC; + signal oserdes_clkdiv : STD_LOGIC; + signal oserdes_dq_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal oserdes_dqs_ts : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal out_fifo_n_0 : STD_LOGIC; + signal out_fifo_n_2 : STD_LOGIC; + signal \phaser_in_gen.phaser_in_n_5\ : STD_LOGIC; + signal \phaser_in_gen.phaser_in_n_7\ : STD_LOGIC; + signal po_oserdes_rst : STD_LOGIC; + signal po_rd_enable : STD_LOGIC; + signal rd_data : STD_LOGIC_VECTOR ( 79 downto 0 ); + signal \read_fifo.tail_r_reg_0_sn_1\ : STD_LOGIC; + signal \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal NLW_out_fifo_Q5_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal NLW_out_fifo_Q6_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 4 ); + signal NLW_phaser_out_PHASEREFCLK_UNCONNECTED : STD_LOGIC; + attribute syn_maxfan : string; + attribute syn_maxfan of \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : label is "3"; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \in_fifo_gen.in_fifo\ : label is "PRIMITIVE"; + attribute BOX_TYPE of out_fifo : label is "PRIMITIVE"; + attribute BOX_TYPE of \phaser_in_gen.phaser_in\ : label is "PRIMITIVE"; + attribute BOX_TYPE of phaser_out : label is "PRIMITIVE"; +begin + A_rst_primitives_reg <= \^a_rst_primitives_reg\; + Q(73 downto 0) <= \^q\(73 downto 0); + if_empty_r(0) <= \^if_empty_r\(0); + \read_fifo.tail_r_reg_0_sn_1\ <= \read_fifo.tail_r_reg_0_sp_1\; +ddr_byte_group_io: entity work.\ddr3_mig_7series_v4_2_ddr_byte_group_io__parameterized2\ + port map ( + CLK => CLK, + CLKB0_4 => CLKB0_4, + CTSBUS(0) => oserdes_dqs_ts(0), + D0(3 downto 0) => if_d0(3 downto 0), + D2(3 downto 0) => if_d2(3 downto 0), + D4(3 downto 0) => if_d4(3 downto 0), + D5(3 downto 0) => if_d5(3 downto 0), + D6(3 downto 0) => if_d6(3 downto 0), + D7(3 downto 0) => if_d7(3 downto 0), + D8(3 downto 0) => if_d8(3 downto 0), + D9(3 downto 0) => if_d9(3 downto 0), + DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0), + DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0), + LD0_0 => LD0_0, + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \^a_rst_primitives_reg\, + idelay_inc => idelay_inc, + \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq\, + \input_[9].iserdes_dq_.iserdesdq_1\ => \pi_dqs_found_lanes_r1_reg[3]\, + iserdes_clkdiv => iserdes_clkdiv, + mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0), + mem_dq_out(8 downto 0) => mem_dq_out(8 downto 0), + mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0), + of_dqbus(35 downto 12) => of_dqbus(39 downto 16), + of_dqbus(11 downto 0) => of_dqbus(11 downto 0), + oserdes_clk => oserdes_clk, + oserdes_clk_delayed => oserdes_clk_delayed, + oserdes_clkdiv => oserdes_clkdiv, + out_dqs_1 => out_dqs_1, + po_oserdes_rst => po_oserdes_rst, + ts_dqs_1 => ts_dqs_1 + ); +\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \if_empty_\, + Q => \^if_empty_r\(0), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(0), + Q => \^q\(0), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(10), + Q => \^q\(10), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(11), + Q => \^q\(11), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(12), + Q => \^q\(12), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(13), + Q => \^q\(13), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(14), + Q => \^q\(14), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(15), + Q => \^q\(15), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(16), + Q => \^q\(16), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(17), + Q => \^q\(17), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(18), + Q => \^q\(18), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(19), + Q => \^q\(19), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(1), + Q => \^q\(1), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(20), + Q => \^q\(20), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(21), + Q => \^q\(21), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(22), + Q => \^q\(22), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(23), + Q => \^q\(23), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(2), + Q => \^q\(2), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(30), + Q => \^q\(24), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(31), + Q => \^q\(25), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(32), + Q => \^q\(26), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(33), + Q => \^q\(27), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(34), + Q => \^q\(28), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(35), + Q => \^q\(29), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(36), + Q => \^q\(30), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(37), + Q => \^q\(31), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(38), + Q => \^q\(32), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(39), + Q => \^q\(33), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(3), + Q => \^q\(3), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(40), + Q => \^q\(34), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(41), + Q => \^q\(35), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(42), + Q => \^q\(36), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(43), + Q => \^q\(37), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(44), + Q => \^q\(38), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(45), + Q => \^q\(39), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(46), + Q => \^q\(40), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(47), + Q => \^q\(41), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(48), + Q => \^q\(42), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(49), + Q => \^q\(43), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(4), + Q => \^q\(4), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(50), + Q => \^q\(44), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(51), + Q => \^q\(45), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(52), + Q => \^q\(46), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(53), + Q => \^q\(47), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(54), + Q => \^q\(48), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(55), + Q => \^q\(49), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(56), + Q => \^q\(50), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(57), + Q => \^q\(51), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(58), + Q => \^q\(52), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(59), + Q => \^q\(53), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(5), + Q => \^q\(5), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(60), + Q => \^q\(54), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(61), + Q => \^q\(55), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(62), + Q => \^q\(56), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(63), + Q => \^q\(57), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(64), + Q => \^q\(58), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(65), + Q => \^q\(59), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(66), + Q => \^q\(60), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(67), + Q => \^q\(61), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(68), + Q => \^q\(62), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(69), + Q => \^q\(63), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(6), + Q => \^q\(6), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(70), + Q => \^q\(64), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(71), + Q => \^q\(65), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(72), + Q => \^q\(66), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(73), + Q => \^q\(67), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(74), + Q => \^q\(68), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(75), + Q => \^q\(69), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(76), + Q => \^q\(70), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(77), + Q => \^q\(71), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(78), + Q => \^q\(72), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(79), + Q => \^q\(73), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(7), + Q => \^q\(7), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(8), + Q => \^q\(8), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => rd_data(9), + Q => \^q\(9), + R => '0' + ); +\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo\: entity work.ddr3_mig_7series_v4_2_ddr_if_post_fifo + port map ( + CLK => CLK, + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => DIC(1 downto 0), + Q(63 downto 16) => \^q\(73 downto 26), + Q(15 downto 8) => \^q\(23 downto 16), + Q(7 downto 0) => \^q\(7 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(63 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(63 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(1 downto 0), + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1 downto 0) => \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1 downto 0), + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1 downto 0) => \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1 downto 0), + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1 downto 0) => \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1 downto 0), + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1 downto 0) => \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1 downto 0), + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1 downto 0) => \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1 downto 0), + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1 downto 0), + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1 downto 0), + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1 downto 0), + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\(1 downto 0) => \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\(1 downto 0), + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1 downto 0), + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1 downto 0), + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1 downto 0), + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1 downto 0) => \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1 downto 0), + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1 downto 0), + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1 downto 0), + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1 downto 0), + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\(1 downto 0) => \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\(1 downto 0), + if_empty_r_0(0) => if_empty_r_0(0), + ififo_rst => ififo_rst, + \my_empty_reg[0]_0\ => \my_empty_reg[3]\(0), + \my_empty_reg[0]_1\ => \my_empty_reg[0]\, + \my_empty_reg[0]_2\ => \my_empty_reg[0]_0\, + \my_empty_reg[3]_0\ => \my_empty_reg[3]\(1), + \my_empty_reg[4]_rep__1_0\ => \my_empty_reg[4]_rep__1\, + \my_empty_reg[4]_rep__2_0\ => \^if_empty_r\(0), + \my_empty_reg[4]_rep__2_1\(1 downto 0) => \my_empty_reg[4]_rep__2\(1 downto 0), + \not_strict_mode.app_rd_data[127]_i_2\(0) => \not_strict_mode.app_rd_data[127]_i_2\(0), + \not_strict_mode.app_rd_data_reg[105]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[109]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[111]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[121]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[123]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[13]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[15]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[25]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[27]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[31]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[43]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[45]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[57]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[61]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[63]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[73]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[75]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[79]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\, + \not_strict_mode.app_rd_data_reg[91]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[93]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[9]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]\(1 downto 0), + p_1_in => p_1_in, + rd_data_en => rd_data_en, + \rd_ptr_timing_reg[1]_0\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + \read_fifo.tail_r_reg\(0) => \read_fifo.tail_r_reg\(0), + \read_fifo.tail_r_reg_0_sp_1\ => \read_fifo.tail_r_reg_0_sn_1\, + \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]\ + ); +ififo_rst_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => ififo_rst_reg0_1, + Q => ififo_rst, + R => '0' + ); +\in_fifo_gen.in_fifo\: unisim.vcomponents.IN_FIFO + generic map( + ALMOST_EMPTY_VALUE => 1, + ALMOST_FULL_VALUE => 1, + ARRAY_MODE => "ARRAY_MODE_4_X_8", + SYNCHRONOUS_MODE => "FALSE" + ) + port map ( + ALMOSTEMPTY => D_if_a_empty, + ALMOSTFULL => \in_fifo_gen.in_fifo_n_1\, + D0(3 downto 0) => if_d0(3 downto 0), + D1(3 downto 0) => B"0000", + D2(3 downto 0) => if_d2(3 downto 0), + D3(3 downto 0) => B"0000", + D4(3 downto 0) => if_d4(3 downto 0), + D5(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED\(7 downto 4), + D5(3 downto 0) => if_d5(3 downto 0), + D6(7 downto 4) => \NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED\(7 downto 4), + D6(3 downto 0) => if_d6(3 downto 0), + D7(3 downto 0) => if_d7(3 downto 0), + D8(3 downto 0) => if_d8(3 downto 0), + D9(3 downto 0) => if_d9(3 downto 0), + EMPTY => \if_empty_\, + FULL => \in_fifo_gen.in_fifo_n_3\, + Q0(7 downto 0) => rd_data(7 downto 0), + Q1(7 downto 0) => rd_data(15 downto 8), + Q2(7 downto 0) => rd_data(23 downto 16), + Q3(7 downto 0) => rd_data(31 downto 24), + Q4(7 downto 0) => rd_data(39 downto 32), + Q5(7 downto 0) => rd_data(47 downto 40), + Q6(7 downto 0) => rd_data(55 downto 48), + Q7(7 downto 0) => rd_data(63 downto 56), + Q8(7 downto 0) => rd_data(71 downto 64), + Q9(7 downto 0) => rd_data(79 downto 72), + RDCLK => CLK, + RDEN => '1', + RESET => ififo_rst, + WRCLK => iserdes_clkdiv, + WREN => ififo_wr_enable + ); +\of_pre_fifo_gen.u_ddr_of_pre_fifo\: entity work.\ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1\ + port map ( + CLK => CLK, + D_of_full => D_of_full, + Q(2 downto 0) => \entry_cnt_reg[4]\(2 downto 0), + calib_wrdata_en => calib_wrdata_en, + mc_wrdata_en => mc_wrdata_en, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[1]_0\ => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\, + \my_empty_reg[1]_1\ => \my_empty_reg[1]\, + ofifo_rst => ofifo_rst, + out_fifo => out_fifo_0, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]\, + wr_en => wr_en, + \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]\ + ); +ofifo_rst_reg: unisim.vcomponents.FDRE + generic map( + INIT => '1' + ) + port map ( + C => CLK, + CE => '1', + D => ofifo_rst_reg0_2, + Q => ofifo_rst, + R => '0' + ); +out_fifo: unisim.vcomponents.OUT_FIFO + generic map( + ALMOST_EMPTY_VALUE => 1, + ALMOST_FULL_VALUE => 1, + ARRAY_MODE => "ARRAY_MODE_8_X_4", + OUTPUT_DISABLE => "FALSE", + SYNCHRONOUS_MODE => "FALSE" + ) + port map ( + ALMOSTEMPTY => out_fifo_n_0, + ALMOSTFULL => D_of_a_full, + D0(7 downto 0) => D0(7 downto 0), + D1(7 downto 0) => \my_empty_reg[7]\(7 downto 0), + D2(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0), + D3(7 downto 0) => B"00000000", + D4(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0), + D5(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0), + D6(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0), + D7(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0), + D8(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0), + D9(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0), + EMPTY => out_fifo_n_2, + FULL => D_of_full, + Q0(3 downto 0) => of_dqbus(3 downto 0), + Q1(3 downto 0) => of_dqbus(7 downto 4), + Q2(3 downto 0) => of_dqbus(11 downto 8), + Q3(3 downto 0) => of_dqbus(15 downto 12), + Q4(3 downto 0) => of_dqbus(19 downto 16), + Q5(7 downto 4) => NLW_out_fifo_Q5_UNCONNECTED(7 downto 4), + Q5(3 downto 0) => of_dqbus(23 downto 20), + Q6(7 downto 4) => NLW_out_fifo_Q6_UNCONNECTED(7 downto 4), + Q6(3 downto 0) => of_dqbus(27 downto 24), + Q7(3 downto 0) => of_dqbus(31 downto 28), + Q8(3 downto 0) => of_dqbus(35 downto 32), + Q9(3 downto 0) => of_dqbus(39 downto 36), + RDCLK => oserdes_clkdiv, + RDEN => po_rd_enable, + RESET => ofifo_rst, + WRCLK => CLK, + WREN => \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4\ + ); +\phaser_in_gen.phaser_in\: unisim.vcomponents.PHASER_IN_PHY + generic map( + BURST_MODE => "TRUE", + CLKOUT_DIV => 2, + DQS_AUTO_RECAL => '1', + DQS_BIAS_MODE => "FALSE", + DQS_FIND_PATTERN => B"001", + FINE_DELAY => 33, + FREQ_REF_DIV => "DIV2", + IS_RST_INVERTED => '0', + MEMREFCLK_PERIOD => 3.000000, + OUTPUT_CLK_SRC => "DELAYED_REF", + PHASEREFCLK_PERIOD => 3.000000, + REFCLK_PERIOD => 1.500000, + SEL_CLK_OFFSET => 6, + SYNC_IN_DIV_RST => "TRUE", + WR_CYCLES => "FALSE" + ) + port map ( + BURSTPENDINGPHY => INBURSTPENDING(0), + COUNTERLOADEN => \pi_dqs_found_lanes_r1_reg[3]_0\, + COUNTERLOADVAL(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_5\(5 downto 0), + COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[3]_1\, + COUNTERREADVAL(5 downto 0) => COUNTERREADVAL(5 downto 0), + DQSFOUND => pi_dqs_found_lanes(0), + DQSOUTOFRANGE => D_pi_dqs_out_of_range, + ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0), + FINEENABLE => \pi_dqs_found_lanes_r1_reg[3]_2\, + FINEINC => \pi_dqs_found_lanes_r1_reg[3]_3\, + FINEOVERFLOW => D_pi_fine_overflow, + FREQREFCLK => freq_refclk, + ICLK => \^a_rst_primitives_reg\, + ICLKDIV => iserdes_clkdiv, + ISERDESRST => \phaser_in_gen.phaser_in_n_5\, + MEMREFCLK => mem_refclk, + PHASELOCKED => A_rst_primitives_reg_0, + PHASEREFCLK => mem_dqs_in(0), + RANKSELPHY(1 downto 0) => INRANKD(1 downto 0), + RCLK => \phaser_in_gen.phaser_in_n_7\, + RST => \pi_dqs_found_lanes_r1_reg[3]\, + RSTDQSFIND => \pi_dqs_found_lanes_r1_reg[3]_4\, + SYNCIN => sync_pulse, + SYSCLK => CLK, + WRENABLE => ififo_wr_enable + ); +phaser_out: unisim.vcomponents.PHASER_OUT_PHY + generic map( + CLKOUT_DIV => 2, + COARSE_BYPASS => "FALSE", + COARSE_DELAY => 0, + DATA_CTL_N => "TRUE", + DATA_RD_CYCLES => "FALSE", + FINE_DELAY => 60, + IS_RST_INVERTED => '0', + MEMREFCLK_PERIOD => 3.000000, + OCLKDELAY_INV => "FALSE", + OCLK_DELAY => 0, + OUTPUT_CLK_SRC => "DELAYED_REF", + PHASEREFCLK_PERIOD => 1.000000, + PO => B"111", + REFCLK_PERIOD => 1.500000, + SYNC_IN_DIV_RST => "TRUE" + ) + port map ( + BURSTPENDINGPHY => OUTBURSTPENDING(0), + COARSEENABLE => \po_counter_read_val_reg[8]\, + COARSEINC => \po_counter_read_val_reg[8]\, + COARSEOVERFLOW => D_po_coarse_overflow, + COUNTERLOADEN => '0', + COUNTERLOADVAL(8 downto 0) => B"000000000", + COUNTERREADEN => \pi_dqs_found_lanes_r1_reg[3]_1\, + COUNTERREADVAL(8 downto 0) => A_rst_primitives_reg_1(8 downto 0), + CTSBUS(1 downto 0) => oserdes_dqs_ts(1 downto 0), + DQSBUS(1 downto 0) => oserdes_dqs(1 downto 0), + DTSBUS(1 downto 0) => oserdes_dq_ts(1 downto 0), + ENCALIBPHY(1 downto 0) => PCENABLECALIB(1 downto 0), + FINEENABLE => \po_counter_read_val_reg[8]_0\, + FINEINC => \po_counter_read_val_reg[8]_1\, + FINEOVERFLOW => D_po_fine_overflow, + FREQREFCLK => freq_refclk, + MEMREFCLK => mem_refclk, + OCLK => oserdes_clk, + OCLKDELAYED => oserdes_clk_delayed, + OCLKDIV => oserdes_clkdiv, + OSERDESRST => po_oserdes_rst, + PHASEREFCLK => NLW_phaser_out_PHASEREFCLK_UNCONNECTED, + RDENABLE => po_rd_enable, + RST => \pi_dqs_found_lanes_r1_reg[3]\, + SELFINEOCLKDELAY => '0', + SYNCIN => sync_pulse, + SYSCLK => CLK + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_calib_top is + port ( + dqs_po_dec_done : out STD_LOGIC; + po_cnt_dec_reg : out STD_LOGIC; + po_cnt_dec_0 : out STD_LOGIC; + \rd_mux_sel_r_reg[0]\ : out STD_LOGIC; + new_cnt_cpt_r_reg : out STD_LOGIC; + rdlvl_stg1_start_reg : out STD_LOGIC; + samp_edge_cnt0_en_r : out STD_LOGIC; + pi_fine_dly_dec_done : out STD_LOGIC; + pi_cnt_dec_reg : out STD_LOGIC; + rdlvl_stg1_done_int_reg : out STD_LOGIC; + \out\ : out STD_LOGIC; + prbs_rdlvl_done_pulse_reg : out STD_LOGIC; + calib_cmd_wren : out STD_LOGIC; + calib_wrdata_en : out STD_LOGIC; + phy_write_calib : out STD_LOGIC; + phy_read_calib : out STD_LOGIC; + tempmon_pi_f_inc : out STD_LOGIC; + tempmon_pi_f_dec : out STD_LOGIC; + idelay_inc : out STD_LOGIC; + phy_dout : out STD_LOGIC_VECTOR ( 39 downto 0 ); + rdlvl_stg1_done_r1 : out STD_LOGIC; + calib_in_common : out STD_LOGIC; + init_calib_complete_reg_rep_0 : out STD_LOGIC; + \init_calib_complete_reg_rep__0_0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__1_0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__2_0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__5_0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__7_0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__8_0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__9_0\ : out STD_LOGIC; + wrcal_done_reg : out STD_LOGIC; + calib_ctl_wren_reg : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_0\ : out STD_LOGIC; + calib_sel : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_byte_sel_div2.calib_in_common_reg_1\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_2\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_3\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_4\ : out STD_LOGIC; + dqs_wl_po_stg2_c_incdec_reg : out STD_LOGIC; + \calib_sel_reg[1]_0\ : out STD_LOGIC; + \calib_sel_reg[1]_1\ : out STD_LOGIC; + \calib_sel_reg[1]_2\ : out STD_LOGIC; + \calib_sel_reg[1]_3\ : out STD_LOGIC; + \calib_sel_reg[1]_4\ : out STD_LOGIC; + \calib_sel_reg[1]_5\ : out STD_LOGIC; + \calib_sel_reg[1]_6\ : out STD_LOGIC; + \calib_sel_reg[1]_7\ : out STD_LOGIC; + \calib_sel_reg[1]_8\ : out STD_LOGIC; + \calib_sel_reg[1]_9\ : out STD_LOGIC; + idelay_ce_r2_reg_0 : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_5\ : out STD_LOGIC; + \calib_sel_reg[0]_0\ : out STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_6\ : out STD_LOGIC; + ck_po_stg2_f_indec_reg : out STD_LOGIC; + \pi_rst_stg1_cal_reg[0]\ : out STD_LOGIC; + pi_en_stg2_f_reg : out STD_LOGIC; + pi_stg2_f_incdec_reg : out STD_LOGIC; + pi_stg2_load_reg : out STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC_VECTOR ( 32 downto 0 ); + \gen_byte_sel_div2.calib_in_common_reg_7\ : out STD_LOGIC; + \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 59 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 59 downto 0 ); + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[3]\ : out STD_LOGIC; + \my_empty_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[3]_0\ : out STD_LOGIC; + \my_empty_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[3]_1\ : out STD_LOGIC; + \po_stg2_wrcal_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \init_calib_complete_reg_rep__9_1\ : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + mux_wrdata_en : out STD_LOGIC; + mux_cmd_wren : out STD_LOGIC; + mux_reset_n : out STD_LOGIC; + LD0 : out STD_LOGIC; + ififo_rst_reg0 : out STD_LOGIC; + ofifo_rst_reg0 : out STD_LOGIC; + LD0_0 : out STD_LOGIC; + ififo_rst_reg0_1 : out STD_LOGIC; + ofifo_rst_reg0_2 : out STD_LOGIC; + D1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D4 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D5 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D6 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D7 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D9 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + D0 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \init_calib_complete_reg_rep__5_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \write_buffer.wr_buf_out_data_reg[122]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \write_buffer.wr_buf_out_data_reg[123]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \write_buffer.wr_buf_out_data_reg[126]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \write_buffer.wr_buf_out_data_reg[124]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \write_buffer.wr_buf_out_data_reg[121]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \write_buffer.wr_buf_out_data_reg[125]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + D : out STD_LOGIC_VECTOR ( 10 downto 0 ); + COUNTERLOADVAL : out STD_LOGIC_VECTOR ( 5 downto 0 ); + \pi_stg2_reg_l_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + calib_in_common4_out : out STD_LOGIC; + dqs_found_done_r_reg : out STD_LOGIC; + \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_ras_n_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_cke_reg[3]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_odt_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_we_n_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : in STD_LOGIC_VECTOR ( 0 to 0 ); + CLK : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + dqs_po_en_stg2_f_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dqs_count_r_reg[0]\ : in STD_LOGIC; + wl_edge_detect_valid_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + po_en_stg2_f_reg : in STD_LOGIC; + \done_cnt_reg[1]\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC; + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + first_fail_detect_reg : in STD_LOGIC; + in0 : in STD_LOGIC; + pi_dqs_found_done_r1_reg : in STD_LOGIC; + prbs_rdlvl_done_pulse0 : in STD_LOGIC; + mc_ref_zq_wip : in STD_LOGIC; + \four_dec_min_limit_reg[0]\ : in STD_LOGIC; + \cnt_pwron_ce_r_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + tempmon_sel_pi_incdec : in STD_LOGIC; + phy_rddata_en : in STD_LOGIC; + \gen_byte_sel_div2.calib_in_common_reg_8\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : in STD_LOGIC; + idelay_ld_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC; + complex_row0_rd_done_reg : in STD_LOGIC; + \not_empty_wait_cnt_reg[4]\ : in STD_LOGIC; + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : in STD_LOGIC_VECTOR ( 143 downto 0 ); + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + \wr_en_inferred__0_i_1\ : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + \wr_en_inferred__0_i_1__0\ : in STD_LOGIC; + \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC; + \wr_en_inferred__0_i_1__1\ : in STD_LOGIC; + \rd_data_edge_detect_r_reg[1]\ : in STD_LOGIC; + \po_rdval_cnt_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 ); + \pi_rdval_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + store_sr_req_r_reg : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_ras_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_we_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + idelay_ld_rst : in STD_LOGIC; + A_rst_primitives : in STD_LOGIC; + out_fifo : in STD_LOGIC_VECTOR ( 71 downto 0 ); + out_fifo_0 : in STD_LOGIC; + out_fifo_1 : in STD_LOGIC_VECTOR ( 71 downto 0 ); + out_fifo_2 : in STD_LOGIC; + mc_address : in STD_LOGIC_VECTOR ( 40 downto 0 ); + mem_out : in STD_LOGIC_VECTOR ( 31 downto 0 ); + out_fifo_3 : in STD_LOGIC; + \dqs_count_r_reg[0]_rep\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\ : in STD_LOGIC; + \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\ : in STD_LOGIC; + \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[18]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC; + mc_data_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); + \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC; + mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 ); + out_fifo_4 : in STD_LOGIC_VECTOR ( 44 downto 0 ); + out_fifo_5 : in STD_LOGIC; + pi_dqs_found_lanes : in STD_LOGIC_VECTOR ( 1 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_calib_top : entity is "mig_7series_v4_2_ddr_calib_top"; +end ddr3_mig_7series_v4_2_ddr_calib_top; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_calib_top is + signal RSTB : STD_LOGIC; + signal address_w : STD_LOGIC_VECTOR ( 12 to 12 ); + signal calib_complete : STD_LOGIC; + signal \^calib_in_common\ : STD_LOGIC; + signal \^calib_sel\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal calib_sel0 : STD_LOGIC; + signal calib_sel15_out : STD_LOGIC; + signal \calib_sel[0]_i_2_n_0\ : STD_LOGIC; + signal calib_zero_inputs : STD_LOGIC; + signal ck_addr_cmd_delay_done : STD_LOGIC; + signal ck_po_stg2_f_en : STD_LOGIC; + signal ck_po_stg2_f_indec : STD_LOGIC; + signal cmd_delay_start0 : STD_LOGIC; + signal cmd_po_en_stg2_f : STD_LOGIC; + signal cnt_pwron_cke_done_r : STD_LOGIC; + signal ctl_lane_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal ddr3_lm_done_r : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_29\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8\ : STD_LOGIC; + signal ddr_phy_tempmon_0_n_2 : STD_LOGIC; + signal ddr_phy_tempmon_0_n_3 : STD_LOGIC; + signal ddr_phy_tempmon_0_n_5 : STD_LOGIC; + signal ddr_phy_tempmon_0_n_6 : STD_LOGIC; + signal detect_pi_found_dqs : STD_LOGIC; + signal done_dqs_dec237_out : STD_LOGIC; + signal done_dqs_tap_inc : STD_LOGIC; + signal dqs_found_prech_req : STD_LOGIC; + signal \^dqs_po_dec_done\ : STD_LOGIC; + signal dqs_po_en_stg2_f : STD_LOGIC; + signal dqs_po_stg2_f_incdec : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_13\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_14\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_15\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_16\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_17\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_18\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_19\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_3\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31\ : STD_LOGIC; + signal \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32\ : STD_LOGIC; + signal fine_adj_state_r : STD_LOGIC_VECTOR ( 0 to 0 ); + signal first_rdlvl_pat_r : STD_LOGIC; + signal first_wrcal_pat_r : STD_LOGIC; + signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\ : STD_LOGIC; + signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\ : STD_LOGIC; + signal \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\ : STD_LOGIC; + signal idelay_ce : STD_LOGIC; + signal idelay_ce_int : STD_LOGIC; + signal idelay_ce_r1 : STD_LOGIC; + signal idelay_inc_int : STD_LOGIC; + signal idelay_inc_r1 : STD_LOGIC; + signal \^init_calib_complete_reg_rep_0\ : STD_LOGIC; + signal \^init_calib_complete_reg_rep__0_0\ : STD_LOGIC; + signal \^init_calib_complete_reg_rep__1_0\ : STD_LOGIC; + signal \^init_calib_complete_reg_rep__2_0\ : STD_LOGIC; + signal \init_calib_complete_reg_rep__3_n_0\ : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of \init_calib_complete_reg_rep__3_n_0\ : signal is "50"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__3_n_0\ : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of \init_calib_complete_reg_rep__3_n_0\ : signal is "10"; + signal \init_calib_complete_reg_rep__4_n_0\ : STD_LOGIC; + attribute MAX_FANOUT of \init_calib_complete_reg_rep__4_n_0\ : signal is "50"; + attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__4_n_0\ : signal is "found"; + attribute syn_maxfan of \init_calib_complete_reg_rep__4_n_0\ : signal is "10"; + signal \^init_calib_complete_reg_rep__5_0\ : STD_LOGIC; + signal \init_calib_complete_reg_rep__6_n_0\ : STD_LOGIC; + attribute MAX_FANOUT of \init_calib_complete_reg_rep__6_n_0\ : signal is "50"; + attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__6_n_0\ : signal is "found"; + attribute syn_maxfan of \init_calib_complete_reg_rep__6_n_0\ : signal is "10"; + signal \^init_calib_complete_reg_rep__7_0\ : STD_LOGIC; + signal \^init_calib_complete_reg_rep__8_0\ : STD_LOGIC; + signal \^init_calib_complete_reg_rep__9_0\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_4\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_5\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_20\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22\ : STD_LOGIC; + signal \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4\ : STD_LOGIC; + signal mem_init_done_r : STD_LOGIC; + signal p_1_in : STD_LOGIC; + signal phy_if_reset : STD_LOGIC; + signal \phy_if_reset0__0\ : STD_LOGIC; + signal phy_if_reset_w : STD_LOGIC; + signal pi_calib_done : STD_LOGIC; + signal pi_dqs_found_done_r1 : STD_LOGIC; + signal pi_dqs_found_rank_done : STD_LOGIC; + signal \^pi_fine_dly_dec_done\ : STD_LOGIC; + signal po_enstg2_f : STD_LOGIC_VECTOR ( 2 to 2 ); + signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^po_stg2_wrcal_cnt_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal prech_done : STD_LOGIC; + signal rd_active_r : STD_LOGIC; + signal rd_data_offset_cal_done : STD_LOGIC; + signal rdlvl_last_byte_done : STD_LOGIC; + signal rdlvl_pi_incdec : STD_LOGIC; + signal rdlvl_prech_req : STD_LOGIC; + signal \^rdlvl_stg1_done_int_reg\ : STD_LOGIC; + signal \^rdlvl_stg1_done_r1\ : STD_LOGIC; + signal rdlvl_stg1_rank_done : STD_LOGIC; + signal \^rdlvl_stg1_start_reg\ : STD_LOGIC; + signal reset_if : STD_LOGIC; + signal reset_if_r8_reg_srl8_n_0 : STD_LOGIC; + signal reset_if_r9 : STD_LOGIC; + signal tempmon_pi_f_en_r : STD_LOGIC; + signal \^tempmon_pi_f_inc\ : STD_LOGIC; + signal tempmon_pi_f_inc_r : STD_LOGIC; + signal u_ddr_phy_init_n_15 : STD_LOGIC; + signal u_ddr_phy_init_n_17 : STD_LOGIC; + signal u_ddr_phy_init_n_2 : STD_LOGIC; + signal u_ddr_phy_init_n_278 : STD_LOGIC; + signal u_ddr_phy_init_n_350 : STD_LOGIC; + signal u_ddr_phy_init_n_351 : STD_LOGIC; + signal u_ddr_phy_init_n_352 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_10 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_11 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_13 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_16 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_17 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_18 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_19 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_20 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_4 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_6 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_8 : STD_LOGIC; + signal u_ddr_phy_wrcal_n_9 : STD_LOGIC; + signal wl_sm_start : STD_LOGIC; + signal \^wrcal_done_reg\ : STD_LOGIC; + signal wrcal_prech_req : STD_LOGIC; + signal wrcal_rd_wait : STD_LOGIC; + signal wrcal_resume_w : STD_LOGIC; + signal wrcal_sanity_chk : STD_LOGIC; + signal wrlvl_byte_done : STD_LOGIC; + signal wrlvl_byte_redo : STD_LOGIC; + signal wrlvl_byte_redo_r : STD_LOGIC; + signal wrlvl_done_r1 : STD_LOGIC; + signal wrlvl_final_if_rst : STD_LOGIC; + signal wrlvl_rank_done : STD_LOGIC; + attribute syn_maxfan of \calib_sel_reg[0]\ : label is "10"; + attribute syn_maxfan of \calib_sel_reg[1]\ : label is "10"; + attribute syn_maxfan of \calib_zero_inputs_reg[0]\ : label is "10"; + attribute syn_maxfan of \gen_byte_sel_div2.calib_in_common_reg\ : label is "10"; + attribute syn_maxfan of idelay_inc_r2_reg : label is "30"; + attribute ORIG_CELL_NAME : string; + attribute ORIG_CELL_NAME of init_calib_complete_reg : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED : integer; + attribute IS_FANOUT_CONSTRAINED of init_calib_complete_reg_rep : label is 1; + attribute ORIG_CELL_NAME of init_calib_complete_reg_rep : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__0\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__0\ : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__1\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__1\ : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__2\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__2\ : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__3\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__3\ : label is "init_calib_complete_reg"; + attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__3\ : label is "found"; + attribute syn_maxfan of \init_calib_complete_reg_rep__3\ : label is "10"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__4\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__4\ : label is "init_calib_complete_reg"; + attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__4\ : label is "found"; + attribute syn_maxfan of \init_calib_complete_reg_rep__4\ : label is "10"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__5\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__5\ : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__6\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__6\ : label is "init_calib_complete_reg"; + attribute RTL_MAX_FANOUT of \init_calib_complete_reg_rep__6\ : label is "found"; + attribute syn_maxfan of \init_calib_complete_reg_rep__6\ : label is "10"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__7\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__7\ : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__8\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__8\ : label is "init_calib_complete_reg"; + attribute IS_FANOUT_CONSTRAINED of \init_calib_complete_reg_rep__9\ : label is 1; + attribute ORIG_CELL_NAME of \init_calib_complete_reg_rep__9\ : label is "init_calib_complete_reg"; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair441"; + attribute SOFT_HLUTNM of \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\ : label is "soft_lutpair441"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2\ : label is "soft_lutpair442"; + attribute SOFT_HLUTNM of \phaser_in_gen.phaser_in_i_2__0\ : label is "soft_lutpair442"; + attribute SOFT_HLUTNM of phaser_out_i_2 : label is "soft_lutpair443"; + attribute SOFT_HLUTNM of \phaser_out_i_2__2\ : label is "soft_lutpair443"; + attribute srl_name : string; + attribute srl_name of reset_if_r8_reg_srl8 : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 "; +begin + calib_in_common <= \^calib_in_common\; + calib_sel(1 downto 0) <= \^calib_sel\(1 downto 0); + dqs_po_dec_done <= \^dqs_po_dec_done\; + init_calib_complete_reg_rep_0 <= \^init_calib_complete_reg_rep_0\; + \init_calib_complete_reg_rep__0_0\ <= \^init_calib_complete_reg_rep__0_0\; + \init_calib_complete_reg_rep__1_0\ <= \^init_calib_complete_reg_rep__1_0\; + \init_calib_complete_reg_rep__2_0\ <= \^init_calib_complete_reg_rep__2_0\; + \init_calib_complete_reg_rep__5_0\ <= \^init_calib_complete_reg_rep__5_0\; + \init_calib_complete_reg_rep__7_0\ <= \^init_calib_complete_reg_rep__7_0\; + \init_calib_complete_reg_rep__8_0\ <= \^init_calib_complete_reg_rep__8_0\; + \init_calib_complete_reg_rep__9_0\ <= \^init_calib_complete_reg_rep__9_0\; + pi_fine_dly_dec_done <= \^pi_fine_dly_dec_done\; + \po_stg2_wrcal_cnt_reg[0]\(0) <= \^po_stg2_wrcal_cnt_reg[0]\(0); + rdlvl_stg1_done_int_reg <= \^rdlvl_stg1_done_int_reg\; + rdlvl_stg1_done_r1 <= \^rdlvl_stg1_done_r1\; + rdlvl_stg1_start_reg <= \^rdlvl_stg1_start_reg\; + tempmon_pi_f_inc <= \^tempmon_pi_f_inc\; + wrcal_done_reg <= \^wrcal_done_reg\; +\calib_sel[0]_i_2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\, + I1 => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\, + O => \calib_sel[0]_i_2_n_0\ + ); +\calib_sel_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22\, + Q => \^calib_sel\(0), + R => '0' + ); +\calib_sel_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32\, + Q => \^calib_sel\(1), + R => '0' + ); +\calib_zero_inputs_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => '1', + D => ddr_phy_tempmon_0_n_5, + Q => calib_zero_inputs, + S => \cnt_pwron_ce_r_reg[9]\(1) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => mc_ras_n(2), + I1 => \^init_calib_complete_reg_rep__8_0\, + I2 => out_fifo_4(10), + I3 => out_fifo_5, + O => \cmd_pipe_plus.mc_ras_n_reg[2]\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_13\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => mc_ras_n(0), + I1 => \^init_calib_complete_reg_rep__8_0\, + I2 => out_fifo_4(8), + I3 => out_fifo_5, + O => \cmd_pipe_plus.mc_ras_n_reg[2]\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_35\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => mc_cas_n(2), + I1 => \^init_calib_complete_reg_rep__7_0\, + I2 => out_fifo_4(29), + I3 => out_fifo_5, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_37\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => mc_cas_n(0), + I1 => \^init_calib_complete_reg_rep__7_0\, + I2 => out_fifo_4(27), + I3 => out_fifo_5, + O => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(0) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_47\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => mc_we_n(2), + I1 => \^init_calib_complete_reg_rep__7_0\, + I2 => out_fifo_4(44), + I3 => out_fifo_5, + O => \cmd_pipe_plus.mc_we_n_reg[2]\(2) + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_49\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => mc_we_n(0), + I1 => \^init_calib_complete_reg_rep__7_0\, + I2 => out_fifo_4(42), + I3 => out_fifo_5, + O => \cmd_pipe_plus.mc_we_n_reg[2]\(0) + ); +\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl\: entity work.ddr3_mig_7series_v4_2_ddr_phy_rdlvl + port map ( + CLK => CLK, + COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0), + D(4) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8\, + D(3) => \^rdlvl_stg1_done_int_reg\, + D(2) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\, + D(1) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11\, + D(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12\, + E(0) => rd_active_r, + \FSM_onehot_cal1_state_r_reg[0]_0\(0) => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0), + Q(1) => po_stg2_wrcal_cnt(1), + Q(0) => \^po_stg2_wrcal_cnt_reg[0]\(0), + address_w(0) => address_w(12), + \cal1_cnt_cpt_r_reg[0]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\, + \calib_sel_reg[1]\ => \calib_sel_reg[1]_7\, + \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_8\, + \calib_sel_reg[1]_1\ => \calib_sel_reg[1]_9\, + calib_zero_inputs => calib_zero_inputs, + \cnt_shift_r_reg[0]_0\(0) => \cnt_shift_r_reg[0]\(0), + \done_cnt_reg[1]_0\ => \done_cnt_reg[1]\, + \done_cnt_reg[2]_0\ => \idelay_tap_cnt_r_reg[0][1][4]\, + dqs_po_dec_done_r1_reg_0 => \^dqs_po_dec_done\, + first_rdlvl_pat_r => first_rdlvl_pat_r, + first_wrcal_pat_r => first_wrcal_pat_r, + found_second_edge_r_reg_0 => first_fail_detect_reg, + \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \^wrcal_done_reg\, + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg0\, + idelay_ce_int => idelay_ce_int, + idelay_inc_int => idelay_inc_int, + \idelay_tap_cnt_r_reg[0][0][0]_0\ => u_ddr_phy_wrcal_n_17, + \idelay_tap_cnt_r_reg[0][1][4]_0\(0) => u_ddr_phy_wrcal_n_16, + \init_state_r[4]_i_25\ => u_ddr_phy_init_n_15, + mpr_rdlvl_start_r_reg_0 => u_ddr_phy_init_n_352, + new_cnt_cpt_r_reg_0 => new_cnt_cpt_r_reg, + p_1_in => p_1_in, + pi_calib_done => pi_calib_done, + pi_cnt_dec_reg_0 => pi_cnt_dec_reg, + pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\, + \pi_dqs_found_lanes_r1_reg[3]\ => \^calib_sel\(1), + \pi_dqs_found_lanes_r1_reg[3]_0\ => \^calib_sel\(0), + \pi_dqs_found_lanes_r1_reg[3]_1\ => \^calib_in_common\, + pi_en_stg2_f_reg_0 => pi_en_stg2_f_reg, + pi_fine_dly_dec_done_reg_0 => \^pi_fine_dly_dec_done\, + \pi_rdval_cnt_reg[5]_0\(5 downto 0) => \pi_rdval_cnt_reg[5]\(5 downto 0), + pi_stg2_f_incdec_reg_0 => pi_stg2_f_incdec_reg, + pi_stg2_load_reg_0 => pi_stg2_load_reg, + \pi_stg2_reg_l_reg[5]_0\(5 downto 0) => \pi_stg2_reg_l_reg[5]\(5 downto 0), + po_cnt_dec_reg => \rd_data_edge_detect_r_reg[1]\, + \po_stg2_wrcal_cnt_reg[0]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_29\, + \po_stg2_wrcal_cnt_reg[1]\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\, + prech_done => prech_done, + \rd_mux_sel_r_reg[0]_0\ => \rd_mux_sel_r_reg[0]\, + rdlvl_last_byte_done => rdlvl_last_byte_done, + rdlvl_last_byte_done_int_reg_0 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\, + rdlvl_last_byte_done_int_reg_1 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\, + rdlvl_pi_incdec => rdlvl_pi_incdec, + rdlvl_prech_req => rdlvl_prech_req, + rdlvl_stg1_done_int_reg_0 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\, + rdlvl_stg1_done_int_reg_1 => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26\, + rdlvl_stg1_rank_done => rdlvl_stg1_rank_done, + rdlvl_stg1_start_r_reg_0 => \^rdlvl_stg1_start_reg\, + reset_if => reset_if, + reset_if_r9 => reset_if_r9, + reset_if_reg => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\, + reset_if_reg_0 => \^rdlvl_stg1_done_r1\, + reset_if_reg_1 => \not_empty_wait_cnt_reg[4]\, + samp_edge_cnt0_en_r => samp_edge_cnt0_en_r, + \samp_edge_cnt1_r_reg[0]_0\ => \samp_edge_cnt1_r_reg[0]\, + sr_valid_r_reg_0 => po_en_stg2_f_reg, + store_sr_req_r_reg_0 => store_sr_req_r_reg, + \tap_cnt_cpt_r_reg[5]_0\(0) => \tap_cnt_cpt_r_reg[5]\(0), + tempmon_pi_f_en_r => tempmon_pi_f_en_r, + tempmon_pi_f_inc_r => tempmon_pi_f_inc_r, + \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0) + ); +ddr_phy_tempmon_0: entity work.ddr3_mig_7series_v4_2_ddr_phy_tempmon + port map ( + CLK => CLK, + D(0) => \^rdlvl_stg1_done_int_reg\, + calib_complete => calib_complete, + calib_sel0 => calib_sel0, + \calib_sel_reg[0]\ => \not_empty_wait_cnt_reg[4]\, + ck_addr_cmd_delay_done => ck_addr_cmd_delay_done, + delay_done_r4_reg => ddr_phy_tempmon_0_n_2, + \device_temp_101_reg[11]_0\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0), + \four_dec_min_limit_reg[0]_0\ => \four_dec_min_limit_reg[0]\, + \four_inc_max_limit_reg[2]_0\ => first_fail_detect_reg, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4\, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ => \^wrcal_done_reg\, + init_calib_complete_reg => ddr_phy_tempmon_0_n_5, + mc_ref_zq_wip => mc_ref_zq_wip, + pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\, + pi_f_dec_reg_0 => tempmon_pi_f_dec, + pi_f_dec_reg_1 => pi_dqs_found_done_r1_reg, + pi_f_inc_reg_0 => \^tempmon_pi_f_inc\, + rdlvl_stg1_done_int_reg => ddr_phy_tempmon_0_n_3, + \three_dec_max_limit_reg[0]_0\(1 downto 0) => \cnt_pwron_ce_r_reg[9]\(1 downto 0), + \two_inc_max_limit_reg[11]_0\ => po_en_stg2_f_reg, + wrcal_done_reg => ddr_phy_tempmon_0_n_6 + ); +\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr\: entity work.ddr3_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr + port map ( + A_rst_primitives => A_rst_primitives, + CLK => CLK, + D(0) => \^rdlvl_stg1_done_int_reg\, + Q(0) => fine_adj_state_r(0), + RSTB => RSTB, + calib_in_common4_out => calib_in_common4_out, + calib_sel0 => calib_sel0, + calib_sel15_out => calib_sel15_out, + \calib_sel_reg[1]\ => \calib_sel_reg[1]_5\, + \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_6\, + \calib_sel_reg[1]_1\ => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\, + calib_zero_inputs => calib_zero_inputs, + ck_addr_cmd_delay_done => ck_addr_cmd_delay_done, + ck_po_stg2_f_en => ck_po_stg2_f_en, + ck_po_stg2_f_en_reg_0(0) => idelay_ld_reg(0), + ck_po_stg2_f_indec => ck_po_stg2_f_indec, + ck_po_stg2_f_indec_reg_0 => ck_po_stg2_f_indec_reg, + cmd_delay_start0 => cmd_delay_start0, + ctl_lane_cnt(0) => ctl_lane_cnt(0), + \ctl_lane_cnt_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31\, + detect_pi_found_dqs => detect_pi_found_dqs, + dqs_found_done_r_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_19\, + dqs_found_done_r_reg_1 => dqs_found_done_r_reg, + dqs_found_prech_req => dqs_found_prech_req, + dqs_found_start_r_reg_0 => u_ddr_phy_init_n_351, + dqs_po_stg2_f_incdec => dqs_po_stg2_f_incdec, + fine_adjust_done_r_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_3\, + first_fail_detect_reg_0 => first_fail_detect_reg, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32\, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ => \not_empty_wait_cnt_reg[4]\, + \gen_byte_sel_div2.calib_in_common_reg\ => \gen_byte_sel_div2.calib_in_common_reg_1\, + \gen_byte_sel_div2.calib_in_common_reg_0\ => ddr_phy_tempmon_0_n_6, + \gen_byte_sel_div2.calib_in_common_reg_1\ => ddr_phy_tempmon_0_n_3, + \gen_byte_sel_div2.ctl_lane_sel_reg[0]\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\, + \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0\ => \^pi_fine_dly_dec_done\, + \gen_byte_sel_div2.ctl_lane_sel_reg[0]_1\ => \^dqs_po_dec_done\, + ififo_rst_reg0 => ififo_rst_reg0, + ififo_rst_reg0_1 => ififo_rst_reg0_1, + init_dqsfound_done_r_reg_0 => \rd_data_edge_detect_r_reg[1]\, + ofifo_rst_reg => \^calib_in_common\, + ofifo_rst_reg0 => ofifo_rst_reg0, + ofifo_rst_reg0_2 => ofifo_rst_reg0_2, + ofifo_rst_reg_0 => \^calib_sel\(0), + ofifo_rst_reg_1 => \^calib_sel\(1), + phy_if_reset => phy_if_reset, + pi_calib_done => pi_calib_done, + pi_calib_done_r1_reg => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_15\, + pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\, + pi_dqs_found_done_r1 => pi_dqs_found_done_r1, + pi_dqs_found_done_r1_reg => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_13\, + pi_dqs_found_done_r1_reg_0 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_14\, + pi_dqs_found_done_r1_reg_1 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_16\, + pi_dqs_found_done_r1_reg_2 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_17\, + pi_dqs_found_done_r1_reg_3 => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_18\, + pi_dqs_found_lanes(1 downto 0) => pi_dqs_found_lanes(1 downto 0), + pi_dqs_found_rank_done => pi_dqs_found_rank_done, + \pi_rst_stg1_cal_r_reg[0]_0\ => \idelay_tap_cnt_r_reg[0][1][4]\, + \pi_rst_stg1_cal_reg[0]_0\ => \pi_rst_stg1_cal_reg[0]\, + prech_done => prech_done, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0\ => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0\(5 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0), + rd_data_offset_cal_done => rd_data_offset_cal_done, + rst_dqs_find_i_4_0 => u_ddr_phy_init_n_278, + rst_dqs_find_reg_0(0) => dqs_po_en_stg2_f_reg(0), + \stable_pass_cnt_reg[0]_0\(0) => \dqs_count_r_reg[0]_rep\(0) + ); +\gen_byte_sel_div2.byte_sel_cnt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21\, + Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\, + R => '0' + ); +\gen_byte_sel_div2.byte_sel_cnt_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_20\, + Q => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\, + R => '0' + ); +\gen_byte_sel_div2.calib_in_common_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \gen_byte_sel_div2.calib_in_common_reg_8\, + Q => \^calib_in_common\, + R => \dqs_count_r_reg[0]\ + ); +\gen_byte_sel_div2.ctl_lane_sel_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31\, + Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\, + R => \dqs_count_r_reg[0]\ + ); +\gen_byte_sel_div2.ctl_lane_sel_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_5\, + Q => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\, + R => \dqs_count_r_reg[0]\ + ); +idelay_ce_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_ce_int, + Q => idelay_ce_r1, + R => \done_cnt_reg[1]\ + ); +idelay_ce_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_ce_r1, + Q => idelay_ce, + R => \dqs_count_r_reg[0]\ + ); +idelay_inc_r1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_inc_int, + Q => idelay_inc_r1, + R => \done_cnt_reg[1]\ + ); +idelay_inc_r2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => idelay_inc_r1, + Q => idelay_inc, + R => \dqs_count_r_reg[0]\ + ); +init_calib_complete_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => phy_dout(39), + R => '0' + ); +init_calib_complete_reg_rep: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep_0\, + R => '0' + ); +\init_calib_complete_reg_rep__0\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep__0_0\, + R => '0' + ); +\init_calib_complete_reg_rep__1\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep__1_0\, + R => '0' + ); +\init_calib_complete_reg_rep__2\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep__2_0\, + R => '0' + ); +\init_calib_complete_reg_rep__3\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \init_calib_complete_reg_rep__3_n_0\, + R => '0' + ); +\init_calib_complete_reg_rep__4\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \init_calib_complete_reg_rep__4_n_0\, + R => '0' + ); +\init_calib_complete_reg_rep__5\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep__5_0\, + R => '0' + ); +\init_calib_complete_reg_rep__6\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \init_calib_complete_reg_rep__6_n_0\, + R => '0' + ); +\init_calib_complete_reg_rep__7\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep__7_0\, + R => '0' + ); +\init_calib_complete_reg_rep__8\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep__8_0\, + R => '0' + ); +\init_calib_complete_reg_rep__9\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => calib_complete, + Q => \^init_calib_complete_reg_rep__9_0\, + R => '0' + ); +\input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000AA80" + ) + port map ( + I0 => idelay_ce, + I1 => \^calib_sel\(0), + I2 => \^calib_sel\(1), + I3 => \^calib_in_common\, + I4 => calib_zero_inputs, + O => idelay_ce_r2_reg_0 + ); +\input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"0000CC08" + ) + port map ( + I0 => \^calib_sel\(1), + I1 => idelay_ce, + I2 => \^calib_sel\(0), + I3 => \^calib_in_common\, + I4 => calib_zero_inputs, + O => \calib_sel_reg[1]_3\ + ); +\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay\: entity work.ddr3_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay + port map ( + CLK => CLK, + Q(0) => Q(0), + ck_addr_cmd_delay_done => ck_addr_cmd_delay_done, + cmd_delay_start0 => cmd_delay_start0, + cmd_po_en_stg2_f => cmd_po_en_stg2_f, + cnt_pwron_cke_done_r => cnt_pwron_cke_done_r, + \ctl_lane_cnt_reg[0]_0\(0) => ctl_lane_cnt(0), + \ctl_lane_cnt_reg[1]_0\ => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_5\, + delay_dec_done_reg_0 => \rd_data_edge_detect_r_reg[1]\, + delay_done_r4_reg_0 => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_4\, + \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_3\, + \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\, + p_1_in => p_1_in, + po_cnt_dec_0 => po_cnt_dec_0, + po_en_stg2_f_reg_0 => po_en_stg2_f_reg, + rd_data_offset_cal_done => rd_data_offset_cal_done, + \wait_cnt_r_reg[0]_0\ => \^dqs_po_dec_done\, + \wait_cnt_r_reg[0]_1\ => \^pi_fine_dly_dec_done\, + \wait_cnt_r_reg[0]_2\(0) => \wait_cnt_r_reg[0]\(0) + ); +\mb_wrlvl_inst.u_ddr_phy_wrlvl\: entity work.ddr3_mig_7series_v4_2_ddr_phy_wrlvl + port map ( + CLK => CLK, + DIC(1 downto 0) => DIC(1 downto 0), + \FSM_sequential_wl_state_r[4]_i_13_0\ => u_ddr_phy_wrcal_n_13, + Q(0) => Q(0), + RSTB => RSTB, + SS(0) => SS(0), + calib_sel0 => calib_sel0, + calib_sel15_out => calib_sel15_out, + \calib_sel_reg[0]\ => \calib_sel_reg[0]_0\, + \calib_sel_reg[0]_0\ => \calib_sel[0]_i_2_n_0\, + \calib_sel_reg[0]_1\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1]\, + \calib_sel_reg[0]_2\ => \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0]\, + \calib_sel_reg[0]_3\ => \^pi_fine_dly_dec_done\, + \calib_sel_reg[1]\ => \calib_sel_reg[1]_1\, + \calib_sel_reg[1]_0\ => \calib_sel_reg[1]_4\, + calib_zero_inputs => calib_zero_inputs, + ck_po_stg2_f_indec => ck_po_stg2_f_indec, + cmd_delay_start0 => cmd_delay_start0, + done_dqs_dec237_out => done_dqs_dec237_out, + done_dqs_tap_inc => done_dqs_tap_inc, + \dqs_count_r_reg[0]_0\ => \dqs_count_r_reg[0]\, + \dqs_count_r_reg[0]_rep_0\(0) => \dqs_count_r_reg[0]_rep\(0), + \dqs_count_r_reg[1]_0\(1) => po_stg2_wrcal_cnt(1), + \dqs_count_r_reg[1]_0\(0) => \^po_stg2_wrcal_cnt_reg[0]\(0), + dqs_po_dec_done_reg_0 => \^dqs_po_dec_done\, + dqs_po_en_stg2_f => dqs_po_en_stg2_f, + dqs_po_en_stg2_f_reg_0(0) => dqs_po_en_stg2_f_reg(0), + dqs_po_stg2_f_incdec => dqs_po_stg2_f_incdec, + dqs_wl_po_stg2_c_incdec_reg_0 => dqs_wl_po_stg2_c_incdec_reg, + \final_coarse_tap_reg[0][0]_0\(0) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18\, + \final_coarse_tap_reg[1][0]_0\(0) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17\, + \final_coarse_tap_reg[1][1]_0\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16\, + \gen_byte_sel_div2.byte_sel_cnt_reg[0]\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21\, + \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0\ => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0]\, + \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_29\, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_20\, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0\ => \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1]\, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1\ => ddr_phy_tempmon_0_n_2, + \gen_byte_sel_div2.byte_sel_cnt_reg[1]_2\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28\, + \gen_byte_sel_div2.calib_in_common_reg\ => \gen_byte_sel_div2.calib_in_common_reg_2\, + \gen_byte_sel_div2.calib_in_common_reg_0\ => \gen_byte_sel_div2.calib_in_common_reg_3\, + \gen_byte_sel_div2.calib_in_common_reg_1\ => \gen_byte_sel_div2.calib_in_common_reg_4\, + \gen_byte_sel_div2.calib_in_common_reg_2\ => \gen_byte_sel_div2.calib_in_common_reg_5\, + \gen_byte_sel_div2.calib_in_common_reg_3\ => \gen_byte_sel_div2.calib_in_common_reg_6\, + \gen_byte_sel_div2.ctl_lane_sel_reg[1]\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22\, + \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\(1 downto 0) => \gen_rd[0].rd_data_rise_wl_r_reg[0]\(1 downto 0), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\(0) => \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\(0), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\(0) => \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\(0), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\(0) => \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\(0), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\ => \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\, + \gen_rd[0].rd_data_rise_wl_r_reg[0]_5\(1 downto 0) => \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\(1 downto 0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\(1 downto 0) => \gen_rd[1].rd_data_rise_wl_r_reg[1]\(1 downto 0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\(1 downto 0) => \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\(1 downto 0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\(0) => \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\(0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\(0) => \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\(0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\(0) => \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\(0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\ => \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\, + \gen_rd[1].rd_data_rise_wl_r_reg[1]_6\(1 downto 0) => \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\(1 downto 0), + phaser_out => \^calib_in_common\, + phaser_out_0 => \^calib_sel\(0), + phaser_out_1 => \^calib_sel\(1), + po_cnt_dec_reg_0 => po_cnt_dec_reg, + po_enstg2_f(0) => po_enstg2_f(2), + \po_rdval_cnt_reg[8]_0\(8 downto 0) => \po_rdval_cnt_reg[8]\(8 downto 0), + \rd_data_edge_detect_r_reg[1]_0\ => \rd_data_edge_detect_r_reg[1]\, + \single_rank.done_dqs_dec_reg_0\ => \not_empty_wait_cnt_reg[4]\, + wl_edge_detect_valid_r_reg_0(0) => wl_edge_detect_valid_r_reg(0), + wl_sm_start => wl_sm_start, + wr_level_done_reg_0 => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4\, + wr_level_start_r_reg_0 => u_ddr_phy_init_n_17, + wrlvl_byte_done => wrlvl_byte_done, + wrlvl_byte_redo => wrlvl_byte_redo, + wrlvl_byte_redo_r => wrlvl_byte_redo_r, + wrlvl_rank_done => wrlvl_rank_done, + \wrlvl_redo_corse_inc[1]_i_2_0\ => u_ddr_phy_wrcal_n_6 + ); +mc_read_idle_r_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__9_0\, + O => \init_calib_complete_reg_rep__9_1\ + ); +\mem_reg_0_15_0_5_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__2_0\, + I1 => mc_cas_n(1), + O => phy_dout(37) + ); +\mem_reg_0_15_0_5_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \init_calib_complete_reg_rep__3_n_0\, + I1 => mc_address(11), + O => phy_dout(0) + ); +mem_reg_0_15_0_5_i_3: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__2_0\, + I1 => mc_address(37), + O => phy_dout(1) + ); +\mem_reg_0_15_12_17_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(139), + O => \write_buffer.wr_buf_out_data_reg[127]\(12) + ); +\mem_reg_0_15_12_17_i_2__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__0_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(65), + O => \write_buffer.wr_buf_out_data_reg[117]\(3) + ); +\mem_reg_0_15_12_17_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(137), + O => \write_buffer.wr_buf_out_data_reg[127]\(11) + ); +\mem_reg_0_15_12_17_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(143), + O => \write_buffer.wr_buf_out_data_reg[127]\(14) + ); +\mem_reg_0_15_12_17_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(141), + O => \write_buffer.wr_buf_out_data_reg[127]\(13) + ); +\mem_reg_0_15_12_17_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(26), + O => \write_buffer.wr_buf_out_data_reg[127]\(16) + ); +mem_reg_0_15_18_23_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(112), + O => \write_buffer.wr_buf_out_data_reg[117]\(13) + ); +\mem_reg_0_15_30_35_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(27), + O => \write_buffer.wr_buf_out_data_reg[127]\(21) + ); +\mem_reg_0_15_30_35_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(116), + O => \write_buffer.wr_buf_out_data_reg[117]\(20) + ); +\mem_reg_0_15_30_35_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(130), + O => \write_buffer.wr_buf_out_data_reg[117]\(22) + ); +\mem_reg_0_15_30_35_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(128), + O => \write_buffer.wr_buf_out_data_reg[117]\(21) + ); +mem_reg_0_15_30_35_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(134), + O => \write_buffer.wr_buf_out_data_reg[117]\(24) + ); +mem_reg_0_15_30_35_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(132), + O => \write_buffer.wr_buf_out_data_reg[117]\(23) + ); +\mem_reg_0_15_36_41_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(138), + O => \write_buffer.wr_buf_out_data_reg[117]\(26) + ); +\mem_reg_0_15_36_41_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(136), + O => \write_buffer.wr_buf_out_data_reg[117]\(25) + ); +\mem_reg_0_15_36_41_i_3__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(142), + O => \write_buffer.wr_buf_out_data_reg[117]\(28) + ); +\mem_reg_0_15_36_41_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(140), + O => \write_buffer.wr_buf_out_data_reg[117]\(27) + ); +mem_reg_0_15_36_41_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(23), + O => \write_buffer.wr_buf_out_data_reg[117]\(29) + ); +\mem_reg_0_15_36_41_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(30), + O => \write_buffer.wr_buf_out_data_reg[127]\(28) + ); +\mem_reg_0_15_48_53_i_1__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(18), + O => \write_buffer.wr_buf_out_data_reg[117]\(36) + ); +mem_reg_0_15_48_53_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \init_calib_complete_reg_rep__3_n_0\, + I1 => mc_address(14), + O => phy_dout(26) + ); +mem_reg_0_15_54_59_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__2_0\, + I1 => mc_address(40), + O => phy_dout(27) + ); +\mem_reg_0_15_54_59_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(124), + O => \write_buffer.wr_buf_out_data_reg[127]\(39) + ); +\mem_reg_0_15_54_59_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(22), + O => \write_buffer.wr_buf_out_data_reg[117]\(42) + ); +\mem_reg_0_15_60_65_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__0_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(73), + O => \write_buffer.wr_buf_out_data_reg[127]\(43) + ); +mem_reg_0_15_60_65_i_5: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(19), + O => \write_buffer.wr_buf_out_data_reg[117]\(47) + ); +\mem_reg_0_15_66_71_i_4__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__0_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(77), + O => \write_buffer.wr_buf_out_data_reg[127]\(50) + ); +\mem_reg_0_15_6_11_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(120), + O => \write_buffer.wr_buf_out_data_reg[127]\(6) + ); +\mem_reg_0_15_6_11_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(131), + O => \write_buffer.wr_buf_out_data_reg[127]\(8) + ); +\mem_reg_0_15_6_11_i_4__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(129), + O => \write_buffer.wr_buf_out_data_reg[127]\(7) + ); +\mem_reg_0_15_6_11_i_5__0\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(135), + O => \write_buffer.wr_buf_out_data_reg[127]\(10) + ); +mem_reg_0_15_6_11_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(133), + O => \write_buffer.wr_buf_out_data_reg[127]\(9) + ); +mem_reg_0_15_72_77_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \init_calib_complete_reg_rep__3_n_0\, + I1 => mc_address(13), + O => phy_dout(36) + ); +\mem_reg_0_15_72_77_i_1__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__1_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(31), + O => \write_buffer.wr_buf_out_data_reg[127]\(54) + ); +mem_reg_0_15_72_77_i_2: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__2_0\, + I1 => mc_address(39), + O => phy_dout(38) + ); +mem_reg_0_15_72_77_i_6: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__0_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(69), + O => \write_buffer.wr_buf_out_data_reg[117]\(56) + ); +out_fifo_i_10: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(112), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(15), + I3 => out_fifo_0, + O => D2(7) + ); +\out_fifo_i_10__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(143), + I2 => out_fifo_1(15), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(7) + ); +\out_fifo_i_11__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(141), + I2 => out_fifo_1(14), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(6) + ); +\out_fifo_i_12__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(139), + I2 => out_fifo_1(13), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(5) + ); +\out_fifo_i_13__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(137), + I2 => out_fifo_1(12), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(4) + ); +\out_fifo_i_14__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(135), + I2 => out_fifo_1(11), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(3) + ); +\out_fifo_i_15__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(133), + I2 => out_fifo_1(10), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(2) + ); +\out_fifo_i_16__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(131), + I2 => out_fifo_1(9), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(1) + ); +out_fifo_i_17: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(0), + I1 => \^init_calib_complete_reg_rep__7_0\, + I2 => out_fifo(8), + I3 => out_fifo_0, + O => D2(0) + ); +\out_fifo_i_17__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \^init_calib_complete_reg_rep__5_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(129), + I2 => out_fifo_1(8), + I3 => out_fifo_2, + O => \init_calib_complete_reg_rep__5_1\(0) + ); +out_fifo_i_18: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(116), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(23), + I3 => out_fifo_0, + O => D3(7) + ); +\out_fifo_i_21__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(74), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(20), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[122]\(4) + ); +\out_fifo_i_22__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(58), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(19), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[122]\(3) + ); +\out_fifo_i_24__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(26), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(17), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[122]\(1) + ); +out_fifo_i_25: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(4), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(16), + I3 => out_fifo_0, + O => D3(0) + ); +out_fifo_i_26: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(142), + I2 => out_fifo(31), + I3 => out_fifo_0, + O => D4(7) + ); +out_fifo_i_27: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(140), + I2 => out_fifo(30), + I3 => out_fifo_0, + O => D4(6) + ); +out_fifo_i_28: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(138), + I2 => out_fifo(29), + I3 => out_fifo_0, + O => D4(5) + ); +\out_fifo_i_28__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(91), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(29), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[123]\(5) + ); +out_fifo_i_29: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(136), + I2 => out_fifo(28), + I3 => out_fifo_0, + O => D4(4) + ); +\out_fifo_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(120), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(7), + I3 => out_fifo_2, + O => D0(7) + ); +out_fifo_i_30: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(134), + I2 => out_fifo(27), + I3 => out_fifo_0, + O => D4(3) + ); +out_fifo_i_31: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(132), + I2 => out_fifo(26), + I3 => out_fifo_0, + O => D4(2) + ); +out_fifo_i_32: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(130), + I2 => out_fifo(25), + I3 => out_fifo_0, + O => D4(1) + ); +\out_fifo_i_32__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(27), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(25), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[123]\(1) + ); +out_fifo_i_33: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \init_calib_complete_reg_rep__6_n_0\, + I1 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(128), + I2 => out_fifo(24), + I3 => out_fifo_0, + O => D4(0) + ); +\out_fifo_i_33__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(11), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(24), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[123]\(0) + ); +out_fifo_i_36: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(87), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(37), + I3 => out_fifo_0, + O => D5(5) + ); +\out_fifo_i_37__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(78), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(36), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[126]\(4) + ); +\out_fifo_i_38__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(62), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(35), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[126]\(3) + ); +out_fifo_i_40: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(23), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(33), + I3 => out_fifo_0, + O => D5(1) + ); +\out_fifo_i_40__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(30), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(33), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[126]\(1) + ); +out_fifo_i_41: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(7), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(32), + I3 => out_fifo_0, + O => D5(0) + ); +\out_fifo_i_42__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(124), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(47), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[124]\(7) + ); +out_fifo_i_45: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(66), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(44), + I3 => out_fifo_0, + O => D6(4) + ); +out_fifo_i_46: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(50), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(43), + I3 => out_fifo_0, + O => D6(3) + ); +out_fifo_i_48: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(18), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(41), + I3 => out_fifo_0, + O => D6(1) + ); +\out_fifo_i_49__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(12), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(40), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[124]\(0) + ); +out_fifo_i_5: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(65), + I1 => \^init_calib_complete_reg_rep__7_0\, + I2 => out_fifo(4), + I3 => out_fifo_0, + O => D1(4) + ); +out_fifo_i_53: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(70), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(52), + I3 => out_fifo_0, + O => D7(4) + ); +\out_fifo_i_53__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(73), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(52), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[121]\(4) + ); +out_fifo_i_54: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(54), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(51), + I3 => out_fifo_0, + O => D7(3) + ); +\out_fifo_i_55__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(41), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(50), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[121]\(2) + ); +out_fifo_i_56: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(22), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(49), + I3 => out_fifo_0, + O => D7(1) + ); +out_fifo_i_60: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(83), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo(61), + I3 => out_fifo_0, + O => D8(5) + ); +\out_fifo_i_61__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(77), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(60), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[125]\(4) + ); +\out_fifo_i_63__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(45), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(58), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[125]\(2) + ); +out_fifo_i_64: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(19), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(57), + I3 => out_fifo_0, + O => D8(1) + ); +out_fifo_i_65: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(3), + I1 => \init_calib_complete_reg_rep__6_n_0\, + I2 => out_fifo(56), + I3 => out_fifo_0, + O => D8(0) + ); +\out_fifo_i_68__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(95), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(69), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(5) + ); +out_fifo_i_69: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(69), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo(68), + I3 => out_fifo_0, + O => D9(4) + ); +out_fifo_i_7: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(33), + I1 => \^init_calib_complete_reg_rep__7_0\, + I2 => out_fifo(2), + I3 => out_fifo_0, + O => D1(2) + ); +out_fifo_i_71: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(37), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo(66), + I3 => out_fifo_0, + O => D9(2) + ); +\out_fifo_i_72__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"88F0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(31), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(65), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(1) + ); +\out_fifo_i_73__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(15), + I1 => \init_calib_complete_reg_rep__4_n_0\, + I2 => out_fifo_1(64), + I3 => out_fifo_2, + O => \write_buffer.wr_buf_out_data_reg[127]_0\(0) + ); +\out_fifo_i_9__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"BBF0" + ) + port map ( + I0 => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(8), + I1 => \^init_calib_complete_reg_rep__5_0\, + I2 => out_fifo_1(0), + I3 => out_fifo_2, + O => D0(0) + ); +\phaser_in_gen.phaser_in_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00F8" + ) + port map ( + I0 => \^calib_sel\(1), + I1 => \^calib_sel\(0), + I2 => \^calib_in_common\, + I3 => calib_zero_inputs, + O => \calib_sel_reg[1]_0\ + ); +\phaser_in_gen.phaser_in_i_2__0\: unisim.vcomponents.LUT4 + generic map( + INIT => X"00F2" + ) + port map ( + I0 => \^calib_sel\(1), + I1 => \^calib_sel\(0), + I2 => \^calib_in_common\, + I3 => calib_zero_inputs, + O => \calib_sel_reg[1]_2\ + ); +phaser_out_i_2: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \^calib_in_common\, + I1 => \^calib_sel\(1), + I2 => \^calib_sel\(0), + I3 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg_0\ + ); +\phaser_out_i_2__2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0004" + ) + port map ( + I0 => \^calib_in_common\, + I1 => \^calib_sel\(0), + I2 => \^calib_sel\(1), + I3 => calib_zero_inputs, + O => \gen_byte_sel_div2.calib_in_common_reg_7\ + ); +phy_if_reset0: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => phy_if_reset_w, + I1 => reset_if, + I2 => wrlvl_final_if_rst, + O => \phy_if_reset0__0\ + ); +phy_if_reset_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_if_reset0__0\, + Q => phy_if_reset, + R => '0' + ); +po_en_stg2_f0: unisim.vcomponents.LUT3 + generic map( + INIT => X"FE" + ) + port map ( + I0 => dqs_po_en_stg2_f, + I1 => cmd_po_en_stg2_f, + I2 => ck_po_stg2_f_en, + O => po_enstg2_f(2) + ); +reset_if_r8_reg_srl8: unisim.vcomponents.SRL16E + port map ( + A0 => '1', + A1 => '1', + A2 => '1', + A3 => '0', + CE => '1', + CLK => CLK, + D => reset_if, + Q => reset_if_r8_reg_srl8_n_0 + ); +reset_if_r9_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => reset_if_r8_reg_srl8_n_0, + Q => reset_if_r9, + R => '0' + ); +reset_if_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30\, + Q => reset_if, + R => '0' + ); +tempmon_pi_f_en_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => tempmon_sel_pi_incdec, + Q => tempmon_pi_f_en_r, + R => \dqs_count_r_reg[0]\ + ); +tempmon_pi_f_inc_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \^tempmon_pi_f_inc\, + Q => tempmon_pi_f_inc_r, + R => \done_cnt_reg[1]\ + ); +u_ddr_phy_init: entity work.ddr3_mig_7series_v4_2_ddr_phy_init + port map ( + CLK => CLK, + D(4) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8\, + D(3) => \^rdlvl_stg1_done_int_reg\, + D(2) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10\, + D(1) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11\, + D(0) => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12\, + D0(5 downto 0) => D0(6 downto 1), + D1(5 downto 3) => D1(7 downto 5), + D1(2) => D1(3), + D1(1 downto 0) => D1(1 downto 0), + D2(5 downto 0) => D2(6 downto 1), + D3(5 downto 0) => D3(6 downto 1), + D5(4 downto 3) => D5(7 downto 6), + D5(2 downto 0) => D5(4 downto 2), + D6(4 downto 2) => D6(7 downto 5), + D6(1) => D6(2), + D6(0) => D6(0), + D7(4 downto 2) => D7(7 downto 5), + D7(1) => D7(2), + D7(0) => D7(0), + D8(4 downto 3) => D8(7 downto 6), + D8(2 downto 0) => D8(4 downto 2), + D9(5 downto 3) => D9(7 downto 5), + D9(2) => D9(3), + D9(1 downto 0) => D9(1 downto 0), + E(0) => E(0), + Q(0) => Q(0), + \back_to_back_reads_4_1.num_reads_reg[1]_0\ => \idelay_tap_cnt_r_reg[0][1][4]\, + burst_addr_r_reg_0 => \^wrcal_done_reg\, + calib_complete => calib_complete, + calib_ctl_wren_reg_0 => calib_cmd_wren, + calib_ctl_wren_reg_1 => calib_ctl_wren_reg, + \calib_data_offset_0_reg[0]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_18\, + \calib_data_offset_0_reg[1]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_17\, + \calib_data_offset_0_reg[2]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_16\, + \calib_data_offset_0_reg[3]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_15\, + \calib_data_offset_0_reg[4]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_14\, + \calib_data_offset_0_reg[5]_0\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_13\, + \calib_seq_reg[1]_0\(10 downto 0) => D(10 downto 0), + calib_wrdata_en => calib_wrdata_en, + ck_addr_cmd_delay_done => ck_addr_cmd_delay_done, + \cmd_pipe_plus.mc_cke_reg[3]\(7 downto 0) => \cmd_pipe_plus.mc_cke_reg[3]\(7 downto 0), + \cmd_pipe_plus.mc_odt_reg[0]\(3 downto 0) => \cmd_pipe_plus.mc_odt_reg[0]\(3 downto 0), + \cmd_pipe_plus.mc_ras_n_reg[1]\(0) => \cmd_pipe_plus.mc_ras_n_reg[2]\(1), + \cmd_pipe_plus.mc_we_n_reg[1]\(32 downto 0) => \cmd_pipe_plus.mc_we_n_reg[1]\(32 downto 0), + \cmd_pipe_plus.mc_we_n_reg[1]_0\(0) => \cmd_pipe_plus.mc_we_n_reg[2]\(1), + \cnt_pwron_ce_r_reg[9]_0\(1 downto 0) => \cnt_pwron_ce_r_reg[9]\(1 downto 0), + cnt_pwron_cke_done_r => cnt_pwron_cke_done_r, + complex_row0_rd_done_reg_0 => complex_row0_rd_done_reg, + \complex_wait_cnt_reg[3]_0\ => \not_empty_wait_cnt_reg[4]\, + ddr3_lm_done_r => ddr3_lm_done_r, + \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ => \^init_calib_complete_reg_rep__1_0\, + \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ => \^init_calib_complete_reg_rep__2_0\, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ => \^init_calib_complete_reg_rep__0_0\, + detect_pi_found_dqs => detect_pi_found_dqs, + detect_pi_found_dqs_reg_0 => u_ddr_phy_init_n_278, + done_dqs_tap_inc => done_dqs_tap_inc, + dqs_found_prech_req => dqs_found_prech_req, + \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0\(0) => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0), + first_rdlvl_pat_r => first_rdlvl_pat_r, + first_wrcal_pat_r => first_wrcal_pat_r, + \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_1\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26\, + \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(4 downto 1) => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(6 downto 3), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0\(0) => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(1), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_1\ => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_19\, + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0\(3 downto 0) => \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]\(3 downto 0), + in0 => in0, + \init_state_r[0]_i_15_0\ => u_ddr_phy_wrcal_n_19, + \init_state_r[0]_i_3_0\ => \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_4\, + \init_state_r[0]_i_5_0\ => u_ddr_phy_wrcal_n_9, + \init_state_r[1]_i_3_0\ => u_ddr_phy_wrcal_n_18, + \init_state_r[1]_i_3_1\ => u_ddr_phy_wrcal_n_10, + \init_state_r[1]_i_4_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27\, + \init_state_r[2]_i_5_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22\, + \init_state_r[2]_i_7_0\ => u_ddr_phy_wrcal_n_8, + \init_state_r[2]_i_7_1\ => u_ddr_phy_wrcal_n_20, + \init_state_r[4]_i_4_0\ => u_ddr_phy_wrcal_n_11, + \init_state_r[4]_i_7_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23\, + \init_state_r_reg[2]_0\(0) => address_w(12), + \init_state_r_reg[4]_0\ => u_ddr_phy_wrcal_n_4, + mc_address(34) => mc_address(38), + mc_address(33 downto 12) => mc_address(36 downto 15), + mc_address(11) => mc_address(12), + mc_address(10 downto 0) => mc_address(10 downto 0), + mc_bank(8 downto 0) => mc_bank(8 downto 0), + mc_cas_n(0) => mc_cas_n(1), + mc_cke(0) => mc_cke(0), + mc_cmd(1 downto 0) => mc_cmd(1 downto 0), + mc_data_offset(0) => mc_data_offset(0), + mc_odt(0) => mc_odt(0), + mc_ras_n(0) => mc_ras_n(1), + mc_we_n(0) => mc_we_n(1), + mc_wrdata_en => mc_wrdata_en, + mem_init_done_r => mem_init_done_r, + mem_out(31 downto 0) => mem_out(31 downto 0), + mpr_rdlvl_start_reg_0 => u_ddr_phy_init_n_352, + mux_cmd_wren => mux_cmd_wren, + mux_reset_n => mux_reset_n, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[3]\ => \my_empty_reg[3]\, + \my_empty_reg[3]_0\ => \my_empty_reg[3]_0\, + \my_empty_reg[3]_1\ => \my_empty_reg[3]_1\, + \my_empty_reg[5]\(0) => \my_empty_reg[5]\(0), + \my_empty_reg[5]_0\(0) => \my_empty_reg[5]_0\(0), + \one_rank.stg1_wr_done_reg_0\ => u_ddr_phy_init_n_15, + \out\ => \out\, + out_fifo(87 downto 85) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(127 downto 125), + out_fifo(84 downto 82) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(123 downto 121), + out_fifo(81 downto 79) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(119 downto 117), + out_fifo(78 downto 76) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(115 downto 113), + out_fifo(75 downto 60) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(111 downto 96), + out_fifo(59 downto 57) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(94 downto 92), + out_fifo(56 downto 54) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(90 downto 88), + out_fifo(53 downto 51) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(86 downto 84), + out_fifo(50 downto 47) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(82 downto 79), + out_fifo(46 downto 45) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(76 downto 75), + out_fifo(44 downto 43) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(72 downto 71), + out_fifo(42 downto 41) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(68 downto 67), + out_fifo(40 downto 39) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(64 downto 63), + out_fifo(38 downto 36) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(61 downto 59), + out_fifo(35 downto 33) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(57 downto 55), + out_fifo(32 downto 30) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(53 downto 51), + out_fifo(29 downto 26) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(49 downto 46), + out_fifo(25 downto 23) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(44 downto 42), + out_fifo(22 downto 20) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(40 downto 38), + out_fifo(19 downto 17) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(36 downto 34), + out_fifo(16) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(32), + out_fifo(15 downto 14) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(29 downto 28), + out_fifo(13 downto 12) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(25 downto 24), + out_fifo(11 downto 10) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(21 downto 20), + out_fifo(9 downto 8) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(17 downto 16), + out_fifo(7 downto 6) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(14 downto 13), + out_fifo(5 downto 4) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(10 downto 9), + out_fifo(3 downto 2) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(6 downto 5), + out_fifo(1 downto 0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(2 downto 1), + out_fifo_0 => \^init_calib_complete_reg_rep__7_0\, + out_fifo_1(43 downto 41) => out_fifo(71 downto 69), + out_fifo_1(40) => out_fifo(67), + out_fifo_1(39 downto 36) => out_fifo(65 downto 62), + out_fifo_1(35 downto 33) => out_fifo(60 downto 58), + out_fifo_1(32 downto 30) => out_fifo(55 downto 53), + out_fifo_1(29) => out_fifo(50), + out_fifo_1(28 downto 25) => out_fifo(48 downto 45), + out_fifo_1(24) => out_fifo(42), + out_fifo_1(23 downto 21) => out_fifo(40 downto 38), + out_fifo_1(20 downto 18) => out_fifo(36 downto 34), + out_fifo_1(17 downto 12) => out_fifo(22 downto 17), + out_fifo_1(11 downto 6) => out_fifo(14 downto 9), + out_fifo_1(5 downto 3) => out_fifo(7 downto 5), + out_fifo_1(2) => out_fifo(3), + out_fifo_1(1 downto 0) => out_fifo(1 downto 0), + out_fifo_10 => \^init_calib_complete_reg_rep__9_0\, + out_fifo_11 => out_fifo_3, + out_fifo_2 => out_fifo_0, + out_fifo_3 => \init_calib_complete_reg_rep__6_n_0\, + out_fifo_4 => \^init_calib_complete_reg_rep__5_0\, + out_fifo_5(43 downto 42) => out_fifo_1(71 downto 70), + out_fifo_5(41 downto 39) => out_fifo_1(68 downto 66), + out_fifo_5(38 downto 36) => out_fifo_1(63 downto 61), + out_fifo_5(35) => out_fifo_1(59), + out_fifo_5(34 downto 30) => out_fifo_1(57 downto 53), + out_fifo_5(29) => out_fifo_1(51), + out_fifo_5(28 downto 27) => out_fifo_1(49 downto 48), + out_fifo_5(26 downto 21) => out_fifo_1(46 downto 41), + out_fifo_5(20 downto 18) => out_fifo_1(39 downto 37), + out_fifo_5(17) => out_fifo_1(34), + out_fifo_5(16 downto 14) => out_fifo_1(32 downto 30), + out_fifo_5(13 downto 11) => out_fifo_1(28 downto 26), + out_fifo_5(10 downto 8) => out_fifo_1(23 downto 21), + out_fifo_5(7) => out_fifo_1(18), + out_fifo_5(6) => out_fifo_1(16), + out_fifo_5(5 downto 0) => out_fifo_1(6 downto 1), + out_fifo_6 => out_fifo_2, + out_fifo_7 => \^init_calib_complete_reg_rep__8_0\, + out_fifo_8(38) => out_fifo_4(43), + out_fifo_8(37 downto 26) => out_fifo_4(41 downto 30), + out_fifo_8(25) => out_fifo_4(28), + out_fifo_8(24 downto 9) => out_fifo_4(26 downto 11), + out_fifo_8(8) => out_fifo_4(9), + out_fifo_8(7 downto 0) => out_fifo_4(7 downto 0), + out_fifo_9 => out_fifo_5, + \phy_ctl_wd_i1_reg[17]\ => \phy_ctl_wd_i1_reg[17]\, + \phy_ctl_wd_i1_reg[18]\ => \phy_ctl_wd_i1_reg[18]\, + \phy_ctl_wd_i1_reg[19]\ => \phy_ctl_wd_i1_reg[19]\, + \phy_ctl_wd_i1_reg[21]\ => \phy_ctl_wd_i1_reg[21]\, + \phy_ctl_wd_i1_reg[22]\ => \init_calib_complete_reg_rep__3_n_0\, + \phy_ctl_wd_i1_reg[22]_0\ => \phy_ctl_wd_i1_reg[22]\, + phy_ctl_wr_i1_reg => \init_calib_complete_reg_rep__4_n_0\, + phy_dout(31 downto 24) => phy_dout(35 downto 28), + phy_dout(23 downto 0) => phy_dout(25 downto 2), + phy_read_calib => phy_read_calib, + phy_write_calib => phy_write_calib, + pi_calib_done => pi_calib_done, + pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\, + pi_dqs_found_done_r1 => pi_dqs_found_done_r1, + pi_dqs_found_done_r1_reg_0 => pi_dqs_found_done_r1_reg, + pi_dqs_found_rank_done => pi_dqs_found_rank_done, + pi_dqs_found_start_reg_0 => u_ddr_phy_init_n_351, + prbs_rdlvl_done_pulse0 => prbs_rdlvl_done_pulse0, + prbs_rdlvl_done_pulse_reg_0 => prbs_rdlvl_done_pulse_reg, + prech_done => prech_done, + prech_req_posedge_r_reg_0 => u_ddr_phy_init_n_2, + rdlvl_last_byte_done => rdlvl_last_byte_done, + rdlvl_pi_incdec => rdlvl_pi_incdec, + rdlvl_prech_req => rdlvl_prech_req, + rdlvl_stg1_done_r1_reg_0 => \^rdlvl_stg1_done_r1\, + rdlvl_stg1_rank_done => rdlvl_stg1_rank_done, + rdlvl_stg1_start_reg_0 => \^rdlvl_stg1_start_reg\, + rst_dqs_find_i_12(0) => fine_adj_state_r(0), + wl_sm_start => wl_sm_start, + \wr_en_inferred__0_i_1_0\ => \wr_en_inferred__0_i_1\, + \wr_en_inferred__0_i_1__0_0\ => \wr_en_inferred__0_i_1__0\, + \wr_en_inferred__0_i_1__1_0\ => \wr_en_inferred__0_i_1__1\, + wr_lvl_start_reg_0 => u_ddr_phy_init_n_17, + \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\, + \wr_ptr_timing_reg[0]_0\ => \^init_calib_complete_reg_rep_0\, + \wr_ptr_timing_reg[0]_1\ => \wr_ptr_timing_reg[0]_0\, + \wr_ptr_timing_reg[0]_2\ => \wr_ptr_timing_reg[0]_1\, + wrcal_prech_req => wrcal_prech_req, + wrcal_rd_wait => wrcal_rd_wait, + wrcal_resume_w => wrcal_resume_w, + wrcal_sanity_chk => wrcal_sanity_chk, + wrcal_start_reg_0 => u_ddr_phy_init_n_350, + \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0\(0) => \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]\(0), + \write_buffer.wr_buf_out_data_reg[108]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[124]\(6 downto 1), + \write_buffer.wr_buf_out_data_reg[117]\(43 downto 41) => \write_buffer.wr_buf_out_data_reg[117]\(59 downto 57), + \write_buffer.wr_buf_out_data_reg[117]\(40 downto 33) => \write_buffer.wr_buf_out_data_reg[117]\(55 downto 48), + \write_buffer.wr_buf_out_data_reg[117]\(32 downto 29) => \write_buffer.wr_buf_out_data_reg[117]\(46 downto 43), + \write_buffer.wr_buf_out_data_reg[117]\(28 downto 24) => \write_buffer.wr_buf_out_data_reg[117]\(41 downto 37), + \write_buffer.wr_buf_out_data_reg[117]\(23 downto 18) => \write_buffer.wr_buf_out_data_reg[117]\(35 downto 30), + \write_buffer.wr_buf_out_data_reg[117]\(17 downto 12) => \write_buffer.wr_buf_out_data_reg[117]\(19 downto 14), + \write_buffer.wr_buf_out_data_reg[117]\(11 downto 3) => \write_buffer.wr_buf_out_data_reg[117]\(12 downto 4), + \write_buffer.wr_buf_out_data_reg[117]\(2 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(2 downto 0), + \write_buffer.wr_buf_out_data_reg[121]\(5 downto 3) => \write_buffer.wr_buf_out_data_reg[121]\(7 downto 5), + \write_buffer.wr_buf_out_data_reg[121]\(2) => \write_buffer.wr_buf_out_data_reg[121]\(3), + \write_buffer.wr_buf_out_data_reg[121]\(1 downto 0) => \write_buffer.wr_buf_out_data_reg[121]\(1 downto 0), + \write_buffer.wr_buf_out_data_reg[122]\(4 downto 2) => \write_buffer.wr_buf_out_data_reg[122]\(7 downto 5), + \write_buffer.wr_buf_out_data_reg[122]\(1) => \write_buffer.wr_buf_out_data_reg[122]\(2), + \write_buffer.wr_buf_out_data_reg[122]\(0) => \write_buffer.wr_buf_out_data_reg[122]\(0), + \write_buffer.wr_buf_out_data_reg[123]\(4 downto 3) => \write_buffer.wr_buf_out_data_reg[123]\(7 downto 6), + \write_buffer.wr_buf_out_data_reg[123]\(2 downto 0) => \write_buffer.wr_buf_out_data_reg[123]\(4 downto 2), + \write_buffer.wr_buf_out_data_reg[125]\(5 downto 3) => \write_buffer.wr_buf_out_data_reg[125]\(7 downto 5), + \write_buffer.wr_buf_out_data_reg[125]\(2) => \write_buffer.wr_buf_out_data_reg[125]\(3), + \write_buffer.wr_buf_out_data_reg[125]\(1 downto 0) => \write_buffer.wr_buf_out_data_reg[125]\(1 downto 0), + \write_buffer.wr_buf_out_data_reg[126]\(4 downto 2) => \write_buffer.wr_buf_out_data_reg[126]\(7 downto 5), + \write_buffer.wr_buf_out_data_reg[126]\(1) => \write_buffer.wr_buf_out_data_reg[126]\(2), + \write_buffer.wr_buf_out_data_reg[126]\(0) => \write_buffer.wr_buf_out_data_reg[126]\(0), + \write_buffer.wr_buf_out_data_reg[127]\(43 downto 39) => \write_buffer.wr_buf_out_data_reg[127]\(59 downto 55), + \write_buffer.wr_buf_out_data_reg[127]\(38 downto 36) => \write_buffer.wr_buf_out_data_reg[127]\(53 downto 51), + \write_buffer.wr_buf_out_data_reg[127]\(35 downto 30) => \write_buffer.wr_buf_out_data_reg[127]\(49 downto 44), + \write_buffer.wr_buf_out_data_reg[127]\(29 downto 27) => \write_buffer.wr_buf_out_data_reg[127]\(42 downto 40), + \write_buffer.wr_buf_out_data_reg[127]\(26 downto 17) => \write_buffer.wr_buf_out_data_reg[127]\(38 downto 29), + \write_buffer.wr_buf_out_data_reg[127]\(16 downto 11) => \write_buffer.wr_buf_out_data_reg[127]\(27 downto 22), + \write_buffer.wr_buf_out_data_reg[127]\(10 downto 7) => \write_buffer.wr_buf_out_data_reg[127]\(20 downto 17), + \write_buffer.wr_buf_out_data_reg[127]\(6) => \write_buffer.wr_buf_out_data_reg[127]\(15), + \write_buffer.wr_buf_out_data_reg[127]\(5 downto 0) => \write_buffer.wr_buf_out_data_reg[127]\(5 downto 0), + \write_buffer.wr_buf_out_data_reg[127]_0\(4 downto 3) => \write_buffer.wr_buf_out_data_reg[127]_0\(7 downto 6), + \write_buffer.wr_buf_out_data_reg[127]_0\(2 downto 0) => \write_buffer.wr_buf_out_data_reg[127]_0\(4 downto 2), + wrlvl_byte_redo => wrlvl_byte_redo, + wrlvl_done_r1 => wrlvl_done_r1, + wrlvl_done_r_reg_0 => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4\, + wrlvl_final_if_rst => wrlvl_final_if_rst, + wrlvl_rank_done => wrlvl_rank_done + ); +u_ddr_phy_wrcal: entity work.ddr3_mig_7series_v4_2_ddr_phy_wrcal + port map ( + CLK => CLK, + D(0) => \^rdlvl_stg1_done_int_reg\, + E(0) => rd_active_r, + \FSM_sequential_wl_state_r[4]_i_18\ => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16\, + \FSM_sequential_wl_state_r[4]_i_18_0\(0) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18\, + \FSM_sequential_wl_state_r[4]_i_18_1\(0) => \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17\, + LD0 => LD0, + LD0_0 => LD0_0, + Q(1) => po_stg2_wrcal_cnt(1), + Q(0) => \^po_stg2_wrcal_cnt_reg[0]\(0), + SR(0) => SR(0), + cal1_dq_idel_ce_reg => u_ddr_phy_wrcal_n_17, + \cal2_state_r_reg[0]_0\ => u_ddr_phy_init_n_350, + calib_zero_inputs => calib_zero_inputs, + ddr3_lm_done_r => ddr3_lm_done_r, + done_dqs_dec237_out => done_dqs_dec237_out, + early1_data_reg_0 => u_ddr_phy_wrcal_n_6, + early2_data_reg_0 => u_ddr_phy_wrcal_n_13, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + idelay_ce_int => idelay_ce_int, + idelay_ld_reg_0(0) => idelay_ld_reg(0), + idelay_ld_rst => idelay_ld_rst, + \idelay_tap_cnt_r_reg[0][1][4]\ => \idelay_tap_cnt_r_reg[0][1][4]\, + \idelay_tap_cnt_r_reg[0][1][4]_0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25\, + \init_state_r[4]_i_15\ => u_ddr_phy_init_n_2, + \input_[9].iserdes_dq_.idelay_dq.idelaye2\ => \^calib_in_common\, + \input_[9].iserdes_dq_.idelay_dq.idelaye2_0\ => \^calib_sel\(0), + \input_[9].iserdes_dq_.idelay_dq.idelaye2_1\ => \^calib_sel\(1), + mem_init_done_r => mem_init_done_r, + \not_empty_wait_cnt_reg[4]_0\ => \not_empty_wait_cnt_reg[4]\, + phy_if_reset_w => phy_if_reset_w, + phy_rddata_en => phy_rddata_en, + pi_dqs_found_done => \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2\, + prech_done => prech_done, + rdlvl_stg1_done_int_reg => u_ddr_phy_wrcal_n_18, + rdlvl_stg1_done_int_reg_0 => u_ddr_phy_wrcal_n_19, + \rstdiv0_sync_r1_reg_rep__15\(0) => u_ddr_phy_wrcal_n_16, + wrcal_done_reg_0 => \^wrcal_done_reg\, + wrcal_done_reg_1 => u_ddr_phy_wrcal_n_10, + wrcal_prech_req => wrcal_prech_req, + wrcal_rd_wait => wrcal_rd_wait, + wrcal_resume_w => wrcal_resume_w, + wrcal_sanity_chk => wrcal_sanity_chk, + wrcal_sanity_chk_done_reg_0 => u_ddr_phy_wrcal_n_4, + wrcal_sanity_chk_done_reg_1 => u_ddr_phy_wrcal_n_9, + wrlvl_byte_done => wrlvl_byte_done, + wrlvl_byte_redo => wrlvl_byte_redo, + wrlvl_byte_redo_r => wrlvl_byte_redo_r, + wrlvl_byte_redo_reg_0 => u_ddr_phy_wrcal_n_8, + wrlvl_byte_redo_reg_1 => u_ddr_phy_wrcal_n_11, + wrlvl_byte_redo_reg_2 => u_ddr_phy_wrcal_n_20, + wrlvl_done_r1 => wrlvl_done_r1 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_rank_common is + port ( + maint_prescaler_tick_r : out STD_LOGIC; + \maintenance_request.maint_req_r_lcl_reg_0\ : out STD_LOGIC; + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + \maintenance_request.maint_zq_r_lcl_reg_0\ : out STD_LOGIC; + \maintenance_request.maint_srx_r_lcl_reg_0\ : out STD_LOGIC; + \periodic_read_request.periodic_rd_r_lcl_reg_0\ : out STD_LOGIC; + app_ref_r : out STD_LOGIC; + \periodic_read_request.periodic_rd_grant_r\ : out STD_LOGIC; + app_sr_active : out STD_LOGIC; + maint_ref_zq_wip : out STD_LOGIC; + \periodic_read_request.periodic_rd_grant_r_reg[0]_0\ : out STD_LOGIC; + wait_for_maint_r_lcl_reg : out STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : out STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : out STD_LOGIC; + wait_for_maint_r_lcl_reg_2 : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \init_calib_complete_reg_rep__9\ : out STD_LOGIC; + I120 : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + q_has_rd_r_reg : out STD_LOGIC; + q_has_rd_r_reg_0 : out STD_LOGIC; + q_has_rd_r_reg_1 : out STD_LOGIC; + q_has_rd_r_reg_2 : out STD_LOGIC; + \maintenance_request.maint_sre_r_lcl_reg_0\ : out STD_LOGIC; + \maintenance_request.maint_req_r_lcl_reg_1\ : out STD_LOGIC; + \maintenance_request.maint_rank_r_lcl_reg[0]_0\ : out STD_LOGIC; + \maintenance_request.maint_sre_r_lcl_reg_1\ : out STD_LOGIC; + \maintenance_request.maint_srx_r_lcl_reg_1\ : out STD_LOGIC; + CLK : in STD_LOGIC; + \maintenance_request.maint_zq_r_lcl_reg_1\ : in STD_LOGIC; + \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ : in STD_LOGIC; + \periodic_read_request.periodic_rd_r_lcl_reg_1\ : in STD_LOGIC; + app_ref_r_reg_0 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + O : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[0]\ : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_request_r\ : in STD_LOGIC; + insert_maint_r1 : in STD_LOGIC; + \refresh_generation.refresh_bank_r\ : in STD_LOGIC; + maint_wip_r : in STD_LOGIC; + \periodic_read_request.periodic_rd_r_lcl_reg_2\ : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_cntr1_r\ : in STD_LOGIC; + app_zq_req : in STD_LOGIC; + app_sr_req : in STD_LOGIC; + \last_master_r_reg[2]\ : in STD_LOGIC; + wait_for_maint_r : in STD_LOGIC; + wait_for_maint_r_lcl_reg_3 : in STD_LOGIC; + wait_for_maint_r_0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_4 : in STD_LOGIC; + wait_for_maint_r_1 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_5 : in STD_LOGIC; + wait_for_maint_r_2 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_6 : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\ : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + cke_r : in STD_LOGIC; + q_has_rd : in STD_LOGIC; + idle_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + q_has_rd_3 : in STD_LOGIC; + q_has_rd_4 : in STD_LOGIC; + q_has_rd_5 : in STD_LOGIC; + auto_pre_r_lcl_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_rank_common : entity is "mig_7series_v4_2_rank_common"; +end ddr3_mig_7series_v4_2_rank_common; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_rank_common is + signal app_ref_ack_ns : STD_LOGIC; + signal \^app_ref_r\ : STD_LOGIC; + signal \^app_sr_active\ : STD_LOGIC; + signal app_sr_active_r_i_1_n_0 : STD_LOGIC; + signal app_zq_ack_ns : STD_LOGIC; + signal app_zq_r : STD_LOGIC; + signal app_zq_r_i_1_n_0 : STD_LOGIC; + signal \maint_prescaler.maint_prescaler_r0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \maint_prescaler.maint_prescaler_r[1]_i_1_n_0\ : STD_LOGIC; + signal \maint_prescaler.maint_prescaler_r[4]_i_1_n_0\ : STD_LOGIC; + signal \maint_prescaler.maint_prescaler_r_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \maint_prescaler.maint_prescaler_tick_ns\ : STD_LOGIC; + signal \^maint_prescaler_tick_r\ : STD_LOGIC; + signal maint_rank_r : STD_LOGIC; + signal \^maint_ref_zq_wip\ : STD_LOGIC; + signal maint_ref_zq_wip_r_i_1_n_0 : STD_LOGIC; + signal maint_sre_r : STD_LOGIC; + signal \maintenance_request.maint_arb0_n_0\ : STD_LOGIC; + signal \maintenance_request.maint_arb0_n_2\ : STD_LOGIC; + signal \maintenance_request.maint_arb0_n_3\ : STD_LOGIC; + signal \^maintenance_request.maint_req_r_lcl_reg_0\ : STD_LOGIC; + signal \maintenance_request.maint_sre_ns\ : STD_LOGIC; + signal \^maintenance_request.maint_srx_r_lcl_reg_0\ : STD_LOGIC; + signal \^maintenance_request.maint_zq_r_lcl_reg_0\ : STD_LOGIC; + signal \maintenance_request.new_maint_rank_r\ : STD_LOGIC; + signal \maintenance_request.upd_last_master_r\ : STD_LOGIC; + signal \maintenance_request.upd_last_master_r_i_1_n_0\ : STD_LOGIC; + signal \^periodic_read_request.periodic_rd_grant_r\ : STD_LOGIC; + signal \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0\ : STD_LOGIC; + signal \periodic_read_request.periodic_rd_r_cnt\ : STD_LOGIC; + signal \periodic_read_request.periodic_rd_r_cnt_i_1_n_0\ : STD_LOGIC; + signal \periodic_read_request.periodic_rd_r_lcl_i_1_n_0\ : STD_LOGIC; + signal \^periodic_read_request.periodic_rd_r_lcl_reg_0\ : STD_LOGIC; + signal \periodic_read_request.upd_last_master_ns\ : STD_LOGIC; + signal \periodic_read_request.upd_last_master_r\ : STD_LOGIC; + signal \refresh_generation.refresh_bank_r[0]_i_2_n_0\ : STD_LOGIC; + signal \refresh_timer.refresh_timer_r0\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \refresh_timer.refresh_timer_r0_0\ : STD_LOGIC; + signal \refresh_timer.refresh_timer_r[1]_i_1_n_0\ : STD_LOGIC; + signal \refresh_timer.refresh_timer_r[5]_i_1_n_0\ : STD_LOGIC; + signal \refresh_timer.refresh_timer_r[5]_i_4_n_0\ : STD_LOGIC; + signal \refresh_timer.refresh_timer_r[5]_i_5_n_0\ : STD_LOGIC; + signal \refresh_timer.refresh_timer_r[5]_i_6_n_0\ : STD_LOGIC; + signal \refresh_timer.refresh_timer_r_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal sel : STD_LOGIC; + signal \sr_cntrl.ckesr_timer.ckesr_timer_r\ : STD_LOGIC; + signal \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\ : STD_LOGIC; + signal \sr_cntrl.sre_request_logic.sre_request_r\ : STD_LOGIC; + signal \sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_request_logic.zq_request_r\ : STD_LOGIC; + signal \zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_13_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg\ : STD_LOGIC_VECTOR ( 19 downto 0 ); + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of app_ref_ack_r_i_1 : label is "soft_lutpair559"; + attribute SOFT_HLUTNM of app_sr_active_r_i_1 : label is "soft_lutpair555"; + attribute SOFT_HLUTNM of app_zq_ack_r_i_1 : label is "soft_lutpair559"; + attribute SOFT_HLUTNM of cke_r_i_1 : label is "soft_lutpair555"; + attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[0]_i_1\ : label is "soft_lutpair560"; + attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[1]_i_1\ : label is "soft_lutpair560"; + attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[2]_i_1\ : label is "soft_lutpair556"; + attribute SOFT_HLUTNM of \maint_prescaler.maint_prescaler_r[3]_i_1\ : label is "soft_lutpair556"; + attribute SOFT_HLUTNM of pass_open_bank_r_lcl_i_5 : label is "soft_lutpair550"; + attribute SOFT_HLUTNM of \periodic_rd_generation.periodic_rd_cntr1_r_i_1\ : label is "soft_lutpair558"; + attribute SOFT_HLUTNM of \periodic_read_request.periodic_rd_grant_r[0]_i_1\ : label is "soft_lutpair552"; + attribute SOFT_HLUTNM of \periodic_read_request.periodic_rd_r_cnt_i_1\ : label is "soft_lutpair558"; + attribute SOFT_HLUTNM of \periodic_read_request.upd_last_master_r_i_1\ : label is "soft_lutpair552"; + attribute SOFT_HLUTNM of \refresh_generation.refresh_bank_r[0]_i_2\ : label is "soft_lutpair551"; + attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[2]_i_1\ : label is "soft_lutpair557"; + attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[3]_i_1\ : label is "soft_lutpair553"; + attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[4]_i_1\ : label is "soft_lutpair553"; + attribute SOFT_HLUTNM of \refresh_timer.refresh_timer_r[5]_i_5\ : label is "soft_lutpair557"; + attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_2\ : label is "soft_lutpair554"; + attribute SOFT_HLUTNM of \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_3\ : label is "soft_lutpair551"; + attribute SOFT_HLUTNM of \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1\ : label is "soft_lutpair554"; + attribute SOFT_HLUTNM of \wait_for_maint_r_lcl_i_2__2\ : label is "soft_lutpair550"; +begin + app_ref_r <= \^app_ref_r\; + app_sr_active <= \^app_sr_active\; + maint_prescaler_tick_r <= \^maint_prescaler_tick_r\; + maint_ref_zq_wip <= \^maint_ref_zq_wip\; + \maintenance_request.maint_req_r_lcl_reg_0\ <= \^maintenance_request.maint_req_r_lcl_reg_0\; + \maintenance_request.maint_srx_r_lcl_reg_0\ <= \^maintenance_request.maint_srx_r_lcl_reg_0\; + \maintenance_request.maint_zq_r_lcl_reg_0\ <= \^maintenance_request.maint_zq_r_lcl_reg_0\; + \periodic_read_request.periodic_rd_grant_r\ <= \^periodic_read_request.periodic_rd_grant_r\; + \periodic_read_request.periodic_rd_r_lcl_reg_0\ <= \^periodic_read_request.periodic_rd_r_lcl_reg_0\; +app_ref_ack_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"8A" + ) + port map ( + I0 => \^app_ref_r\, + I1 => \refresh_generation.refresh_bank_r\, + I2 => \grant_r_reg[0]\, + O => app_ref_ack_ns + ); +app_ref_ack_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => app_ref_ack_ns, + Q => app_ref_ack, + R => '0' + ); +app_ref_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => app_ref_r_reg_0, + Q => \^app_ref_r\, + R => \periodic_read_request.periodic_rd_r_lcl_reg_1\ + ); +app_sr_active_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"2F20" + ) + port map ( + I0 => maint_sre_r, + I1 => \^maintenance_request.maint_srx_r_lcl_reg_0\, + I2 => insert_maint_r1, + I3 => \^app_sr_active\, + O => app_sr_active_r_i_1_n_0 + ); +app_sr_active_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => app_sr_active_r_i_1_n_0, + Q => \^app_sr_active\, + R => '0' + ); +app_zq_ack_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"2A" + ) + port map ( + I0 => app_zq_r, + I1 => \zq_cntrl.zq_request_logic.zq_request_r\, + I2 => \grant_r_reg[0]\, + O => app_zq_ack_ns + ); +app_zq_ack_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => app_zq_ack_ns, + Q => app_zq_ack, + R => '0' + ); +app_zq_r_i_1: unisim.vcomponents.LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => app_zq_req, + I1 => app_zq_r, + I2 => \zq_cntrl.zq_request_logic.zq_request_r\, + O => app_zq_r_i_1_n_0 + ); +app_zq_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => app_zq_r_i_1_n_0, + Q => app_zq_r, + R => \periodic_read_request.periodic_rd_r_lcl_reg_1\ + ); +auto_pre_r_lcl_i_3: unisim.vcomponents.LUT6 + generic map( + INIT => X"0D0D0DFF0D0D0D0D" + ) + port map ( + I0 => \^maintenance_request.maint_req_r_lcl_reg_0\, + I1 => auto_pre_r_lcl_reg, + I2 => maint_wip_r, + I3 => maint_sre_r, + I4 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I5 => maint_rank_r, + O => \maintenance_request.maint_req_r_lcl_reg_1\ + ); +cke_r_i_1: unisim.vcomponents.LUT4 + generic map( + INIT => X"0CEC" + ) + port map ( + I0 => \^maintenance_request.maint_srx_r_lcl_reg_0\, + I1 => cke_r, + I2 => insert_maint_r1, + I3 => maint_sre_r, + O => I120(0) + ); +\maint_controller.maint_hit_busies_r[3]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFFFFF1010FF10" + ) + port map ( + I0 => maint_sre_r, + I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I2 => maint_rank_r, + I3 => \^maintenance_request.maint_req_r_lcl_reg_0\, + I4 => auto_pre_r_lcl_reg, + I5 => maint_wip_r, + O => \maintenance_request.maint_sre_r_lcl_reg_0\ + ); +\maint_prescaler.maint_prescaler_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(0), + O => \maint_prescaler.maint_prescaler_r0\(0) + ); +\maint_prescaler.maint_prescaler_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(0), + I1 => \maint_prescaler.maint_prescaler_r_reg\(1), + O => \maint_prescaler.maint_prescaler_r[1]_i_1_n_0\ + ); +\maint_prescaler.maint_prescaler_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(2), + I1 => \maint_prescaler.maint_prescaler_r_reg\(1), + I2 => \maint_prescaler.maint_prescaler_r_reg\(0), + O => \maint_prescaler.maint_prescaler_r0\(2) + ); +\maint_prescaler.maint_prescaler_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(3), + I1 => \maint_prescaler.maint_prescaler_r_reg\(2), + I2 => \maint_prescaler.maint_prescaler_r_reg\(0), + I3 => \maint_prescaler.maint_prescaler_r_reg\(1), + O => \maint_prescaler.maint_prescaler_r0\(3) + ); +\maint_prescaler.maint_prescaler_r[4]_i_1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"00000004FFFFFFFF" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(2), + I1 => \maint_prescaler.maint_prescaler_r_reg\(0), + I2 => \maint_prescaler.maint_prescaler_r_reg\(1), + I3 => \maint_prescaler.maint_prescaler_r_reg\(3), + I4 => \maint_prescaler.maint_prescaler_r_reg\(4), + I5 => \grant_r_reg[0]\, + O => \maint_prescaler.maint_prescaler_r[4]_i_1_n_0\ + ); +\maint_prescaler.maint_prescaler_r[4]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFFFFFE" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(4), + I1 => \maint_prescaler.maint_prescaler_r_reg\(3), + I2 => \maint_prescaler.maint_prescaler_r_reg\(1), + I3 => \maint_prescaler.maint_prescaler_r_reg\(0), + I4 => \maint_prescaler.maint_prescaler_r_reg\(2), + O => sel + ); +\maint_prescaler.maint_prescaler_r[4]_i_3\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAA9" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(4), + I1 => \maint_prescaler.maint_prescaler_r_reg\(3), + I2 => \maint_prescaler.maint_prescaler_r_reg\(1), + I3 => \maint_prescaler.maint_prescaler_r_reg\(0), + I4 => \maint_prescaler.maint_prescaler_r_reg\(2), + O => \maint_prescaler.maint_prescaler_r0\(4) + ); +\maint_prescaler.maint_prescaler_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sel, + D => \maint_prescaler.maint_prescaler_r0\(0), + Q => \maint_prescaler.maint_prescaler_r_reg\(0), + R => \maint_prescaler.maint_prescaler_r[4]_i_1_n_0\ + ); +\maint_prescaler.maint_prescaler_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sel, + D => \maint_prescaler.maint_prescaler_r[1]_i_1_n_0\, + Q => \maint_prescaler.maint_prescaler_r_reg\(1), + R => \maint_prescaler.maint_prescaler_r[4]_i_1_n_0\ + ); +\maint_prescaler.maint_prescaler_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sel, + D => \maint_prescaler.maint_prescaler_r0\(2), + Q => \maint_prescaler.maint_prescaler_r_reg\(2), + R => \maint_prescaler.maint_prescaler_r[4]_i_1_n_0\ + ); +\maint_prescaler.maint_prescaler_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => sel, + D => \maint_prescaler.maint_prescaler_r0\(3), + Q => \maint_prescaler.maint_prescaler_r_reg\(3), + R => \maint_prescaler.maint_prescaler_r[4]_i_1_n_0\ + ); +\maint_prescaler.maint_prescaler_r_reg[4]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => sel, + D => \maint_prescaler.maint_prescaler_r0\(4), + Q => \maint_prescaler.maint_prescaler_r_reg\(4), + S => \maint_prescaler.maint_prescaler_r[4]_i_1_n_0\ + ); +\maint_prescaler.maint_prescaler_tick_r_lcl_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000100" + ) + port map ( + I0 => \maint_prescaler.maint_prescaler_r_reg\(4), + I1 => \maint_prescaler.maint_prescaler_r_reg\(3), + I2 => \maint_prescaler.maint_prescaler_r_reg\(1), + I3 => \maint_prescaler.maint_prescaler_r_reg\(0), + I4 => \maint_prescaler.maint_prescaler_r_reg\(2), + O => \maint_prescaler.maint_prescaler_tick_ns\ + ); +\maint_prescaler.maint_prescaler_tick_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maint_prescaler.maint_prescaler_tick_ns\, + Q => \^maint_prescaler_tick_r\, + R => '0' + ); +maint_ref_zq_wip_r_i_1: unisim.vcomponents.LUT6 + generic map( + INIT => X"FFFFD000D000D000" + ) + port map ( + I0 => \refresh_generation.refresh_bank_r\, + I1 => \zq_cntrl.zq_request_logic.zq_request_r\, + I2 => \grant_r_reg[0]\, + I3 => insert_maint_r1, + I4 => maint_wip_r, + I5 => \^maint_ref_zq_wip\, + O => maint_ref_zq_wip_r_i_1_n_0 + ); +maint_ref_zq_wip_r_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => maint_ref_zq_wip_r_i_1_n_0, + Q => \^maint_ref_zq_wip\, + R => SR(0) + ); +\maintenance_request.maint_arb0\: entity work.ddr3_mig_7series_v4_2_round_robin_arb + port map ( + CLK => CLK, + app_sr_req => app_sr_req, + \grant_r_reg[0]_0\ => \grant_r_reg[0]\, + \grant_r_reg[1]_0\ => \maintenance_request.maint_arb0_n_3\, + \last_master_r_reg[2]_0\ => \last_master_r_reg[2]\, + maint_rank_r => maint_rank_r, + maint_sre_r => maint_sre_r, + \maintenance_request.maint_rank_r_lcl_reg[0]\ => \maintenance_request.maint_arb0_n_0\, + \maintenance_request.maint_sre_ns\ => \maintenance_request.maint_sre_ns\, + \maintenance_request.maint_sre_r_lcl_reg\ => \maintenance_request.maint_arb0_n_2\, + \maintenance_request.maint_srx_r_lcl_reg\ => \^maintenance_request.maint_srx_r_lcl_reg_0\, + \maintenance_request.maint_zq_r_lcl_reg\ => \^maintenance_request.maint_zq_r_lcl_reg_0\, + \maintenance_request.new_maint_rank_r\ => \maintenance_request.new_maint_rank_r\, + \maintenance_request.upd_last_master_r\ => \maintenance_request.upd_last_master_r\, + \refresh_generation.refresh_bank_r\ => \refresh_generation.refresh_bank_r\, + \sr_cntrl.ckesr_timer.ckesr_timer_r\ => \sr_cntrl.ckesr_timer.ckesr_timer_r\, + \sr_cntrl.sre_request_logic.sre_request_r\ => \sr_cntrl.sre_request_logic.sre_request_r\, + \zq_cntrl.zq_request_logic.zq_request_r\ => \zq_cntrl.zq_request_logic.zq_request_r\ + ); +\maintenance_request.maint_rank_r_lcl_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maintenance_request.maint_arb0_n_0\, + Q => maint_rank_r, + R => '0' + ); +\maintenance_request.maint_req_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maintenance_request.new_maint_rank_r\, + Q => \^maintenance_request.maint_req_r_lcl_reg_0\, + R => '0' + ); +\maintenance_request.maint_sre_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maintenance_request.maint_sre_ns\, + Q => maint_sre_r, + R => '0' + ); +\maintenance_request.maint_srx_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maintenance_request.maint_arb0_n_2\, + Q => \^maintenance_request.maint_srx_r_lcl_reg_0\, + R => \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ + ); +\maintenance_request.maint_zq_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maintenance_request.maint_arb0_n_3\, + Q => \^maintenance_request.maint_zq_r_lcl_reg_0\, + R => \maintenance_request.maint_zq_r_lcl_reg_1\ + ); +\maintenance_request.new_maint_rank_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maintenance_request.upd_last_master_r\, + Q => \maintenance_request.new_maint_rank_r\, + R => '0' + ); +\maintenance_request.upd_last_master_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"54005500" + ) + port map ( + I0 => maint_wip_r, + I1 => \sr_cntrl.sre_request_logic.sre_request_r\, + I2 => \zq_cntrl.zq_request_logic.zq_request_r\, + I3 => \grant_r_reg[0]\, + I4 => \refresh_generation.refresh_bank_r\, + O => \maintenance_request.upd_last_master_r_i_1_n_0\ + ); +\maintenance_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \maintenance_request.upd_last_master_r_i_1_n_0\, + Q => \maintenance_request.upd_last_master_r\, + R => '0' + ); +pass_open_bank_r_lcl_i_5: unisim.vcomponents.LUT3 + generic map( + INIT => X"02" + ) + port map ( + I0 => maint_rank_r, + I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I2 => maint_sre_r, + O => \maintenance_request.maint_rank_r_lcl_reg[0]_0\ + ); +\periodic_rd_generation.periodic_rd_cntr1_r_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^periodic_read_request.periodic_rd_grant_r\, + I1 => \periodic_read_request.periodic_rd_r_lcl_reg_2\, + I2 => \periodic_rd_generation.periodic_rd_cntr1_r\, + O => \periodic_read_request.periodic_rd_grant_r_reg[0]_0\ + ); +\periodic_read_request.periodic_rd_grant_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFF0008" + ) + port map ( + I0 => \grant_r_reg[0]\, + I1 => \periodic_rd_generation.periodic_rd_request_r\, + I2 => \periodic_read_request.upd_last_master_r\, + I3 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\, + I4 => \^periodic_read_request.periodic_rd_grant_r\, + O => \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0\ + ); +\periodic_read_request.periodic_rd_grant_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0\, + Q => \^periodic_read_request.periodic_rd_grant_r\, + R => '0' + ); +\periodic_read_request.periodic_rd_r_cnt_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"78" + ) + port map ( + I0 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\, + I1 => \periodic_read_request.periodic_rd_r_lcl_reg_2\, + I2 => \periodic_read_request.periodic_rd_r_cnt\, + O => \periodic_read_request.periodic_rd_r_cnt_i_1_n_0\ + ); +\periodic_read_request.periodic_rd_r_cnt_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_read_request.periodic_rd_r_cnt_i_1_n_0\, + Q => \periodic_read_request.periodic_rd_r_cnt\, + R => SR(0) + ); +\periodic_read_request.periodic_rd_r_lcl_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FF4C" + ) + port map ( + I0 => \periodic_read_request.periodic_rd_r_lcl_reg_2\, + I1 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\, + I2 => \periodic_read_request.periodic_rd_r_cnt\, + I3 => \periodic_read_request.upd_last_master_r\, + O => \periodic_read_request.periodic_rd_r_lcl_i_1_n_0\ + ); +\periodic_read_request.periodic_rd_r_lcl_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_read_request.periodic_rd_r_lcl_i_1_n_0\, + Q => \^periodic_read_request.periodic_rd_r_lcl_reg_0\, + R => \periodic_read_request.periodic_rd_r_lcl_reg_1\ + ); +\periodic_read_request.upd_last_master_r_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0008" + ) + port map ( + I0 => \grant_r_reg[0]\, + I1 => \periodic_rd_generation.periodic_rd_request_r\, + I2 => \periodic_read_request.upd_last_master_r\, + I3 => \^periodic_read_request.periodic_rd_r_lcl_reg_0\, + O => \periodic_read_request.upd_last_master_ns\ + ); +\periodic_read_request.upd_last_master_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \periodic_read_request.upd_last_master_ns\, + Q => \periodic_read_request.upd_last_master_r\, + R => '0' + ); +q_has_rd_r_i_2: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFBAAAA" + ) + port map ( + I0 => q_has_rd, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => \^maintenance_request.maint_req_r_lcl_reg_0\, + I5 => idle_r(3), + O => q_has_rd_r_reg + ); +\q_has_rd_r_i_2__0\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFBAAAA" + ) + port map ( + I0 => q_has_rd_3, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => \^maintenance_request.maint_req_r_lcl_reg_0\, + I5 => idle_r(2), + O => q_has_rd_r_reg_0 + ); +\q_has_rd_r_i_2__1\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFBAAAA" + ) + port map ( + I0 => q_has_rd_4, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => \^maintenance_request.maint_req_r_lcl_reg_0\, + I5 => idle_r(1), + O => q_has_rd_r_reg_1 + ); +\q_has_rd_r_i_2__2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAFFFBAAAA" + ) + port map ( + I0 => q_has_rd_5, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => \^maintenance_request.maint_req_r_lcl_reg_0\, + I5 => idle_r(0), + O => q_has_rd_r_reg_2 + ); +\refresh_generation.refresh_bank_r[0]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"88820008" + ) + port map ( + I0 => \grant_r_reg[0]\, + I1 => \refresh_generation.refresh_bank_r\, + I2 => app_ref_req, + I3 => \refresh_timer.refresh_timer_r[5]_i_4_n_0\, + I4 => \refresh_generation.refresh_bank_r[0]_i_2_n_0\, + O => \init_calib_complete_reg_rep__9\ + ); +\refresh_generation.refresh_bank_r[0]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00000004" + ) + port map ( + I0 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I1 => insert_maint_r1, + I2 => \^maintenance_request.maint_srx_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => maint_rank_r, + O => \refresh_generation.refresh_bank_r[0]_i_2_n_0\ + ); +\refresh_timer.refresh_timer_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(0), + O => \refresh_timer.refresh_timer_r0\(0) + ); +\refresh_timer.refresh_timer_r[1]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"9" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(0), + I1 => \refresh_timer.refresh_timer_r_reg\(1), + O => \refresh_timer.refresh_timer_r[1]_i_1_n_0\ + ); +\refresh_timer.refresh_timer_r[2]_i_1\: unisim.vcomponents.LUT3 + generic map( + INIT => X"A9" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(2), + I1 => \refresh_timer.refresh_timer_r_reg\(1), + I2 => \refresh_timer.refresh_timer_r_reg\(0), + O => \refresh_timer.refresh_timer_r0\(2) + ); +\refresh_timer.refresh_timer_r[3]_i_1\: unisim.vcomponents.LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(3), + I1 => \refresh_timer.refresh_timer_r_reg\(2), + I2 => \refresh_timer.refresh_timer_r_reg\(0), + I3 => \refresh_timer.refresh_timer_r_reg\(1), + O => \refresh_timer.refresh_timer_r0\(3) + ); +\refresh_timer.refresh_timer_r[4]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAAA9" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(4), + I1 => \refresh_timer.refresh_timer_r_reg\(3), + I2 => \refresh_timer.refresh_timer_r_reg\(1), + I3 => \refresh_timer.refresh_timer_r_reg\(0), + I4 => \refresh_timer.refresh_timer_r_reg\(2), + O => \refresh_timer.refresh_timer_r0\(4) + ); +\refresh_timer.refresh_timer_r[5]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r[5]_i_4_n_0\, + I1 => \grant_r_reg[0]\, + O => \refresh_timer.refresh_timer_r[5]_i_1_n_0\ + ); +\refresh_timer.refresh_timer_r[5]_i_2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"AAAAAA8A" + ) + port map ( + I0 => \^maint_prescaler_tick_r\, + I1 => \refresh_timer.refresh_timer_r_reg\(5), + I2 => \refresh_timer.refresh_timer_r[5]_i_5_n_0\, + I3 => \refresh_timer.refresh_timer_r_reg\(4), + I4 => \refresh_timer.refresh_timer_r_reg\(3), + O => \refresh_timer.refresh_timer_r0_0\ + ); +\refresh_timer.refresh_timer_r[5]_i_3\: unisim.vcomponents.LUT6 + generic map( + INIT => X"AAAAAAAAAAAAAAA9" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(5), + I1 => \refresh_timer.refresh_timer_r_reg\(3), + I2 => \refresh_timer.refresh_timer_r_reg\(4), + I3 => \refresh_timer.refresh_timer_r_reg\(1), + I4 => \refresh_timer.refresh_timer_r_reg\(0), + I5 => \refresh_timer.refresh_timer_r_reg\(2), + O => \refresh_timer.refresh_timer_r0\(5) + ); +\refresh_timer.refresh_timer_r[5]_i_4\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000040000" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(5), + I1 => \^maint_prescaler_tick_r\, + I2 => \refresh_timer.refresh_timer_r_reg\(2), + I3 => \refresh_timer.refresh_timer_r_reg\(1), + I4 => \refresh_timer.refresh_timer_r_reg\(0), + I5 => \refresh_timer.refresh_timer_r[5]_i_6_n_0\, + O => \refresh_timer.refresh_timer_r[5]_i_4_n_0\ + ); +\refresh_timer.refresh_timer_r[5]_i_5\: unisim.vcomponents.LUT3 + generic map( + INIT => X"01" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(1), + I1 => \refresh_timer.refresh_timer_r_reg\(0), + I2 => \refresh_timer.refresh_timer_r_reg\(2), + O => \refresh_timer.refresh_timer_r[5]_i_5_n_0\ + ); +\refresh_timer.refresh_timer_r[5]_i_6\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \refresh_timer.refresh_timer_r_reg\(3), + I1 => \refresh_timer.refresh_timer_r_reg\(4), + O => \refresh_timer.refresh_timer_r[5]_i_6_n_0\ + ); +\refresh_timer.refresh_timer_r_reg[0]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \refresh_timer.refresh_timer_r0_0\, + D => \refresh_timer.refresh_timer_r0\(0), + Q => \refresh_timer.refresh_timer_r_reg\(0), + S => \refresh_timer.refresh_timer_r[5]_i_1_n_0\ + ); +\refresh_timer.refresh_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \refresh_timer.refresh_timer_r0_0\, + D => \refresh_timer.refresh_timer_r[1]_i_1_n_0\, + Q => \refresh_timer.refresh_timer_r_reg\(1), + R => \refresh_timer.refresh_timer_r[5]_i_1_n_0\ + ); +\refresh_timer.refresh_timer_r_reg[2]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \refresh_timer.refresh_timer_r0_0\, + D => \refresh_timer.refresh_timer_r0\(2), + Q => \refresh_timer.refresh_timer_r_reg\(2), + S => \refresh_timer.refresh_timer_r[5]_i_1_n_0\ + ); +\refresh_timer.refresh_timer_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \refresh_timer.refresh_timer_r0_0\, + D => \refresh_timer.refresh_timer_r0\(3), + Q => \refresh_timer.refresh_timer_r_reg\(3), + R => \refresh_timer.refresh_timer_r[5]_i_1_n_0\ + ); +\refresh_timer.refresh_timer_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \refresh_timer.refresh_timer_r0_0\, + D => \refresh_timer.refresh_timer_r0\(4), + Q => \refresh_timer.refresh_timer_r_reg\(4), + R => \refresh_timer.refresh_timer_r[5]_i_1_n_0\ + ); +\refresh_timer.refresh_timer_r_reg[5]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \refresh_timer.refresh_timer_r0_0\, + D => \refresh_timer.refresh_timer_r0\(5), + Q => \refresh_timer.refresh_timer_r_reg\(5), + S => \refresh_timer.refresh_timer_r[5]_i_1_n_0\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFEF" + ) + port map ( + I0 => maint_sre_r, + I1 => \^maintenance_request.maint_srx_r_lcl_reg_0\, + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\, + I3 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + O => \maintenance_request.maint_sre_r_lcl_reg_1\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_3\: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => \^maintenance_request.maint_srx_r_lcl_reg_0\, + I1 => maint_sre_r, + O => \maintenance_request.maint_srx_r_lcl_reg_1\ + ); +\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0101010101015101" + ) + port map ( + I0 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + I1 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\, + I2 => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\, + I3 => \^maintenance_request.maint_srx_r_lcl_reg_0\, + I4 => maint_sre_r, + I5 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + O => \rstdiv0_sync_r1_reg_rep__13\(0) + ); +\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => maint_sre_r, + I1 => insert_maint_r1, + O => \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\ + ); +\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0]\: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0\, + Q => \sr_cntrl.ckesr_timer.ckesr_timer_r\, + R => '0' + ); +\sr_cntrl.sre_request_logic.sre_request_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"00F8F0F8" + ) + port map ( + I0 => app_sr_req, + I1 => \grant_r_reg[0]\, + I2 => \sr_cntrl.sre_request_logic.sre_request_r\, + I3 => maint_sre_r, + I4 => insert_maint_r1, + O => \sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0\ + ); +\sr_cntrl.sre_request_logic.sre_request_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0\, + Q => \sr_cntrl.sre_request_logic.sre_request_r\, + R => \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ + ); +wait_for_maint_r_lcl_i_1: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFBAAAA" + ) + port map ( + I0 => wait_for_maint_r_0, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => wait_for_maint_r_lcl_reg_4, + O => wait_for_maint_r_lcl_reg_0 + ); +\wait_for_maint_r_lcl_i_1__0\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFBAAAA" + ) + port map ( + I0 => wait_for_maint_r_1, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => wait_for_maint_r_lcl_reg_5, + O => wait_for_maint_r_lcl_reg_1 + ); +\wait_for_maint_r_lcl_i_1__1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFBAAAA" + ) + port map ( + I0 => wait_for_maint_r_2, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => wait_for_maint_r_lcl_reg_6, + O => wait_for_maint_r_lcl_reg_2 + ); +\wait_for_maint_r_lcl_i_2__2\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFBAAAA" + ) + port map ( + I0 => wait_for_maint_r, + I1 => maint_rank_r, + I2 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I3 => maint_sre_r, + I4 => wait_for_maint_r_lcl_reg_3, + O => wait_for_maint_r_lcl_reg + ); +\zq_cntrl.zq_request_logic.zq_request_r_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FF2AFFFF" + ) + port map ( + I0 => \zq_cntrl.zq_request_logic.zq_request_r\, + I1 => \^maintenance_request.maint_zq_r_lcl_reg_0\, + I2 => insert_maint_r1, + I3 => app_zq_req, + I4 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\, + O => \zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0\ + ); +\zq_cntrl.zq_request_logic.zq_request_r_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0\, + Q => \zq_cntrl.zq_request_logic.zq_request_r\, + R => \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\, + O => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_10\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(19), + I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(17), + I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(18), + I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(16), + O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_11\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(6), + I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(5), + I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(7), + I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(4), + O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_12\: unisim.vcomponents.LUT4 + generic map( + INIT => X"0001" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(14), + I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(13), + I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(15), + I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(12), + O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_13\: unisim.vcomponents.LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(11), + I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(10), + I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(9), + I3 => \zq_cntrl.zq_timer.zq_timer_r_reg\(8), + O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_13_n_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_2\: unisim.vcomponents.LUT4 + generic map( + INIT => X"A8AA" + ) + port map ( + I0 => \^maint_prescaler_tick_r\, + I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1), + I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0), + I3 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\, + O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_4\: unisim.vcomponents.LUT5 + generic map( + INIT => X"8AAAAAAA" + ) + port map ( + I0 => \grant_r_reg[0]\, + I1 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1), + I2 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0), + I3 => \^maint_prescaler_tick_r\, + I4 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\, + O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_5\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000010" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0\, + I1 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0\, + I2 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0\, + I3 => \zq_cntrl.zq_timer.zq_timer_r[0]_i_13_n_0\, + I4 => \zq_cntrl.zq_timer.zq_timer_r_reg\(3), + I5 => \zq_cntrl.zq_timer.zq_timer_r_reg\(2), + O => \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0\ + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_6\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(3), + O => S(3) + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_7\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(2), + O => S(2) + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_8\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(1), + O => S(1) + ); +\zq_cntrl.zq_timer.zq_timer_r[0]_i_9\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(0), + O => S(0) + ); +\zq_cntrl.zq_timer.zq_timer_r[12]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(15), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3) + ); +\zq_cntrl.zq_timer.zq_timer_r[12]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(14), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(2) + ); +\zq_cntrl.zq_timer.zq_timer_r[12]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(13), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(1) + ); +\zq_cntrl.zq_timer.zq_timer_r[12]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(12), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(0) + ); +\zq_cntrl.zq_timer.zq_timer_r[16]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(19), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3) + ); +\zq_cntrl.zq_timer.zq_timer_r[16]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(18), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(2) + ); +\zq_cntrl.zq_timer.zq_timer_r[16]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(17), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(1) + ); +\zq_cntrl.zq_timer.zq_timer_r[16]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(16), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(0) + ); +\zq_cntrl.zq_timer.zq_timer_r[4]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(7), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3) + ); +\zq_cntrl.zq_timer.zq_timer_r[4]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(6), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(2) + ); +\zq_cntrl.zq_timer.zq_timer_r[4]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(5), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(1) + ); +\zq_cntrl.zq_timer.zq_timer_r[4]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(4), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(0) + ); +\zq_cntrl.zq_timer.zq_timer_r[8]_i_2\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(11), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3) + ); +\zq_cntrl.zq_timer.zq_timer_r[8]_i_3\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(10), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(2) + ); +\zq_cntrl.zq_timer.zq_timer_r[8]_i_4\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(9), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(1) + ); +\zq_cntrl.zq_timer.zq_timer_r[8]_i_5\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => \zq_cntrl.zq_timer.zq_timer_r_reg\(8), + O => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(0) + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => O(0), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(0), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[10]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(2), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(10), + S => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(3), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(11), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(0), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(12), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(1), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(13), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[14]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(2), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(14), + S => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[15]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(3), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(15), + S => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[16]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(0), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(16), + S => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(1), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(17), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(2), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(18), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[19]\: unisim.vcomponents.FDSE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(3), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(19), + S => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => O(1), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(1), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => O(2), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(2), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => O(3), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(3), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(0), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(4), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(1), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(5), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(2), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(6), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(3), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(7), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(0), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(8), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0\, + D => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(1), + Q => \zq_cntrl.zq_timer.zq_timer_r_reg\(9), + R => \zq_cntrl.zq_timer.zq_timer_r0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ui_top is + port ( + \not_strict_mode.status_ram.rd_buf_we_r1_reg\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rd_buf_indx.rd_buf_indx_r_reg[4]\ : out STD_LOGIC; + ram_init_addr : out STD_LOGIC_VECTOR ( 3 downto 0 ); + DOA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DOB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DOC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + app_rdy_r_reg : out STD_LOGIC; + app_wdf_rdy : out STD_LOGIC; + \not_strict_mode.app_rd_data_end_reg\ : out STD_LOGIC; + ram_init_done_r : out STD_LOGIC; + app_rd_data_valid : out STD_LOGIC; + app_en_r2 : out STD_LOGIC; + \app_cmd_r2_reg[0]\ : out STD_LOGIC; + \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\ : out STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC; + \req_bank_r_lcl_reg[0]\ : out STD_LOGIC; + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC; + \req_bank_r_lcl_reg[0]_0\ : out STD_LOGIC; + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + row : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \req_row_r_lcl_reg[13]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + was_wr0 : out STD_LOGIC; + \app_addr_r1_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + req_wr_r_lcl0 : out STD_LOGIC; + \app_addr_r1_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 ); + \write_buffer.wr_buf_out_data_reg[37]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 143 downto 0 ); + \write_buffer.wr_buf_out_data_reg[95]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 ); + CLK : in STD_LOGIC; + \write_data_control.wb_wr_data_addr_r_reg[2]\ : in STD_LOGIC; + wr_data_addr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \not_strict_mode.status_ram.rd_buf_we_r1_reg_0\ : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[5]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_end_ns\ : in STD_LOGIC; + app_wdf_end_r1_reg : in STD_LOGIC; + app_en : in STD_LOGIC; + app_wdf_wren : in STD_LOGIC; + app_wdf_end : in STD_LOGIC; + periodic_rd_ack_r : in STD_LOGIC; + periodic_rd_cntr_r : in STD_LOGIC; + periodic_rd_r : in STD_LOGIC; + rb_hit_busy_r_reg : in STD_LOGIC; + req_bank_r : in STD_LOGIC_VECTOR ( 11 downto 0 ); + rb_hit_busy_r_reg_0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + rb_hit_busy_r_reg_2 : in STD_LOGIC; + row_hit_r_reg : in STD_LOGIC_VECTOR ( 14 downto 0 ); + accept_ns : in STD_LOGIC; + \not_strict_mode.bypass__0\ : in STD_LOGIC; + app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 ); + app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : in STD_LOGIC; + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : in STD_LOGIC; + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\ : in STD_LOGIC; + app_addr : in STD_LOGIC_VECTOR ( 27 downto 0 ); + app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 ); + D : in STD_LOGIC_VECTOR ( 127 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ui_top : entity is "mig_7series_v4_2_ui_top"; +end ddr3_mig_7series_v4_2_ui_top; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ui_top is + signal app_rdy_ns : STD_LOGIC; + signal \not_strict_mode.occ_cnt_r\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \pointer_ram.pointer_wr_addr\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \pointer_ram.pointer_wr_data\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^ram_init_done_r\ : STD_LOGIC; + signal rd_accepted : STD_LOGIC; + signal rd_data_buf_addr_r : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \read_data_indx.rd_data_indx_r_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ui_cmd0_n_35 : STD_LOGIC; + signal ui_cmd0_n_37 : STD_LOGIC; + signal ui_rd_data0_n_137 : STD_LOGIC; + signal wr_accepted : STD_LOGIC; + signal wr_data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \wr_req_counter.wr_req_cnt_r\ : STD_LOGIC_VECTOR ( 0 to 0 ); +begin + ram_init_done_r <= \^ram_init_done_r\; +ui_cmd0: entity work.ddr3_mig_7series_v4_2_ui_cmd + port map ( + CLK => CLK, + E(0) => app_rdy_r_reg, + Q(4 downto 0) => rd_data_buf_addr_r(4 downto 0), + S(3 downto 0) => S(3 downto 0), + app_addr(27 downto 0) => app_addr(27 downto 0), + \app_addr_r1_reg[26]_0\ => \app_addr_r1_reg[27]\(1), + \app_addr_r1_reg[27]_0\(1) => \app_addr_r1_reg[27]\(2), + \app_addr_r1_reg[27]_0\(0) => \app_addr_r1_reg[27]\(0), + \app_addr_r1_reg[9]_0\(9 downto 0) => \app_addr_r1_reg[9]\(9 downto 0), + app_cmd(1 downto 0) => app_cmd(1 downto 0), + \app_cmd_r2_reg[0]_0\ => \app_cmd_r2_reg[0]\, + app_en => app_en, + app_en_r2_reg_0 => app_en_r2, + app_en_r2_reg_1 => app_wdf_end_r1_reg, + app_rdy_ns => app_rdy_ns, + \not_strict_mode.occ_cnt_r\(1 downto 0) => \not_strict_mode.occ_cnt_r\(1 downto 0), + \not_strict_mode.occ_cnt_r_reg[1]\ => ui_cmd0_n_37, + \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0) => \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4 downto 0), + p_0_in(0) => p_0_in(0), + periodic_rd_ack_r => periodic_rd_ack_r, + periodic_rd_cntr_r => periodic_rd_cntr_r, + periodic_rd_r => periodic_rd_r, + rb_hit_busy_r_reg => rb_hit_busy_r_reg, + rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0, + rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1, + rb_hit_busy_r_reg_2 => rb_hit_busy_r_reg_2, + rd_accepted => rd_accepted, + req_bank_r(11 downto 0) => req_bank_r(11 downto 0), + \req_bank_r_lcl_reg[0]\ => \req_bank_r_lcl_reg[0]\, + \req_bank_r_lcl_reg[0]_0\ => \req_bank_r_lcl_reg[0]_0\, + \req_bank_r_lcl_reg[2]\ => \req_bank_r_lcl_reg[2]\, + \req_bank_r_lcl_reg[2]_0\ => \req_bank_r_lcl_reg[2]_0\, + \req_row_r_lcl_reg[13]\(0) => \req_row_r_lcl_reg[13]\(0), + req_wr_r_lcl0 => req_wr_r_lcl0, + row(14 downto 0) => row(14 downto 0), + row_hit_r_reg(14 downto 0) => row_hit_r_reg(14 downto 0), + was_wr0 => was_wr0, + wr_accepted => wr_accepted, + wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0), + \wr_req_counter.wr_req_cnt_r\(0) => \wr_req_counter.wr_req_cnt_r\(0), + \wr_req_counter.wr_req_cnt_r_reg[0]\ => ui_cmd0_n_35 + ); +ui_rd_data0: entity work.ddr3_mig_7series_v4_2_ui_rd_data + port map ( + ADDRA(4) => \rd_buf_indx.rd_buf_indx_r_reg[4]\, + ADDRA(3 downto 0) => ram_init_addr(3 downto 0), + ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0), + CLK => CLK, + D(127 downto 0) => D(127 downto 0), + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => DIC(1 downto 0), + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + Q(4 downto 0) => rd_data_buf_addr_r(4 downto 0), + app_rd_data(127 downto 0) => app_rd_data(127 downto 0), + app_rd_data_valid => app_rd_data_valid, + \not_strict_mode.app_rd_data_end_ns\ => \not_strict_mode.app_rd_data_end_ns\, + \not_strict_mode.app_rd_data_end_reg_0\ => \not_strict_mode.app_rd_data_end_reg\, + \not_strict_mode.app_rd_data_reg[101]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[101]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[101]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[5]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[5]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[5]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[5]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]_1\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]_1\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]_2\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]_1\(1 downto 0), + \not_strict_mode.bypass__0\ => \not_strict_mode.bypass__0\, + \not_strict_mode.occ_cnt_r_reg[1]_0\(1 downto 0) => \not_strict_mode.occ_cnt_r\(1 downto 0), + \not_strict_mode.occ_cnt_r_reg[5]_0\ => ui_rd_data0_n_137, + \not_strict_mode.occ_cnt_r_reg[5]_1\ => ui_cmd0_n_37, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[0]_0\ => app_wdf_end_r1_reg, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_60\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1 downto 0), + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1 downto 0) => \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1 downto 0), + \not_strict_mode.status_ram.rd_buf_we_r1_reg_0\(0) => \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0), + \not_strict_mode.status_ram.rd_buf_we_r1_reg_1\ => \not_strict_mode.status_ram.rd_buf_we_r1_reg_0\, + \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]_0\(6 downto 0) => \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]\(6 downto 0), + \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0), + rd_accepted => rd_accepted, + \rd_buf_indx.ram_init_done_r_lcl_reg_0\ => \^ram_init_done_r\, + wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0), + \write_data_control.wb_wr_data_addr_r_reg[2]\(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0) + ); +ui_wr_data0: entity work.ddr3_mig_7series_v4_2_ui_wr_data + port map ( + ADDRD(3 downto 0) => \pointer_ram.pointer_wr_addr\(3 downto 0), + CLK => CLK, + E(0) => E(0), + Q(3 downto 0) => \read_data_indx.rd_data_indx_r_reg\(3 downto 0), + accept_ns => accept_ns, + app_rdy_ns => app_rdy_ns, + app_rdy_r_reg => ui_rd_data0_n_137, + app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0), + app_wdf_end => app_wdf_end, + app_wdf_end_r1_reg_0 => app_wdf_end_r1_reg, + app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0), + app_wdf_rdy => app_wdf_rdy, + app_wdf_wren => app_wdf_wren, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\ => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\, + p_0_in(0) => p_0_in(0), + \pointer_ram.pointer_wr_data\(3 downto 0) => \pointer_ram.pointer_wr_data\(3 downto 0), + ram_init_done_r => \^ram_init_done_r\, + wr_accepted => wr_accepted, + wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0), + wr_data_buf_addr(3 downto 0) => wr_data_buf_addr(3 downto 0), + \wr_req_counter.wr_req_cnt_r_reg[0]_0\(0) => \wr_req_counter.wr_req_cnt_r\(0), + \wr_req_counter.wr_req_cnt_r_reg[0]_1\ => ui_cmd0_n_35, + \write_buffer.wr_buf_out_data_reg[143]_0\(143 downto 0) => Q(143 downto 0), + \write_buffer.wr_buf_out_data_reg[37]_0\(11 downto 0) => \write_buffer.wr_buf_out_data_reg[37]\(11 downto 0), + \write_buffer.wr_buf_out_data_reg[95]_0\(11 downto 0) => \write_buffer.wr_buf_out_data_reg[95]\(11 downto 0), + \write_data_control.wb_wr_data_addr_r_reg[2]_0\ => \write_data_control.wb_wr_data_addr_r_reg[2]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_arb_mux is + port ( + granted_col_r_reg : out STD_LOGIC; + insert_maint_r1_lcl_reg : out STD_LOGIC; + DIC : out STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[3]\ : out STD_LOGIC; + col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cke_r : out STD_LOGIC; + rnk_config_valid_r : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + I121 : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \rnk_config_strobe_r_reg[0]\ : out STD_LOGIC; + \grant_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[3]_2\ : out STD_LOGIC; + granted_col_r_reg_0 : out STD_LOGIC; + \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC; + \periodic_rd_generation.read_this_rank\ : out STD_LOGIC; + ofs_rdy_r_reg : out STD_LOGIC; + \last_master_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + override_demand_ns : out STD_LOGIC; + \wtr_timer.wtr_cnt_r_reg[1]\ : out STD_LOGIC; + \grant_r_reg[1]\ : out STD_LOGIC; + I119 : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_aux_out0_1 : out STD_LOGIC; + rd_wr_r_lcl_reg : out STD_LOGIC; + granted_col_r_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[0]\ : out STD_LOGIC; + \rnk_config_strobe_r_reg[0]_0\ : out STD_LOGIC; + mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + act_this_rank : out STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + CLK : in STD_LOGIC; + rnk_config_strobe_ns : in STD_LOGIC; + insert_maint_r1_lcl_reg_0 : in STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_ns\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + I120 : in STD_LOGIC_VECTOR ( 0 to 0 ); + rnk_config_valid_r_lcl_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + rnk_config_valid_r_lcl_reg_0 : in STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + col_wait_r : in STD_LOGIC; + \grant_r_reg[0]_0\ : in STD_LOGIC; + \last_master_r_reg[0]\ : in STD_LOGIC; + \grant_r_reg[0]_1\ : in STD_LOGIC; + \grant_r_reg[0]_2\ : in STD_LOGIC; + \grant_r_reg[2]\ : in STD_LOGIC; + \grant_r_reg[0]_3\ : in STD_LOGIC; + \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC; + rd_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[1]_0\ : in STD_LOGIC; + \grant_r_reg[1]_1\ : in STD_LOGIC; + granted_col_r_reg_2 : in STD_LOGIC; + col_wait_r_0 : in STD_LOGIC; + \grant_r_reg[2]_0\ : in STD_LOGIC; + \grant_r[3]_i_6\ : in STD_LOGIC; + ofs_rdy_r : in STD_LOGIC; + \grant_r[3]_i_6_0\ : in STD_LOGIC; + rd_wr_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r[3]_i_3__0\ : in STD_LOGIC; + ofs_rdy_r_1 : in STD_LOGIC; + \grant_r[3]_i_3__0_0\ : in STD_LOGIC; + col_wait_r_2 : in STD_LOGIC; + \grant_r_reg[3]_3\ : in STD_LOGIC; + \grant_r[2]_i_3\ : in STD_LOGIC; + ofs_rdy_r_3 : in STD_LOGIC; + \grant_r[2]_i_3_0\ : in STD_LOGIC; + \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC; + \col_mux.col_periodic_rd_r_reg\ : in STD_LOGIC; + req_periodic_rd_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + wr_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + demand_act_priority_r : in STD_LOGIC; + granted_row_r_reg : in STD_LOGIC; + granted_row_r_reg_0 : in STD_LOGIC; + \grant_r_reg[0]_4\ : in STD_LOGIC; + \grant_r_reg[0]_5\ : in STD_LOGIC; + \grant_r_reg[0]_6\ : in STD_LOGIC; + \grant_r_reg[1]_2\ : in STD_LOGIC; + demand_act_priority_r_4 : in STD_LOGIC; + \grant_r_reg[3]_4\ : in STD_LOGIC; + \grant_r_reg[3]_5\ : in STD_LOGIC; + demand_act_priority_r_5 : in STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[0]\ : in STD_LOGIC; + \grant_r_reg[3]_6\ : in STD_LOGIC; + demand_act_priority_r_6 : in STD_LOGIC; + \grant_r_reg[3]_7\ : in STD_LOGIC; + \grant_r_reg[3]_8\ : in STD_LOGIC; + \cmd_pipe_plus.mc_ras_n_reg[0]\ : in STD_LOGIC; + maint_zq_r : in STD_LOGIC; + maint_srx_r : in STD_LOGIC; + row_cmd_wr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + inhbt_act_faw_r : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[10]\ : in STD_LOGIC; + req_row_r : in STD_LOGIC_VECTOR ( 43 downto 0 ); + req_data_buf_addr_r : in STD_LOGIC_VECTOR ( 19 downto 0 ); + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + act_this_rank_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[2]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \cmd_pipe_plus.mc_address_reg[24]_2\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + auto_pre_r : in STD_LOGIC; + auto_pre_r_7 : in STD_LOGIC; + auto_pre_r_8 : in STD_LOGIC; + auto_pre_r_9 : in STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[14]\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \cmd_pipe_plus.mc_address_reg[40]\ : in STD_LOGIC; + \grant_r[3]_i_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r[3]_i_4_0\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_arb_mux : entity is "mig_7series_v4_2_arb_mux"; +end ddr3_mig_7series_v4_2_arb_mux; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_arb_mux is + signal \^dic\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^col_data_buf_addr\ : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal \col_mux.col_data_buf_addr_r\ : STD_LOGIC_VECTOR ( 4 to 4 ); + signal \col_mux.col_periodic_rd_r\ : STD_LOGIC; + signal col_rd_wr_r : STD_LOGIC; + signal \^grant_r_reg[3]\ : STD_LOGIC; + signal mc_data_offset1 : STD_LOGIC_VECTOR ( 3 to 3 ); + signal rnk_config_0 : STD_LOGIC; + signal rnk_config_r : STD_LOGIC; +begin + DIC(0) <= \^dic\(0); + col_data_buf_addr(4 downto 0) <= \^col_data_buf_addr\(4 downto 0); + \grant_r_reg[3]\ <= \^grant_r_reg[3]\; +arb_row_col0: entity work.ddr3_mig_7series_v4_2_arb_row_col + port map ( + CLK => CLK, + D(2 downto 0) => D(2 downto 0), + DIC(0) => \^dic\(0), + I119(0) => I119(0), + I121(0) => I121(0), + O(0) => mc_data_offset1(3), + Q(3 downto 0) => Q(3 downto 0), + act_this_rank => act_this_rank, + act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0), + auto_pre_r => auto_pre_r, + auto_pre_r_7 => auto_pre_r_7, + auto_pre_r_8 => auto_pre_r_8, + auto_pre_r_9 => auto_pre_r_9, + \cmd_pipe_plus.mc_address_reg[10]\ => \cmd_pipe_plus.mc_address_reg[10]\, + \cmd_pipe_plus.mc_address_reg[14]\(14 downto 0) => \cmd_pipe_plus.mc_address_reg[14]\(14 downto 0), + \cmd_pipe_plus.mc_address_reg[24]\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_0\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]_0\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_1\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]_1\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_2\(9 downto 0) => \cmd_pipe_plus.mc_address_reg[24]_2\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[40]\ => \cmd_pipe_plus.mc_address_reg[40]\, + \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0), + \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\, + \cmd_pipe_plus.mc_ras_n_reg[0]\ => \cmd_pipe_plus.mc_ras_n_reg[0]\, + \cmd_pipe_plus.mc_we_n_reg[0]\ => \cmd_pipe_plus.mc_we_n_reg[0]\, + col_data_buf_addr(4 downto 0) => \^col_data_buf_addr\(4 downto 0), + \col_mux.col_data_buf_addr_r\(0) => \col_mux.col_data_buf_addr_r\(4), + \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\, + \col_mux.col_periodic_rd_r_reg\ => \col_mux.col_periodic_rd_r_reg\, + col_rd_wr_r => col_rd_wr_r, + col_wait_r => col_wait_r, + col_wait_r_0 => col_wait_r_0, + col_wait_r_2 => col_wait_r_2, + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0), + demand_act_priority_r => demand_act_priority_r, + demand_act_priority_r_4 => demand_act_priority_r_4, + demand_act_priority_r_5 => demand_act_priority_r_5, + demand_act_priority_r_6 => demand_act_priority_r_6, + \genblk3[1].rnk_config_strobe_r_reg[1]_0\ => override_demand_ns, + \grant_r[2]_i_3\ => \grant_r[2]_i_3\, + \grant_r[2]_i_3_0\ => \grant_r[2]_i_3_0\, + \grant_r[3]_i_3__0\ => \grant_r[3]_i_3__0\, + \grant_r[3]_i_3__0_0\ => \grant_r[3]_i_3__0_0\, + \grant_r[3]_i_4\(0) => \grant_r[3]_i_4\(0), + \grant_r[3]_i_4_0\ => \grant_r[3]_i_4_0\, + \grant_r[3]_i_6\ => \grant_r[3]_i_6\, + \grant_r[3]_i_6_0\ => \grant_r[3]_i_6_0\, + \grant_r_reg[0]\ => \grant_r_reg[0]\, + \grant_r_reg[0]_0\ => \grant_r_reg[0]_0\, + \grant_r_reg[0]_1\ => \grant_r_reg[0]_1\, + \grant_r_reg[0]_2\ => \grant_r_reg[0]_2\, + \grant_r_reg[0]_3\ => \grant_r_reg[0]_3\, + \grant_r_reg[0]_4\ => \grant_r_reg[0]_4\, + \grant_r_reg[0]_5\ => \grant_r_reg[0]_5\, + \grant_r_reg[0]_6\ => \grant_r_reg[0]_6\, + \grant_r_reg[1]\ => \grant_r_reg[1]\, + \grant_r_reg[1]_0\ => \grant_r_reg[1]_0\, + \grant_r_reg[1]_1\ => \grant_r_reg[1]_1\, + \grant_r_reg[1]_2\ => \grant_r_reg[1]_2\, + \grant_r_reg[2]\ => \grant_r_reg[2]\, + \grant_r_reg[2]_0\ => \grant_r_reg[2]_0\, + \grant_r_reg[3]\ => \^grant_r_reg[3]\, + \grant_r_reg[3]_0\(3 downto 0) => \grant_r_reg[3]_0\(3 downto 0), + \grant_r_reg[3]_1\(3 downto 0) => \grant_r_reg[3]_1\(3 downto 0), + \grant_r_reg[3]_2\ => \grant_r_reg[3]_2\, + \grant_r_reg[3]_3\ => \grant_r_reg[3]_3\, + \grant_r_reg[3]_4\ => \grant_r_reg[3]_4\, + \grant_r_reg[3]_5\ => \grant_r_reg[3]_5\, + \grant_r_reg[3]_6\ => \grant_r_reg[3]_6\, + \grant_r_reg[3]_7\ => \grant_r_reg[3]_7\, + \grant_r_reg[3]_8\ => \grant_r_reg[3]_8\, + granted_col_r_reg_0 => granted_col_r_reg, + granted_col_r_reg_1 => granted_col_r_reg_0, + granted_col_r_reg_2(0) => granted_col_r_reg_1(0), + granted_col_r_reg_3 => granted_col_r_reg_2, + granted_row_r_reg_0 => granted_row_r_reg, + granted_row_r_reg_1 => granted_row_r_reg_0, + inhbt_act_faw_r => inhbt_act_faw_r, + insert_maint_r1_lcl_reg_0 => insert_maint_r1_lcl_reg, + insert_maint_r1_lcl_reg_1 => insert_maint_r1_lcl_reg_0, + \last_master_r_reg[0]\ => \last_master_r_reg[0]\, + \last_master_r_reg[1]\(0) => \last_master_r_reg[1]\(0), + maint_srx_r => maint_srx_r, + maint_zq_r => maint_zq_r, + mc_aux_out0_1 => mc_aux_out0_1, + mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0), + mc_ras_n_ns(1 downto 0) => mc_ras_n_ns(1 downto 0), + ofs_rdy_r => ofs_rdy_r, + ofs_rdy_r_1 => ofs_rdy_r_1, + ofs_rdy_r_3 => ofs_rdy_r_3, + ofs_rdy_r_reg => ofs_rdy_r_reg, + \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\, + \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\, + \periodic_rd_generation.read_this_rank_r_reg\ => \periodic_rd_generation.read_this_rank_r_reg\, + \pre_4_1_1T_arb.granted_pre_ns\ => \pre_4_1_1T_arb.granted_pre_ns\, + \pre_4_1_1T_arb.granted_pre_r_reg_0\(40 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg\(40 downto 0), + \pre_4_1_1T_arb.granted_pre_r_reg_1\(8 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(8 downto 0), + rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0), + rd_wr_r(3 downto 0) => rd_wr_r(3 downto 0), + rd_wr_r_lcl_reg => rd_wr_r_lcl_reg, + req_data_buf_addr_r(19 downto 0) => req_data_buf_addr_r(19 downto 0), + req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0), + req_row_r(43 downto 0) => req_row_r(43 downto 0), + rnk_config_0 => rnk_config_0, + rnk_config_r => rnk_config_r, + rnk_config_strobe_ns => rnk_config_strobe_ns, + \rnk_config_strobe_r_reg[0]_0\ => \rnk_config_strobe_r_reg[0]\, + \rnk_config_strobe_r_reg[0]_1\ => \rnk_config_strobe_r_reg[0]_0\, + rnk_config_valid_r => rnk_config_valid_r, + rnk_config_valid_r_lcl_reg_0(0) => rnk_config_valid_r_lcl_reg(0), + rnk_config_valid_r_lcl_reg_1 => rnk_config_valid_r_lcl_reg_0, + row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0), + wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0), + \wtr_timer.wtr_cnt_r_reg[1]\ => \wtr_timer.wtr_cnt_r_reg[1]\ + ); +arb_select0: entity work.ddr3_mig_7series_v4_2_arb_select + port map ( + CLK => CLK, + DIC(0) => \^dic\(0), + I120(0) => I120(0), + O(0) => mc_data_offset1(3), + SR(0) => SR(0), + cke_r => cke_r, + \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0), + col_data_buf_addr(0) => \^col_data_buf_addr\(4), + \col_mux.col_data_buf_addr_r\(0) => \col_mux.col_data_buf_addr_r\(4), + \col_mux.col_periodic_rd_r\ => \col_mux.col_periodic_rd_r\, + \col_mux.col_rd_wr_r_reg_0\ => \^grant_r_reg[3]\, + col_rd_wr_r => col_rd_wr_r, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0), + rnk_config_0 => rnk_config_0, + rnk_config_r => rnk_config_r + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_4lanes is + port ( + A_rst_primitives_reg_0 : out STD_LOGIC; + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_1 : out STD_LOGIC; + mem_dq_out : out STD_LOGIC_VECTOR ( 40 downto 0 ); + mem_dq_ts : out STD_LOGIC_VECTOR ( 17 downto 0 ); + out_dqs_0 : out STD_LOGIC; + ts_dqs_0 : out STD_LOGIC; + pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_2 : out STD_LOGIC; + out_dqs_1 : out STD_LOGIC; + ts_dqs_1 : out STD_LOGIC; + \rd_ptr_reg[0]_1\ : out STD_LOGIC; + \rd_ptr_reg[1]_1\ : out STD_LOGIC; + \rd_ptr_reg[2]_1\ : out STD_LOGIC; + \rd_ptr_reg[3]_1\ : out STD_LOGIC; + phy_mc_ctl_full : out STD_LOGIC; + ref_dll_lock : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 0 to 0 ); + idelay_ld_rst : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[1]\ : out STD_LOGIC; + \my_empty_reg[1]_0\ : out STD_LOGIC; + init_complete_r1_timing_reg : out STD_LOGIC; + \my_empty_reg[1]_1\ : out STD_LOGIC; + \my_empty_reg[1]_2\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + DIC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + DIA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + DIB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \my_empty_reg[4]_rep__1\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC; + \pi_counter_read_val_reg[5]_1\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + phy_rddata_en : out STD_LOGIC; + rd_data_en : out STD_LOGIC; + \my_empty_reg[0]\ : out STD_LOGIC; + \my_empty_reg[0]_0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC_VECTOR ( 127 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + in0 : out STD_LOGIC; + phy_mc_data_full : out STD_LOGIC; + wr_en : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + phy_mc_cmd_full : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]\ : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[4]_rep__0\ : out STD_LOGIC; + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \po_counter_read_val_reg[8]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \rd_ptr_reg[3]_2\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + p_1_in : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \po_counter_read_val_reg[8]_1\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_2\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_3\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_4\ : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + CLK : in STD_LOGIC; + \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \rd_ptr_reg[3]_10\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_11\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_12\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC; + mem_dq_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); + idelay_inc : in STD_LOGIC; + LD0 : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC; + mem_dqs_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC; + COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \po_counter_read_val_reg[8]_5\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_6\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_7\ : in STD_LOGIC; + D1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D4 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D5 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D6 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D7 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D8 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0 : in STD_LOGIC; + ofifo_rst_reg0 : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC; + LD0_0 : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_4\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \po_counter_read_val_reg[8]_8\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_9\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_10\ : in STD_LOGIC; + D0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0_1 : in STD_LOGIC; + ofifo_rst_reg0_2 : in STD_LOGIC; + phy_ctl_wr_i2 : in STD_LOGIC; + pll_locked : in STD_LOGIC; + phy_read_calib : in STD_LOGIC; + phy_mc_ctl_full_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_write_calib : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); + RST0 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \po_counter_read_val_reg[8]_11\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_12\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_13\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_14\ : in STD_LOGIC; + \my_empty_reg[7]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_9\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_10\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_11\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + calib_cmd_wren : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \read_fifo.tail_r_reg_0_sp_1\ : in STD_LOGIC; + mux_wrdata_en : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC; + calib_wrdata_en : in STD_LOGIC; + out_fifo : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data[127]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DOC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[8]\ : in STD_LOGIC; + DOB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[73]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[75]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[79]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[81]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[87]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[91]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[93]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[97]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[99]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[103]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[105]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[109]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[111]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[115]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[121]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[123]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mux_cmd_wren : in STD_LOGIC; + mc_address : in STD_LOGIC_VECTOR ( 5 downto 0 ); + mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_dout : in STD_LOGIC_VECTOR ( 39 downto 0 ); + calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_4lanes : entity is "mig_7series_v4_2_ddr_phy_4lanes"; +end ddr3_mig_7series_v4_2_ddr_phy_4lanes; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_4lanes is + signal A_pi_rst_div2 : STD_LOGIC; + attribute async_reg : string; + attribute async_reg of A_pi_rst_div2 : signal is "true"; + signal A_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \^a_rst_primitives_reg_0\ : STD_LOGIC; + signal B_of_full : STD_LOGIC; + signal B_pi_rst_div2 : STD_LOGIC; + attribute async_reg of B_pi_rst_div2 : signal is "true"; + signal C_pi_rst_div2 : STD_LOGIC; + attribute async_reg of C_pi_rst_div2 : signal is "true"; + signal C_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \^dia\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dib\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dic\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal D_pi_counter_read_val : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal D_pi_rst_div2 : STD_LOGIC; + attribute async_reg of D_pi_rst_div2 : signal is "true"; + signal D_po_counter_read_val : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_23\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_24\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_25\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_26\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_27\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_28\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_29\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_30\ : STD_LOGIC; + signal \ddr_byte_lane_B.ddr_byte_lane_B_n_31\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C_n_257\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C_n_258\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C_n_259\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C_n_260\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C_n_261\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C_n_262\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D_n_24\ : STD_LOGIC; + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal if_empty_r : STD_LOGIC_VECTOR ( 3 to 3 ); + signal if_empty_r_1 : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\ : STD_LOGIC_VECTOR ( 4 downto 2 ); + signal ofifo_rst : STD_LOGIC; + signal phaser_ctl_bus : STD_LOGIC_VECTOR ( 0 to 0 ); + signal phy_control_i_n_0 : STD_LOGIC; + signal phy_control_i_n_1 : STD_LOGIC; + signal phy_control_i_n_10 : STD_LOGIC; + signal phy_control_i_n_11 : STD_LOGIC; + signal phy_control_i_n_14 : STD_LOGIC; + signal phy_control_i_n_15 : STD_LOGIC; + signal phy_control_i_n_16 : STD_LOGIC; + signal phy_control_i_n_17 : STD_LOGIC; + signal phy_control_i_n_18 : STD_LOGIC; + signal phy_control_i_n_19 : STD_LOGIC; + signal phy_control_i_n_20 : STD_LOGIC; + signal phy_control_i_n_21 : STD_LOGIC; + signal phy_control_i_n_22 : STD_LOGIC; + signal phy_control_i_n_23 : STD_LOGIC; + signal phy_control_i_n_24 : STD_LOGIC; + signal phy_control_i_n_3 : STD_LOGIC; + signal phy_control_i_n_4 : STD_LOGIC; + signal phy_control_i_n_5 : STD_LOGIC; + signal phy_control_i_n_6 : STD_LOGIC; + signal phy_control_i_n_7 : STD_LOGIC; + signal phy_control_i_n_8 : STD_LOGIC; + signal phy_control_i_n_9 : STD_LOGIC; + signal phy_encalib : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^pi_counter_read_val_reg[5]_1\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal rclk_delay_11 : STD_LOGIC; + signal \rclk_delay_reg[10]_srl11_i_1_n_0\ : STD_LOGIC; + signal \rclk_delay_reg[10]_srl11_n_0\ : STD_LOGIC; + signal \read_fifo.tail_r_reg_0_sn_1\ : STD_LOGIC; + signal \^ref_dll_lock\ : STD_LOGIC; + signal rst_out_i_1_n_0 : STD_LOGIC; + signal rst_out_reg_n_0 : STD_LOGIC; + signal rst_primitives : STD_LOGIC; + signal rst_primitives_i_1_n_0 : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of phaser_ref_i : label is "PRIMITIVE"; + attribute BOX_TYPE of phy_control_i : label is "PRIMITIVE"; + attribute srl_bus_name : string; + attribute srl_bus_name of \rclk_delay_reg[10]_srl11\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg "; + attribute srl_name : string; + attribute srl_name of \rclk_delay_reg[10]_srl11\ : label is "\u_ddr3_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 "; +begin + A_rst_primitives_reg_0 <= \^a_rst_primitives_reg_0\; + DIA(1 downto 0) <= \^dia\(1 downto 0); + DIB(1 downto 0) <= \^dib\(1 downto 0); + DIC(1 downto 0) <= \^dic\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\(1 downto 0); + \pi_counter_read_val_reg[5]_1\(5 downto 0) <= \^pi_counter_read_val_reg[5]_1\(5 downto 0); + \read_fifo.tail_r_reg_0_sn_1\ <= \read_fifo.tail_r_reg_0_sp_1\; + ref_dll_lock <= \^ref_dll_lock\; +A_rst_primitives_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => rst_primitives, + Q => \^a_rst_primitives_reg_0\, + R => '0' + ); +\FSM_onehot_cal1_state_r[16]_i_2\: unisim.vcomponents.LUT6 + generic map( + INIT => X"0000000000000001" + ) + port map ( + I0 => \^pi_counter_read_val_reg[5]_1\(5), + I1 => \^pi_counter_read_val_reg[5]_1\(3), + I2 => \^pi_counter_read_val_reg[5]_1\(0), + I3 => \^pi_counter_read_val_reg[5]_1\(2), + I4 => \^pi_counter_read_val_reg[5]_1\(1), + I5 => \^pi_counter_read_val_reg[5]_1\(4), + O => \pi_counter_read_val_reg[5]_0\ + ); +\ddr_byte_lane_A.ddr_byte_lane_A\: entity work.ddr3_mig_7series_v4_2_ddr_byte_lane + port map ( + B_of_full => B_of_full, + CLK => CLK, + COUNTERREADVAL(8 downto 0) => A_po_counter_read_val(8 downto 0), + OUTBURSTPENDING(0) => phaser_ctl_bus(0), + PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0), + calib_cmd_wren => calib_cmd_wren, + ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0), + freq_refclk => freq_refclk, + mc_address(5 downto 0) => mc_address(5 downto 0), + mc_cas_n(0) => mc_cas_n(0), + mem_dq_out(10 downto 0) => mem_dq_out(10 downto 0), + mem_refclk => mem_refclk, + mux_cmd_wren => mux_cmd_wren, + \my_empty_reg[1]\ => \my_empty_reg[1]\, + \my_empty_reg[7]\(3 downto 0) => \my_empty_reg[7]_7\(3 downto 0), + \my_empty_reg[7]_0\(3 downto 0) => \my_empty_reg[7]_8\(3 downto 0), + \my_empty_reg[7]_1\(3 downto 0) => \my_empty_reg[7]_9\(3 downto 0), + \my_empty_reg[7]_2\(3 downto 0) => \my_empty_reg[7]_10\(3 downto 0), + \my_empty_reg[7]_3\(3 downto 0) => \my_empty_reg[7]_11\(3 downto 0), + \my_empty_reg[7]_4\(3 downto 0) => \my_empty_reg[7]_12\(3 downto 0), + \my_empty_reg[7]_5\(3 downto 0) => \my_empty_reg[7]_13\(3 downto 0), + \my_empty_reg[7]_6\(3 downto 0) => \my_empty_reg[7]_14\(3 downto 0), + ofifo_rst => ofifo_rst, + ofifo_rst_reg_0 => \^a_rst_primitives_reg_0\, + out_fifo_0 => \wr_ptr_timing_reg[0]_0\, + phy_dout(39 downto 0) => phy_dout(39 downto 0), + phy_mc_cmd_full => phy_mc_cmd_full, + \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_11\, + \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_12\, + \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_13\, + \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_14\, + \rd_ptr_reg[3]\(31 downto 0) => \rd_ptr_reg[3]_2\(31 downto 0), + sync_pulse => sync_pulse, + \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B\: entity work.\ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized0\ + port map ( + B_of_full => B_of_full, + CLK => CLK, + COUNTERREADVAL(8 downto 0) => A_po_counter_read_val(8 downto 0), + D(8) => \ddr_byte_lane_B.ddr_byte_lane_B_n_23\, + D(7) => \ddr_byte_lane_B.ddr_byte_lane_B_n_24\, + D(6) => \ddr_byte_lane_B.ddr_byte_lane_B_n_25\, + D(5) => \ddr_byte_lane_B.ddr_byte_lane_B_n_26\, + D(4) => \ddr_byte_lane_B.ddr_byte_lane_B_n_27\, + D(3) => \ddr_byte_lane_B.ddr_byte_lane_B_n_28\, + D(2) => \ddr_byte_lane_B.ddr_byte_lane_B_n_29\, + D(1) => \ddr_byte_lane_B.ddr_byte_lane_B_n_30\, + D(0) => \ddr_byte_lane_B.ddr_byte_lane_B_n_31\, + OUTBURSTPENDING(0) => phy_control_i_n_24, + PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0), + Q(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + calib_cmd_wren => calib_cmd_wren, + calib_sel(1 downto 0) => calib_sel(1 downto 0), + freq_refclk => freq_refclk, + mem_dq_out(11 downto 0) => mem_dq_out(22 downto 11), + mem_out(2 downto 0) => mem_out(2 downto 0), + mem_refclk => mem_refclk, + mux_cmd_wren => mux_cmd_wren, + \my_empty_reg[1]\ => \my_empty_reg[1]_0\, + ofifo_rst => ofifo_rst, + \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_1\, + \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_2\, + \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_3\, + \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_4\, + \po_counter_read_val_reg[8]_3\ => \^a_rst_primitives_reg_0\, + \po_counter_read_val_reg[8]_4\(8 downto 0) => D_po_counter_read_val(8 downto 0), + \po_counter_read_val_reg[8]_5\(8 downto 0) => C_po_counter_read_val(8 downto 0), + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_0\(3 downto 0) => \rd_ptr_reg[3]_3\(3 downto 0), + \rd_ptr_reg[3]_1\(3 downto 0) => \rd_ptr_reg[3]_4\(3 downto 0), + \rd_ptr_reg[3]_2\(2 downto 0) => \rd_ptr_reg[3]_5\(2 downto 0), + \rd_ptr_reg[3]_3\(3 downto 0) => \rd_ptr_reg[3]_6\(3 downto 0), + \rd_ptr_reg[3]_4\(3 downto 0) => \rd_ptr_reg[3]_7\(3 downto 0), + \rd_ptr_reg[3]_5\(7 downto 0) => \rd_ptr_reg[3]_8\(7 downto 0), + \rd_ptr_reg[3]_6\(6 downto 0) => \rd_ptr_reg[3]_9\(6 downto 0), + \rd_ptr_reg[3]_7\(3 downto 0) => \rd_ptr_reg[3]_10\(3 downto 0), + \rd_ptr_reg[3]_8\(3 downto 0) => \rd_ptr_reg[3]_11\(3 downto 0), + \rd_ptr_reg[3]_9\(2 downto 0) => \rd_ptr_reg[3]_12\(2 downto 0), + sync_pulse => sync_pulse, + wr_en_3 => wr_en_3, + \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]_0\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C\: entity work.\ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized1\ + port map ( + A_rst_primitives_reg => A_rst_primitives_reg_1, + A_rst_primitives_reg_0(8 downto 0) => C_po_counter_read_val(8 downto 0), + CLK => CLK, + CLKB0 => CLKB0, + COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0), + COUNTERREADVAL(5 downto 0) => D_pi_counter_read_val(5 downto 0), + D(5) => \ddr_byte_lane_C.ddr_byte_lane_C_n_257\, + D(4) => \ddr_byte_lane_C.ddr_byte_lane_C_n_258\, + D(3) => \ddr_byte_lane_C.ddr_byte_lane_C_n_259\, + D(2) => \ddr_byte_lane_C.ddr_byte_lane_C_n_260\, + D(1) => \ddr_byte_lane_C.ddr_byte_lane_C_n_261\, + D(0) => \ddr_byte_lane_C.ddr_byte_lane_C_n_262\, + D1(7 downto 0) => D1(7 downto 0), + D2(7 downto 0) => D2(7 downto 0), + D3(7 downto 0) => D3(7 downto 0), + D4(7 downto 0) => D4(7 downto 0), + D5(7 downto 0) => D5(7 downto 0), + D6(7 downto 0) => D6(7 downto 0), + D7(7 downto 0) => D7(7 downto 0), + D8(7 downto 0) => D8(7 downto 0), + D9(7 downto 0) => D9(7 downto 0), + DIA(1 downto 0) => \^dia\(1 downto 0), + DIB(1 downto 0) => \^dib\(1 downto 0), + DIC(1 downto 0) => \^dic\(1 downto 0), + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + INBURSTPENDING(0) => phy_control_i_n_19, + INRANKC(1) => phy_control_i_n_8, + INRANKC(0) => phy_control_i_n_9, + LD0 => LD0, + OUTBURSTPENDING(0) => phy_control_i_n_23, + PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0), + Q(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(73 downto 0), + calib_sel(1 downto 0) => calib_sel(1 downto 0), + calib_wrdata_en => calib_wrdata_en, + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(63 downto 56) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(119 downto 112), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(55 downto 48) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(103 downto 96), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(47 downto 40) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(87 downto 80), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(39 downto 32) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(71 downto 64), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(31 downto 24) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(55 downto 48), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(23 downto 16) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(39 downto 32), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(15 downto 8) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(23 downto 16), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0\(7 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(7 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0), + freq_refclk => freq_refclk, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0), + \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + idelay_inc => idelay_inc, + idelay_ld_rst => idelay_ld_rst, + idelay_ld_rst_reg => \^a_rst_primitives_reg_0\, + if_empty_r(0) => if_empty_r(3), + if_empty_r_0(0) => if_empty_r_1(3), + ififo_rst_reg0 => ififo_rst_reg0, + in0 => in0, + init_complete_r1_timing_reg => init_complete_r1_timing_reg, + \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\, + mc_wrdata_en => mc_wrdata_en, + mem_dq_in(7 downto 0) => mem_dq_in(7 downto 0), + mem_dq_out(8 downto 0) => mem_dq_out(31 downto 23), + mem_dq_ts(8 downto 0) => mem_dq_ts(8 downto 0), + mem_dqs_in(0) => mem_dqs_in(0), + mem_refclk => mem_refclk, + mux_wrdata_en => mux_wrdata_en, + my_empty(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(3), + my_empty(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(0), + \my_empty_reg[1]\ => \my_empty_reg[1]_1\, + \my_empty_reg[3]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3), + \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0), + \my_empty_reg[4]_rep__0\ => \my_empty_reg[4]_rep__0\, + \not_strict_mode.app_rd_data_reg[0]\ => \not_strict_mode.app_rd_data_reg[8]\, + \not_strict_mode.app_rd_data_reg[101]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[103]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[115]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[19]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[21]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[33]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[37]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[39]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[49]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[51]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[55]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[67]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[69]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[7]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[81]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[85]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[87]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[97]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[99]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]\(1 downto 0), + ofifo_rst_reg0 => ofifo_rst_reg0, + ofs_rdy_r_reg(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2), + \out\(1 downto 0) => \out\(1 downto 0), + out_dqs_0 => out_dqs_0, + phy_mc_data_full => phy_mc_data_full, + phy_rddata_en => phy_rddata_en, + pi_dqs_found_lanes(0) => pi_dqs_found_lanes(0), + \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\, + \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\, + \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\, + \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\, + \pi_dqs_found_lanes_r1_reg[2]_3\ => \pi_dqs_found_lanes_r1_reg[2]_3\, + pi_phase_locked_all_r1_reg => \ddr_byte_lane_D.ddr_byte_lane_D_n_24\, + \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_5\, + \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_6\, + \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_7\, + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]_0\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]_0\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]_0\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]_0\, + \read_fifo.tail_r_reg[1]\ => \read_fifo.tail_r_reg_0_sn_1\, + sync_pulse => sync_pulse, + ts_dqs_0 => ts_dqs_0, + wr_en_2 => wr_en_2, + \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\, + \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0), + \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]_1\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D\: entity work.\ddr3_mig_7series_v4_2_ddr_byte_lane__parameterized2\ + port map ( + A_rst_primitives_reg => A_rst_primitives_reg_2, + A_rst_primitives_reg_0 => \ddr_byte_lane_D.ddr_byte_lane_D_n_24\, + A_rst_primitives_reg_1(8 downto 0) => D_po_counter_read_val(8 downto 0), + CLK => CLK, + CLKB0_4 => CLKB0_4, + COUNTERREADVAL(5 downto 0) => D_pi_counter_read_val(5 downto 0), + D0(7 downto 0) => D0(7 downto 0), + DIA(1 downto 0) => \^dia\(1 downto 0), + DIB(1 downto 0) => \^dib\(1 downto 0), + DIC(1 downto 0) => \^dic\(1 downto 0), + INBURSTPENDING(0) => phy_control_i_n_18, + INRANKD(1) => phy_control_i_n_10, + INRANKD(0) => phy_control_i_n_11, + LD0_0 => LD0_0, + OUTBURSTPENDING(0) => phy_control_i_n_22, + PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0), + Q(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0), + calib_wrdata_en => calib_wrdata_en, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(63 downto 56) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(127 downto 120), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(55 downto 48) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(111 downto 104), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(47 downto 40) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(95 downto 88), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(39 downto 32) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(79 downto 72), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(31 downto 24) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(63 downto 56), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(23 downto 16) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(47 downto 40), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(15 downto 8) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(31 downto 24), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(7 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(15 downto 8), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\(1 downto 0), + \entry_cnt_reg[4]\(2 downto 0) => \of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg\(4 downto 2), + freq_refclk => freq_refclk, + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0), + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd[1].mux_rd_fall2_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0), + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall3_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0), + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0), + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_rise3_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0), + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0), + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd[3].mux_rd_fall1_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0), + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd[3].mux_rd_fall2_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0), + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall3_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd[3].mux_rd_rise0_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd[3].mux_rd_rise1_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd[3].mux_rd_rise2_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0), + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_rise3_r_reg[3]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0), + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0), + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd[5].mux_rd_fall1_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0), + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd[5].mux_rd_fall2_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0), + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall3_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd[5].mux_rd_rise0_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd[5].mux_rd_rise1_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd[5].mux_rd_rise2_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0), + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_rise3_r_reg[5]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0), + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0), + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd[7].mux_rd_fall1_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0), + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd[7].mux_rd_fall2_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0), + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall3_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd[7].mux_rd_rise0_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd[7].mux_rd_rise1_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd[7].mux_rd_rise2_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0), + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_rise3_r_reg[7]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0), + idelay_inc => idelay_inc, + if_empty_r(0) => if_empty_r_1(3), + if_empty_r_0(0) => if_empty_r(3), + ififo_rst_reg0_1 => ififo_rst_reg0_1, + \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq_0\, + mc_wrdata_en => mc_wrdata_en, + mem_dq_in(7 downto 0) => mem_dq_in(15 downto 8), + mem_dq_out(8 downto 0) => mem_dq_out(40 downto 32), + mem_dq_ts(8 downto 0) => mem_dq_ts(17 downto 9), + mem_dqs_in(0) => mem_dqs_in(1), + mem_refclk => mem_refclk, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[0]\ => \my_empty_reg[0]\, + \my_empty_reg[0]_0\ => \my_empty_reg[0]_0\, + \my_empty_reg[1]\ => \my_empty_reg[1]_2\, + \my_empty_reg[3]\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(3), + \my_empty_reg[3]\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0\(0), + \my_empty_reg[4]_rep__1\ => \my_empty_reg[4]_rep__1\, + \my_empty_reg[4]_rep__2\(1) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(3), + \my_empty_reg[4]_rep__2\(0) => \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty\(0), + \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0), + \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0), + \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0), + \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0), + \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0), + \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0), + \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0), + \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0), + \not_strict_mode.app_rd_data[127]_i_2\(0) => \not_strict_mode.app_rd_data[127]_i_2\(0), + \not_strict_mode.app_rd_data_reg[105]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[109]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[111]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[121]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[123]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[13]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[15]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[25]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[27]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[31]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[43]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[45]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[57]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[61]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[63]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[73]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[75]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[79]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\, + \not_strict_mode.app_rd_data_reg[91]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[93]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[9]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]\(1 downto 0), + ofifo_rst_reg0_2 => ofifo_rst_reg0_2, + out_dqs_1 => out_dqs_1, + out_fifo_0 => out_fifo, + p_1_in => p_1_in, + pi_dqs_found_lanes(0) => pi_dqs_found_lanes(1), + \pi_dqs_found_lanes_r1_reg[3]\ => \^a_rst_primitives_reg_0\, + \pi_dqs_found_lanes_r1_reg[3]_0\ => \pi_dqs_found_lanes_r1_reg[3]\, + \pi_dqs_found_lanes_r1_reg[3]_1\ => \pi_dqs_found_lanes_r1_reg[3]_0\, + \pi_dqs_found_lanes_r1_reg[3]_2\ => \pi_dqs_found_lanes_r1_reg[3]_1\, + \pi_dqs_found_lanes_r1_reg[3]_3\ => \pi_dqs_found_lanes_r1_reg[3]_2\, + \pi_dqs_found_lanes_r1_reg[3]_4\ => \pi_dqs_found_lanes_r1_reg[3]_3\, + \pi_dqs_found_lanes_r1_reg[3]_5\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_4\(5 downto 0), + \po_counter_read_val_reg[8]\ => \po_counter_read_val_reg[8]_8\, + \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_9\, + \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_10\, + rd_data_en => rd_data_en, + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]_1\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]_1\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]_1\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]_1\, + \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + \read_fifo.tail_r_reg\(0) => \read_fifo.tail_r_reg\(0), + \read_fifo.tail_r_reg_0_sp_1\ => \read_fifo.tail_r_reg_0_sn_1\, + sync_pulse => sync_pulse, + ts_dqs_1 => ts_dqs_1, + wr_en => wr_en, + \wr_ptr_reg[0]\ => \wr_ptr_reg[0]_0\, + \wr_ptr_reg[1]\ => \wr_ptr_reg[1]_0\, + \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0), + \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]_1\ + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => A_pi_rst_div2 + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => B_pi_rst_div2 + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => C_pi_rst_div2 + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => D_pi_rst_div2 + ); +mcGo_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => rst_out_reg_n_0, + Q => D(0), + R => '0' + ); +phaser_ref_i: unisim.vcomponents.PHASER_REF + generic map( + IS_PWRDWN_INVERTED => '0', + IS_RST_INVERTED => '0' + ) + port map ( + CLKIN => freq_refclk, + LOCKED => \^ref_dll_lock\, + PWRDWN => '0', + RST => RST0 + ); +phy_control_i: unisim.vcomponents.PHY_CONTROL + generic map( + AO_TOGGLE => 1, + AO_WRLVL_EN => B"0000", + BURST_MODE => "TRUE", + CLK_RATIO => 4, + CMD_OFFSET => 8, + CO_DURATION => 1, + DATA_CTL_A_N => "FALSE", + DATA_CTL_B_N => "FALSE", + DATA_CTL_C_N => "TRUE", + DATA_CTL_D_N => "TRUE", + DISABLE_SEQ_MATCH => "TRUE", + DI_DURATION => 1, + DO_DURATION => 1, + EVENTS_DELAY => 18, + FOUR_WINDOW_CLOCKS => 63, + MULTI_REGION => "FALSE", + PHY_COUNT_ENABLE => "FALSE", + RD_CMD_OFFSET_0 => 10, + RD_CMD_OFFSET_1 => 10, + RD_CMD_OFFSET_2 => 10, + RD_CMD_OFFSET_3 => 10, + RD_DURATION_0 => 6, + RD_DURATION_1 => 6, + RD_DURATION_2 => 6, + RD_DURATION_3 => 6, + SYNC_MODE => "FALSE", + WR_CMD_OFFSET_0 => 8, + WR_CMD_OFFSET_1 => 8, + WR_CMD_OFFSET_2 => 8, + WR_CMD_OFFSET_3 => 8, + WR_DURATION_0 => 7, + WR_DURATION_1 => 7, + WR_DURATION_2 => 7, + WR_DURATION_3 => 7 + ) + port map ( + AUXOUTPUT(3) => phy_control_i_n_14, + AUXOUTPUT(2) => phy_control_i_n_15, + AUXOUTPUT(1) => phy_control_i_n_16, + AUXOUTPUT(0) => phy_control_i_n_17, + INBURSTPENDING(3) => phy_control_i_n_18, + INBURSTPENDING(2) => phy_control_i_n_19, + INBURSTPENDING(1) => phy_control_i_n_20, + INBURSTPENDING(0) => phy_control_i_n_21, + INRANKA(1) => phy_control_i_n_4, + INRANKA(0) => phy_control_i_n_5, + INRANKB(1) => phy_control_i_n_6, + INRANKB(0) => phy_control_i_n_7, + INRANKC(1) => phy_control_i_n_8, + INRANKC(0) => phy_control_i_n_9, + INRANKD(1) => phy_control_i_n_10, + INRANKD(0) => phy_control_i_n_11, + MEMREFCLK => mem_refclk, + OUTBURSTPENDING(3) => phy_control_i_n_22, + OUTBURSTPENDING(2) => phy_control_i_n_23, + OUTBURSTPENDING(1) => phy_control_i_n_24, + OUTBURSTPENDING(0) => phaser_ctl_bus(0), + PCENABLECALIB(1 downto 0) => phy_encalib(1 downto 0), + PHYCLK => CLK, + PHYCTLALMOSTFULL => phy_control_i_n_0, + PHYCTLEMPTY => phy_control_i_n_1, + PHYCTLFULL => phy_mc_ctl_full, + PHYCTLMSTREMPTY => phy_control_i_n_1, + PHYCTLREADY => phy_control_i_n_3, + PHYCTLWD(31 downto 25) => B"0000001", + PHYCTLWD(24 downto 17) => Q(10 downto 3), + PHYCTLWD(16 downto 3) => B"00000000000000", + PHYCTLWD(2 downto 0) => Q(2 downto 0), + PHYCTLWRENABLE => phy_ctl_wr_i2, + PLLLOCK => pll_locked, + READCALIBENABLE => phy_read_calib, + REFDLLLOCK => \^ref_dll_lock\, + RESET => phy_mc_ctl_full_r_reg(0), + SYNCIN => sync_pulse, + WRITECALIBENABLE => phy_write_calib + ); +\pi_counter_read_val_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_C.ddr_byte_lane_C_n_262\, + Q => \^pi_counter_read_val_reg[5]_1\(0), + R => '0' + ); +\pi_counter_read_val_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_C.ddr_byte_lane_C_n_261\, + Q => \^pi_counter_read_val_reg[5]_1\(1), + R => '0' + ); +\pi_counter_read_val_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_C.ddr_byte_lane_C_n_260\, + Q => \^pi_counter_read_val_reg[5]_1\(2), + R => '0' + ); +\pi_counter_read_val_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_C.ddr_byte_lane_C_n_259\, + Q => \^pi_counter_read_val_reg[5]_1\(3), + R => '0' + ); +\pi_counter_read_val_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_C.ddr_byte_lane_C_n_258\, + Q => \^pi_counter_read_val_reg[5]_1\(4), + R => '0' + ); +\pi_counter_read_val_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_C.ddr_byte_lane_C_n_257\, + Q => \^pi_counter_read_val_reg[5]_1\(5), + R => '0' + ); +\po_counter_read_val_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_31\, + Q => \po_counter_read_val_reg[8]_0\(0), + R => '0' + ); +\po_counter_read_val_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_30\, + Q => \po_counter_read_val_reg[8]_0\(1), + R => '0' + ); +\po_counter_read_val_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_29\, + Q => \po_counter_read_val_reg[8]_0\(2), + R => '0' + ); +\po_counter_read_val_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_28\, + Q => \po_counter_read_val_reg[8]_0\(3), + R => '0' + ); +\po_counter_read_val_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_27\, + Q => \po_counter_read_val_reg[8]_0\(4), + R => '0' + ); +\po_counter_read_val_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_26\, + Q => \po_counter_read_val_reg[8]_0\(5), + R => '0' + ); +\po_counter_read_val_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_25\, + Q => \po_counter_read_val_reg[8]_0\(6), + R => '0' + ); +\po_counter_read_val_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_24\, + Q => \po_counter_read_val_reg[8]_0\(7), + R => '0' + ); +\po_counter_read_val_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \ddr_byte_lane_B.ddr_byte_lane_B_n_23\, + Q => \po_counter_read_val_reg[8]_0\(8), + R => '0' + ); +\rclk_delay_reg[10]_srl11\: unisim.vcomponents.SRL16E + port map ( + A0 => '0', + A1 => '1', + A2 => '0', + A3 => '1', + CE => '1', + CLK => CLK, + D => \rclk_delay_reg[10]_srl11_i_1_n_0\, + Q => \rclk_delay_reg[10]_srl11_n_0\ + ); +\rclk_delay_reg[10]_srl11_i_1\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => rst_primitives, + O => \rclk_delay_reg[10]_srl11_i_1_n_0\ + ); +\rclk_delay_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \rclk_delay_reg[10]_srl11_n_0\, + Q => rclk_delay_11, + R => '0' + ); +rst_out_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => rclk_delay_11, + I1 => rst_out_reg_n_0, + O => rst_out_i_1_n_0 + ); +rst_out_reg: unisim.vcomponents.FDCE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + CLR => SR(0), + D => rst_out_i_1_n_0, + Q => rst_out_reg_n_0 + ); +rst_primitives_i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => phy_control_i_n_3, + O => rst_primitives_i_1_n_0 + ); +rst_primitives_reg: unisim.vcomponents.FDRE + generic map( + INIT => '0' + ) + port map ( + C => CLK, + CE => '1', + D => rst_primitives_i_1_n_0, + Q => rst_primitives, + R => '0' + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_rank_mach is + port ( + \periodic_rd_generation.read_this_rank_r\ : out STD_LOGIC; + inhbt_act_faw_r : out STD_LOGIC; + maint_req_r : out STD_LOGIC; + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + maint_zq_r : out STD_LOGIC; + maint_srx_r : out STD_LOGIC; + \periodic_read_request.periodic_rd_r_lcl_reg\ : out STD_LOGIC; + \periodic_read_request.periodic_rd_grant_r\ : out STD_LOGIC; + app_sr_active : out STD_LOGIC; + maint_ref_zq_wip : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 0 to 0 ); + wait_for_maint_r_lcl_reg : out STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : out STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : out STD_LOGIC; + wait_for_maint_r_lcl_reg_2 : out STD_LOGIC; + \rstdiv0_sync_r1_reg_rep__13\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + I120 : out STD_LOGIC_VECTOR ( 0 to 0 ); + S : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[15]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[19]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + q_has_rd_r_reg : out STD_LOGIC; + q_has_rd_r_reg_0 : out STD_LOGIC; + q_has_rd_r_reg_1 : out STD_LOGIC; + q_has_rd_r_reg_2 : out STD_LOGIC; + \maintenance_request.maint_sre_r_lcl_reg\ : out STD_LOGIC; + \maintenance_request.maint_req_r_lcl_reg\ : out STD_LOGIC; + \maintenance_request.maint_rank_r_lcl_reg[0]\ : out STD_LOGIC; + \maintenance_request.maint_sre_r_lcl_reg_0\ : out STD_LOGIC; + \maintenance_request.maint_srx_r_lcl_reg\ : out STD_LOGIC; + act_this_rank : in STD_LOGIC; + CLK : in STD_LOGIC; + \periodic_rd_generation.read_this_rank\ : in STD_LOGIC; + \maintenance_request.maint_zq_r_lcl_reg\ : in STD_LOGIC; + \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC; + \periodic_read_request.periodic_rd_r_lcl_reg_0\ : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + O : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \grant_r_reg[0]\ : in STD_LOGIC; + insert_maint_r1 : in STD_LOGIC; + maint_wip_r : in STD_LOGIC; + \periodic_read_request.periodic_rd_r_lcl_reg_1\ : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ : in STD_LOGIC; + clear_periodic_rd_request : in STD_LOGIC; + app_zq_req : in STD_LOGIC; + app_sr_req : in STD_LOGIC; + \last_master_r_reg[2]\ : in STD_LOGIC; + \wtr_timer.wtr_cnt_r_reg[0]\ : in STD_LOGIC; + wait_for_maint_r : in STD_LOGIC; + wait_for_maint_r_lcl_reg_3 : in STD_LOGIC; + wait_for_maint_r_0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_4 : in STD_LOGIC; + wait_for_maint_r_1 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_5 : in STD_LOGIC; + wait_for_maint_r_2 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_6 : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\ : in STD_LOGIC; + \inhbt_act_faw.inhbt_act_faw_r_reg\ : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ : in STD_LOGIC; + cke_r : in STD_LOGIC; + q_has_rd : in STD_LOGIC; + idle_r : in STD_LOGIC_VECTOR ( 3 downto 0 ); + q_has_rd_3 : in STD_LOGIC; + q_has_rd_4 : in STD_LOGIC; + q_has_rd_5 : in STD_LOGIC; + auto_pre_r_lcl_reg : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_rank_mach : entity is "mig_7series_v4_2_rank_mach"; +end ddr3_mig_7series_v4_2_rank_mach; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_rank_mach is + signal app_ref_r : STD_LOGIC; + signal maint_prescaler_tick_r : STD_LOGIC; + signal \periodic_rd_generation.periodic_rd_cntr1_r\ : STD_LOGIC; + signal \periodic_rd_generation.periodic_rd_request_r\ : STD_LOGIC; + signal \rank_cntrl[0].rank_cntrl0_n_6\ : STD_LOGIC; + signal rank_common0_n_11 : STD_LOGIC; + signal rank_common0_n_17 : STD_LOGIC; + signal \refresh_generation.refresh_bank_r\ : STD_LOGIC; +begin +\rank_cntrl[0].rank_cntrl0\: entity work.ddr3_mig_7series_v4_2_rank_cntrl + port map ( + CLK => CLK, + Q(0) => Q(0), + SR(0) => SR(0), + act_this_rank => act_this_rank, + app_ref_r => app_ref_r, + app_ref_req => app_ref_req, + app_ref_req_0 => \rank_cntrl[0].rank_cntrl0_n_6\, + clear_periodic_rd_request => clear_periodic_rd_request, + \inhbt_act_faw.inhbt_act_faw_r_reg_0\ => \inhbt_act_faw.inhbt_act_faw_r_reg\, + inhbt_act_faw_r => inhbt_act_faw_r, + maint_prescaler_tick_r => maint_prescaler_tick_r, + \periodic_rd_generation.periodic_rd_cntr1_r\ => \periodic_rd_generation.periodic_rd_cntr1_r\, + \periodic_rd_generation.periodic_rd_cntr1_r_reg_0\ => rank_common0_n_11, + \periodic_rd_generation.periodic_rd_request_r\ => \periodic_rd_generation.periodic_rd_request_r\, + \periodic_rd_generation.periodic_rd_request_r_reg_0\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\, + \periodic_rd_generation.periodic_rd_request_r_reg_1\ => \grant_r_reg[0]\, + \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1\ => \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\, + \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\, + \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\, + \refresh_generation.refresh_bank_r\ => \refresh_generation.refresh_bank_r\, + \refresh_generation.refresh_bank_r_reg[0]_0\ => rank_common0_n_17, + \wtr_timer.wtr_cnt_r_reg[0]_0\ => \wtr_timer.wtr_cnt_r_reg[0]\, + \wtr_timer.wtr_cnt_r_reg[1]_0\ => \last_master_r_reg[2]\ + ); +rank_common0: entity work.ddr3_mig_7series_v4_2_rank_common + port map ( + CLK => CLK, + I120(0) => I120(0), + O(3 downto 0) => O(3 downto 0), + S(3 downto 0) => S(3 downto 0), + SR(0) => SR(0), + app_ref_ack => app_ref_ack, + app_ref_r => app_ref_r, + app_ref_r_reg_0 => \rank_cntrl[0].rank_cntrl0_n_6\, + app_ref_req => app_ref_req, + app_sr_active => app_sr_active, + app_sr_req => app_sr_req, + app_zq_ack => app_zq_ack, + app_zq_req => app_zq_req, + auto_pre_r_lcl_reg => auto_pre_r_lcl_reg, + cke_r => cke_r, + \grant_r_reg[0]\ => \grant_r_reg[0]\, + idle_r(3 downto 0) => idle_r(3 downto 0), + \init_calib_complete_reg_rep__9\ => rank_common0_n_17, + insert_maint_r1 => insert_maint_r1, + \last_master_r_reg[2]\ => \last_master_r_reg[2]\, + maint_prescaler_tick_r => maint_prescaler_tick_r, + maint_ref_zq_wip => maint_ref_zq_wip, + maint_wip_r => maint_wip_r, + \maintenance_request.maint_rank_r_lcl_reg[0]_0\ => \maintenance_request.maint_rank_r_lcl_reg[0]\, + \maintenance_request.maint_req_r_lcl_reg_0\ => maint_req_r, + \maintenance_request.maint_req_r_lcl_reg_1\ => \maintenance_request.maint_req_r_lcl_reg\, + \maintenance_request.maint_sre_r_lcl_reg_0\ => \maintenance_request.maint_sre_r_lcl_reg\, + \maintenance_request.maint_sre_r_lcl_reg_1\ => \maintenance_request.maint_sre_r_lcl_reg_0\, + \maintenance_request.maint_srx_r_lcl_reg_0\ => maint_srx_r, + \maintenance_request.maint_srx_r_lcl_reg_1\ => \maintenance_request.maint_srx_r_lcl_reg\, + \maintenance_request.maint_zq_r_lcl_reg_0\ => maint_zq_r, + \maintenance_request.maint_zq_r_lcl_reg_1\ => \maintenance_request.maint_zq_r_lcl_reg\, + \periodic_rd_generation.periodic_rd_cntr1_r\ => \periodic_rd_generation.periodic_rd_cntr1_r\, + \periodic_rd_generation.periodic_rd_request_r\ => \periodic_rd_generation.periodic_rd_request_r\, + \periodic_read_request.periodic_rd_grant_r\ => \periodic_read_request.periodic_rd_grant_r\, + \periodic_read_request.periodic_rd_grant_r_reg[0]_0\ => rank_common0_n_11, + \periodic_read_request.periodic_rd_r_lcl_reg_0\ => \periodic_read_request.periodic_rd_r_lcl_reg\, + \periodic_read_request.periodic_rd_r_lcl_reg_1\ => \periodic_read_request.periodic_rd_r_lcl_reg_0\, + \periodic_read_request.periodic_rd_r_lcl_reg_2\ => \periodic_read_request.periodic_rd_r_lcl_reg_1\, + q_has_rd => q_has_rd, + q_has_rd_3 => q_has_rd_3, + q_has_rd_4 => q_has_rd_4, + q_has_rd_5 => q_has_rd_5, + q_has_rd_r_reg => q_has_rd_r_reg, + q_has_rd_r_reg_0 => q_has_rd_r_reg_0, + q_has_rd_r_reg_1 => q_has_rd_r_reg_1, + q_has_rd_r_reg_2 => q_has_rd_r_reg_2, + \refresh_generation.refresh_bank_r\ => \refresh_generation.refresh_bank_r\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\, + \rstdiv0_sync_r1_reg_rep__13\(0) => \rstdiv0_sync_r1_reg_rep__13\(0), + wait_for_maint_r => wait_for_maint_r, + wait_for_maint_r_0 => wait_for_maint_r_0, + wait_for_maint_r_1 => wait_for_maint_r_1, + wait_for_maint_r_2 => wait_for_maint_r_2, + wait_for_maint_r_lcl_reg => wait_for_maint_r_lcl_reg, + wait_for_maint_r_lcl_reg_0 => wait_for_maint_r_lcl_reg_0, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_1, + wait_for_maint_r_lcl_reg_2 => wait_for_maint_r_lcl_reg_2, + wait_for_maint_r_lcl_reg_3 => wait_for_maint_r_lcl_reg_3, + wait_for_maint_r_lcl_reg_4 => wait_for_maint_r_lcl_reg_4, + wait_for_maint_r_lcl_reg_5 => wait_for_maint_r_lcl_reg_5, + wait_for_maint_r_lcl_reg_6 => wait_for_maint_r_lcl_reg_6, + \zq_cntrl.zq_request_logic.zq_request_r_reg_0\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(3 downto 0), + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3 downto 0), + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(3 downto 0), + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3 downto 0), + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(3 downto 0), + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3 downto 0), + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(3 downto 0), + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1\(3 downto 0) => \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3 downto 0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_bank_mach is + port ( + sent_col : out STD_LOGIC; + insert_maint_r1 : out STD_LOGIC; + \generate_maint_cmds.insert_maint_r_lcl_reg\ : out STD_LOGIC; + DIC : out STD_LOGIC_VECTOR ( 0 to 0 ); + col_rd_wr : out STD_LOGIC; + col_data_buf_addr : out STD_LOGIC_VECTOR ( 4 downto 0 ); + cke_r : out STD_LOGIC; + idle_r : out STD_LOGIC_VECTOR ( 3 downto 0 ); + q_has_rd : out STD_LOGIC; + q_has_rd_0 : out STD_LOGIC; + q_has_rd_1 : out STD_LOGIC; + q_has_rd_2 : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg : out STD_LOGIC; + accept_ns : out STD_LOGIC; + wait_for_maint_r : out STD_LOGIC; + wait_for_maint_r_3 : out STD_LOGIC; + wait_for_maint_r_4 : out STD_LOGIC; + wait_for_maint_r_5 : out STD_LOGIC; + maint_wip_r : out STD_LOGIC; + periodic_rd_cntr_r_reg : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + periodic_rd_ack_r_lcl_reg_0 : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_1 : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_2 : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg_3 : out STD_LOGIC; + I121 : out STD_LOGIC_VECTOR ( 0 to 0 ); + D : out STD_LOGIC_VECTOR ( 2 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + idle_r_lcl_reg : out STD_LOGIC; + idle_r_lcl_reg_0 : out STD_LOGIC; + idle_r_lcl_reg_1 : out STD_LOGIC; + idle_r_lcl_reg_2 : out STD_LOGIC; + granted_col_r_reg : out STD_LOGIC; + \periodic_rd_generation.read_this_rank_r_reg\ : out STD_LOGIC; + \periodic_rd_generation.read_this_rank\ : out STD_LOGIC; + I119 : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_aux_out0_1 : out STD_LOGIC; + granted_col_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + clear_periodic_rd_request : out STD_LOGIC; + \grant_r_reg[0]\ : out STD_LOGIC; + mc_cas_n_ns : out STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_ras_n_ns : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \pre_4_1_1T_arb.granted_pre_r_reg\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + act_this_rank : out STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : out STD_LOGIC; + \pre_4_1_1T_arb.granted_pre_r_reg_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_bank_r_lcl_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_bank_r_lcl_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + CLK : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + I120 : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg : in STD_LOGIC; + rb_hit_busy_r_reg_0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + rb_hit_busy_r_reg_2 : in STD_LOGIC; + phy_mc_ctl_full : in STD_LOGIC; + phy_mc_cmd_full : in STD_LOGIC; + was_wr0 : in STD_LOGIC; + maint_srx_r : in STD_LOGIC; + rnk_config_valid_r_lcl_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + wait_for_maint_r_lcl_reg : in STD_LOGIC; + wait_for_maint_r_lcl_reg_0 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_1 : in STD_LOGIC; + wait_for_maint_r_lcl_reg_2 : in STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + periodic_rd_cntr_r_reg_0 : in STD_LOGIC; + col_wait_r_reg : in STD_LOGIC; + \maint_controller.maint_hit_busies_r_reg[3]\ : in STD_LOGIC; + q_has_rd_r_reg : in STD_LOGIC; + \maint_controller.maint_wip_r_lcl_reg\ : in STD_LOGIC; + q_has_rd_r_reg_0 : in STD_LOGIC; + q_has_rd_r_reg_1 : in STD_LOGIC; + q_has_rd_r_reg_2 : in STD_LOGIC; + was_priority_reg : in STD_LOGIC; + app_en_r2 : in STD_LOGIC; + maint_req_r : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\ : in STD_LOGIC; + maint_zq_r : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]\ : in STD_LOGIC; + \periodic_rd_generation.read_this_rank_r\ : in STD_LOGIC; + \cmd_pipe_plus.mc_odt_reg[0]\ : in STD_LOGIC; + \periodic_read_request.periodic_rd_grant_r\ : in STD_LOGIC; + auto_pre_r_lcl_reg : in STD_LOGIC; + accept_internal_r_reg : in STD_LOGIC; + rd_wr_r_lcl_reg : in STD_LOGIC; + pass_open_bank_r_lcl_reg : in STD_LOGIC; + inhbt_act_faw_r : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + phy_mc_data_full : in STD_LOGIC; + \grant_r[3]_i_4\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rtp_timer_r_reg[0]\ : in STD_LOGIC; + \req_data_buf_addr_r_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \q_entry_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_bank_mach : entity is "mig_7series_v4_2_bank_mach"; +end ddr3_mig_7series_v4_2_bank_mach; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_bank_mach is + signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal act_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal arb_mux0_n_23 : STD_LOGIC; + signal arb_mux0_n_32 : STD_LOGIC; + signal arb_mux0_n_36 : STD_LOGIC; + signal arb_mux0_n_37 : STD_LOGIC; + signal arb_mux0_n_39 : STD_LOGIC; + signal arb_mux0_n_40 : STD_LOGIC; + signal arb_mux0_n_43 : STD_LOGIC; + signal arb_mux0_n_46 : STD_LOGIC; + signal \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns\ : STD_LOGIC; + signal \arb_row_col0/rnk_config_strobe_ns\ : STD_LOGIC; + signal auto_pre_r : STD_LOGIC; + signal auto_pre_r_10 : STD_LOGIC; + signal auto_pre_r_15 : STD_LOGIC; + signal auto_pre_r_3 : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_20\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_21\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_23\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_24\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_25\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_26\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_27\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_28\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_29\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_30\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_31\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_32\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_34\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_35\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_36\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_37\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_38\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_39\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_40\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_41\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_42\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_43\ : STD_LOGIC; + signal \bank_cntrl[0].bank0_n_44\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_18\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_19\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_20\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_21\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_23\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_24\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_26\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_27\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_28\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_29\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_30\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_31\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_32\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_33\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_34\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_50\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_51\ : STD_LOGIC; + signal \bank_cntrl[1].bank0_n_52\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_16\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_18\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_19\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_20\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_22\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_23\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_24\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_25\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_26\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_27\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_28\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_30\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_31\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_32\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_33\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_49\ : STD_LOGIC; + signal \bank_cntrl[2].bank0_n_50\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_18\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_19\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_21\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_22\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_23\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_24\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_25\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_26\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_27\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_28\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_29\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_30\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_31\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_32\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_34\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_35\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_51\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_52\ : STD_LOGIC; + signal \bank_cntrl[3].bank0_n_53\ : STD_LOGIC; + signal bank_common0_n_11 : STD_LOGIC; + signal bank_common0_n_12 : STD_LOGIC; + signal bank_common0_n_13 : STD_LOGIC; + signal bank_common0_n_14 : STD_LOGIC; + signal bank_common0_n_15 : STD_LOGIC; + signal bank_common0_n_21 : STD_LOGIC; + signal bank_common0_n_22 : STD_LOGIC; + signal bank_common0_n_5 : STD_LOGIC; + signal bank_common0_n_8 : STD_LOGIC; + signal bank_common0_n_9 : STD_LOGIC; + signal \bank_compare0/req_col_r\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \bank_compare0/req_col_r_14\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \bank_compare0/req_col_r_2\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \bank_compare0/req_col_r_9\ : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal \bank_state0/col_wait_r\ : STD_LOGIC; + signal \bank_state0/col_wait_r_20\ : STD_LOGIC; + signal \bank_state0/col_wait_r_8\ : STD_LOGIC; + signal \bank_state0/demand_act_priority_r\ : STD_LOGIC; + signal \bank_state0/demand_act_priority_r_13\ : STD_LOGIC; + signal \bank_state0/demand_act_priority_r_19\ : STD_LOGIC; + signal \bank_state0/demand_act_priority_r_7\ : STD_LOGIC; + signal \bank_state0/demand_priority_r\ : STD_LOGIC; + signal \bank_state0/demand_priority_r_12\ : STD_LOGIC; + signal \bank_state0/demand_priority_r_18\ : STD_LOGIC; + signal \bank_state0/demand_priority_r_6\ : STD_LOGIC; + signal \bank_state0/demanded_prior_r\ : STD_LOGIC; + signal \bank_state0/demanded_prior_r_11\ : STD_LOGIC; + signal \bank_state0/demanded_prior_r_17\ : STD_LOGIC; + signal \bank_state0/demanded_prior_r_5\ : STD_LOGIC; + signal \bank_state0/ofs_rdy_r\ : STD_LOGIC; + signal \bank_state0/ofs_rdy_r0\ : STD_LOGIC; + signal \bank_state0/ofs_rdy_r0_0\ : STD_LOGIC; + signal \bank_state0/ofs_rdy_r0_1\ : STD_LOGIC; + signal \bank_state0/ofs_rdy_r_16\ : STD_LOGIC; + signal \bank_state0/ofs_rdy_r_4\ : STD_LOGIC; + signal \bank_state0/override_demand_ns\ : STD_LOGIC; + signal \bank_state0/override_demand_r\ : STD_LOGIC; + signal bm_end : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^generate_maint_cmds.insert_maint_r_lcl_reg\ : STD_LOGIC; + signal head_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^idle_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^idle_r_lcl_reg_0\ : STD_LOGIC; + signal \^idle_r_lcl_reg_1\ : STD_LOGIC; + signal \^idle_r_lcl_reg_2\ : STD_LOGIC; + signal \maint_controller.maint_hit_busies_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \maint_controller.maint_rdy\ : STD_LOGIC; + signal \^maint_wip_r\ : STD_LOGIC; + signal ordered_r : STD_LOGIC; + signal ordered_r_lcl : STD_LOGIC; + signal p_9_in : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg_0\ : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg_1\ : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg_2\ : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg_3\ : STD_LOGIC; + signal \^periodic_rd_cntr_r_reg\ : STD_LOGIC; + signal periodic_rd_insert : STD_LOGIC; + signal rb_hit_busy_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rd_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal rd_wr_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^req_bank_r_lcl_reg[2]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^req_bank_r_lcl_reg[2]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^req_bank_r_lcl_reg[2]_1\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \^req_bank_r_lcl_reg[2]_2\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal req_data_buf_addr_r : STD_LOGIC_VECTOR ( 19 downto 0 ); + signal req_periodic_rd_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal req_row_r : STD_LOGIC_VECTOR ( 59 downto 15 ); + signal \^req_row_r_lcl_reg[14]\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal req_wr_r : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal rnk_config_valid_r : STD_LOGIC; + signal row_cmd_wr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal sending_pre : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal sending_row : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^sent_col\ : STD_LOGIC; + signal was_priority : STD_LOGIC; + signal was_wr : STD_LOGIC; + signal wr_this_rank_r : STD_LOGIC_VECTOR ( 3 downto 0 ); +begin + Q(3 downto 0) <= \^q\(3 downto 0); + \generate_maint_cmds.insert_maint_r_lcl_reg\ <= \^generate_maint_cmds.insert_maint_r_lcl_reg\; + idle_r(3 downto 0) <= \^idle_r\(3 downto 0); + idle_r_lcl_reg_0 <= \^idle_r_lcl_reg_0\; + idle_r_lcl_reg_1 <= \^idle_r_lcl_reg_1\; + idle_r_lcl_reg_2 <= \^idle_r_lcl_reg_2\; + maint_wip_r <= \^maint_wip_r\; + periodic_rd_ack_r_lcl_reg_0 <= \^periodic_rd_ack_r_lcl_reg_0\; + periodic_rd_ack_r_lcl_reg_1 <= \^periodic_rd_ack_r_lcl_reg_1\; + periodic_rd_ack_r_lcl_reg_2 <= \^periodic_rd_ack_r_lcl_reg_2\; + periodic_rd_ack_r_lcl_reg_3 <= \^periodic_rd_ack_r_lcl_reg_3\; + periodic_rd_cntr_r_reg <= \^periodic_rd_cntr_r_reg\; + \req_bank_r_lcl_reg[2]\(2 downto 0) <= \^req_bank_r_lcl_reg[2]\(2 downto 0); + \req_bank_r_lcl_reg[2]_0\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_0\(2 downto 0); + \req_bank_r_lcl_reg[2]_1\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_1\(2 downto 0); + \req_bank_r_lcl_reg[2]_2\(2 downto 0) <= \^req_bank_r_lcl_reg[2]_2\(2 downto 0); + \req_row_r_lcl_reg[14]\(14 downto 0) <= \^req_row_r_lcl_reg[14]\(14 downto 0); + sent_col <= \^sent_col\; +arb_mux0: entity work.ddr3_mig_7series_v4_2_arb_mux + port map ( + CLK => CLK, + D(2 downto 0) => D(2 downto 0), + DIC(0) => DIC(0), + I119(0) => I119(0), + I120(0) => I120(0), + I121(0) => I121(0), + Q(3 downto 0) => \^q\(3 downto 0), + SR(0) => SR(0), + act_this_rank => act_this_rank, + act_this_rank_r(3 downto 0) => act_this_rank_r(3 downto 0), + auto_pre_r => auto_pre_r_15, + auto_pre_r_7 => auto_pre_r, + auto_pre_r_8 => auto_pre_r_3, + auto_pre_r_9 => auto_pre_r_10, + cke_r => cke_r, + \cmd_pipe_plus.mc_address_reg[10]\ => \bank_cntrl[1].bank0_n_50\, + \cmd_pipe_plus.mc_address_reg[14]\(14 downto 0) => \^req_row_r_lcl_reg[14]\(14 downto 0), + \cmd_pipe_plus.mc_address_reg[24]\(9 downto 0) => \bank_compare0/req_col_r_14\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_0\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_1\(9 downto 0) => \bank_compare0/req_col_r_2\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[24]_2\(9 downto 0) => \bank_compare0/req_col_r_9\(9 downto 0), + \cmd_pipe_plus.mc_address_reg[40]\ => \bank_cntrl[2].bank0_n_50\, + \cmd_pipe_plus.mc_bank_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_0\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]_0\(2 downto 0) => \^req_bank_r_lcl_reg[2]_1\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[2]_1\(2 downto 0) => \^req_bank_r_lcl_reg[2]_2\(2 downto 0), + \cmd_pipe_plus.mc_bank_reg[8]\(2 downto 0) => \^req_bank_r_lcl_reg[2]\(2 downto 0), + \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0), + \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_odt_reg[0]\, + \cmd_pipe_plus.mc_ras_n_reg[0]\ => \maint_controller.maint_wip_r_lcl_reg\, + \cmd_pipe_plus.mc_we_n_reg[0]\ => \bank_cntrl[3].bank0_n_31\, + col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0), + \col_mux.col_periodic_rd_r_reg\ => col_wait_r_reg, + col_wait_r => \bank_state0/col_wait_r_8\, + col_wait_r_0 => \bank_state0/col_wait_r_20\, + col_wait_r_2 => \bank_state0/col_wait_r\, + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0), + demand_act_priority_r => \bank_state0/demand_act_priority_r\, + demand_act_priority_r_4 => \bank_state0/demand_act_priority_r_7\, + demand_act_priority_r_5 => \bank_state0/demand_act_priority_r_13\, + demand_act_priority_r_6 => \bank_state0/demand_act_priority_r_19\, + \grant_r[2]_i_3\ => \bank_cntrl[3].bank0_n_22\, + \grant_r[2]_i_3_0\ => \bank_cntrl[0].bank0_n_29\, + \grant_r[3]_i_3__0\ => \bank_cntrl[2].bank0_n_22\, + \grant_r[3]_i_3__0_0\ => \bank_cntrl[1].bank0_n_28\, + \grant_r[3]_i_4\(0) => \grant_r[3]_i_4\(0), + \grant_r[3]_i_4_0\ => \rtp_timer_r_reg[0]\, + \grant_r[3]_i_6\ => \bank_cntrl[0].bank0_n_25\, + \grant_r[3]_i_6_0\ => \bank_cntrl[3].bank0_n_29\, + \grant_r_reg[0]\ => \grant_r_reg[0]\, + \grant_r_reg[0]_0\ => \bank_cntrl[1].bank0_n_19\, + \grant_r_reg[0]_1\ => \bank_cntrl[3].bank0_n_30\, + \grant_r_reg[0]_2\ => \bank_cntrl[0].bank0_n_30\, + \grant_r_reg[0]_3\ => \bank_cntrl[2].bank0_n_27\, + \grant_r_reg[0]_4\ => \bank_cntrl[3].bank0_n_35\, + \grant_r_reg[0]_5\ => \bank_cntrl[2].bank0_n_33\, + \grant_r_reg[0]_6\ => \bank_cntrl[0].bank0_n_43\, + \grant_r_reg[1]\ => arb_mux0_n_40, + \grant_r_reg[1]_0\ => \bank_cntrl[2].bank0_n_25\, + \grant_r_reg[1]_1\ => \bank_cntrl[3].bank0_n_28\, + \grant_r_reg[1]_2\ => \bank_cntrl[1].bank0_n_34\, + \grant_r_reg[2]\ => \bank_cntrl[1].bank0_n_24\, + \grant_r_reg[2]_0\ => \bank_cntrl[3].bank0_n_18\, + \grant_r_reg[3]\ => col_rd_wr, + \grant_r_reg[3]_0\(3 downto 0) => sending_pre(3 downto 0), + \grant_r_reg[3]_1\(3 downto 0) => sending_row(3 downto 0), + \grant_r_reg[3]_2\ => arb_mux0_n_32, + \grant_r_reg[3]_3\ => \bank_cntrl[0].bank0_n_24\, + \grant_r_reg[3]_4\ => \bank_cntrl[0].bank0_n_42\, + \grant_r_reg[3]_5\ => \bank_cntrl[1].bank0_n_33\, + \grant_r_reg[3]_6\ => \bank_cntrl[2].bank0_n_32\, + \grant_r_reg[3]_7\ => \bank_cntrl[2].bank0_n_28\, + \grant_r_reg[3]_8\ => \bank_cntrl[3].bank0_n_34\, + granted_col_r_reg => \^sent_col\, + granted_col_r_reg_0 => granted_col_r_reg, + granted_col_r_reg_1(0) => granted_col_r_reg_0(0), + granted_col_r_reg_2 => \bank_cntrl[2].bank0_n_26\, + granted_row_r_reg => \bank_cntrl[0].bank0_n_41\, + granted_row_r_reg_0 => \bank_cntrl[1].bank0_n_31\, + inhbt_act_faw_r => inhbt_act_faw_r, + insert_maint_r1_lcl_reg => insert_maint_r1, + insert_maint_r1_lcl_reg_0 => \^generate_maint_cmds.insert_maint_r_lcl_reg\, + \last_master_r_reg[0]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\, + \last_master_r_reg[1]\(0) => arb_mux0_n_37, + maint_srx_r => maint_srx_r, + maint_zq_r => maint_zq_r, + mc_aux_out0_1 => mc_aux_out0_1, + mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0), + mc_ras_n_ns(1 downto 0) => mc_ras_n_ns(1 downto 0), + ofs_rdy_r => \bank_state0/ofs_rdy_r_16\, + ofs_rdy_r_1 => \bank_state0/ofs_rdy_r_4\, + ofs_rdy_r_3 => \bank_state0/ofs_rdy_r\, + ofs_rdy_r_reg => arb_mux0_n_36, + override_demand_ns => \bank_state0/override_demand_ns\, + \periodic_rd_generation.read_this_rank\ => \periodic_rd_generation.read_this_rank\, + \periodic_rd_generation.read_this_rank_r\ => \periodic_rd_generation.read_this_rank_r\, + \periodic_rd_generation.read_this_rank_r_reg\ => \periodic_rd_generation.read_this_rank_r_reg\, + \pre_4_1_1T_arb.granted_pre_ns\ => \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns\, + \pre_4_1_1T_arb.granted_pre_r_reg\(40 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg\(40 downto 0), + \pre_4_1_1T_arb.granted_pre_r_reg_0\(8 downto 0) => \pre_4_1_1T_arb.granted_pre_r_reg_0\(8 downto 0), + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 0), + rd_this_rank_r(3 downto 0) => rd_this_rank_r(3 downto 0), + rd_wr_r(3 downto 0) => rd_wr_r(3 downto 0), + rd_wr_r_lcl_reg => arb_mux0_n_43, + req_data_buf_addr_r(19 downto 0) => req_data_buf_addr_r(19 downto 0), + req_periodic_rd_r(3 downto 0) => req_periodic_rd_r(3 downto 0), + req_row_r(43 downto 10) => req_row_r(59 downto 26), + req_row_r(9 downto 0) => req_row_r(24 downto 15), + rnk_config_strobe_ns => \arb_row_col0/rnk_config_strobe_ns\, + \rnk_config_strobe_r_reg[0]\ => arb_mux0_n_23, + \rnk_config_strobe_r_reg[0]_0\ => arb_mux0_n_46, + rnk_config_valid_r => rnk_config_valid_r, + rnk_config_valid_r_lcl_reg(0) => rnk_config_valid_r_lcl_reg(0), + rnk_config_valid_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_23\, + row_cmd_wr(3 downto 0) => row_cmd_wr(3 downto 0), + wr_this_rank_r(3 downto 0) => wr_this_rank_r(3 downto 0), + \wtr_timer.wtr_cnt_r_reg[1]\ => arb_mux0_n_39 + ); +\bank_cntrl[0].bank0\: entity work.ddr3_mig_7series_v4_2_bank_cntrl + port map ( + CLK => CLK, + D(0) => \bank_cntrl[0].bank0_n_21\, + E(0) => \^idle_r\(0), + Q(0) => \maint_controller.maint_hit_busies_r\(0), + S(3 downto 0) => S(3 downto 0), + SR(0) => SR(0), + accept_internal_r_reg => accept_internal_r_reg, + accept_internal_r_reg_0 => \^idle_r_lcl_reg_0\, + accept_internal_r_reg_1 => \^idle_r_lcl_reg_2\, + accept_internal_r_reg_2 => \^idle_r_lcl_reg_1\, + act_this_rank_r(0) => act_this_rank_r(0), + act_wait_r_lcl_reg => \bank_cntrl[0].bank0_n_41\, + act_wait_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_42\, + act_wait_r_lcl_reg_1(0) => sending_row(0), + auto_pre_r => auto_pre_r, + auto_pre_r_lcl_reg => \bank_cntrl[0].bank0_n_43\, + auto_pre_r_lcl_reg_0 => auto_pre_r_lcl_reg, + bm_end(0) => bm_end(0), + bm_end_r1_reg => \bank_cntrl[0].bank0_n_27\, + bm_end_r1_reg_0 => \bank_cntrl[0].bank0_n_28\, + col_wait_r => \bank_state0/col_wait_r\, + col_wait_r_reg => \bank_cntrl[0].bank0_n_30\, + col_wait_r_reg_0 => \maint_controller.maint_wip_r_lcl_reg\, + \compute_tail.tail_r_lcl_reg\ => \bank_cntrl[3].bank0_n_21\, + \compute_tail.tail_r_lcl_reg_0\ => bank_common0_n_14, + demand_act_priority_r => \bank_state0/demand_act_priority_r\, + demand_priority_r => \bank_state0/demand_priority_r\, + demand_priority_r_2 => \bank_state0/demand_priority_r_18\, + demand_priority_r_reg => \bank_cntrl[0].bank0_n_44\, + demanded_prior_r => \bank_state0/demanded_prior_r\, + demanded_prior_r_3 => \bank_state0/demanded_prior_r_17\, + demanded_prior_r_reg(1) => \^q\(3), + demanded_prior_r_reg(0) => \^q\(0), + demanded_prior_r_reg_0 => \bank_cntrl[1].bank0_n_52\, + head_r(0) => head_r(0), + idle_r_lcl_reg => \bank_cntrl[0].bank0_n_20\, + idle_r_lcl_reg_0 => idle_r_lcl_reg, + idle_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_26\, + idle_r_lcl_reg_2 => \bank_cntrl[0].bank0_n_32\, + idle_r_lcl_reg_3 => \bank_cntrl[0].bank0_n_34\, + idle_r_lcl_reg_4 => \bank_cntrl[0].bank0_n_35\, + idle_r_lcl_reg_5 => \bank_cntrl[0].bank0_n_38\, + \maint_controller.maint_hit_busies_r_reg[0]\ => \maint_controller.maint_hit_busies_r_reg[3]\, + maint_req_r => maint_req_r, + ofs_rdy_r => \bank_state0/ofs_rdy_r\, + ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_1\, + ofs_rdy_r0_0 => \bank_state0/ofs_rdy_r0_0\, + ofs_rdy_r0_1 => \bank_state0/ofs_rdy_r0\, + ofs_rdy_r_reg(2 downto 0) => rd_wr_r(3 downto 1), + \order_q_r_reg[0]\ => \bank_cntrl[3].bank0_n_25\, + \order_q_r_reg[1]\ => \bank_cntrl[0].bank0_n_29\, + \order_q_r_reg[1]_0\ => \bank_cntrl[3].bank0_n_27\, + ordered_r => ordered_r, + override_demand_r => \bank_state0/override_demand_r\, + override_demand_r_reg => \bank_cntrl[0].bank0_n_25\, + p_9_in => p_9_in, + pass_open_bank_r_lcl_reg => \^periodic_rd_cntr_r_reg\, + pass_open_bank_r_lcl_reg_0 => \^maint_wip_r\, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg, + periodic_rd_insert => periodic_rd_insert, + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_data_full => phy_mc_data_full, + pre_bm_end_r_reg => \bank_cntrl[0].bank0_n_23\, + pre_bm_end_r_reg_0 => \bank_cntrl[0].bank0_n_36\, + pre_bm_end_r_reg_1 => \bank_cntrl[0].bank0_n_37\, + pre_bm_end_r_reg_2(0) => sending_pre(0), + pre_passing_open_bank_r_reg => \bank_cntrl[0].bank0_n_31\, + pre_wait_r_reg => col_wait_r_reg, + \q_entry_r_reg[0]\ => \^periodic_rd_ack_r_lcl_reg_0\, + \q_entry_r_reg[0]_0\(2 downto 0) => rb_hit_busy_r(3 downto 1), + \q_entry_r_reg[0]_1\ => bank_common0_n_11, + \q_entry_r_reg[1]\ => \bank_cntrl[0].bank0_n_24\, + \q_entry_r_reg[1]_0\(0) => \^idle_r\(1), + \q_entry_r_reg[1]_1\(0) => \^idle_r\(2), + \q_entry_r_reg[1]_2\(0) => \^idle_r\(3), + \q_entry_r_reg[1]_3\ => \bank_cntrl[3].bank0_n_53\, + \q_entry_r_reg[1]_4\(0) => \q_entry_r_reg[0]\(0), + q_has_priority_r_reg => bank_common0_n_12, + q_has_rd => q_has_rd, + q_has_rd_r_reg => q_has_rd_r_reg, + \ras_timer_r_reg[0]\ => \bank_cntrl[3].bank0_n_24\, + \ras_timer_r_reg[0]_0\ => \bank_cntrl[1].bank0_n_27\, + \ras_timer_r_reg[0]_1\ => \bank_cntrl[2].bank0_n_24\, + \ras_timer_r_reg[0]_2\ => \bank_cntrl[1].bank0_n_32\, + \ras_timer_r_reg[0]_3\ => \bank_cntrl[2].bank0_n_30\, + \ras_timer_r_reg[0]_4\ => \bank_cntrl[3].bank0_n_32\, + \ras_timer_r_reg[1]\ => \bank_cntrl[3].bank0_n_23\, + \ras_timer_r_reg[1]_0\ => \bank_cntrl[1].bank0_n_26\, + \ras_timer_r_reg[1]_1\ => \bank_cntrl[2].bank0_n_23\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]\ => \bank_cntrl[1].bank0_n_18\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0\ => rb_hit_busy_r_reg_0, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \bank_cntrl[2].bank0_n_18\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => rb_hit_busy_r_reg_1, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\ => rb_hit_busy_r_reg_2, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\(0) => bm_end(3), + rb_hit_busy_r(0) => rb_hit_busy_r(0), + rb_hit_busy_r_reg => \bank_cntrl[0].bank0_n_39\, + rb_hit_busy_r_reg_0 => \bank_cntrl[0].bank0_n_40\, + rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg, + rd_this_rank_r(0) => rd_this_rank_r(0), + rd_wr_r(0) => rd_wr_r(0), + rd_wr_r_lcl_reg => rd_wr_r_lcl_reg, + \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_0\(2 downto 0), + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0), + req_bank_rdy_r_reg => \bank_cntrl[3].bank0_n_26\, + \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r\(9 downto 0), + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(4 downto 0), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(0), + req_priority_r_reg => bank_common0_n_8, + \req_row_r_lcl_reg[14]\(14 downto 0) => \^req_row_r_lcl_reg[14]\(14 downto 0), + req_wr_r(0) => req_wr_r(0), + req_wr_r_lcl0 => req_wr_r_lcl0, + \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[3].bank0_n_51\, + \rnk_config_strobe_r_reg[0]_0\ => arb_mux0_n_46, + row(14 downto 0) => row(14 downto 0), + row_cmd_wr(0) => row_cmd_wr(0), + row_hit_r_reg(0) => row_hit_r_reg(0), + \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\, + \starve_limit_cntr_r_reg[0]\ => \^sent_col\, + wait_for_maint_r_lcl_reg => wait_for_maint_r, + wait_for_maint_r_lcl_reg_0 => bank_common0_n_5, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg, + was_priority => was_priority, + was_wr => was_wr, + wr_this_rank_r(0) => wr_this_rank_r(0) + ); +\bank_cntrl[1].bank0\: entity work.\ddr3_mig_7series_v4_2_bank_cntrl__parameterized0\ + port map ( + CLK => CLK, + D(0) => \bank_cntrl[1].bank0_n_21\, + E(0) => \^idle_r\(1), + Q(2 downto 0) => \^q\(2 downto 0), + SR(0) => SR(0), + act_this_rank_r(0) => act_this_rank_r(1), + act_wait_r_lcl_reg => \bank_cntrl[1].bank0_n_31\, + act_wait_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_33\, + auto_pre_r => auto_pre_r_3, + auto_pre_r_lcl_reg => \bank_cntrl[1].bank0_n_34\, + auto_pre_r_lcl_reg_0 => auto_pre_r_lcl_reg, + bm_end_r1_reg => \bank_cntrl[1].bank0_n_26\, + bm_end_r1_reg_0 => \bank_cntrl[1].bank0_n_27\, + \cmd_pipe_plus.mc_address_reg[10]\(1) => sending_row(3), + \cmd_pipe_plus.mc_address_reg[10]\(0) => sending_row(1), + \cmd_pipe_plus.mc_address_reg[10]_0\ => arb_mux0_n_32, + \cmd_pipe_plus.mc_address_reg[10]_1\(0) => row_cmd_wr(3), + \cmd_pipe_plus.mc_address_reg[10]_2\(0) => req_row_r(55), + col_wait_r => \bank_state0/col_wait_r_8\, + col_wait_r_reg => \bank_cntrl[1].bank0_n_24\, + col_wait_r_reg_0 => col_wait_r_reg, + \compute_tail.tail_r_lcl_reg\ => \^periodic_rd_ack_r_lcl_reg_1\, + \compute_tail.tail_r_lcl_reg_0\ => bank_common0_n_13, + \compute_tail.tail_r_lcl_reg_1\ => \bank_cntrl[2].bank0_n_19\, + demand_act_priority_r => \bank_state0/demand_act_priority_r_7\, + demand_priority_r => \bank_state0/demand_priority_r_6\, + demand_priority_r_0 => \bank_state0/demand_priority_r_12\, + demand_priority_r_reg => \bank_cntrl[1].bank0_n_51\, + demanded_prior_r => \bank_state0/demanded_prior_r_5\, + demanded_prior_r_1 => \bank_state0/demanded_prior_r_11\, + demanded_prior_r_reg => \bank_cntrl[1].bank0_n_52\, + demanded_prior_r_reg_0 => \bank_cntrl[3].bank0_n_52\, + head_r(0) => head_r(1), + head_r_lcl_reg => \bank_cntrl[0].bank0_n_20\, + head_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_40\, + idle_r_lcl_reg => \bank_cntrl[1].bank0_n_20\, + idle_r_lcl_reg_0 => \^idle_r_lcl_reg_2\, + \maint_controller.maint_hit_busies_r_reg[1]\(0) => \maint_controller.maint_hit_busies_r\(1), + \maint_controller.maint_hit_busies_r_reg[1]_0\ => \maint_controller.maint_hit_busies_r_reg[3]\, + maint_req_r => maint_req_r, + ofs_rdy_r => \bank_state0/ofs_rdy_r_4\, + ofs_rdy_r0 => \bank_state0/ofs_rdy_r0\, + \order_q_r_reg[0]\ => \bank_cntrl[3].bank0_n_25\, + \order_q_r_reg[1]\ => \bank_cntrl[1].bank0_n_28\, + \order_q_r_reg[1]_0\ => \bank_cntrl[3].bank0_n_27\, + ordered_r_lcl => ordered_r_lcl, + pass_open_bank_r_lcl_reg => \^periodic_rd_cntr_r_reg\, + pass_open_bank_r_lcl_reg_0 => \^maint_wip_r\, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg, + periodic_rd_insert => periodic_rd_insert, + pre_bm_end_r_reg => \bank_cntrl[1].bank0_n_18\, + pre_bm_end_r_reg_0(0) => sending_pre(1), + pre_passing_open_bank_r_reg => \bank_cntrl[1].bank0_n_32\, + pre_wait_r_reg => \maint_controller.maint_wip_r_lcl_reg\, + \q_entry_r_reg[0]\(0) => \^idle_r\(0), + \q_entry_r_reg[0]_0\(0) => \^idle_r\(2), + \q_entry_r_reg[0]_1\(0) => \^idle_r\(3), + \q_entry_r_reg[0]_2\ => \bank_cntrl[0].bank0_n_39\, + \q_entry_r_reg[0]_3\ => \bank_cntrl[0].bank0_n_38\, + \q_entry_r_reg[1]\ => \bank_cntrl[1].bank0_n_19\, + \q_entry_r_reg[1]_0\ => \bank_cntrl[3].bank0_n_53\, + \q_entry_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_26\, + \q_entry_r_reg[1]_2\(0) => \q_entry_r_reg[0]\(0), + q_has_priority_r_reg => bank_common0_n_12, + q_has_rd_0 => q_has_rd_0, + q_has_rd_r_reg => q_has_rd_r_reg_1, + \ras_timer_r_reg[0]\ => \bank_cntrl[0].bank0_n_28\, + \ras_timer_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_24\, + \ras_timer_r_reg[0]_1\ => \bank_cntrl[2].bank0_n_24\, + \ras_timer_r_reg[0]_2\ => \bank_cntrl[2].bank0_n_30\, + \ras_timer_r_reg[0]_3\ => \bank_cntrl[0].bank0_n_31\, + \ras_timer_r_reg[0]_4\ => \bank_cntrl[3].bank0_n_32\, + \ras_timer_r_reg[1]\ => \bank_cntrl[0].bank0_n_27\, + \ras_timer_r_reg[1]_0\ => \bank_cntrl[2].bank0_n_23\, + \ras_timer_r_reg[1]_1\ => \bank_cntrl[3].bank0_n_23\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]\ => \bank_cntrl[2].bank0_n_18\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0\ => rb_hit_busy_r_reg_1, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(1) => bm_end(3), + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0) => bm_end(0), + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => rb_hit_busy_r_reg_2, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => rb_hit_busy_r_reg, + rb_hit_busy_r_reg(0) => rb_hit_busy_r(1), + rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0, + rd_this_rank_r(0) => rd_this_rank_r(1), + rd_wr_r(0) => rd_wr_r(0), + rd_wr_r_lcl_reg(0) => rd_wr_r(1), + rd_wr_r_lcl_reg_0 => \bank_cntrl[1].bank0_n_30\, + rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg, + \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_1\(2 downto 0), + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0), + req_bank_rdy_r_i_2(0) => req_wr_r(0), + req_bank_rdy_r_reg => \bank_cntrl[3].bank0_n_26\, + \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_2\(9 downto 0), + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(9 downto 5), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(1), + req_priority_r_reg => bank_common0_n_8, + \req_row_r_lcl_reg[10]\ => \bank_cntrl[1].bank0_n_50\, + \req_row_r_lcl_reg[14]\(14 downto 0) => req_row_r(29 downto 15), + req_wr_r_lcl0 => req_wr_r_lcl0, + req_wr_r_lcl_reg => \bank_cntrl[1].bank0_n_29\, + rnk_config_strobe_ns => \arb_row_col0/rnk_config_strobe_ns\, + \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[2].bank0_n_27\, + \rnk_config_strobe_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_30\, + \rnk_config_strobe_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_30\, + \rnk_config_strobe_r_reg[0]_2\ => \bank_cntrl[2].bank0_n_49\, + \rnk_config_strobe_r_reg[0]_3\ => arb_mux0_n_46, + rnk_config_valid_r => rnk_config_valid_r, + rnk_config_valid_r_lcl_reg => \bank_cntrl[1].bank0_n_23\, + row(14 downto 0) => row(14 downto 0), + row_cmd_wr(0) => row_cmd_wr(1), + \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\, + \starve_limit_cntr_r_reg[0]\ => \^sent_col\, + wait_for_maint_r_lcl_reg => wait_for_maint_r_3, + wait_for_maint_r_lcl_reg_0 => bank_common0_n_5, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_0, + was_priority => was_priority, + was_wr => was_wr, + wr_this_rank_r(0) => wr_this_rank_r(1) + ); +\bank_cntrl[2].bank0\: entity work.\ddr3_mig_7series_v4_2_bank_cntrl__parameterized1\ + port map ( + CLK => CLK, + D(0) => \bank_cntrl[2].bank0_n_20\, + E(0) => \^idle_r\(2), + Q(1 downto 0) => \^q\(2 downto 1), + SR(0) => SR(0), + act_this_rank_r(0) => act_this_rank_r(2), + act_wait_r_lcl_reg => \bank_cntrl[2].bank0_n_28\, + act_wait_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_32\, + act_wait_r_lcl_reg_1 => \bank_cntrl[2].bank0_n_50\, + act_wait_r_lcl_reg_2(0) => sending_row(2), + auto_pre_r => auto_pre_r_10, + auto_pre_r_lcl_reg => \bank_cntrl[2].bank0_n_33\, + auto_pre_r_lcl_reg_0 => auto_pre_r_lcl_reg, + bm_end_r1_reg => \bank_cntrl[2].bank0_n_23\, + bm_end_r1_reg_0 => \bank_cntrl[2].bank0_n_24\, + \cmd_pipe_plus.mc_address_reg[40]\(0) => row_cmd_wr(1), + \cmd_pipe_plus.mc_address_reg[40]_0\(0) => req_row_r(25), + col_wait_r_reg => \bank_cntrl[2].bank0_n_25\, + col_wait_r_reg_0 => \bank_cntrl[2].bank0_n_27\, + col_wait_r_reg_1 => col_wait_r_reg, + \compute_tail.tail_r_lcl_reg\ => \^periodic_rd_ack_r_lcl_reg_2\, + \compute_tail.tail_r_lcl_reg_0\ => \bank_cntrl[0].bank0_n_36\, + \compute_tail.tail_r_lcl_reg_1\ => bank_common0_n_22, + demand_act_priority_r => \bank_state0/demand_act_priority_r_13\, + demand_priority_r => \bank_state0/demand_priority_r_12\, + demand_priority_r_1 => \bank_state0/demand_priority_r_6\, + demand_priority_r_reg => \bank_cntrl[2].bank0_n_49\, + demanded_prior_r => \bank_state0/demanded_prior_r_11\, + demanded_prior_r_0 => \bank_state0/demanded_prior_r_5\, + demanded_prior_r_reg => \bank_cntrl[3].bank0_n_52\, + \grant_r[1]_i_2\ => arb_mux0_n_23, + \grant_r_reg[1]\ => arb_mux0_n_43, + \grant_r_reg[1]_0\(0) => arb_mux0_n_37, + granted_col_r_reg => arb_mux0_n_39, + granted_col_r_reg_0 => arb_mux0_n_40, + head_r(0) => head_r(2), + head_r_lcl_reg => \bank_cntrl[1].bank0_n_29\, + head_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_20\, + head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_40\, + idle_r_lcl_reg => \^idle_r_lcl_reg_1\, + \maint_controller.maint_hit_busies_r_reg[2]\(0) => \maint_controller.maint_hit_busies_r\(2), + \maint_controller.maint_hit_busies_r_reg[2]_0\ => \maint_controller.maint_hit_busies_r_reg[3]\, + \maint_controller.maint_rdy\ => \maint_controller.maint_rdy\, + \maint_controller.maint_rdy_r1_reg\ => bank_common0_n_15, + \maint_controller.maint_rdy_r1_reg_0\(2) => \bank_cntrl[3].bank0_n_19\, + \maint_controller.maint_rdy_r1_reg_0\(1) => \bank_cntrl[1].bank0_n_21\, + \maint_controller.maint_rdy_r1_reg_0\(0) => \bank_cntrl[0].bank0_n_21\, + maint_req_r => maint_req_r, + ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_0\, + \order_q_r_reg[0]\ => bank_common0_n_9, + \order_q_r_reg[0]_0\ => \bank_cntrl[3].bank0_n_25\, + \order_q_r_reg[1]\ => \bank_cntrl[3].bank0_n_27\, + ordered_r_lcl_reg => \bank_cntrl[2].bank0_n_16\, + override_demand_ns => \bank_state0/override_demand_ns\, + override_demand_r => \bank_state0/override_demand_r\, + override_demand_r_reg => \bank_cntrl[2].bank0_n_22\, + pass_open_bank_r_lcl_reg => \^periodic_rd_cntr_r_reg\, + pass_open_bank_r_lcl_reg_0 => \^maint_wip_r\, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg, + periodic_rd_insert => periodic_rd_insert, + \pre_4_1_1T_arb.granted_pre_r_reg\ => \bank_cntrl[1].bank0_n_34\, + pre_bm_end_r_reg => \bank_cntrl[2].bank0_n_18\, + pre_bm_end_r_reg_0 => \bank_cntrl[2].bank0_n_19\, + pre_bm_end_r_reg_1(1 downto 0) => sending_pre(2 downto 1), + pre_passing_open_bank_r_reg => \bank_cntrl[2].bank0_n_30\, + pre_wait_r_reg => \maint_controller.maint_wip_r_lcl_reg\, + \q_entry_r_reg[0]\ => \bank_cntrl[0].bank0_n_39\, + \q_entry_r_reg[0]_0\ => \bank_cntrl[1].bank0_n_20\, + \q_entry_r_reg[1]\ => \bank_cntrl[3].bank0_n_53\, + \q_entry_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_26\, + \q_entry_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_35\, + \q_entry_r_reg[1]_2\(0) => \q_entry_r_reg[0]\(0), + q_has_priority_r_reg => bank_common0_n_12, + q_has_rd_1 => q_has_rd_1, + q_has_rd_r_reg => q_has_rd_r_reg_0, + \ras_timer_r_reg[0]\ => \bank_cntrl[1].bank0_n_27\, + \ras_timer_r_reg[0]_0\ => \bank_cntrl[0].bank0_n_28\, + \ras_timer_r_reg[0]_1\ => \bank_cntrl[3].bank0_n_24\, + \ras_timer_r_reg[0]_2\ => \bank_cntrl[1].bank0_n_32\, + \ras_timer_r_reg[0]_3\ => \bank_cntrl[0].bank0_n_31\, + \ras_timer_r_reg[0]_4\ => \bank_cntrl[3].bank0_n_32\, + \ras_timer_r_reg[1]\ => \bank_cntrl[1].bank0_n_26\, + \ras_timer_r_reg[1]_0\ => \bank_cntrl[3].bank0_n_23\, + \ras_timer_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_27\, + ras_timer_zero_r_reg => \bank_cntrl[2].bank0_n_31\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(1) => bm_end(3), + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]\(0) => bm_end(0), + \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0\ => rb_hit_busy_r_reg_2, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => rb_hit_busy_r_reg, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[1].bank0_n_18\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => rb_hit_busy_r_reg_0, + rb_hit_busy_r_reg(0) => rb_hit_busy_r(2), + rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_1, + rd_this_rank_r(0) => rd_this_rank_r(2), + rd_wr_r_lcl_reg(0) => rd_wr_r(2), + rd_wr_r_lcl_reg_0 => \bank_cntrl[2].bank0_n_26\, + rd_wr_r_lcl_reg_1 => rd_wr_r_lcl_reg, + \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]_2\(2 downto 0), + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0), + req_bank_rdy_r_reg => \bank_cntrl[3].bank0_n_26\, + \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_9\(9 downto 0), + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(14 downto 10), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(2), + req_priority_r_reg => bank_common0_n_8, + \req_row_r_lcl_reg[14]\(14 downto 0) => req_row_r(44 downto 30), + req_wr_r(0) => req_wr_r(2), + req_wr_r_lcl0 => req_wr_r_lcl0, + \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[1].bank0_n_51\, + \rnk_config_strobe_r_reg[0]_0\ => arb_mux0_n_46, + row(14 downto 0) => row(14 downto 0), + row_cmd_wr(0) => row_cmd_wr(2), + \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\, + \starve_limit_cntr_r_reg[0]\ => \^sent_col\, + wait_for_maint_r_lcl_reg => wait_for_maint_r_4, + wait_for_maint_r_lcl_reg_0 => bank_common0_n_5, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_1, + was_priority => was_priority, + was_wr => was_wr, + wr_this_rank_r(0) => wr_this_rank_r(2) + ); +\bank_cntrl[3].bank0\: entity work.\ddr3_mig_7series_v4_2_bank_cntrl__parameterized2\ + port map ( + CLK => CLK, + D(0) => \bank_cntrl[3].bank0_n_19\, + E(0) => \^idle_r\(3), + Q(2 downto 1) => \^q\(3 downto 2), + Q(0) => \^q\(0), + SR(0) => SR(0), + act_this_rank_r(0) => act_this_rank_r(3), + act_wait_r_lcl_reg(0) => row_cmd_wr(3), + act_wait_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_31\, + act_wait_r_lcl_reg_1 => \bank_cntrl[3].bank0_n_34\, + auto_pre_r => auto_pre_r_15, + auto_pre_r_lcl_reg => \bank_cntrl[3].bank0_n_35\, + auto_pre_r_lcl_reg_0 => auto_pre_r_lcl_reg, + bm_end(0) => bm_end(0), + bm_end_r1_reg => \bank_cntrl[3].bank0_n_23\, + bm_end_r1_reg_0 => \bank_cntrl[3].bank0_n_24\, + col_wait_r => \bank_state0/col_wait_r_20\, + col_wait_r_reg => \bank_cntrl[3].bank0_n_28\, + col_wait_r_reg_0 => \bank_cntrl[3].bank0_n_30\, + col_wait_r_reg_1 => col_wait_r_reg, + \compute_tail.tail_r_lcl_reg\ => \bank_cntrl[0].bank0_n_23\, + \compute_tail.tail_r_lcl_reg_0\ => \^periodic_rd_ack_r_lcl_reg_3\, + \compute_tail.tail_r_lcl_reg_1\ => bank_common0_n_21, + demand_act_priority_r => \bank_state0/demand_act_priority_r_19\, + demand_priority_r => \bank_state0/demand_priority_r_18\, + demand_priority_r_0 => \bank_state0/demand_priority_r\, + demand_priority_r_reg => \bank_cntrl[3].bank0_n_51\, + demanded_prior_r => \bank_state0/demanded_prior_r_17\, + demanded_prior_r_1 => \bank_state0/demanded_prior_r\, + demanded_prior_r_reg => \bank_cntrl[3].bank0_n_52\, + demanded_prior_r_reg_0 => \bank_cntrl[1].bank0_n_52\, + \grant_r_reg[1]\ => arb_mux0_n_39, + \grant_r_reg[1]_0\ => arb_mux0_n_40, + \grant_r_reg[1]_1\ => arb_mux0_n_36, + head_r(0) => head_r(3), + head_r_lcl_reg => \bank_cntrl[0].bank0_n_20\, + head_r_lcl_reg_0 => \bank_cntrl[0].bank0_n_39\, + head_r_lcl_reg_1 => \bank_cntrl[0].bank0_n_40\, + idle_r_lcl_reg => \^idle_r_lcl_reg_0\, + idle_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_53\, + \maint_controller.maint_hit_busies_r_reg[3]\(0) => \maint_controller.maint_hit_busies_r\(3), + \maint_controller.maint_hit_busies_r_reg[3]_0\ => \maint_controller.maint_hit_busies_r_reg[3]\, + maint_req_r => maint_req_r, + ofs_rdy_r => \bank_state0/ofs_rdy_r_16\, + ofs_rdy_r0 => \bank_state0/ofs_rdy_r0_1\, + \order_q_r_reg[1]\ => \bank_cntrl[3].bank0_n_29\, + \order_q_r_reg[1]_0\ => \bank_cntrl[2].bank0_n_16\, + ordered_r => ordered_r, + ordered_r_lcl => ordered_r_lcl, + ordered_r_lcl_reg => \bank_cntrl[3].bank0_n_25\, + ordered_r_lcl_reg_0 => \bank_cntrl[3].bank0_n_27\, + override_demand_r => \bank_state0/override_demand_r\, + override_demand_r_reg => \bank_cntrl[3].bank0_n_22\, + pass_open_bank_r_lcl_reg => \^periodic_rd_cntr_r_reg\, + pass_open_bank_r_lcl_reg_0 => \^maint_wip_r\, + pass_open_bank_r_lcl_reg_1 => pass_open_bank_r_lcl_reg, + periodic_rd_insert => periodic_rd_insert, + \pre_4_1_1T_arb.granted_pre_ns\ => \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns\, + \pre_4_1_1T_arb.granted_pre_r_reg\(0) => sending_pre(3), + \pre_4_1_1T_arb.granted_pre_r_reg_0\ => \bank_cntrl[0].bank0_n_43\, + \pre_4_1_1T_arb.granted_pre_r_reg_1\ => \bank_cntrl[2].bank0_n_31\, + pre_bm_end_r_reg(0) => bm_end(3), + pre_bm_end_r_reg_0 => \bank_cntrl[3].bank0_n_21\, + pre_passing_open_bank_r_reg => \bank_cntrl[3].bank0_n_32\, + pre_wait_r_reg => \maint_controller.maint_wip_r_lcl_reg\, + \q_entry_r[1]_i_2__0\(0) => \^idle_r\(2), + \q_entry_r[1]_i_2__0_0\(0) => \^idle_r\(1), + \q_entry_r[1]_i_2__0_1\(0) => \^idle_r\(0), + \q_entry_r_reg[0]\ => \bank_cntrl[0].bank0_n_37\, + \q_entry_r_reg[0]_0\(0) => \q_entry_r_reg[0]\(0), + \q_entry_r_reg[1]\ => \bank_cntrl[3].bank0_n_18\, + \q_entry_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_34\, + \q_entry_r_reg[1]_1\ => \bank_cntrl[0].bank0_n_32\, + q_has_priority_r_reg => bank_common0_n_12, + q_has_rd_2 => q_has_rd_2, + q_has_rd_r_reg => q_has_rd_r_reg_2, + \ras_timer_r_reg[0]\ => \bank_cntrl[2].bank0_n_24\, + \ras_timer_r_reg[0]_0\ => \bank_cntrl[1].bank0_n_27\, + \ras_timer_r_reg[0]_1\ => \bank_cntrl[0].bank0_n_28\, + \ras_timer_r_reg[0]_2\ => \bank_cntrl[0].bank0_n_31\, + \ras_timer_r_reg[0]_3\ => \bank_cntrl[2].bank0_n_30\, + \ras_timer_r_reg[0]_4\ => \bank_cntrl[1].bank0_n_32\, + \ras_timer_r_reg[1]\ => \bank_cntrl[2].bank0_n_23\, + \ras_timer_r_reg[1]_0\ => \bank_cntrl[0].bank0_n_27\, + \ras_timer_r_reg[1]_1\ => \bank_cntrl[1].bank0_n_26\, + ras_timer_zero_r_reg(0) => sending_row(3), + \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]\ => rb_hit_busy_r_reg, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]\ => \bank_cntrl[1].bank0_n_18\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0\ => rb_hit_busy_r_reg_0, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]\ => \bank_cntrl[2].bank0_n_18\, + \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0\ => rb_hit_busy_r_reg_1, + rb_hit_busy_r(2 downto 0) => rb_hit_busy_r(2 downto 0), + rb_hit_busy_r_reg(0) => rb_hit_busy_r(3), + rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_2, + rd_this_rank_r(0) => rd_this_rank_r(3), + rd_wr_r_lcl_reg(0) => rd_wr_r(3), + rd_wr_r_lcl_reg_0 => rd_wr_r_lcl_reg, + \req_bank_r_lcl_reg[2]\(2 downto 0) => \^req_bank_r_lcl_reg[2]\(2 downto 0), + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0), + req_bank_rdy_r_reg(0) => req_wr_r(2), + req_bank_rdy_r_reg_0(0) => rd_wr_r(2), + req_bank_rdy_r_reg_1 => \bank_cntrl[1].bank0_n_30\, + \req_col_r_reg[9]\(9 downto 0) => \bank_compare0/req_col_r_14\(9 downto 0), + \req_col_r_reg[9]_0\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_data_buf_addr_r_reg[4]\(4 downto 0) => req_data_buf_addr_r(19 downto 15), + \req_data_buf_addr_r_reg[4]_0\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + req_periodic_rd_r(0) => req_periodic_rd_r(3), + req_priority_r_reg => bank_common0_n_8, + \req_row_r_lcl_reg[14]\(14 downto 0) => req_row_r(59 downto 45), + req_wr_r_lcl0 => req_wr_r_lcl0, + req_wr_r_lcl_reg => \bank_cntrl[3].bank0_n_26\, + \rnk_config_strobe_r_reg[0]\ => \bank_cntrl[0].bank0_n_44\, + \rnk_config_strobe_r_reg[0]_0\ => arb_mux0_n_46, + row(14 downto 0) => row(14 downto 0), + \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\, + \starve_limit_cntr_r_reg[0]\ => \^sent_col\, + wait_for_maint_r_lcl_reg => wait_for_maint_r_5, + wait_for_maint_r_lcl_reg_0 => bank_common0_n_5, + wait_for_maint_r_lcl_reg_1 => wait_for_maint_r_lcl_reg_2, + was_priority => was_priority, + was_wr => was_wr, + wr_this_rank_r(0) => wr_this_rank_r(3) + ); +bank_common0: entity work.ddr3_mig_7series_v4_2_bank_common + port map ( + CLK => CLK, + D(3) => \bank_cntrl[3].bank0_n_19\, + D(2) => \bank_cntrl[2].bank0_n_20\, + D(1) => \bank_cntrl[1].bank0_n_21\, + D(0) => \bank_cntrl[0].bank0_n_21\, + E(0) => \^idle_r\(3), + Q(3 downto 0) => \maint_controller.maint_hit_busies_r\(3 downto 0), + SR(0) => SR(0), + accept_ns => accept_ns, + app_en_r2 => app_en_r2, + app_rdy_r_reg => bank_common0_n_13, + app_rdy_r_reg_0 => bank_common0_n_14, + app_rdy_r_reg_1 => bank_common0_n_21, + app_rdy_r_reg_2 => bank_common0_n_22, + clear_periodic_rd_request => clear_periodic_rd_request, + \generate_maint_cmds.insert_maint_r_lcl_reg_0\ => \^generate_maint_cmds.insert_maint_r_lcl_reg\, + head_r(3 downto 0) => head_r(3 downto 0), + idle_r_lcl_reg => bank_common0_n_11, + \maint_controller.maint_rdy\ => \maint_controller.maint_rdy\, + \maint_controller.maint_wip_r_lcl_reg_0\ => \^maint_wip_r\, + \maint_controller.maint_wip_r_lcl_reg_1\ => bank_common0_n_15, + \maint_controller.maint_wip_r_lcl_reg_2\ => \maint_controller.maint_wip_r_lcl_reg\, + maint_req_r => maint_req_r, + maint_srx_r => maint_srx_r, + maint_zq_r => maint_zq_r, + p_9_in => p_9_in, + periodic_rd_ack_r_lcl_reg_0 => periodic_rd_ack_r_lcl_reg, + periodic_rd_ack_r_lcl_reg_1 => \^periodic_rd_ack_r_lcl_reg_2\, + periodic_rd_ack_r_lcl_reg_2 => bank_common0_n_12, + periodic_rd_ack_r_lcl_reg_3 => \^periodic_rd_ack_r_lcl_reg_0\, + periodic_rd_ack_r_lcl_reg_4 => \^periodic_rd_ack_r_lcl_reg_3\, + periodic_rd_ack_r_lcl_reg_5 => \^periodic_rd_ack_r_lcl_reg_1\, + periodic_rd_cntr_r_reg_0 => \^periodic_rd_cntr_r_reg\, + periodic_rd_cntr_r_reg_1 => periodic_rd_cntr_r_reg_0, + periodic_rd_insert => periodic_rd_insert, + \periodic_read_request.periodic_rd_grant_r\ => \periodic_read_request.periodic_rd_grant_r\, + \q_entry_r_reg[0]\(0) => \^idle_r\(2), + \q_entry_r_reg[0]_0\(0) => \^idle_r\(1), + \q_entry_r_reg[0]_1\(0) => \^idle_r\(0), + rb_hit_busy_r(3 downto 0) => rb_hit_busy_r(3 downto 0), + req_wr_r(0) => req_wr_r(2), + req_wr_r_lcl_reg => bank_common0_n_9, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\(0) => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\(0), + \rstdiv0_sync_r1_reg_rep__13\ => bank_common0_n_5, + was_priority => was_priority, + was_priority_reg_0 => bank_common0_n_8, + was_priority_reg_1 => was_priority_reg, + was_wr => was_wr, + was_wr0 => was_wr0 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_mc_phy is + port ( + A_rst_primitives_reg : out STD_LOGIC; + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_0 : out STD_LOGIC; + mem_dq_out : out STD_LOGIC_VECTOR ( 40 downto 0 ); + mem_dq_ts : out STD_LOGIC_VECTOR ( 17 downto 0 ); + out_dqs_0 : out STD_LOGIC; + ts_dqs_0 : out STD_LOGIC; + pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_1 : out STD_LOGIC; + out_dqs_1 : out STD_LOGIC; + ts_dqs_1 : out STD_LOGIC; + \rd_ptr_reg[0]_1\ : out STD_LOGIC; + \rd_ptr_reg[1]_1\ : out STD_LOGIC; + \rd_ptr_reg[2]_1\ : out STD_LOGIC; + \rd_ptr_reg[3]_1\ : out STD_LOGIC; + phy_mc_ctl_full : out STD_LOGIC; + ref_dll_lock : out STD_LOGIC; + idelay_ld_rst : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[1]\ : out STD_LOGIC; + \my_empty_reg[1]_0\ : out STD_LOGIC; + init_complete_r1_timing_reg : out STD_LOGIC; + \my_empty_reg[1]_1\ : out STD_LOGIC; + \my_empty_reg[1]_2\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + DIC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + DIA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + DIB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \my_empty_reg[4]_rep__1\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \pi_counter_read_val_reg[5]\ : out STD_LOGIC; + \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + phy_rddata_en : out STD_LOGIC; + rd_data_en : out STD_LOGIC; + \my_empty_reg[0]\ : out STD_LOGIC; + \my_empty_reg[0]_0\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 127 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + in0 : out STD_LOGIC; + phy_mc_data_full : out STD_LOGIC; + wr_en : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + phy_mc_cmd_full : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]\ : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[4]_rep__0\ : out STD_LOGIC; + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \mcGo_r_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \rd_ptr_reg[3]_2\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + p_1_in : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \po_counter_read_val_reg[8]_0\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_1\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_2\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_3\ : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + CLK : in STD_LOGIC; + \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \rd_ptr_reg[3]_10\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_11\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_12\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC; + mem_dq_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); + idelay_inc : in STD_LOGIC; + LD0 : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC; + mem_dqs_in : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC; + COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \po_counter_read_val_reg[8]_4\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_5\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_6\ : in STD_LOGIC; + D1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D4 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D5 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D6 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D7 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D8 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0 : in STD_LOGIC; + ofifo_rst_reg0 : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC; + LD0_0 : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_4\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \po_counter_read_val_reg[8]_7\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_8\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_9\ : in STD_LOGIC; + D0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0_1 : in STD_LOGIC; + ofifo_rst_reg0_2 : in STD_LOGIC; + phy_ctl_wr_i2 : in STD_LOGIC; + pll_locked : in STD_LOGIC; + phy_read_calib : in STD_LOGIC; + \mcGo_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_write_calib : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); + RST0 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + \po_counter_read_val_reg[8]_10\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_11\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_12\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_13\ : in STD_LOGIC; + \my_empty_reg[7]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_9\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_10\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_11\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + calib_cmd_wren : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \read_fifo.tail_r_reg_0_sp_1\ : in STD_LOGIC; + mux_wrdata_en : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC; + calib_wrdata_en : in STD_LOGIC; + out_fifo : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data[127]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DOC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[8]\ : in STD_LOGIC; + DOB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[73]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[75]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[79]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[81]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[87]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[91]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[93]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[97]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[99]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[103]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[105]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[109]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[111]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[115]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[121]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[123]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mux_cmd_wren : in STD_LOGIC; + mc_address : in STD_LOGIC_VECTOR ( 5 downto 0 ); + mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_dout : in STD_LOGIC_VECTOR ( 39 downto 0 ); + calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_mc_phy : entity is "mig_7series_v4_2_ddr_mc_phy"; +end ddr3_mig_7series_v4_2_ddr_mc_phy; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_mc_phy is + signal mcGo_w : STD_LOGIC_VECTOR ( 0 to 0 ); + signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 1 ); + signal \read_fifo.tail_r_reg_0_sn_1\ : STD_LOGIC; +begin + \read_fifo.tail_r_reg_0_sn_1\ <= \read_fifo.tail_r_reg_0_sp_1\; +\ddr_phy_4lanes_0.u_ddr_phy_4lanes\: entity work.ddr3_mig_7series_v4_2_ddr_phy_4lanes + port map ( + A_rst_primitives_reg_0 => A_rst_primitives_reg, + A_rst_primitives_reg_1 => A_rst_primitives_reg_0, + A_rst_primitives_reg_2 => A_rst_primitives_reg_1, + CLK => CLK, + CLKB0 => CLKB0, + CLKB0_4 => CLKB0_4, + COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0), + D(0) => mcGo_w(0), + D0(7 downto 0) => D0(7 downto 0), + D1(7 downto 0) => D1(7 downto 0), + D2(7 downto 0) => D2(7 downto 0), + D3(7 downto 0) => D3(7 downto 0), + D4(7 downto 0) => D4(7 downto 0), + D5(7 downto 0) => D5(7 downto 0), + D6(7 downto 0) => D6(7 downto 0), + D7(7 downto 0) => D7(7 downto 0), + D8(7 downto 0) => D8(7 downto 0), + D9(7 downto 0) => D9(7 downto 0), + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => DIC(1 downto 0), + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + LD0 => LD0, + LD0_0 => LD0_0, + Q(10 downto 0) => Q(10 downto 0), + RST0 => RST0, + SR(0) => SR(0), + calib_cmd_wren => calib_cmd_wren, + calib_sel(1 downto 0) => calib_sel(1 downto 0), + calib_wrdata_en => calib_wrdata_en, + ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0), + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(127 downto 0) => D(127 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(1 downto 0), + freq_refclk => freq_refclk, + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + idelay_inc => idelay_inc, + idelay_ld_rst => idelay_ld_rst, + ififo_rst_reg0 => ififo_rst_reg0, + ififo_rst_reg0_1 => ififo_rst_reg0_1, + in0 => in0, + init_complete_r1_timing_reg => init_complete_r1_timing_reg, + \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\, + \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq_0\, + mc_address(5 downto 0) => mc_address(5 downto 0), + mc_cas_n(0) => mc_cas_n(0), + mc_wrdata_en => mc_wrdata_en, + mem_dq_in(15 downto 0) => mem_dq_in(15 downto 0), + mem_dq_out(40 downto 0) => mem_dq_out(40 downto 0), + mem_dq_ts(17 downto 0) => mem_dq_ts(17 downto 0), + mem_dqs_in(1 downto 0) => mem_dqs_in(1 downto 0), + mem_out(2 downto 0) => mem_out(2 downto 0), + mem_refclk => mem_refclk, + mux_cmd_wren => mux_cmd_wren, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[0]\ => \my_empty_reg[0]\, + \my_empty_reg[0]_0\ => \my_empty_reg[0]_0\, + \my_empty_reg[1]\ => \my_empty_reg[1]\, + \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\, + \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\, + \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\, + \my_empty_reg[4]_rep__0\ => \my_empty_reg[4]_rep__0\, + \my_empty_reg[4]_rep__1\ => \my_empty_reg[4]_rep__1\, + \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0), + \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0), + \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0), + \my_empty_reg[7]_10\(3 downto 0) => \my_empty_reg[7]_10\(3 downto 0), + \my_empty_reg[7]_11\(3 downto 0) => \my_empty_reg[7]_11\(3 downto 0), + \my_empty_reg[7]_12\(3 downto 0) => \my_empty_reg[7]_12\(3 downto 0), + \my_empty_reg[7]_13\(3 downto 0) => \my_empty_reg[7]_13\(3 downto 0), + \my_empty_reg[7]_14\(3 downto 0) => \my_empty_reg[7]_14\(3 downto 0), + \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0), + \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0), + \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0), + \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0), + \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0), + \my_empty_reg[7]_7\(3 downto 0) => \my_empty_reg[7]_7\(3 downto 0), + \my_empty_reg[7]_8\(3 downto 0) => \my_empty_reg[7]_8\(3 downto 0), + \my_empty_reg[7]_9\(3 downto 0) => \my_empty_reg[7]_9\(3 downto 0), + \not_strict_mode.app_rd_data[127]_i_2\(0) => \not_strict_mode.app_rd_data[127]_i_2\(0), + \not_strict_mode.app_rd_data_reg[101]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[103]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[105]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[109]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[111]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[115]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[121]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[123]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[13]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[15]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[19]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[21]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[25]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[27]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[31]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[33]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[37]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[39]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[43]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[45]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[49]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[51]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[55]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[57]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[61]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[63]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[67]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[69]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[73]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[75]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[79]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[7]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[81]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[85]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[87]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\, + \not_strict_mode.app_rd_data_reg[91]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[93]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[97]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[99]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[9]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]\(1 downto 0), + ofifo_rst_reg0 => ofifo_rst_reg0, + ofifo_rst_reg0_2 => ofifo_rst_reg0_2, + \out\(1 downto 0) => \out\(1 downto 0), + out_dqs_0 => out_dqs_0, + out_dqs_1 => out_dqs_1, + out_fifo => out_fifo, + p_1_in => p_1_in, + phy_ctl_wr_i2 => phy_ctl_wr_i2, + phy_dout(39 downto 0) => phy_dout(39 downto 0), + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_ctl_full_r_reg(0) => \mcGo_r_reg[0]_0\(0), + phy_mc_data_full => phy_mc_data_full, + phy_rddata_en => phy_rddata_en, + phy_read_calib => phy_read_calib, + phy_write_calib => phy_write_calib, + \pi_counter_read_val_reg[5]_0\ => \pi_counter_read_val_reg[5]\, + \pi_counter_read_val_reg[5]_1\(5 downto 0) => \pi_counter_read_val_reg[5]_0\(5 downto 0), + pi_dqs_found_lanes(1 downto 0) => pi_dqs_found_lanes(1 downto 0), + \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\, + \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\, + \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\, + \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\, + \pi_dqs_found_lanes_r1_reg[2]_3\ => \pi_dqs_found_lanes_r1_reg[2]_3\, + \pi_dqs_found_lanes_r1_reg[3]\ => \pi_dqs_found_lanes_r1_reg[3]\, + \pi_dqs_found_lanes_r1_reg[3]_0\ => \pi_dqs_found_lanes_r1_reg[3]_0\, + \pi_dqs_found_lanes_r1_reg[3]_1\ => \pi_dqs_found_lanes_r1_reg[3]_1\, + \pi_dqs_found_lanes_r1_reg[3]_2\ => \pi_dqs_found_lanes_r1_reg[3]_2\, + \pi_dqs_found_lanes_r1_reg[3]_3\ => \pi_dqs_found_lanes_r1_reg[3]_3\, + \pi_dqs_found_lanes_r1_reg[3]_4\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_4\(5 downto 0), + pll_locked => pll_locked, + \po_counter_read_val_reg[8]_0\(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0), + \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_0\, + \po_counter_read_val_reg[8]_10\ => \po_counter_read_val_reg[8]_9\, + \po_counter_read_val_reg[8]_11\ => \po_counter_read_val_reg[8]_10\, + \po_counter_read_val_reg[8]_12\ => \po_counter_read_val_reg[8]_11\, + \po_counter_read_val_reg[8]_13\ => \po_counter_read_val_reg[8]_12\, + \po_counter_read_val_reg[8]_14\ => \po_counter_read_val_reg[8]_13\, + \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_1\, + \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_2\, + \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_3\, + \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_4\, + \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_5\, + \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_6\, + \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_7\, + \po_counter_read_val_reg[8]_9\ => \po_counter_read_val_reg[8]_8\, + rd_data_en => rd_data_en, + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\, + \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\, + \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\, + \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\, + \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\, + \rd_ptr_reg[3]_10\(3 downto 0) => \rd_ptr_reg[3]_10\(3 downto 0), + \rd_ptr_reg[3]_11\(3 downto 0) => \rd_ptr_reg[3]_11\(3 downto 0), + \rd_ptr_reg[3]_12\(2 downto 0) => \rd_ptr_reg[3]_12\(2 downto 0), + \rd_ptr_reg[3]_2\(31 downto 0) => \rd_ptr_reg[3]_2\(31 downto 0), + \rd_ptr_reg[3]_3\(3 downto 0) => \rd_ptr_reg[3]_3\(3 downto 0), + \rd_ptr_reg[3]_4\(3 downto 0) => \rd_ptr_reg[3]_4\(3 downto 0), + \rd_ptr_reg[3]_5\(2 downto 0) => \rd_ptr_reg[3]_5\(2 downto 0), + \rd_ptr_reg[3]_6\(3 downto 0) => \rd_ptr_reg[3]_6\(3 downto 0), + \rd_ptr_reg[3]_7\(3 downto 0) => \rd_ptr_reg[3]_7\(3 downto 0), + \rd_ptr_reg[3]_8\(7 downto 0) => \rd_ptr_reg[3]_8\(7 downto 0), + \rd_ptr_reg[3]_9\(6 downto 0) => \rd_ptr_reg[3]_9\(6 downto 0), + \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + \read_fifo.tail_r_reg\(0) => \read_fifo.tail_r_reg\(0), + \read_fifo.tail_r_reg_0_sp_1\ => \read_fifo.tail_r_reg_0_sn_1\, + ref_dll_lock => ref_dll_lock, + sync_pulse => sync_pulse, + ts_dqs_0 => ts_dqs_0, + ts_dqs_1 => ts_dqs_1, + wr_en => wr_en, + wr_en_2 => wr_en_2, + wr_en_3 => wr_en_3, + \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\, + \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\, + \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\, + \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0), + \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0), + \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\, + \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]_0\, + \wr_ptr_timing_reg[0]_1\ => \wr_ptr_timing_reg[0]_1\ + ); +\mcGo_r_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mcGo_w(0), + Q => p_0_in(1), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(10), + Q => p_0_in(11), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(11), + Q => p_0_in(12), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(12), + Q => p_0_in(13), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(13), + Q => p_0_in(14), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(14), + Q => p_0_in(15), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(15), + Q => \mcGo_r_reg[15]_0\(0), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(1), + Q => p_0_in(2), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(2), + Q => p_0_in(3), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(3), + Q => p_0_in(4), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(4), + Q => p_0_in(5), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(5), + Q => p_0_in(6), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(6), + Q => p_0_in(7), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(7), + Q => p_0_in(8), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(8), + Q => p_0_in(9), + R => \mcGo_r_reg[0]_0\(0) + ); +\mcGo_r_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => p_0_in(9), + Q => p_0_in(10), + R => \mcGo_r_reg[0]_0\(0) + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_mc_phy_wrapper is + port ( + A_rst_primitives : out STD_LOGIC; + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg : out STD_LOGIC; + pi_dqs_found_lanes : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_0 : out STD_LOGIC; + \rd_ptr_reg[0]_1\ : out STD_LOGIC; + \rd_ptr_reg[1]_1\ : out STD_LOGIC; + \rd_ptr_reg[2]_1\ : out STD_LOGIC; + \rd_ptr_reg[3]_1\ : out STD_LOGIC; + phy_mc_ctl_full : out STD_LOGIC; + ref_dll_lock : out STD_LOGIC; + idelay_ld_rst : out STD_LOGIC; + ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_reset_n : out STD_LOGIC; + ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_cas_n : out STD_LOGIC; + ddr3_ras_n : out STD_LOGIC; + ddr3_we_n : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \my_empty_reg[1]\ : out STD_LOGIC; + \my_empty_reg[1]_0\ : out STD_LOGIC; + init_complete_r1_timing_reg : out STD_LOGIC; + \my_empty_reg[1]_1\ : out STD_LOGIC; + \my_empty_reg[1]_2\ : out STD_LOGIC; + \my_empty_reg[5]\ : out STD_LOGIC; + \my_empty_reg[3]\ : out STD_LOGIC; + \my_empty_reg[5]_0\ : out STD_LOGIC; + \my_empty_reg[3]_0\ : out STD_LOGIC; + \my_empty_reg[5]_1\ : out STD_LOGIC; + \my_empty_reg[3]_1\ : out STD_LOGIC; + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 73 downto 0 ); + DIC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + DIA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + DIB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \my_empty_reg[4]_rep__1\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \pi_counter_read_val_reg[5]\ : out STD_LOGIC; + \pi_counter_read_val_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + phy_rddata_en : out STD_LOGIC; + rd_data_en : out STD_LOGIC; + \my_empty_reg[0]\ : out STD_LOGIC; + \my_empty_reg[0]_0\ : out STD_LOGIC; + D : out STD_LOGIC_VECTOR ( 127 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + in0 : out STD_LOGIC; + phy_mc_data_full : out STD_LOGIC; + wr_en : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + phy_mc_cmd_full : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + \rd_ptr_reg[3]_2\ : out STD_LOGIC_VECTOR ( 31 downto 0 ); + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]\ : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[4]_rep__0\ : out STD_LOGIC; + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \po_counter_read_val_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + \mcGo_r_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + p_1_in : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : out STD_LOGIC; + ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); + ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + \po_counter_read_val_reg[8]_0\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_1\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_2\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_3\ : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + CLK : in STD_LOGIC; + \rd_ptr_reg[3]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \rd_ptr_reg[3]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \rd_ptr_reg[3]_9\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); + \rd_ptr_reg[3]_10\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_11\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \rd_ptr_reg[3]_12\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \input_[9].iserdes_dq_.iserdesdq\ : in STD_LOGIC; + idelay_inc : in STD_LOGIC; + LD0 : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_2\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[2]_3\ : in STD_LOGIC; + COUNTERLOADVAL : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \po_counter_read_val_reg[8]_4\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_5\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_6\ : in STD_LOGIC; + D1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D4 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D5 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D6 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D7 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D8 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + D9 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0 : in STD_LOGIC; + ofifo_rst_reg0 : in STD_LOGIC; + \input_[9].iserdes_dq_.iserdesdq_0\ : in STD_LOGIC; + LD0_0 : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_0\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_1\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_2\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_3\ : in STD_LOGIC; + \pi_dqs_found_lanes_r1_reg[3]_4\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + \po_counter_read_val_reg[8]_7\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_8\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_9\ : in STD_LOGIC; + D0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + \my_empty_reg[7]_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ififo_rst_reg0_1 : in STD_LOGIC; + ofifo_rst_reg0_2 : in STD_LOGIC; + pll_locked : in STD_LOGIC; + phy_read_calib : in STD_LOGIC; + \mcGo_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + phy_write_calib : in STD_LOGIC; + RST0 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + mux_reset_n : in STD_LOGIC; + idle : in STD_LOGIC; + UNCONN_IN : in STD_LOGIC; + UNCONN_IN_0 : in STD_LOGIC; + UNCONN_IN_1 : in STD_LOGIC; + phy_ctl_wr_i1_reg_0 : in STD_LOGIC; + \po_counter_read_val_reg[8]_10\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_11\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_12\ : in STD_LOGIC; + \po_counter_read_val_reg[8]_13\ : in STD_LOGIC; + \my_empty_reg[7]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_9\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_10\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_11\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \my_empty_reg[7]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_timing_reg[0]\ : in STD_LOGIC; + calib_cmd_wren : in STD_LOGIC; + \wr_ptr_timing_reg[0]_0\ : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \read_fifo.tail_r_reg_0_sp_1\ : in STD_LOGIC; + mux_wrdata_en : in STD_LOGIC; + mc_wrdata_en : in STD_LOGIC; + \wr_ptr_timing_reg[0]_1\ : in STD_LOGIC; + calib_wrdata_en : in STD_LOGIC; + out_fifo : in STD_LOGIC; + mux_cmd_wren : in STD_LOGIC; + \my_full_reg[0]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data[127]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DOC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[8]\ : in STD_LOGIC; + DOB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[73]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[75]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[79]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[81]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[87]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[91]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[93]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[97]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[99]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[103]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[105]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[109]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[111]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[115]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[121]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[123]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mc_address : in STD_LOGIC_VECTOR ( 5 downto 0 ); + mc_cas_n : in STD_LOGIC_VECTOR ( 0 to 0 ); + E : in STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \my_empty_reg[4]_inv\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wr_ptr_timing_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wr_ptr_timing_reg[0]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \phy_ctl_wd_i1_reg[24]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); + phy_dout : in STD_LOGIC_VECTOR ( 39 downto 0 ); + calib_sel : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_mc_phy_wrapper : entity is "mig_7series_v4_2_ddr_mc_phy_wrapper"; +end ddr3_mig_7series_v4_2_ddr_mc_phy_wrapper; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_mc_phy_wrapper is + signal mem_dq_in : STD_LOGIC_VECTOR ( 39 downto 21 ); + signal mem_dq_out : STD_LOGIC_VECTOR ( 45 downto 0 ); + signal mem_dq_ts : STD_LOGIC_VECTOR ( 45 downto 25 ); + signal mem_dqs_in : STD_LOGIC_VECTOR ( 3 downto 2 ); + signal out_dqs_0 : STD_LOGIC; + signal out_dqs_1 : STD_LOGIC; + signal phy_ctl_wd_i1 : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal phy_ctl_wd_i2 : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal phy_ctl_wr_i1 : STD_LOGIC; + signal phy_ctl_wr_i2 : STD_LOGIC; + signal \read_fifo.tail_r_reg_0_sn_1\ : STD_LOGIC; + signal ts_dqs_0 : STD_LOGIC; + signal ts_dqs_1 : STD_LOGIC; + attribute BOX_TYPE : string; + attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE : string; + attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[0].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[0].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[10].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[10].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[11].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[11].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[12].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[12].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[13].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[13].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[14].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[14].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[1].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[1].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[2].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[2].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[3].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[3].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[4].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[4].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[5].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[5].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[6].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[6].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[7].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[7].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[8].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[8].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_addr_obuf[9].u_addr_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_addr_obuf[9].u_addr_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_bank_obuf[0].u_bank_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_bank_obuf[0].u_bank_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_bank_obuf[1].u_bank_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_bank_obuf[1].u_bank_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_bank_obuf[2].u_bank_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_bank_obuf[2].u_bank_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_dm_obuf.loop_dm[0].u_dm_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_dm_obuf.loop_dm[1].u_dm_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \gen_reset_obuf.u_reset_obuf\ : label is "PRIMITIVE"; + attribute CAPACITANCE of \gen_reset_obuf.u_reset_obuf\ : label is "DONT_CARE"; + attribute BOX_TYPE of u_cas_n_obuf : label is "PRIMITIVE"; + attribute CAPACITANCE of u_cas_n_obuf : label is "DONT_CARE"; + attribute BOX_TYPE of u_ras_n_obuf : label is "PRIMITIVE"; + attribute CAPACITANCE of u_ras_n_obuf : label is "DONT_CARE"; + attribute BOX_TYPE of u_we_n_obuf : label is "PRIMITIVE"; + attribute CAPACITANCE of u_we_n_obuf : label is "DONT_CARE"; +begin + \read_fifo.tail_r_reg_0_sn_1\ <= \read_fifo.tail_r_reg_0_sp_1\; +\cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(22), + O => ddr3_cke(0) + ); +\cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(20), + O => ddr3_odt(0) + ); +\gen_addr_obuf[0].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(17), + O => ddr3_addr(0) + ); +\gen_addr_obuf[10].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(13), + O => ddr3_addr(10) + ); +\gen_addr_obuf[11].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(0), + O => ddr3_addr(11) + ); +\gen_addr_obuf[12].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(2), + O => ddr3_addr(12) + ); +\gen_addr_obuf[13].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(9), + O => ddr3_addr(13) + ); +\gen_addr_obuf[14].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(11), + O => ddr3_addr(14) + ); +\gen_addr_obuf[1].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(1), + O => ddr3_addr(1) + ); +\gen_addr_obuf[2].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(8), + O => ddr3_addr(2) + ); +\gen_addr_obuf[3].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(12), + O => ddr3_addr(3) + ); +\gen_addr_obuf[4].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(6), + O => ddr3_addr(4) + ); +\gen_addr_obuf[5].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(16), + O => ddr3_addr(5) + ); +\gen_addr_obuf[6].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(3), + O => ddr3_addr(6) + ); +\gen_addr_obuf[7].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(4), + O => ddr3_addr(7) + ); +\gen_addr_obuf[8].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(7), + O => ddr3_addr(8) + ); +\gen_addr_obuf[9].u_addr_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(5), + O => ddr3_addr(9) + ); +\gen_bank_obuf[0].u_bank_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(19), + O => ddr3_ba(0) + ); +\gen_bank_obuf[1].u_bank_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(23), + O => ddr3_ba(1) + ); +\gen_bank_obuf[2].u_bank_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(15), + O => ddr3_ba(2) + ); +\gen_dm_obuf.loop_dm[0].u_dm_obuf\: unisim.vcomponents.OBUFT + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(28), + O => ddr3_dm(0), + T => mem_dq_ts(28) + ); +\gen_dm_obuf.loop_dm[1].u_dm_obuf\: unisim.vcomponents.OBUFT + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(37), + O => ddr3_dm(1), + T => mem_dq_ts(37) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(26), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(0), + O => mem_dq_in(22), + T => mem_dq_ts(26) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(38), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(10), + O => mem_dq_in(32), + T => mem_dq_ts(38) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(40), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(11), + O => mem_dq_in(34), + T => mem_dq_ts(40) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(42), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(12), + O => mem_dq_in(36), + T => mem_dq_ts(42) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(44), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(13), + O => mem_dq_in(38), + T => mem_dq_ts(44) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(41), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(14), + O => mem_dq_in(35), + T => mem_dq_ts(41) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(45), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(15), + O => mem_dq_in(39), + T => mem_dq_ts(45) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(25), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(1), + O => mem_dq_in(21), + T => mem_dq_ts(25) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(30), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(2), + O => mem_dq_in(26), + T => mem_dq_ts(30) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(32), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(3), + O => mem_dq_in(28), + T => mem_dq_ts(32) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(27), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(4), + O => mem_dq_in(23), + T => mem_dq_ts(27) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(33), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(5), + O => mem_dq_in(29), + T => mem_dq_ts(33) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(31), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(6), + O => mem_dq_in(27), + T => mem_dq_ts(31) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(29), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(7), + O => mem_dq_in(25), + T => mem_dq_ts(29) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(36), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(8), + O => mem_dq_in(30), + T => mem_dq_ts(36) + ); +\gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq\: unisim.vcomponents.IOBUF_INTERMDISABLE + generic map( + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => mem_dq_out(43), + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dq(9), + O => mem_dq_in(37), + T => mem_dq_ts(43) + ); +\gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE + generic map( + DQS_BIAS => "TRUE", + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => out_dqs_0, + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dqs_p(0), + IOB => ddr3_dqs_n(0), + O => mem_dqs_in(2), + T => ts_dqs_0 + ); +\gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs\: unisim.vcomponents.IOBUFDS_INTERMDISABLE + generic map( + DQS_BIAS => "TRUE", + IOSTANDARD => "DEFAULT", + SIM_DEVICE => "7SERIES", + USE_IBUFDISABLE => "TRUE" + ) + port map ( + I => out_dqs_1, + IBUFDISABLE => idle, + INTERMDISABLE => idle, + IO => ddr3_dqs_p(1), + IOB => ddr3_dqs_n(1), + O => mem_dqs_in(3), + T => ts_dqs_1 + ); +\gen_reset_obuf.u_reset_obuf\: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mux_reset_n, + O => ddr3_reset_n + ); +\genblk24.phy_ctl_pre_fifo_0\: entity work.ddr3_mig_7series_v4_2_ddr_of_pre_fifo + port map ( + CLK => CLK, + E(0) => E(0), + SR(0) => SR(0), + UNCONN_IN => UNCONN_IN, + mux_cmd_wren => mux_cmd_wren, + \my_empty_reg[3]_0\ => \my_empty_reg[3]\, + \my_empty_reg[4]_inv_0\(0) => \my_empty_reg[4]_inv\(0), + \my_empty_reg[5]_0\ => \my_empty_reg[5]\, + \my_empty_reg[8]_0\(0) => \my_empty_reg[8]\(0), + \my_full_reg[0]_0\ => \my_full_reg[0]\ + ); +\genblk24.phy_ctl_pre_fifo_1\: entity work.\ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0\ + port map ( + CLK => CLK, + SR(0) => SR(0), + UNCONN_IN => UNCONN_IN_0, + mux_cmd_wren => mux_cmd_wren, + \my_empty_reg[3]_0\ => \my_empty_reg[3]_0\, + \my_empty_reg[4]_inv_0\(0) => \my_empty_reg[4]_inv\(0), + \my_empty_reg[5]_0\ => \my_empty_reg[5]_0\, + \my_full_reg[0]_0\ => \my_full_reg[0]\, + \rd_ptr_reg[2]_0\(0) => \my_empty_reg[8]\(0), + \wr_ptr_timing_reg[0]_0\(0) => \wr_ptr_timing_reg[0]_2\(0) + ); +\genblk24.phy_ctl_pre_fifo_2\: entity work.\ddr3_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6\ + port map ( + CLK => CLK, + SR(0) => SR(0), + UNCONN_IN => UNCONN_IN_1, + mux_cmd_wren => mux_cmd_wren, + \my_empty_reg[3]_0\ => \my_empty_reg[3]_1\, + \my_empty_reg[4]_inv_0\(0) => \my_empty_reg[4]_inv\(0), + \my_empty_reg[5]_0\ => \my_empty_reg[5]_1\, + \my_empty_reg[8]_0\(0) => \my_empty_reg[8]\(0), + \my_full_reg[0]_0\ => \my_full_reg[0]\, + \wr_ptr_timing_reg[0]_0\(0) => \wr_ptr_timing_reg[0]_3\(0) + ); +\phy_ctl_wd_i1_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(0), + Q => phy_ctl_wd_i1(0), + R => '0' + ); +\phy_ctl_wd_i1_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(3), + Q => phy_ctl_wd_i1(17), + R => '0' + ); +\phy_ctl_wd_i1_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(4), + Q => phy_ctl_wd_i1(18), + R => '0' + ); +\phy_ctl_wd_i1_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(5), + Q => phy_ctl_wd_i1(19), + R => '0' + ); +\phy_ctl_wd_i1_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(1), + Q => phy_ctl_wd_i1(1), + R => '0' + ); +\phy_ctl_wd_i1_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(6), + Q => phy_ctl_wd_i1(20), + R => '0' + ); +\phy_ctl_wd_i1_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(7), + Q => phy_ctl_wd_i1(21), + R => '0' + ); +\phy_ctl_wd_i1_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(8), + Q => phy_ctl_wd_i1(22), + R => '0' + ); +\phy_ctl_wd_i1_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(9), + Q => phy_ctl_wd_i1(23), + R => '0' + ); +\phy_ctl_wd_i1_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(10), + Q => phy_ctl_wd_i1(24), + R => '0' + ); +\phy_ctl_wd_i1_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \phy_ctl_wd_i1_reg[24]_0\(2), + Q => phy_ctl_wd_i1(2), + R => '0' + ); +\phy_ctl_wd_i2_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(0), + Q => phy_ctl_wd_i2(0), + R => '0' + ); +\phy_ctl_wd_i2_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(17), + Q => phy_ctl_wd_i2(17), + R => '0' + ); +\phy_ctl_wd_i2_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(18), + Q => phy_ctl_wd_i2(18), + R => '0' + ); +\phy_ctl_wd_i2_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(19), + Q => phy_ctl_wd_i2(19), + R => '0' + ); +\phy_ctl_wd_i2_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(1), + Q => phy_ctl_wd_i2(1), + R => '0' + ); +\phy_ctl_wd_i2_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(20), + Q => phy_ctl_wd_i2(20), + R => '0' + ); +\phy_ctl_wd_i2_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(21), + Q => phy_ctl_wd_i2(21), + R => '0' + ); +\phy_ctl_wd_i2_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(22), + Q => phy_ctl_wd_i2(22), + R => '0' + ); +\phy_ctl_wd_i2_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(23), + Q => phy_ctl_wd_i2(23), + R => '0' + ); +\phy_ctl_wd_i2_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(24), + Q => phy_ctl_wd_i2(24), + R => '0' + ); +\phy_ctl_wd_i2_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wd_i1(2), + Q => phy_ctl_wd_i2(2), + R => '0' + ); +phy_ctl_wr_i1_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wr_i1_reg_0, + Q => phy_ctl_wr_i1, + R => '0' + ); +phy_ctl_wr_i2_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => phy_ctl_wr_i1, + Q => phy_ctl_wr_i2, + R => '0' + ); +u_cas_n_obuf: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(18), + O => ddr3_cas_n + ); +u_ddr_mc_phy: entity work.ddr3_mig_7series_v4_2_ddr_mc_phy + port map ( + A_rst_primitives_reg => A_rst_primitives, + A_rst_primitives_reg_0 => A_rst_primitives_reg, + A_rst_primitives_reg_1 => A_rst_primitives_reg_0, + CLK => CLK, + CLKB0 => CLKB0, + CLKB0_4 => CLKB0_4, + COUNTERLOADVAL(5 downto 0) => COUNTERLOADVAL(5 downto 0), + D(127 downto 0) => D(127 downto 0), + D0(7 downto 0) => D0(7 downto 0), + D1(7 downto 0) => D1(7 downto 0), + D2(7 downto 0) => D2(7 downto 0), + D3(7 downto 0) => D3(7 downto 0), + D4(7 downto 0) => D4(7 downto 0), + D5(7 downto 0) => D5(7 downto 0), + D6(7 downto 0) => D6(7 downto 0), + D7(7 downto 0) => D7(7 downto 0), + D8(7 downto 0) => D8(7 downto 0), + D9(7 downto 0) => D9(7 downto 0), + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => DIC(1 downto 0), + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + LD0 => LD0, + LD0_0 => LD0_0, + Q(10 downto 3) => phy_ctl_wd_i2(24 downto 17), + Q(2 downto 0) => phy_ctl_wd_i2(2 downto 0), + RST0 => RST0, + SR(0) => SR(0), + calib_cmd_wren => calib_cmd_wren, + calib_sel(1 downto 0) => calib_sel(1 downto 0), + calib_wrdata_en => calib_wrdata_en, + ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0), + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0) => Q(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(1 downto 0), + freq_refclk => freq_refclk, + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\, + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0), + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + idelay_inc => idelay_inc, + idelay_ld_rst => idelay_ld_rst, + ififo_rst_reg0 => ififo_rst_reg0, + ififo_rst_reg0_1 => ififo_rst_reg0_1, + in0 => in0, + init_complete_r1_timing_reg => init_complete_r1_timing_reg, + \input_[9].iserdes_dq_.iserdesdq\ => \input_[9].iserdes_dq_.iserdesdq\, + \input_[9].iserdes_dq_.iserdesdq_0\ => \input_[9].iserdes_dq_.iserdesdq_0\, + \mcGo_r_reg[0]_0\(0) => \mcGo_r_reg[0]\(0), + \mcGo_r_reg[15]_0\(0) => \mcGo_r_reg[15]\(0), + mc_address(5 downto 0) => mc_address(5 downto 0), + mc_cas_n(0) => mc_cas_n(0), + mc_wrdata_en => mc_wrdata_en, + mem_dq_in(15 downto 10) => mem_dq_in(39 downto 34), + mem_dq_in(9) => mem_dq_in(32), + mem_dq_in(8 downto 3) => mem_dq_in(30 downto 25), + mem_dq_in(2 downto 0) => mem_dq_in(23 downto 21), + mem_dq_out(40 downto 35) => mem_dq_out(45 downto 40), + mem_dq_out(34 downto 32) => mem_dq_out(38 downto 36), + mem_dq_out(31 downto 23) => mem_dq_out(33 downto 25), + mem_dq_out(22 downto 10) => mem_dq_out(23 downto 11), + mem_dq_out(9 downto 0) => mem_dq_out(9 downto 0), + mem_dq_ts(17 downto 12) => mem_dq_ts(45 downto 40), + mem_dq_ts(11 downto 9) => mem_dq_ts(38 downto 36), + mem_dq_ts(8 downto 0) => mem_dq_ts(33 downto 25), + mem_dqs_in(1 downto 0) => mem_dqs_in(3 downto 2), + mem_out(2 downto 0) => mem_out(2 downto 0), + mem_refclk => mem_refclk, + mux_cmd_wren => mux_cmd_wren, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[0]\ => \my_empty_reg[0]\, + \my_empty_reg[0]_0\ => \my_empty_reg[0]_0\, + \my_empty_reg[1]\ => \my_empty_reg[1]\, + \my_empty_reg[1]_0\ => \my_empty_reg[1]_0\, + \my_empty_reg[1]_1\ => \my_empty_reg[1]_1\, + \my_empty_reg[1]_2\ => \my_empty_reg[1]_2\, + \my_empty_reg[4]_rep__0\ => \my_empty_reg[4]_rep__0\, + \my_empty_reg[4]_rep__1\ => \my_empty_reg[4]_rep__1\, + \my_empty_reg[7]\(7 downto 0) => \my_empty_reg[7]\(7 downto 0), + \my_empty_reg[7]_0\(7 downto 0) => \my_empty_reg[7]_0\(7 downto 0), + \my_empty_reg[7]_1\(7 downto 0) => \my_empty_reg[7]_1\(7 downto 0), + \my_empty_reg[7]_10\(3 downto 0) => \my_empty_reg[7]_10\(3 downto 0), + \my_empty_reg[7]_11\(3 downto 0) => \my_empty_reg[7]_11\(3 downto 0), + \my_empty_reg[7]_12\(3 downto 0) => \my_empty_reg[7]_12\(3 downto 0), + \my_empty_reg[7]_13\(3 downto 0) => \my_empty_reg[7]_13\(3 downto 0), + \my_empty_reg[7]_14\(3 downto 0) => \my_empty_reg[7]_14\(3 downto 0), + \my_empty_reg[7]_2\(7 downto 0) => \my_empty_reg[7]_2\(7 downto 0), + \my_empty_reg[7]_3\(7 downto 0) => \my_empty_reg[7]_3\(7 downto 0), + \my_empty_reg[7]_4\(7 downto 0) => \my_empty_reg[7]_4\(7 downto 0), + \my_empty_reg[7]_5\(7 downto 0) => \my_empty_reg[7]_5\(7 downto 0), + \my_empty_reg[7]_6\(7 downto 0) => \my_empty_reg[7]_6\(7 downto 0), + \my_empty_reg[7]_7\(3 downto 0) => \my_empty_reg[7]_7\(3 downto 0), + \my_empty_reg[7]_8\(3 downto 0) => \my_empty_reg[7]_8\(3 downto 0), + \my_empty_reg[7]_9\(3 downto 0) => \my_empty_reg[7]_9\(3 downto 0), + \not_strict_mode.app_rd_data[127]_i_2\(0) => \not_strict_mode.app_rd_data[127]_i_2\(0), + \not_strict_mode.app_rd_data_reg[101]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[103]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[105]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[109]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[111]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[115]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[121]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[123]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[13]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[15]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[19]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[21]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[25]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[27]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[31]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[33]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[37]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[39]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[43]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[45]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[49]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[51]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[55]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[57]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[61]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[63]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[67]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[69]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[73]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[75]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[79]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[7]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[81]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[85]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[87]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\, + \not_strict_mode.app_rd_data_reg[91]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[93]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[97]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[99]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[9]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]\(1 downto 0), + ofifo_rst_reg0 => ofifo_rst_reg0, + ofifo_rst_reg0_2 => ofifo_rst_reg0_2, + \out\(1 downto 0) => \out\(1 downto 0), + out_dqs_0 => out_dqs_0, + out_dqs_1 => out_dqs_1, + out_fifo => out_fifo, + p_1_in => p_1_in, + phy_ctl_wr_i2 => phy_ctl_wr_i2, + phy_dout(39 downto 0) => phy_dout(39 downto 0), + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_data_full => phy_mc_data_full, + phy_rddata_en => phy_rddata_en, + phy_read_calib => phy_read_calib, + phy_write_calib => phy_write_calib, + \pi_counter_read_val_reg[5]\ => \pi_counter_read_val_reg[5]\, + \pi_counter_read_val_reg[5]_0\(5 downto 0) => \pi_counter_read_val_reg[5]_0\(5 downto 0), + pi_dqs_found_lanes(1 downto 0) => pi_dqs_found_lanes(1 downto 0), + \pi_dqs_found_lanes_r1_reg[2]\ => \pi_dqs_found_lanes_r1_reg[2]\, + \pi_dqs_found_lanes_r1_reg[2]_0\ => \pi_dqs_found_lanes_r1_reg[2]_0\, + \pi_dqs_found_lanes_r1_reg[2]_1\ => \pi_dqs_found_lanes_r1_reg[2]_1\, + \pi_dqs_found_lanes_r1_reg[2]_2\ => \pi_dqs_found_lanes_r1_reg[2]_2\, + \pi_dqs_found_lanes_r1_reg[2]_3\ => \pi_dqs_found_lanes_r1_reg[2]_3\, + \pi_dqs_found_lanes_r1_reg[3]\ => \pi_dqs_found_lanes_r1_reg[3]\, + \pi_dqs_found_lanes_r1_reg[3]_0\ => \pi_dqs_found_lanes_r1_reg[3]_0\, + \pi_dqs_found_lanes_r1_reg[3]_1\ => \pi_dqs_found_lanes_r1_reg[3]_1\, + \pi_dqs_found_lanes_r1_reg[3]_2\ => \pi_dqs_found_lanes_r1_reg[3]_2\, + \pi_dqs_found_lanes_r1_reg[3]_3\ => \pi_dqs_found_lanes_r1_reg[3]_3\, + \pi_dqs_found_lanes_r1_reg[3]_4\(5 downto 0) => \pi_dqs_found_lanes_r1_reg[3]_4\(5 downto 0), + pll_locked => pll_locked, + \po_counter_read_val_reg[8]\(8 downto 0) => \po_counter_read_val_reg[8]\(8 downto 0), + \po_counter_read_val_reg[8]_0\ => \po_counter_read_val_reg[8]_0\, + \po_counter_read_val_reg[8]_1\ => \po_counter_read_val_reg[8]_1\, + \po_counter_read_val_reg[8]_10\ => \po_counter_read_val_reg[8]_10\, + \po_counter_read_val_reg[8]_11\ => \po_counter_read_val_reg[8]_11\, + \po_counter_read_val_reg[8]_12\ => \po_counter_read_val_reg[8]_12\, + \po_counter_read_val_reg[8]_13\ => \po_counter_read_val_reg[8]_13\, + \po_counter_read_val_reg[8]_2\ => \po_counter_read_val_reg[8]_2\, + \po_counter_read_val_reg[8]_3\ => \po_counter_read_val_reg[8]_3\, + \po_counter_read_val_reg[8]_4\ => \po_counter_read_val_reg[8]_4\, + \po_counter_read_val_reg[8]_5\ => \po_counter_read_val_reg[8]_5\, + \po_counter_read_val_reg[8]_6\ => \po_counter_read_val_reg[8]_6\, + \po_counter_read_val_reg[8]_7\ => \po_counter_read_val_reg[8]_7\, + \po_counter_read_val_reg[8]_8\ => \po_counter_read_val_reg[8]_8\, + \po_counter_read_val_reg[8]_9\ => \po_counter_read_val_reg[8]_9\, + rd_data_en => rd_data_en, + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\, + \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\, + \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\, + \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\, + \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\, + \rd_ptr_reg[3]_10\(3 downto 0) => \rd_ptr_reg[3]_10\(3 downto 0), + \rd_ptr_reg[3]_11\(3 downto 0) => \rd_ptr_reg[3]_11\(3 downto 0), + \rd_ptr_reg[3]_12\(2 downto 0) => \rd_ptr_reg[3]_12\(2 downto 0), + \rd_ptr_reg[3]_2\(31 downto 0) => \rd_ptr_reg[3]_2\(31 downto 0), + \rd_ptr_reg[3]_3\(3 downto 0) => \rd_ptr_reg[3]_3\(3 downto 0), + \rd_ptr_reg[3]_4\(3 downto 0) => \rd_ptr_reg[3]_4\(3 downto 0), + \rd_ptr_reg[3]_5\(2 downto 0) => \rd_ptr_reg[3]_5\(2 downto 0), + \rd_ptr_reg[3]_6\(3 downto 0) => \rd_ptr_reg[3]_6\(3 downto 0), + \rd_ptr_reg[3]_7\(3 downto 0) => \rd_ptr_reg[3]_7\(3 downto 0), + \rd_ptr_reg[3]_8\(7 downto 0) => \rd_ptr_reg[3]_8\(7 downto 0), + \rd_ptr_reg[3]_9\(6 downto 0) => \rd_ptr_reg[3]_9\(6 downto 0), + \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + \read_fifo.tail_r_reg\(0) => \read_fifo.tail_r_reg\(0), + \read_fifo.tail_r_reg_0_sp_1\ => \read_fifo.tail_r_reg_0_sn_1\, + ref_dll_lock => ref_dll_lock, + sync_pulse => sync_pulse, + ts_dqs_0 => ts_dqs_0, + ts_dqs_1 => ts_dqs_1, + wr_en => wr_en, + wr_en_2 => wr_en_2, + wr_en_3 => wr_en_3, + \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\, + \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\, + \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\, + \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0), + \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0), + \wr_ptr_timing_reg[0]\ => \wr_ptr_timing_reg[0]\, + \wr_ptr_timing_reg[0]_0\ => \wr_ptr_timing_reg[0]_0\, + \wr_ptr_timing_reg[0]_1\ => \wr_ptr_timing_reg[0]_1\ + ); +u_ras_n_obuf: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(14), + O => ddr3_ras_n + ); +u_we_n_obuf: unisim.vcomponents.OBUF + generic map( + IOSTANDARD => "DEFAULT" + ) + port map ( + I => mem_dq_out(21), + O => ddr3_we_n + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_mc is + port ( + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + \generate_maint_cmds.insert_maint_r_lcl_reg\ : out STD_LOGIC; + periodic_rd_ack_r_lcl_reg : out STD_LOGIC; + accept_ns : out STD_LOGIC; + mc_cmd : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \periodic_read_request.periodic_rd_r_lcl_reg\ : out STD_LOGIC; + app_sr_active : out STD_LOGIC; + periodic_rd_cntr_r_reg : out STD_LOGIC; + idle_r_lcl_reg : out STD_LOGIC; + idle_r_lcl_reg_0 : out STD_LOGIC; + idle_r_lcl_reg_1 : out STD_LOGIC; + idle_r_lcl_reg_2 : out STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[6]\ : out STD_LOGIC; + Q : out STD_LOGIC_VECTOR ( 7 downto 0 ); + \read_fifo.tail_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_we_n_reg[2]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + mc_cas_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_ras_n : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.mc_we_n_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \cmd_pipe_plus.wr_data_en_reg_0\ : out STD_LOGIC; + wr_data_en : out STD_LOGIC; + \req_bank_r_lcl_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_bank_r_lcl_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_bank_r_lcl_reg[2]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_bank_r_lcl_reg[2]_2\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + \not_strict_mode.app_rd_data_end_ns\ : out STD_LOGIC; + \not_strict_mode.bypass__0\ : out STD_LOGIC; + wr_data_addr : out STD_LOGIC_VECTOR ( 3 downto 0 ); + mc_ref_zq_wip : out STD_LOGIC; + \cmd_pipe_plus.mc_address_reg[44]_0\ : out STD_LOGIC_VECTOR ( 40 downto 0 ); + \cmd_pipe_plus.mc_bank_reg[8]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); + mc_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + mc_wrdata_en : out STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_data_offset_reg[5]_0\ : out STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[4]_0\ : out STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[2]_0\ : out STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[1]_0\ : out STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[0]_0\ : out STD_LOGIC; + idle : out STD_LOGIC; + CLK : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg : in STD_LOGIC; + rb_hit_busy_r_reg_0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + rb_hit_busy_r_reg_2 : in STD_LOGIC; + phy_mc_ctl_full : in STD_LOGIC; + phy_mc_cmd_full : in STD_LOGIC; + was_wr0 : in STD_LOGIC; + \maintenance_request.maint_zq_r_lcl_reg\ : in STD_LOGIC; + \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC; + rnk_config_valid_r_lcl_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \periodic_read_request.periodic_rd_r_lcl_reg_0\ : in STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[5]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \grant_r_reg[0]\ : in STD_LOGIC; + app_zq_req : in STD_LOGIC; + app_sr_req : in STD_LOGIC; + \last_master_r_reg[2]\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC; + was_priority_reg : in STD_LOGIC; + app_en_r2 : in STD_LOGIC; + \read_fifo.tail_r_reg[1]\ : in STD_LOGIC; + ram_init_done_r : in STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[5]\ : in STD_LOGIC; + \inhbt_act_faw.inhbt_act_faw_r_reg\ : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ : in STD_LOGIC; + rd_wr_r_lcl_reg : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + phy_mc_data_full : in STD_LOGIC; + \rtp_timer_r_reg[0]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data_end_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + rd_data_en : in STD_LOGIC; + \not_strict_mode.app_rd_data_end_reg_0\ : in STD_LOGIC; + ram_init_addr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \req_data_buf_addr_r_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]_3\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \read_fifo.head_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC; + \read_fifo.tail_r_reg[0]_0\ : in STD_LOGIC; + \cmd_pipe_plus.mc_data_offset_reg[0]_1\ : in STD_LOGIC + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_mc : entity is "mig_7series_v4_2_mc"; +end ddr3_mig_7series_v4_2_mc; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_mc is + signal \arb_mux0/arb_select0/cke_r\ : STD_LOGIC; + signal \arb_mux0/arb_select0/mc_aux_out0_1\ : STD_LOGIC; + signal \arb_mux0/arb_select0/mc_data_offset1\ : STD_LOGIC_VECTOR ( 5 downto 1 ); + signal \bank_cntrl[0].bank0/q_has_rd\ : STD_LOGIC; + signal \bank_cntrl[0].bank0/wait_for_maint_r\ : STD_LOGIC; + signal \bank_cntrl[1].bank0/q_has_rd\ : STD_LOGIC; + signal \bank_cntrl[1].bank0/wait_for_maint_r\ : STD_LOGIC; + signal \bank_cntrl[2].bank0/q_has_rd\ : STD_LOGIC; + signal \bank_cntrl[2].bank0/wait_for_maint_r\ : STD_LOGIC; + signal \bank_cntrl[3].bank0/q_has_rd\ : STD_LOGIC; + signal \bank_cntrl[3].bank0/wait_for_maint_r\ : STD_LOGIC; + signal bank_mach0_n_102 : STD_LOGIC; + signal bank_mach0_n_31 : STD_LOGIC; + signal bank_mach0_n_32 : STD_LOGIC; + signal bank_mach0_n_33 : STD_LOGIC; + signal bank_mach0_n_34 : STD_LOGIC; + signal bank_mach0_n_35 : STD_LOGIC; + signal bank_mach0_n_37 : STD_LOGIC; + signal bank_mach0_n_47 : STD_LOGIC; + signal bank_mach0_n_48 : STD_LOGIC; + signal bank_mach0_n_54 : STD_LOGIC; + signal clear_periodic_rd_request : STD_LOGIC; + signal \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\ : STD_LOGIC; + signal \cmd_pipe_plus.mc_ras_n[1]_i_1_n_0\ : STD_LOGIC; + signal \^cmd_pipe_plus.mc_we_n_reg[2]_1\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal col_data_buf_addr : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal col_mach0_n_16 : STD_LOGIC; + signal col_periodic_rd : STD_LOGIC; + signal col_rd_wr : STD_LOGIC; + signal \^generate_maint_cmds.insert_maint_r_lcl_reg\ : STD_LOGIC; + signal idle_r : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal inhbt_act_faw_r : STD_LOGIC; + signal insert_maint_r1 : STD_LOGIC; + signal maint_ref_zq_wip : STD_LOGIC; + signal maint_req_r : STD_LOGIC; + signal maint_srx_r : STD_LOGIC; + signal maint_wip_r : STD_LOGIC; + signal maint_zq_r : STD_LOGIC; + signal mc_address_ns : STD_LOGIC_VECTOR ( 44 downto 0 ); + signal mc_bank_ns : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \^mc_cas_n\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_cas_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_cke_ns : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \^mc_cmd\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal mc_data_offset_ns : STD_LOGIC_VECTOR ( 3 to 3 ); + signal mc_odt_ns : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \^mc_ras_n\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_ras_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_ref_zq_wip_ns : STD_LOGIC; + signal mc_we_n_ns : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_wrdata_en_ns : STD_LOGIC; + signal \^periodic_rd_ack_r_lcl_reg\ : STD_LOGIC; + signal \^periodic_rd_cntr_r_reg\ : STD_LOGIC; + signal \^periodic_read_request.periodic_rd_r_lcl_reg\ : STD_LOGIC; + signal \rank_cntrl[0].rank_cntrl0/act_this_rank\ : STD_LOGIC; + signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\ : STD_LOGIC; + signal \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\ : STD_LOGIC; + signal \rank_common0/periodic_read_request.periodic_rd_grant_r\ : STD_LOGIC; + signal rank_mach0_n_12 : STD_LOGIC; + signal rank_mach0_n_13 : STD_LOGIC; + signal rank_mach0_n_14 : STD_LOGIC; + signal rank_mach0_n_15 : STD_LOGIC; + signal rank_mach0_n_16 : STD_LOGIC; + signal rank_mach0_n_18 : STD_LOGIC; + signal rank_mach0_n_19 : STD_LOGIC; + signal rank_mach0_n_20 : STD_LOGIC; + signal rank_mach0_n_21 : STD_LOGIC; + signal rank_mach0_n_22 : STD_LOGIC; + signal rank_mach0_n_23 : STD_LOGIC; + signal rank_mach0_n_24 : STD_LOGIC; + signal rank_mach0_n_25 : STD_LOGIC; + signal rank_mach0_n_26 : STD_LOGIC; + signal rank_mach0_n_27 : STD_LOGIC; + signal rank_mach0_n_28 : STD_LOGIC; + signal rank_mach0_n_29 : STD_LOGIC; + signal rank_mach0_n_30 : STD_LOGIC; + signal rank_mach0_n_31 : STD_LOGIC; + signal rank_mach0_n_32 : STD_LOGIC; + signal rank_mach0_n_33 : STD_LOGIC; + signal rank_mach0_n_34 : STD_LOGIC; + signal rank_mach0_n_35 : STD_LOGIC; + signal rank_mach0_n_36 : STD_LOGIC; + signal rank_mach0_n_37 : STD_LOGIC; + signal rank_mach0_n_38 : STD_LOGIC; + signal rank_mach0_n_39 : STD_LOGIC; + signal rank_mach0_n_40 : STD_LOGIC; + signal rank_mach0_n_41 : STD_LOGIC; + signal rank_mach0_n_42 : STD_LOGIC; + signal rank_mach0_n_43 : STD_LOGIC; + signal rank_mach0_n_44 : STD_LOGIC; + signal rank_mach0_n_45 : STD_LOGIC; + signal rank_mach0_n_46 : STD_LOGIC; + signal sending_col : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal sent_col : STD_LOGIC; + signal wr_data_addr_ns : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^wr_data_en\ : STD_LOGIC; + signal wr_data_en_ns : STD_LOGIC; + signal \wtr_timer.wtr_cnt_r\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\ : STD_LOGIC; + signal \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\ : STD_LOGIC; + signal \NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); + attribute syn_maxfan : string; + attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[0]\ : label is "30"; + attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[1]\ : label is "30"; + attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[2]\ : label is "30"; + attribute syn_maxfan of \cmd_pipe_plus.wr_data_addr_reg[3]\ : label is "30"; + attribute ADDER_THRESHOLD : integer; + attribute ADDER_THRESHOLD of \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3\ : label is 11; + attribute ADDER_THRESHOLD of \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1\ : label is 11; + attribute ADDER_THRESHOLD of \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1\ : label is 11; +begin + \cmd_pipe_plus.mc_we_n_reg[2]_1\(2 downto 0) <= \^cmd_pipe_plus.mc_we_n_reg[2]_1\(2 downto 0); + \generate_maint_cmds.insert_maint_r_lcl_reg\ <= \^generate_maint_cmds.insert_maint_r_lcl_reg\; + mc_cas_n(2 downto 0) <= \^mc_cas_n\(2 downto 0); + mc_cmd(1 downto 0) <= \^mc_cmd\(1 downto 0); + mc_ras_n(2 downto 0) <= \^mc_ras_n\(2 downto 0); + periodic_rd_ack_r_lcl_reg <= \^periodic_rd_ack_r_lcl_reg\; + periodic_rd_cntr_r_reg <= \^periodic_rd_cntr_r_reg\; + \periodic_read_request.periodic_rd_r_lcl_reg\ <= \^periodic_read_request.periodic_rd_r_lcl_reg\; + wr_data_en <= \^wr_data_en\; +bank_mach0: entity work.ddr3_mig_7series_v4_2_bank_mach + port map ( + CLK => CLK, + D(2) => mc_we_n_ns(2), + D(1) => bank_mach0_n_37, + D(0) => mc_we_n_ns(0), + DIC(0) => col_periodic_rd, + I119(0) => mc_odt_ns(0), + I120(0) => mc_cke_ns(1), + I121(0) => bank_mach0_n_35, + Q(3 downto 0) => sending_col(3 downto 0), + S(3 downto 0) => S(3 downto 0), + SR(0) => SR(0), + accept_internal_r_reg => \grant_r_reg[0]\, + accept_ns => accept_ns, + act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\, + app_en_r2 => app_en_r2, + auto_pre_r_lcl_reg => rank_mach0_n_43, + cke_r => \arb_mux0/arb_select0/cke_r\, + clear_periodic_rd_request => clear_periodic_rd_request, + \cmd_pipe_plus.mc_data_offset_reg[5]\(5 downto 0) => \cmd_pipe_plus.mc_data_offset_reg[5]_1\(5 downto 0), + \cmd_pipe_plus.mc_odt_reg[0]\ => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\, + col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0), + col_rd_wr => col_rd_wr, + col_wait_r_reg => \last_master_r_reg[2]\, + \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3]\(3 downto 0) => wr_data_addr_ns(3 downto 0), + \generate_maint_cmds.insert_maint_r_lcl_reg\ => \^generate_maint_cmds.insert_maint_r_lcl_reg\, + \grant_r[3]_i_4\(0) => \wtr_timer.wtr_cnt_r\(1), + \grant_r_reg[0]\ => bank_mach0_n_54, + granted_col_r_reg => bank_mach0_n_47, + granted_col_r_reg_0(0) => mc_data_offset_ns(3), + idle_r(3 downto 0) => idle_r(3 downto 0), + idle_r_lcl_reg => idle_r_lcl_reg, + idle_r_lcl_reg_0 => idle_r_lcl_reg_0, + idle_r_lcl_reg_1 => idle_r_lcl_reg_1, + idle_r_lcl_reg_2 => idle_r_lcl_reg_2, + inhbt_act_faw_r => inhbt_act_faw_r, + insert_maint_r1 => insert_maint_r1, + \maint_controller.maint_hit_busies_r_reg[3]\ => rank_mach0_n_42, + \maint_controller.maint_wip_r_lcl_reg\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + maint_req_r => maint_req_r, + maint_srx_r => maint_srx_r, + maint_wip_r => maint_wip_r, + maint_zq_r => maint_zq_r, + mc_aux_out0_1 => \arb_mux0/arb_select0/mc_aux_out0_1\, + mc_cas_n_ns(2 downto 0) => mc_cas_n_ns(2 downto 0), + mc_ras_n_ns(1) => mc_ras_n_ns(2), + mc_ras_n_ns(0) => mc_ras_n_ns(0), + pass_open_bank_r_lcl_reg => rank_mach0_n_44, + periodic_rd_ack_r_lcl_reg => \^periodic_rd_ack_r_lcl_reg\, + periodic_rd_ack_r_lcl_reg_0 => bank_mach0_n_31, + periodic_rd_ack_r_lcl_reg_1 => bank_mach0_n_32, + periodic_rd_ack_r_lcl_reg_2 => bank_mach0_n_33, + periodic_rd_ack_r_lcl_reg_3 => bank_mach0_n_34, + periodic_rd_cntr_r_reg => \^periodic_rd_cntr_r_reg\, + periodic_rd_cntr_r_reg_0 => \^periodic_read_request.periodic_rd_r_lcl_reg\, + \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\, + \periodic_rd_generation.read_this_rank_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\, + \periodic_rd_generation.read_this_rank_r_reg\ => bank_mach0_n_48, + \periodic_read_request.periodic_rd_grant_r\ => \rank_common0/periodic_read_request.periodic_rd_grant_r\, + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_data_full => phy_mc_data_full, + \pre_4_1_1T_arb.granted_pre_r_reg\(40 downto 26) => mc_address_ns(44 downto 30), + \pre_4_1_1T_arb.granted_pre_r_reg\(25 downto 0) => mc_address_ns(25 downto 0), + \pre_4_1_1T_arb.granted_pre_r_reg_0\(8 downto 0) => mc_bank_ns(8 downto 0), + \q_entry_r_reg[0]\(0) => \read_fifo.head_r_reg[0]\(0), + q_has_rd => \bank_cntrl[0].bank0/q_has_rd\, + q_has_rd_0 => \bank_cntrl[1].bank0/q_has_rd\, + q_has_rd_1 => \bank_cntrl[2].bank0/q_has_rd\, + q_has_rd_2 => \bank_cntrl[3].bank0/q_has_rd\, + q_has_rd_r_reg => rank_mach0_n_41, + q_has_rd_r_reg_0 => rank_mach0_n_39, + q_has_rd_r_reg_1 => rank_mach0_n_40, + q_has_rd_r_reg_2 => rank_mach0_n_38, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3 downto 2) => \arb_mux0/arb_select0/mc_data_offset1\(5 downto 4), + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1 downto 0) => \arb_mux0/arb_select0/mc_data_offset1\(2 downto 1), + rb_hit_busy_r_reg => rb_hit_busy_r_reg, + rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0, + rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1, + rb_hit_busy_r_reg_2 => rb_hit_busy_r_reg_2, + rd_wr_r_lcl_reg => rd_wr_r_lcl_reg, + \req_bank_r_lcl_reg[2]\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0), + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => \req_bank_r_lcl_reg[2]_0\(2 downto 0), + \req_bank_r_lcl_reg[2]_1\(2 downto 0) => \req_bank_r_lcl_reg[2]_1\(2 downto 0), + \req_bank_r_lcl_reg[2]_2\(2 downto 0) => \req_bank_r_lcl_reg[2]_2\(2 downto 0), + \req_bank_r_lcl_reg[2]_3\(2 downto 0) => \req_bank_r_lcl_reg[2]_3\(2 downto 0), + \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_data_buf_addr_r_reg[4]\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + \req_row_r_lcl_reg[14]\(14 downto 0) => \req_row_r_lcl_reg[14]\(14 downto 0), + req_wr_r_lcl0 => req_wr_r_lcl0, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]\ => \inhbt_act_faw.inhbt_act_faw_r_reg\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]\ => rank_mach0_n_45, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]\ => rank_mach0_n_46, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => bank_mach0_n_102, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\(0) => rank_mach0_n_16, + rnk_config_valid_r_lcl_reg(0) => rnk_config_valid_r_lcl_reg(0), + row(14 downto 0) => row(14 downto 0), + row_hit_r_reg(0) => row_hit_r_reg(0), + \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\, + sent_col => sent_col, + wait_for_maint_r => \bank_cntrl[0].bank0/wait_for_maint_r\, + wait_for_maint_r_3 => \bank_cntrl[1].bank0/wait_for_maint_r\, + wait_for_maint_r_4 => \bank_cntrl[2].bank0/wait_for_maint_r\, + wait_for_maint_r_5 => \bank_cntrl[3].bank0/wait_for_maint_r\, + wait_for_maint_r_lcl_reg => rank_mach0_n_12, + wait_for_maint_r_lcl_reg_0 => rank_mach0_n_15, + wait_for_maint_r_lcl_reg_1 => rank_mach0_n_14, + wait_for_maint_r_lcl_reg_2 => rank_mach0_n_13, + was_priority_reg => was_priority_reg, + was_wr0 => was_wr0 + ); +\cmd_pipe_plus.mc_address_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(0), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(0), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[10]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(10), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(10), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[11]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(11), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(11), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[12]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(12), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(12), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[13]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(13), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(13), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[14]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(14), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(14), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[15]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(15), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(15), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[16]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(16), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(16), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[17]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(17), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(17), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[18]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(18), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(18), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[19]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(19), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(19), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(1), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(1), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[20]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(20), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(20), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[21]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(21), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(21), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[22]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(22), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(22), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[23]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(23), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(23), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[24]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(24), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(24), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[25]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(25), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(25), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(2), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(2), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[30]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(30), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(26), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[31]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(31), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(27), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[32]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(32), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(28), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[33]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(33), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(29), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[34]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(34), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(30), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[35]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(35), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(31), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[36]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(36), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(32), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[37]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(37), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(33), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[38]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(38), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(34), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[39]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(39), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(35), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(3), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(3), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[40]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(40), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(36), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[41]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(41), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(37), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[42]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(42), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(38), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[43]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(43), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(39), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[44]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(44), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(40), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(4), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(4), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(5), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(5), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(6), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(6), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(7), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(7), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(8), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(8), + R => '0' + ); +\cmd_pipe_plus.mc_address_reg[9]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_address_ns(9), + Q => \cmd_pipe_plus.mc_address_reg[44]_0\(9), + R => '0' + ); +\cmd_pipe_plus.mc_aux_out0_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \arb_mux0/arb_select0/mc_aux_out0_1\, + Q => \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1]\, + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(0), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(0), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(1), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(1), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(2), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(2), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(3), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(3), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(4), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(4), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(5), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(5), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[6]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(6), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(6), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[7]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(7), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(7), + R => '0' + ); +\cmd_pipe_plus.mc_bank_reg[8]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_bank_ns(8), + Q => \cmd_pipe_plus.mc_bank_reg[8]_0\(8), + R => '0' + ); +\cmd_pipe_plus.mc_cas_n_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_cas_n_ns(0), + Q => \^mc_cas_n\(0), + R => '0' + ); +\cmd_pipe_plus.mc_cas_n_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_cas_n_ns(1), + Q => \^mc_cas_n\(1), + R => '0' + ); +\cmd_pipe_plus.mc_cas_n_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_cas_n_ns(2), + Q => \^mc_cas_n\(2), + R => '0' + ); +\cmd_pipe_plus.mc_cke_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_cke_ns(1), + Q => mc_cke(0), + R => '0' + ); +\cmd_pipe_plus.mc_cmd_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => sent_col, + Q => \^mc_cmd\(0), + R => '0' + ); +\cmd_pipe_plus.mc_cmd_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bank_mach0_n_35, + Q => \^mc_cmd\(1), + R => '0' + ); +\cmd_pipe_plus.mc_data_offset_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cmd_pipe_plus.mc_data_offset_reg[0]_1\, + Q => \cmd_pipe_plus.mc_data_offset_reg[0]_0\, + R => bank_mach0_n_47 + ); +\cmd_pipe_plus.mc_data_offset_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \arb_mux0/arb_select0/mc_data_offset1\(1), + Q => \cmd_pipe_plus.mc_data_offset_reg[1]_0\, + R => bank_mach0_n_47 + ); +\cmd_pipe_plus.mc_data_offset_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \arb_mux0/arb_select0/mc_data_offset1\(2), + Q => \cmd_pipe_plus.mc_data_offset_reg[2]_0\, + R => bank_mach0_n_47 + ); +\cmd_pipe_plus.mc_data_offset_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_data_offset_ns(3), + Q => \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0), + R => '0' + ); +\cmd_pipe_plus.mc_data_offset_reg[4]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \arb_mux0/arb_select0/mc_data_offset1\(4), + Q => \cmd_pipe_plus.mc_data_offset_reg[4]_0\, + R => bank_mach0_n_47 + ); +\cmd_pipe_plus.mc_data_offset_reg[5]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \arb_mux0/arb_select0/mc_data_offset1\(5), + Q => \cmd_pipe_plus.mc_data_offset_reg[5]_0\, + R => bank_mach0_n_47 + ); +\cmd_pipe_plus.mc_odt_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_odt_ns(0), + Q => mc_odt(0), + R => '0' + ); +\cmd_pipe_plus.mc_ras_n[1]_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"FFFEFFFF" + ) + port map ( + I0 => sending_col(1), + I1 => sending_col(0), + I2 => sending_col(3), + I3 => sending_col(2), + I4 => sent_col, + O => \cmd_pipe_plus.mc_ras_n[1]_i_1_n_0\ + ); +\cmd_pipe_plus.mc_ras_n_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_ras_n_ns(0), + Q => \^mc_ras_n\(0), + R => '0' + ); +\cmd_pipe_plus.mc_ras_n_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => \cmd_pipe_plus.mc_ras_n[1]_i_1_n_0\, + Q => \^mc_ras_n\(1), + R => '0' + ); +\cmd_pipe_plus.mc_ras_n_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_ras_n_ns(2), + Q => \^mc_ras_n\(2), + R => '0' + ); +\cmd_pipe_plus.mc_we_n_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_we_n_ns(0), + Q => \^cmd_pipe_plus.mc_we_n_reg[2]_1\(0), + R => '0' + ); +\cmd_pipe_plus.mc_we_n_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => bank_mach0_n_37, + Q => \^cmd_pipe_plus.mc_we_n_reg[2]_1\(1), + R => '0' + ); +\cmd_pipe_plus.mc_we_n_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_we_n_ns(2), + Q => \^cmd_pipe_plus.mc_we_n_reg[2]_1\(2), + R => '0' + ); +\cmd_pipe_plus.mc_wrdata_en_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_wrdata_en_ns, + Q => mc_wrdata_en, + R => '0' + ); +\cmd_pipe_plus.wr_data_addr_reg[0]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_data_addr_ns(0), + Q => wr_data_addr(0), + R => '0' + ); +\cmd_pipe_plus.wr_data_addr_reg[1]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_data_addr_ns(1), + Q => wr_data_addr(1), + R => '0' + ); +\cmd_pipe_plus.wr_data_addr_reg[2]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_data_addr_ns(2), + Q => wr_data_addr(2), + R => '0' + ); +\cmd_pipe_plus.wr_data_addr_reg[3]\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_data_addr_ns(3), + Q => wr_data_addr(3), + R => '0' + ); +\cmd_pipe_plus.wr_data_en_reg\: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => wr_data_en_ns, + Q => \^wr_data_en\, + R => '0' + ); +col_mach0: entity work.ddr3_mig_7series_v4_2_col_mach + port map ( + CLK => CLK, + D(3 downto 0) => wr_data_addr_ns(3 downto 0), + DIC(0) => col_periodic_rd, + I121(0) => bank_mach0_n_35, + Q(7 downto 0) => Q(7 downto 0), + col_data_buf_addr(4 downto 0) => col_data_buf_addr(4 downto 0), + col_rd_wr => col_rd_wr, + maint_ref_zq_wip => maint_ref_zq_wip, + mc_cmd(0) => \^mc_cmd\(0), + mc_ref_zq_wip_ns => mc_ref_zq_wip_ns, + mc_wrdata_en_ns => mc_wrdata_en_ns, + \not_strict_mode.app_rd_data_end_ns\ => \not_strict_mode.app_rd_data_end_ns\, + \not_strict_mode.app_rd_data_end_reg\(0) => \not_strict_mode.app_rd_data_end_reg\(0), + \not_strict_mode.app_rd_data_end_reg_0\ => \not_strict_mode.app_rd_data_end_reg_0\, + \not_strict_mode.bypass__0\ => \not_strict_mode.bypass__0\, + ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0), + ram_init_done_r => ram_init_done_r, + rd_data_en => rd_data_en, + \read_fifo.fifo_out_data_r_reg[5]_0\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + \read_fifo.fifo_out_data_r_reg[5]_1\ => \read_fifo.fifo_out_data_r_reg[5]\, + \read_fifo.fifo_out_data_r_reg[6]_0\ => \read_fifo.fifo_out_data_r_reg[6]\, + \read_fifo.fifo_out_data_r_reg[7]_0\ => \inhbt_act_faw.inhbt_act_faw_r_reg\, + \read_fifo.head_r_reg[0]_0\(0) => \read_fifo.head_r_reg[0]\(0), + \read_fifo.tail_r_reg[0]_0\ => \read_fifo.tail_r_reg[0]\(0), + \read_fifo.tail_r_reg[0]_1\ => \read_fifo.tail_r_reg[0]_0\, + \read_fifo.tail_r_reg[1]_0\ => \read_fifo.tail_r_reg[1]\, + \read_fifo.tail_r_reg[1]_1\ => \maintenance_request.maint_zq_r_lcl_reg\, + \read_fifo.tail_r_reg[4]_0\ => col_mach0_n_16, + wr_data_en_ns => wr_data_en_ns + ); +mc_read_idle_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => col_mach0_n_16, + Q => idle, + R => \periodic_read_request.periodic_rd_r_lcl_reg_0\ + ); +mc_ref_zq_wip_r_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => mc_ref_zq_wip_ns, + Q => mc_ref_zq_wip, + R => '0' + ); +\mem_reg_0_15_12_17_i_2__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^mc_ras_n\(0), + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + O => \cmd_pipe_plus.mc_we_n_reg[2]_0\(0) + ); +\mem_reg_0_15_18_23_i_1__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^mc_ras_n\(2), + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + O => \cmd_pipe_plus.mc_we_n_reg[2]_0\(1) + ); +\mem_reg_0_15_48_53_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^mc_cas_n\(0), + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + O => \cmd_pipe_plus.mc_we_n_reg[2]_0\(2) + ); +\mem_reg_0_15_48_53_i_3__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^mc_cas_n\(2), + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + O => \cmd_pipe_plus.mc_we_n_reg[2]_0\(3) + ); +\mem_reg_0_15_72_77_i_2__2\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^cmd_pipe_plus.mc_we_n_reg[2]_1\(0), + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + O => \cmd_pipe_plus.mc_we_n_reg[2]_0\(4) + ); +\mem_reg_0_15_72_77_i_3__1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^cmd_pipe_plus.mc_we_n_reg[2]_1\(2), + I1 => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + O => \cmd_pipe_plus.mc_we_n_reg[2]_0\(5) + ); +\pointer_ram.rams[0].RAM32M0_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => \^wr_data_en\, + I1 => ram_init_done_r, + O => \cmd_pipe_plus.wr_data_en_reg_0\ + ); +rank_mach0: entity work.ddr3_mig_7series_v4_2_rank_mach + port map ( + CLK => CLK, + I120(0) => mc_cke_ns(1), + O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\, + O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\, + O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\, + O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\, + Q(0) => \wtr_timer.wtr_cnt_r\(1), + S(3) => rank_mach0_n_18, + S(2) => rank_mach0_n_19, + S(1) => rank_mach0_n_20, + S(0) => rank_mach0_n_21, + SR(0) => SR(0), + act_this_rank => \rank_cntrl[0].rank_cntrl0/act_this_rank\, + app_ref_ack => app_ref_ack, + app_ref_req => app_ref_req, + app_sr_active => app_sr_active, + app_sr_req => app_sr_req, + app_zq_ack => app_zq_ack, + app_zq_req => app_zq_req, + auto_pre_r_lcl_reg => \^periodic_rd_cntr_r_reg\, + cke_r => \arb_mux0/arb_select0/cke_r\, + clear_periodic_rd_request => clear_periodic_rd_request, + \grant_r_reg[0]\ => \grant_r_reg[0]\, + idle_r(3 downto 0) => idle_r(3 downto 0), + \inhbt_act_faw.inhbt_act_faw_r_reg\ => \inhbt_act_faw.inhbt_act_faw_r_reg\, + inhbt_act_faw_r => inhbt_act_faw_r, + insert_maint_r1 => insert_maint_r1, + \last_master_r_reg[2]\ => \last_master_r_reg[2]\, + maint_ref_zq_wip => maint_ref_zq_wip, + maint_req_r => maint_req_r, + maint_srx_r => maint_srx_r, + maint_wip_r => maint_wip_r, + maint_zq_r => maint_zq_r, + \maintenance_request.maint_rank_r_lcl_reg[0]\ => rank_mach0_n_44, + \maintenance_request.maint_req_r_lcl_reg\ => rank_mach0_n_43, + \maintenance_request.maint_sre_r_lcl_reg\ => rank_mach0_n_42, + \maintenance_request.maint_sre_r_lcl_reg_0\ => rank_mach0_n_45, + \maintenance_request.maint_srx_r_lcl_reg\ => rank_mach0_n_46, + \maintenance_request.maint_zq_r_lcl_reg\ => \maintenance_request.maint_zq_r_lcl_reg\, + \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ => bank_mach0_n_48, + \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0\ => \periodic_rd_generation.periodic_rd_timer_r_reg[2]\, + \periodic_rd_generation.read_this_rank\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank\, + \periodic_rd_generation.read_this_rank_r\ => \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r\, + \periodic_read_request.periodic_rd_grant_r\ => \rank_common0/periodic_read_request.periodic_rd_grant_r\, + \periodic_read_request.periodic_rd_r_lcl_reg\ => \^periodic_read_request.periodic_rd_r_lcl_reg\, + \periodic_read_request.periodic_rd_r_lcl_reg_0\ => \periodic_read_request.periodic_rd_r_lcl_reg_0\, + \periodic_read_request.periodic_rd_r_lcl_reg_1\ => \^periodic_rd_ack_r_lcl_reg\, + q_has_rd => \bank_cntrl[3].bank0/q_has_rd\, + q_has_rd_3 => \bank_cntrl[2].bank0/q_has_rd\, + q_has_rd_4 => \bank_cntrl[1].bank0/q_has_rd\, + q_has_rd_5 => \bank_cntrl[0].bank0/q_has_rd\, + q_has_rd_r_reg => rank_mach0_n_38, + q_has_rd_r_reg_0 => rank_mach0_n_39, + q_has_rd_r_reg_1 => rank_mach0_n_40, + q_has_rd_r_reg_2 => rank_mach0_n_41, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0\ => bank_mach0_n_102, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1\ => \^generate_maint_cmds.insert_maint_r_lcl_reg\, + \rstdiv0_sync_r1_reg_rep__13\(0) => rank_mach0_n_16, + wait_for_maint_r => \bank_cntrl[0].bank0/wait_for_maint_r\, + wait_for_maint_r_0 => \bank_cntrl[3].bank0/wait_for_maint_r\, + wait_for_maint_r_1 => \bank_cntrl[2].bank0/wait_for_maint_r\, + wait_for_maint_r_2 => \bank_cntrl[1].bank0/wait_for_maint_r\, + wait_for_maint_r_lcl_reg => rank_mach0_n_12, + wait_for_maint_r_lcl_reg_0 => rank_mach0_n_13, + wait_for_maint_r_lcl_reg_1 => rank_mach0_n_14, + wait_for_maint_r_lcl_reg_2 => rank_mach0_n_15, + wait_for_maint_r_lcl_reg_3 => bank_mach0_n_31, + wait_for_maint_r_lcl_reg_4 => bank_mach0_n_34, + wait_for_maint_r_lcl_reg_5 => bank_mach0_n_33, + wait_for_maint_r_lcl_reg_6 => bank_mach0_n_32, + \wtr_timer.wtr_cnt_r_reg[0]\ => bank_mach0_n_54, + \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(3) => rank_mach0_n_26, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(2) => rank_mach0_n_27, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(1) => rank_mach0_n_28, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]\(0) => rank_mach0_n_29, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\, + \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(3) => rank_mach0_n_30, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(2) => rank_mach0_n_31, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(1) => rank_mach0_n_32, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]\(0) => rank_mach0_n_33, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\, + \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(3) => rank_mach0_n_34, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(2) => rank_mach0_n_35, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(1) => rank_mach0_n_36, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]\(0) => rank_mach0_n_37, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\, + \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(3) => rank_mach0_n_22, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(2) => rank_mach0_n_23, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(1) => rank_mach0_n_24, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]\(0) => rank_mach0_n_25, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\, + \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0\(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\ + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3\: unisim.vcomponents.CARRY4 + port map ( + CI => '0', + CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\, + CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1\, + CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2\, + CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4\, + O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5\, + O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6\, + O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7\, + S(3) => rank_mach0_n_18, + S(2) => rank_mach0_n_19, + S(1) => rank_mach0_n_20, + S(0) => rank_mach0_n_21 + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\, + CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\, + CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1\, + CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2\, + CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4\, + O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5\, + O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6\, + O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7\, + S(3) => rank_mach0_n_30, + S(2) => rank_mach0_n_31, + S(1) => rank_mach0_n_32, + S(0) => rank_mach0_n_33 + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0\, + CO(3) => \NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED\(3), + CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1\, + CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2\, + CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"0111", + O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4\, + O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5\, + O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6\, + O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7\, + S(3) => rank_mach0_n_34, + S(2) => rank_mach0_n_35, + S(1) => rank_mach0_n_36, + S(0) => rank_mach0_n_37 + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0\, + CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\, + CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1\, + CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2\, + CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4\, + O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5\, + O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6\, + O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7\, + S(3) => rank_mach0_n_22, + S(2) => rank_mach0_n_23, + S(1) => rank_mach0_n_24, + S(0) => rank_mach0_n_25 + ); +\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1\: unisim.vcomponents.CARRY4 + port map ( + CI => \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0\, + CO(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0\, + CO(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1\, + CO(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2\, + CO(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3\, + CYINIT => '0', + DI(3 downto 0) => B"1111", + O(3) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4\, + O(2) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5\, + O(1) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6\, + O(0) => \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7\, + S(3) => rank_mach0_n_26, + S(2) => rank_mach0_n_27, + S(1) => rank_mach0_n_28, + S(0) => rank_mach0_n_29 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_ddr_phy_top is + port ( + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg : out STD_LOGIC; + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_0 : out STD_LOGIC; + \rd_ptr_reg[0]_1\ : out STD_LOGIC; + \rd_ptr_reg[1]_1\ : out STD_LOGIC; + \rd_ptr_reg[2]_1\ : out STD_LOGIC; + \rd_ptr_reg[3]_1\ : out STD_LOGIC; + phy_mc_ctl_full : out STD_LOGIC; + ref_dll_lock : out STD_LOGIC; + ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_reset_n : out STD_LOGIC; + ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_cas_n : out STD_LOGIC; + ddr3_ras_n : out STD_LOGIC; + ddr3_we_n : out STD_LOGIC; + po_cnt_dec_reg : out STD_LOGIC; + po_cnt_dec_0 : out STD_LOGIC; + new_cnt_cpt_r_reg : out STD_LOGIC; + rdlvl_stg1_start_reg : out STD_LOGIC; + samp_edge_cnt0_en_r : out STD_LOGIC; + pi_cnt_dec_reg : out STD_LOGIC; + prbs_rdlvl_done_pulse_reg : out STD_LOGIC; + phy_dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + init_calib_complete_reg_rep : out STD_LOGIC; + \init_calib_complete_reg_rep__0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__1\ : out STD_LOGIC; + \init_calib_complete_reg_rep__2\ : out STD_LOGIC; + \init_calib_complete_reg_rep__9\ : out STD_LOGIC; + init_complete_r1_timing_reg : out STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[1]\ : out STD_LOGIC_VECTOR ( 32 downto 0 ); + \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 59 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 59 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + DIC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \init_calib_complete_reg_rep__9_0\ : out STD_LOGIC; + rd_data_en : out STD_LOGIC; + \my_empty_reg[0]\ : out STD_LOGIC; + \my_empty_reg[0]_0\ : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ : out STD_LOGIC; + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 ); + D : out STD_LOGIC_VECTOR ( 127 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]\ : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + p_1_in : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + phy_mc_data_full : out STD_LOGIC; + wr_en : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + phy_mc_cmd_full : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); + ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + CLK : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + pll_locked : in STD_LOGIC; + \mcGo_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST0 : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + idle : in STD_LOGIC; + dqs_po_en_stg2_f_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dqs_count_r_reg[0]\ : in STD_LOGIC; + wl_edge_detect_valid_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + po_en_stg2_f_reg : in STD_LOGIC; + \done_cnt_reg[1]\ : in STD_LOGIC; + \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC; + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + first_fail_detect_reg : in STD_LOGIC; + pi_dqs_found_done_r1_reg : in STD_LOGIC; + mc_ref_zq_wip : in STD_LOGIC; + \four_dec_min_limit_reg[0]\ : in STD_LOGIC; + \my_empty_reg[4]_inv\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mem_out : in STD_LOGIC_VECTOR ( 47 downto 0 ); + mc_wrdata_en : in STD_LOGIC; + \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC; + complex_row0_rd_done_reg : in STD_LOGIC; + \my_full_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 143 downto 0 ); + \rd_data_edge_detect_r_reg[1]\ : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \not_strict_mode.app_rd_data[127]_i_2\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \read_fifo.tail_r_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DOC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[8]\ : in STD_LOGIC; + DOB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[73]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[75]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[79]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[81]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[87]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[91]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[93]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[97]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[99]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[103]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[105]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[109]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[111]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[115]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[121]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[123]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + mc_cas_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_ras_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + mc_odt : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_cke : in STD_LOGIC_VECTOR ( 0 to 0 ); + mc_we_n : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \my_empty_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + mc_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \phy_ctl_wd_i1_reg[17]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[18]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[19]\ : in STD_LOGIC; + mc_data_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); + \phy_ctl_wd_i1_reg[21]\ : in STD_LOGIC; + \phy_ctl_wd_i1_reg[22]\ : in STD_LOGIC; + mc_address : in STD_LOGIC_VECTOR ( 40 downto 0 ); + mc_bank : in STD_LOGIC_VECTOR ( 8 downto 0 ); + out_fifo : in STD_LOGIC_VECTOR ( 71 downto 0 ); + out_fifo_0 : in STD_LOGIC_VECTOR ( 71 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_ddr_phy_top : entity is "mig_7series_v4_2_ddr_phy_top"; +end ddr3_mig_7series_v4_2_ddr_phy_top; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_ddr_phy_top is + signal \^dic\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal calib_cmd_wren : STD_LOGIC; + signal calib_in_common : STD_LOGIC; + signal calib_in_common4_out : STD_LOGIC; + signal calib_sel : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal calib_wrdata_en : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : STD_LOGIC_VECTOR ( 73 downto 0 ); + signal \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : STD_LOGIC_VECTOR ( 73 downto 0 ); + signal dqs_po_dec_done : STD_LOGIC; + signal \gen_byte_sel_div2.calib_in_common_i_1_n_0\ : STD_LOGIC; + signal \genblk24.phy_ctl_pre_fifo_0/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_0/wr_en\ : signal is "50"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_0/wr_en\ : signal is "found"; + signal \genblk24.phy_ctl_pre_fifo_1/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_1/wr_en\ : signal is "50"; + attribute RTL_MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_1/wr_en\ : signal is "found"; + signal \genblk24.phy_ctl_pre_fifo_2/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_2/wr_en\ : signal is "50"; + attribute RTL_MAX_FANOUT of \genblk24.phy_ctl_pre_fifo_2/wr_en\ : signal is "found"; + signal idelay_inc : STD_LOGIC; + signal \^init_calib_complete_reg_rep__9\ : STD_LOGIC; + signal mux_address : STD_LOGIC_VECTOR ( 44 downto 1 ); + signal mux_cmd_wren : STD_LOGIC; + signal mux_reset_n : STD_LOGIC; + signal mux_wrdata_en : STD_LOGIC; + signal p_1_out : STD_LOGIC_VECTOR ( 24 downto 0 ); + signal \^phy_dout\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal phy_mc_go : STD_LOGIC; + signal phy_rddata_en : STD_LOGIC; + signal phy_read_calib : STD_LOGIC; + signal phy_write_calib : STD_LOGIC; + signal pi_fine_dly_dec_done : STD_LOGIC; + signal po_stg2_wrcal_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal tempmon_pi_f_dec : STD_LOGIC; + signal tempmon_pi_f_inc : STD_LOGIC; + signal tempmon_sel_pi_incdec : STD_LOGIC; + signal u_ddr_calib_top_n_10 : STD_LOGIC; + signal u_ddr_calib_top_n_131 : STD_LOGIC; + signal u_ddr_calib_top_n_23 : STD_LOGIC; + signal u_ddr_calib_top_n_252 : STD_LOGIC; + signal u_ddr_calib_top_n_254 : STD_LOGIC; + signal u_ddr_calib_top_n_256 : STD_LOGIC; + signal u_ddr_calib_top_n_27 : STD_LOGIC; + signal u_ddr_calib_top_n_3 : STD_LOGIC; + signal u_ddr_calib_top_n_33 : STD_LOGIC; + signal u_ddr_calib_top_n_37 : STD_LOGIC; + signal u_ddr_calib_top_n_41 : STD_LOGIC; + signal u_ddr_calib_top_n_45 : STD_LOGIC; + signal u_ddr_calib_top_n_476 : STD_LOGIC; + signal u_ddr_calib_top_n_49 : STD_LOGIC; + signal u_ddr_calib_top_n_53 : STD_LOGIC; + signal u_ddr_calib_top_n_65 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr_calib_top_n_65 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_65 : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of u_ddr_calib_top_n_65 : signal is "10"; + signal u_ddr_calib_top_n_66 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr_calib_top_n_66 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_66 : signal is "found"; + attribute syn_maxfan of u_ddr_calib_top_n_66 : signal is "10"; + signal u_ddr_calib_top_n_67 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr_calib_top_n_67 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr_calib_top_n_67 : signal is "found"; + attribute syn_maxfan of u_ddr_calib_top_n_67 : signal is "10"; + signal u_ddr_calib_top_n_69 : STD_LOGIC; + signal u_ddr_calib_top_n_70 : STD_LOGIC; + signal u_ddr_calib_top_n_71 : STD_LOGIC; + signal u_ddr_calib_top_n_74 : STD_LOGIC; + signal u_ddr_calib_top_n_75 : STD_LOGIC; + signal u_ddr_calib_top_n_76 : STD_LOGIC; + signal u_ddr_calib_top_n_77 : STD_LOGIC; + signal u_ddr_calib_top_n_78 : STD_LOGIC; + signal u_ddr_calib_top_n_79 : STD_LOGIC; + signal u_ddr_calib_top_n_80 : STD_LOGIC; + signal u_ddr_calib_top_n_81 : STD_LOGIC; + signal u_ddr_calib_top_n_82 : STD_LOGIC; + signal u_ddr_calib_top_n_83 : STD_LOGIC; + signal u_ddr_calib_top_n_84 : STD_LOGIC; + signal u_ddr_calib_top_n_85 : STD_LOGIC; + signal u_ddr_calib_top_n_86 : STD_LOGIC; + signal u_ddr_calib_top_n_87 : STD_LOGIC; + signal u_ddr_calib_top_n_88 : STD_LOGIC; + signal u_ddr_calib_top_n_89 : STD_LOGIC; + signal u_ddr_calib_top_n_9 : STD_LOGIC; + signal u_ddr_calib_top_n_90 : STD_LOGIC; + signal u_ddr_calib_top_n_91 : STD_LOGIC; + signal u_ddr_calib_top_n_92 : STD_LOGIC; + signal u_ddr_calib_top_n_93 : STD_LOGIC; + signal u_ddr_calib_top_n_94 : STD_LOGIC; + signal u_ddr_calib_top_n_95 : STD_LOGIC; + signal u_ddr_calib_top_n_96 : STD_LOGIC; + signal u_ddr_calib_top_n_97 : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives\ : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\ : STD_LOGIC_VECTOR ( 67 downto 8 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\ : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\ : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\ : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0\ : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\ : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\ : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst_reg0\ : STD_LOGIC; + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\ : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst_reg0\ : STD_LOGIC; + signal \u_ddr_mc_phy/pi_counter_read_val_w[0]_1\ : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal \u_ddr_mc_phy/po_counter_read_val_w[0]_0\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal u_ddr_mc_phy_wrapper_n_254 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_266 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_479 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_52 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_527 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_53 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_55 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_56 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_57 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_58 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_59 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_60 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_61 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_62 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_8 : STD_LOGIC; + signal u_ddr_mc_phy_wrapper_n_9 : STD_LOGIC; + signal \u_ddr_phy_init/prbs_rdlvl_done_pulse0\ : STD_LOGIC; + signal \u_ddr_phy_init/rdlvl_stg1_done_r1\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ : STD_LOGIC; + signal \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ : STD_LOGIC; + signal \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0\ : STD_LOGIC; + attribute SOFT_HLUTNM : string; + attribute SOFT_HLUTNM of prbs_rdlvl_done_pulse_i_1 : label is "soft_lutpair490"; + attribute SOFT_HLUTNM of \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1\ : label is "soft_lutpair490"; +begin + DIC(1 downto 0) <= \^dic\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0) <= \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0); + \init_calib_complete_reg_rep__9\ <= \^init_calib_complete_reg_rep__9\; + phy_dout(0) <= \^phy_dout\(0); +\gen_byte_sel_div2.calib_in_common_i_1\: unisim.vcomponents.LUT5 + generic map( + INIT => X"BFFF8FFF" + ) + port map ( + I0 => calib_in_common4_out, + I1 => u_ddr_calib_top_n_476, + I2 => pi_fine_dly_dec_done, + I3 => dqs_po_dec_done, + I4 => calib_in_common, + O => \gen_byte_sel_div2.calib_in_common_i_1_n_0\ + ); +prbs_rdlvl_done_pulse_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"2" + ) + port map ( + I0 => u_ddr_calib_top_n_9, + I1 => \u_ddr_phy_init/rdlvl_stg1_done_r1\, + O => \u_ddr_phy_init/prbs_rdlvl_done_pulse0\ + ); +tempmon_pi_f_en_r_i_1: unisim.vcomponents.LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => tempmon_pi_f_inc, + I1 => tempmon_pi_f_dec, + O => tempmon_sel_pi_incdec + ); +u_ddr_calib_top: entity work.ddr3_mig_7series_v4_2_ddr_calib_top + port map ( + A_rst_primitives => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives\, + CLK => CLK, + COUNTERLOADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0), + D(10 downto 3) => p_1_out(24 downto 17), + D(2 downto 0) => p_1_out(2 downto 0), + D0(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d0\(7 downto 0), + D1(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 0), + D2(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0), + D3(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 0), + D4(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0), + D5(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0), + D6(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0), + D7(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0), + D8(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0), + D9(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0), + DIC(1 downto 0) => \^dic\(1 downto 0), + E(0) => u_ddr_calib_top_n_252, + LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\, + LD0_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\, + Q(0) => phy_mc_go, + SR(0) => SR(0), + SS(0) => SS(0), + calib_cmd_wren => calib_cmd_wren, + calib_ctl_wren_reg => u_ddr_calib_top_n_70, + calib_in_common => calib_in_common, + calib_in_common4_out => calib_in_common4_out, + calib_sel(1 downto 0) => calib_sel(1 downto 0), + \calib_sel_reg[0]_0\ => u_ddr_calib_top_n_91, + \calib_sel_reg[1]_0\ => u_ddr_calib_top_n_79, + \calib_sel_reg[1]_1\ => u_ddr_calib_top_n_80, + \calib_sel_reg[1]_2\ => u_ddr_calib_top_n_81, + \calib_sel_reg[1]_3\ => u_ddr_calib_top_n_82, + \calib_sel_reg[1]_4\ => u_ddr_calib_top_n_83, + \calib_sel_reg[1]_5\ => u_ddr_calib_top_n_84, + \calib_sel_reg[1]_6\ => u_ddr_calib_top_n_85, + \calib_sel_reg[1]_7\ => u_ddr_calib_top_n_86, + \calib_sel_reg[1]_8\ => u_ddr_calib_top_n_87, + \calib_sel_reg[1]_9\ => u_ddr_calib_top_n_88, + calib_wrdata_en => calib_wrdata_en, + ck_po_stg2_f_indec_reg => u_ddr_calib_top_n_93, + \cmd_pipe_plus.mc_cke_reg[3]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0), + \cmd_pipe_plus.mc_odt_reg[0]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3 downto 0), + \cmd_pipe_plus.mc_ras_n_reg[2]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(2 downto 0), + \cmd_pipe_plus.mc_we_n_reg[1]\(32 downto 0) => \cmd_pipe_plus.mc_we_n_reg[1]\(32 downto 0), + \cmd_pipe_plus.mc_we_n_reg[2]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(2 downto 0), + \cnt_pwron_ce_r_reg[9]\(1 downto 0) => \my_empty_reg[4]_inv\(1 downto 0), + \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0), + complex_row0_rd_done_reg => complex_row0_rd_done_reg, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\(143 downto 0) => Q(143 downto 0), + \device_temp_101_reg[11]\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0), + \done_cnt_reg[1]\ => \done_cnt_reg[1]\, + \dqs_count_r_reg[0]\ => \dqs_count_r_reg[0]\, + \dqs_count_r_reg[0]_rep\(0) => \mcGo_r_reg[0]\(0), + dqs_found_done_r_reg => u_ddr_calib_top_n_476, + dqs_po_dec_done => dqs_po_dec_done, + dqs_po_en_stg2_f_reg(0) => dqs_po_en_stg2_f_reg(0), + dqs_wl_po_stg2_c_incdec_reg => u_ddr_calib_top_n_78, + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0) => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0), + first_fail_detect_reg => first_fail_detect_reg, + \four_dec_min_limit_reg[0]\ => \four_dec_min_limit_reg[0]\, + \gen_byte_sel_div2.calib_in_common_reg_0\ => u_ddr_calib_top_n_71, + \gen_byte_sel_div2.calib_in_common_reg_1\ => u_ddr_calib_top_n_74, + \gen_byte_sel_div2.calib_in_common_reg_2\ => u_ddr_calib_top_n_75, + \gen_byte_sel_div2.calib_in_common_reg_3\ => u_ddr_calib_top_n_76, + \gen_byte_sel_div2.calib_in_common_reg_4\ => u_ddr_calib_top_n_77, + \gen_byte_sel_div2.calib_in_common_reg_5\ => u_ddr_calib_top_n_90, + \gen_byte_sel_div2.calib_in_common_reg_6\ => u_ddr_calib_top_n_92, + \gen_byte_sel_div2.calib_in_common_reg_7\ => u_ddr_calib_top_n_131, + \gen_byte_sel_div2.calib_in_common_reg_8\ => \gen_byte_sel_div2.calib_in_common_i_1_n_0\, + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(3 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(6 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 4), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(2 downto 0), + \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3 downto 0), + \gen_rd[0].rd_data_rise_wl_r_reg[0]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_0\(0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_1\(0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(18), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_2\(0) => \not_strict_mode.app_rd_data_reg[117]\(16), + \gen_rd[0].rd_data_rise_wl_r_reg[0]_3\ => u_ddr_mc_phy_wrapper_n_527, + \gen_rd[0].rd_data_rise_wl_r_reg[0]_4\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_1\(0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_2\(0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(42), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_3\(0) => \not_strict_mode.app_rd_data_reg[127]\(32), + \gen_rd[1].rd_data_rise_wl_r_reg[1]_4\ => u_ddr_mc_phy_wrapper_n_254, + \gen_rd[1].rd_data_rise_wl_r_reg[1]_5\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + idelay_ce_r2_reg_0 => u_ddr_calib_top_n_89, + idelay_inc => idelay_inc, + idelay_ld_reg(0) => \my_empty_reg[8]\(0), + idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\, + \idelay_tap_cnt_r_reg[0][1][4]\ => \idelay_tap_cnt_r_reg[0][1][4]\, + ififo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0\, + ififo_rst_reg0_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst_reg0\, + in0 => u_ddr_mc_phy_wrapper_n_479, + init_calib_complete_reg_rep_0 => init_calib_complete_reg_rep, + \init_calib_complete_reg_rep__0_0\ => \init_calib_complete_reg_rep__0\, + \init_calib_complete_reg_rep__1_0\ => \init_calib_complete_reg_rep__1\, + \init_calib_complete_reg_rep__2_0\ => \init_calib_complete_reg_rep__2\, + \init_calib_complete_reg_rep__5_0\ => u_ddr_calib_top_n_65, + \init_calib_complete_reg_rep__5_1\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(7 downto 0), + \init_calib_complete_reg_rep__7_0\ => u_ddr_calib_top_n_66, + \init_calib_complete_reg_rep__8_0\ => u_ddr_calib_top_n_67, + \init_calib_complete_reg_rep__9_0\ => \^init_calib_complete_reg_rep__9\, + \init_calib_complete_reg_rep__9_1\ => \init_calib_complete_reg_rep__9_0\, + mc_address(40 downto 0) => mc_address(40 downto 0), + mc_bank(8 downto 0) => mc_bank(8 downto 0), + mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0), + mc_cke(0) => mc_cke(0), + mc_cmd(1 downto 0) => mc_cmd(1 downto 0), + mc_data_offset(0) => mc_data_offset(0), + mc_odt(0) => mc_odt(0), + mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0), + mc_ref_zq_wip => mc_ref_zq_wip, + mc_we_n(2 downto 0) => mc_we_n(2 downto 0), + mc_wrdata_en => mc_wrdata_en, + mem_out(31 downto 28) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(67 downto 64), + mem_out(27 downto 24) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(59 downto 56), + mem_out(23 downto 20) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(51 downto 48), + mem_out(19 downto 16) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(43 downto 40), + mem_out(15 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(35 downto 32), + mem_out(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(27 downto 24), + mem_out(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(19 downto 16), + mem_out(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(11 downto 8), + mux_cmd_wren => mux_cmd_wren, + mux_reset_n => mux_reset_n, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[3]\ => \genblk24.phy_ctl_pre_fifo_0/wr_en\, + \my_empty_reg[3]_0\ => \genblk24.phy_ctl_pre_fifo_1/wr_en\, + \my_empty_reg[3]_1\ => \genblk24.phy_ctl_pre_fifo_2/wr_en\, + \my_empty_reg[5]\(0) => u_ddr_calib_top_n_254, + \my_empty_reg[5]_0\(0) => u_ddr_calib_top_n_256, + new_cnt_cpt_r_reg => new_cnt_cpt_r_reg, + \not_empty_wait_cnt_reg[4]\ => \my_full_reg[0]\, + ofifo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\, + ofifo_rst_reg0_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst_reg0\, + \out\ => u_ddr_calib_top_n_10, + out_fifo(71 downto 0) => out_fifo(71 downto 0), + out_fifo_0 => u_ddr_mc_phy_wrapper_n_55, + out_fifo_1(71 downto 0) => out_fifo_0(71 downto 0), + out_fifo_2 => u_ddr_mc_phy_wrapper_n_56, + out_fifo_3 => u_ddr_mc_phy_wrapper_n_52, + out_fifo_4(44 downto 30) => mem_out(46 downto 32), + out_fifo_4(29 downto 11) => mem_out(30 downto 12), + out_fifo_4(10 downto 0) => mem_out(10 downto 0), + out_fifo_5 => u_ddr_mc_phy_wrapper_n_53, + \phy_ctl_wd_i1_reg[17]\ => \phy_ctl_wd_i1_reg[17]\, + \phy_ctl_wd_i1_reg[18]\ => \phy_ctl_wd_i1_reg[18]\, + \phy_ctl_wd_i1_reg[19]\ => \phy_ctl_wd_i1_reg[19]\, + \phy_ctl_wd_i1_reg[21]\ => \phy_ctl_wd_i1_reg[21]\, + \phy_ctl_wd_i1_reg[22]\ => \phy_ctl_wd_i1_reg[22]\, + phy_dout(39) => \^phy_dout\(0), + phy_dout(38) => mux_address(43), + phy_dout(37) => mux_address(29), + phy_dout(36) => mux_address(13), + phy_dout(35) => u_ddr_calib_top_n_23, + phy_dout(34) => mux_address(32), + phy_dout(33) => mux_address(17), + phy_dout(32) => mux_address(2), + phy_dout(31) => u_ddr_calib_top_n_27, + phy_dout(30) => mux_address(38), + phy_dout(29) => mux_address(23), + phy_dout(28) => mux_address(8), + phy_dout(27) => mux_address(44), + phy_dout(26) => mux_address(14), + phy_dout(25) => u_ddr_calib_top_n_33, + phy_dout(24) => mux_address(34), + phy_dout(23) => mux_address(19), + phy_dout(22) => mux_address(4), + phy_dout(21) => u_ddr_calib_top_n_37, + phy_dout(20) => mux_address(39), + phy_dout(19) => mux_address(24), + phy_dout(18) => mux_address(9), + phy_dout(17) => u_ddr_calib_top_n_41, + phy_dout(16) => mux_address(37), + phy_dout(15) => mux_address(22), + phy_dout(14) => mux_address(7), + phy_dout(13) => u_ddr_calib_top_n_45, + phy_dout(12) => mux_address(36), + phy_dout(11) => mux_address(21), + phy_dout(10) => mux_address(6), + phy_dout(9) => u_ddr_calib_top_n_49, + phy_dout(8) => mux_address(42), + phy_dout(7) => mux_address(27), + phy_dout(6) => mux_address(12), + phy_dout(5) => u_ddr_calib_top_n_53, + phy_dout(4) => mux_address(31), + phy_dout(3) => mux_address(16), + phy_dout(2) => mux_address(1), + phy_dout(1) => mux_address(41), + phy_dout(0) => mux_address(11), + phy_rddata_en => phy_rddata_en, + phy_read_calib => phy_read_calib, + phy_write_calib => phy_write_calib, + pi_cnt_dec_reg => pi_cnt_dec_reg, + pi_dqs_found_done_r1_reg => pi_dqs_found_done_r1_reg, + pi_dqs_found_lanes(1) => u_ddr_mc_phy_wrapper_n_8, + pi_dqs_found_lanes(0) => u_ddr_mc_phy_wrapper_n_9, + pi_en_stg2_f_reg => u_ddr_calib_top_n_95, + pi_fine_dly_dec_done => pi_fine_dly_dec_done, + \pi_rdval_cnt_reg[5]\(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[0]_1\(5 downto 0), + \pi_rst_stg1_cal_reg[0]\ => u_ddr_calib_top_n_94, + pi_stg2_f_incdec_reg => u_ddr_calib_top_n_96, + pi_stg2_load_reg => u_ddr_calib_top_n_97, + \pi_stg2_reg_l_reg[5]\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val\(5 downto 0), + po_cnt_dec_0 => po_cnt_dec_0, + po_cnt_dec_reg => po_cnt_dec_reg, + po_en_stg2_f_reg => po_en_stg2_f_reg, + \po_rdval_cnt_reg[8]\(8 downto 0) => \u_ddr_mc_phy/po_counter_read_val_w[0]_0\(8 downto 0), + \po_stg2_wrcal_cnt_reg[0]\(0) => po_stg2_wrcal_cnt(0), + prbs_rdlvl_done_pulse0 => \u_ddr_phy_init/prbs_rdlvl_done_pulse0\, + prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse_reg, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0) => \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5 downto 0), + \rd_data_edge_detect_r_reg[1]\ => \rd_data_edge_detect_r_reg[1]\, + \rd_mux_sel_r_reg[0]\ => u_ddr_calib_top_n_3, + rdlvl_stg1_done_int_reg => u_ddr_calib_top_n_9, + rdlvl_stg1_done_r1 => \u_ddr_phy_init/rdlvl_stg1_done_r1\, + rdlvl_stg1_start_reg => rdlvl_stg1_start_reg, + samp_edge_cnt0_en_r => samp_edge_cnt0_en_r, + \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\, + store_sr_req_r_reg => u_ddr_mc_phy_wrapper_n_266, + \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0), + tempmon_pi_f_dec => tempmon_pi_f_dec, + tempmon_pi_f_inc => tempmon_pi_f_inc, + tempmon_sel_pi_incdec => tempmon_sel_pi_incdec, + \wait_cnt_r_reg[0]\(0) => \wait_cnt_r_reg[0]\(0), + \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0), + wl_edge_detect_valid_r_reg(0) => wl_edge_detect_valid_r_reg(0), + \wr_en_inferred__0_i_1\ => u_ddr_mc_phy_wrapper_n_58, + \wr_en_inferred__0_i_1__0\ => u_ddr_mc_phy_wrapper_n_60, + \wr_en_inferred__0_i_1__1\ => u_ddr_mc_phy_wrapper_n_62, + \wr_ptr_timing_reg[0]\ => u_ddr_mc_phy_wrapper_n_57, + \wr_ptr_timing_reg[0]_0\ => u_ddr_mc_phy_wrapper_n_59, + \wr_ptr_timing_reg[0]_1\ => u_ddr_mc_phy_wrapper_n_61, + wrcal_done_reg => u_ddr_calib_top_n_69, + \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]\(0) => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0\, + \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0), + \write_buffer.wr_buf_out_data_reg[121]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 0), + \write_buffer.wr_buf_out_data_reg[122]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 0), + \write_buffer.wr_buf_out_data_reg[123]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(7 downto 0), + \write_buffer.wr_buf_out_data_reg[124]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0), + \write_buffer.wr_buf_out_data_reg[125]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(7 downto 0), + \write_buffer.wr_buf_out_data_reg[126]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0), + \write_buffer.wr_buf_out_data_reg[127]\(59 downto 0) => \write_buffer.wr_buf_out_data_reg[127]\(59 downto 0), + \write_buffer.wr_buf_out_data_reg[127]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(7 downto 0) + ); +u_ddr_mc_phy_wrapper: entity work.ddr3_mig_7series_v4_2_ddr_mc_phy_wrapper + port map ( + A_rst_primitives => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives\, + A_rst_primitives_reg => A_rst_primitives_reg, + A_rst_primitives_reg_0 => A_rst_primitives_reg_0, + CLK => CLK, + CLKB0 => CLKB0, + CLKB0_4 => CLKB0_4, + COUNTERLOADVAL(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val\(5 downto 0), + D(127 downto 0) => D(127 downto 0), + D0(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d0\(7 downto 0), + D1(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d1\(7 downto 0), + D2(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2\(7 downto 0), + D3(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3\(7 downto 0), + D4(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4\(7 downto 0), + D5(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5\(7 downto 0), + D6(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6\(7 downto 0), + D7(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7\(7 downto 0), + D8(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8\(7 downto 0), + D9(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9\(7 downto 0), + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => \^dic\(1 downto 0), + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + E(0) => u_ddr_calib_top_n_252, + LD0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0\, + LD0_0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0\, + Q(73 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0), + RST0 => RST0, + SR(0) => SR(0), + UNCONN_IN => \genblk24.phy_ctl_pre_fifo_0/wr_en\, + UNCONN_IN_0 => \genblk24.phy_ctl_pre_fifo_1/wr_en\, + UNCONN_IN_1 => \genblk24.phy_ctl_pre_fifo_2/wr_en\, + calib_cmd_wren => calib_cmd_wren, + calib_sel(1 downto 0) => calib_sel(1 downto 0), + calib_wrdata_en => calib_wrdata_en, + ddr3_addr(14 downto 0) => ddr3_addr(14 downto 0), + ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0), + ddr3_cas_n => ddr3_cas_n, + ddr3_cke(0) => ddr3_cke(0), + ddr3_dm(1 downto 0) => ddr3_dm(1 downto 0), + ddr3_dq(15 downto 0) => ddr3_dq(15 downto 0), + ddr3_dqs_n(1 downto 0) => ddr3_dqs_n(1 downto 0), + ddr3_dqs_p(1 downto 0) => ddr3_dqs_p(1 downto 0), + ddr3_odt(0) => ddr3_odt(0), + ddr3_ras_n => ddr3_ras_n, + ddr3_reset_n => ddr3_reset_n, + ddr3_we_n => ddr3_we_n, + ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0), + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(73 downto 0) => \^dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(1 downto 0), + freq_refclk => freq_refclk, + \gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd[1].mux_rd_rise0_r_reg[1]\ => u_ddr_calib_top_n_3, + \gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]\(0) => po_stg2_wrcal_cnt(0), + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0\, + \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\ => \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0\, + idelay_inc => idelay_inc, + idelay_ld_rst => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst\, + idle => idle, + ififo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0\, + ififo_rst_reg0_1 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst_reg0\, + in0 => u_ddr_mc_phy_wrapper_n_479, + init_complete_r1_timing_reg => init_complete_r1_timing_reg, + \input_[9].iserdes_dq_.iserdesdq\ => u_ddr_calib_top_n_82, + \input_[9].iserdes_dq_.iserdesdq_0\ => u_ddr_calib_top_n_89, + \mcGo_r_reg[0]\(0) => \mcGo_r_reg[0]\(0), + \mcGo_r_reg[15]\(0) => phy_mc_go, + mc_address(5 downto 4) => mc_address(40 downto 39), + mc_address(3) => mc_address(37), + mc_address(2 downto 1) => mc_address(14 downto 13), + mc_address(0) => mc_address(11), + mc_cas_n(0) => mc_cas_n(1), + mc_wrdata_en => mc_wrdata_en, + mem_out(2) => mem_out(47), + mem_out(1) => mem_out(31), + mem_out(0) => mem_out(11), + mem_refclk => mem_refclk, + mux_cmd_wren => mux_cmd_wren, + mux_reset_n => mux_reset_n, + mux_wrdata_en => mux_wrdata_en, + \my_empty_reg[0]\ => \my_empty_reg[0]\, + \my_empty_reg[0]_0\ => \my_empty_reg[0]_0\, + \my_empty_reg[1]\ => u_ddr_mc_phy_wrapper_n_52, + \my_empty_reg[1]_0\ => u_ddr_mc_phy_wrapper_n_53, + \my_empty_reg[1]_1\ => u_ddr_mc_phy_wrapper_n_55, + \my_empty_reg[1]_2\ => u_ddr_mc_phy_wrapper_n_56, + \my_empty_reg[3]\ => u_ddr_mc_phy_wrapper_n_58, + \my_empty_reg[3]_0\ => u_ddr_mc_phy_wrapper_n_60, + \my_empty_reg[3]_1\ => u_ddr_mc_phy_wrapper_n_62, + \my_empty_reg[4]_inv\(0) => \my_empty_reg[4]_inv\(1), + \my_empty_reg[4]_rep__0\ => u_ddr_mc_phy_wrapper_n_527, + \my_empty_reg[4]_rep__1\ => u_ddr_mc_phy_wrapper_n_254, + \my_empty_reg[5]\ => u_ddr_mc_phy_wrapper_n_57, + \my_empty_reg[5]_0\ => u_ddr_mc_phy_wrapper_n_59, + \my_empty_reg[5]_1\ => u_ddr_mc_phy_wrapper_n_61, + \my_empty_reg[7]\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1\(7 downto 0), + \my_empty_reg[7]_0\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2\(7 downto 0), + \my_empty_reg[7]_1\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4\(7 downto 0), + \my_empty_reg[7]_10\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4\(3 downto 0), + \my_empty_reg[7]_11\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5\(3 downto 0), + \my_empty_reg[7]_12\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6\(3 downto 0), + \my_empty_reg[7]_13\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7\(3 downto 0), + \my_empty_reg[7]_14\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8\(3 downto 0), + \my_empty_reg[7]_2\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5\(7 downto 0), + \my_empty_reg[7]_3\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6\(7 downto 0), + \my_empty_reg[7]_4\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7\(7 downto 0), + \my_empty_reg[7]_5\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8\(7 downto 0), + \my_empty_reg[7]_6\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9\(7 downto 0), + \my_empty_reg[7]_7\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1\(3 downto 0), + \my_empty_reg[7]_8\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2\(3 downto 0), + \my_empty_reg[7]_9\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3\(3 downto 0), + \my_empty_reg[8]\(0) => \my_empty_reg[8]\(0), + \my_full_reg[0]\ => \my_full_reg[0]\, + \not_strict_mode.app_rd_data[127]_i_2\(0) => \not_strict_mode.app_rd_data[127]_i_2\(0), + \not_strict_mode.app_rd_data_reg[101]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[103]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[105]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[109]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[111]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[115]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[121]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[123]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[13]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[15]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[19]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[21]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[25]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[27]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[31]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[33]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[37]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[39]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[43]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[45]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[49]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[51]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[55]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[57]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[61]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[63]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[67]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[69]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[73]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[75]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[79]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[7]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[81]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[85]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[87]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[8]\ => \not_strict_mode.app_rd_data_reg[8]\, + \not_strict_mode.app_rd_data_reg[91]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[93]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[97]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[99]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[9]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]\(1 downto 0), + ofifo_rst_reg0 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0\, + ofifo_rst_reg0_2 => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst_reg0\, + \out\(1 downto 0) => \out\(1 downto 0), + out_fifo => u_ddr_calib_top_n_65, + p_1_in => p_1_in, + \phy_ctl_wd_i1_reg[24]_0\(10 downto 3) => p_1_out(24 downto 17), + \phy_ctl_wd_i1_reg[24]_0\(2 downto 0) => p_1_out(2 downto 0), + phy_ctl_wr_i1_reg_0 => u_ddr_calib_top_n_70, + phy_dout(39) => \^phy_dout\(0), + phy_dout(38) => mux_address(43), + phy_dout(37) => mux_address(29), + phy_dout(36) => mux_address(13), + phy_dout(35) => u_ddr_calib_top_n_23, + phy_dout(34) => mux_address(32), + phy_dout(33) => mux_address(17), + phy_dout(32) => mux_address(2), + phy_dout(31) => u_ddr_calib_top_n_27, + phy_dout(30) => mux_address(38), + phy_dout(29) => mux_address(23), + phy_dout(28) => mux_address(8), + phy_dout(27) => mux_address(44), + phy_dout(26) => mux_address(14), + phy_dout(25) => u_ddr_calib_top_n_33, + phy_dout(24) => mux_address(34), + phy_dout(23) => mux_address(19), + phy_dout(22) => mux_address(4), + phy_dout(21) => u_ddr_calib_top_n_37, + phy_dout(20) => mux_address(39), + phy_dout(19) => mux_address(24), + phy_dout(18) => mux_address(9), + phy_dout(17) => u_ddr_calib_top_n_41, + phy_dout(16) => mux_address(37), + phy_dout(15) => mux_address(22), + phy_dout(14) => mux_address(7), + phy_dout(13) => u_ddr_calib_top_n_45, + phy_dout(12) => mux_address(36), + phy_dout(11) => mux_address(21), + phy_dout(10) => mux_address(6), + phy_dout(9) => u_ddr_calib_top_n_49, + phy_dout(8) => mux_address(42), + phy_dout(7) => mux_address(27), + phy_dout(6) => mux_address(12), + phy_dout(5) => u_ddr_calib_top_n_53, + phy_dout(4) => mux_address(31), + phy_dout(3) => mux_address(16), + phy_dout(2) => mux_address(1), + phy_dout(1) => mux_address(41), + phy_dout(0) => mux_address(11), + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_data_full => phy_mc_data_full, + phy_rddata_en => phy_rddata_en, + phy_read_calib => phy_read_calib, + phy_write_calib => phy_write_calib, + \pi_counter_read_val_reg[5]\ => u_ddr_mc_phy_wrapper_n_266, + \pi_counter_read_val_reg[5]_0\(5 downto 0) => \u_ddr_mc_phy/pi_counter_read_val_w[0]_1\(5 downto 0), + pi_dqs_found_lanes(1) => u_ddr_mc_phy_wrapper_n_8, + pi_dqs_found_lanes(0) => u_ddr_mc_phy_wrapper_n_9, + \pi_dqs_found_lanes_r1_reg[2]\ => u_ddr_calib_top_n_88, + \pi_dqs_found_lanes_r1_reg[2]_0\ => u_ddr_calib_top_n_81, + \pi_dqs_found_lanes_r1_reg[2]_1\ => u_ddr_calib_top_n_86, + \pi_dqs_found_lanes_r1_reg[2]_2\ => u_ddr_calib_top_n_87, + \pi_dqs_found_lanes_r1_reg[2]_3\ => u_ddr_calib_top_n_85, + \pi_dqs_found_lanes_r1_reg[3]\ => u_ddr_calib_top_n_97, + \pi_dqs_found_lanes_r1_reg[3]_0\ => u_ddr_calib_top_n_79, + \pi_dqs_found_lanes_r1_reg[3]_1\ => u_ddr_calib_top_n_95, + \pi_dqs_found_lanes_r1_reg[3]_2\ => u_ddr_calib_top_n_96, + \pi_dqs_found_lanes_r1_reg[3]_3\ => u_ddr_calib_top_n_94, + \pi_dqs_found_lanes_r1_reg[3]_4\(5 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val\(5 downto 0), + pll_locked => pll_locked, + \po_counter_read_val_reg[8]\(8 downto 0) => \u_ddr_mc_phy/po_counter_read_val_w[0]_0\(8 downto 0), + \po_counter_read_val_reg[8]_0\ => u_ddr_calib_top_n_77, + \po_counter_read_val_reg[8]_1\ => u_ddr_calib_top_n_131, + \po_counter_read_val_reg[8]_10\ => u_ddr_calib_top_n_75, + \po_counter_read_val_reg[8]_11\ => u_ddr_calib_top_n_71, + \po_counter_read_val_reg[8]_12\ => u_ddr_calib_top_n_76, + \po_counter_read_val_reg[8]_13\ => u_ddr_calib_top_n_74, + \po_counter_read_val_reg[8]_2\ => u_ddr_calib_top_n_90, + \po_counter_read_val_reg[8]_3\ => u_ddr_calib_top_n_92, + \po_counter_read_val_reg[8]_4\ => u_ddr_calib_top_n_80, + \po_counter_read_val_reg[8]_5\ => u_ddr_calib_top_n_83, + \po_counter_read_val_reg[8]_6\ => u_ddr_calib_top_n_84, + \po_counter_read_val_reg[8]_7\ => u_ddr_calib_top_n_78, + \po_counter_read_val_reg[8]_8\ => u_ddr_calib_top_n_91, + \po_counter_read_val_reg[8]_9\ => u_ddr_calib_top_n_93, + rd_data_en => rd_data_en, + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\, + \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\, + \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\, + \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\, + \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\, + \rd_ptr_reg[3]_10\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7\(3 downto 0), + \rd_ptr_reg[3]_11\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8\(3 downto 0), + \rd_ptr_reg[3]_12\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9\(2 downto 0), + \rd_ptr_reg[3]_2\(31 downto 28) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(67 downto 64), + \rd_ptr_reg[3]_2\(27 downto 24) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(59 downto 56), + \rd_ptr_reg[3]_2\(23 downto 20) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(51 downto 48), + \rd_ptr_reg[3]_2\(19 downto 16) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(43 downto 40), + \rd_ptr_reg[3]_2\(15 downto 12) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(35 downto 32), + \rd_ptr_reg[3]_2\(11 downto 8) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(27 downto 24), + \rd_ptr_reg[3]_2\(7 downto 4) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(19 downto 16), + \rd_ptr_reg[3]_2\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out\(11 downto 8), + \rd_ptr_reg[3]_3\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0\(3 downto 0), + \rd_ptr_reg[3]_4\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1\(3 downto 0), + \rd_ptr_reg[3]_5\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2\(2 downto 0), + \rd_ptr_reg[3]_6\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3\(3 downto 0), + \rd_ptr_reg[3]_7\(3 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4\(3 downto 0), + \rd_ptr_reg[3]_8\(7 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5\(7 downto 0), + \rd_ptr_reg[3]_9\(6 downto 3) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(7 downto 4), + \rd_ptr_reg[3]_9\(2 downto 0) => \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6\(2 downto 0), + \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + \read_fifo.tail_r_reg\(0) => \read_fifo.tail_r_reg\(0), + \read_fifo.tail_r_reg_0_sp_1\ => u_ddr_calib_top_n_10, + ref_dll_lock => ref_dll_lock, + sync_pulse => sync_pulse, + wr_en => wr_en, + wr_en_2 => wr_en_2, + wr_en_3 => wr_en_3, + \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\, + \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\, + \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\, + \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0), + \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0), + \wr_ptr_timing_reg[0]\ => \^init_calib_complete_reg_rep__9\, + \wr_ptr_timing_reg[0]_0\ => u_ddr_calib_top_n_67, + \wr_ptr_timing_reg[0]_1\ => u_ddr_calib_top_n_66, + \wr_ptr_timing_reg[0]_2\(0) => u_ddr_calib_top_n_254, + \wr_ptr_timing_reg[0]_3\(0) => u_ddr_calib_top_n_256 + ); +\wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1\: unisim.vcomponents.LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => u_ddr_calib_top_n_9, + I1 => u_ddr_calib_top_n_69, + O => \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_mem_intfc is + port ( + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + \generate_maint_cmds.insert_maint_r_lcl_reg\ : out STD_LOGIC; + periodic_rd_ack_r : out STD_LOGIC; + accept_ns : out STD_LOGIC; + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg : out STD_LOGIC; + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_0 : out STD_LOGIC; + \rd_ptr_reg[0]_1\ : out STD_LOGIC; + \rd_ptr_reg[1]_1\ : out STD_LOGIC; + \rd_ptr_reg[2]_1\ : out STD_LOGIC; + \rd_ptr_reg[3]_1\ : out STD_LOGIC; + ref_dll_lock : out STD_LOGIC; + ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_reset_n : out STD_LOGIC; + ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_cas_n : out STD_LOGIC; + ddr3_ras_n : out STD_LOGIC; + ddr3_we_n : out STD_LOGIC; + periodic_rd_r : out STD_LOGIC; + app_sr_active : out STD_LOGIC; + periodic_rd_cntr_r : out STD_LOGIC; + po_cnt_dec_reg : out STD_LOGIC; + po_cnt_dec_0 : out STD_LOGIC; + new_cnt_cpt_r_reg : out STD_LOGIC; + rdlvl_stg1_start_reg : out STD_LOGIC; + samp_edge_cnt0_en_r : out STD_LOGIC; + pi_cnt_dec_reg : out STD_LOGIC; + prbs_rdlvl_done_pulse_reg : out STD_LOGIC; + phy_dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + \init_calib_complete_reg_rep__0\ : out STD_LOGIC; + \init_calib_complete_reg_rep__1\ : out STD_LOGIC; + \init_calib_complete_reg_rep__2\ : out STD_LOGIC; + idle_r_lcl_reg : out STD_LOGIC; + idle_r_lcl_reg_0 : out STD_LOGIC; + idle_r_lcl_reg_1 : out STD_LOGIC; + idle_r_lcl_reg_2 : out STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[6]\ : out STD_LOGIC; + \cmd_pipe_plus.mc_we_n_reg[2]\ : out STD_LOGIC_VECTOR ( 38 downto 0 ); + \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 59 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 59 downto 0 ); + \cmd_pipe_plus.wr_data_en_reg\ : out STD_LOGIC; + wr_data_en : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + DIC : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DIB : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \req_row_r_lcl_reg[14]\ : out STD_LOGIC_VECTOR ( 14 downto 0 ); + req_bank_r : out STD_LOGIC_VECTOR ( 11 downto 0 ); + D : out STD_LOGIC_VECTOR ( 127 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + \not_strict_mode.bypass__0\ : out STD_LOGIC; + \not_strict_mode.app_rd_data_end_ns\ : out STD_LOGIC; + \read_fifo.fifo_out_data_r_reg[7]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]\ : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + p_1_in : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + wr_data_addr : out STD_LOGIC_VECTOR ( 3 downto 0 ); + wr_en : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); + ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + CLK : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + req_wr_r_lcl0 : in STD_LOGIC; + rb_hit_busy_r_reg : in STD_LOGIC; + rb_hit_busy_r_reg_0 : in STD_LOGIC; + rb_hit_busy_r_reg_1 : in STD_LOGIC; + rb_hit_busy_r_reg_2 : in STD_LOGIC; + was_wr0 : in STD_LOGIC; + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + pll_locked : in STD_LOGIC; + \read_fifo.head_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST0 : in STD_LOGIC; + \maintenance_request.maint_zq_r_lcl_reg\ : in STD_LOGIC; + \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC; + rnk_config_valid_r_lcl_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); + dqs_po_en_stg2_f_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dqs_count_r_reg[0]\ : in STD_LOGIC; + wl_edge_detect_valid_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \done_cnt_reg[1]\ : in STD_LOGIC; + \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC; + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + first_fail_detect_reg : in STD_LOGIC; + pi_dqs_found_done_r1_reg : in STD_LOGIC; + S : in STD_LOGIC_VECTOR ( 3 downto 0 ); + row_hit_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + app_zq_req : in STD_LOGIC; + app_sr_req : in STD_LOGIC; + \last_master_r_reg[2]\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC; + was_priority_reg : in STD_LOGIC; + app_en_r2 : in STD_LOGIC; + ram_init_done_r : in STD_LOGIC; + \inhbt_act_faw.inhbt_act_faw_r_reg\ : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 47 downto 0 ); + \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC; + complex_row0_rd_done_reg : in STD_LOGIC; + \rtp_timer_r_reg[0]\ : in STD_LOGIC; + Q : in STD_LOGIC_VECTOR ( 143 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + rd_wr_r_lcl_reg : in STD_LOGIC; + row : in STD_LOGIC_VECTOR ( 14 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + DOC : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOB : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DOA : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[31]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[33]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[35]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[37]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[39]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[41]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[43]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[45]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[49]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[51]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[53]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[55]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[57]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[59]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[61]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[63]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[65]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[67]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[69]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[71]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[73]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[75]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[77]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[79]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[81]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[83]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[85]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[87]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[89]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[91]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[93]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[95]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[97]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[99]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[101]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[103]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[105]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[107]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[109]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[111]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[113]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[115]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[119]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[121]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[123]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[125]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); + \not_strict_mode.app_rd_data_end_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \not_strict_mode.app_rd_data_end_reg_0\ : in STD_LOGIC; + ram_init_addr : in STD_LOGIC_VECTOR ( 3 downto 0 ); + \req_data_buf_addr_r_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 ); + \req_bank_r_lcl_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); + \req_col_r_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC; + \my_empty_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \device_temp_101_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); + out_fifo : in STD_LOGIC_VECTOR ( 71 downto 0 ); + out_fifo_0 : in STD_LOGIC_VECTOR ( 71 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_mem_intfc : entity is "mig_7series_v4_2_mem_intfc"; +end ddr3_mig_7series_v4_2_mem_intfc; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_mem_intfc is + signal \col_mach0/p_0_in\ : STD_LOGIC; + signal \col_mach0/read_fifo.tail_r_reg\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal ddr_phy_top0_n_351 : STD_LOGIC; + signal ddr_phy_top0_n_353 : STD_LOGIC; + signal ddr_phy_top0_n_354 : STD_LOGIC; + signal ddr_phy_top0_n_355 : STD_LOGIC; + signal ddr_phy_top0_n_356 : STD_LOGIC; + signal ddr_phy_top0_n_357 : STD_LOGIC; + signal ddr_phy_top0_n_358 : STD_LOGIC; + signal ddr_phy_top0_n_359 : STD_LOGIC; + signal ddr_phy_top0_n_360 : STD_LOGIC; + signal ddr_phy_top0_n_361 : STD_LOGIC; + signal ddr_phy_top0_n_54 : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of ddr_phy_top0_n_54 : signal is "50"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of ddr_phy_top0_n_54 : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of ddr_phy_top0_n_54 : signal is "10"; + signal ddr_phy_top0_n_58 : STD_LOGIC; + attribute MAX_FANOUT of ddr_phy_top0_n_58 : signal is "50"; + attribute RTL_MAX_FANOUT of ddr_phy_top0_n_58 : signal is "found"; + attribute syn_maxfan of ddr_phy_top0_n_58 : signal is "10"; + signal ddr_phy_top0_n_59 : STD_LOGIC; + signal idle : STD_LOGIC; + signal mc0_n_128 : STD_LOGIC; + signal mc0_n_129 : STD_LOGIC; + signal mc0_n_130 : STD_LOGIC; + signal mc0_n_131 : STD_LOGIC; + signal mc0_n_132 : STD_LOGIC; + signal mc0_n_133 : STD_LOGIC; + signal mc_address : STD_LOGIC_VECTOR ( 44 downto 0 ); + signal mc_bank : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal mc_cas_n : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_cke : STD_LOGIC_VECTOR ( 3 to 3 ); + signal mc_cmd : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal mc_odt : STD_LOGIC_VECTOR ( 0 to 0 ); + signal mc_ras_n : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_we_n : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal mc_wrdata_en : STD_LOGIC; + signal \^not_strict_mode.bypass__0\ : STD_LOGIC; + signal phy_mc_cmd_full : STD_LOGIC; + signal phy_mc_ctl_full : STD_LOGIC; + signal phy_mc_data_full : STD_LOGIC; + signal rd_data_en : STD_LOGIC; + signal tempmon_sample_en : STD_LOGIC; +begin + \not_strict_mode.bypass__0\ <= \^not_strict_mode.bypass__0\; +ddr_phy_top0: entity work.ddr3_mig_7series_v4_2_ddr_phy_top + port map ( + A_rst_primitives_reg => A_rst_primitives_reg, + A_rst_primitives_reg_0 => A_rst_primitives_reg_0, + CLK => CLK, + CLKB0 => CLKB0, + CLKB0_4 => CLKB0_4, + D(127 downto 0) => D(127 downto 0), + DIA(1 downto 0) => DIA(1 downto 0), + DIB(1 downto 0) => DIB(1 downto 0), + DIC(1 downto 0) => DIC(1 downto 0), + DOA(1 downto 0) => DOA(1 downto 0), + DOB(1 downto 0) => DOB(1 downto 0), + DOC(1 downto 0) => DOC(1 downto 0), + Q(143 downto 0) => Q(143 downto 0), + RST0 => RST0, + SR(0) => SR(0), + SS(0) => SS(0), + \cmd_pipe_plus.mc_we_n_reg[1]\(32) => \cmd_pipe_plus.mc_we_n_reg[2]\(37), + \cmd_pipe_plus.mc_we_n_reg[1]\(31 downto 23) => \cmd_pipe_plus.mc_we_n_reg[2]\(35 downto 27), + \cmd_pipe_plus.mc_we_n_reg[1]\(22) => \cmd_pipe_plus.mc_we_n_reg[2]\(25), + \cmd_pipe_plus.mc_we_n_reg[1]\(21 downto 9) => \cmd_pipe_plus.mc_we_n_reg[2]\(23 downto 11), + \cmd_pipe_plus.mc_we_n_reg[1]\(8) => \cmd_pipe_plus.mc_we_n_reg[2]\(9), + \cmd_pipe_plus.mc_we_n_reg[1]\(7 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(7 downto 0), + \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0), + complex_row0_rd_done_reg => complex_row0_rd_done_reg, + ddr3_addr(14 downto 0) => ddr3_addr(14 downto 0), + ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0), + ddr3_cas_n => ddr3_cas_n, + ddr3_cke(0) => ddr3_cke(0), + ddr3_dm(1 downto 0) => ddr3_dm(1 downto 0), + ddr3_dq(15 downto 0) => ddr3_dq(15 downto 0), + ddr3_dqs_n(1 downto 0) => ddr3_dqs_n(1 downto 0), + ddr3_dqs_p(1 downto 0) => ddr3_dqs_p(1 downto 0), + ddr3_odt(0) => ddr3_odt(0), + ddr3_ras_n => ddr3_ras_n, + ddr3_reset_n => ddr3_reset_n, + ddr3_we_n => ddr3_we_n, + ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0), + \device_temp_101_reg[11]\(11 downto 0) => \device_temp_101_reg[11]\(11 downto 0), + \done_cnt_reg[1]\ => \done_cnt_reg[1]\, + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(1 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(1 downto 0), + \dqs_count_r_reg[0]\ => \dqs_count_r_reg[0]\, + dqs_po_en_stg2_f_reg(0) => dqs_po_en_stg2_f_reg(0), + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0) => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0), + first_fail_detect_reg => first_fail_detect_reg, + \four_dec_min_limit_reg[0]\ => \maintenance_request.maint_zq_r_lcl_reg\, + freq_refclk => freq_refclk, + \idelay_tap_cnt_r_reg[0][1][4]\ => \idelay_tap_cnt_r_reg[0][1][4]\, + idle => idle, + init_calib_complete_reg_rep => ddr_phy_top0_n_54, + \init_calib_complete_reg_rep__0\ => \init_calib_complete_reg_rep__0\, + \init_calib_complete_reg_rep__1\ => \init_calib_complete_reg_rep__1\, + \init_calib_complete_reg_rep__2\ => \init_calib_complete_reg_rep__2\, + \init_calib_complete_reg_rep__9\ => ddr_phy_top0_n_58, + \init_calib_complete_reg_rep__9_0\ => ddr_phy_top0_n_351, + init_complete_r1_timing_reg => ddr_phy_top0_n_59, + \mcGo_r_reg[0]\(0) => \read_fifo.head_r_reg[0]\(0), + mc_address(40 downto 26) => mc_address(44 downto 30), + mc_address(25 downto 0) => mc_address(25 downto 0), + mc_bank(8 downto 0) => mc_bank(8 downto 0), + mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0), + mc_cke(0) => mc_cke(3), + mc_cmd(1 downto 0) => mc_cmd(1 downto 0), + mc_data_offset(0) => mc0_n_128, + mc_odt(0) => mc_odt(0), + mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0), + mc_ref_zq_wip => tempmon_sample_en, + mc_we_n(2 downto 0) => mc_we_n(2 downto 0), + mc_wrdata_en => mc_wrdata_en, + mem_out(47 downto 0) => mem_out(47 downto 0), + mem_refclk => mem_refclk, + \my_empty_reg[0]\ => ddr_phy_top0_n_353, + \my_empty_reg[0]_0\ => ddr_phy_top0_n_354, + \my_empty_reg[4]_inv\(1 downto 0) => rnk_config_valid_r_lcl_reg(1 downto 0), + \my_empty_reg[8]\(0) => \my_empty_reg[8]\(0), + \my_full_reg[0]\ => \rtp_timer_r_reg[0]\, + new_cnt_cpt_r_reg => new_cnt_cpt_r_reg, + \not_strict_mode.app_rd_data[127]_i_2\(0) => \col_mach0/p_0_in\, + \not_strict_mode.app_rd_data_reg[101]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[101]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[103]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[103]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[105]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[105]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[107]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[107]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[109]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[109]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[111]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[111]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[113]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[113]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[115]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[115]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[117]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[119]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[119]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[11]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[11]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[121]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[121]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[123]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[123]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[125]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[125]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0) => \not_strict_mode.app_rd_data_reg[127]_0\(1 downto 0), + \not_strict_mode.app_rd_data_reg[13]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[13]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[15]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[15]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[17]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[17]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[19]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[19]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[21]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[21]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[23]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[23]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[25]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[25]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[27]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[27]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[29]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[29]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[31]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[31]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[33]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[33]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[35]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[35]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[37]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[37]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[39]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[39]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[41]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[41]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[43]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[43]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[45]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[45]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[47]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[47]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[49]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[49]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[51]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[51]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[53]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[53]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[55]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[55]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[57]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[57]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[59]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[59]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[61]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[61]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[63]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[63]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[65]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[65]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[67]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[67]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[69]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[69]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[71]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[71]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[73]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[73]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[75]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[75]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[77]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[77]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[79]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[79]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[7]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[7]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[81]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[81]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[83]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[83]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[85]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[85]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[87]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[87]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[89]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[89]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[8]\ => \^not_strict_mode.bypass__0\, + \not_strict_mode.app_rd_data_reg[91]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[91]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[93]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[93]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[95]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[95]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[97]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[97]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[99]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[99]\(1 downto 0), + \not_strict_mode.app_rd_data_reg[9]\(1 downto 0) => \not_strict_mode.app_rd_data_reg[9]\(1 downto 0), + \out\(1 downto 0) => \out\(1 downto 0), + out_fifo(71 downto 0) => out_fifo(71 downto 0), + out_fifo_0(71 downto 0) => out_fifo_0(71 downto 0), + p_1_in => p_1_in, + \phy_ctl_wd_i1_reg[17]\ => mc0_n_133, + \phy_ctl_wd_i1_reg[18]\ => mc0_n_132, + \phy_ctl_wd_i1_reg[19]\ => mc0_n_131, + \phy_ctl_wd_i1_reg[21]\ => mc0_n_130, + \phy_ctl_wd_i1_reg[22]\ => mc0_n_129, + phy_dout(0) => phy_dout(0), + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_data_full => phy_mc_data_full, + pi_cnt_dec_reg => pi_cnt_dec_reg, + pi_dqs_found_done_r1_reg => pi_dqs_found_done_r1_reg, + pll_locked => pll_locked, + po_cnt_dec_0 => po_cnt_dec_0, + po_cnt_dec_reg => po_cnt_dec_reg, + po_en_stg2_f_reg => \zq_cntrl.zq_request_logic.zq_request_r_reg\, + prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse_reg, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]\ => ddr_phy_top0_n_355, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(5) => ddr_phy_top0_n_356, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(4) => ddr_phy_top0_n_357, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(3) => ddr_phy_top0_n_358, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(2) => ddr_phy_top0_n_359, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(1) => ddr_phy_top0_n_360, + \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]\(0) => ddr_phy_top0_n_361, + \rd_data_edge_detect_r_reg[1]\ => \inhbt_act_faw.inhbt_act_faw_r_reg\, + rd_data_en => rd_data_en, + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\, + \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\, + \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\, + \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\, + \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\, + \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + rdlvl_stg1_start_reg => rdlvl_stg1_start_reg, + \read_fifo.tail_r_reg\(0) => \col_mach0/read_fifo.tail_r_reg\(0), + ref_dll_lock => ref_dll_lock, + samp_edge_cnt0_en_r => samp_edge_cnt0_en_r, + \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\, + sync_pulse => sync_pulse, + \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0), + \wait_cnt_r_reg[0]\(0) => \wait_cnt_r_reg[0]\(0), + \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0), + wl_edge_detect_valid_r_reg(0) => wl_edge_detect_valid_r_reg(0), + wr_en => wr_en, + wr_en_2 => wr_en_2, + wr_en_3 => wr_en_3, + \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\, + \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\, + \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\, + \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0), + \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0), + \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(59 downto 0), + \write_buffer.wr_buf_out_data_reg[127]\(59 downto 0) => \write_buffer.wr_buf_out_data_reg[127]\(59 downto 0) + ); +mc0: entity work.ddr3_mig_7series_v4_2_mc + port map ( + CLK => CLK, + Q(7) => \read_fifo.fifo_out_data_r_reg[7]\(6), + Q(6) => \col_mach0/p_0_in\, + Q(5 downto 0) => \read_fifo.fifo_out_data_r_reg[7]\(5 downto 0), + S(3 downto 0) => S(3 downto 0), + SR(0) => SR(0), + accept_ns => accept_ns, + app_en_r2 => app_en_r2, + app_ref_ack => app_ref_ack, + app_ref_req => app_ref_req, + app_sr_active => app_sr_active, + app_sr_req => app_sr_req, + app_zq_ack => app_zq_ack, + app_zq_req => app_zq_req, + \cmd_pipe_plus.mc_address_reg[44]_0\(40 downto 26) => mc_address(44 downto 30), + \cmd_pipe_plus.mc_address_reg[44]_0\(25 downto 0) => mc_address(25 downto 0), + \cmd_pipe_plus.mc_bank_reg[8]_0\(8 downto 0) => mc_bank(8 downto 0), + \cmd_pipe_plus.mc_data_offset_reg[0]_0\ => mc0_n_133, + \cmd_pipe_plus.mc_data_offset_reg[0]_1\ => ddr_phy_top0_n_355, + \cmd_pipe_plus.mc_data_offset_reg[1]_0\ => mc0_n_132, + \cmd_pipe_plus.mc_data_offset_reg[2]_0\ => mc0_n_131, + \cmd_pipe_plus.mc_data_offset_reg[3]_0\(0) => mc0_n_128, + \cmd_pipe_plus.mc_data_offset_reg[4]_0\ => mc0_n_130, + \cmd_pipe_plus.mc_data_offset_reg[5]_0\ => mc0_n_129, + \cmd_pipe_plus.mc_data_offset_reg[5]_1\(5) => ddr_phy_top0_n_356, + \cmd_pipe_plus.mc_data_offset_reg[5]_1\(4) => ddr_phy_top0_n_357, + \cmd_pipe_plus.mc_data_offset_reg[5]_1\(3) => ddr_phy_top0_n_358, + \cmd_pipe_plus.mc_data_offset_reg[5]_1\(2) => ddr_phy_top0_n_359, + \cmd_pipe_plus.mc_data_offset_reg[5]_1\(1) => ddr_phy_top0_n_360, + \cmd_pipe_plus.mc_data_offset_reg[5]_1\(0) => ddr_phy_top0_n_361, + \cmd_pipe_plus.mc_we_n_reg[2]_0\(5) => \cmd_pipe_plus.mc_we_n_reg[2]\(38), + \cmd_pipe_plus.mc_we_n_reg[2]_0\(4) => \cmd_pipe_plus.mc_we_n_reg[2]\(36), + \cmd_pipe_plus.mc_we_n_reg[2]_0\(3) => \cmd_pipe_plus.mc_we_n_reg[2]\(26), + \cmd_pipe_plus.mc_we_n_reg[2]_0\(2) => \cmd_pipe_plus.mc_we_n_reg[2]\(24), + \cmd_pipe_plus.mc_we_n_reg[2]_0\(1) => \cmd_pipe_plus.mc_we_n_reg[2]\(10), + \cmd_pipe_plus.mc_we_n_reg[2]_0\(0) => \cmd_pipe_plus.mc_we_n_reg[2]\(8), + \cmd_pipe_plus.mc_we_n_reg[2]_1\(2 downto 0) => mc_we_n(2 downto 0), + \cmd_pipe_plus.wr_data_en_reg_0\ => \cmd_pipe_plus.wr_data_en_reg\, + \generate_maint_cmds.insert_maint_r_lcl_reg\ => \generate_maint_cmds.insert_maint_r_lcl_reg\, + \grant_r_reg[0]\ => ddr_phy_top0_n_58, + idle => idle, + idle_r_lcl_reg => idle_r_lcl_reg, + idle_r_lcl_reg_0 => idle_r_lcl_reg_0, + idle_r_lcl_reg_1 => idle_r_lcl_reg_1, + idle_r_lcl_reg_2 => idle_r_lcl_reg_2, + \inhbt_act_faw.inhbt_act_faw_r_reg\ => \inhbt_act_faw.inhbt_act_faw_r_reg\, + \last_master_r_reg[2]\ => \last_master_r_reg[2]\, + \maintenance_request.maint_zq_r_lcl_reg\ => \maintenance_request.maint_zq_r_lcl_reg\, + mc_cas_n(2 downto 0) => mc_cas_n(2 downto 0), + mc_cke(0) => mc_cke(3), + mc_cmd(1 downto 0) => mc_cmd(1 downto 0), + mc_odt(0) => mc_odt(0), + mc_ras_n(2 downto 0) => mc_ras_n(2 downto 0), + mc_ref_zq_wip => tempmon_sample_en, + mc_wrdata_en => mc_wrdata_en, + \not_strict_mode.app_rd_data_end_ns\ => \not_strict_mode.app_rd_data_end_ns\, + \not_strict_mode.app_rd_data_end_reg\(0) => \not_strict_mode.app_rd_data_end_reg\(0), + \not_strict_mode.app_rd_data_end_reg_0\ => \not_strict_mode.app_rd_data_end_reg_0\, + \not_strict_mode.bypass__0\ => \^not_strict_mode.bypass__0\, + periodic_rd_ack_r_lcl_reg => periodic_rd_ack_r, + periodic_rd_cntr_r_reg => periodic_rd_cntr_r, + \periodic_rd_generation.periodic_rd_timer_r_reg[2]\ => ddr_phy_top0_n_54, + \periodic_read_request.periodic_rd_r_lcl_reg\ => periodic_rd_r, + \periodic_read_request.periodic_rd_r_lcl_reg_0\ => ddr_phy_top0_n_351, + phy_mc_cmd_full => phy_mc_cmd_full, + phy_mc_ctl_full => phy_mc_ctl_full, + phy_mc_data_full => phy_mc_data_full, + ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0), + ram_init_done_r => ram_init_done_r, + rb_hit_busy_r_reg => rb_hit_busy_r_reg, + rb_hit_busy_r_reg_0 => rb_hit_busy_r_reg_0, + rb_hit_busy_r_reg_1 => rb_hit_busy_r_reg_1, + rb_hit_busy_r_reg_2 => rb_hit_busy_r_reg_2, + rd_data_en => rd_data_en, + rd_wr_r_lcl_reg => rd_wr_r_lcl_reg, + \read_fifo.fifo_out_data_r_reg[5]\ => ddr_phy_top0_n_353, + \read_fifo.fifo_out_data_r_reg[6]\ => \read_fifo.fifo_out_data_r_reg[6]\, + \read_fifo.head_r_reg[0]\(0) => \read_fifo.head_r_reg[0]\(0), + \read_fifo.tail_r_reg[0]\(0) => \col_mach0/read_fifo.tail_r_reg\(0), + \read_fifo.tail_r_reg[0]_0\ => ddr_phy_top0_n_354, + \read_fifo.tail_r_reg[1]\ => ddr_phy_top0_n_59, + \req_bank_r_lcl_reg[2]\(2 downto 0) => req_bank_r(11 downto 9), + \req_bank_r_lcl_reg[2]_0\(2 downto 0) => req_bank_r(2 downto 0), + \req_bank_r_lcl_reg[2]_1\(2 downto 0) => req_bank_r(5 downto 3), + \req_bank_r_lcl_reg[2]_2\(2 downto 0) => req_bank_r(8 downto 6), + \req_bank_r_lcl_reg[2]_3\(2 downto 0) => \req_bank_r_lcl_reg[2]\(2 downto 0), + \req_col_r_reg[9]\(9 downto 0) => \req_col_r_reg[9]\(9 downto 0), + \req_data_buf_addr_r_reg[4]\(4 downto 0) => \req_data_buf_addr_r_reg[4]\(4 downto 0), + \req_row_r_lcl_reg[14]\(14 downto 0) => \req_row_r_lcl_reg[14]\(14 downto 0), + req_wr_r_lcl0 => req_wr_r_lcl0, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + rnk_config_valid_r_lcl_reg(0) => rnk_config_valid_r_lcl_reg(1), + row(14 downto 0) => row(14 downto 0), + row_hit_r_reg(0) => row_hit_r_reg(0), + \rtp_timer_r_reg[0]\ => \rtp_timer_r_reg[0]\, + was_priority_reg => was_priority_reg, + was_wr0 => was_wr0, + wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0), + wr_data_en => wr_data_en, + \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_mig_7series_v4_2_memc_ui_top_std is + port ( + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + insert_maint_r : out STD_LOGIC; + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg : out STD_LOGIC; + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + A_rst_primitives_reg_0 : out STD_LOGIC; + \rd_ptr_reg[0]_1\ : out STD_LOGIC; + \rd_ptr_reg[1]_1\ : out STD_LOGIC; + \rd_ptr_reg[2]_1\ : out STD_LOGIC; + \rd_ptr_reg[3]_1\ : out STD_LOGIC; + ref_dll_lock : out STD_LOGIC; + ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_reset_n : out STD_LOGIC; + ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_cas_n : out STD_LOGIC; + ddr3_ras_n : out STD_LOGIC; + ddr3_we_n : out STD_LOGIC; + app_sr_active : out STD_LOGIC; + E : out STD_LOGIC_VECTOR ( 0 to 0 ); + app_wdf_rdy : out STD_LOGIC; + \not_strict_mode.app_rd_data_end_reg\ : out STD_LOGIC; + app_rd_data_valid : out STD_LOGIC; + po_cnt_dec : out STD_LOGIC; + po_cnt_dec_0 : out STD_LOGIC; + new_cnt_cpt_r_reg : out STD_LOGIC; + rdlvl_stg1_start_reg : out STD_LOGIC; + samp_edge_cnt0_en_r : out STD_LOGIC; + pi_cnt_dec : out STD_LOGIC; + prbs_rdlvl_done_pulse : out STD_LOGIC; + phy_dout : out STD_LOGIC_VECTOR ( 0 to 0 ); + \cmd_pipe_plus.mc_we_n_reg[2]\ : out STD_LOGIC_VECTOR ( 38 downto 0 ); + \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 71 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 71 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 73 downto 0 ); + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \wr_ptr_reg[0]\ : out STD_LOGIC; + \wr_ptr_reg[1]\ : out STD_LOGIC; + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + \wr_ptr_reg[0]_0\ : out STD_LOGIC; + \wr_ptr_reg[1]_0\ : out STD_LOGIC; + \wr_ptr_reg[3]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 ); + p_1_in : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + wr_en : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); + ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + CLK : in STD_LOGIC; + SR : in STD_LOGIC_VECTOR ( 0 to 0 ); + freq_refclk : in STD_LOGIC; + mem_refclk : in STD_LOGIC; + sync_pulse : in STD_LOGIC; + CLKB0 : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + pll_locked : in STD_LOGIC; + \read_fifo.head_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + RST0 : in STD_LOGIC; + \maintenance_request.maint_zq_r_lcl_reg\ : in STD_LOGIC; + \zq_cntrl.zq_request_logic.zq_request_r_reg\ : in STD_LOGIC; + rnk_config_valid_r_lcl_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); + reset_reg_0 : in STD_LOGIC; + app_en : in STD_LOGIC; + dqs_po_en_stg2_f_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \dqs_count_r_reg[0]\ : in STD_LOGIC; + wl_edge_detect_valid_r_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); + \done_cnt_reg[1]\ : in STD_LOGIC; + \samp_edge_cnt1_r_reg[0]\ : in STD_LOGIC; + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + first_fail_detect_reg : in STD_LOGIC; + pi_dqs_found_done_r1_reg : in STD_LOGIC; + app_wdf_wren : in STD_LOGIC; + app_wdf_end : in STD_LOGIC; + app_zq_req : in STD_LOGIC; + app_sr_req : in STD_LOGIC; + \last_master_r_reg[2]\ : in STD_LOGIC; + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ : in STD_LOGIC; + \inhbt_act_faw.inhbt_act_faw_r_reg\ : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 47 downto 0 ); + \idelay_tap_cnt_r_reg[0][1][4]\ : in STD_LOGIC; + complex_row0_rd_done_reg : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ : in STD_LOGIC; + \my_empty_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + app_addr : in STD_LOGIC_VECTOR ( 27 downto 0 ); + app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 ); + app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 ); + app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + SS : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \tap_cnt_cpt_r_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \cnt_shift_r_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + \wait_cnt_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); + D : in STD_LOGIC_VECTOR ( 11 downto 0 ); + out_fifo : in STD_LOGIC_VECTOR ( 71 downto 0 ); + out_fifo_0 : in STD_LOGIC_VECTOR ( 71 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_mig_7series_v4_2_memc_ui_top_std : entity is "mig_7series_v4_2_memc_ui_top_std"; +end ddr3_mig_7series_v4_2_memc_ui_top_std; + +architecture STRUCTURE of ddr3_mig_7series_v4_2_memc_ui_top_std is + signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal accept_ns : STD_LOGIC; + signal bank : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal col : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal data_buf_addr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_wr_r_lcl0\ : STD_LOGIC; + signal \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r\ : STD_LOGIC; + signal \mc0/bank_mach0/bank_common0/was_wr0\ : STD_LOGIC; + signal \mc0/bank_mach0/req_bank_r\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \mc0/bank_mach0/req_row_r\ : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal \mc0/periodic_rd_ack_r\ : STD_LOGIC; + signal \mc0/periodic_rd_r\ : STD_LOGIC; + signal mem_intfc0_n_228 : STD_LOGIC; + signal mem_intfc0_n_304 : STD_LOGIC; + signal mem_intfc0_n_305 : STD_LOGIC; + signal mem_intfc0_n_306 : STD_LOGIC; + signal mem_intfc0_n_307 : STD_LOGIC; + signal mem_intfc0_n_308 : STD_LOGIC; + signal mem_intfc0_n_309 : STD_LOGIC; + signal mem_intfc0_n_310 : STD_LOGIC; + signal mem_intfc0_n_311 : STD_LOGIC; + signal mem_intfc0_n_312 : STD_LOGIC; + signal mem_intfc0_n_313 : STD_LOGIC; + signal mem_intfc0_n_314 : STD_LOGIC; + signal mem_intfc0_n_315 : STD_LOGIC; + signal mem_intfc0_n_316 : STD_LOGIC; + signal mem_intfc0_n_317 : STD_LOGIC; + signal mem_intfc0_n_318 : STD_LOGIC; + signal mem_intfc0_n_319 : STD_LOGIC; + signal mem_intfc0_n_320 : STD_LOGIC; + signal mem_intfc0_n_321 : STD_LOGIC; + signal mem_intfc0_n_322 : STD_LOGIC; + signal mem_intfc0_n_323 : STD_LOGIC; + signal mem_intfc0_n_324 : STD_LOGIC; + signal mem_intfc0_n_325 : STD_LOGIC; + signal mem_intfc0_n_326 : STD_LOGIC; + signal mem_intfc0_n_327 : STD_LOGIC; + signal mem_intfc0_n_328 : STD_LOGIC; + signal mem_intfc0_n_329 : STD_LOGIC; + signal mem_intfc0_n_330 : STD_LOGIC; + signal mem_intfc0_n_331 : STD_LOGIC; + signal mem_intfc0_n_332 : STD_LOGIC; + signal mem_intfc0_n_333 : STD_LOGIC; + signal mem_intfc0_n_334 : STD_LOGIC; + signal mem_intfc0_n_335 : STD_LOGIC; + signal mem_intfc0_n_336 : STD_LOGIC; + signal mem_intfc0_n_337 : STD_LOGIC; + signal mem_intfc0_n_338 : STD_LOGIC; + signal mem_intfc0_n_339 : STD_LOGIC; + signal mem_intfc0_n_340 : STD_LOGIC; + signal mem_intfc0_n_341 : STD_LOGIC; + signal mem_intfc0_n_342 : STD_LOGIC; + signal mem_intfc0_n_343 : STD_LOGIC; + signal mem_intfc0_n_344 : STD_LOGIC; + signal mem_intfc0_n_345 : STD_LOGIC; + signal mem_intfc0_n_346 : STD_LOGIC; + signal mem_intfc0_n_347 : STD_LOGIC; + signal mem_intfc0_n_348 : STD_LOGIC; + signal mem_intfc0_n_349 : STD_LOGIC; + signal mem_intfc0_n_350 : STD_LOGIC; + signal mem_intfc0_n_351 : STD_LOGIC; + signal mem_intfc0_n_352 : STD_LOGIC; + signal mem_intfc0_n_353 : STD_LOGIC; + signal mem_intfc0_n_354 : STD_LOGIC; + signal mem_intfc0_n_355 : STD_LOGIC; + signal mem_intfc0_n_356 : STD_LOGIC; + signal mem_intfc0_n_357 : STD_LOGIC; + signal mem_intfc0_n_358 : STD_LOGIC; + signal mem_intfc0_n_359 : STD_LOGIC; + signal mem_intfc0_n_360 : STD_LOGIC; + signal mem_intfc0_n_361 : STD_LOGIC; + signal mem_intfc0_n_362 : STD_LOGIC; + signal mem_intfc0_n_363 : STD_LOGIC; + signal mem_intfc0_n_364 : STD_LOGIC; + signal mem_intfc0_n_365 : STD_LOGIC; + signal mem_intfc0_n_366 : STD_LOGIC; + signal mem_intfc0_n_367 : STD_LOGIC; + signal mem_intfc0_n_61 : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of mem_intfc0_n_61 : signal is "50"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of mem_intfc0_n_61 : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of mem_intfc0_n_61 : signal is "10"; + signal mem_intfc0_n_62 : STD_LOGIC; + attribute MAX_FANOUT of mem_intfc0_n_62 : signal is "50"; + attribute RTL_MAX_FANOUT of mem_intfc0_n_62 : signal is "found"; + attribute syn_maxfan of mem_intfc0_n_62 : signal is "10"; + signal mem_intfc0_n_622 : STD_LOGIC; + signal mem_intfc0_n_623 : STD_LOGIC; + signal mem_intfc0_n_624 : STD_LOGIC; + signal mem_intfc0_n_625 : STD_LOGIC; + signal mem_intfc0_n_626 : STD_LOGIC; + signal mem_intfc0_n_627 : STD_LOGIC; + signal mem_intfc0_n_628 : STD_LOGIC; + signal mem_intfc0_n_629 : STD_LOGIC; + signal mem_intfc0_n_63 : STD_LOGIC; + attribute MAX_FANOUT of mem_intfc0_n_63 : signal is "50"; + attribute RTL_MAX_FANOUT of mem_intfc0_n_63 : signal is "found"; + attribute syn_maxfan of mem_intfc0_n_63 : signal is "10"; + signal mem_intfc0_n_630 : STD_LOGIC; + signal mem_intfc0_n_631 : STD_LOGIC; + signal mem_intfc0_n_632 : STD_LOGIC; + signal mem_intfc0_n_633 : STD_LOGIC; + signal mem_intfc0_n_634 : STD_LOGIC; + signal mem_intfc0_n_635 : STD_LOGIC; + signal mem_intfc0_n_636 : STD_LOGIC; + signal mem_intfc0_n_637 : STD_LOGIC; + signal mem_intfc0_n_638 : STD_LOGIC; + signal mem_intfc0_n_639 : STD_LOGIC; + signal mem_intfc0_n_64 : STD_LOGIC; + signal mem_intfc0_n_640 : STD_LOGIC; + signal mem_intfc0_n_641 : STD_LOGIC; + signal mem_intfc0_n_642 : STD_LOGIC; + signal mem_intfc0_n_643 : STD_LOGIC; + signal mem_intfc0_n_644 : STD_LOGIC; + signal mem_intfc0_n_645 : STD_LOGIC; + signal mem_intfc0_n_646 : STD_LOGIC; + signal mem_intfc0_n_647 : STD_LOGIC; + signal mem_intfc0_n_648 : STD_LOGIC; + signal mem_intfc0_n_649 : STD_LOGIC; + signal mem_intfc0_n_65 : STD_LOGIC; + signal mem_intfc0_n_650 : STD_LOGIC; + signal mem_intfc0_n_651 : STD_LOGIC; + signal mem_intfc0_n_652 : STD_LOGIC; + signal mem_intfc0_n_653 : STD_LOGIC; + signal mem_intfc0_n_654 : STD_LOGIC; + signal mem_intfc0_n_655 : STD_LOGIC; + signal mem_intfc0_n_656 : STD_LOGIC; + signal mem_intfc0_n_657 : STD_LOGIC; + signal mem_intfc0_n_658 : STD_LOGIC; + signal mem_intfc0_n_659 : STD_LOGIC; + signal mem_intfc0_n_66 : STD_LOGIC; + signal mem_intfc0_n_660 : STD_LOGIC; + signal mem_intfc0_n_661 : STD_LOGIC; + signal mem_intfc0_n_662 : STD_LOGIC; + signal mem_intfc0_n_663 : STD_LOGIC; + signal mem_intfc0_n_664 : STD_LOGIC; + signal mem_intfc0_n_665 : STD_LOGIC; + signal mem_intfc0_n_666 : STD_LOGIC; + signal mem_intfc0_n_667 : STD_LOGIC; + signal mem_intfc0_n_668 : STD_LOGIC; + signal mem_intfc0_n_669 : STD_LOGIC; + signal mem_intfc0_n_67 : STD_LOGIC; + signal mem_intfc0_n_670 : STD_LOGIC; + signal mem_intfc0_n_671 : STD_LOGIC; + signal mem_intfc0_n_672 : STD_LOGIC; + signal mem_intfc0_n_673 : STD_LOGIC; + signal mem_intfc0_n_674 : STD_LOGIC; + signal mem_intfc0_n_675 : STD_LOGIC; + signal mem_intfc0_n_676 : STD_LOGIC; + signal mem_intfc0_n_677 : STD_LOGIC; + signal mem_intfc0_n_678 : STD_LOGIC; + signal mem_intfc0_n_679 : STD_LOGIC; + signal mem_intfc0_n_68 : STD_LOGIC; + signal mem_intfc0_n_680 : STD_LOGIC; + signal mem_intfc0_n_681 : STD_LOGIC; + signal mem_intfc0_n_682 : STD_LOGIC; + signal mem_intfc0_n_683 : STD_LOGIC; + signal mem_intfc0_n_684 : STD_LOGIC; + signal mem_intfc0_n_685 : STD_LOGIC; + signal \not_strict_mode.app_rd_data_ns\ : STD_LOGIC_VECTOR ( 127 downto 0 ); + signal ram_init_addr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal ram_init_done_r : STD_LOGIC; + signal rd_data_addr : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal rd_data_end : STD_LOGIC; + signal rd_data_offset : STD_LOGIC; + signal reset_reg_n_0 : STD_LOGIC; + signal row : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal u_ui_top_n_1 : STD_LOGIC; + signal u_ui_top_n_10 : STD_LOGIC; + signal u_ui_top_n_100 : STD_LOGIC; + signal u_ui_top_n_101 : STD_LOGIC; + signal u_ui_top_n_102 : STD_LOGIC; + signal u_ui_top_n_103 : STD_LOGIC; + signal u_ui_top_n_104 : STD_LOGIC; + signal u_ui_top_n_105 : STD_LOGIC; + signal u_ui_top_n_106 : STD_LOGIC; + signal u_ui_top_n_107 : STD_LOGIC; + signal u_ui_top_n_108 : STD_LOGIC; + signal u_ui_top_n_109 : STD_LOGIC; + signal u_ui_top_n_11 : STD_LOGIC; + signal u_ui_top_n_110 : STD_LOGIC; + signal u_ui_top_n_111 : STD_LOGIC; + signal u_ui_top_n_112 : STD_LOGIC; + signal u_ui_top_n_113 : STD_LOGIC; + signal u_ui_top_n_114 : STD_LOGIC; + signal u_ui_top_n_115 : STD_LOGIC; + signal u_ui_top_n_116 : STD_LOGIC; + signal u_ui_top_n_117 : STD_LOGIC; + signal u_ui_top_n_118 : STD_LOGIC; + signal u_ui_top_n_119 : STD_LOGIC; + signal u_ui_top_n_12 : STD_LOGIC; + signal u_ui_top_n_120 : STD_LOGIC; + signal u_ui_top_n_121 : STD_LOGIC; + signal u_ui_top_n_122 : STD_LOGIC; + signal u_ui_top_n_123 : STD_LOGIC; + signal u_ui_top_n_124 : STD_LOGIC; + signal u_ui_top_n_125 : STD_LOGIC; + signal u_ui_top_n_126 : STD_LOGIC; + signal u_ui_top_n_127 : STD_LOGIC; + signal u_ui_top_n_128 : STD_LOGIC; + signal u_ui_top_n_129 : STD_LOGIC; + signal u_ui_top_n_13 : STD_LOGIC; + signal u_ui_top_n_130 : STD_LOGIC; + signal u_ui_top_n_131 : STD_LOGIC; + signal u_ui_top_n_132 : STD_LOGIC; + signal u_ui_top_n_133 : STD_LOGIC; + signal u_ui_top_n_14 : STD_LOGIC; + signal u_ui_top_n_140 : STD_LOGIC; + signal u_ui_top_n_141 : STD_LOGIC; + signal u_ui_top_n_146 : STD_LOGIC; + signal u_ui_top_n_147 : STD_LOGIC; + signal u_ui_top_n_148 : STD_LOGIC; + signal u_ui_top_n_149 : STD_LOGIC; + signal u_ui_top_n_15 : STD_LOGIC; + signal u_ui_top_n_150 : STD_LOGIC; + signal u_ui_top_n_151 : STD_LOGIC; + signal u_ui_top_n_152 : STD_LOGIC; + signal u_ui_top_n_153 : STD_LOGIC; + signal u_ui_top_n_16 : STD_LOGIC; + signal u_ui_top_n_169 : STD_LOGIC; + signal u_ui_top_n_17 : STD_LOGIC; + signal u_ui_top_n_18 : STD_LOGIC; + signal u_ui_top_n_19 : STD_LOGIC; + signal u_ui_top_n_20 : STD_LOGIC; + signal u_ui_top_n_21 : STD_LOGIC; + signal u_ui_top_n_22 : STD_LOGIC; + signal u_ui_top_n_23 : STD_LOGIC; + signal u_ui_top_n_24 : STD_LOGIC; + signal u_ui_top_n_25 : STD_LOGIC; + signal u_ui_top_n_26 : STD_LOGIC; + signal u_ui_top_n_27 : STD_LOGIC; + signal u_ui_top_n_28 : STD_LOGIC; + signal u_ui_top_n_29 : STD_LOGIC; + signal u_ui_top_n_30 : STD_LOGIC; + signal u_ui_top_n_31 : STD_LOGIC; + signal u_ui_top_n_32 : STD_LOGIC; + signal u_ui_top_n_33 : STD_LOGIC; + signal u_ui_top_n_34 : STD_LOGIC; + signal u_ui_top_n_35 : STD_LOGIC; + signal u_ui_top_n_36 : STD_LOGIC; + signal u_ui_top_n_37 : STD_LOGIC; + signal u_ui_top_n_38 : STD_LOGIC; + signal u_ui_top_n_39 : STD_LOGIC; + signal u_ui_top_n_40 : STD_LOGIC; + signal u_ui_top_n_41 : STD_LOGIC; + signal u_ui_top_n_42 : STD_LOGIC; + signal u_ui_top_n_43 : STD_LOGIC; + signal u_ui_top_n_44 : STD_LOGIC; + signal u_ui_top_n_45 : STD_LOGIC; + signal u_ui_top_n_46 : STD_LOGIC; + signal u_ui_top_n_47 : STD_LOGIC; + signal u_ui_top_n_48 : STD_LOGIC; + signal u_ui_top_n_49 : STD_LOGIC; + signal u_ui_top_n_50 : STD_LOGIC; + signal u_ui_top_n_51 : STD_LOGIC; + signal u_ui_top_n_52 : STD_LOGIC; + signal u_ui_top_n_53 : STD_LOGIC; + signal u_ui_top_n_54 : STD_LOGIC; + signal u_ui_top_n_55 : STD_LOGIC; + signal u_ui_top_n_56 : STD_LOGIC; + signal u_ui_top_n_57 : STD_LOGIC; + signal u_ui_top_n_58 : STD_LOGIC; + signal u_ui_top_n_59 : STD_LOGIC; + signal u_ui_top_n_6 : STD_LOGIC; + signal u_ui_top_n_60 : STD_LOGIC; + signal u_ui_top_n_61 : STD_LOGIC; + signal u_ui_top_n_62 : STD_LOGIC; + signal u_ui_top_n_63 : STD_LOGIC; + signal u_ui_top_n_64 : STD_LOGIC; + signal u_ui_top_n_65 : STD_LOGIC; + signal u_ui_top_n_66 : STD_LOGIC; + signal u_ui_top_n_67 : STD_LOGIC; + signal u_ui_top_n_68 : STD_LOGIC; + signal u_ui_top_n_69 : STD_LOGIC; + signal u_ui_top_n_7 : STD_LOGIC; + signal u_ui_top_n_70 : STD_LOGIC; + signal u_ui_top_n_71 : STD_LOGIC; + signal u_ui_top_n_72 : STD_LOGIC; + signal u_ui_top_n_73 : STD_LOGIC; + signal u_ui_top_n_74 : STD_LOGIC; + signal u_ui_top_n_75 : STD_LOGIC; + signal u_ui_top_n_76 : STD_LOGIC; + signal u_ui_top_n_77 : STD_LOGIC; + signal u_ui_top_n_78 : STD_LOGIC; + signal u_ui_top_n_79 : STD_LOGIC; + signal u_ui_top_n_8 : STD_LOGIC; + signal u_ui_top_n_80 : STD_LOGIC; + signal u_ui_top_n_81 : STD_LOGIC; + signal u_ui_top_n_82 : STD_LOGIC; + signal u_ui_top_n_83 : STD_LOGIC; + signal u_ui_top_n_84 : STD_LOGIC; + signal u_ui_top_n_85 : STD_LOGIC; + signal u_ui_top_n_86 : STD_LOGIC; + signal u_ui_top_n_87 : STD_LOGIC; + signal u_ui_top_n_88 : STD_LOGIC; + signal u_ui_top_n_89 : STD_LOGIC; + signal u_ui_top_n_9 : STD_LOGIC; + signal u_ui_top_n_90 : STD_LOGIC; + signal u_ui_top_n_91 : STD_LOGIC; + signal u_ui_top_n_92 : STD_LOGIC; + signal u_ui_top_n_93 : STD_LOGIC; + signal u_ui_top_n_94 : STD_LOGIC; + signal u_ui_top_n_95 : STD_LOGIC; + signal u_ui_top_n_96 : STD_LOGIC; + signal u_ui_top_n_97 : STD_LOGIC; + signal u_ui_top_n_98 : STD_LOGIC; + signal u_ui_top_n_99 : STD_LOGIC; + signal \ui_cmd0/app_en_r2\ : STD_LOGIC; + signal \ui_rd_data0/not_strict_mode.app_rd_data_end_ns\ : STD_LOGIC; + signal \ui_rd_data0/not_strict_mode.bypass__0\ : STD_LOGIC; + signal \ui_rd_data0/not_strict_mode.rd_status\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal wr_data : STD_LOGIC_VECTOR ( 127 downto 0 ); + signal wr_data_addr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal wr_data_en : STD_LOGIC; + signal wr_data_mask : STD_LOGIC_VECTOR ( 15 downto 0 ); + attribute syn_maxfan of reset_reg : label is "10"; +begin + E(0) <= \^e\(0); +mem_intfc0: entity work.ddr3_mig_7series_v4_2_mem_intfc + port map ( + A_rst_primitives_reg => A_rst_primitives_reg, + A_rst_primitives_reg_0 => A_rst_primitives_reg_0, + CLK => CLK, + CLKB0 => CLKB0, + CLKB0_4 => CLKB0_4, + D(127 downto 0) => \not_strict_mode.app_rd_data_ns\(127 downto 0), + DIA(1) => mem_intfc0_n_306, + DIA(0) => mem_intfc0_n_307, + DIB(1) => mem_intfc0_n_308, + DIB(0) => mem_intfc0_n_309, + DIC(1) => mem_intfc0_n_304, + DIC(0) => mem_intfc0_n_305, + DOA(1) => u_ui_top_n_6, + DOA(0) => u_ui_top_n_7, + DOB(1) => u_ui_top_n_8, + DOB(0) => u_ui_top_n_9, + DOC(1) => u_ui_top_n_10, + DOC(0) => u_ui_top_n_11, + Q(143 downto 128) => wr_data_mask(15 downto 0), + Q(127 downto 0) => wr_data(127 downto 0), + RST0 => RST0, + S(3) => u_ui_top_n_150, + S(2) => u_ui_top_n_151, + S(1) => u_ui_top_n_152, + S(0) => u_ui_top_n_153, + SR(0) => SR(0), + SS(0) => SS(0), + accept_ns => accept_ns, + app_en_r2 => \ui_cmd0/app_en_r2\, + app_ref_ack => app_ref_ack, + app_ref_req => app_ref_req, + app_sr_active => app_sr_active, + app_sr_req => app_sr_req, + app_zq_ack => app_zq_ack, + app_zq_req => app_zq_req, + \cmd_pipe_plus.mc_we_n_reg[2]\(38 downto 0) => \cmd_pipe_plus.mc_we_n_reg[2]\(38 downto 0), + \cmd_pipe_plus.wr_data_en_reg\ => mem_intfc0_n_228, + \cnt_shift_r_reg[0]\(0) => \cnt_shift_r_reg[0]\(0), + complex_row0_rd_done_reg => complex_row0_rd_done_reg, + ddr3_addr(14 downto 0) => ddr3_addr(14 downto 0), + ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0), + ddr3_cas_n => ddr3_cas_n, + ddr3_cke(0) => ddr3_cke(0), + ddr3_dm(1 downto 0) => ddr3_dm(1 downto 0), + ddr3_dq(15 downto 0) => ddr3_dq(15 downto 0), + ddr3_dqs_n(1 downto 0) => ddr3_dqs_n(1 downto 0), + ddr3_dqs_p(1 downto 0) => ddr3_dqs_p(1 downto 0), + ddr3_odt(0) => ddr3_odt(0), + ddr3_ras_n => ddr3_ras_n, + ddr3_reset_n => ddr3_reset_n, + ddr3_we_n => ddr3_we_n, + ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0), + \device_temp_101_reg[11]\(11 downto 0) => D(11 downto 0), + \done_cnt_reg[1]\ => \done_cnt_reg[1]\, + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(1) => mem_intfc0_n_310, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]\(0) => mem_intfc0_n_311, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(1) => mem_intfc0_n_312, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]\(0) => mem_intfc0_n_313, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(1) => mem_intfc0_n_314, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]\(0) => mem_intfc0_n_315, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(1) => mem_intfc0_n_316, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]\(0) => mem_intfc0_n_317, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(1) => mem_intfc0_n_318, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]\(0) => mem_intfc0_n_319, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(1) => mem_intfc0_n_622, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]\(0) => mem_intfc0_n_623, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(1) => mem_intfc0_n_644, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]\(0) => mem_intfc0_n_645, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(1) => mem_intfc0_n_646, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]\(0) => mem_intfc0_n_647, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(1) => mem_intfc0_n_648, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]\(0) => mem_intfc0_n_649, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(1) => mem_intfc0_n_650, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]\(0) => mem_intfc0_n_651, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(1) => mem_intfc0_n_652, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]\(0) => mem_intfc0_n_653, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(1) => mem_intfc0_n_654, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]\(0) => mem_intfc0_n_655, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(1) => mem_intfc0_n_656, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]\(0) => mem_intfc0_n_657, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(1) => mem_intfc0_n_336, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]\(0) => mem_intfc0_n_337, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(1) => mem_intfc0_n_338, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]\(0) => mem_intfc0_n_339, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(1) => mem_intfc0_n_340, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]\(0) => mem_intfc0_n_341, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(1) => mem_intfc0_n_342, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]\(0) => mem_intfc0_n_343, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(1) => mem_intfc0_n_344, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]\(0) => mem_intfc0_n_345, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(1) => mem_intfc0_n_346, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]\(0) => mem_intfc0_n_347, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(1) => mem_intfc0_n_348, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]\(0) => mem_intfc0_n_349, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(1) => mem_intfc0_n_350, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]\(0) => mem_intfc0_n_351, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(1) => mem_intfc0_n_624, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]\(0) => mem_intfc0_n_625, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(1) => mem_intfc0_n_630, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]\(0) => mem_intfc0_n_631, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(1) => mem_intfc0_n_632, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]\(0) => mem_intfc0_n_633, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(1) => mem_intfc0_n_634, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]\(0) => mem_intfc0_n_635, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(1) => mem_intfc0_n_636, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]\(0) => mem_intfc0_n_637, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(1) => mem_intfc0_n_638, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]\(0) => mem_intfc0_n_639, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(1) => mem_intfc0_n_640, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]\(0) => mem_intfc0_n_641, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(1) => mem_intfc0_n_642, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]\(0) => mem_intfc0_n_643, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(1) => mem_intfc0_n_352, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]\(0) => mem_intfc0_n_353, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(1) => mem_intfc0_n_626, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0\(0) => mem_intfc0_n_627, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(1) => mem_intfc0_n_354, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]\(0) => mem_intfc0_n_355, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(1) => mem_intfc0_n_672, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0\(0) => mem_intfc0_n_673, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(1) => mem_intfc0_n_356, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]\(0) => mem_intfc0_n_357, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(1) => mem_intfc0_n_674, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0\(0) => mem_intfc0_n_675, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(1) => mem_intfc0_n_358, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]\(0) => mem_intfc0_n_359, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(1) => mem_intfc0_n_676, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0\(0) => mem_intfc0_n_677, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(1) => mem_intfc0_n_360, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]\(0) => mem_intfc0_n_361, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(1) => mem_intfc0_n_678, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0\(0) => mem_intfc0_n_679, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(1) => mem_intfc0_n_362, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]\(0) => mem_intfc0_n_363, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(1) => mem_intfc0_n_680, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0\(0) => mem_intfc0_n_681, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(1) => mem_intfc0_n_364, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]\(0) => mem_intfc0_n_365, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(1) => mem_intfc0_n_682, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0\(0) => mem_intfc0_n_683, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(1) => mem_intfc0_n_366, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]\(0) => mem_intfc0_n_367, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(1) => mem_intfc0_n_684, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0\(0) => mem_intfc0_n_685, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(1) => mem_intfc0_n_320, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]\(0) => mem_intfc0_n_321, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(1) => mem_intfc0_n_628, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0\(0) => mem_intfc0_n_629, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(1) => mem_intfc0_n_322, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]\(0) => mem_intfc0_n_323, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(1) => mem_intfc0_n_658, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0\(0) => mem_intfc0_n_659, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(1) => mem_intfc0_n_324, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]\(0) => mem_intfc0_n_325, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(1) => mem_intfc0_n_660, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0\(0) => mem_intfc0_n_661, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(1) => mem_intfc0_n_326, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]\(0) => mem_intfc0_n_327, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(1) => mem_intfc0_n_662, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0\(0) => mem_intfc0_n_663, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(1) => mem_intfc0_n_328, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]\(0) => mem_intfc0_n_329, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(1) => mem_intfc0_n_664, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0\(0) => mem_intfc0_n_665, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(1) => mem_intfc0_n_330, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]\(0) => mem_intfc0_n_331, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(1) => mem_intfc0_n_666, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0\(0) => mem_intfc0_n_667, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(1) => mem_intfc0_n_332, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]\(0) => mem_intfc0_n_333, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(1) => mem_intfc0_n_668, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0\(0) => mem_intfc0_n_669, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0) => Q(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(1) => mem_intfc0_n_334, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(0) => mem_intfc0_n_335, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1\(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(1) => mem_intfc0_n_670, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2\(0) => mem_intfc0_n_671, + \dqs_count_r_reg[0]\ => \dqs_count_r_reg[0]\, + dqs_po_en_stg2_f_reg(0) => dqs_po_en_stg2_f_reg(0), + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0) => \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0), + first_fail_detect_reg => first_fail_detect_reg, + freq_refclk => freq_refclk, + \generate_maint_cmds.insert_maint_r_lcl_reg\ => insert_maint_r, + \idelay_tap_cnt_r_reg[0][1][4]\ => \idelay_tap_cnt_r_reg[0][1][4]\, + idle_r_lcl_reg => mem_intfc0_n_64, + idle_r_lcl_reg_0 => mem_intfc0_n_65, + idle_r_lcl_reg_1 => mem_intfc0_n_66, + idle_r_lcl_reg_2 => mem_intfc0_n_67, + \inhbt_act_faw.inhbt_act_faw_r_reg\ => \inhbt_act_faw.inhbt_act_faw_r_reg\, + \init_calib_complete_reg_rep__0\ => mem_intfc0_n_61, + \init_calib_complete_reg_rep__1\ => mem_intfc0_n_62, + \init_calib_complete_reg_rep__2\ => mem_intfc0_n_63, + \last_master_r_reg[2]\ => \last_master_r_reg[2]\, + \maintenance_request.maint_zq_r_lcl_reg\ => \maintenance_request.maint_zq_r_lcl_reg\, + mem_out(47 downto 0) => mem_out(47 downto 0), + mem_refclk => mem_refclk, + \my_empty_reg[8]\(0) => \my_empty_reg[8]\(0), + new_cnt_cpt_r_reg => new_cnt_cpt_r_reg, + \not_strict_mode.app_rd_data_end_ns\ => \ui_rd_data0/not_strict_mode.app_rd_data_end_ns\, + \not_strict_mode.app_rd_data_end_reg\(0) => \ui_rd_data0/not_strict_mode.rd_status\(1), + \not_strict_mode.app_rd_data_end_reg_0\ => u_ui_top_n_1, + \not_strict_mode.app_rd_data_reg[101]\(1) => u_ui_top_n_102, + \not_strict_mode.app_rd_data_reg[101]\(0) => u_ui_top_n_103, + \not_strict_mode.app_rd_data_reg[103]\(1) => u_ui_top_n_112, + \not_strict_mode.app_rd_data_reg[103]\(0) => u_ui_top_n_113, + \not_strict_mode.app_rd_data_reg[105]\(1) => u_ui_top_n_110, + \not_strict_mode.app_rd_data_reg[105]\(0) => u_ui_top_n_111, + \not_strict_mode.app_rd_data_reg[107]\(1) => u_ui_top_n_108, + \not_strict_mode.app_rd_data_reg[107]\(0) => u_ui_top_n_109, + \not_strict_mode.app_rd_data_reg[109]\(1) => u_ui_top_n_118, + \not_strict_mode.app_rd_data_reg[109]\(0) => u_ui_top_n_119, + \not_strict_mode.app_rd_data_reg[111]\(1) => u_ui_top_n_116, + \not_strict_mode.app_rd_data_reg[111]\(0) => u_ui_top_n_117, + \not_strict_mode.app_rd_data_reg[113]\(1) => u_ui_top_n_114, + \not_strict_mode.app_rd_data_reg[113]\(0) => u_ui_top_n_115, + \not_strict_mode.app_rd_data_reg[115]\(1) => u_ui_top_n_124, + \not_strict_mode.app_rd_data_reg[115]\(0) => u_ui_top_n_125, + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[117]_0\(1) => u_ui_top_n_122, + \not_strict_mode.app_rd_data_reg[117]_0\(0) => u_ui_top_n_123, + \not_strict_mode.app_rd_data_reg[119]\(1) => u_ui_top_n_120, + \not_strict_mode.app_rd_data_reg[119]\(0) => u_ui_top_n_121, + \not_strict_mode.app_rd_data_reg[11]\(1) => u_ui_top_n_12, + \not_strict_mode.app_rd_data_reg[11]\(0) => u_ui_top_n_13, + \not_strict_mode.app_rd_data_reg[121]\(1) => u_ui_top_n_130, + \not_strict_mode.app_rd_data_reg[121]\(0) => u_ui_top_n_131, + \not_strict_mode.app_rd_data_reg[123]\(1) => u_ui_top_n_128, + \not_strict_mode.app_rd_data_reg[123]\(0) => u_ui_top_n_129, + \not_strict_mode.app_rd_data_reg[125]\(1) => u_ui_top_n_126, + \not_strict_mode.app_rd_data_reg[125]\(0) => u_ui_top_n_127, + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]_0\(1) => u_ui_top_n_132, + \not_strict_mode.app_rd_data_reg[127]_0\(0) => u_ui_top_n_133, + \not_strict_mode.app_rd_data_reg[13]\(1) => u_ui_top_n_22, + \not_strict_mode.app_rd_data_reg[13]\(0) => u_ui_top_n_23, + \not_strict_mode.app_rd_data_reg[15]\(1) => u_ui_top_n_20, + \not_strict_mode.app_rd_data_reg[15]\(0) => u_ui_top_n_21, + \not_strict_mode.app_rd_data_reg[17]\(1) => u_ui_top_n_18, + \not_strict_mode.app_rd_data_reg[17]\(0) => u_ui_top_n_19, + \not_strict_mode.app_rd_data_reg[19]\(1) => u_ui_top_n_28, + \not_strict_mode.app_rd_data_reg[19]\(0) => u_ui_top_n_29, + \not_strict_mode.app_rd_data_reg[21]\(1) => u_ui_top_n_26, + \not_strict_mode.app_rd_data_reg[21]\(0) => u_ui_top_n_27, + \not_strict_mode.app_rd_data_reg[23]\(1) => u_ui_top_n_24, + \not_strict_mode.app_rd_data_reg[23]\(0) => u_ui_top_n_25, + \not_strict_mode.app_rd_data_reg[25]\(1) => u_ui_top_n_34, + \not_strict_mode.app_rd_data_reg[25]\(0) => u_ui_top_n_35, + \not_strict_mode.app_rd_data_reg[27]\(1) => u_ui_top_n_32, + \not_strict_mode.app_rd_data_reg[27]\(0) => u_ui_top_n_33, + \not_strict_mode.app_rd_data_reg[29]\(1) => u_ui_top_n_30, + \not_strict_mode.app_rd_data_reg[29]\(0) => u_ui_top_n_31, + \not_strict_mode.app_rd_data_reg[31]\(1) => u_ui_top_n_40, + \not_strict_mode.app_rd_data_reg[31]\(0) => u_ui_top_n_41, + \not_strict_mode.app_rd_data_reg[33]\(1) => u_ui_top_n_38, + \not_strict_mode.app_rd_data_reg[33]\(0) => u_ui_top_n_39, + \not_strict_mode.app_rd_data_reg[35]\(1) => u_ui_top_n_36, + \not_strict_mode.app_rd_data_reg[35]\(0) => u_ui_top_n_37, + \not_strict_mode.app_rd_data_reg[37]\(1) => u_ui_top_n_46, + \not_strict_mode.app_rd_data_reg[37]\(0) => u_ui_top_n_47, + \not_strict_mode.app_rd_data_reg[39]\(1) => u_ui_top_n_44, + \not_strict_mode.app_rd_data_reg[39]\(0) => u_ui_top_n_45, + \not_strict_mode.app_rd_data_reg[41]\(1) => u_ui_top_n_42, + \not_strict_mode.app_rd_data_reg[41]\(0) => u_ui_top_n_43, + \not_strict_mode.app_rd_data_reg[43]\(1) => u_ui_top_n_52, + \not_strict_mode.app_rd_data_reg[43]\(0) => u_ui_top_n_53, + \not_strict_mode.app_rd_data_reg[45]\(1) => u_ui_top_n_50, + \not_strict_mode.app_rd_data_reg[45]\(0) => u_ui_top_n_51, + \not_strict_mode.app_rd_data_reg[47]\(1) => u_ui_top_n_48, + \not_strict_mode.app_rd_data_reg[47]\(0) => u_ui_top_n_49, + \not_strict_mode.app_rd_data_reg[49]\(1) => u_ui_top_n_58, + \not_strict_mode.app_rd_data_reg[49]\(0) => u_ui_top_n_59, + \not_strict_mode.app_rd_data_reg[51]\(1) => u_ui_top_n_56, + \not_strict_mode.app_rd_data_reg[51]\(0) => u_ui_top_n_57, + \not_strict_mode.app_rd_data_reg[53]\(1) => u_ui_top_n_54, + \not_strict_mode.app_rd_data_reg[53]\(0) => u_ui_top_n_55, + \not_strict_mode.app_rd_data_reg[55]\(1) => u_ui_top_n_64, + \not_strict_mode.app_rd_data_reg[55]\(0) => u_ui_top_n_65, + \not_strict_mode.app_rd_data_reg[57]\(1) => u_ui_top_n_62, + \not_strict_mode.app_rd_data_reg[57]\(0) => u_ui_top_n_63, + \not_strict_mode.app_rd_data_reg[59]\(1) => u_ui_top_n_60, + \not_strict_mode.app_rd_data_reg[59]\(0) => u_ui_top_n_61, + \not_strict_mode.app_rd_data_reg[61]\(1) => u_ui_top_n_70, + \not_strict_mode.app_rd_data_reg[61]\(0) => u_ui_top_n_71, + \not_strict_mode.app_rd_data_reg[63]\(1) => u_ui_top_n_68, + \not_strict_mode.app_rd_data_reg[63]\(0) => u_ui_top_n_69, + \not_strict_mode.app_rd_data_reg[65]\(1) => u_ui_top_n_66, + \not_strict_mode.app_rd_data_reg[65]\(0) => u_ui_top_n_67, + \not_strict_mode.app_rd_data_reg[67]\(1) => u_ui_top_n_76, + \not_strict_mode.app_rd_data_reg[67]\(0) => u_ui_top_n_77, + \not_strict_mode.app_rd_data_reg[69]\(1) => u_ui_top_n_74, + \not_strict_mode.app_rd_data_reg[69]\(0) => u_ui_top_n_75, + \not_strict_mode.app_rd_data_reg[71]\(1) => u_ui_top_n_72, + \not_strict_mode.app_rd_data_reg[71]\(0) => u_ui_top_n_73, + \not_strict_mode.app_rd_data_reg[73]\(1) => u_ui_top_n_82, + \not_strict_mode.app_rd_data_reg[73]\(0) => u_ui_top_n_83, + \not_strict_mode.app_rd_data_reg[75]\(1) => u_ui_top_n_80, + \not_strict_mode.app_rd_data_reg[75]\(0) => u_ui_top_n_81, + \not_strict_mode.app_rd_data_reg[77]\(1) => u_ui_top_n_78, + \not_strict_mode.app_rd_data_reg[77]\(0) => u_ui_top_n_79, + \not_strict_mode.app_rd_data_reg[79]\(1) => u_ui_top_n_88, + \not_strict_mode.app_rd_data_reg[79]\(0) => u_ui_top_n_89, + \not_strict_mode.app_rd_data_reg[7]\(1) => u_ui_top_n_16, + \not_strict_mode.app_rd_data_reg[7]\(0) => u_ui_top_n_17, + \not_strict_mode.app_rd_data_reg[81]\(1) => u_ui_top_n_86, + \not_strict_mode.app_rd_data_reg[81]\(0) => u_ui_top_n_87, + \not_strict_mode.app_rd_data_reg[83]\(1) => u_ui_top_n_84, + \not_strict_mode.app_rd_data_reg[83]\(0) => u_ui_top_n_85, + \not_strict_mode.app_rd_data_reg[85]\(1) => u_ui_top_n_94, + \not_strict_mode.app_rd_data_reg[85]\(0) => u_ui_top_n_95, + \not_strict_mode.app_rd_data_reg[87]\(1) => u_ui_top_n_92, + \not_strict_mode.app_rd_data_reg[87]\(0) => u_ui_top_n_93, + \not_strict_mode.app_rd_data_reg[89]\(1) => u_ui_top_n_90, + \not_strict_mode.app_rd_data_reg[89]\(0) => u_ui_top_n_91, + \not_strict_mode.app_rd_data_reg[91]\(1) => u_ui_top_n_100, + \not_strict_mode.app_rd_data_reg[91]\(0) => u_ui_top_n_101, + \not_strict_mode.app_rd_data_reg[93]\(1) => u_ui_top_n_98, + \not_strict_mode.app_rd_data_reg[93]\(0) => u_ui_top_n_99, + \not_strict_mode.app_rd_data_reg[95]\(1) => u_ui_top_n_96, + \not_strict_mode.app_rd_data_reg[95]\(0) => u_ui_top_n_97, + \not_strict_mode.app_rd_data_reg[97]\(1) => u_ui_top_n_106, + \not_strict_mode.app_rd_data_reg[97]\(0) => u_ui_top_n_107, + \not_strict_mode.app_rd_data_reg[99]\(1) => u_ui_top_n_104, + \not_strict_mode.app_rd_data_reg[99]\(0) => u_ui_top_n_105, + \not_strict_mode.app_rd_data_reg[9]\(1) => u_ui_top_n_14, + \not_strict_mode.app_rd_data_reg[9]\(0) => u_ui_top_n_15, + \not_strict_mode.bypass__0\ => \ui_rd_data0/not_strict_mode.bypass__0\, + \out\(1 downto 0) => \out\(1 downto 0), + out_fifo(71 downto 0) => out_fifo(71 downto 0), + out_fifo_0(71 downto 0) => out_fifo_0(71 downto 0), + p_1_in => p_1_in, + periodic_rd_ack_r => \mc0/periodic_rd_ack_r\, + periodic_rd_cntr_r => \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r\, + periodic_rd_r => \mc0/periodic_rd_r\, + phy_dout(0) => phy_dout(0), + pi_cnt_dec_reg => pi_cnt_dec, + pi_dqs_found_done_r1_reg => pi_dqs_found_done_r1_reg, + pll_locked => pll_locked, + po_cnt_dec_0 => po_cnt_dec_0, + po_cnt_dec_reg => po_cnt_dec, + prbs_rdlvl_done_pulse_reg => prbs_rdlvl_done_pulse, + ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0), + ram_init_done_r => ram_init_done_r, + rb_hit_busy_r_reg => u_ui_top_n_146, + rb_hit_busy_r_reg_0 => u_ui_top_n_149, + rb_hit_busy_r_reg_1 => u_ui_top_n_148, + rb_hit_busy_r_reg_2 => u_ui_top_n_147, + \rd_ptr_reg[0]\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]_0\, + \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_1\, + \rd_ptr_reg[1]\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]_0\, + \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_1\, + \rd_ptr_reg[2]\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]_0\, + \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_1\, + \rd_ptr_reg[3]\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]_0\, + \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_1\, + \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + rd_wr_r_lcl_reg => u_ui_top_n_140, + rdlvl_stg1_start_reg => rdlvl_stg1_start_reg, + \read_fifo.fifo_out_data_r_reg[6]\ => mem_intfc0_n_68, + \read_fifo.fifo_out_data_r_reg[7]\(6) => rd_data_end, + \read_fifo.fifo_out_data_r_reg[7]\(5 downto 1) => rd_data_addr(4 downto 0), + \read_fifo.fifo_out_data_r_reg[7]\(0) => rd_data_offset, + \read_fifo.head_r_reg[0]\(0) => \read_fifo.head_r_reg[0]\(0), + ref_dll_lock => ref_dll_lock, + req_bank_r(11 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 0), + \req_bank_r_lcl_reg[2]\(2 downto 0) => bank(2 downto 0), + \req_col_r_reg[9]\(9 downto 0) => col(9 downto 0), + \req_data_buf_addr_r_reg[4]\(4) => u_ui_top_n_141, + \req_data_buf_addr_r_reg[4]\(3 downto 0) => data_buf_addr(3 downto 0), + \req_row_r_lcl_reg[14]\(14 downto 0) => \mc0/bank_mach0/req_row_r\(14 downto 0), + req_wr_r_lcl0 => \mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_wr_r_lcl0\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\, + rnk_config_valid_r_lcl_reg(1 downto 0) => rnk_config_valid_r_lcl_reg(1 downto 0), + row(14 downto 0) => row(14 downto 0), + row_hit_r_reg(0) => u_ui_top_n_169, + \rtp_timer_r_reg[0]\ => reset_reg_0, + samp_edge_cnt0_en_r => samp_edge_cnt0_en_r, + \samp_edge_cnt1_r_reg[0]\ => \samp_edge_cnt1_r_reg[0]\, + sync_pulse => sync_pulse, + \tap_cnt_cpt_r_reg[5]\(0) => \tap_cnt_cpt_r_reg[5]\(0), + \wait_cnt_r_reg[0]\(0) => \wait_cnt_r_reg[0]\(0), + \wait_cnt_r_reg[0]_0\(0) => \wait_cnt_r_reg[0]_0\(0), + was_priority_reg => \^e\(0), + was_wr0 => \mc0/bank_mach0/bank_common0/was_wr0\, + wl_edge_detect_valid_r_reg(0) => wl_edge_detect_valid_r_reg(0), + wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0), + wr_data_en => wr_data_en, + wr_en => wr_en, + wr_en_2 => wr_en_2, + wr_en_3 => wr_en_3, + \wr_ptr_reg[0]\ => \wr_ptr_reg[0]\, + \wr_ptr_reg[0]_0\ => \wr_ptr_reg[0]_0\, + \wr_ptr_reg[1]\ => \wr_ptr_reg[1]\, + \wr_ptr_reg[1]_0\ => \wr_ptr_reg[1]_0\, + \wr_ptr_reg[3]\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0), + \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_1\(3 downto 0), + \write_buffer.wr_buf_out_data_reg[117]\(59 downto 55) => \write_buffer.wr_buf_out_data_reg[117]\(71 downto 67), + \write_buffer.wr_buf_out_data_reg[117]\(54 downto 51) => \write_buffer.wr_buf_out_data_reg[117]\(65 downto 62), + \write_buffer.wr_buf_out_data_reg[117]\(50 downto 47) => \write_buffer.wr_buf_out_data_reg[117]\(60 downto 57), + \write_buffer.wr_buf_out_data_reg[117]\(46 downto 44) => \write_buffer.wr_buf_out_data_reg[117]\(55 downto 53), + \write_buffer.wr_buf_out_data_reg[117]\(43 downto 38) => \write_buffer.wr_buf_out_data_reg[117]\(50 downto 45), + \write_buffer.wr_buf_out_data_reg[117]\(37 downto 33) => \write_buffer.wr_buf_out_data_reg[117]\(42 downto 38), + \write_buffer.wr_buf_out_data_reg[117]\(32 downto 29) => \write_buffer.wr_buf_out_data_reg[117]\(36 downto 33), + \write_buffer.wr_buf_out_data_reg[117]\(28 downto 14) => \write_buffer.wr_buf_out_data_reg[117]\(31 downto 17), + \write_buffer.wr_buf_out_data_reg[117]\(13 downto 7) => \write_buffer.wr_buf_out_data_reg[117]\(15 downto 9), + \write_buffer.wr_buf_out_data_reg[117]\(6 downto 2) => \write_buffer.wr_buf_out_data_reg[117]\(7 downto 3), + \write_buffer.wr_buf_out_data_reg[117]\(1 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(1 downto 0), + \write_buffer.wr_buf_out_data_reg[127]\(59 downto 58) => \write_buffer.wr_buf_out_data_reg[127]\(71 downto 70), + \write_buffer.wr_buf_out_data_reg[127]\(57 downto 54) => \write_buffer.wr_buf_out_data_reg[127]\(68 downto 65), + \write_buffer.wr_buf_out_data_reg[127]\(53 downto 49) => \write_buffer.wr_buf_out_data_reg[127]\(63 downto 59), + \write_buffer.wr_buf_out_data_reg[127]\(48 downto 42) => \write_buffer.wr_buf_out_data_reg[127]\(57 downto 51), + \write_buffer.wr_buf_out_data_reg[127]\(41 downto 33) => \write_buffer.wr_buf_out_data_reg[127]\(49 downto 41), + \write_buffer.wr_buf_out_data_reg[127]\(32 downto 30) => \write_buffer.wr_buf_out_data_reg[127]\(39 downto 37), + \write_buffer.wr_buf_out_data_reg[127]\(29 downto 25) => \write_buffer.wr_buf_out_data_reg[127]\(34 downto 30), + \write_buffer.wr_buf_out_data_reg[127]\(24 downto 21) => \write_buffer.wr_buf_out_data_reg[127]\(28 downto 25), + \write_buffer.wr_buf_out_data_reg[127]\(20 downto 18) => \write_buffer.wr_buf_out_data_reg[127]\(23 downto 21), + \write_buffer.wr_buf_out_data_reg[127]\(17 downto 0) => \write_buffer.wr_buf_out_data_reg[127]\(18 downto 1), + \zq_cntrl.zq_request_logic.zq_request_r_reg\ => \zq_cntrl.zq_request_logic.zq_request_r_reg\ + ); +reset_reg: unisim.vcomponents.FDRE + port map ( + C => CLK, + CE => '1', + D => reset_reg_0, + Q => reset_reg_n_0, + R => '0' + ); +u_ui_top: entity work.ddr3_mig_7series_v4_2_ui_top + port map ( + CLK => CLK, + D(127 downto 0) => \not_strict_mode.app_rd_data_ns\(127 downto 0), + DIA(1) => mem_intfc0_n_306, + DIA(0) => mem_intfc0_n_307, + DIB(1) => mem_intfc0_n_308, + DIB(0) => mem_intfc0_n_309, + DIC(1) => mem_intfc0_n_304, + DIC(0) => mem_intfc0_n_305, + DOA(1) => u_ui_top_n_6, + DOA(0) => u_ui_top_n_7, + DOB(1) => u_ui_top_n_8, + DOB(0) => u_ui_top_n_9, + DOC(1) => u_ui_top_n_10, + DOC(0) => u_ui_top_n_11, + E(0) => wr_data_en, + Q(143 downto 128) => wr_data_mask(15 downto 0), + Q(127 downto 0) => wr_data(127 downto 0), + S(3) => u_ui_top_n_150, + S(2) => u_ui_top_n_151, + S(1) => u_ui_top_n_152, + S(0) => u_ui_top_n_153, + accept_ns => accept_ns, + app_addr(27 downto 0) => app_addr(27 downto 0), + \app_addr_r1_reg[27]\(2 downto 0) => bank(2 downto 0), + \app_addr_r1_reg[9]\(9 downto 0) => col(9 downto 0), + app_cmd(1 downto 0) => app_cmd(1 downto 0), + \app_cmd_r2_reg[0]\ => u_ui_top_n_140, + app_en => app_en, + app_en_r2 => \ui_cmd0/app_en_r2\, + app_rd_data(127 downto 0) => app_rd_data(127 downto 0), + app_rd_data_valid => app_rd_data_valid, + app_rdy_r_reg => \^e\(0), + app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0), + app_wdf_end => app_wdf_end, + app_wdf_end_r1_reg => reset_reg_n_0, + app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0), + app_wdf_rdy => app_wdf_rdy, + app_wdf_wren => app_wdf_wren, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ => mem_intfc0_n_62, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ => mem_intfc0_n_63, + \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_0\ => mem_intfc0_n_61, + \not_strict_mode.app_rd_data_end_ns\ => \ui_rd_data0/not_strict_mode.app_rd_data_end_ns\, + \not_strict_mode.app_rd_data_end_reg\ => \not_strict_mode.app_rd_data_end_reg\, + \not_strict_mode.app_rd_data_reg[101]\(1) => mem_intfc0_n_332, + \not_strict_mode.app_rd_data_reg[101]\(0) => mem_intfc0_n_333, + \not_strict_mode.app_rd_data_reg[101]_0\(1) => mem_intfc0_n_364, + \not_strict_mode.app_rd_data_reg[101]_0\(0) => mem_intfc0_n_365, + \not_strict_mode.app_rd_data_reg[101]_1\(1) => mem_intfc0_n_316, + \not_strict_mode.app_rd_data_reg[101]_1\(0) => mem_intfc0_n_317, + \not_strict_mode.app_rd_data_reg[107]\(1) => mem_intfc0_n_654, + \not_strict_mode.app_rd_data_reg[107]\(0) => mem_intfc0_n_655, + \not_strict_mode.app_rd_data_reg[107]_0\(1) => mem_intfc0_n_640, + \not_strict_mode.app_rd_data_reg[107]_0\(0) => mem_intfc0_n_641, + \not_strict_mode.app_rd_data_reg[107]_1\(1) => mem_intfc0_n_348, + \not_strict_mode.app_rd_data_reg[107]_1\(0) => mem_intfc0_n_349, + \not_strict_mode.app_rd_data_reg[113]\(1) => mem_intfc0_n_318, + \not_strict_mode.app_rd_data_reg[113]\(0) => mem_intfc0_n_319, + \not_strict_mode.app_rd_data_reg[113]_0\(1) => mem_intfc0_n_668, + \not_strict_mode.app_rd_data_reg[113]_0\(0) => mem_intfc0_n_669, + \not_strict_mode.app_rd_data_reg[113]_1\(1) => mem_intfc0_n_682, + \not_strict_mode.app_rd_data_reg[113]_1\(0) => mem_intfc0_n_683, + \not_strict_mode.app_rd_data_reg[119]\(1) => mem_intfc0_n_350, + \not_strict_mode.app_rd_data_reg[119]\(0) => mem_intfc0_n_351, + \not_strict_mode.app_rd_data_reg[119]_0\(1) => mem_intfc0_n_334, + \not_strict_mode.app_rd_data_reg[119]_0\(0) => mem_intfc0_n_335, + \not_strict_mode.app_rd_data_reg[119]_1\(1) => mem_intfc0_n_366, + \not_strict_mode.app_rd_data_reg[119]_1\(0) => mem_intfc0_n_367, + \not_strict_mode.app_rd_data_reg[11]\(1) => mem_intfc0_n_622, + \not_strict_mode.app_rd_data_reg[11]\(0) => mem_intfc0_n_623, + \not_strict_mode.app_rd_data_reg[11]_0\(1) => mem_intfc0_n_624, + \not_strict_mode.app_rd_data_reg[11]_0\(0) => mem_intfc0_n_625, + \not_strict_mode.app_rd_data_reg[11]_1\(1) => mem_intfc0_n_336, + \not_strict_mode.app_rd_data_reg[11]_1\(0) => mem_intfc0_n_337, + \not_strict_mode.app_rd_data_reg[125]\(1) => mem_intfc0_n_684, + \not_strict_mode.app_rd_data_reg[125]\(0) => mem_intfc0_n_685, + \not_strict_mode.app_rd_data_reg[125]_0\(1) => mem_intfc0_n_656, + \not_strict_mode.app_rd_data_reg[125]_0\(0) => mem_intfc0_n_657, + \not_strict_mode.app_rd_data_reg[125]_1\(1) => mem_intfc0_n_642, + \not_strict_mode.app_rd_data_reg[125]_1\(0) => mem_intfc0_n_643, + \not_strict_mode.app_rd_data_reg[127]\(1) => mem_intfc0_n_670, + \not_strict_mode.app_rd_data_reg[127]\(0) => mem_intfc0_n_671, + \not_strict_mode.app_rd_data_reg[17]\(1) => mem_intfc0_n_628, + \not_strict_mode.app_rd_data_reg[17]\(0) => mem_intfc0_n_629, + \not_strict_mode.app_rd_data_reg[17]_0\(1) => mem_intfc0_n_626, + \not_strict_mode.app_rd_data_reg[17]_0\(0) => mem_intfc0_n_627, + \not_strict_mode.app_rd_data_reg[23]\(1) => mem_intfc0_n_338, + \not_strict_mode.app_rd_data_reg[23]\(0) => mem_intfc0_n_339, + \not_strict_mode.app_rd_data_reg[23]_0\(1) => mem_intfc0_n_322, + \not_strict_mode.app_rd_data_reg[23]_0\(0) => mem_intfc0_n_323, + \not_strict_mode.app_rd_data_reg[23]_1\(1) => mem_intfc0_n_354, + \not_strict_mode.app_rd_data_reg[23]_1\(0) => mem_intfc0_n_355, + \not_strict_mode.app_rd_data_reg[29]\(1) => mem_intfc0_n_672, + \not_strict_mode.app_rd_data_reg[29]\(0) => mem_intfc0_n_673, + \not_strict_mode.app_rd_data_reg[29]_0\(1) => mem_intfc0_n_644, + \not_strict_mode.app_rd_data_reg[29]_0\(0) => mem_intfc0_n_645, + \not_strict_mode.app_rd_data_reg[29]_1\(1) => mem_intfc0_n_630, + \not_strict_mode.app_rd_data_reg[29]_1\(0) => mem_intfc0_n_631, + \not_strict_mode.app_rd_data_reg[35]\(1) => mem_intfc0_n_356, + \not_strict_mode.app_rd_data_reg[35]\(0) => mem_intfc0_n_357, + \not_strict_mode.app_rd_data_reg[35]_0\(1) => mem_intfc0_n_658, + \not_strict_mode.app_rd_data_reg[35]_0\(0) => mem_intfc0_n_659, + \not_strict_mode.app_rd_data_reg[41]\(1) => mem_intfc0_n_632, + \not_strict_mode.app_rd_data_reg[41]\(0) => mem_intfc0_n_633, + \not_strict_mode.app_rd_data_reg[41]_0\(1) => mem_intfc0_n_340, + \not_strict_mode.app_rd_data_reg[41]_0\(0) => mem_intfc0_n_341, + \not_strict_mode.app_rd_data_reg[41]_1\(1) => mem_intfc0_n_324, + \not_strict_mode.app_rd_data_reg[41]_1\(0) => mem_intfc0_n_325, + \not_strict_mode.app_rd_data_reg[47]\(1) => mem_intfc0_n_660, + \not_strict_mode.app_rd_data_reg[47]\(0) => mem_intfc0_n_661, + \not_strict_mode.app_rd_data_reg[47]_0\(1) => mem_intfc0_n_674, + \not_strict_mode.app_rd_data_reg[47]_0\(0) => mem_intfc0_n_675, + \not_strict_mode.app_rd_data_reg[47]_1\(1) => mem_intfc0_n_646, + \not_strict_mode.app_rd_data_reg[47]_1\(0) => mem_intfc0_n_647, + \not_strict_mode.app_rd_data_reg[53]\(1) => mem_intfc0_n_326, + \not_strict_mode.app_rd_data_reg[53]\(0) => mem_intfc0_n_327, + \not_strict_mode.app_rd_data_reg[53]_0\(1) => mem_intfc0_n_358, + \not_strict_mode.app_rd_data_reg[53]_0\(0) => mem_intfc0_n_359, + \not_strict_mode.app_rd_data_reg[53]_1\(1) => mem_intfc0_n_310, + \not_strict_mode.app_rd_data_reg[53]_1\(0) => mem_intfc0_n_311, + \not_strict_mode.app_rd_data_reg[59]\(1) => mem_intfc0_n_648, + \not_strict_mode.app_rd_data_reg[59]\(0) => mem_intfc0_n_649, + \not_strict_mode.app_rd_data_reg[59]_0\(1) => mem_intfc0_n_634, + \not_strict_mode.app_rd_data_reg[59]_0\(0) => mem_intfc0_n_635, + \not_strict_mode.app_rd_data_reg[59]_1\(1) => mem_intfc0_n_342, + \not_strict_mode.app_rd_data_reg[59]_1\(0) => mem_intfc0_n_343, + \not_strict_mode.app_rd_data_reg[5]\(1) => mem_intfc0_n_320, + \not_strict_mode.app_rd_data_reg[5]\(0) => mem_intfc0_n_321, + \not_strict_mode.app_rd_data_reg[5]_0\(1) => mem_intfc0_n_352, + \not_strict_mode.app_rd_data_reg[5]_0\(0) => mem_intfc0_n_353, + \not_strict_mode.app_rd_data_reg[65]\(1) => mem_intfc0_n_312, + \not_strict_mode.app_rd_data_reg[65]\(0) => mem_intfc0_n_313, + \not_strict_mode.app_rd_data_reg[65]_0\(1) => mem_intfc0_n_662, + \not_strict_mode.app_rd_data_reg[65]_0\(0) => mem_intfc0_n_663, + \not_strict_mode.app_rd_data_reg[65]_1\(1) => mem_intfc0_n_676, + \not_strict_mode.app_rd_data_reg[65]_1\(0) => mem_intfc0_n_677, + \not_strict_mode.app_rd_data_reg[71]\(1) => mem_intfc0_n_344, + \not_strict_mode.app_rd_data_reg[71]\(0) => mem_intfc0_n_345, + \not_strict_mode.app_rd_data_reg[71]_0\(1) => mem_intfc0_n_328, + \not_strict_mode.app_rd_data_reg[71]_0\(0) => mem_intfc0_n_329, + \not_strict_mode.app_rd_data_reg[71]_1\(1) => mem_intfc0_n_360, + \not_strict_mode.app_rd_data_reg[71]_1\(0) => mem_intfc0_n_361, + \not_strict_mode.app_rd_data_reg[77]\(1) => mem_intfc0_n_678, + \not_strict_mode.app_rd_data_reg[77]\(0) => mem_intfc0_n_679, + \not_strict_mode.app_rd_data_reg[77]_0\(1) => mem_intfc0_n_650, + \not_strict_mode.app_rd_data_reg[77]_0\(0) => mem_intfc0_n_651, + \not_strict_mode.app_rd_data_reg[77]_1\(1) => mem_intfc0_n_636, + \not_strict_mode.app_rd_data_reg[77]_1\(0) => mem_intfc0_n_637, + \not_strict_mode.app_rd_data_reg[83]\(1) => mem_intfc0_n_362, + \not_strict_mode.app_rd_data_reg[83]\(0) => mem_intfc0_n_363, + \not_strict_mode.app_rd_data_reg[83]_0\(1) => mem_intfc0_n_314, + \not_strict_mode.app_rd_data_reg[83]_0\(0) => mem_intfc0_n_315, + \not_strict_mode.app_rd_data_reg[83]_1\(1) => mem_intfc0_n_664, + \not_strict_mode.app_rd_data_reg[83]_1\(0) => mem_intfc0_n_665, + \not_strict_mode.app_rd_data_reg[89]\(1) => mem_intfc0_n_638, + \not_strict_mode.app_rd_data_reg[89]\(0) => mem_intfc0_n_639, + \not_strict_mode.app_rd_data_reg[89]_0\(1) => mem_intfc0_n_346, + \not_strict_mode.app_rd_data_reg[89]_0\(0) => mem_intfc0_n_347, + \not_strict_mode.app_rd_data_reg[89]_1\(1) => mem_intfc0_n_330, + \not_strict_mode.app_rd_data_reg[89]_1\(0) => mem_intfc0_n_331, + \not_strict_mode.app_rd_data_reg[95]\(1) => mem_intfc0_n_666, + \not_strict_mode.app_rd_data_reg[95]\(0) => mem_intfc0_n_667, + \not_strict_mode.app_rd_data_reg[95]_0\(1) => mem_intfc0_n_680, + \not_strict_mode.app_rd_data_reg[95]_0\(0) => mem_intfc0_n_681, + \not_strict_mode.app_rd_data_reg[95]_1\(1) => mem_intfc0_n_652, + \not_strict_mode.app_rd_data_reg[95]_1\(0) => mem_intfc0_n_653, + \not_strict_mode.bypass__0\ => \ui_rd_data0/not_strict_mode.bypass__0\, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(1) => u_ui_top_n_12, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]\(0) => u_ui_top_n_13, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(1) => u_ui_top_n_14, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_0\(0) => u_ui_top_n_15, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(1) => u_ui_top_n_16, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_1\(0) => u_ui_top_n_17, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(1) => u_ui_top_n_34, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_10\(0) => u_ui_top_n_35, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(1) => u_ui_top_n_36, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_11\(0) => u_ui_top_n_37, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(1) => u_ui_top_n_38, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_12\(0) => u_ui_top_n_39, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(1) => u_ui_top_n_40, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_13\(0) => u_ui_top_n_41, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(1) => u_ui_top_n_42, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_14\(0) => u_ui_top_n_43, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(1) => u_ui_top_n_44, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_15\(0) => u_ui_top_n_45, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(1) => u_ui_top_n_46, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_16\(0) => u_ui_top_n_47, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(1) => u_ui_top_n_48, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_17\(0) => u_ui_top_n_49, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(1) => u_ui_top_n_50, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_18\(0) => u_ui_top_n_51, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(1) => u_ui_top_n_52, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_19\(0) => u_ui_top_n_53, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(1) => u_ui_top_n_18, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_2\(0) => u_ui_top_n_19, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(1) => u_ui_top_n_54, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_20\(0) => u_ui_top_n_55, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(1) => u_ui_top_n_56, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_21\(0) => u_ui_top_n_57, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(1) => u_ui_top_n_58, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_22\(0) => u_ui_top_n_59, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(1) => u_ui_top_n_60, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_23\(0) => u_ui_top_n_61, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(1) => u_ui_top_n_62, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_24\(0) => u_ui_top_n_63, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(1) => u_ui_top_n_64, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_25\(0) => u_ui_top_n_65, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(1) => u_ui_top_n_66, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_26\(0) => u_ui_top_n_67, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(1) => u_ui_top_n_68, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_27\(0) => u_ui_top_n_69, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(1) => u_ui_top_n_70, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_28\(0) => u_ui_top_n_71, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(1) => u_ui_top_n_72, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_29\(0) => u_ui_top_n_73, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(1) => u_ui_top_n_20, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_3\(0) => u_ui_top_n_21, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(1) => u_ui_top_n_74, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_30\(0) => u_ui_top_n_75, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(1) => u_ui_top_n_76, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_31\(0) => u_ui_top_n_77, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(1) => u_ui_top_n_78, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_32\(0) => u_ui_top_n_79, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(1) => u_ui_top_n_80, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_33\(0) => u_ui_top_n_81, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(1) => u_ui_top_n_82, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_34\(0) => u_ui_top_n_83, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(1) => u_ui_top_n_84, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_35\(0) => u_ui_top_n_85, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(1) => u_ui_top_n_86, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_36\(0) => u_ui_top_n_87, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(1) => u_ui_top_n_88, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_37\(0) => u_ui_top_n_89, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(1) => u_ui_top_n_90, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_38\(0) => u_ui_top_n_91, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(1) => u_ui_top_n_92, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_39\(0) => u_ui_top_n_93, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(1) => u_ui_top_n_22, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_4\(0) => u_ui_top_n_23, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(1) => u_ui_top_n_94, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_40\(0) => u_ui_top_n_95, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(1) => u_ui_top_n_96, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_41\(0) => u_ui_top_n_97, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(1) => u_ui_top_n_98, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_42\(0) => u_ui_top_n_99, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(1) => u_ui_top_n_100, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_43\(0) => u_ui_top_n_101, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(1) => u_ui_top_n_102, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_44\(0) => u_ui_top_n_103, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(1) => u_ui_top_n_104, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_45\(0) => u_ui_top_n_105, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(1) => u_ui_top_n_106, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_46\(0) => u_ui_top_n_107, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(1) => u_ui_top_n_108, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_47\(0) => u_ui_top_n_109, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(1) => u_ui_top_n_110, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_48\(0) => u_ui_top_n_111, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(1) => u_ui_top_n_112, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_49\(0) => u_ui_top_n_113, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(1) => u_ui_top_n_24, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_5\(0) => u_ui_top_n_25, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(1) => u_ui_top_n_114, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_50\(0) => u_ui_top_n_115, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(1) => u_ui_top_n_116, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_51\(0) => u_ui_top_n_117, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(1) => u_ui_top_n_118, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_52\(0) => u_ui_top_n_119, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(1) => u_ui_top_n_120, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_53\(0) => u_ui_top_n_121, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(1) => u_ui_top_n_122, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_54\(0) => u_ui_top_n_123, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(1) => u_ui_top_n_124, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_55\(0) => u_ui_top_n_125, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(1) => u_ui_top_n_126, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_56\(0) => u_ui_top_n_127, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(1) => u_ui_top_n_128, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_57\(0) => u_ui_top_n_129, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(1) => u_ui_top_n_130, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_58\(0) => u_ui_top_n_131, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(1) => u_ui_top_n_132, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_59\(0) => u_ui_top_n_133, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(1) => u_ui_top_n_26, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_6\(0) => u_ui_top_n_27, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(1) => u_ui_top_n_28, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_7\(0) => u_ui_top_n_29, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(1) => u_ui_top_n_30, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_8\(0) => u_ui_top_n_31, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(1) => u_ui_top_n_32, + \not_strict_mode.rd_buf.rd_buf_indx_copy_r_reg[4]_9\(0) => u_ui_top_n_33, + \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(4) => u_ui_top_n_141, + \not_strict_mode.rd_data_buf_addr_r_lcl_reg[4]\(3 downto 0) => data_buf_addr(3 downto 0), + \not_strict_mode.status_ram.rd_buf_we_r1_reg\(0) => \ui_rd_data0/not_strict_mode.rd_status\(1), + \not_strict_mode.status_ram.rd_buf_we_r1_reg_0\ => mem_intfc0_n_68, + \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]\(6) => rd_data_end, + \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]\(5 downto 1) => rd_data_addr(4 downto 0), + \not_strict_mode.status_ram.status_ram_wr_data_r_reg[1]\(0) => rd_data_offset, + periodic_rd_ack_r => \mc0/periodic_rd_ack_r\, + periodic_rd_cntr_r => \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r\, + periodic_rd_r => \mc0/periodic_rd_r\, + ram_init_addr(3 downto 0) => ram_init_addr(3 downto 0), + ram_init_done_r => ram_init_done_r, + rb_hit_busy_r_reg => mem_intfc0_n_64, + rb_hit_busy_r_reg_0 => mem_intfc0_n_65, + rb_hit_busy_r_reg_1 => mem_intfc0_n_66, + rb_hit_busy_r_reg_2 => mem_intfc0_n_67, + \rd_buf_indx.rd_buf_indx_r_reg[4]\ => u_ui_top_n_1, + req_bank_r(11 downto 0) => \mc0/bank_mach0/req_bank_r\(11 downto 0), + \req_bank_r_lcl_reg[0]\ => u_ui_top_n_147, + \req_bank_r_lcl_reg[0]_0\ => u_ui_top_n_149, + \req_bank_r_lcl_reg[2]\ => u_ui_top_n_146, + \req_bank_r_lcl_reg[2]_0\ => u_ui_top_n_148, + \req_row_r_lcl_reg[13]\(0) => u_ui_top_n_169, + req_wr_r_lcl0 => \mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_wr_r_lcl0\, + row(14 downto 0) => row(14 downto 0), + row_hit_r_reg(14 downto 0) => \mc0/bank_mach0/req_row_r\(14 downto 0), + was_wr0 => \mc0/bank_mach0/bank_common0/was_wr0\, + wr_data_addr(3 downto 0) => wr_data_addr(3 downto 0), + \write_buffer.wr_buf_out_data_reg[37]\(11) => \write_buffer.wr_buf_out_data_reg[117]\(66), + \write_buffer.wr_buf_out_data_reg[37]\(10) => \write_buffer.wr_buf_out_data_reg[117]\(61), + \write_buffer.wr_buf_out_data_reg[37]\(9) => \write_buffer.wr_buf_out_data_reg[117]\(56), + \write_buffer.wr_buf_out_data_reg[37]\(8 downto 7) => \write_buffer.wr_buf_out_data_reg[117]\(52 downto 51), + \write_buffer.wr_buf_out_data_reg[37]\(6 downto 5) => \write_buffer.wr_buf_out_data_reg[117]\(44 downto 43), + \write_buffer.wr_buf_out_data_reg[37]\(4) => \write_buffer.wr_buf_out_data_reg[117]\(37), + \write_buffer.wr_buf_out_data_reg[37]\(3) => \write_buffer.wr_buf_out_data_reg[117]\(32), + \write_buffer.wr_buf_out_data_reg[37]\(2) => \write_buffer.wr_buf_out_data_reg[117]\(16), + \write_buffer.wr_buf_out_data_reg[37]\(1) => \write_buffer.wr_buf_out_data_reg[117]\(8), + \write_buffer.wr_buf_out_data_reg[37]\(0) => \write_buffer.wr_buf_out_data_reg[117]\(2), + \write_buffer.wr_buf_out_data_reg[95]\(11) => \write_buffer.wr_buf_out_data_reg[127]\(69), + \write_buffer.wr_buf_out_data_reg[95]\(10) => \write_buffer.wr_buf_out_data_reg[127]\(64), + \write_buffer.wr_buf_out_data_reg[95]\(9) => \write_buffer.wr_buf_out_data_reg[127]\(58), + \write_buffer.wr_buf_out_data_reg[95]\(8) => \write_buffer.wr_buf_out_data_reg[127]\(50), + \write_buffer.wr_buf_out_data_reg[95]\(7) => \write_buffer.wr_buf_out_data_reg[127]\(40), + \write_buffer.wr_buf_out_data_reg[95]\(6 downto 5) => \write_buffer.wr_buf_out_data_reg[127]\(36 downto 35), + \write_buffer.wr_buf_out_data_reg[95]\(4) => \write_buffer.wr_buf_out_data_reg[127]\(29), + \write_buffer.wr_buf_out_data_reg[95]\(3) => \write_buffer.wr_buf_out_data_reg[127]\(24), + \write_buffer.wr_buf_out_data_reg[95]\(2 downto 1) => \write_buffer.wr_buf_out_data_reg[127]\(20 downto 19), + \write_buffer.wr_buf_out_data_reg[95]\(0) => \write_buffer.wr_buf_out_data_reg[127]\(0), + \write_data_control.wb_wr_data_addr_r_reg[2]\ => mem_intfc0_n_228 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3_ddr3_mig is + port ( + \gen_mmcm.mmcm_i\ : out STD_LOGIC; + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + rd_ptr : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \out\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + iserdes_clk : out STD_LOGIC; + \rd_ptr_reg[0]\ : out STD_LOGIC; + \rd_ptr_reg[1]\ : out STD_LOGIC; + \rd_ptr_reg[2]\ : out STD_LOGIC; + \rd_ptr_reg[3]\ : out STD_LOGIC; + \rd_ptr_timing_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); + iserdes_clk_0 : out STD_LOGIC; + \rd_ptr_reg[0]_0\ : out STD_LOGIC; + \rd_ptr_reg[1]_0\ : out STD_LOGIC; + \rd_ptr_reg[2]_0\ : out STD_LOGIC; + \rd_ptr_reg[3]_0\ : out STD_LOGIC; + ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_reset_n : out STD_LOGIC; + ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_cas_n : out STD_LOGIC; + ddr3_ras_n : out STD_LOGIC; + ddr3_we_n : out STD_LOGIC; + app_sr_active : out STD_LOGIC; + app_rdy_r_reg : out STD_LOGIC; + app_wdf_rdy : out STD_LOGIC; + \not_strict_mode.app_rd_data_end_reg\ : out STD_LOGIC; + app_rd_data_valid : out STD_LOGIC; + \device_temp_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); + ui_clk_sync_rst : out STD_LOGIC; + phy_dout : out STD_LOGIC_VECTOR ( 38 downto 0 ); + \write_buffer.wr_buf_out_data_reg[117]\ : out STD_LOGIC_VECTOR ( 71 downto 0 ); + \write_buffer.wr_buf_out_data_reg[127]\ : out STD_LOGIC_VECTOR ( 71 downto 0 ); + Q : out STD_LOGIC_VECTOR ( 3 downto 0 ); + wr_ptr : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \wr_ptr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + wr_ptr_1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + \wr_ptr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\ : out STD_LOGIC_VECTOR ( 73 downto 0 ); + app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 ); + p_1_in : out STD_LOGIC; + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ : out STD_LOGIC; + wr_en : out STD_LOGIC; + wr_en_2 : out STD_LOGIC; + wr_en_3 : out STD_LOGIC; + ddr_ck_out : out STD_LOGIC_VECTOR ( 1 downto 0 ); + init_calib_complete : out STD_LOGIC; + ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); + ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + CLKB0 : in STD_LOGIC; + CLKB0_4 : in STD_LOGIC; + app_en : in STD_LOGIC; + device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 ); + clk_ref_i : in STD_LOGIC; + sys_rst : in STD_LOGIC; + app_wdf_wren : in STD_LOGIC; + app_wdf_end : in STD_LOGIC; + app_zq_req : in STD_LOGIC; + app_sr_req : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + mem_out : in STD_LOGIC_VECTOR ( 47 downto 0 ); + app_addr : in STD_LOGIC_VECTOR ( 27 downto 0 ); + app_cmd : in STD_LOGIC_VECTOR ( 1 downto 0 ); + app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 ); + app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + sys_clk_i : in STD_LOGIC; + \not_strict_mode.app_rd_data_reg[117]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + \not_strict_mode.app_rd_data_reg[127]\ : in STD_LOGIC_VECTOR ( 63 downto 0 ); + out_fifo : in STD_LOGIC_VECTOR ( 71 downto 0 ); + out_fifo_0 : in STD_LOGIC_VECTOR ( 71 downto 0 ) + ); + attribute ORIG_REF_NAME : string; + attribute ORIG_REF_NAME of ddr3_ddr3_mig : entity is "ddr3_mig"; +end ddr3_ddr3_mig; + +architecture STRUCTURE of ddr3_ddr3_mig is + signal device_temp_sync_r4_neq_r3 : STD_LOGIC; + signal freq_refclk : STD_LOGIC; + signal \^gen_mmcm.mmcm_i\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\ : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\ : STD_LOGIC; + signal \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0\ : STD_LOGIC; + signal \mem_intfc0/mc0/bank_mach0/insert_maint_r\ : STD_LOGIC; + signal mem_refclk : STD_LOGIC; + signal mmcm_clk : STD_LOGIC; + signal pll_locked : STD_LOGIC; + signal ref_dll_lock : STD_LOGIC; + signal rst_tmp : STD_LOGIC; + signal rstdiv0_sync_r1 : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of rstdiv0_sync_r1 : signal is "50"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of rstdiv0_sync_r1 : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of rstdiv0_sync_r1 : signal is "50"; + signal sync_pulse : STD_LOGIC; + signal sys_rst_act_hi : STD_LOGIC; + signal u_ddr3_infrastructure_n_0 : STD_LOGIC; + signal u_ddr3_infrastructure_n_10 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_10 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_10 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_10 : signal is "50"; + signal u_ddr3_infrastructure_n_11 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_11 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_11 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_11 : signal is "50"; + signal u_ddr3_infrastructure_n_12 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_12 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_12 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_12 : signal is "50"; + signal u_ddr3_infrastructure_n_13 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_13 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_13 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_13 : signal is "50"; + signal u_ddr3_infrastructure_n_14 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_14 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_14 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_14 : signal is "50"; + signal u_ddr3_infrastructure_n_15 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_15 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_15 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_15 : signal is "50"; + signal u_ddr3_infrastructure_n_16 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_16 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_16 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_16 : signal is "50"; + signal u_ddr3_infrastructure_n_17 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_17 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_17 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_17 : signal is "50"; + signal u_ddr3_infrastructure_n_18 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_18 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_18 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_18 : signal is "50"; + signal u_ddr3_infrastructure_n_19 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_19 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_19 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_19 : signal is "50"; + signal u_ddr3_infrastructure_n_20 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_20 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_20 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_20 : signal is "50"; + signal u_ddr3_infrastructure_n_21 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_21 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_21 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_21 : signal is "50"; + signal u_ddr3_infrastructure_n_22 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_22 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_22 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_22 : signal is "50"; + signal u_ddr3_infrastructure_n_23 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_23 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_23 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_23 : signal is "50"; + signal u_ddr3_infrastructure_n_24 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_24 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_24 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_24 : signal is "50"; + signal u_ddr3_infrastructure_n_26 : STD_LOGIC; + signal u_ddr3_infrastructure_n_27 : STD_LOGIC; + signal u_ddr3_infrastructure_n_29 : STD_LOGIC; + signal u_ddr3_infrastructure_n_30 : STD_LOGIC; + signal u_ddr3_infrastructure_n_33 : STD_LOGIC; + signal u_ddr3_infrastructure_n_34 : STD_LOGIC; + signal u_ddr3_infrastructure_n_35 : STD_LOGIC; + signal u_ddr3_infrastructure_n_7 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_7 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_7 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_7 : signal is "50"; + signal u_ddr3_infrastructure_n_8 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_8 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_8 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_8 : signal is "50"; + signal u_ddr3_infrastructure_n_9 : STD_LOGIC; + attribute MAX_FANOUT of u_ddr3_infrastructure_n_9 : signal is "50"; + attribute RTL_MAX_FANOUT of u_ddr3_infrastructure_n_9 : signal is "found"; + attribute syn_maxfan of u_ddr3_infrastructure_n_9 : signal is "50"; + signal u_memc_ui_top_std_n_55 : STD_LOGIC; + signal u_memc_ui_top_std_n_56 : STD_LOGIC; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of u_memc_ui_top_std : label is "mig_7series_v4_2_ddr3_7Series, ddr3, 2018.3"; +begin + \gen_mmcm.mmcm_i\ <= \^gen_mmcm.mmcm_i\; +\temp_mon_enabled.u_tempmon\: entity work.ddr3_mig_7series_v4_2_tempmon + port map ( + D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0), + SR(0) => u_ddr3_infrastructure_n_27, + device_temp_i(11 downto 0) => device_temp_i(11 downto 0), + \device_temp_r_reg[11]_0\ => \^gen_mmcm.mmcm_i\, + device_temp_sync_r4_neq_r3 => device_temp_sync_r4_neq_r3, + \out\(11 downto 0) => \device_temp_r_reg[11]\(11 downto 0) + ); +u_ddr3_clk_ibuf: entity work.ddr3_mig_7series_v4_2_clk_ibuf + port map ( + mmcm_clk => mmcm_clk, + sys_clk_i => sys_clk_i + ); +u_ddr3_infrastructure: entity work.ddr3_mig_7series_v4_2_infrastructure + port map ( + AS(0) => sys_rst_act_hi, + CLK => \^gen_mmcm.mmcm_i\, + RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0\, + SR(0) => rstdiv0_sync_r1, + SS(0) => u_ddr3_infrastructure_n_29, + \cnt_shift_r_reg[0]\ => u_memc_ui_top_std_n_56, + device_temp_sync_r4_neq_r3 => device_temp_sync_r4_neq_r3, + freq_refclk => freq_refclk, + \gen_mmcm.mmcm_i_i_1_0\ => u_ddr3_infrastructure_n_0, + insert_maint_r => \mem_intfc0/mc0/bank_mach0/insert_maint_r\, + mem_refclk => mem_refclk, + mmcm_clk => mmcm_clk, + pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\, + pll_locked => pll_locked, + po_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\, + po_cnt_dec_0 => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec\, + prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\, + rst_tmp => rst_tmp, + rstdiv0_sync_r1_reg_rep_0(0) => u_ddr3_infrastructure_n_7, + \rstdiv0_sync_r1_reg_rep__0_0\(0) => u_ddr3_infrastructure_n_8, + \rstdiv0_sync_r1_reg_rep__10_0\ => u_ddr3_infrastructure_n_19, + \rstdiv0_sync_r1_reg_rep__12_0\ => u_ddr3_infrastructure_n_20, + \rstdiv0_sync_r1_reg_rep__13_0\ => u_ddr3_infrastructure_n_21, + \rstdiv0_sync_r1_reg_rep__14_0\ => u_ddr3_infrastructure_n_22, + \rstdiv0_sync_r1_reg_rep__14_1\(0) => u_ddr3_infrastructure_n_30, + \rstdiv0_sync_r1_reg_rep__15_0\ => u_ddr3_infrastructure_n_23, + \rstdiv0_sync_r1_reg_rep__15_1\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\, + \rstdiv0_sync_r1_reg_rep__15_2\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\, + \rstdiv0_sync_r1_reg_rep__15_3\ => u_ddr3_infrastructure_n_33, + \rstdiv0_sync_r1_reg_rep__15_4\(0) => u_ddr3_infrastructure_n_34, + \rstdiv0_sync_r1_reg_rep__16_0\ => u_ddr3_infrastructure_n_24, + \rstdiv0_sync_r1_reg_rep__16_1\ => u_ddr3_infrastructure_n_26, + \rstdiv0_sync_r1_reg_rep__16_2\(0) => u_ddr3_infrastructure_n_27, + \rstdiv0_sync_r1_reg_rep__16_3\ => u_ddr3_infrastructure_n_35, + \rstdiv0_sync_r1_reg_rep__1_0\(0) => u_ddr3_infrastructure_n_9, + \rstdiv0_sync_r1_reg_rep__2_0\(0) => u_ddr3_infrastructure_n_10, + \rstdiv0_sync_r1_reg_rep__3_0\ => u_ddr3_infrastructure_n_11, + \rstdiv0_sync_r1_reg_rep__4_0\ => u_ddr3_infrastructure_n_12, + \rstdiv0_sync_r1_reg_rep__5_0\(0) => u_ddr3_infrastructure_n_13, + \rstdiv0_sync_r1_reg_rep__6_0\ => u_ddr3_infrastructure_n_14, + \rstdiv0_sync_r1_reg_rep__7_0\ => u_ddr3_infrastructure_n_15, + \rstdiv0_sync_r1_reg_rep__8_0\(1) => u_ddr3_infrastructure_n_16, + \rstdiv0_sync_r1_reg_rep__8_0\(0) => u_ddr3_infrastructure_n_17, + \rstdiv0_sync_r1_reg_rep__9_0\ => u_ddr3_infrastructure_n_18, + samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\, + sync_pulse => sync_pulse, + \tap_cnt_cpt_r_reg[5]\ => u_memc_ui_top_std_n_55, + ui_clk_sync_rst => ui_clk_sync_rst + ); +u_iodelay_ctrl: entity work.ddr3_mig_7series_v4_2_iodelay_ctrl + port map ( + AS(0) => sys_rst_act_hi, + clk_ref_i => clk_ref_i, + ref_dll_lock => ref_dll_lock, + rst_tmp => rst_tmp, + \rstdiv2_sync_r_reg[11]\ => u_ddr3_infrastructure_n_0, + sys_rst => sys_rst + ); +u_memc_ui_top_std: entity work.ddr3_mig_7series_v4_2_memc_ui_top_std + port map ( + A_rst_primitives_reg => iserdes_clk, + A_rst_primitives_reg_0 => iserdes_clk_0, + CLK => \^gen_mmcm.mmcm_i\, + CLKB0 => CLKB0, + CLKB0_4 => CLKB0_4, + D(11 downto 0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100\(11 downto 0), + E(0) => app_rdy_r_reg, + Q(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(73 downto 0), + RST0 => \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0\, + SR(0) => u_ddr3_infrastructure_n_7, + SS(0) => u_ddr3_infrastructure_n_29, + app_addr(27 downto 0) => app_addr(27 downto 0), + app_cmd(1 downto 0) => app_cmd(1 downto 0), + app_en => app_en, + app_rd_data(127 downto 0) => app_rd_data(127 downto 0), + app_rd_data_valid => app_rd_data_valid, + app_ref_ack => app_ref_ack, + app_ref_req => app_ref_req, + app_sr_active => app_sr_active, + app_sr_req => app_sr_req, + app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0), + app_wdf_end => app_wdf_end, + app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0), + app_wdf_rdy => app_wdf_rdy, + app_wdf_wren => app_wdf_wren, + app_zq_ack => app_zq_ack, + app_zq_req => app_zq_req, + \cmd_pipe_plus.mc_we_n_reg[2]\(38 downto 0) => phy_dout(38 downto 0), + \cnt_shift_r_reg[0]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0\, + complex_row0_rd_done_reg => u_ddr3_infrastructure_n_35, + ddr3_addr(14 downto 0) => ddr3_addr(14 downto 0), + ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0), + ddr3_cas_n => ddr3_cas_n, + ddr3_cke(0) => ddr3_cke(0), + ddr3_dm(1 downto 0) => ddr3_dm(1 downto 0), + ddr3_dq(15 downto 0) => ddr3_dq(15 downto 0), + ddr3_dqs_n(1 downto 0) => ddr3_dqs_n(1 downto 0), + ddr3_dqs_p(1 downto 0) => ddr3_dqs_p(1 downto 0), + ddr3_odt(0) => ddr3_odt(0), + ddr3_ras_n => ddr3_ras_n, + ddr3_reset_n => ddr3_reset_n, + ddr3_we_n => ddr3_we_n, + ddr_ck_out(1 downto 0) => ddr_ck_out(1 downto 0), + \done_cnt_reg[1]\ => u_ddr3_infrastructure_n_12, + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0) => \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0), + \dqs_count_r_reg[0]\ => u_ddr3_infrastructure_n_11, + dqs_po_en_stg2_f_reg(0) => u_ddr3_infrastructure_n_9, + \en_cnt_div4.enable_wrlvl_cnt_reg[2]\(0) => u_ddr3_infrastructure_n_13, + first_fail_detect_reg => u_ddr3_infrastructure_n_18, + freq_refclk => freq_refclk, + \idelay_tap_cnt_r_reg[0][1][4]\ => u_ddr3_infrastructure_n_23, + \inhbt_act_faw.inhbt_act_faw_r_reg\ => u_ddr3_infrastructure_n_22, + insert_maint_r => \mem_intfc0/mc0/bank_mach0/insert_maint_r\, + \last_master_r_reg[2]\ => u_ddr3_infrastructure_n_20, + \maintenance_request.maint_zq_r_lcl_reg\ => u_ddr3_infrastructure_n_15, + mem_out(47 downto 0) => mem_out(47 downto 0), + mem_refclk => mem_refclk, + \my_empty_reg[8]\(0) => u_ddr3_infrastructure_n_8, + new_cnt_cpt_r_reg => u_memc_ui_top_std_n_55, + \not_strict_mode.app_rd_data_end_reg\ => \not_strict_mode.app_rd_data_end_reg\, + \not_strict_mode.app_rd_data_reg[117]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[117]\(63 downto 0), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 0) => \not_strict_mode.app_rd_data_reg[127]\(63 downto 0), + \out\(1 downto 0) => \out\(1 downto 0), + out_fifo(71 downto 0) => out_fifo(71 downto 0), + out_fifo_0(71 downto 0) => out_fifo_0(71 downto 0), + p_1_in => p_1_in, + phy_dout(0) => init_calib_complete, + pi_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec\, + pi_dqs_found_done_r1_reg => u_ddr3_infrastructure_n_14, + pll_locked => pll_locked, + po_cnt_dec => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec\, + po_cnt_dec_0 => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec\, + prbs_rdlvl_done_pulse => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse\, + \rd_ptr_reg[0]\ => rd_ptr(0), + \rd_ptr_reg[0]_0\ => \rd_ptr_reg[0]\, + \rd_ptr_reg[0]_1\ => \rd_ptr_reg[0]_0\, + \rd_ptr_reg[1]\ => rd_ptr(1), + \rd_ptr_reg[1]_0\ => \rd_ptr_reg[1]\, + \rd_ptr_reg[1]_1\ => \rd_ptr_reg[1]_0\, + \rd_ptr_reg[2]\ => rd_ptr(2), + \rd_ptr_reg[2]_0\ => \rd_ptr_reg[2]\, + \rd_ptr_reg[2]_1\ => \rd_ptr_reg[2]_0\, + \rd_ptr_reg[3]\ => rd_ptr(3), + \rd_ptr_reg[3]_0\ => \rd_ptr_reg[3]\, + \rd_ptr_reg[3]_1\ => \rd_ptr_reg[3]_0\, + \rd_ptr_timing_reg[1]\(1 downto 0) => \rd_ptr_timing_reg[1]\(1 downto 0), + rdlvl_stg1_start_reg => u_memc_ui_top_std_n_56, + \read_fifo.head_r_reg[0]\(0) => rstdiv0_sync_r1, + ref_dll_lock => ref_dll_lock, + reset_reg_0 => u_ddr3_infrastructure_n_24, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]\ => u_ddr3_infrastructure_n_26, + \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]\ => u_ddr3_infrastructure_n_21, + rnk_config_valid_r_lcl_reg(1) => u_ddr3_infrastructure_n_16, + rnk_config_valid_r_lcl_reg(0) => u_ddr3_infrastructure_n_17, + samp_edge_cnt0_en_r => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r\, + \samp_edge_cnt1_r_reg[0]\ => u_ddr3_infrastructure_n_33, + sync_pulse => sync_pulse, + \tap_cnt_cpt_r_reg[5]\(0) => \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0\, + \wait_cnt_r_reg[0]\(0) => u_ddr3_infrastructure_n_30, + \wait_cnt_r_reg[0]_0\(0) => u_ddr3_infrastructure_n_34, + wl_edge_detect_valid_r_reg(0) => u_ddr3_infrastructure_n_10, + wr_en => wr_en, + wr_en_2 => wr_en_2, + wr_en_3 => wr_en_3, + \wr_ptr_reg[0]\ => wr_ptr(0), + \wr_ptr_reg[0]_0\ => wr_ptr_1(0), + \wr_ptr_reg[1]\ => wr_ptr(1), + \wr_ptr_reg[1]_0\ => wr_ptr_1(1), + \wr_ptr_reg[3]\(3 downto 0) => Q(3 downto 0), + \wr_ptr_reg[3]_0\(3 downto 0) => \wr_ptr_reg[3]\(3 downto 0), + \wr_ptr_reg[3]_1\(3 downto 0) => \wr_ptr_reg[3]_0\(3 downto 0), + \write_buffer.wr_buf_out_data_reg[117]\(71 downto 0) => \write_buffer.wr_buf_out_data_reg[117]\(71 downto 0), + \write_buffer.wr_buf_out_data_reg[127]\(71 downto 0) => \write_buffer.wr_buf_out_data_reg[127]\(71 downto 0), + \zq_cntrl.zq_request_logic.zq_request_r_reg\ => u_ddr3_infrastructure_n_19 + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity ddr3 is + port ( + ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); + ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr3_ras_n : out STD_LOGIC; + ddr3_cas_n : out STD_LOGIC; + ddr3_we_n : out STD_LOGIC; + ddr3_reset_n : out STD_LOGIC; + ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + sys_clk_i : in STD_LOGIC; + clk_ref_i : in STD_LOGIC; + app_addr : in STD_LOGIC_VECTOR ( 28 downto 0 ); + app_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 ); + app_en : in STD_LOGIC; + app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 ); + app_wdf_end : in STD_LOGIC; + app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + app_wdf_wren : in STD_LOGIC; + app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 ); + app_rd_data_end : out STD_LOGIC; + app_rd_data_valid : out STD_LOGIC; + app_rdy : out STD_LOGIC; + app_wdf_rdy : out STD_LOGIC; + app_sr_req : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + app_zq_req : in STD_LOGIC; + app_sr_active : out STD_LOGIC; + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + ui_clk : out STD_LOGIC; + ui_clk_sync_rst : out STD_LOGIC; + init_calib_complete : out STD_LOGIC; + device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 ); + device_temp : out STD_LOGIC_VECTOR ( 11 downto 0 ); + sys_rst : in STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of ddr3 : entity is true; +end ddr3; + +architecture STRUCTURE of ddr3 is + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\ : STD_LOGIC; + signal \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\ : STD_LOGIC; + signal u_ddr3_mig_n_10 : STD_LOGIC; + signal u_ddr3_mig_n_100 : STD_LOGIC; + signal u_ddr3_mig_n_11 : STD_LOGIC; + signal u_ddr3_mig_n_12 : STD_LOGIC; + signal u_ddr3_mig_n_13 : STD_LOGIC; + signal u_ddr3_mig_n_144 : STD_LOGIC; + signal u_ddr3_mig_n_145 : STD_LOGIC; + signal u_ddr3_mig_n_146 : STD_LOGIC; + signal u_ddr3_mig_n_147 : STD_LOGIC; + signal u_ddr3_mig_n_148 : STD_LOGIC; + signal u_ddr3_mig_n_149 : STD_LOGIC; + signal u_ddr3_mig_n_150 : STD_LOGIC; + signal u_ddr3_mig_n_151 : STD_LOGIC; + signal u_ddr3_mig_n_17 : STD_LOGIC; + signal u_ddr3_mig_n_18 : STD_LOGIC; + signal u_ddr3_mig_n_19 : STD_LOGIC; + signal u_ddr3_mig_n_20 : STD_LOGIC; + signal u_ddr3_mig_n_232 : STD_LOGIC; + signal u_ddr3_mig_n_233 : STD_LOGIC; + signal u_ddr3_mig_n_234 : STD_LOGIC; + signal u_ddr3_mig_n_235 : STD_LOGIC; + signal u_ddr3_mig_n_236 : STD_LOGIC; + signal u_ddr3_mig_n_237 : STD_LOGIC; + signal u_ddr3_mig_n_238 : STD_LOGIC; + signal u_ddr3_mig_n_239 : STD_LOGIC; + signal u_ddr3_mig_n_65 : STD_LOGIC; + signal u_ddr3_mig_n_67 : STD_LOGIC; + signal u_ddr3_mig_n_69 : STD_LOGIC; + signal u_ddr3_mig_n_73 : STD_LOGIC; + signal u_ddr3_mig_n_77 : STD_LOGIC; + signal u_ddr3_mig_n_79 : STD_LOGIC; + signal u_ddr3_mig_n_81 : STD_LOGIC; + signal u_ddr3_mig_n_85 : STD_LOGIC; + signal u_ddr3_mig_n_89 : STD_LOGIC; + signal u_ddr3_mig_n_93 : STD_LOGIC; + signal u_ddr3_mig_n_95 : STD_LOGIC; + signal u_ddr3_mig_n_96 : STD_LOGIC; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\ : STD_LOGIC_VECTOR ( 40 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\ : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke\ : STD_LOGIC_VECTOR ( 3 to 3 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt\ : STD_LOGIC_VECTOR ( 0 to 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n\ : STD_LOGIC_VECTOR ( 1 to 1 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\ : STD_LOGIC_VECTOR ( 127 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\ : STD_LOGIC_VECTOR ( 75 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT : string; + attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "50"; + attribute RTL_MAX_FANOUT : string; + attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "found"; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "40"; + attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "found"; + attribute syn_maxfan : string; + attribute syn_maxfan of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "10"; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\ : STD_LOGIC; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\ : STD_LOGIC_VECTOR ( 79 downto 8 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "50"; + attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "found"; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\ : STD_LOGIC_VECTOR ( 79 downto 6 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "40"; + attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "found"; + attribute syn_maxfan of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ : signal is "10"; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\ : STD_LOGIC; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\ : STD_LOGIC_VECTOR ( 79 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : STD_LOGIC; + attribute MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "50"; + attribute RTL_MAX_FANOUT of \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ : signal is "found"; + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\ : STD_LOGIC_VECTOR ( 79 downto 0 ); + signal \^ui_clk\ : STD_LOGIC; + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute METHODOLOGY_DRC_VIOS : string; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is ""; + attribute RTL_RAM_BITS : integer; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 720; + attribute RTL_RAM_NAME : string; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE : string; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "RAM_SDP"; + attribute ram_addr_begin : integer; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0; + attribute ram_addr_end : integer; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 8; + attribute ram_offset : integer; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0; + attribute ram_slice_begin : integer; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0; + attribute ram_slice_end : integer; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 5; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 12; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 17; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 18; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 23; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 24; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 29; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 30; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 36; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 41; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 42; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 47; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 48; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 53; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 54; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 59; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 60; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 65; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 66; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 71; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 6; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 11; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 8; + attribute ram_offset of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 72; + attribute ram_slice_end of \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 77; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 12; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 17; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 18; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 23; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 24; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\ : label is 29; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 30; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 36; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 41; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 42; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 47; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 48; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 53; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 54; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 59; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 60; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 65; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 66; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 71; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 6; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 11; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 72; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 77; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 3; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 78; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 79; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 12; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 17; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 18; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 23; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 24; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\ : label is 29; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 30; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 36; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 41; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 42; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 47; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 48; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 53; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 54; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 59; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 60; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 65; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 66; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 71; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 6; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 11; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 72; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 77; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 8; + attribute ram_offset of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 78; + attribute ram_slice_end of \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 79; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 0; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\ : label is 5; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 12; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\ : label is 17; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 18; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\ : label is 23; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 30; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 36; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\ : label is 41; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 42; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\ : label is 47; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 48; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\ : label is 53; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 54; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\ : label is 59; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 60; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\ : label is 65; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 66; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\ : label is 71; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 6; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\ : label is 11; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 72; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\ : label is 77; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 320; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 3; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 78; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\ : label is 79; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 0; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\ : label is 5; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 12; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\ : label is 17; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 18; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\ : label is 23; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 30; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\ : label is 35; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 36; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\ : label is 41; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 42; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\ : label is 47; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 48; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\ : label is 53; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 54; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\ : label is 59; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 60; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\ : label is 65; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 66; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\ : label is 71; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 6; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\ : label is 11; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 72; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\ : label is 77; + attribute METHODOLOGY_DRC_VIOS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is ""; + attribute RTL_RAM_BITS of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 720; + attribute RTL_RAM_NAME of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem"; + attribute RTL_RAM_TYPE of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is "RAM_SDP"; + attribute ram_addr_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0; + attribute ram_addr_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 8; + attribute ram_offset of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 0; + attribute ram_slice_begin of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 78; + attribute ram_slice_end of \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\ : label is 79; +begin + ui_clk <= \^ui_clk\; +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(18), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(3), + DIB(1) => u_ddr3_mig_n_100, + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(33), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(1 downto 0), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(3 downto 2), + DOC(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n\(1), + DIC(0) => u_ddr3_mig_n_95, + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(17 downto 16), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => '1', + DIA(0) => u_ddr3_mig_n_93, + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(19 downto 18), + DOB(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(5), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(2), + DIB(1) => u_ddr3_mig_n_89, + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(8), + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(25 downto 24), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(27 downto 26), + DOC(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(20), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(5), + DIC(1) => u_ddr3_mig_n_85, + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(35), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(33 downto 32), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(35 downto 34), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(15), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(41 downto 40), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => u_ddr3_mig_n_81, + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(30), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke\(3), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke\(3), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke\(3), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke\(3), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(43 downto 42), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(45 downto 44), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(47 downto 46), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n\(1), + DIA(0) => u_ddr3_mig_n_79, + DIB(1) => '1', + DIB(0) => u_ddr3_mig_n_77, + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(4), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(1), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(49 downto 48), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(51 downto 50), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(53 downto 52), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => u_ddr3_mig_n_73, + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(7), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(3), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(0), + DIC(1) => u_ddr3_mig_n_69, + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(6), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(55 downto 54), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(57 downto 56), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(59 downto 58), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1 downto 0) => B"00", + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt\(0), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt\(0), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(65 downto 64), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt\(0), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt\(0), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(67 downto 66), + DOB(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(25), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(10), + DIC(1) => u_ddr3_mig_n_96, + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(40), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED\(1 downto 0), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(9 downto 8), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(11 downto 10), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRB(4) => '0', + ADDRB(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRC(4) => '0', + ADDRC(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n\(1), + DIA(0) => u_ddr3_mig_n_67, + DIB(1) => '1', + DIB(0) => u_ddr3_mig_n_65, + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(73 downto 72), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(75 downto 74), + DOC(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(13 downto 12), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(15 downto 14), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(17 downto 16), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(13 downto 12), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(15 downto 14), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(17 downto 16), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(19 downto 18), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(21 downto 20), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(23 downto 22), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(19 downto 18), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(21 downto 20), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(23 downto 22), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(25 downto 24), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(27 downto 26), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(29 downto 28), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(25 downto 24), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(27 downto 26), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(29 downto 28), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(31 downto 30), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(33 downto 32), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(35 downto 34), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(31 downto 30), + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(37 downto 36), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(39 downto 38), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(41 downto 40), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_n_3\, + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(41 downto 40), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(43 downto 42), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(45 downto 44), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(47 downto 46), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(43 downto 42), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(45 downto 44), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(47 downto 46), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(49 downto 48), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(51 downto 50), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(53 downto 52), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(49 downto 48), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(51 downto 50), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(53 downto 52), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(55 downto 54), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(57 downto 56), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(59 downto 58), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(55 downto 54), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(57 downto 56), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(59 downto 58), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(61 downto 60), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(63 downto 62), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(65 downto 64), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(61 downto 60), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(63 downto 62), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(65 downto 64), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(67 downto 66), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(69 downto 68), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(71 downto 70), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(67 downto 66), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(69 downto 68), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(71 downto 70), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(7 downto 6), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(9 downto 8), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(11 downto 10), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1\, + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(9 downto 8), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(11 downto 10), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(73 downto 72), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(75 downto 74), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(77 downto 76), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(73 downto 72), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(75 downto 74), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(77 downto 76), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(79 downto 78), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(79 downto 78), + DOB(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(81), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(65), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(113), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(97), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(16), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(0), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(48), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(32), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(80), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(64), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(112), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(96), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(20), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(4), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(52), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(36), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(84), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(68), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(116), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(100), + DIB(1) => u_ddr3_mig_n_150, + DIB(0) => u_ddr3_mig_n_151, + DIC(1) => u_ddr3_mig_n_148, + DIC(0) => u_ddr3_mig_n_149, + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => u_ddr3_mig_n_146, + DIA(0) => u_ddr3_mig_n_147, + DIB(1) => u_ddr3_mig_n_144, + DIB(0) => u_ddr3_mig_n_145, + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(23), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(7), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(55), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(39), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(87), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(71), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(119), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(103), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(18), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(2), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(50), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(34), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(82), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(66), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(114), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(98), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(22), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(6), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(54), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(38), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(86), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(70), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(118), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(102), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(19), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(3), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(51), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(35), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(83), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(67), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(115), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(99), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(17), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(1), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(49), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(33), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED\(1 downto 0), + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(21), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(5), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(53), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(37), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(85), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(69), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\, + DOB(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\, + DOB(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\, + DOC(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\, + DOC(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_13, + ADDRA(2) => u_ddr3_mig_n_12, + ADDRA(1) => u_ddr3_mig_n_11, + ADDRA(0) => u_ddr3_mig_n_10, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_13, + ADDRB(2) => u_ddr3_mig_n_12, + ADDRB(1) => u_ddr3_mig_n_11, + ADDRB(0) => u_ddr3_mig_n_10, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_13, + ADDRC(2) => u_ddr3_mig_n_12, + ADDRC(1) => u_ddr3_mig_n_11, + ADDRC(0) => u_ddr3_mig_n_10, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(117), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(101), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\, + DOA(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\, + DOB(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(1 downto 0), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(3 downto 2), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(5 downto 4), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(1 downto 0), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(3 downto 2), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(5 downto 4), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(13 downto 12), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(15 downto 14), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(17 downto 16), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_3\, + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(17 downto 16), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(19 downto 18), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(21 downto 20), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(23 downto 22), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(19 downto 18), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(21 downto 20), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(23 downto 22), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(31 downto 30), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(33 downto 32), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(35 downto 34), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_n_1\, + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(33 downto 32), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(35 downto 34), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(37 downto 36), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(39 downto 38), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(41 downto 40), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(37 downto 36), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(39 downto 38), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(41 downto 40), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(43 downto 42), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(45 downto 44), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(47 downto 46), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(43 downto 42), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(45 downto 44), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(47 downto 46), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(49 downto 48), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(51 downto 50), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(53 downto 52), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(49 downto 48), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(51 downto 50), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(53 downto 52), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(55 downto 54), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(57 downto 56), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(59 downto 58), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(55 downto 54), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(57 downto 56), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(59 downto 58), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(61 downto 60), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(63 downto 62), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(65 downto 64), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(61 downto 60), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(63 downto 62), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(65 downto 64), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(67 downto 66), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(69 downto 68), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(71 downto 70), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(67 downto 66), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(69 downto 68), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(71 downto 70), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_66_71_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(7 downto 6), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(9 downto 8), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(11 downto 10), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(7 downto 6), + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(73 downto 72), + DIB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(75 downto 74), + DIC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(77 downto 76), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(73 downto 72), + DOB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(75 downto 74), + DOC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(77 downto 76), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4 downto 2) => B"000", + ADDRA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRB(4 downto 2) => B"000", + ADDRB(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRC(4 downto 2) => B"000", + ADDRC(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + ADDRD(4 downto 2) => B"000", + ADDRD(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + DIA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(79 downto 78), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(79 downto 78), + DOB(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(24), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(8), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(56), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(40), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(88), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(72), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => u_ddr3_mig_n_234, + DIA(0) => u_ddr3_mig_n_235, + DIB(1) => u_ddr3_mig_n_232, + DIB(0) => u_ddr3_mig_n_233, + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(26), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(10), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(58), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(42), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(90), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(74), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(122), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(106), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1 downto 0) => B"00", + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(27), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(11), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(59), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(43), + DID(1 downto 0) => B"00", + DOA(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOA_UNCONNECTED\(1 downto 0), + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(91), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(75), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(123), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(107), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(30), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(14), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(62), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(46), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(94), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(78), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(126), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(110), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(28), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(12), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(60), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(44), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(92), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(76), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(124), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(108), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(25), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(9), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(57), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(41), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(89), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(73), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(121), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(105), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(29), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(13), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(61), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(45), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(93), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(77), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(125), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(109), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(120), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(104), + DIB(1) => u_ddr3_mig_n_238, + DIB(0) => u_ddr3_mig_n_239, + DIC(1) => u_ddr3_mig_n_236, + DIC(0) => u_ddr3_mig_n_237, + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(31), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(15), + DIB(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(63), + DIB(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(47), + DIC(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(95), + DIC(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(79), + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\, + DOB(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\, + DOB(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\, + DOC(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\, + DOC(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\, + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79\: unisim.vcomponents.RAM32M + port map ( + ADDRA(4) => '0', + ADDRA(3) => u_ddr3_mig_n_20, + ADDRA(2) => u_ddr3_mig_n_19, + ADDRA(1) => u_ddr3_mig_n_18, + ADDRA(0) => u_ddr3_mig_n_17, + ADDRB(4) => '0', + ADDRB(3) => u_ddr3_mig_n_20, + ADDRB(2) => u_ddr3_mig_n_19, + ADDRB(1) => u_ddr3_mig_n_18, + ADDRB(0) => u_ddr3_mig_n_17, + ADDRC(4) => '0', + ADDRC(3) => u_ddr3_mig_n_20, + ADDRC(2) => u_ddr3_mig_n_19, + ADDRC(1) => u_ddr3_mig_n_18, + ADDRC(0) => u_ddr3_mig_n_17, + ADDRD(4) => '0', + ADDRD(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + DIA(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(127), + DIA(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(111), + DIB(1 downto 0) => B"00", + DIC(1 downto 0) => B"00", + DID(1 downto 0) => B"00", + DOA(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\, + DOA(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\, + DOB(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED\(1 downto 0), + DOC(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED\(1 downto 0), + DOD(1 downto 0) => \NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED\(1 downto 0), + WCLK => \^ui_clk\, + WE => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\ + ); +u_ddr3_mig: entity work.ddr3_ddr3_mig + port map ( + CLKB0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\, + CLKB0_4 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\, + Q(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + app_addr(27 downto 0) => app_addr(27 downto 0), + app_cmd(1 downto 0) => app_cmd(1 downto 0), + app_en => app_en, + app_rd_data(127 downto 0) => app_rd_data(127 downto 0), + app_rd_data_valid => app_rd_data_valid, + app_rdy_r_reg => app_rdy, + app_ref_ack => app_ref_ack, + app_ref_req => app_ref_req, + app_sr_active => app_sr_active, + app_sr_req => app_sr_req, + app_wdf_data(127 downto 0) => app_wdf_data(127 downto 0), + app_wdf_end => app_wdf_end, + app_wdf_mask(15 downto 0) => app_wdf_mask(15 downto 0), + app_wdf_rdy => app_wdf_rdy, + app_wdf_wren => app_wdf_wren, + app_zq_ack => app_zq_ack, + app_zq_req => app_zq_req, + clk_ref_i => clk_ref_i, + ddr3_addr(14 downto 0) => ddr3_addr(14 downto 0), + ddr3_ba(2 downto 0) => ddr3_ba(2 downto 0), + ddr3_cas_n => ddr3_cas_n, + ddr3_cke(0) => ddr3_cke(0), + ddr3_dm(1 downto 0) => ddr3_dm(1 downto 0), + ddr3_dq(15 downto 0) => ddr3_dq(15 downto 0), + ddr3_dqs_n(1 downto 0) => ddr3_dqs_n(1 downto 0), + ddr3_dqs_p(1 downto 0) => ddr3_dqs_p(1 downto 0), + ddr3_odt(0) => ddr3_odt(0), + ddr3_ras_n => ddr3_ras_n, + ddr3_reset_n => ddr3_reset_n, + ddr3_we_n => ddr3_we_n, + ddr_ck_out(1) => ddr3_ck_n(0), + ddr_ck_out(0) => ddr3_ck_p(0), + device_temp_i(11 downto 0) => device_temp_i(11 downto 0), + \device_temp_r_reg[11]\(11 downto 0) => device_temp(11 downto 0), + \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]\ => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\, + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]\(73 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r\(79 downto 6), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(73 downto 24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(79 downto 30), + \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0\(23 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r\(23 downto 0), + \gen_mmcm.mmcm_i\ => \^ui_clk\, + init_calib_complete => init_calib_complete, + iserdes_clk => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk\, + iserdes_clk_0 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk\, + mem_out(47 downto 44) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(75 downto 72), + mem_out(43 downto 40) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(67 downto 64), + mem_out(39 downto 20) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(59 downto 40), + mem_out(19 downto 16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(35 downto 32), + mem_out(15 downto 12) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(27 downto 24), + mem_out(11 downto 8) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(19 downto 16), + mem_out(7 downto 4) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(11 downto 8), + mem_out(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out\(3 downto 0), + \not_strict_mode.app_rd_data_end_reg\ => app_rd_data_end, + \not_strict_mode.app_rd_data_reg[117]\(63 downto 24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(79 downto 40), + \not_strict_mode.app_rd_data_reg[117]\(23 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out\(31 downto 8), + \not_strict_mode.app_rd_data_reg[127]\(63 downto 16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(79 downto 32), + \not_strict_mode.app_rd_data_reg[127]\(15 downto 8) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(23 downto 16), + \not_strict_mode.app_rd_data_reg[127]\(7 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out\(7 downto 0), + \out\(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + out_fifo(71) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\, + out_fifo(70) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\, + out_fifo(69) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\, + out_fifo(68) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\, + out_fifo(67) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\, + out_fifo(66) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\, + out_fifo(65) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\, + out_fifo(64) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\, + out_fifo(63) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\, + out_fifo(62) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\, + out_fifo(61) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\, + out_fifo(60) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\, + out_fifo(59) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\, + out_fifo(58) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\, + out_fifo(57) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\, + out_fifo(56) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\, + out_fifo(55) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\, + out_fifo(54) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\, + out_fifo(53) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\, + out_fifo(52) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\, + out_fifo(51) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\, + out_fifo(50) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\, + out_fifo(49) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\, + out_fifo(48) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\, + out_fifo(47) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\, + out_fifo(46) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\, + out_fifo(45) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\, + out_fifo(44) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\, + out_fifo(43) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\, + out_fifo(42) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\, + out_fifo(41) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\, + out_fifo(40) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\, + out_fifo(39) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\, + out_fifo(38) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\, + out_fifo(37) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\, + out_fifo(36) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\, + out_fifo(35) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\, + out_fifo(34) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\, + out_fifo(33) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\, + out_fifo(32) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\, + out_fifo(31) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\, + out_fifo(30) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\, + out_fifo(29) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\, + out_fifo(28) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\, + out_fifo(27) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\, + out_fifo(26) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\, + out_fifo(25) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\, + out_fifo(24) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\, + out_fifo(23) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0\, + out_fifo(22) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1\, + out_fifo(21) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4\, + out_fifo(20) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5\, + out_fifo(19) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2\, + out_fifo(18) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3\, + out_fifo(17) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0\, + out_fifo(16) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1\, + out_fifo(15) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\, + out_fifo(14) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\, + out_fifo(13) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\, + out_fifo(12) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\, + out_fifo(11) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\, + out_fifo(10) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\, + out_fifo(9) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\, + out_fifo(8) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\, + out_fifo(7) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\, + out_fifo(6) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\, + out_fifo(5) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\, + out_fifo(4) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\, + out_fifo(3) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\, + out_fifo(2) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\, + out_fifo(1) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\, + out_fifo(0) => \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\, + out_fifo_0(71) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0\, + out_fifo_0(70) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1\, + out_fifo_0(69) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4\, + out_fifo_0(68) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5\, + out_fifo_0(67) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2\, + out_fifo_0(66) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3\, + out_fifo_0(65) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0\, + out_fifo_0(64) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1\, + out_fifo_0(63) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4\, + out_fifo_0(62) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5\, + out_fifo_0(61) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2\, + out_fifo_0(60) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3\, + out_fifo_0(59) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0\, + out_fifo_0(58) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1\, + out_fifo_0(57) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4\, + out_fifo_0(56) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5\, + out_fifo_0(55) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2\, + out_fifo_0(54) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3\, + out_fifo_0(53) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0\, + out_fifo_0(52) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1\, + out_fifo_0(51) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4\, + out_fifo_0(50) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5\, + out_fifo_0(49) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2\, + out_fifo_0(48) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3\, + out_fifo_0(47) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0\, + out_fifo_0(46) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1\, + out_fifo_0(45) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4\, + out_fifo_0(44) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5\, + out_fifo_0(43) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2\, + out_fifo_0(42) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3\, + out_fifo_0(41) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0\, + out_fifo_0(40) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1\, + out_fifo_0(39) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4\, + out_fifo_0(38) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5\, + out_fifo_0(37) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2\, + out_fifo_0(36) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3\, + out_fifo_0(35) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0\, + out_fifo_0(34) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1\, + out_fifo_0(33) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4\, + out_fifo_0(32) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5\, + out_fifo_0(31) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2\, + out_fifo_0(30) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3\, + out_fifo_0(29) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0\, + out_fifo_0(28) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1\, + out_fifo_0(27) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4\, + out_fifo_0(26) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5\, + out_fifo_0(25) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2\, + out_fifo_0(24) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3\, + out_fifo_0(23) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4\, + out_fifo_0(22) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5\, + out_fifo_0(21) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2\, + out_fifo_0(20) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3\, + out_fifo_0(19) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0\, + out_fifo_0(18) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1\, + out_fifo_0(17) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4\, + out_fifo_0(16) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5\, + out_fifo_0(15) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2\, + out_fifo_0(14) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3\, + out_fifo_0(13) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0\, + out_fifo_0(12) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1\, + out_fifo_0(11) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4\, + out_fifo_0(10) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5\, + out_fifo_0(9) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2\, + out_fifo_0(8) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3\, + out_fifo_0(7) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0\, + out_fifo_0(6) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1\, + out_fifo_0(5) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4\, + out_fifo_0(4) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5\, + out_fifo_0(3) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2\, + out_fifo_0(2) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3\, + out_fifo_0(1) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0\, + out_fifo_0(0) => \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1\, + p_1_in => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en\, + phy_dout(38) => u_ddr3_mig_n_65, + phy_dout(37) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n\(1), + phy_dout(36) => u_ddr3_mig_n_67, + phy_dout(35) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_odt\(0), + phy_dout(34) => u_ddr3_mig_n_69, + phy_dout(33) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(6), + phy_dout(32) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(3), + phy_dout(31) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(0), + phy_dout(30) => u_ddr3_mig_n_73, + phy_dout(29) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(7), + phy_dout(28) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(4), + phy_dout(27) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(1), + phy_dout(26) => u_ddr3_mig_n_77, + phy_dout(25) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n\(1), + phy_dout(24) => u_ddr3_mig_n_79, + phy_dout(23) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke\(3), + phy_dout(22) => u_ddr3_mig_n_81, + phy_dout(21) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(30), + phy_dout(20) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(15), + phy_dout(19) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(0), + phy_dout(18) => u_ddr3_mig_n_85, + phy_dout(17) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(35), + phy_dout(16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(20), + phy_dout(15) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(5), + phy_dout(14) => u_ddr3_mig_n_89, + phy_dout(13) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(8), + phy_dout(12) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(5), + phy_dout(11) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank\(2), + phy_dout(10) => u_ddr3_mig_n_93, + phy_dout(9) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n\(1), + phy_dout(8) => u_ddr3_mig_n_95, + phy_dout(7) => u_ddr3_mig_n_96, + phy_dout(6) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(40), + phy_dout(5) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(25), + phy_dout(4) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(10), + phy_dout(3) => u_ddr3_mig_n_100, + phy_dout(2) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(33), + phy_dout(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(18), + phy_dout(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address\(3), + rd_ptr(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr\(3 downto 0), + \rd_ptr_reg[0]\ => u_ddr3_mig_n_10, + \rd_ptr_reg[0]_0\ => u_ddr3_mig_n_17, + \rd_ptr_reg[1]\ => u_ddr3_mig_n_11, + \rd_ptr_reg[1]_0\ => u_ddr3_mig_n_18, + \rd_ptr_reg[2]\ => u_ddr3_mig_n_12, + \rd_ptr_reg[2]_0\ => u_ddr3_mig_n_19, + \rd_ptr_reg[3]\ => u_ddr3_mig_n_13, + \rd_ptr_reg[3]_0\ => u_ddr3_mig_n_20, + \rd_ptr_timing_reg[1]\(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in\(1 downto 0), + sys_clk_i => sys_clk_i, + sys_rst => sys_rst, + ui_clk_sync_rst => ui_clk_sync_rst, + wr_en => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\, + wr_en_2 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\, + wr_en_3 => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en\, + wr_ptr(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + wr_ptr_1(1 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr\(1 downto 0), + \wr_ptr_reg[3]\(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + \wr_ptr_reg[3]_0\(3 downto 0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr\(3 downto 0), + \write_buffer.wr_buf_out_data_reg[117]\(71) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(117), + \write_buffer.wr_buf_out_data_reg[117]\(70) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(101), + \write_buffer.wr_buf_out_data_reg[117]\(69) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(85), + \write_buffer.wr_buf_out_data_reg[117]\(68) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(69), + \write_buffer.wr_buf_out_data_reg[117]\(67) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(53), + \write_buffer.wr_buf_out_data_reg[117]\(66) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(37), + \write_buffer.wr_buf_out_data_reg[117]\(65) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(21), + \write_buffer.wr_buf_out_data_reg[117]\(64) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(5), + \write_buffer.wr_buf_out_data_reg[117]\(63) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(115), + \write_buffer.wr_buf_out_data_reg[117]\(62) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(99), + \write_buffer.wr_buf_out_data_reg[117]\(61) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(83), + \write_buffer.wr_buf_out_data_reg[117]\(60) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(67), + \write_buffer.wr_buf_out_data_reg[117]\(59) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(51), + \write_buffer.wr_buf_out_data_reg[117]\(58) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(35), + \write_buffer.wr_buf_out_data_reg[117]\(57) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(19), + \write_buffer.wr_buf_out_data_reg[117]\(56) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(3), + \write_buffer.wr_buf_out_data_reg[117]\(55) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(118), + \write_buffer.wr_buf_out_data_reg[117]\(54) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(102), + \write_buffer.wr_buf_out_data_reg[117]\(53) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(86), + \write_buffer.wr_buf_out_data_reg[117]\(52) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(70), + \write_buffer.wr_buf_out_data_reg[117]\(51) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(54), + \write_buffer.wr_buf_out_data_reg[117]\(50) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(38), + \write_buffer.wr_buf_out_data_reg[117]\(49) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(22), + \write_buffer.wr_buf_out_data_reg[117]\(48) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(6), + \write_buffer.wr_buf_out_data_reg[117]\(47) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(114), + \write_buffer.wr_buf_out_data_reg[117]\(46) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(98), + \write_buffer.wr_buf_out_data_reg[117]\(45) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(82), + \write_buffer.wr_buf_out_data_reg[117]\(44) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(66), + \write_buffer.wr_buf_out_data_reg[117]\(43) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(50), + \write_buffer.wr_buf_out_data_reg[117]\(42) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(34), + \write_buffer.wr_buf_out_data_reg[117]\(41) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(18), + \write_buffer.wr_buf_out_data_reg[117]\(40) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(2), + \write_buffer.wr_buf_out_data_reg[117]\(39) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(119), + \write_buffer.wr_buf_out_data_reg[117]\(38) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(103), + \write_buffer.wr_buf_out_data_reg[117]\(37) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(87), + \write_buffer.wr_buf_out_data_reg[117]\(36) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(71), + \write_buffer.wr_buf_out_data_reg[117]\(35) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(55), + \write_buffer.wr_buf_out_data_reg[117]\(34) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(39), + \write_buffer.wr_buf_out_data_reg[117]\(33) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(23), + \write_buffer.wr_buf_out_data_reg[117]\(32) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(7), + \write_buffer.wr_buf_out_data_reg[117]\(31) => u_ddr3_mig_n_144, + \write_buffer.wr_buf_out_data_reg[117]\(30) => u_ddr3_mig_n_145, + \write_buffer.wr_buf_out_data_reg[117]\(29) => u_ddr3_mig_n_146, + \write_buffer.wr_buf_out_data_reg[117]\(28) => u_ddr3_mig_n_147, + \write_buffer.wr_buf_out_data_reg[117]\(27) => u_ddr3_mig_n_148, + \write_buffer.wr_buf_out_data_reg[117]\(26) => u_ddr3_mig_n_149, + \write_buffer.wr_buf_out_data_reg[117]\(25) => u_ddr3_mig_n_150, + \write_buffer.wr_buf_out_data_reg[117]\(24) => u_ddr3_mig_n_151, + \write_buffer.wr_buf_out_data_reg[117]\(23) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(116), + \write_buffer.wr_buf_out_data_reg[117]\(22) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(100), + \write_buffer.wr_buf_out_data_reg[117]\(21) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(84), + \write_buffer.wr_buf_out_data_reg[117]\(20) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(68), + \write_buffer.wr_buf_out_data_reg[117]\(19) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(52), + \write_buffer.wr_buf_out_data_reg[117]\(18) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(36), + \write_buffer.wr_buf_out_data_reg[117]\(17) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(20), + \write_buffer.wr_buf_out_data_reg[117]\(16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(4), + \write_buffer.wr_buf_out_data_reg[117]\(15) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(112), + \write_buffer.wr_buf_out_data_reg[117]\(14) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(96), + \write_buffer.wr_buf_out_data_reg[117]\(13) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(80), + \write_buffer.wr_buf_out_data_reg[117]\(12) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(64), + \write_buffer.wr_buf_out_data_reg[117]\(11) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(48), + \write_buffer.wr_buf_out_data_reg[117]\(10) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(32), + \write_buffer.wr_buf_out_data_reg[117]\(9) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(16), + \write_buffer.wr_buf_out_data_reg[117]\(8) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(0), + \write_buffer.wr_buf_out_data_reg[117]\(7) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(113), + \write_buffer.wr_buf_out_data_reg[117]\(6) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(97), + \write_buffer.wr_buf_out_data_reg[117]\(5) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(81), + \write_buffer.wr_buf_out_data_reg[117]\(4) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(65), + \write_buffer.wr_buf_out_data_reg[117]\(3) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(49), + \write_buffer.wr_buf_out_data_reg[117]\(2) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(33), + \write_buffer.wr_buf_out_data_reg[117]\(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(17), + \write_buffer.wr_buf_out_data_reg[117]\(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(1), + \write_buffer.wr_buf_out_data_reg[127]\(71) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(127), + \write_buffer.wr_buf_out_data_reg[127]\(70) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(111), + \write_buffer.wr_buf_out_data_reg[127]\(69) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(95), + \write_buffer.wr_buf_out_data_reg[127]\(68) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(79), + \write_buffer.wr_buf_out_data_reg[127]\(67) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(63), + \write_buffer.wr_buf_out_data_reg[127]\(66) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(47), + \write_buffer.wr_buf_out_data_reg[127]\(65) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(31), + \write_buffer.wr_buf_out_data_reg[127]\(64) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(15), + \write_buffer.wr_buf_out_data_reg[127]\(63) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(125), + \write_buffer.wr_buf_out_data_reg[127]\(62) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(109), + \write_buffer.wr_buf_out_data_reg[127]\(61) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(93), + \write_buffer.wr_buf_out_data_reg[127]\(60) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(77), + \write_buffer.wr_buf_out_data_reg[127]\(59) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(61), + \write_buffer.wr_buf_out_data_reg[127]\(58) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(45), + \write_buffer.wr_buf_out_data_reg[127]\(57) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(29), + \write_buffer.wr_buf_out_data_reg[127]\(56) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(13), + \write_buffer.wr_buf_out_data_reg[127]\(55) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(121), + \write_buffer.wr_buf_out_data_reg[127]\(54) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(105), + \write_buffer.wr_buf_out_data_reg[127]\(53) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(89), + \write_buffer.wr_buf_out_data_reg[127]\(52) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(73), + \write_buffer.wr_buf_out_data_reg[127]\(51) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(57), + \write_buffer.wr_buf_out_data_reg[127]\(50) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(41), + \write_buffer.wr_buf_out_data_reg[127]\(49) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(25), + \write_buffer.wr_buf_out_data_reg[127]\(48) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(9), + \write_buffer.wr_buf_out_data_reg[127]\(47) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(124), + \write_buffer.wr_buf_out_data_reg[127]\(46) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(108), + \write_buffer.wr_buf_out_data_reg[127]\(45) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(92), + \write_buffer.wr_buf_out_data_reg[127]\(44) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(76), + \write_buffer.wr_buf_out_data_reg[127]\(43) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(60), + \write_buffer.wr_buf_out_data_reg[127]\(42) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(44), + \write_buffer.wr_buf_out_data_reg[127]\(41) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(28), + \write_buffer.wr_buf_out_data_reg[127]\(40) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(12), + \write_buffer.wr_buf_out_data_reg[127]\(39) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(126), + \write_buffer.wr_buf_out_data_reg[127]\(38) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(110), + \write_buffer.wr_buf_out_data_reg[127]\(37) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(94), + \write_buffer.wr_buf_out_data_reg[127]\(36) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(78), + \write_buffer.wr_buf_out_data_reg[127]\(35) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(62), + \write_buffer.wr_buf_out_data_reg[127]\(34) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(46), + \write_buffer.wr_buf_out_data_reg[127]\(33) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(30), + \write_buffer.wr_buf_out_data_reg[127]\(32) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(14), + \write_buffer.wr_buf_out_data_reg[127]\(31) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(123), + \write_buffer.wr_buf_out_data_reg[127]\(30) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(107), + \write_buffer.wr_buf_out_data_reg[127]\(29) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(91), + \write_buffer.wr_buf_out_data_reg[127]\(28) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(75), + \write_buffer.wr_buf_out_data_reg[127]\(27) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(59), + \write_buffer.wr_buf_out_data_reg[127]\(26) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(43), + \write_buffer.wr_buf_out_data_reg[127]\(25) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(27), + \write_buffer.wr_buf_out_data_reg[127]\(24) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(11), + \write_buffer.wr_buf_out_data_reg[127]\(23) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(122), + \write_buffer.wr_buf_out_data_reg[127]\(22) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(106), + \write_buffer.wr_buf_out_data_reg[127]\(21) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(90), + \write_buffer.wr_buf_out_data_reg[127]\(20) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(74), + \write_buffer.wr_buf_out_data_reg[127]\(19) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(58), + \write_buffer.wr_buf_out_data_reg[127]\(18) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(42), + \write_buffer.wr_buf_out_data_reg[127]\(17) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(26), + \write_buffer.wr_buf_out_data_reg[127]\(16) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(10), + \write_buffer.wr_buf_out_data_reg[127]\(15) => u_ddr3_mig_n_232, + \write_buffer.wr_buf_out_data_reg[127]\(14) => u_ddr3_mig_n_233, + \write_buffer.wr_buf_out_data_reg[127]\(13) => u_ddr3_mig_n_234, + \write_buffer.wr_buf_out_data_reg[127]\(12) => u_ddr3_mig_n_235, + \write_buffer.wr_buf_out_data_reg[127]\(11) => u_ddr3_mig_n_236, + \write_buffer.wr_buf_out_data_reg[127]\(10) => u_ddr3_mig_n_237, + \write_buffer.wr_buf_out_data_reg[127]\(9) => u_ddr3_mig_n_238, + \write_buffer.wr_buf_out_data_reg[127]\(8) => u_ddr3_mig_n_239, + \write_buffer.wr_buf_out_data_reg[127]\(7) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(120), + \write_buffer.wr_buf_out_data_reg[127]\(6) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(104), + \write_buffer.wr_buf_out_data_reg[127]\(5) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(88), + \write_buffer.wr_buf_out_data_reg[127]\(4) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(72), + \write_buffer.wr_buf_out_data_reg[127]\(3) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(56), + \write_buffer.wr_buf_out_data_reg[127]\(2) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(40), + \write_buffer.wr_buf_out_data_reg[127]\(1) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(24), + \write_buffer.wr_buf_out_data_reg[127]\(0) => \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata\(8) + ); +end STRUCTURE; diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.v new file mode 100644 index 0000000..fa15a67 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.v @@ -0,0 +1,62 @@ +// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +// Date : Wed Feb 5 18:54:41 2025 +// Host : Win102023HEYRFQ running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub j:/work/HY/Xilinx/A704/V1.0/PRJ/RTL/ddr_ctrl/ddr3/ddr3_stub.v +// Design : ddr3 +// Purpose : Stub declaration of top-level module interface +// Device : xc7a35tfgg484-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module ddr3(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr, + ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke, + ddr3_dm, ddr3_odt, sys_clk_i, clk_ref_i, app_addr, app_cmd, app_en, app_wdf_data, app_wdf_end, + app_wdf_mask, app_wdf_wren, app_rd_data, app_rd_data_end, app_rd_data_valid, app_rdy, + app_wdf_rdy, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, + ui_clk, ui_clk_sync_rst, init_calib_complete, device_temp_i, device_temp, sys_rst) +/* synthesis syn_black_box black_box_pad_pin="ddr3_dq[15:0],ddr3_dqs_n[1:0],ddr3_dqs_p[1:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_dm[1:0],ddr3_odt[0:0],sys_clk_i,clk_ref_i,app_addr[28:0],app_cmd[2:0],app_en,app_wdf_data[127:0],app_wdf_end,app_wdf_mask[15:0],app_wdf_wren,app_rd_data[127:0],app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,ui_clk,ui_clk_sync_rst,init_calib_complete,device_temp_i[11:0],device_temp[11:0],sys_rst" */; + inout [15:0]ddr3_dq; + inout [1:0]ddr3_dqs_n; + inout [1:0]ddr3_dqs_p; + output [14:0]ddr3_addr; + output [2:0]ddr3_ba; + output ddr3_ras_n; + output ddr3_cas_n; + output ddr3_we_n; + output ddr3_reset_n; + output [0:0]ddr3_ck_p; + output [0:0]ddr3_ck_n; + output [0:0]ddr3_cke; + output [1:0]ddr3_dm; + output [0:0]ddr3_odt; + input sys_clk_i; + input clk_ref_i; + input [28:0]app_addr; + input [2:0]app_cmd; + input app_en; + input [127:0]app_wdf_data; + input app_wdf_end; + input [15:0]app_wdf_mask; + input app_wdf_wren; + output [127:0]app_rd_data; + output app_rd_data_end; + output app_rd_data_valid; + output app_rdy; + output app_wdf_rdy; + input app_sr_req; + input app_ref_req; + input app_zq_req; + output app_sr_active; + output app_ref_ack; + output app_zq_ack; + output ui_clk; + output ui_clk_sync_rst; + output init_calib_complete; + input [11:0]device_temp_i; + output [11:0]device_temp; + input sys_rst; +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.vhdl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.vhdl new file mode 100644 index 0000000..504a31b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_stub.vhdl @@ -0,0 +1,66 @@ +-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 +-- Date : Wed Feb 5 18:54:41 2025 +-- Host : Win102023HEYRFQ running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub j:/work/HY/Xilinx/A704/V1.0/PRJ/RTL/ddr_ctrl/ddr3/ddr3_stub.vhdl +-- Design : ddr3 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7a35tfgg484-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ddr3 is + Port ( + ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); + ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_addr : out STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr3_ras_n : out STD_LOGIC; + ddr3_cas_n : out STD_LOGIC; + ddr3_we_n : out STD_LOGIC; + ddr3_reset_n : out STD_LOGIC; + ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); + ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); + ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); + sys_clk_i : in STD_LOGIC; + clk_ref_i : in STD_LOGIC; + app_addr : in STD_LOGIC_VECTOR ( 28 downto 0 ); + app_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 ); + app_en : in STD_LOGIC; + app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 ); + app_wdf_end : in STD_LOGIC; + app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); + app_wdf_wren : in STD_LOGIC; + app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 ); + app_rd_data_end : out STD_LOGIC; + app_rd_data_valid : out STD_LOGIC; + app_rdy : out STD_LOGIC; + app_wdf_rdy : out STD_LOGIC; + app_sr_req : in STD_LOGIC; + app_ref_req : in STD_LOGIC; + app_zq_req : in STD_LOGIC; + app_sr_active : out STD_LOGIC; + app_ref_ack : out STD_LOGIC; + app_zq_ack : out STD_LOGIC; + ui_clk : out STD_LOGIC; + ui_clk_sync_rst : out STD_LOGIC; + init_calib_complete : out STD_LOGIC; + device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 ); + device_temp : out STD_LOGIC_VECTOR ( 11 downto 0 ); + sys_rst : in STD_LOGIC + ); + +end ddr3; + +architecture stub of ddr3 is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "ddr3_dq[15:0],ddr3_dqs_n[1:0],ddr3_dqs_p[1:0],ddr3_addr[14:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_dm[1:0],ddr3_odt[0:0],sys_clk_i,clk_ref_i,app_addr[28:0],app_cmd[2:0],app_en,app_wdf_data[127:0],app_wdf_end,app_wdf_mask[15:0],app_wdf_wren,app_rd_data[127:0],app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,ui_clk,ui_clk_sync_rst,init_calib_complete,device_temp_i[11:0],device_temp[11:0],sys_rst"; +begin +end; diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_xmdf.tcl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_xmdf.tcl new file mode 100644 index 0000000..c70cb71 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/ddr3_xmdf.tcl @@ -0,0 +1,319 @@ +# The package naming convention is _xmdf +package provide ddr3_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::ddr3_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::ddr3_xmdf::xmdfInit { instance } { + # Variable containing name of library into which module is compiled + # Recommendation: + # Required + utilities_xmdf::xmdfSetData $instance Module Attributes Name ddr3 +} +# ::ddr3_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::ddr3_xmdf::xmdfApplyParams { instance } { + +set fcount 0 + # Array containing libraries that are assumed to exist + # Examples include unisim and xilinxcorelib + # Optional + # In this example, we assume that the unisim library will + # be magically + # available to the simulation and synthesis tool + utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library + utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim + incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ddr3.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ddr3_mig.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_buf.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_dec_fix.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_gen.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ecc/mig_7series_v4_2_ecc_merge_enc.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ecc/mig_7series_v4_2_fi_xor.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_std.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + 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+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_skip_calib_tap.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/constraints/ddr3.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ddr3 +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr3/user_design/constraints/ddr3.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ddr3 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_a.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_a.prj new file mode 100644 index 0000000..48d4cc5 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_a.prj @@ -0,0 +1,130 @@ + + + + ddr3 + 1 + 1 + OFF + 1024 + ON + Disabled + xc7a75t-fgg484/-2 + 2.4 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + 7a/xc7a35t-fgg484 + 7a/xc7a50t-fgg484 + 7a/xc7a100t-fgg484 + + + DDR3_SDRAM/Components/MT41J128M16XX-15E + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_b.prj b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_b.prj new file mode 100644 index 0000000..c658547 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/mig_b.prj @@ -0,0 +1,155 @@ + + + + + + + + ddr3 + + 1 + + 1 + + OFF + + 1024 + + ON + + Disabled + + xc7a35t-fgg484/-2 + + 4.2 + + No Buffer + + No Buffer + + ACTIVE LOW + + FALSE + + 1 + + 50 Ohms + + 0 + + + 7a/xc7a50t-fgg484 + 7a/xc7a75t-fgg484 + 7a/xc7a100t-fgg484 + 7a/xc7a15t-fgg484 + + + + DDR3_SDRAM/Components/MT41K256M16XX-125 + 3000 + 1.8V + 4:1 + 333.333 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Disable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.in b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.in new file mode 100644 index 0000000..88b141d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.in @@ -0,0 +1,24 @@ +SET_FLAG MODE BATCH +SET_FLAG STANDALONE_MODE TRUE +SET_PREFERENCE ipi_mode no +SET_PREFERENCE is_ip_locked false +SET_PREFERENCE devicefamily artix7 +SET_PREFERENCE device xc7a35t +SET_PREFERENCE speedgrade -2 +SET_PREFERENCE package fgg484 +SET_PREFERENCE verilogsim true +SET_PREFERENCE vhdlsim false +SET_PREFERENCE designentry Verilog +SET_PREFERENCE outputdirectory j:/work/HY/Xilinx/A704/V1.0/PRJ/RTL/ddr_ctrl/ddr3/_tmp/ +SET_PREFERENCE subworkingdirectory j:/work/HY/Xilinx/A704/V1.0/PRJ/RTL/ddr_ctrl/ddr3/_tmp/ +SET_PREFERENCE flowvendor Other +SET_PREFERENCE tool vivado +SET_PREFERENCE compnamestatus 0 +SET_PARAMETER component_name ddr3 +SET_PARAMETER xml_input_file J:/work/HY/Xilinx/A704/V1.0/PRJ/RTL/ddr_ctrl/ddr3/mig_b.prj +SET_PARAMETER data_dir_path e:/Vivado/Vivado/2020.2/data/ip/xilinx/mig_7series_v4_2 +SET_CORE_NAME Memory Interface Generator (MIG 7 Series) +SET_CORE_VERSION 4.2 +SET_CORE_VLNV xilinx.com:ip:mig_7series:4.2 +SET_CORE_PATH e:/Vivado/Vivado/2020.2/data/ip/xilinx/mig_7series_v4_2 +SET_CORE_DATASHEET e:/Vivado/Vivado/2020.2/data/ip/xilinx/mig_7series_v4_2/data/docs/ds176_7series_MIS.pdf diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.out b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.out new file mode 100644 index 0000000..49ac05a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/ddr3/xil_txt.out @@ -0,0 +1,4 @@ +SET_ERROR_CODE 0 +SET_XMDF_PATH ./ddr3_xmdf.tcl +SET_PARAMETER component_name ddr3 +SET_PARAMETER xml_input_file ./ddr3/mig.prj diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/example_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/example_top.v new file mode 100644 index 0000000..5bfb447 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/example_top.v @@ -0,0 +1,1324 @@ +//***************************************************************************** + +// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. + +// + +// This file contains confidential and proprietary information + +// of Xilinx, Inc. and is protected under U.S. and + +// international copyright and other intellectual property + +// laws. + +// + +// DISCLAIMER + +// This disclaimer is not a license and does not grant any + +// rights to the materials distributed herewith. Except as + +// otherwise provided in a valid license issued to you by + +// Xilinx, and to the maximum extent permitted by applicable + +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + +// (2) Xilinx shall not be liable (whether in contract or tort, + +// including negligence, or under any other theory of + +// liability) for any loss or damage of any kind or nature + +// related to, arising under or in connection with these + +// materials, including for any direct, or any indirect, + +// special, incidental, or consequential loss or damage + +// (including loss of data, profits, goodwill, or any type of + +// loss or damage suffered as a result of any action brought + +// by a third party) even if such damage or loss was + +// reasonably foreseeable or Xilinx had been advised of the + +// possibility of the same. + +// + +// CRITICAL APPLICATIONS + +// Xilinx products are not designed or intended to be fail- + +// safe, or for use in any application requiring fail-safe + +// performance, such as life-support or safety devices or + +// systems, Class III medical devices, nuclear facilities, + +// applications related to the deployment of airbags, or any + +// other applications that could lead to death, personal + +// injury, or severe property or environmental damage + +// (individually and collectively, "Critical + +// Applications"). Customer assumes the sole risk and + +// liability of any use of Xilinx products in Critical + +// Applications, subject only to applicable laws and + +// regulations governing limitations on product liability. + +// + +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + +// PART OF THIS FILE AT ALL TIMES. + +// + +//***************************************************************************** + +// ____ ____ + +// / /\/ / + +// /___/ \ / Vendor : Xilinx + +// \ \ \/ Version : 4.2 + +// \ \ Application : MIG + +// / / Filename : example_top.v + +// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ + +// \ \ / \ Date Created : Tue Sept 21 2010 + +// \___\/\___\ + +// + +// Device : 7 Series + +// Design Name : DDR3 SDRAM + +// Purpose : + +// Top-level module. This module serves as an example, + +// and allows the user to synthesize a self-contained design, + +// which they can be used to test their hardware. + +// In addition to the memory controller, the module instantiates: + +// 1. Synthesizable testbench - used to model user's backend logic + +// and generate different traffic patterns + +// Reference : + +// Revision History : + +//***************************************************************************** + + + +//`define SKIP_CALIB + +`timescale 1ps/1ps + + + +module example_top # + + ( + + + + //*************************************************************************** + + // Traffic Gen related parameters + + //*************************************************************************** + + parameter PORT_MODE = "BI_MODE", + + parameter DATA_MODE = 4'b0010, + + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", + + parameter EYE_TEST = "FALSE", + + // set EYE_TEST = "TRUE" to probe memory + + // signals. Traffic Generator will only + + // write to one single location and no + + // read transactions will be generated. + + parameter DATA_PATTERN = "DGEN_ALL", + + // For small devices, choose one only. + + // For large device, choose "DGEN_ALL" + + // "DGEN_HAMMER", "DGEN_WALKING1", + + // "DGEN_WALKING0","DGEN_ADDR"," + + // "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + + parameter CMD_PATTERN = "CGEN_ALL", + + // "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM", + + // "CGEN_SEQUENTIAL", "CGEN_ALL" + + parameter CMD_WDT = 'h3FF, + + parameter WR_WDT = 'h1FFF, + + parameter RD_WDT = 'h3FF, + + parameter SEL_VICTIM_LINE = 0, + + parameter BEGIN_ADDRESS = 32'h00000000, + + parameter END_ADDRESS = 32'h00ffffff, + + parameter PRBS_EADDR_MASK_POS = 32'hff000000, + + + + //*************************************************************************** + + // The following parameters refer to width of various ports + + //*************************************************************************** + + parameter CK_WIDTH = 1, + + // # of CK/CK# outputs to memory. + + parameter nCS_PER_RANK = 1, + + // # of unique CS outputs per rank for phy + + parameter CKE_WIDTH = 1, + + // # of CKE outputs to memory. + + parameter DM_WIDTH = 2, + + // # of DM (data mask) + + parameter ODT_WIDTH = 1, + + // # of ODT outputs to memory. + + parameter BANK_WIDTH = 3, + + // # of memory Bank Address bits. + + parameter COL_WIDTH = 10, + + // # of memory Column Address bits. + + parameter CS_WIDTH = 1, + + // # of unique CS outputs to memory. + + parameter DQ_WIDTH = 16, + + // # of DQ (data) + + parameter DQS_WIDTH = 2, + + parameter DQS_CNT_WIDTH = 1, + + // = ceil(log2(DQS_WIDTH)) + + parameter DRAM_WIDTH = 8, + + // # of DQ per DQS + + parameter ECC = "OFF", + + parameter ECC_TEST = "OFF", + + //parameter nBANK_MACHS = 4, + + parameter nBANK_MACHS = 4, + + parameter RANKS = 1, + + // # of Ranks. + + parameter ROW_WIDTH = 15, + + // # of memory Row Address bits. + + parameter ADDR_WIDTH = 29, + + // # = RANK_WIDTH + BANK_WIDTH + + // + ROW_WIDTH + COL_WIDTH; + + // Chip Select is always tied to low for + + // single rank devices + + + + //*************************************************************************** + + // The following parameters are mode register settings + + //*************************************************************************** + + parameter BURST_MODE = "8", + + // DDR3 SDRAM: + + // Burst Length (Mode Register 0). + + // # = "8", "4", "OTF". + + // DDR2 SDRAM: + + // Burst Length (Mode Register). + + // # = "8", "4". + + + + + + //*************************************************************************** + + // The following parameters are multiplier and divisor factors for PLLE2. + + // Based on the selected design frequency these parameters vary. + + //*************************************************************************** + + parameter CLKIN_PERIOD = 3000, + + // Input Clock Period + + parameter CLKFBOUT_MULT = 4, + + // write PLL VCO multiplier + + parameter DIVCLK_DIVIDE = 1, + + // write PLL VCO divisor + + parameter CLKOUT0_PHASE = 0.0, + + // Phase for PLL output clock (CLKOUT0) + + parameter CLKOUT0_DIVIDE = 2, + + // VCO output divisor for PLL output clock (CLKOUT0) + + parameter CLKOUT1_DIVIDE = 4, + + // VCO output divisor for PLL output clock (CLKOUT1) + + parameter CLKOUT2_DIVIDE = 64, + + // VCO output divisor for PLL output clock (CLKOUT2) + + parameter CLKOUT3_DIVIDE = 16, + + // VCO output divisor for PLL output clock (CLKOUT3) + + parameter MMCM_VCO = 666, + + // Max Freq (MHz) of MMCM VCO + + parameter MMCM_MULT_F = 8, + + // write MMCM VCO multiplier + + parameter MMCM_DIVCLK_DIVIDE = 1, + + // write MMCM VCO divisor + + + + //*************************************************************************** + + // Simulation parameters + + //*************************************************************************** + + parameter SIMULATION = "FALSE", + + // Should be TRUE during design simulations and + + // FALSE during implementations + + + + //*************************************************************************** + + // IODELAY and PHY related parameters + + //*************************************************************************** + + parameter TCQ = 100, + + + + parameter DRAM_TYPE = "DDR3", + + + + + + //*************************************************************************** + + // System clock frequency parameters + + //*************************************************************************** + + parameter nCK_PER_CLK = 4, + + // # of memory CKs per fabric CLK + + + + + + + + //*************************************************************************** + + // Debug parameters + + //*************************************************************************** + + parameter DEBUG_PORT = "OFF", + + // # = "ON" Enable debug signals/controls. + + // = "OFF" Disable debug signals/controls. + + + + parameter RST_ACT_LOW = 1 + + // =1 for active low reset, + + // =0 for active high. + + ) + + ( + + + + // Inouts + + inout [15:0] ddr3_dq, + + inout [1:0] ddr3_dqs_n, + + inout [1:0] ddr3_dqs_p, + + + + // Outputs + + output [14:0] ddr3_addr, + + output [2:0] ddr3_ba, + + output ddr3_ras_n, + + output ddr3_cas_n, + + output ddr3_we_n, + + output ddr3_reset_n, + + output [0:0] ddr3_ck_p, + + output [0:0] ddr3_ck_n, + + output [0:0] ddr3_cke, + + + + + + output [1:0] ddr3_dm, + + + + output [0:0] ddr3_odt, + + + + + + // Inputs + + + + // Single-ended system clock + + input sys_clk_i, + + + + // Single-ended iodelayctrl clk (reference clock) + + input clk_ref_i, + + + + output tg_compare_error, + + output init_calib_complete, + + input [11:0] device_temp_i, + + // The 12 MSB bits of the temperature sensor transfer + + // function need to be connected to this port. This port + + // will be synchronized w.r.t. to fabric clock internally. + + + + + + // System reset - Default polarity of sys_rst pin is Active Low. + + // System reset polarity will change based on the option + + // selected in GUI. + + input sys_rst, + output [47:0] tg_wr_data_counts, + output [47:0] tg_rd_data_counts + ); + + + +function integer clogb2 (input integer size); + + begin + + size = size - 1; + + for (clogb2=1; size>1; clogb2=clogb2+1) + + size = size >> 1; + + end + + endfunction // clogb2 + + + + function integer STR_TO_INT; + + input [7:0] in; + + begin + + if(in == "8") + + STR_TO_INT = 8; + + else if(in == "4") + + STR_TO_INT = 4; + + else + + STR_TO_INT = 0; + + end + + endfunction + + + + + + localparam DATA_WIDTH = 16; + + localparam RANK_WIDTH = clogb2(RANKS); + + localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH; + + localparam BURST_LENGTH = STR_TO_INT(BURST_MODE); + + localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH; + + localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8; + + + + //*************************************************************************** + + // Traffic Gen related parameters (derived) + + //*************************************************************************** + + localparam TG_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH) + + + BANK_WIDTH + ROW_WIDTH + COL_WIDTH; + + localparam MASK_SIZE = DATA_WIDTH/8; + + + + + + // Wire declarations + + + + wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err; + + wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err; + + wire [ADDR_WIDTH-1:0] app_addr; + + wire [2:0] app_cmd; + + wire app_en; + + wire app_rdy; + + wire [APP_DATA_WIDTH-1:0] app_rd_data; + + wire app_rd_data_end; + + wire app_rd_data_valid; + + wire [APP_DATA_WIDTH-1:0] app_wdf_data; + + wire app_wdf_end; + + wire [APP_MASK_WIDTH-1:0] app_wdf_mask; + + wire app_wdf_rdy; + + wire app_sr_active; + + wire app_ref_ack; + + wire app_zq_ack; + + wire app_wdf_wren; + + wire [(64+(2*APP_DATA_WIDTH))-1:0] error_status; + + wire [(PAYLOAD_WIDTH/8)-1:0] cumlative_dq_lane_error; + + wire mem_pattern_init_done; + + wire [47:0] tg_wr_data_counts; + + wire [47:0] tg_rd_data_counts; + + wire modify_enable_sel; + + wire [2:0] data_mode_manual_sel; + + wire [2:0] addr_mode_manual_sel; + + wire [APP_DATA_WIDTH-1:0] cmp_data; + + reg [63:0] cmp_data_r; + + wire cmp_data_valid; + + reg cmp_data_valid_r; + + wire cmp_error; + + wire [(PAYLOAD_WIDTH/8)-1:0] dq_error_bytelane_cmp; + + + + wire clk; + + wire rst; + + + + wire dbg_sel_pi_incdec; + + wire dbg_pi_f_inc; + + wire dbg_pi_f_dec; + + wire dbg_sel_po_incdec; + + wire dbg_po_f_inc; + + wire dbg_po_f_stg23_sel; + + wire dbg_po_f_dec; + + + + + + wire vio_modify_enable; + + wire [3:0] vio_data_mode_value; + + wire vio_pause_traffic; + + wire [2:0] vio_addr_mode_value; + + wire [3:0] vio_instr_mode_value; + + wire [1:0] vio_bl_mode_value; + + wire [9:0] vio_fixed_bl_value; + + wire [2:0] vio_fixed_instr_value; + + wire vio_data_mask_gen; + + wire vio_tg_rst; + + wire vio_dbg_sel_pi_incdec; + + wire vio_dbg_pi_f_inc; + + wire vio_dbg_pi_f_dec; + + wire vio_dbg_sel_po_incdec; + + wire vio_dbg_po_f_inc; + + wire vio_dbg_po_f_stg23_sel; + + wire vio_dbg_po_f_dec; + + + + wire [11:0] device_temp; + + + +`ifdef SKIP_CALIB + + // skip calibration wires + + wire calib_tap_req; + + reg calib_tap_load; + + reg [6:0] calib_tap_addr; + + reg [7:0] calib_tap_val; + + reg calib_tap_load_done; + +`endif + + + + + + + +//*************************************************************************** + + + + + + + + + + + + + + + +// Start of User Design top instance + +//*************************************************************************** + +// The User design is instantiated below. The memory interface ports are + +// connected to the top-level and the application interface ports are + +// connected to the traffic generator module. This provides a reference + +// for connecting the memory controller to system. + +//*************************************************************************** + + + + ddr3 u_ddr3 + + ( + + + + + +// Memory interface ports + + .ddr3_addr (ddr3_addr), + + .ddr3_ba (ddr3_ba), + + .ddr3_cas_n (ddr3_cas_n), + + .ddr3_ck_n (ddr3_ck_n), + + .ddr3_ck_p (ddr3_ck_p), + + .ddr3_cke (ddr3_cke), + + .ddr3_ras_n (ddr3_ras_n), + + .ddr3_we_n (ddr3_we_n), + + .ddr3_dq (ddr3_dq), + + .ddr3_dqs_n (ddr3_dqs_n), + + .ddr3_dqs_p (ddr3_dqs_p), + + .ddr3_reset_n (ddr3_reset_n), + + .init_calib_complete (init_calib_complete), + + + + + + .ddr3_dm (ddr3_dm), + + .ddr3_odt (ddr3_odt), + +// Application interface ports + + .app_addr (app_addr), + + .app_cmd (app_cmd), + + .app_en (app_en), + + .app_wdf_data (app_wdf_data), + + .app_wdf_end (app_wdf_end), + + .app_wdf_wren (app_wdf_wren), + + .app_rd_data (app_rd_data), + + .app_rd_data_end (app_rd_data_end), + + .app_rd_data_valid (app_rd_data_valid), + + .app_rdy (app_rdy), + + .app_wdf_rdy (app_wdf_rdy), + + .app_sr_req (1'b0), + + .app_ref_req (1'b0), + + .app_zq_req (1'b0), + + .app_sr_active (app_sr_active), + + .app_ref_ack (app_ref_ack), + + .app_zq_ack (app_zq_ack), + + .ui_clk (clk), + + .ui_clk_sync_rst (rst), + + + + .app_wdf_mask (app_wdf_mask), + + + + + +// System Clock Ports + + .sys_clk_i (sys_clk_i), + +// Reference Clock Ports + + .clk_ref_i (clk_ref_i), + + .device_temp_i (device_temp_i), + + .device_temp (device_temp), + + `ifdef SKIP_CALIB + + .calib_tap_req (calib_tap_req), + + .calib_tap_load (calib_tap_load), + + .calib_tap_addr (calib_tap_addr), + + .calib_tap_val (calib_tap_val), + + .calib_tap_load_done (calib_tap_load_done), + + `endif + + + + .sys_rst (sys_rst) + + ); + +// End of User Design top instance + + + + + +//*************************************************************************** + +// The traffic generation module instantiated below drives traffic (patterns) + +// on the application interface of the memory controller + +//*************************************************************************** + + + + mig_7series_v4_2_traffic_gen_top # + + ( + + .TCQ (TCQ), + + .SIMULATION (SIMULATION), + + .FAMILY ("VIRTEX7"), + + .MEM_TYPE (DRAM_TYPE), + + .TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE), + + //.BL_WIDTH (BL_WIDTH), + + .nCK_PER_CLK (nCK_PER_CLK), + + .NUM_DQ_PINS (PAYLOAD_WIDTH), + + .MEM_BURST_LEN (BURST_LENGTH), + + .MEM_COL_WIDTH (COL_WIDTH), + + .PORT_MODE (PORT_MODE), + + .DATA_PATTERN (DATA_PATTERN), + + .CMD_PATTERN (CMD_PATTERN), + + .DATA_WIDTH (APP_DATA_WIDTH), + + .ADDR_WIDTH (TG_ADDR_WIDTH), + + .MASK_SIZE (MASK_SIZE), + + .BEGIN_ADDRESS (BEGIN_ADDRESS), + + .DATA_MODE (DATA_MODE), + + .END_ADDRESS (END_ADDRESS), + + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), + + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + + .CMD_WDT (CMD_WDT), + + .RD_WDT (RD_WDT), + + .WR_WDT (WR_WDT), + + .EYE_TEST (EYE_TEST) + + ) + + u_traffic_gen_top + + ( + + .clk (clk), + + .rst (rst), + + .tg_only_rst (po_win_tg_rst | vio_tg_rst), + + .manual_clear_error (manual_clear_error), + + .memc_init_done (init_calib_complete), + + .memc_cmd_full (~app_rdy), + + .memc_cmd_en (app_en), + + .memc_cmd_instr (app_cmd), + + .memc_cmd_bl (), + + .memc_cmd_addr (app_addr), + + .memc_wr_en (app_wdf_wren), + + .memc_wr_end (app_wdf_end), + + .memc_wr_mask (app_wdf_mask), + + .memc_wr_data (app_wdf_data), + + .memc_wr_full (~app_wdf_rdy), + + .memc_rd_en (), + + .memc_rd_data (app_rd_data), + + .memc_rd_empty (~app_rd_data_valid), + + .qdr_wr_cmd_o (), + + .qdr_rd_cmd_o (), + + .vio_pause_traffic (vio_pause_traffic), + + .vio_modify_enable (vio_modify_enable), + + .vio_data_mode_value (vio_data_mode_value), + + .vio_addr_mode_value (vio_addr_mode_value), + + .vio_instr_mode_value (vio_instr_mode_value), + + .vio_bl_mode_value (vio_bl_mode_value), + + .vio_fixed_bl_value (vio_fixed_bl_value), + + .vio_fixed_instr_value(vio_fixed_instr_value), + + .vio_data_mask_gen (vio_data_mask_gen), + + .fixed_addr_i (32'b0), + + .fixed_data_i (32'b0), + + .simple_data0 (32'b0), + + .simple_data1 (32'b0), + + .simple_data2 (32'b0), + + .simple_data3 (32'b0), + + .simple_data4 (32'b0), + + .simple_data5 (32'b0), + + .simple_data6 (32'b0), + + .simple_data7 (32'b0), + + .wdt_en_i (wdt_en_w), + + .bram_cmd_i (39'b0), + + .bram_valid_i (1'b0), + + .bram_rdy_o (), + + .cmp_data (cmp_data), + + .cmp_data_valid (cmp_data_valid), + + .cmp_error (cmp_error), + + .wr_data_counts (tg_wr_data_counts), + + .rd_data_counts (tg_rd_data_counts), + + .dq_error_bytelane_cmp (dq_error_bytelane_cmp), + + .error (tg_compare_error), + + .error_status (error_status), + + .cumlative_dq_lane_error (cumlative_dq_lane_error), + + .cmd_wdt_err_o (cmd_wdt_err_w), + + .wr_wdt_err_o (wr_wdt_err_w), + + .rd_wdt_err_o (rd_wdt_err_w), + + .mem_pattern_init_done (mem_pattern_init_done) + + ); + + + + + + //***************************************************************** + + // Default values are assigned to the debug inputs of the traffic + + // generator + + //***************************************************************** + + assign vio_modify_enable = 1'b0; + + assign vio_data_mode_value = 4'b0010; + + assign vio_addr_mode_value = 3'b011; + + assign vio_instr_mode_value = 4'b0010; + + assign vio_bl_mode_value = 2'b10; + + assign vio_fixed_bl_value = 8'd16; + + assign vio_data_mask_gen = 1'b0; + + assign vio_pause_traffic = 1'b0; + + assign vio_fixed_instr_value = 3'b001; + + assign dbg_clear_error = 1'b0; + + assign po_win_tg_rst = 1'b0; + + assign vio_tg_rst = 1'b0; + + assign wdt_en_w = 1'b1; + + + + assign dbg_sel_pi_incdec = 'b0; + + assign dbg_sel_po_incdec = 'b0; + + assign dbg_pi_f_inc = 'b0; + + assign dbg_pi_f_dec = 'b0; + + assign dbg_po_f_inc = 'b0; + + assign dbg_po_f_dec = 'b0; + + assign dbg_po_f_stg23_sel = 'b0; + + + + + +`ifdef SKIP_CALIB + + //*************************************************************************** + + // Skip calib test logic + + //*************************************************************************** + + + + reg[3*DQS_WIDTH-1:0] po_coarse_tap; + + reg[6*DQS_WIDTH-1:0] po_stg3_taps; + + reg[6*DQS_WIDTH-1:0] po_stg2_taps; + + reg[6*DQS_WIDTH-1:0] pi_stg2_taps; + + reg[5*DQS_WIDTH-1:0] idelay_taps; + + reg[11:0] cal_device_temp; + + + + + + always @(posedge clk) begin + + // tap values from golden run (factory) + + po_coarse_tap <= #TCQ 'h2; + + po_stg3_taps <= #TCQ 'h0D; + + po_stg2_taps <= #TCQ 'h1D; + + pi_stg2_taps <= #TCQ 'h1E; + + idelay_taps <= #TCQ 'h08; + + cal_device_temp <= #TCQ 'h000; + + end + + + + always @(posedge clk) begin + + if (rst) + + calib_tap_load <= #TCQ 1'b0; + + else if (calib_tap_req) + + calib_tap_load <= #TCQ 1'b1; + + end + + + + always @(posedge clk) begin + + if (rst) begin + + calib_tap_addr <= #TCQ 'd0; + + calib_tap_val <= #TCQ po_coarse_tap[3*calib_tap_addr[6:3]+:3]; //'d1; + + calib_tap_load_done <= #TCQ 1'b0; + + end else if (calib_tap_load) begin + + case (calib_tap_addr[2:0]) + + 3'b000: begin + + calib_tap_addr[2:0] <= #TCQ 3'b001; + + calib_tap_val <= #TCQ po_stg3_taps[6*calib_tap_addr[6:3]+:6]; //'d19; + + end + + 3'b001: begin + + calib_tap_addr[2:0] <= #TCQ 3'b010; + + calib_tap_val <= #TCQ po_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d45; + + end + + 3'b010: begin + + calib_tap_addr[2:0] <= #TCQ 3'b011; + + calib_tap_val <= #TCQ pi_stg2_taps[6*calib_tap_addr[6:3]+:6]; //'d20; + + end + + 3'b011: begin + + calib_tap_addr[2:0] <= #TCQ 3'b100; + + calib_tap_val <= #TCQ idelay_taps[5*calib_tap_addr[6:3]+:5]; //'d1; + + end + + 3'b100: begin + + if (calib_tap_addr[6:3] < DQS_WIDTH-1) begin + + calib_tap_addr[2:0] <= #TCQ 3'b000; + + calib_tap_val <= #TCQ po_coarse_tap[3*(calib_tap_addr[6:3]+1)+:3]; //'d1; + + calib_tap_addr[6:3] <= #TCQ calib_tap_addr[6:3] + 1; + + end else begin + + calib_tap_addr[2:0] <= #TCQ 3'b110; + + calib_tap_val <= #TCQ cal_device_temp[7:0]; + + calib_tap_addr[6:3] <= #TCQ 4'b1111; + + end + + end + + 3'b110: begin + + calib_tap_addr[2:0] <= #TCQ 3'b111; + + calib_tap_val <= #TCQ {4'h0,cal_device_temp[11:8]}; + + calib_tap_addr[6:3] <= #TCQ 4'b1111; + + end + + 3'b111: begin + + calib_tap_load_done <= #TCQ 1'b1; + + end + + endcase + + end + + end + + + + + +//****************skip calib test logic end********************************** + +`endif + + + +endmodule + + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_afifo.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_afifo.v new file mode 100644 index 0000000..86ce619 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_afifo.v @@ -0,0 +1,231 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: afifo.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $ +// \ \ / \ Date Created: Oct 21 2008 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: A generic synchronous fifo. +//Reference: +//Revision History: 1.2 11/8/2010 Removed unused signals. + +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_afifo # +( + parameter TCQ = 100, + parameter DSIZE = 32, + parameter FIFO_DEPTH = 16, + parameter ASIZE = 4, + parameter SYNC = 1 // only has always '1' logic. +) +( +input wr_clk, +input rst, +input wr_en, +input [DSIZE-1:0] wr_data, +input rd_en, +input rd_clk, +output [DSIZE-1:0] rd_data, +output reg full, +output reg empty, +output reg almost_full +); + +// memory array +reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1]; + +//Read Capture Logic +// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk +reg [ASIZE:0] rd_capture_ptr; +reg [ASIZE:0] pre_rd_capture_gray_ptr; +reg [ASIZE:0] rd_capture_gray_ptr; + +reg [ASIZE:0] wr_capture_ptr; +reg [ASIZE:0] pre_wr_capture_gray_ptr; +reg [ASIZE:0] wr_capture_gray_ptr; +wire [ASIZE:0] buf_avail; +wire [ASIZE:0] buf_filled; +wire [ASIZE-1:0] wr_addr, rd_addr; +wire COutb,COutd; +reg COuta,COutc; +reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp; +integer i,j,k; + + + always @ (rd_ptr) + rd_capture_ptr = rd_ptr; + + + +//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers +// before do comparison. + + + +always @ (wr_ptr) + wr_capture_ptr = wr_ptr; + +// dualport ram +// Memory (RAM) that holds the contents of the FIFO + + +assign wr_addr = wr_ptr[ASIZE-1:0]; +assign rd_data = mem[rd_addr]; +always @(posedge wr_clk) +begin +if (wr_en && !full) + mem[wr_addr] <= #TCQ wr_data; + +end + + +// Read Side Logic + + +assign rd_addr = rd_ptr_cp[ASIZE-1:0]; +assign rd_strobe = rd_en && !empty; + +integer n; + // change the binary pointer to gray pointer + + +always @(posedge rd_clk) +begin +if (rst) + begin + rd_ptr <= #TCQ 'b0; + rd_ptr_cp <= #TCQ 'b0; + + end +else begin + if (rd_strobe) begin + {COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1; + rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1; + + end + + // change the binary pointer to gray pointer +end + +end + +//generate empty signal +assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr; + +always @ (posedge rd_clk ) +begin + if (rst) + empty <= #TCQ 1'b1; + else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe)) + empty <= #TCQ 1'b1; + else + empty <= #TCQ 1'b0; +end + + +// write side logic; + +reg [ASIZE:0] wbin; +wire [ASIZE:0] wgraynext, wbinnext; + + + +always @(posedge rd_clk) +begin +if (rst) + begin + wr_ptr <= #TCQ 'b0; + end +else begin + if (wr_en) + {COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1; + + // change the binary pointer to gray pointer +end + +end + + +// calculate how many buf still available +//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr; +assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16; + + +always @ (posedge wr_clk ) +begin + if (rst) + full <= #TCQ 1'b0; + else if ((buf_avail == 0) || (buf_avail == 1 && wr_en)) + full <= #TCQ 1'b1; + else + full <= #TCQ 1'b0; +end + + +always @ (posedge wr_clk ) +begin + if (rst) + almost_full <= #TCQ 1'b0; + else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en)) + almost_full <= #TCQ 1'b1; + else + almost_full <= #TCQ 1'b0; +end + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_gen.v new file mode 100644 index 0000000..95798fd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_gen.v @@ -0,0 +1,1788 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: cmd_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ +// \ \ / \ Date Created: Oct 21 2008 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module genreates different type of commands, address, +// burst_length to mcb_flow_control module. +//Reference: +//Revision History: +// Nov14 2008. Added constraints for generating PRBS_BL when +// generated address is too close to end of address space. +// The BL will be force to 1 to avoid across other port's space. +// April 2 2009 Fixed Sequential Address Circuit to avoide generate any address +// beyond the allowed address range. +// Oct 22 2009 Fixed BRAM interface. +// Fixed run_traffic stop and go problem. +// Merged V6 and SP6 specific requirements. +// Modified syntax for VHDL Formality comparison. +// Dec 1 2011 Fixed Simple Data mode address generation problem. +// Jan 4 2012 Added percent write instruction mode ( mode == 4) to +// let user specify percentage of write commands out of mix +// write/read commands. + +//***************************************************************************** + + + +`timescale 1ps/1ps + + + +`define RD 3'b001; + +`define RDP 3'b011; + +`define WR 3'b000; + +`define WRP 3'b010; + +`define REFRESH 3'b100; + + + +(* use_dsp48 = "no" *) + +module mig_7series_v4_2_cmd_gen # + + ( + + parameter TCQ = 100, + + + + parameter FAMILY = "SPARTAN6", + + parameter MEM_TYPE = "DDR3", + + + + parameter BL_WIDTH = 6, // User Commands Burst length that send over User Interface. + + parameter MEM_BURST_LEN = 8, + + parameter nCK_PER_CLK = 4, + + parameter PORT_MODE = "BI_MODE", + + parameter NUM_DQ_PINS = 8, + + parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL", + + parameter ADDR_WIDTH = 30, + + parameter BANK_WIDTH = 3, + + parameter DWIDTH = 32, + + parameter PIPE_STAGES = 0, + + parameter MEM_COL_WIDTH = 10, // memory column width + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + + parameter PRBS_EADDR = 32'h00002000, + + parameter PRBS_SADDR = 32'h00002000 + + ) + + ( + + input clk_i, + + input [9:0] rst_i, + + input run_traffic_i, + + input [3:0] vio_instr_mode_value, + input [3:0] vio_percent_write, + input single_operation, + + // runtime parameter + + input mem_pattern_init_done_i, + + input [31:0] start_addr_i, // define the start of address + + input [31:0] end_addr_i, + + input [31:0] cmd_seed_i, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen + + input load_seed_i, // + + // upper layer inputs to determine the command bus and data pattern + + // internal traffic generator initialize the memory with + + input [2:0] addr_mode_i, // "00" = bram; takes the address from bram output + + // "01" = fixed address from the fixed_addr input + + // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR + + // "11" = sequential + + + + input [3:0] data_mode_i, // 4'b0010:address as data + + // 4'b0011:DGEN_HAMMER + + // 4'b0100:DGEN_NEIGHBOUR + + // 4'b0101:DGEN_WALKING1 + + // 4'b0110:DGEN_WALKING0 + + // 4'b0111:PRBS_DATA + + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + + input [3:0] instr_mode_i, // "0000" = bram; takes instruction from bram output + + // "0001" = fixed instr from fixed instr input + + // "0010" = R/W + + // "0011" = RP/WP + + // "0100" = R/RP/W/WP + + // "0101" = R/RP/W/WP/REF + + // "0110" = PRBS + + + + + + input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output + + // "01" = fixed , takes the burst length from the fixed_bl input + + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + + + input mode_load_i, + + + + // fixed pattern inputs interface + + input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64 + + input [2:0] fixed_instr_i, //RD 3'b001 + + //RDP 3'b011 + + //WR 3'b000 + + //WRP 3'b010 + + //REFRESH 3'b100 + + input [31:0] fixed_addr_i, // only upper 30 bits will be used + + // BRAM FIFO input + + input [31:0] bram_addr_i, // + + input [2:0] bram_instr_i, + + input [5:0] bram_bl_i, + + input bram_valid_i, + + output bram_rdy_o, + + + + input reading_rd_data_i, + + // mcb_flow_control interface + + input rdy_i, + + + + output [31:0] addr_o, // generated address + + output [2:0] instr_o, // generated instruction + + output [BL_WIDTH - 1:0] bl_o, // generated instruction + +// output reg [31:0] m_addr_o, + + output cmd_o_vld , // valid commands when asserted + + output reg mem_init_done_o + + ); + + + + localparam PRBS_ADDR_WIDTH = 32; + + localparam INSTR_PRBS_WIDTH = 16; + + localparam BL_PRBS_WIDTH = 16; + + + +localparam BRAM_DATAL_MODE = 4'b0000; + +localparam FIXED_DATA_MODE = 4'b0001; + +localparam ADDR_DATA_MODE = 4'b0010; + +localparam HAMMER_DATA_MODE = 4'b0011; + +localparam NEIGHBOR_DATA_MODE = 4'b0100; + +localparam WALKING1_DATA_MODE = 4'b0101; + +localparam WALKING0_DATA_MODE = 4'b0110; + +localparam PRBS_DATA_MODE = 4'b0111; + +localparam DWIDTH_BY_8 = (DWIDTH >> 3); + +localparam LOGB2_MEM_BURST_INT = (MEM_BURST_LEN == 8)? 3:2; + + + +reg [BL_WIDTH+DWIDTH_BY_8-1:0] bl_x_DWIDTH_BY_8; + +reg [BL_WIDTH+2:0] INC_COUNTS /* synthesis syn_dspstyle = logic */ ; + +reg [2:0] addr_mode_reg; + +reg [1:0] bl_mode_reg; + +reg [31:0] addr_counts /* synthesis syn_dspstyle = logic */ ; + +reg [31:0] addr_counts_next_r; + +reg [BANK_WIDTH-1:0] bank_counts; + +wire [14:0] prbs_bl; + +reg [2:0] instr_out; + +wire [14:0] prbs_instr_a; + +wire [14:0] prbs_instr_b; + +reg [BL_WIDTH - 1:0] prbs_brlen; + +wire [31:0] prbs_addr; + +wire [31:0] seq_addr; + +wire [31:0] fixed_addr; + +reg [31:0] addr_out ; + +reg [BL_WIDTH - 1:0] bl_out; + +reg [BL_WIDTH + DWIDTH/8 - 1:0]cal_blout; + +reg [BL_WIDTH - 1:0] bl_out_reg; + +reg mode_load_d1; + +reg mode_load_d2; + +reg mode_load_pulse; + +wire [BL_WIDTH+35:0] pipe_data_o; + +wire cmd_clk_en; + +wire pipe_out_vld; + +reg force_bl1; + +reg bl_out_clk_en; + +reg [BL_WIDTH+35:0] pipe_data_in; + +reg instr_vld; + +reg bl_out_vld; + +reg gen_addr_larger ; + +reg gen_bl_larger; + +reg [7:0] buf_avail_r; + +reg [6:0] rd_data_received_counts; + +reg [6:0] rd_data_counts_asked; + +reg instr_vld_dly1; + +reg first_load_pulse; + +reg mem_init_done; + +reg refresh_cmd_en ; + +reg [9:0] refresh_timer; + +reg refresh_prbs; + +reg cmd_vld; + +reg run_traffic_r; + +reg cmd_clk_en_r; + +reg finish_init; + +reg mem_init_done_r; + +reg first_mode_load_pulse_r1; + +reg first_mode_load_pulse_set; + +reg mode_load_pulse_r1; + +reg n_gen_write_only; + +reg [9:0]force_rd_counts; + +reg force_rd; + +reg bl_64; + +reg force_wrcmd_gen; +reg toggle_rw; +reg [3:0] write_percent_cnt; + + + +always @ (posedge clk_i) + + if (rst_i[0]) + + mem_init_done_o <= #TCQ 1'b0; + + else if (cmd_clk_en_r) + + mem_init_done_o <= #TCQ mem_init_done_r; + + +always @ (posedge clk_i) +begin + + run_traffic_r <= #TCQ run_traffic_i; + +end + + +// commands go through pipeline inserters + +assign addr_o = pipe_data_o[31:0]; + +assign instr_o = pipe_data_o[34:32]; + + + +assign bl_o = pipe_data_o[(BL_WIDTH - 1 + 35):35]; + + + + + + + + // most significant bit + +assign cmd_o_vld = pipe_data_o[BL_WIDTH + 35] & run_traffic_r; + +assign pipe_out_vld = pipe_data_o[BL_WIDTH + 35] & run_traffic_r; + + + + + +assign pipe_data_o = pipe_data_in; + + + +always @(posedge clk_i) begin + + + + instr_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse)); + + bl_out_clk_en <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse)); + + bl_out_vld <= #TCQ bl_out_clk_en; + + end + + + +always @ (posedge clk_i) begin + + if (rst_i[0] || single_operation) + + first_load_pulse <= #TCQ 1'b1; + + else if (mode_load_pulse) + + first_load_pulse <= #TCQ 1'b0; + + else + + first_load_pulse <= #TCQ first_load_pulse; + + end + + + + + +always @(posedge clk_i) begin + +if (CMD_PATTERN == "CGEN_BRAM") + + cmd_vld <= #TCQ (cmd_clk_en ); + +else //if (CMD_PATTERN != "CGEN_BRAM") + + cmd_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse )); + + + +end + + + + + +assign cmd_clk_en = ( rdy_i & pipe_out_vld & run_traffic_i || mode_load_pulse && (CMD_PATTERN == "CGEN_BRAM")); + + + + + + + +integer i; + +always @ (posedge clk_i) + +if (rst_i[1]) + + bl_64 <= 1'b0; + +else if (data_mode_i == 7 || data_mode_i == 8 || data_mode_i == 9) + + bl_64 <= 1'b1; + +else + + bl_64 <= 1'b0; + + + + + + always @ (posedge clk_i) begin + + if (rst_i[1]) + + if (vio_instr_mode_value == 4'h7) + + pipe_data_in[31:0] <= #TCQ fixed_addr_i; + + else + + pipe_data_in[31:0] <= #TCQ start_addr_i; + + else if (instr_vld) + + // In order to simplify all different test pattern, the V6 generated + + // seed address from cmd_gen are aligned to burst length. The PRBS + + // burst length for write always 64 else it will break. + + // if (MEM_BURST_LEN == 8) + + if (data_mode_i == 5 || data_mode_i == 6) + + // for walking 1's / walking 0's pattern, the least 8 bits starting address + + // has to be all zero. This is to force the DQ pattern of each starting burst + + // starts from DQ0. + + if (FAMILY == "VIRTEX6") + + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'h00}; + + + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'h00}; // DWIDTH = 64 + + + + + + else if (data_mode_i == 4) + + // pipe_data_in[31:0] <= #TCQ {addr_out[31:3], 3'b000}; + + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'b000}; + + + + else if (bl_64) + + // nCK_PER_CLK = 4 && PRBS Length = 8 + + //force the least 11 bits starting address is always zero to align + + // PRBS sequence. + + if (nCK_PER_CLK == 4) + + if (FAMILY == "VIRTEX6") + + pipe_data_in[31:0] <= #TCQ {addr_out[31:11], 11'h000}; + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:9], 9'h000}; + + + + else + + if (FAMILY == "VIRTEX6") + + pipe_data_in[31:0] <= #TCQ {addr_out[31:10], 10'h000}; + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:9], 9'h000}; + + else if (gen_addr_larger && mem_init_done)// && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) + + pipe_data_in[31:0] <= #TCQ {end_addr_i[31:8],8'h0}; + + else + + pipe_data_in[31:0] <= #TCQ {addr_out[31:2], 2'b00}; + + // else + + // pipe_data_in[31:0] <= #TCQ {addr_out[31:2],2'b00000}; + + + +end + + + +//end endgenerate + + + + + + always @ (posedge clk_i) begin + + if (rst_i[0]) + + force_wrcmd_gen <= #TCQ 1'b0; + + else if (buf_avail_r == 63) + + force_wrcmd_gen <= #TCQ 1'b0; + + else if (instr_vld_dly1 && pipe_data_in[32]== 1 && pipe_data_in[41:35] > 16) + + force_wrcmd_gen <= #TCQ 1'b1; + + end + +reg [3:0]instr_mode_reg; + + always @ (posedge clk_i) + + begin + + instr_mode_reg <= #TCQ instr_mode_i; + + end + + always @ (posedge clk_i) + + begin + + if (rst_i[2]) begin + + pipe_data_in[40:32] <= #TCQ 'b0; + + end + + else if (instr_vld) begin + + if (instr_mode_reg == 0) begin + + pipe_data_in[34:32] <= #TCQ instr_out; + + end + + else if (instr_out[2]) begin + + pipe_data_in[34:32] <= #TCQ 3'b100; + + end + + // + + else if ( FAMILY == "SPARTAN6" && PORT_MODE == "RD_MODE") + + begin + + pipe_data_in[34:32] <= #TCQ {instr_out[2:1],1'b1}; + + end + + + + else if ((force_wrcmd_gen || buf_avail_r <= 15) && FAMILY == "SPARTAN6" && PORT_MODE != "RD_MODE") + + begin + + pipe_data_in[34:32] <= #TCQ {instr_out[2],2'b00}; + + end + + else begin + + pipe_data_in[34:32] <= #TCQ instr_out; + + end + + + + //********* condition the generated bl value except if TG is programmed for BRAM interface' + + // if the generated address is close to end address range, the bl_out will be altered to 1. + + if (data_mode_i == 7 ) + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ bl_out; + + + + else if (data_mode_i == 4 ) + + + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd32; + + + + + + else + + if (gen_bl_larger && mem_pattern_init_done_i) // this condition is needed + + + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd8; + + else if (force_bl1 && mem_pattern_init_done_i) + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ 10'd2; // for V6 + + + + else + + pipe_data_in[BL_WIDTH-1+35:35] <= #TCQ bl_out; // 8:2' 4:4 + + + + end //else instr_vld + + end // always + + + +reg COut; + + + +always @ (posedge clk_i) + +begin + + if (rst_i[2]) + + pipe_data_in[BL_WIDTH + 35] <= #TCQ 'b0; + + else if (cmd_vld) + + pipe_data_in[BL_WIDTH + 35] <= #TCQ instr_vld;//instr_vld; + + else if (rdy_i && pipe_out_vld) + + pipe_data_in[BL_WIDTH + 35] <= #TCQ 1'b0; + + end + + + + always @ (posedge clk_i) + + instr_vld_dly1 <= #TCQ instr_vld; + + + + + +reg COutA; + +always @ (posedge clk_i) begin + + if (rst_i[0]) begin + + rd_data_counts_asked <= #TCQ 'b0; + + end else if (instr_vld_dly1 && pipe_data_in[32]== 1) begin + + if (pipe_data_in[(BL_WIDTH +35):35] == 0) + + {COutA,rd_data_counts_asked} <= #TCQ rd_data_counts_asked + (10'd64) ; + + else + + {COutA,rd_data_counts_asked} <= #TCQ rd_data_counts_asked + (pipe_data_in[41:35]) ; + + + + end + + end + + + +always @ (posedge clk_i) begin + + if (rst_i[0]) begin + + rd_data_received_counts <= #TCQ 'b0; + + end else if(reading_rd_data_i) begin + + rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1; + + end + + end + + + + + +reg COut_d; + + always @ (posedge clk_i) + + if (FAMILY == "SPARTAN6") + + {COut_d, buf_avail_r} <= #TCQ ( rd_data_received_counts[6:0] - rd_data_counts_asked[6:0] + 7'd64); + + else // Virtex 6 MC has no need to generate such constraints . + + buf_avail_r <= #TCQ 8'd64; + + + +localparam BRAM_ADDR = 2'b00; + +localparam FIXED_ADDR = 2'b01; + +localparam PRBS_ADDR = 2'b10; + +localparam SEQUENTIAL_ADDR = 2'b11; + + + +// registered the mode settings + +always @ (posedge clk_i) begin + + if (rst_i[3]) + + if (CMD_PATTERN == "CGEN_BRAM") + + addr_mode_reg <= #TCQ 3'b000; + + else + + addr_mode_reg <= #TCQ 3'b011; + + else if (mode_load_pulse) + + addr_mode_reg <= #TCQ addr_mode_i; + +end + + + +always @ (posedge clk_i) begin + + if (mode_load_pulse) begin + + bl_mode_reg <= #TCQ bl_mode_i ; + + end + +// mode_load_d1 <= #TCQ mode_load_i; +// +// mode_load_d2 <= #TCQ mode_load_d1; + +end + +always @ (posedge clk_i) +begin + if (rst_i[0]) + begin + mode_load_d1 <= #TCQ 'b0; + mode_load_d2 <= #TCQ 'b0; + end + else + begin + mode_load_d1 <= #TCQ mode_load_i ; + mode_load_d2 <= #TCQ mode_load_d1 ; + end +end + + + +always @ (posedge clk_i) + + mode_load_pulse <= #TCQ mode_load_d1 & ~mode_load_d2; + + + +// MUX the addr pattern out depending on the addr_mode setting + + + +// "000" = bram; takes the address from bram output + +// "001" = fixed address from the fixed_addr input + +// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR + +// "011" = sequential + +// "100" = mode that used for prbs addr , prbs bl and prbs data + +//always @(addr_mode_reg,prbs_addr,seq_addr,fixed_addr,bram_addr_i,data_mode_i) + +always @ (posedge clk_i) begin + +if (rst_i[3]) + + + + addr_out <= #TCQ start_addr_i; + +else if (vio_instr_mode_value == 4'h7) + + addr_out <= #TCQ fixed_addr_i; + + + +else + + case({addr_mode_reg}) + + 3'b000: addr_out <= #TCQ bram_addr_i; + + 3'b001: addr_out <= #TCQ fixed_addr; + +// 3'b010: addr_out <= #TCQ {prbs_addr[31:10], 10'h00}; // this is specific to + + // data mode = PRBS + + + + 3'b010: if (FAMILY == "VIRTEX6") + + if (data_mode_i == 5) // ??? optimize this + + addr_out <= #TCQ {prbs_addr[31:BL_WIDTH+1], {BL_WIDTH+1{1'b0}}}; // this is specific to + + else + + addr_out <= #TCQ {prbs_addr[31:BL_WIDTH], {BL_WIDTH{1'b0}}}; // this is specific to + + else + + addr_out <= #TCQ {prbs_addr}; + + + + + + 3'b011: addr_out <= #TCQ {2'b0,seq_addr[29:0]}; + + 3'b100: addr_out <= #TCQ {3'b000,seq_addr[6:2],seq_addr[23:0]};//{prbs_addr[31:6],6'b000000} ; + + 3'b101: addr_out <= #TCQ {prbs_addr[31:20],seq_addr[19:0]} ; + + + + default : addr_out <= #TCQ 'b0; + + endcase + +end + + + +// ADDR PRBS GENERATION + +generate + +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) + + begin: gen_prbs_addr + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .TCQ (TCQ), + .FAMILY (FAMILY), + .ADDR_WIDTH (32), + .DWIDTH (DWIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .PRBS_WIDTH (32), + .SEED_WIDTH (32), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), + .PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS), + .PRBS_EADDR (PRBS_EADDR), + .PRBS_SADDR (PRBS_SADDR) + ) + + addr_prbs_gen + + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (mode_load_pulse), + + .prbs_seed_i (cmd_seed_i[31:0]), + + .prbs_o (prbs_addr) + + ); + + end + + else + + begin: no_prbs + + assign prbs_addr = 'b0; + + + + end + +endgenerate + + + +always @ (posedge clk_i) begin + +if (addr_out[31:8] >= end_addr_i[31:8]) + + gen_addr_larger <= 1'b1; + +else + + gen_addr_larger <= 1'b0; + +end + +wire [23:0] calc_end_addr /* synthesis syn_dspstyle = logic */ ; +assign calc_end_addr = (bl_out*(DWIDTH/8) + addr_out[31:8]) ; + +always @ (posedge clk_i) begin +if (instr_mode_i == 4 && mem_init_done) + gen_bl_larger <= 1'b0; + +else if ( calc_end_addr >= end_addr_i[31:8] ) + gen_bl_larger <= 1'b1; +else + gen_bl_larger <= 1'b0; +end + + + +//converting string to integer + +//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4; + +localparam MEM_BURST_INT = MEM_BURST_LEN ; + + +generate + +if (FAMILY == "SPARTAN6") begin : INC_COUNTS_S + + always @ (posedge clk_i) + + if (mem_init_done) + INC_COUNTS <= #TCQ (DWIDTH/8)*(bl_out_reg); + else begin + if (fixed_bl_i == 0) + INC_COUNTS <= #TCQ (DWIDTH/8)*(64); + else + INC_COUNTS <= #TCQ (DWIDTH/8)*(fixed_bl_i); + end + + end + +else begin : INC_COUNTS_V + + always @ (posedge clk_i) begin + if (rst_i[3]) begin + INC_COUNTS[BL_WIDTH-1:0] <= fixed_bl_i * (DWIDTH)/16; + INC_COUNTS[BL_WIDTH+2:BL_WIDTH] <= 'b0; + end + else + if (nCK_PER_CLK == 4 && MEM_BURST_LEN != 2) + INC_COUNTS <= #TCQ (bl_out << LOGB2_MEM_BURST_INT); + else begin + if (MEM_TYPE != "QDR2PLUS") begin //nCK_PER_CK == 2 + if (MEM_BURST_LEN == 8 || MEM_BURST_LEN == 2) // 13:11 + INC_COUNTS <= #TCQ (bl_out << (LOGB2_MEM_BURST_INT - 1)); + else + INC_COUNTS <= #TCQ (bl_out << LOGB2_MEM_BURST_INT); + end + else begin + INC_COUNTS[BL_WIDTH-1:0] <= #TCQ bl_out; + INC_COUNTS[BL_WIDTH+2:BL_WIDTH] <= 'b0; + end + end + end + +end + +endgenerate + + +generate + +// Sequential Address pattern +// It is generated when rdy_i is valid and write command is valid and bl_cmd is valid. +if (CMD_PATTERN == "CGEN_SEQUENTIAL" || CMD_PATTERN == "CGEN_ALL" ) + + begin : seq_addr_gen + + assign seq_addr = addr_counts; + + always @ (posedge clk_i) + begin + + if (rst_i[2]) + + first_mode_load_pulse_set <= 1'b0; + + else if (mode_load_pulse_r1) + + first_mode_load_pulse_set <= #TCQ 1'b1; + end + + always @ (posedge clk_i) + begin + + mode_load_pulse_r1 <= #TCQ mode_load_pulse; + first_mode_load_pulse_r1 <= #TCQ mode_load_pulse & ~first_mode_load_pulse_set; + end + + always @ (posedge clk_i) + begin + + if (rst_i[4]) + + mem_init_done_r <= #TCQ 1'b0 ; + + else if (cmd_clk_en_r) + + mem_init_done_r <= #TCQ mem_init_done ; + end + + + reg COut_b,COut_c; + wire [32:0] addr_counts_added; + assign addr_counts_added = addr_counts + INC_COUNTS /* synthesis syn_dspstyle = logic */ ; + + always @ (posedge clk_i) + + addr_counts_next_r <= #TCQ addr_counts_added ; + + + always @ (posedge clk_i) + + cmd_clk_en_r <= #TCQ cmd_clk_en; + + + always @ (posedge clk_i) + begin + + if (rst_i[4]) begin + + addr_counts <= #TCQ start_addr_i; + mem_init_done <= #TCQ 1'b0; + + end + + else if (cmd_clk_en_r || first_mode_load_pulse_r1) + + if(addr_counts_next_r >= end_addr_i ) begin + + addr_counts <= #TCQ start_addr_i; + mem_init_done <= #TCQ 1'b1; + + end + + else // address counts get incremented by burst_length and port size each wr command generated + + {COut_c,addr_counts} <= #TCQ addr_counts_added ; + end + + end + + else + + begin: no_gen_seq_addr + + assign seq_addr = 'b0; + + end + +endgenerate + +always @ (posedge clk_i) begin + + if (rst_i[4]) + + n_gen_write_only <= 1'b0; + + else if (~n_gen_write_only && addr_counts_next_r>= end_addr_i) + + n_gen_write_only <= 1'b1; + + + + else if(addr_counts_next_r>= end_addr_i && instr_out[0] == 1'b0) + + n_gen_write_only <= 1'b0; +end + +generate + +// Fixed Address pattern +if (CMD_PATTERN == "CGEN_FIXED" || CMD_PATTERN == "CGEN_ALL" ) + + begin : fixed_addr_gen + + assign fixed_addr = (DWIDTH == 32)? {fixed_addr_i[31:2],2'b0} : + + (DWIDTH == 64)? {fixed_addr_i[31:3],3'b0}: + + (DWIDTH <= 128)? {fixed_addr_i[31:4],4'b0}: + + (DWIDTH <= 256)? {fixed_addr_i[31:5],5'b0}: + + {fixed_addr_i[31:6],6'b0}; + + end + +else + + begin : no_fixed_addr_gen + + assign fixed_addr = 'b0; + + end + +endgenerate + + +generate + +// BRAM Address pattern +if (CMD_PATTERN == "CGEN_BRAM" || CMD_PATTERN == "CGEN_ALL" ) + + begin : bram_addr_gen + + assign bram_rdy_o = run_traffic_i & cmd_clk_en & bram_valid_i | mode_load_pulse; + + end + +else + + begin: no_bram_addr_gen + + assign bram_rdy_o = 1'b0; + + end + +endgenerate + + + +/////////////////////////////////////////////////////////////////////////// + +// INSTR COMMAND GENERATION + + + +// tap points are 3,2 + +//`define RD 3'b001 + +//`define RDP 3'b011 + +//`define WR 3'b000 + +//`define WRP 3'b010 + +//`define REFRESH 3'b100 + +// use 14 stages 1 sr16; tap position 1,3,5,14 + + + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + force_rd_counts <= #TCQ 'b0; + +else if (instr_vld) begin + + force_rd_counts <= #TCQ force_rd_counts + 1'b1; + + end + +end + + + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + force_rd <= #TCQ 1'b0; + +else if (force_rd_counts[3]) + + force_rd <= #TCQ 1'b1; + +else + + force_rd <= #TCQ 1'b0; + +end + +// adding refresh timer to limit the amount of issuing refresh command. + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + refresh_timer <= #TCQ 'b0; + +else + + refresh_timer <= #TCQ refresh_timer + 1'b1; + +end + + +always @ (posedge clk_i) begin + +if (rst_i[4]) + + refresh_cmd_en <= #TCQ 'b0; + +//else if (refresh_timer >= 12'hff0 && refresh_timer <= 12'hfff) + +else if (refresh_timer == 10'h3ff) + + refresh_cmd_en <= #TCQ 'b1; + +else if (cmd_clk_en && refresh_cmd_en) + + refresh_cmd_en <= #TCQ 'b0; +end + +always @ (posedge clk_i) begin + +if (FAMILY == "SPARTAN6") + + refresh_prbs <= #TCQ prbs_instr_b[3] & refresh_cmd_en; + +else + + refresh_prbs <= #TCQ 1'b0; + +end + +always @ (posedge clk_i) +begin +if (rst_i[4]) + write_percent_cnt <= 'b0; +else if (cmd_clk_en_r) + if ( write_percent_cnt == 9) + write_percent_cnt <= 'b0; + else + write_percent_cnt <= write_percent_cnt + 1'b1; +end +always @ (posedge clk_i) +begin +if (rst_i[4]) + toggle_rw <= 1'b0; +else if (cmd_clk_en_r && mem_init_done) + if (write_percent_cnt >= vio_percent_write) + toggle_rw <= 1'b1; + else + toggle_rw <= 1'b0; +end + +always @ (posedge clk_i) begin + + case(instr_mode_i) + + 0: instr_out <= #TCQ bram_instr_i; + + 1: instr_out <= #TCQ fixed_instr_i; + + 2: instr_out <= #TCQ {2'b00,(prbs_instr_a[0] | force_rd)}; + 3: instr_out <= #TCQ {2'b00,prbs_instr_a[0]}; //: WP/RP + 4: instr_out <= #TCQ {2'b00,toggle_rw}; // percent write + + + // may be add another PRBS for generating REFRESH + +// 5: instr_out <= #TCQ {prbs_instr_b[3],prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH + + 5: instr_out <= #TCQ {refresh_prbs ,prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH + + + + + + default : instr_out <= #TCQ {2'b00,1'b1}; + + endcase + +end + + + +generate // PRBS INSTRUCTION generation + +// use two PRBS generators and tap off 1 bit from each to create more randomness for + +// generating actual read/write commands + +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) + + begin: gen_prbs_instr + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .TCQ (TCQ), + + .PRBS_CMD ("INSTR"), + + .DWIDTH (DWIDTH), + + + + .ADDR_WIDTH (32), + + .SEED_WIDTH (15), + + .PRBS_WIDTH (20) + + ) + + instr_prbs_gen_a + + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (load_seed_i), + + .prbs_seed_i (cmd_seed_i[14:0]), + + .prbs_o (prbs_instr_a) + + ); + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .PRBS_CMD ("INSTR"), + + .DWIDTH (DWIDTH), + + + + .SEED_WIDTH (15), + + .PRBS_WIDTH (20) + + ) + instr_prbs_gen_b + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (load_seed_i), + + .prbs_seed_i (cmd_seed_i[16:2]), + + .prbs_o (prbs_instr_b) + + ); + + end + + else + + begin: no_prbs_instr_gen + + assign prbs_instr_a = 'b0; + + assign prbs_instr_b = 'b0; + + end + +endgenerate + + + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// BURST LENGTH GENERATION + +// burst length code = user burst length input - 1 + +// mcb_flow_control does the minus before sending out to mcb\ + +// when filling up the memory, need to make sure bl doesn't go beyound its upper limit boundary + +//assign force_bl1 = (addr_out[31:0] >= (end_addr_i[31:0] - 4*64)) ? 1'b1: 1'b0; + +// for neighbour pattern, need to limit the bl to make sure it is within column size boundary. + + + +// This is required in S6 . + + + +always @ (posedge clk_i) + +begin + +if (rst_i[4] ) + + cal_blout <= 'b0; + +else + + cal_blout <= bl_out* (DWIDTH/8); + +end + +wire [31:0] dummy; +wire [32:0] dummy_sub; + +assign dummy = (addr_out + cal_blout); +assign dummy_sub = (dummy - end_addr_i); + +always @(*) begin + + force_bl1 = 1'b0; + if (rst_i[6] || (mem_init_done && instr_mode_i == 4)) + force_bl1 = 1'b0; + else if ((dummy_sub[32] == 0) || (buf_avail_r <= 50 && PORT_MODE == "RD_MODE")) + force_bl1 = 1'b1; + +end + +//always @(addr_out,mem_init_done, instr_mode_i,bl_out,cal_blout,end_addr_i,rst_i,buf_avail_r,bl_x_DWIDTH_BY_8) begin + +// if (rst_i[6]) +// force_bl1 = 1'b0; +// else if (mem_init_done && instr_mode_i == 4) +// force_bl1 = 1'b0; + +// else if (((addr_out + cal_blout) >= end_addr_i) || (buf_avail_r <= 50 && PORT_MODE == "RD_MODE")) + +// force_bl1 = 1'b1; + +// else + +// force_bl1 = 1'b0; +//end + +always @(posedge clk_i) begin + + if (rst_i[6]) + + bl_out_reg <= #TCQ fixed_bl_i; + + else if (bl_out_vld) + + bl_out_reg <= #TCQ bl_out; + +end + +// BurstLength defination in Traffic Gen is the consecutive write/read commands + +// that sent to Memory Controller User Interface. In V6, cmd_gen module sends + +// the number of burst length to rd_data_gen, wr_data_gen and mcb_flow_control_v6. + +// The mcb_flow_control takes the base address of the first burst and the bl value, + +// it automatically increment the next consecutive address of the back-to-back commands + +// until the burst counts decrement to 0. + +//verilint STARC-2.2.3.3 off +always @ (posedge clk_i) begin + + if (mode_load_pulse || rst_i[3]) + + if (data_mode_i == 4) + + bl_out <= #TCQ 10'd32 ; + + else + + bl_out <= #TCQ fixed_bl_i ; + + else if (cmd_clk_en) begin + + case({bl_mode_reg}) + + 0: begin + + bl_out[5:0] <= #TCQ bram_bl_i ; + + bl_out[BL_WIDTH-1:6] <= #TCQ 'b0 ; + + + + end + + 1: if (data_mode_i == 4) + + bl_out <= #TCQ 10'd32 ; + + else + + bl_out <= #TCQ fixed_bl_i ; + + 2: bl_out <= #TCQ prbs_brlen; + + default : begin + + bl_out[5:0] <= #TCQ 6'h1; + + bl_out[BL_WIDTH - 1:6] <= #TCQ 'b0; + + + + end + + endcase + + end + +end +//verilint STARC-2.2.3.3 off + + + //synthesis translate_off + +//always @ (bl_out) + +// if(bl_out >2 && FAMILY == "VIRTEX6") begin + +// $display("Error ! Not valid burst length"); + +// $stop; + +// end + + //synthesis translate_on + + + +generate + +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) + + begin: gen_prbs_bl + + mig_7series_v4_2_cmd_prbs_gen # + ( + + .TCQ (TCQ), + + .FAMILY (FAMILY), + + .PRBS_CMD ("BLEN"), + + .ADDR_WIDTH (32), + + .SEED_WIDTH (15), + + .PRBS_WIDTH (20) + + ) + + bl_prbs_gen + + ( + + .clk_i (clk_i), + + .clk_en (cmd_clk_en), + + .prbs_seed_init (load_seed_i), + + .prbs_seed_i (cmd_seed_i[16:2]), + + .prbs_o (prbs_bl) + + ); + + + + always @ (prbs_bl) + + if (FAMILY == "SPARTAN6" || FAMILY == "MCB") // supports 1 throug 64 + + prbs_brlen[5:0] = (prbs_bl[5:1] == 5'b00000) ? 6'b000010: {prbs_bl[5:1],1'b0}; + + else // VIRTEX6 only supports 1 or 2 burst on user ports + + prbs_brlen = (prbs_bl[BL_WIDTH-1:1] == 5'b00000) ? {{BL_WIDTH-2{1'b0}},2'b10}: {prbs_bl[BL_WIDTH-1:1],1'b0}; + + end + + else + + begin: no_gen_prbs_bl + + assign prbs_bl = 'b0; + + end + +endgenerate + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v new file mode 100644 index 0000000..d018c52 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen.v @@ -0,0 +1,268 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: cmd_prbs_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This moduel use LFSR to generate random address, isntructions +// or burst_length. +//Reference: +//Revision History: 1.1 7/9/2009 Added condition to zero out the LSB address bits according to +// DWIDTH and FAMILY. 7/9/2009 +// 1.2 11/8/2010 Fixed the PRBS Address generation. +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_cmd_prbs_gen # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter MEM_BURST_LEN = 8, + parameter ADDR_WIDTH = 29, + parameter DWIDTH = 32, + parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS" + parameter PRBS_WIDTH = 64, // 64,15,20 + parameter SEED_WIDTH = 32, // 32,15,4 + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + parameter PRBS_EADDR = 32'h00002000, + parameter PRBS_SADDR = 32'h00002000 + ) + ( + input clk_i, + input prbs_seed_init, // when high the prbs_x_seed will be loaded + input clk_en, + input [SEED_WIDTH-1:0] prbs_seed_i, + + output[SEED_WIDTH-1:0] prbs_o // generated address + ); + +wire[ADDR_WIDTH - 1:0] ZEROS; +reg [SEED_WIDTH - 1:0] prbs; +reg [PRBS_WIDTH :1] lfsr_q; + +assign ZEROS = 'b0; + + +function integer logb2; + input integer number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end +endfunction + + +// +//************************************************************** +//#################################################################################################################### +// # +// # +// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} # +// upper 32 bits are loadable # +// # +// +// +// ........................................................................................ +// ^ ^ ^ ^ | +// | ____ | ___ ___ | ___ | ___ ___ ___ | +// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable. +// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<-- +// |___| --- |___| |___| --- |___| --- |___|...|___| |___| +// +// +// <<-- shifting -- +//##################################################################################################################### + +// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages. +// we need to provide 30 bits addres. SRLC32 has only one bit output. +// address seed will be loaded to upper 32 bits. +// +// parallel load and serial shift out to LFSR during INIT time + +generate + if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) + begin :gen64_taps + always @ (posedge clk_i) begin + if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {31'b0,prbs_seed_i}; + end else if(clk_en) begin + lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63]; + lfsr_q[63] <= #TCQ lfsr_q[62]; + lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61]; + lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60]; + lfsr_q[60:2] <= #TCQ lfsr_q[59:1]; + lfsr_q[1] <= #TCQ lfsr_q[64]; + end + end + + always @(lfsr_q[32:1]) begin + prbs = lfsr_q[32:1]; + end + end +//endgenerate +//generate +else if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) + begin :gen32_taps + always @ (posedge clk_i) begin + if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {prbs_seed_i}; + end else if(clk_en) begin + lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + end + end + + integer i; + always @(lfsr_q[32:1]) begin + + if (FAMILY == "SPARTAN6" ) begin // for 32 bits + + for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1) + + if(PRBS_SADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; + else if(PRBS_EADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; + else + prbs[i] = lfsr_q[i+1]; + + prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}}; + + end + else begin + for(i = logb2(MEM_BURST_LEN) - 2; i <= SEED_WIDTH - 1; i = i + 1) + // for(i = 3; i <= SEED_WIDTH - 1; i = i + 1) + +// BL8: 0,8 +//BL4: incremnt by 4 +// for(i = 3; i <= SEED_WIDTH - 1; i = i + 1) + + if(PRBS_SADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; + else if(PRBS_EADDR_MASK_POS[i] == 0) + prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; + else + prbs[i] = 1'b0;// lfsr_q[i+1]; + // 3 1 + prbs[logb2(MEM_BURST_LEN)-3:0] = 'b0;//{logb2(MEM_BURST_LEN) -3{1'b0}}; + // prbs[2:0] = {3{1'b0}}; + + + end + + end +end +//endgenerate + +////////////////////////////////////////////////////////////////////////// +//#################################################################################################################### +// # +// # +// 15 taps: [15,14]: # +// # +// # +// +// +// ............................................................. +// ^ ^ . ^ +// | ____ | ___ ___ ___ ___ ___ | +// | | | |---|<- | | | | | |...| | | | | +// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<-- +// |___| --- |___| |___| |___|...|___| |___| +// +// +// <<-- shifting -- +//##################################################################################################################### + +//generate +// if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") +else + begin :gen20_taps + always @(posedge clk_i) begin + if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]}; + end else if(clk_en) begin + lfsr_q[20] <= #TCQ lfsr_q[19]; + lfsr_q[19] <= #TCQ lfsr_q[18]; + + lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17]; + + lfsr_q[17:2] <= #TCQ lfsr_q[16:1]; + lfsr_q[1] <= #TCQ lfsr_q[20]; + end + end + + always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin + prbs = {ZEROS[SEED_WIDTH - 1:6],lfsr_q[6:1]}; + end + end +endgenerate + +assign prbs_o = prbs; + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v new file mode 100644 index 0000000..70f5039 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_data_prbs_gen.v @@ -0,0 +1,128 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: data_prbs_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module is used LFSR to generate random data for memory +// data write or memory data read comparison.The first data is +// seeded by the input prbs_seed_i which is connected to memory address. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_data_prbs_gen # + ( + parameter TCQ = 100, + + parameter EYE_TEST = "FALSE", + parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" + parameter SEED_WIDTH = 32 + ) + ( + input clk_i, + input clk_en, + input rst_i, + input prbs_seed_init, // when high the prbs_x_seed will be loaded + input [PRBS_WIDTH - 1:0] prbs_seed_i, + + output [PRBS_WIDTH - 1:0] prbs_o // generated address + ); + +reg [PRBS_WIDTH - 1 :0] prbs; +reg [PRBS_WIDTH :1] lfsr_q; +integer i; + + + +always @ (posedge clk_i) +begin + if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up +// if (rst_i ) //reset it to a known good state to prevent it locks up + + begin + lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; + // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; + + lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; + end + else if (clk_en) begin + + lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + + + end +end + +always @ (lfsr_q[PRBS_WIDTH:1]) begin + prbs = lfsr_q[PRBS_WIDTH:1]; +end + +assign prbs_o = prbs; + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_init_mem_pattern_ctr.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_init_mem_pattern_ctr.v new file mode 100644 index 0000000..4fd543b --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_init_mem_pattern_ctr.v @@ -0,0 +1,2117 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: init_mem_pattern_ctr.v +// /___/ /\ Date Last Modified: $Date: 2011/02/24 00:08:32 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This moduel has a small FSM to control the operation of +// memc_traffic_gen module.It first fill up the memory with a selected +// DATA pattern and then starts the memory testing state. +//Reference: +//Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE +// and the fixed_bl_o is fixed at 64 if data_mode_o == PRBA and FAMILY == "SPARTAN6" +// The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH. +// 1.2 10-1-2009 Added parameter TST_MEM_INSTR_MODE to select instruction pattern during +// memory testing phase. +// 1.3 1-4-2012 Fixed end address logic if defined END_ADDRESS == 0x0FFFFFFF. +//***************************************************************************** + + + +`timescale 1ps/1ps + + + + + + + + + + + +module mig_7series_v4_2_init_mem_pattern_ctr # + + ( + + parameter SIMULATION = "FALSE", + + parameter TCQ = 100, + + parameter FAMILY = "SPARTAN6", // VIRTEX6, SPARTAN6 + + parameter MEM_TYPE = "DDR3",//DDR3,DDR2, QDR2PLUS, + + + + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands: + + // "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE" + + // "R_W_INSTR_MODE", "RP_WP_INSTR_MODE + + // "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE" + + // ******************************* + + // Virtex 6 Available commands: + + // "FIXED_INSTR_R_MODE" - Only Read commands will be generated. + + // "FIXED_INSTR_W_MODE" -- Only Write commands will be generated. + + // "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated + + // with lower 10 bits address in sequential increment. + + // This mode is for Read Eye measurement. + + + + // "R_W_INSTR_MODE" - Random Read/Write commands will be generated. + + parameter MEM_BURST_LEN = 8, // VIRTEX 6 Option. + + parameter nCK_PER_CLK = 4, + + parameter BL_WIDTH = 10, + + parameter NUM_DQ_PINS = 4, // Total number of memory dq pins in the design. + + + + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_ALL" option generates all available + + // commands pattern. + + parameter BEGIN_ADDRESS = 32'h00000000, + + parameter END_ADDRESS = 32'h00000fff, + + parameter ADDR_WIDTH = 30, + + parameter DWIDTH = 32, + + parameter CMD_SEED_VALUE = 32'h12345678, + + parameter DATA_SEED_VALUE = 32'hca345675, + + parameter DATA_MODE = 4'b0010, + + parameter PORT_MODE = "BI_MODE", // V6 Option: "BI_MODE"; SP6 Option: "WR_MODE", "RD_MODE", "BI_MODE" + + parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory + + // signals. It overwrites the TST_MEM_INSTR_MODE setting. + + // Traffic Generator will onlywrite to one single location and no + + // read transactions will be generated. + + + + + + ) + + ( + + input clk_i, + + input rst_i, + + + + input single_write_button, + + input single_read_button, + + input slow_write_read_button, + + input single_operation, // tie this signal to '1' if want to do single operation + + + + input memc_cmd_en_i, + + input memc_wr_en_i, + + input vio_modify_enable, // 0: default to ADDR as DATA PATTERN. No runtime change in data mode. + + // 1: enable exteral VIO to control the data_mode pattern + + input [3:0] vio_instr_mode_value, // "0000" = Fixed + + // "0001" = bram; takes instruction from bram output + + // "0010" = R/W + + // "0011" = RP/WP + + // "0100" = R/RP/W/WP + + // "0101" = R/RP/W/WP/REF + + // "0111" = Single Step + + + + // and address mode pattern during runtime. + + input [3:0] vio_data_mode_value, + + input [2:0] vio_addr_mode_value, + + + + + + + + + + + + + + input [1:0] vio_bl_mode_value, + + input vio_data_mask_gen, + + input [2:0] vio_fixed_instr_value, + + input [BL_WIDTH - 1:0] vio_fixed_bl_value, // valid range is: from 1 to 64. + + + + input memc_init_done_i, + + input cmp_error, + + output reg run_traffic_o, + + // runtime parameter + + output [31:0] start_addr_o, // define the start of address + + output [31:0] end_addr_o, + + output [31:0] cmd_seed_o, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen + + output [31:0] data_seed_o, + + output reg load_seed_o, // + + // upper layer inputs to determine the command bus and data pattern + + // internal traffic generator initialize the memory with + + output reg [2:0] addr_mode_o, // "00" = bram; takes the address from bram output + + // "001" = fixed address from the fixed_addr input + + // "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR + + // "011" = sequential + + + + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + + output reg [3:0] instr_mode_o, // "0000" = Fixed + + // "0001" = bram; takes instruction from bram output + + // "0010" = R/W + + // "0011" = RP/WP + + // "0100" = R/RP/W/WP + + // "0101" = R/RP/W/WP/REF + + // "0111" = Single Step + + // "1111" = Debug Read Only, bypass memory initialization + + + + output reg [1:0] bl_mode_o, // "00" = bram; takes the burst length from bram output + + // "01" = fixed , takes the burst length from the fixed_bl input + + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + + + output reg [3:0] data_mode_o, // "00" = bram; + + // "01" = fixed data from the fixed_data input + + // "10" = psuedo ramdom pattern; generated from internal 32 bit LFSR + + // "11" = sequential using the addrs as the starting data pattern + + output reg mode_load_o, + + + + // fixed pattern inputs interface + + output reg [BL_WIDTH-1:0] fixed_bl_o, // range from 1 to 64 + + output reg [2:0] fixed_instr_o, //RD 3'b001 + + //RDP 3'b011 + + //WR 3'b000 + + //WRP 3'b010 + + //REFRESH 3'b100 + + output reg mem_pattern_init_done_o + + + + ); + + + + //FSM State Defination + +parameter IDLE = 8'b00000001, + + + + INIT_MEM_WRITE = 8'b00000010, + + INIT_MEM_READ = 8'b00000100, + + TEST_MEM = 8'b00001000, + + SINGLE_STEP_WRITE = 8'b00010000, //0x10 + + SINGLE_STEP_READ = 8'b00100000, //0x20 + + CMP_ERROR = 8'b01000000, + + SINGLE_CMD_WAIT = 8'b10000000; + + + + + +localparam BRAM_ADDR = 3'b000; + +localparam FIXED_ADDR = 3'b001; + +localparam PRBS_ADDR = 3'b010; + +localparam SEQUENTIAL_ADDR = 3'b011; + + + +localparam BRAM_INSTR_MODE = 4'b0000; + +localparam FIXED_INSTR_MODE = 4'b0001; + +localparam R_W_INSTR_MODE = 4'b0010; + +localparam RP_WP_INSTR_MODE = 4'b0011; + +localparam R_RP_W_WP_INSTR_MODE = 4'b0100; + +localparam R_RP_W_WP_REF_INSTR_MODE = 4'b0101; + + + +localparam BRAM_BL_MODE = 2'b00; + +localparam FIXED_BL_MODE = 2'b01; + +localparam PRBS_BL_MODE = 2'b10; + + + +localparam BRAM_DATAL_MODE = 4'b0000; + +localparam FIXED_DATA_MODE = 4'b0001; + +localparam ADDR_DATA_MODE = 4'b0010; + +localparam HAMMER_DATA_MODE = 4'b0011; + +localparam NEIGHBOR_DATA_MODE = 4'b0100; + +localparam WALKING1_DATA_MODE = 4'b0101; + +localparam WALKING0_DATA_MODE = 4'b0110; + +localparam PRBS_DATA_MODE = 4'b0111; + + + +// type fixed instruction + +localparam RD_INSTR = 3'b001; + +localparam RDP_INSTR = 3'b011; + +localparam WR_INSTR = 3'b000; + + + +localparam WRP_INSTR = 3'b010; + +localparam REFRESH_INSTR = 3'b100; + +localparam NOP_WR_INSTR = 3'b101; + +//(* FSM_ENCODING="USER" *) reg [6:0] STATE = current_state; + +reg [7:0] current_state; + +reg [7:0] next_state; + +reg memc_init_done_reg; + +reg AC2_G_E2,AC1_G_E1,AC3_G_E3; + +reg upper_end_matched; + +reg [31:0] end_boundary_addr; + + + +reg memc_cmd_en_r; + +reg lower_end_matched; + +reg end_addr_reached; + +reg run_traffic; + +reg bram_mode_enable; + +reg [31:0] current_address; + +reg [BL_WIDTH-1:0] fix_bl_value; + +reg [3:0] data_mode_sel; + +reg [1:0] bl_mode_sel; + +reg [2:0] addr_mode; + +reg [10:0] INC_COUNTS; + +wire [3:0] test_mem_instr_mode; + +reg pre_instr_switch; + +reg switch_instr; + +reg memc_wr_en_r; + +reg mode_load_d1,mode_load_d2,mode_load_pulse; + +reg mode_load_d3,mode_load_d4,mode_load_d5; + + + +always @ (posedge clk_i) begin + + mode_load_d1 <= #TCQ mode_load_o; + + mode_load_d2 <= #TCQ mode_load_d1; + + mode_load_d3 <= #TCQ mode_load_d2; + + mode_load_d4 <= #TCQ mode_load_d3; + + mode_load_d5 <= #TCQ mode_load_d4; + + + +end + + + +always @ (posedge clk_i) + + mode_load_pulse <= #TCQ mode_load_d4 & ~mode_load_d5; + + + + + +always @ (TST_MEM_INSTR_MODE, EYE_TEST) + +if ((TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || TST_MEM_INSTR_MODE == "R_W_INSTR_MODE" || + + TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" || TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" || + + TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" || TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE" ) + + && (EYE_TEST == "TRUE")) + +begin: Warning_Message1 + +$display("Invalid Parameter setting! When EYE_TEST is set to TRUE, only WRITE commands can be generated."); + + + +$stop; + +end + +else + +begin: NoWarning_Message1 + + + +end + +always @ (TST_MEM_INSTR_MODE) + +if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "SPARTAN6") + +begin + +$display("Error ! Not supported test instruction mode in Spartan 6"); + + + +$stop; + +end + +else + +begin + + // dummy + +end + + + + + + + +always @ (vio_fixed_bl_value,vio_data_mode_value) + +if (vio_fixed_bl_value[6:0] > 7'd64 && FAMILY == "SPARTAN6") + +begin + +$display("Error ! Maximum User Burst Length is 64"); + +$display("Change a smaller burst size"); + + + +$stop; + +end + +else if ((vio_data_mode_value == 4'h6 || vio_data_mode_value == 4'h5) && FAMILY == "VIRTEX6") + +begin + + $display("Data DQ bus Walking 1's test."); + + $display("A single DQ bit is set to 1 and walk through entire DQ bus to test "); + + $display("if each DQ bit can be set to 0 or 1 "); + + + + if (NUM_DQ_PINS == 8)begin + + $display("Warning ! Fixed Burst Length in this mode is forced to 64"); + + $display("to ensure '1' always appear on DQ0 of each beginning User Burst"); + + end + + else begin + + $display("Warning ! Fixed Burst Length in this mode is forced to equal to NUM_DQ_PINS"); + + $display("to ensure '1' always appear on DQ0 of each beginning User Burst"); + + end + + + +end + +else + +begin// dummy + + + +end + + + +always @ (data_mode_o) + +if (data_mode_o == 4'h7 && FAMILY == "SPARTAN6") + +begin + + $display("Error ! Hammer PRBS is not support in MCB-like interface"); + + $display("Set value to 4'h8 for Psuedo PRBS"); + + $stop; + +end + + + +else + +begin + + // dummy + +end + + + +//always @ (vio_data_mode_value,TST_MEM_INSTR_MODE) + +//if (TST_MEM_INSTR_MODE != "FIXED_INSTR_R_MODE" && + +// vio_data_mode_value == 4'b1000) + +//begin + +//$display("Error ! The selected PRBS data pattern has to run together with FIXED_INSTR_R_MODE"); + +//$display("Set the TST_MEM_INSTR_MODE = FIXED_INSTR_R_MODE and addr_mode to sequential mode"); + +//$stop; + +//end + + + +assign test_mem_instr_mode = (vio_instr_mode_value[3:2] == 2'b11) ? 4'b1111: + + (vio_instr_mode_value[3:2] == 2'b10) ? 4'b1011: + + (TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE") ? 4'b0000: + + (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || + + TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") ? 4'b0001: + + (TST_MEM_INSTR_MODE == "R_W_INSTR_MODE") ? 4'b0010: + + (TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0011: + + (TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0100: + + (TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0101: + + 4'b0010; + + + + + + + + always @ (posedge clk_i) + + begin + + if (data_mode_o == 4) + + begin + + fix_bl_value[4:0] <= 5'd8;//Simple_Data_MODE; + + fix_bl_value[BL_WIDTH-1:5] <= 'b0; + + end + + else if (data_mode_o == 5 || data_mode_o == 6 ) + if (MEM_TYPE == "RLD3" && vio_modify_enable) + fix_bl_value <= vio_fixed_bl_value; + else + + if (NUM_DQ_PINS == 8) + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + end + + else + + fix_bl_value <= NUM_DQ_PINS;//Waling 1's or 0's; + + else if (data_mode_o == 8) + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + + + end + + + + else if (vio_modify_enable == 1'b1) + + if (vio_fixed_bl_value == 0) // not valid value; + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + + + end + + else begin + + fix_bl_value <= vio_fixed_bl_value; + + + + end + + else + + begin + + fix_bl_value[6:0] <= 7'b1000000; + + + + fix_bl_value[BL_WIDTH-1:7] <= 'b0; + + + + + + end + + + + end + + + + + +generate + +if (FAMILY == "SPARTAN6" ) + +begin : INC_COUNTS_S + + + +always @ (posedge clk_i) + + INC_COUNTS <= (DWIDTH/8); + +end + +else // VIRTEX 6 + +begin : INC_COUNTS_V + +always @ (posedge clk_i) + if (MEM_TYPE == "QDR2PLUS") + INC_COUNTS <= 1;// Each address is associated with 4 words in QDR2. + else + INC_COUNTS <= MEM_BURST_LEN; +end + +endgenerate + + + + + +// In V6, each write command in MEM_BLEN = 8, TG writes 8 words of DQ width data to the accessed location. + +// For MEM_BLEN = 4, TG writes 4 words of DQ width data to the accessed location. + +reg Cout_b; + +always @ (posedge clk_i) + +begin + +if (rst_i) + + current_address <= BEGIN_ADDRESS; + +else if (memc_wr_en_r && (current_state == INIT_MEM_WRITE && (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")) + + || (memc_wr_en_r && (current_state == IDLE && PORT_MODE == "RD_MODE")) ) + +// ** current_address stops incrementing when reaching the beginning of last END_ADDRESS write burst. + {Cout_b,current_address} <= current_address + INC_COUNTS; + +else + + current_address <= current_address; + + + +end + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + AC3_G_E3 <= 1'b0; + + else if (current_address[29:24] >= end_boundary_addr[29:24]) + + AC3_G_E3 <= 1'b1; + + else + + AC3_G_E3 <= AC3_G_E3; + + + + if (rst_i) + + AC2_G_E2 <= 1'b0; + + else if (current_address[23:16] >= end_boundary_addr[23:16]) + AC2_G_E2 <= AC3_G_E3; + + else + + AC2_G_E2 <= AC2_G_E2; + + + + + + if (rst_i) + + AC1_G_E1 <= 1'b0; + + else if (current_address[15:8] >= end_boundary_addr[15:8] ) + AC1_G_E1 <= AC2_G_E2 & AC3_G_E3; + +else + + AC1_G_E1 <= AC1_G_E1; + + + + + +end + +always @(posedge clk_i) + +begin + +if (rst_i) + + upper_end_matched <= 1'b0; + + + +else if (memc_cmd_en_i) + + upper_end_matched <= AC3_G_E3 & AC2_G_E2 & AC1_G_E1; + +else + + upper_end_matched <= upper_end_matched; + + + +end + + + + + + //synthesis translate_off + +always @ (fix_bl_value) + + if(fix_bl_value * MEM_BURST_LEN > END_ADDRESS) + + begin + + $display("Error ! User Burst Size goes beyond END Address"); + + $display("decrease vio_fixed_bl_value or increase END Address range"); + + $stop; + + end + + else + + begin + + // dummy + + + + end + + + + + +always @ (vio_data_mode_value, vio_data_mask_gen) + + if(vio_data_mode_value != 4'b0010 && vio_data_mask_gen) + + begin + + $display("Error ! Data Mask Generation only supported in Data Mode = Address as Data"); + + $stop; + + end + + else + + begin + + // dummy + + + + end + + + + //synthesis translate_on + + + +reg COuta; + +always @(posedge clk_i) + +begin + // **end_boundary_addr defination is the beginning address of the last write burst of END_ADDRESS + {COuta,end_boundary_addr} <= (END_ADDRESS[31:0] - {{32-BL_WIDTH{1'b0}} ,fix_bl_value } +1) ; + +end + + + + + + + +always @(posedge clk_i) + +begin + + if ((current_address[7:4] >= END_ADDRESS[7:4]) && MEM_TYPE == "QDR2PLUS") + + + + lower_end_matched <= 1'b1; + + + + else if ((current_address[7:0] >= end_boundary_addr[7:0]) && MEM_TYPE != "QDR2PLUS") + + + + lower_end_matched <= 1'b1; + + else + + lower_end_matched <= 1'b0; + + + +end + + + + + + + +always @(posedge clk_i) + +begin + + if (rst_i) + + pre_instr_switch <= 1'b0; + + + +else if (current_address[7:0] >= end_boundary_addr[7:0] ) // V6 send a seed address to memc_flow_ctr + + pre_instr_switch <= 1'b1; + + + +end + + + + + +always @(posedge clk_i) + +begin + + + + //if (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6" && MEM_TYPE == "QDR2PLUS") + + // end_addr_reached <= 1'b1; + + + + if ((upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 32) || + + (upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 64) || + + (upper_end_matched && DWIDTH == 128 && FAMILY == "SPARTAN6") || + + (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6")) + + end_addr_reached <= 1'b1; + + else + + end_addr_reached <= 1'b0; + + + +end + + + +always @(posedge clk_i) + +begin + + if ((upper_end_matched && pre_instr_switch && FAMILY == "VIRTEX6")) + + switch_instr <= 1'b1; + + else + + switch_instr <= 1'b0; + + + +end + + + + + + always @ (posedge clk_i) + + begin + + memc_wr_en_r <= memc_wr_en_i; + + memc_init_done_reg <= memc_init_done_i; + +end + + + + always @ (posedge clk_i) + + run_traffic_o <= run_traffic; + + + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i) + + current_state <= 5'b00001; + + else + + current_state <= next_state; + + end + + + + assign start_addr_o = BEGIN_ADDRESS;//BEGIN_ADDRESS; + + assign end_addr_o = END_ADDRESS; + + assign cmd_seed_o = CMD_SEED_VALUE; + + assign data_seed_o = DATA_SEED_VALUE; + + + + + +// + +always @ (posedge clk_i) + +begin + + if (rst_i) + + mem_pattern_init_done_o <= 1'b0; + else if (current_address >= end_boundary_addr ) + + mem_pattern_init_done_o <= 1'b1; + +end + + + +reg [3:0] syn1_vio_data_mode_value; + +reg [2:0] syn1_vio_addr_mode_value; + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i) begin + + syn1_vio_data_mode_value <= 4'b0011; + + syn1_vio_addr_mode_value <= 3'b011; + + end + + else if (vio_modify_enable == 1'b1) begin + + syn1_vio_data_mode_value <= vio_data_mode_value; + + syn1_vio_addr_mode_value <= vio_addr_mode_value; + + end + + end + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i) begin + + data_mode_sel <= DATA_MODE;//ADDR_DATA_MODE; + + end + + else if (vio_modify_enable == 1'b1) begin + + data_mode_sel <= syn1_vio_data_mode_value; + + end + + end + + + + + + + + always @ (posedge clk_i) + + begin + + if (rst_i ) + + bl_mode_sel <= FIXED_BL_MODE; + + else if (test_mem_instr_mode[3]) + + bl_mode_sel <= 2'b11; + + else if (vio_modify_enable == 1'b1) begin + + bl_mode_sel <= vio_bl_mode_value; + + end + + end + + + + + + always @ (posedge clk_i) + + begin + + // whenever vio_instr_mode_value[3] == 1'b1, TG expects reading back phy calibration data pattern + + // which is: 0xFF, 0x00, 0xAA,0x55, 0x55, 0xAA, 0x99 and 0x66. + + if (vio_modify_enable) + + if (vio_instr_mode_value == 4'h7) + + data_mode_o <= 4'h1; // fixed data input + + else + + data_mode_o <= (test_mem_instr_mode[3]) ? 4'b1000: data_mode_sel; + + else + + data_mode_o <= DATA_MODE; + + + + + + addr_mode_o <= (test_mem_instr_mode[3]) ? 3'b000: addr_mode ; + + + + // assuming if vio_modify_enable is enabled and vio_addr_mode_value is set to zero + + // user wants to have bram interface. + + if (syn1_vio_addr_mode_value == 0 && vio_modify_enable == 1'b1) + + bram_mode_enable <= 1'b1; + + else + + bram_mode_enable <= 1'b0; + + + + end + +reg single_write_r1,single_write_r2,single_read_r1,single_read_r2; + +reg single_instr_run_trarric; + +reg slow_write_read_button_r1,slow_write_read_button_r2; + +reg toggle_start_stop_write_read; + +wire int_single_wr,int_single_rd; + +reg [8:0] write_read_counter; + +always @ (posedge clk_i) + +begin + + if (rst_i) begin + + write_read_counter <= 'b0; + + slow_write_read_button_r1 <= 1'b0; + + slow_write_read_button_r2 <= 1'b0; + + + + toggle_start_stop_write_read <= 1'b0; + + end + + else begin + + write_read_counter <= write_read_counter + 1; + + slow_write_read_button_r1 <= slow_write_read_button; + + slow_write_read_button_r2 <= slow_write_read_button_r1; + + + + if (~slow_write_read_button_r2 && slow_write_read_button_r1) + + toggle_start_stop_write_read <= ~toggle_start_stop_write_read; + + + + end + +end + + + +assign int_single_wr = write_read_counter[8]; + +assign int_single_rd = ~write_read_counter[8]; + + + + + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + begin + + single_write_r1 <= 1'b0; + + single_write_r2 <= 1'b0; + + single_read_r1 <= 1'b0; + + single_read_r2 <= 1'b0; + + + + end + + else begin + + single_write_r1 <= single_write_button | (int_single_wr & toggle_start_stop_write_read); + + single_write_r2 <= single_write_r1 ; + + single_read_r1 <= single_read_button | (int_single_rd & toggle_start_stop_write_read); + + single_read_r2 <= single_read_r1 ; + + end + +end + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + single_instr_run_trarric <= 1'b0; + + else if ((single_write_r1 && ~single_write_r2) || (single_read_r1 && ~single_read_r2)) + + single_instr_run_trarric <= 1'b1; + + else if (mode_load_o) + + single_instr_run_trarric <= 1'b0; + +end + + + + + +always @ (posedge clk_i) + +begin + + if (rst_i) + + run_traffic <= 1'b0; + + else if ((current_state == SINGLE_CMD_WAIT ) || (current_state == SINGLE_STEP_WRITE ) || (current_state == SINGLE_STEP_READ )) + + run_traffic <= single_instr_run_trarric; + + else if ((current_state == SINGLE_CMD_WAIT ) ) + + run_traffic <= 1'b0; + + + + else if ( (current_state != IDLE)) + + run_traffic <= 1'b1; + + else + + run_traffic <= 1'b0; + + + +end + + + + + +always @ (*) + +begin + + load_seed_o = 1'b0; + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + addr_mode = 'b0; + + else + + addr_mode = SEQUENTIAL_ADDR; + + + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + instr_mode_o = 'b0; + + else + + instr_mode_o = FIXED_INSTR_MODE; + + + + + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + bl_mode_o = 'b0; + + else + + bl_mode_o = FIXED_BL_MODE; + + + + + + if (vio_modify_enable) + + if (vio_instr_mode_value == 7) + + fixed_bl_o = 10'd1; + + else if (data_mode_o[2:0] == 3'b111) + + if (FAMILY == "VIRTEX6") + + fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256. + + else + + fixed_bl_o = 10'd64; + + else + + if (FAMILY == "VIRTEX6") + + fixed_bl_o = vio_fixed_bl_value; + + // PRBS mode + + else if (data_mode_o[3:0] == 4'b1000 && FAMILY == "SPARTAN6") + + fixed_bl_o = 10'd64; // + + + + else + + fixed_bl_o = fix_bl_value; + + else + + fixed_bl_o = fix_bl_value; + + + + // fixed_bl_o = 10'd64; + + // fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256. + + + + mode_load_o = 1'b0; + + // run_traffic = 1'b0; + + next_state = IDLE; + + + + if (PORT_MODE == "RD_MODE") + + fixed_instr_o = RD_INSTR; + + + + else //if( PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") + + fixed_instr_o = WR_INSTR; + + + + + +case(current_state) + + IDLE: + + begin + + if(memc_init_done_reg ) //rdp_rdy_i comes from read_data path + + begin + + + + if (vio_instr_mode_value == 4'h7 && single_write_r1 && ~single_write_r2) + + begin + + next_state = SINGLE_STEP_WRITE; + + mode_load_o = 1'b1; + + // run_traffic = 1'b1; + + load_seed_o = 1'b1; + + end + + + + else if (vio_instr_mode_value == 4'h7 && single_read_r1 && ~single_read_r2) + + begin + + next_state = SINGLE_STEP_READ; + + mode_load_o = 1'b1; + + // run_traffic = 1'b1; + + load_seed_o = 1'b1; + + end + + + + + + + + else if ((PORT_MODE == "WR_MODE" || (PORT_MODE == "BI_MODE" && test_mem_instr_mode[3:2] != 2'b11)) && + + vio_instr_mode_value != 4'h7 ) // normal test mode + + begin + + next_state = INIT_MEM_WRITE; + + mode_load_o = 1'b1; + + // run_traffic = 1'b0; + + load_seed_o = 1'b1; + + end + + else if ((PORT_MODE == "RD_MODE" && end_addr_reached || (test_mem_instr_mode == 4'b1111)) && + + vio_instr_mode_value != 4'h7 ) + + begin + + next_state = TEST_MEM; + + mode_load_o = 1'b1; + + // run_traffic = 1'b1; + + load_seed_o = 1'b1; + + end + + else + + begin + + next_state = IDLE; + + // run_traffic = 1'b0; + + load_seed_o = 1'b0; + + + + end + + + + end + + else + + begin + + next_state = IDLE; + + // run_traffic = 1'b0; + + load_seed_o = 1'b0; + + + + end + + + + end + + SINGLE_CMD_WAIT: begin + + if (single_operation&& single_read_r1 && ~single_read_r2) + + next_state = SINGLE_STEP_READ; + + else + + next_state = SINGLE_CMD_WAIT; + + + + fixed_instr_o = RD_INSTR; + + addr_mode = FIXED_ADDR; + + bl_mode_o = FIXED_BL_MODE; + + + + mode_load_o = 1'b0; + + load_seed_o = 1'b0; + + end + + SINGLE_STEP_WRITE: begin + + + + // run_traffic = single_instr_run_trarric; + + + + + + if (memc_cmd_en_i) + + next_state = IDLE; + + + + else + + next_state = SINGLE_STEP_WRITE; + + + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + addr_mode = FIXED_ADDR; + + bl_mode_o = FIXED_BL_MODE; + + + + fixed_instr_o = WR_INSTR; + + + + end + + + + SINGLE_STEP_READ: begin //0x20 + + + + // run_traffic = single_instr_run_trarric; + + if (single_operation) + + next_state = SINGLE_CMD_WAIT; + + + + else if (memc_cmd_en_i) + + next_state = IDLE; + + else + + next_state = SINGLE_STEP_READ; + + + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + // run_traffic = 1'b1; + + addr_mode = FIXED_ADDR; + + bl_mode_o = FIXED_BL_MODE; + + + + fixed_instr_o = RD_INSTR; + + + + end + + + + INIT_MEM_WRITE: begin + + + + + + + + if (end_addr_reached && EYE_TEST == "FALSE" ) + + begin + + next_state = TEST_MEM; + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + // run_traffic = 1'b1; + + + + end + + else + + begin + + next_state = INIT_MEM_WRITE; + + // run_traffic = 1'b1; + + mode_load_o = 1'b0; + + load_seed_o = 1'b0; + + if (EYE_TEST == "TRUE") + + addr_mode = FIXED_ADDR; + + else if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + addr_mode = 'b0; + + else + + addr_mode = SEQUENTIAL_ADDR; + + + + + + if (switch_instr && TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE") + + fixed_instr_o = RD_INSTR; + + else + + + + fixed_instr_o = WR_INSTR; + + + + end + + + + end + + + + INIT_MEM_READ: begin + + + + if (end_addr_reached ) + + begin + + next_state = TEST_MEM; + + mode_load_o = 1'b1; + + load_seed_o = 1'b1; + + + + end + + else + + begin + + next_state = INIT_MEM_READ; + + // run_traffic = 1'b0; + + mode_load_o = 1'b0; + + load_seed_o = 1'b0; + + + + end + + + + end + + TEST_MEM: begin + + if (single_operation) + + next_state = SINGLE_CMD_WAIT; + + else if (cmp_error) + + next_state = TEST_MEM;//CMP_ERROR; + + + + else + + next_state = TEST_MEM; + + // run_traffic = 1'b1; + + + + if (vio_modify_enable) + + fixed_instr_o = vio_fixed_instr_value; + + else if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") + + fixed_instr_o = WR_INSTR; + + else if (PORT_MODE == "BI_MODE" && ( TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || + + TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE")) + + fixed_instr_o = RD_INSTR; + + else if (PORT_MODE == "RD_MODE") + + fixed_instr_o = RD_INSTR; + + + + else //if( PORT_MODE == "WR_MODE") + + fixed_instr_o = WR_INSTR; + + + + + + + + if ((data_mode_o == 3'b111) && FAMILY == "VIRTEX6") + + fixed_bl_o = 10'd256; + + else if ((FAMILY == "SPARTAN6")) + + fixed_bl_o = 10'd64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64. + + else + + fixed_bl_o = fix_bl_value; + + + + + + if (data_mode_o == 3'b111) + + bl_mode_o = FIXED_BL_MODE; + + + + else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") + + bl_mode_o = FIXED_BL_MODE; + + else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110) + + // simplify the downstream logic, data_mode is forced to FIXED_BL_MODE + + // if data_mode is set to Walking 1's or Walking 0's. + + bl_mode_o = FIXED_BL_MODE; + + else + + bl_mode_o = bl_mode_sel ; + + + + /* if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") + + addr_mode = SEQUENTIAL_ADDR; + + else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110) + + // simplify the downstream logic, addr_mode is forced to SEQUENTIAL + + // if data_mode is set to Walking 1's or Walking 0's. + + // This ensure the starting burst address always in in the beginning + + // of burst_length address for the number of DQ pins.And to ensure the + + // DQ0 always asserts at the beginning of each user burst. + + addr_mode = SEQUENTIAL_ADDR; + + else if (bl_mode_o == PRBS_BL_MODE) + + addr_mode = PRBS_ADDR; + + else + + addr_mode = 3'b010;*/ + + + + addr_mode = vio_addr_mode_value; + + + + if (vio_modify_enable ) + + instr_mode_o = vio_instr_mode_value; + + + + else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "VIRTEX6") + + instr_mode_o = FIXED_INSTR_MODE; + + else if(PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE != "FIXED_INSTR_R_EYE_MODE") + + if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + instr_mode_o = BRAM_INSTR_MODE; + + else + + instr_mode_o = test_mem_instr_mode;//R_RP_W_WP_REF_INSTR_MODE;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;// + + else //if (PORT_MODE == "RD_MODE" || PORT_MODE == "WR_MODE") begin + + instr_mode_o = FIXED_INSTR_MODE; + + + + end + + + + + + CMP_ERROR: + + begin + + next_state = CMP_ERROR; + + bl_mode_o = bl_mode_sel;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE; + + fixed_instr_o = RD_INSTR; + + addr_mode = SEQUENTIAL_ADDR;//PRBS_ADDR;//PRBS_ADDR;//PRBS_ADDR;//SEQUENTIAL_ADDR; + + if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + + instr_mode_o = BRAM_INSTR_MODE;// + + else + + instr_mode_o = test_mem_instr_mode;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;// + + + + // run_traffic = 1'b1; // ?? keep it running or stop if error happened + + + + end + + default: + + begin + + next_state = IDLE; + + //run_traffic = 1'b0; + + + + end + + + + endcase + + end + + + + + + + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_flow_vcontrol.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_flow_vcontrol.v new file mode 100644 index 0000000..63f4dcd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_flow_vcontrol.v @@ -0,0 +1,503 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: mcb_flow_control.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:21 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Virtex 6 +//Design Name: DDR2/DDR3 +//Purpose: This module is the main flow control between cmd_gen.v, +// write_data_path and read_data_path modules. +//Reference: +//Revision History: 7/29/10 Support V6 Back-to-back commands over user interface. +// +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_memc_flow_vcontrol # + ( + parameter TCQ = 100, + parameter nCK_PER_CLK = 4, + parameter NUM_DQ_PINS = 32, + parameter BL_WIDTH = 6, + parameter MEM_BURST_LEN = 4, + parameter FAMILY = "SPARTAN6", + parameter MEM_TYPE = "DDR3" + + ) + ( + input clk_i, + input [9:0] rst_i, + input [3:0] data_mode_i, + input [5:0] cmds_gap_delay_value, + input mem_pattern_init_done_i, + // interface to cmd_gen, pipeline inserter + output reg cmd_rdy_o, + input cmd_valid_i, + input [2:0] cmd_i, + input [31:0] addr_i, + input [BL_WIDTH - 1:0] bl_i, + + // interface to mcb_cmd port + input mcb_cmd_full, + input mcb_wr_full_i, + output reg [2:0] cmd_o, + output [31:0] addr_o, + output reg [BL_WIDTH-1:0] bl_o, + output cmd_en_o, // interface to write data path module + // *** interface to qdr **** + output reg qdr_rd_cmd_o, + // ************************* + input mcb_wr_en_i, + input last_word_wr_i, + input wdp_rdy_i, + output reg wdp_valid_o, + output reg wdp_validB_o, + output reg wdp_validC_o, + output [31:0] wr_addr_o, + output [BL_WIDTH-1:0] wr_bl_o, + // interface to read data path module + input rdp_rdy_i, + output reg rdp_valid_o, + output [31:0] rd_addr_o, + output [BL_WIDTH-1:0] rd_bl_o + ); + + //FSM State Defination + localparam READY = 4'b0001, + READ = 4'b0010, + WRITE = 4'b0100, + CMD_WAIT = 4'b1000; + + localparam RD = 3'b001; + localparam RDP = 3'b011; + localparam WR = 3'b000; + localparam WRP = 3'b010; + localparam REFRESH = 3'b100; + localparam NOP = 3'b101; + + + reg cmd_fifo_rdy; + reg push_cmd; + reg cmd_rdy; + reg [31:0] addr_r; + reg [2:0] cmd_reg; + reg [31:0] addr_reg; + reg [BL_WIDTH-1:0] bl_reg; + reg [BL_WIDTH:0] cmd_counts; + reg rdp_valid; +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC; + reg [3:0] current_state; + reg [3:0] next_state; + reg push_cmd_r; + reg cmd_en_r1; + reg wr_in_progress; + reg wrcmd_in_progress; + reg rdcmd_in_progress; + reg [5:0] commands_delay_counters; + reg goahead; + reg cmd_en_r2; + reg cmd_wr_pending_r1; + reg [3:0] addr_INC; + reg COuta; + wire cmd_rd; + wire cmd_wr; + + always @ (posedge clk_i) begin + if (data_mode_i == 4'b1000 || FAMILY == "SPARTAN6") + addr_INC <= #TCQ 0; + else + addr_INC <= #TCQ MEM_BURST_LEN[3:0]; + end + +// mcb_command bus outputs + always @(posedge clk_i) begin + if (rst_i[0]) begin + commands_delay_counters <= 6'b00000; + goahead <= 1'b1; + end + else if (cmds_gap_delay_value == 5'd0) + goahead <= 1'b1; + else if (wr_in_progress || wrcmd_in_progress || + rdcmd_in_progress || cmd_rdy_o) begin + commands_delay_counters <= 6'b00000; + goahead <= 1'b0; + end + else if (commands_delay_counters == cmds_gap_delay_value) begin + commands_delay_counters <= commands_delay_counters; + goahead <= 1'b1; + end + else + commands_delay_counters <= commands_delay_counters + 1'b1; + end + + assign cmd_en_o = (FAMILY == "VIRTEX6") ? cmd_en_r1 : (~cmd_en_r1 & cmd_en_r2) ; + + always @ (posedge clk_i) + cmd_rdy_o <= #TCQ cmd_rdy; + + always @ (posedge clk_i) begin + if (rst_i[8]) + cmd_en_r1 <= #TCQ 1'b0; +// else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 || mcb_wr_full_i)) + else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 )) + + cmd_en_r1 <= #TCQ 1'b0; + else if ((rdcmd_in_progress || wrcmd_in_progress && MEM_TYPE != "QDR2PLUS") || + (mcb_wr_en_i && MEM_TYPE == "QDR2PLUS")) + cmd_en_r1 <= #TCQ 1'b1; + else if (!mcb_cmd_full) + cmd_en_r1 <= #TCQ 1'b0; + end + + always @ (posedge clk_i) + if (rst_i[8]) + cmd_en_r2 <= #TCQ 1'b0; + else + cmd_en_r2 <= cmd_en_r1; + +// QDR read command generation + always @ (posedge clk_i) begin + if (rst_i[8]) + qdr_rd_cmd_o <= #TCQ 1'b0; + else if (cmd_counts == 1 && !mcb_cmd_full && rdcmd_in_progress && cmd_en_r1) + qdr_rd_cmd_o <= #TCQ 1'b0; + else if (rdcmd_in_progress) + qdr_rd_cmd_o <= #TCQ 1'b1; + else if (!mcb_cmd_full) + qdr_rd_cmd_o <= #TCQ 1'b0; + end + + always @ (posedge clk_i) begin + if (rst_i[9]) + cmd_fifo_rdy <= #TCQ 1'b1; + else if (cmd_en_r1 || mcb_cmd_full) + cmd_fifo_rdy <= #TCQ 1'b0; + else if (!mcb_cmd_full) + cmd_fifo_rdy <= #TCQ 1'b1; + end + + always @ (posedge clk_i) begin + if (rst_i[9]) begin + cmd_o <= #TCQ 'b0; + bl_o <= #TCQ 'b0; + end + else if (push_cmd_r && current_state == READ) begin + cmd_o <= #TCQ cmd_i; + bl_o <= #TCQ bl_i - 'b1; + end + else if (push_cmd_r && current_state == WRITE) begin + if (FAMILY == "SPARTAN6") + cmd_o <= #TCQ cmd_reg; + else + cmd_o <= #TCQ {2'b00,cmd_reg[0]}; + bl_o <= #TCQ bl_reg; + end + end + + always @ (posedge clk_i) + if ((push_cmd && mem_pattern_init_done_i) | rst_i) + addr_reg <= #TCQ addr_i; + else if (push_cmd && !mem_pattern_init_done_i) + addr_reg <= #TCQ addr_r; + + always @ (posedge clk_i) begin + if (push_cmd && cmd_rd || rst_i[0]) + addr_r <= #TCQ addr_i; + else if (push_cmd_r && current_state != READ) + addr_r <= #TCQ addr_reg; + else if ((wrcmd_in_progress || rdcmd_in_progress) && + cmd_en_r1 && ~mcb_cmd_full) begin + if (MEM_TYPE == "QDR2PLUS") + {COuta,addr_r[31:0]} <= addr_o + 1; + else + {COuta,addr_r[31:0]} <= addr_o + addr_INC; + + end + end + + assign addr_o = addr_r; + assign wr_addr_o = addr_i; + assign rd_addr_o = addr_i; + assign rd_bl_o = bl_i; + assign wr_bl_o = bl_i; + + always @ (posedge clk_i) begin + wdp_valid_o <= wdp_valid; + wdp_validB_o <= wdp_validB; + wdp_validC_o <= wdp_validC; + end + + always @ (posedge clk_i) + rdp_valid_o <= rdp_valid; + + always @(posedge clk_i) + push_cmd_r <= #TCQ push_cmd; + + always @(posedge clk_i) + if (push_cmd) begin + cmd_reg <= #TCQ cmd_i; + bl_reg <= #TCQ bl_i - 1'b1; + end + + always @ (posedge clk_i) + begin + if (rst_i[8]) + cmd_counts <= #TCQ 'b0; + else if (push_cmd_r) begin + if (bl_i == 0) begin + if (MEM_BURST_LEN == 8) begin + if (nCK_PER_CLK == 4) + cmd_counts <= #TCQ {2'b01, {BL_WIDTH-1{1'b0}}}; + else + cmd_counts <= #TCQ {3'b001, {BL_WIDTH-2{1'b0}}}; + end + else + cmd_counts <= {1'b0,{BL_WIDTH{1'b1}}} ;//- 2;//63; + end + else begin + if (MEM_BURST_LEN == 8) begin + if (nCK_PER_CLK == 4) + cmd_counts <= {1'b0,bl_i}; + else + cmd_counts <= {3'b000,bl_i[BL_WIDTH-2:1]}; + end + else + cmd_counts <= {1'b0,bl_i};//- 1 ;// {1'b0,bl_i[5:1]} -2; + end + end + else if ((wrcmd_in_progress || rdcmd_in_progress) && cmd_en_r1 && ~mcb_cmd_full) begin + if (cmd_counts > 0) begin + if (FAMILY == "VIRTEX6") + cmd_counts <= cmd_counts - 1'b1; + else if (wrcmd_in_progress) + cmd_counts <= cmd_counts - 1'b1; + else + cmd_counts <= 0; + end + end + end + + //--Command Decodes-- + assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i) ? 1'b1 : 1'b0; + assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0; + + always @ (posedge clk_i) begin + if (rst_i[0]) + cmd_wr_pending_r1 <= #TCQ 1'b0; + else if (last_word_wr_i) + cmd_wr_pending_r1 <= #TCQ 1'b1; + else if (push_cmd & cmd_wr) + cmd_wr_pending_r1 <= #TCQ 1'b0; + end + + always @ (posedge clk_i) begin + if (rst_i[0]) + wr_in_progress <= #TCQ 1'b0; + else if (last_word_wr_i) + wr_in_progress <= #TCQ 1'b0; + else if (push_cmd && cmd_wr) + wr_in_progress <= #TCQ 1'b1; + end + + always @ (posedge clk_i) begin + if (rst_i[0]) + wrcmd_in_progress <= #TCQ 1'b0; + else if (cmd_wr && push_cmd_r) + wrcmd_in_progress <= #TCQ 1'b1; + else if (cmd_counts == 0 || (cmd_counts == 1 && ~mcb_cmd_full)) + wrcmd_in_progress <= #TCQ 1'b0; + end + + always @ (posedge clk_i) begin + if (rst_i[0]) + rdcmd_in_progress <= #TCQ 1'b0; + else if (cmd_rd && push_cmd_r) + rdcmd_in_progress <= #TCQ 1'b1; + else if (cmd_counts <= 1) + rdcmd_in_progress <= #TCQ 1'b0; + end + +// mcb_flow_control statemachine + always @ (posedge clk_i) + if (rst_i[0]) + current_state <= #TCQ 5'b00001; + else + current_state <= #TCQ next_state; + + always @ (*) begin + push_cmd = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + rdp_valid = 1'b0; + cmd_rdy = 1'b0; + next_state = current_state; + + case(current_state) // next state logic + + READY: begin // 5'h01 + + if (rdp_rdy_i && cmd_rd && ~mcb_cmd_full) begin + next_state = READ; + push_cmd = 1'b1; + rdp_valid = 1'b1; + cmd_rdy = 1'b1; + end + else if (wdp_rdy_i && cmd_wr && ~mcb_cmd_full) begin + next_state = WRITE; + push_cmd = 1'b1; + wdp_valid = 1'b1; + wdp_validB = 1'b1; + wdp_validC = 1'b1; + cmd_rdy = 1'b1; + end + else begin + next_state = READY; + push_cmd = 1'b0; + cmd_rdy = 1'b0; + end + end // READY + + READ: begin // 5'h02 + + if (rdcmd_in_progress) begin + next_state = READ; + push_cmd = 1'b0; + rdp_valid = 1'b0; + wdp_valid = 1'b0; + end + else if (!rdp_rdy_i) begin + next_state = READ; + push_cmd = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + rdp_valid = 1'b0; + end + else if (~cmd_fifo_rdy && ~rdcmd_in_progress && goahead) begin + next_state = CMD_WAIT; + end + else if (goahead && ~push_cmd_r) begin + next_state = READY; + cmd_rdy = 1'b0; + end + else + next_state = READ; + end // READ + + WRITE: begin // 5'h04 + + if (wr_in_progress || wrcmd_in_progress || push_cmd_r) begin + next_state = WRITE; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + push_cmd = 1'b0; + end + else if (!cmd_fifo_rdy && last_word_wr_i && goahead) begin + next_state = CMD_WAIT; + push_cmd = 1'b0; + end + else if (goahead) begin + next_state = READY; + end + else + next_state = WRITE; + + cmd_rdy = 1'b0; + + end // WRITE + + CMD_WAIT: begin // 5'h08 + + if (!cmd_fifo_rdy || wr_in_progress) begin + next_state = CMD_WAIT; + cmd_rdy = 1'b0; + end + else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd) begin + next_state = READY; + push_cmd = 1'b0; + cmd_rdy = 1'b0; + rdp_valid = 1'b0; + end + else if (cmd_fifo_rdy && cmd_wr && goahead && + cmd_wr_pending_r1) begin + next_state = READY; + push_cmd = 1'b0; + cmd_rdy = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + end + else begin + next_state = CMD_WAIT; + cmd_rdy = 1'b0; + end + end // CMD_WAIT + + default: begin + push_cmd = 1'b0; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + next_state = READY; + end + + endcase + end + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_traffic_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_traffic_gen.v new file mode 100644 index 0000000..5d06399 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_memc_traffic_gen.v @@ -0,0 +1,909 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MEMC +// / / Filename: memc_traffic_gen.v +// /___/ /\ Date Last Modified: $Date: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6/Virtex6 +//Design Name: memc_traffic_gen +//Purpose: This is top level module of memory traffic generator which can +// generate different CMD_PATTERN and DATA_PATTERN to Spartan 6 +// hard memory controller core. +//Reference: +//Revision History: 1.1 Brought out internal signals cmp_data and cmp_error as outputs. +// 1.2 7/1/2009 Added EYE_TEST parameter for signal SI probing. +// 1.3 10/1/2009 Added dq_error_bytelane_cmp,cumlative_dq_lane_error signals for V6. +// Any comparison error on user read data bus are mapped back to +// dq bus. The cumulative_dq_lane_error accumulate any errors on +// DQ bus. And the dq_error_bytelane_cmp shows error during current +// command cycle. The error can be cleared by input signal "manual_clear_error". +// 1.4 7/29/10 Support virtex Back-to-back commands over user interface. +// +// 1/4/2012 Added vio_percent_write (instr_mode == 4) to +// let user specify percentage of write commands out of mix +// write/read commands. + +//***************************************************************************** +`timescale 1ps/1ps + +module mig_7series_v4_2_memc_traffic_gen # + ( + parameter TCQ = 100, // SIMULATION tCQ delay. + parameter FAMILY = "SPARTAN6", // "VIRTEX6", "SPARTAN6" + parameter MEM_TYPE = "DDR3", + parameter SIMULATION = "FALSE", + parameter tCK = 2500, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + + parameter BL_WIDTH = 6, + parameter MEM_BURST_LEN = 8, // For VIRTEX6 Only in this traffic gen. + // This traffic gen doesn't support DDR3 OTF Burst mode. + + parameter PORT_MODE = "BI_MODE", // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE" + // VIRTEX6: "BI_MODE" + parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL", + + parameter ADDR_WIDTH = 30, // Spartan 6 Addr width is 30 + + parameter BANK_WIDTH = 3, + + parameter CMP_DATA_PIPE_STAGES = 0, // parameter for MPMC, it should always set to 0 + + // memory type specific + parameter MEM_COL_WIDTH = 10, // memory column width + parameter NUM_DQ_PINS = 16, // Spartan 6 Options: 4,8,16; + // Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144 + + parameter SEL_VICTIM_LINE = 3, // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern + // SEL_VICTIM_LINE is only for V6. + // Virtex 6 option: 8,9,16,17,32,36,64,72 + parameter DWIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, //NUM_DQ_PINS*4, // Spartan 6 Options: 32,64,128; + // Virtex 6 Always: 4* NUM_DQ_PINS + + + // the following parameter is to limit the range of generated PRBS Address + // + // e.g PRBS_SADDR_MASK_POS = 32'h0000_7000 the bit 14:12 of PRBS_SADDR will be ORed with + // PRBS_SADDR = 32'h0000_5000 the LFSR[14:12] to add the starting address offset. + + // PRBS_EADDR = 32'h0000_7fff + // PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to + // zero out the LFSR[31:15] + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + parameter PRBS_EADDR = 32'h00002000, + parameter PRBS_SADDR = 32'h00005000, + parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals. + // Traffic Generator will only write to one single location and no + // read transactions will be generated. + + + ) + + ( + + input clk_i, + input rst_i, + input run_traffic_i, + input single_operation, + input manual_clear_error, + input [5:0] cmds_gap_delay_value, // control delay gap between each sucessive + input [3:0] vio_instr_mode_value, + input [3:0] vio_percent_write, + // burst commands. + + // *** runtime parameter *** + input mem_pattern_init_done_i, + input [31:0] start_addr_i, // define the start of address + input [31:0] end_addr_i, // define upper limit addressboundary + input [31:0] cmd_seed_i, // seed for cmd PRBS generators + input [31:0] data_seed_i, // data seed will be added to generated address + // for PRBS data generation + // seed for cmd PRBS generators + input load_seed_i, // when asserted the cmd_seed and data_seed inputs will be registered. + + // upper layer inputs to determine the command bus and data pattern + // internal traffic generator initialize the memory with + input [2:0] addr_mode_i, // "00" = bram; takes the address from bram interface + // "01" = fixed address from the fixed_addr input + // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR + // "11" = sequential + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + input [3:0] instr_mode_i, // "0000" = BRAM + // "0001" = Fixed; takes instruction from bram output + // "0010" = R/W + // "0011" = RP/WP + // "0100" = R/RP/W/WP + // "0101" = R/RP/W/WP/REF + // "0110" = PRBS + // "1111" = Read Only from Address 0 . Expecting phy calibration data pattern. + + + input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output + // "01" = fixed , takes the burst length from the fixed_bl input + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + input [3:0] data_mode_i, // "000" = address as data + // "001" = hammer + // "010" = neighbour + // "011" = prbs + // "100" = walking 0's + // "101" = walking 1's + // "110" = + // "111" = + + input wr_data_mask_gen_i, // "1": turn on wr_data_mask generation + // random follow by walking 1's + input mode_load_i, + + // fixed pattern inputs interface + input [BL_WIDTH - 1:0] fixed_bl_i, // range from 1 to 64 + input [2:0] fixed_instr_i, //RD 3'b001 + //RDP 3'b011 + //WR 3'b000 + //WRP 3'b010 + //REFRESH 3'b100 + + + input [31:0] fixed_addr_i, // only upper 30 bits will be used + input [31:0] fixed_data_i, // + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + + // BRAM interface. + // bram bus formats: + // Only SP6 has been tested. + input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}} + input bram_valid_i, + output bram_rdy_o, // + + ///////////////////////////////////////////////////////////////////////////// + // MCB INTERFACE + // interface to mcb command port + output memc_cmd_en_o, + output [2:0] memc_cmd_instr_o, + output [31:0] memc_cmd_addr_o, + output [5:0] memc_cmd_bl_o, // this output is for Spartan 6 + + input memc_cmd_full_i, + // interface to qdr interface + output qdr_wr_cmd_o, + output qdr_rd_cmd_o, + + // interface to mcb wr data port + output memc_wr_en_o, + output [DWIDTH-1:0] memc_wr_data_o, + output memc_wr_data_end_o, + output [(DWIDTH/8) - 1:0] memc_wr_mask_o, + + input memc_wr_full_i, + + // interface to mcb rd data port + output memc_rd_en_o, + input [DWIDTH-1:0] memc_rd_data_i, + input memc_rd_empty_i, + ///////////////////////////////////////////////////////////////////////////// + // status feedback + input counts_rst, + output reg [47:0] wr_data_counts, + output reg [47:0] rd_data_counts, + output cmp_error, + output cmp_data_valid, + output error, // asserted whenever the read back data is not correct. + output [64 + (2*DWIDTH - 1):0] error_status ,// TBD how signals mapped + output [DWIDTH-1:0] cmp_data, + output [DWIDTH-1:0] mem_rd_data, + + + // **** V6 Signals + output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane + output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error, // V6: latched error byte lane that occure on + // first error + + //************************************************ + // DQ bit error debug signals. + + output [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error , + output [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error , + output [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error , + output [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error , + + output [NUM_DQ_PINS-1:0] dq_r0_bit_error_r, + output [NUM_DQ_PINS-1:0] dq_f0_bit_error_r, + output [NUM_DQ_PINS-1:0] dq_r1_bit_error_r, + output [NUM_DQ_PINS-1:0] dq_f1_bit_error_r, + + + + // + output [NUM_DQ_PINS - 1:0] dq_r0_read_bit, // rising 0 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_f0_read_bit, // falling 0 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_r1_read_bit, // rising 1 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_f1_read_bit, // falling 1 read bits from mc + output [NUM_DQ_PINS - 1:0] dq_r0_expect_bit, // rising 0 read bits from internal expect data generator + output [NUM_DQ_PINS - 1:0] dq_f0_expect_bit, // falling 0 read bits from internal expect data generator + output [NUM_DQ_PINS - 1:0] dq_r1_expect_bit, // rising 1 read bits from internal expect data generator + output [NUM_DQ_PINS - 1:0] dq_f1_expect_bit, // falling 1 read bits from internal expect data generator + output [31:0] error_addr // the command address of the returned data. + // Can use dq_rx_bit_error as write enable to latch the address. + + + + ); + + + wire [DWIDTH-1:0] rdpath_rd_data_i; + wire rdpath_data_valid_i; + wire memc_wr_en; + wire cmd2flow_valid; + wire [2:0] cmd2flow_cmd; + wire [31:0] cmd2flow_addr; + wire [BL_WIDTH-1:0] cmd2flow_bl; + wire last_word_wr; + wire flow2cmd_rdy; + wire [31:0] wr_addr; + wire [31:0] rd_addr; + wire [BL_WIDTH-1:0] wr_bl; + wire [BL_WIDTH-1:0] rd_bl; + reg run_traffic_reg; +wire wr_validB, wr_valid,wr_validC; +wire [31:0] bram_addr_i; +wire [2:0] bram_instr_i; +wire [5:0] bram_bl_i; +reg AC2_G_E2,AC1_G_E1,AC3_G_E3; +reg upper_end_matched; +reg [7:0] end_boundary_addr; +reg lower_end_matched; +wire [31:0] addr_o; +wire [31:0] m_addr; +wire dcount_rst; +wire [31:0] rd_addr_error; +wire rd_rdy; +//wire cmp_error; +wire cmd_full; +wire rd_mdata_fifo_rd_en; +wire rd_mdata_fifo_afull; +reg memc_wr_en_r; +wire memc_wr_data_end; +reg [DWIDTH-1:0] memc_rd_data_r; + +wire [DWIDTH-1:0] memc_wr_data; +reg [DWIDTH-1:0] memc_wr_data_r; + + +wire wr_path_data_rdy_i; +// +wire [31:0] cmp_addr; +wire [5:0] cmp_bl; + + +reg [9:0] rst_ra,rst_rb /* synthesis syn_maxfan = 10 */; +wire mem_init_done; +reg [3:0] data_mode_r_a; +reg [3:0] data_mode_r_b; +reg [3:0] data_mode_r_c; +reg error_access_range = 1'b0; + +wire [BL_WIDTH-1:0] memc_bl_o; + +// generic parameters and need to be tested in both MCB mode and V7 Virtext Mode. + + + initial begin + if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8) && (MEM_BURST_LEN !== 2)) + begin: NO_OTF_Warning_Error + $display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!"); + $stop; + end + else + begin: Dummy1 + + end + end + +always @ (memc_cmd_en_o,memc_cmd_addr_o,memc_cmd_bl_o,start_addr_i,end_addr_i) +if (memc_cmd_en_o && + ((FAMILY == "SPARTAN6" && memc_cmd_addr_o + 20) > end_addr_i[ADDR_WIDTH-1:0]) || + ((FAMILY == "VIRTEX6" && memc_cmd_addr_o ) > end_addr_i[ADDR_WIDTH-1:0]) + ) + begin + $display("Error ! Command access beyond address range"); + $display("Assigned Address Space: Start_Address = 0x%h ; End_Addr = 0x%h",start_addr_i,end_addr_i); + $display("Attempted area = 0x%h",memc_cmd_addr_o + (memc_cmd_bl_o - 1) * (DWIDTH/8)); + + $stop; + end +else +begin: No_Error_Display + +end + +assign memc_cmd_bl_o = memc_bl_o[5:0]; + + + + + +always @ (posedge clk_i) +begin + data_mode_r_a <= #TCQ data_mode_i; + data_mode_r_b <= #TCQ data_mode_i; + data_mode_r_c <= #TCQ data_mode_i; +end + + + + +//reg GSR = 1'b0; + always @(rst_i) + begin + rst_ra = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i}; + rst_rb = {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i}; + + end + // register it . Just in case the calling modules didn't syn with clk_i + always @(posedge clk_i) + begin + run_traffic_reg <= #TCQ run_traffic_i; + end + + assign bram_addr_i = {bram_cmd_i[29:0],2'b00}; + assign bram_instr_i = bram_cmd_i[32:30]; + assign bram_bl_i[5:0] = bram_cmd_i[38:33]; //41 + +// +// +reg COutc,COutd; + +assign dcount_rst = counts_rst | rst_ra[0]; +always @ (posedge clk_i) +begin + if (dcount_rst) + wr_data_counts <= #TCQ 'b0; + else if (memc_wr_en) + {COutc,wr_data_counts} <= #TCQ wr_data_counts + DWIDTH/8; + +end + +always @ (posedge clk_i) +begin + if (dcount_rst) + rd_data_counts <= #TCQ 'b0; + else if (memc_rd_en_o) + {COutd,rd_data_counts} <= #TCQ rd_data_counts + DWIDTH/8; + +end + + + +// **** for debug +// this part of logic is to check there are no commands been duplicated or dropped +// in the cmd_flow_control logic +generate +if (SIMULATION == "TRUE") +begin: cmd_check +wire fifo_error; +wire [31:0] xfer_addr; +wire [BL_WIDTH-1:0] xfer_cmd_bl; +wire cmd_fifo_rd; + +assign cmd_fifo_wr = flow2cmd_rdy & cmd2flow_valid; + +assign fifo_error = ( xfer_addr != memc_cmd_addr_o) ? 1'b1: 1'b0; + + +wire cmd_fifo_empty; +//assign cmd_fifo_rd = memc_cmd_en_o & ~memc_cmd_full_i & ~cmd_fifo_empty; +assign cmd_fifo_rd = memc_cmd_en_o & ~cmd_fifo_empty; + + + mig_7series_v4_2_afifo # + (.TCQ (TCQ), + .DSIZE (32+BL_WIDTH), + .FIFO_DEPTH (16), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + cmd_fifo + ( + .wr_clk (clk_i), + .rst (rst_ra[0]), + .wr_en (cmd_fifo_wr), + .wr_data ({cmd2flow_bl,cmd2flow_addr}), + .rd_en (cmd_fifo_rd), + .rd_clk (clk_i), + .rd_data ({xfer_cmd_bl,xfer_addr}), + .full (cmd_fifo_full), + .almost_full (), + .empty (cmd_fifo_empty) + + ); + + +end +else +begin + assign fifo_error = 1'b0; +end + +endgenerate + +reg [31:0] end_addr_r; + always @ (posedge clk_i) + end_addr_r <= end_addr_i; + + + mig_7series_v4_2_cmd_gen + #( + .TCQ (TCQ), + .FAMILY (FAMILY) , + .MEM_TYPE (MEM_TYPE), + + .BL_WIDTH (BL_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + + .MEM_BURST_LEN (MEM_BURST_LEN), + .PORT_MODE (PORT_MODE), + .BANK_WIDTH (BANK_WIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .DATA_PATTERN (DATA_PATTERN), + .CMD_PATTERN (CMD_PATTERN), + .ADDR_WIDTH (ADDR_WIDTH), + .DWIDTH (DWIDTH), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ), + .PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ), + .PRBS_EADDR (PRBS_EADDR), + .PRBS_SADDR (PRBS_SADDR ) + + ) + u_c_gen + ( + .clk_i (clk_i), + .rst_i (rst_ra), + .reading_rd_data_i (memc_rd_en_o), + .vio_instr_mode_value (vio_instr_mode_value), + .vio_percent_write (vio_percent_write), + .single_operation (single_operation), + .run_traffic_i (run_traffic_reg), + .mem_pattern_init_done_i (mem_pattern_init_done_i), + .start_addr_i (start_addr_i), + .end_addr_i (end_addr_r), + .cmd_seed_i (cmd_seed_i), + .load_seed_i (load_seed_i), + .addr_mode_i (addr_mode_i), + .data_mode_i (data_mode_r_a), + + .instr_mode_i (instr_mode_i), + .bl_mode_i (bl_mode_i), + .mode_load_i (mode_load_i), + // fixed pattern inputs interface + .fixed_bl_i (fixed_bl_i), + .fixed_addr_i (fixed_addr_i), + .fixed_instr_i (fixed_instr_i), + // BRAM FIFO input : Holist vector inputs + + .bram_addr_i (bram_addr_i), + .bram_instr_i (bram_instr_i ), + .bram_bl_i (bram_bl_i ), + .bram_valid_i (bram_valid_i ), + .bram_rdy_o (bram_rdy_o ), + + .rdy_i (flow2cmd_rdy), + .instr_o (cmd2flow_cmd), + .addr_o (cmd2flow_addr), + .bl_o (cmd2flow_bl), +// .m_addr_o (m_addr), + .cmd_o_vld (cmd2flow_valid), + .mem_init_done_o (mem_init_done) + + ); + +assign memc_cmd_addr_o = addr_o; + + +assign qdr_wr_cmd_o = memc_wr_en_r; + +assign cmd_full = memc_cmd_full_i; + mig_7series_v4_2_memc_flow_vcontrol # + ( + .TCQ (TCQ), + .nCK_PER_CLK (nCK_PER_CLK), + + .BL_WIDTH (BL_WIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE) + + ) + memc_control + ( + .clk_i (clk_i), + .rst_i (rst_ra), + .data_mode_i (data_mode_r_b), + .cmds_gap_delay_value (cmds_gap_delay_value), + .mcb_wr_full_i (memc_wr_full_i), + .cmd_rdy_o (flow2cmd_rdy), + .cmd_valid_i (cmd2flow_valid), + .cmd_i (cmd2flow_cmd), + + + .mem_pattern_init_done_i (mem_pattern_init_done_i), + + .addr_i (cmd2flow_addr), + .bl_i (cmd2flow_bl), + // interface to memc_cmd port + .mcb_cmd_full (cmd_full), + .cmd_o (memc_cmd_instr_o), + .addr_o (addr_o), + .bl_o (memc_bl_o), + .cmd_en_o (memc_cmd_en_o), + .qdr_rd_cmd_o (qdr_rd_cmd_o), + // interface to write data path module + + .mcb_wr_en_i (memc_wr_en), + .last_word_wr_i (last_word_wr), + .wdp_rdy_i (wr_rdy),//(wr_rdy), + .wdp_valid_o (wr_valid), + .wdp_validB_o (wr_validB), + .wdp_validC_o (wr_validC), + + .wr_addr_o (wr_addr), + .wr_bl_o (wr_bl), + // interface to read data path module + + .rdp_rdy_i (rd_rdy),// (rd_rdy), + .rdp_valid_o (rd_valid), + .rd_addr_o (rd_addr), + .rd_bl_o (rd_bl) + + ); + + + /* afifo # + ( + + .TCQ (TCQ), + .DSIZE (DWIDTH), + .FIFO_DEPTH (32), + .ASIZE (5), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_mdata_fifo + ( + .wr_clk (clk_i), + .rst (rst_rb[0]), + .wr_en (!memc_rd_empty_i), + .wr_data (memc_rd_data_i), + .rd_en (memc_rd_en_o), + .rd_clk (clk_i), + .rd_data (rd_v6_mdata), + .full (), + .almost_full (rd_mdata_fifo_afull), + .empty (rd_mdata_fifo_empty) + + ); +*/ + +wire cmd_rd_en; + +assign cmd_rd_en = memc_cmd_en_o; + + + + +assign rdpath_data_valid_i =!memc_rd_empty_i ; +assign rdpath_rd_data_i = memc_rd_data_i ; + + +generate +if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE") +begin : RD_PATH + mig_7series_v4_2_read_data_path + #( + .TCQ (TCQ), + .FAMILY (FAMILY) , + .MEM_TYPE (MEM_TYPE), + .BL_WIDTH (BL_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + + .MEM_BURST_LEN (MEM_BURST_LEN), + .START_ADDR (PRBS_SADDR), + .CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES), + .ADDR_WIDTH (ADDR_WIDTH), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .SIMULATION (SIMULATION) + + ) + read_data_path + ( + .clk_i (clk_i), + .rst_i (rst_rb), + .manual_clear_error (manual_clear_error), + .cmd_rdy_o (rd_rdy), + .cmd_valid_i (rd_valid), + .memc_cmd_full_i (memc_cmd_full_i), + .prbs_fseed_i (data_seed_i), + .cmd_sent (memc_cmd_instr_o), + .bl_sent (memc_bl_o[5:0]), + .cmd_en_i (cmd_rd_en), + .vio_instr_mode_value (vio_instr_mode_value), + + .data_mode_i (data_mode_r_b), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + .mode_load_i (mode_load_i), + + .addr_i (rd_addr), + .bl_i (rd_bl), + .data_rdy_o (memc_rd_en_o), + + .data_valid_i (rdpath_data_valid_i), + .data_i (rdpath_rd_data_i), + + + .data_error_o (cmp_error), + .cmp_data_valid (cmp_data_valid), + .cmp_data_o (cmp_data), + .rd_mdata_o (mem_rd_data ), + .cmp_addr_o (cmp_addr), + .cmp_bl_o (cmp_bl), + .dq_error_bytelane_cmp (dq_error_bytelane_cmp), + + //**************************************************** + .cumlative_dq_lane_error_r (cumlative_dq_lane_error), + .cumlative_dq_r0_bit_error_r (cumlative_dq_r0_bit_error), + .cumlative_dq_f0_bit_error_r (cumlative_dq_f0_bit_error), + .cumlative_dq_r1_bit_error_r (cumlative_dq_r1_bit_error), + .cumlative_dq_f1_bit_error_r (cumlative_dq_f1_bit_error), + .dq_r0_bit_error_r (dq_r0_bit_error_r), + .dq_f0_bit_error_r (dq_f0_bit_error_r), + .dq_r1_bit_error_r (dq_r1_bit_error_r), + .dq_f1_bit_error_r (dq_f1_bit_error_r), + + .dq_r0_read_bit_r (dq_r0_read_bit), + .dq_f0_read_bit_r (dq_f0_read_bit), + .dq_r1_read_bit_r (dq_r1_read_bit), + .dq_f1_read_bit_r (dq_f1_read_bit), + .dq_r0_expect_bit_r (dq_r0_expect_bit), + .dq_f0_expect_bit_r (dq_f0_expect_bit ), + .dq_r1_expect_bit_r (dq_r1_expect_bit), + .dq_f1_expect_bit_r (dq_f1_expect_bit ), + .error_addr_o (error_addr) + + + + + + ); + +end +else +begin + assign cmp_error = 1'b0; + assign cmp_data_valid = 1'b0; + assign cmp_data ='b0; + +end + +endgenerate + + + +assign wr_path_data_rdy_i = !(memc_wr_full_i ) ;//& (~memc_cmd_full_i); + +generate +if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") +begin : WR_PATH + + mig_7series_v4_2_write_data_path + #( + + .TCQ (TCQ), + .FAMILY (FAMILY), + .nCK_PER_CLK (nCK_PER_CLK), + .MEM_TYPE (MEM_TYPE), + + .START_ADDR (PRBS_SADDR), + .BL_WIDTH (BL_WIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .EYE_TEST (EYE_TEST) + + ) + write_data_path + ( + .clk_i(clk_i), + .rst_i (rst_rb), + .cmd_rdy_o (wr_rdy), + .cmd_valid_i (wr_valid), + .cmd_validB_i (wr_validB), + .cmd_validC_i (wr_validC), + .prbs_fseed_i (data_seed_i), + .mode_load_i (mode_load_i), + .wr_data_mask_gen_i (wr_data_mask_gen_i), + .mem_init_done_i (mem_init_done), + + + .data_mode_i (data_mode_r_c), + .last_word_wr_o (last_word_wr), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + + .addr_i (wr_addr), + .bl_i (wr_bl), + .memc_cmd_full_i (memc_cmd_full_i), + .data_rdy_i (wr_path_data_rdy_i), + .data_valid_o (memc_wr_en), + .data_o (memc_wr_data), + .data_mask_o (memc_wr_mask_o), + .data_wr_end_o (memc_wr_data_end) + ); + +end +else +begin + assign memc_wr_en = 1'b0; + assign memc_wr_data = 'b0; + assign memc_wr_mask_o = 'b0; + +end + +endgenerate + +generate +if (MEM_TYPE != "QDR2PLUS" && (FAMILY == "VIRTEX6" || FAMILY == "SPARTAN6" )) + begin: nonQDR_WR + assign memc_wr_en_o = memc_wr_en; + assign memc_wr_data_o = memc_wr_data ; + assign memc_wr_data_end_o = (nCK_PER_CLK == 4) ? memc_wr_data_end: memc_wr_data_end; + end +// QDR +else + begin: QDR_WR + + always @ (posedge clk_i) + memc_wr_data_r <= memc_wr_data; + + assign memc_wr_en_o = memc_wr_en; + assign memc_wr_data_o = memc_wr_data_r ; + + assign memc_wr_data_end_o = memc_wr_data_end; + end +endgenerate + +//QDR +always @ (posedge clk_i) +begin + +if (memc_wr_full_i) + begin + memc_wr_en_r <= 1'b0; + end +else + begin + memc_wr_en_r <= memc_wr_en; + end + +end + + mig_7series_v4_2_tg_status + #( + + .TCQ (TCQ), + .DWIDTH (DWIDTH) + ) + tg_status + ( + .clk_i (clk_i), + .rst_i (rst_ra[2]), + .manual_clear_error (manual_clear_error), + .data_error_i (cmp_error), + .cmp_data_i (cmp_data), + .rd_data_i (mem_rd_data ), + .cmp_addr_i (cmp_addr), + .cmp_bl_i (cmp_bl), + .mcb_cmd_full_i (memc_cmd_full_i), + .mcb_wr_full_i (memc_wr_full_i), + .mcb_rd_empty_i (memc_rd_empty_i), + .error_status (error_status), + .error (error) + ); + + +endmodule // memc_traffic_gen diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_rd_data_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_rd_data_gen.v new file mode 100644 index 0000000..44a86a2 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_rd_data_gen.v @@ -0,0 +1,382 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: rd_data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module has all the timing control for generating "compare data" +// to compare the read data from memory. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_rd_data_gen # + ( + parameter TCQ = 100, + parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6" + parameter MEM_TYPE = "DDR3", + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + + parameter MEM_BURST_LEN = 8, + parameter START_ADDR = 32'h00000000, + + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter COLUMN_WIDTH = 10 + + ) + ( + input clk_i, // + input [4:0] rst_i, + input [31:0] prbs_fseed_i, + input [3:0] data_mode_i, // "00" = bram; + input mode_load_i, + input [3:0] vio_instr_mode_value, + + output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. + // And then it should reasserted when + // it is generating the last_word. + input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. + output reg cmd_start_o, +// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern. + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + + input [31:0] fixed_data_i, + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data + output user_bl_cnt_is_1_o, + input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6 + // connect from mcb_rd_empty when used as rd_data_gen in sp6 + // connect from rd_data_valid in v6 + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the + // pattern is available. +// output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1 + output [31:0] tg_st_addr_o, + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1 + +); +// + + + +wire [31:0] prbs_data; +reg cmd_start; +reg [31:0] adata; +reg [31:0] hdata; +reg [31:0] ndata; +reg [31:0] w1data; +reg [NUM_DQ_PINS*4-1:0] v6_w1data; + +reg [31:0] w0data; +reg [DWIDTH-1:0] data; +reg cmd_rdy; +reg [BL_WIDTH:0]user_burst_cnt; +reg [31:0] w3data; +reg prefetch; +assign data_port_fifo_rdy = data_rdy_i; + + + + +reg user_bl_cnt_is_1; +assign user_bl_cnt_is_1_o = user_bl_cnt_is_1; +always @ (posedge clk_i) +begin +if (data_port_fifo_rdy) + if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6") + || (user_burst_cnt == 2 && FAMILY == "VIRTEX6") + ) + + user_bl_cnt_is_1 <= #TCQ 1'b1; + else + user_bl_cnt_is_1 <= #TCQ 1'b0; +end + + +//reg cmd_start_b; +always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch) +begin + + cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ; + cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ; + +end + + + + +// counter to count user burst length +// verilint STARC-2.2.3.3 off +always @( posedge clk_i) +begin + if ( rst_i[0] ) + user_burst_cnt <= #TCQ 'd0; + else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin + + // SPATAN6 has maximum of burst length of 64. + if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000) + begin + user_burst_cnt[6:0] <= #TCQ 7'd64; + user_burst_cnt[BL_WIDTH:7] <= 'b0; + end + else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}}) + user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}}; + else + user_burst_cnt <= #TCQ {1'b0,bl_i }; + end + else if(data_port_fifo_rdy) + if (user_burst_cnt != 6'd0) + user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; + else + user_burst_cnt <= #TCQ 'd0; + +end +// verilint STARC-2.2.3.3 on + +// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i +// is assert and reassert during the last data + +//data_valid_o logic + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + prefetch <= #TCQ 1'b1; + else if (data_port_fifo_rdy || cmd_start) + prefetch <= #TCQ 1'b0; + + else if (user_burst_cnt == 0 && ~data_port_fifo_rdy) + prefetch <= #TCQ 1'b1; + +end +assign cmd_rdy_o = cmd_rdy ; + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdy <= #TCQ 1'b1; + + else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch )) + cmd_rdy <= #TCQ 1'b0; + else if ((data_port_fifo_rdy && user_burst_cnt == 2 && vio_instr_mode_value != 7 ) || + (data_port_fifo_rdy && user_burst_cnt == 1 && vio_instr_mode_value == 7 )) + + cmd_rdy <= #TCQ 1'b1; + + +end + + + + +always @ (data_port_fifo_rdy) +if (FAMILY == "SPARTAN6") + data_valid_o = data_port_fifo_rdy; +else + data_valid_o = data_port_fifo_rdy; + + +/* +generate +if (FAMILY == "SPARTAN6") +begin : SP6_DGEN +s7ven_data_gen # + +( + .TCQ (TCQ), + .DMODE ("READ"), + .nCK_PER_CLK (nCK_PER_CLK), + .FAMILY (FAMILY), + + .ADDR_WIDTH (32 ), + .BL_WIDTH (BL_WIDTH ), + .MEM_BURST_LEN (MEM_BURST_LEN), + .DWIDTH (DWIDTH ), + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .START_ADDR (START_ADDR), + + .COLUMN_WIDTH (COLUMN_WIDTH) + + ) + s7ven_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .mem_init_done_i (1'b1), + .wr_data_mask_gen_i (1'b0), + + .prbs_fseed_i (prbs_fseed_i), + .mode_load_i (mode_load_i), + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_start ), + .cmd_startC (cmd_start ), + .cmd_startD (cmd_start ), + .cmd_startE (cmd_start ), + .m_addr_i (addr_i),//(m_addr_i ), + + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (data_port_fifo_rdy ), + .data_o (data_o ), + .data_mask_o (), + + .bram_rd_valid_o () + ); + +end + +endgenerate*/ +//generate +//if (FAMILY == "VIRTEX6") +//begin : V_DGEN +mig_7series_v4_2_s7ven_data_gen # +( + .TCQ (TCQ), + .DMODE ("READ"), + .nCK_PER_CLK (nCK_PER_CLK), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + + .ADDR_WIDTH (32 ), + .BL_WIDTH (BL_WIDTH ), + .MEM_BURST_LEN (MEM_BURST_LEN), + .DWIDTH (DWIDTH ), + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .START_ADDR (START_ADDR), + + .COLUMN_WIDTH (COLUMN_WIDTH) + + ) + s7ven_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .mem_init_done_i (1'b1), + .wr_data_mask_gen_i (1'b0), + + .prbs_fseed_i (prbs_fseed_i), + .mode_load_i (mode_load_i), + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_start ), + .cmd_startC (cmd_start ), + .cmd_startD (cmd_start ), + .cmd_startE (cmd_start ), + .m_addr_i (addr_i),//(m_addr_i ), + + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (data_port_fifo_rdy ), + .data_o (data_o ), + .tg_st_addr_o (tg_st_addr_o), + .data_mask_o (), + + .bram_rd_valid_o () + ); + +//end +//endgenerate + + + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_data_path.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_data_path.v new file mode 100644 index 0000000..fff048e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_data_path.v @@ -0,0 +1,751 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: read_data_path.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This is top level of read path and also consist of comparison logic +// for read data. +//Reference: +//Revision History: 11/18 /2011 Fixed a localparam ER_WIDTH bug for QDR2+ case. +// 03/15/2012 Registered error_byte, error_bit to avoid false +// comparison when data_valid_i is deasserted. +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_read_data_path #( + parameter TCQ = 100, + parameter START_ADDR = 32'h00000000, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + + parameter MEM_TYPE = "DDR3", + parameter FAMILY = "VIRTEX6", + parameter BL_WIDTH = 6, + parameter MEM_BURST_LEN = 8, + parameter ADDR_WIDTH = 32, + parameter CMP_DATA_PIPE_STAGES = 3, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter DWIDTH = nCK_PER_CLK * 2 * NUM_DQ_PINS, + + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter MEM_COL_WIDTH = 10, + parameter SIMULATION = "FALSE" + + ) + ( + + + input clk_i, + input [9:0] rst_i, + input manual_clear_error, + output cmd_rdy_o, + input cmd_valid_i, + input memc_cmd_full_i, + input [31:0] prbs_fseed_i, + input mode_load_i, + input [3:0] vio_instr_mode_value, + + input [3:0] data_mode_i, + input [2:0] cmd_sent, + input [5:0] bl_sent , + input cmd_en_i , +// input [31:0] m_addr_i, + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [31:0] fixed_data_i, + input [31:0] addr_i, + input [BL_WIDTH-1:0] bl_i, + + + output data_rdy_o, + input data_valid_i, + input [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_i, + output data_error_o, //data_error on user data bus side + output [DWIDTH-1:0] cmp_data_o, + output [DWIDTH-1:0] rd_mdata_o , + output cmp_data_valid, + output [31:0] cmp_addr_o, + output [5 :0] cmp_bl_o, + output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane + output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error_r, // V6: latched error byte lane that occure on + // first error + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error_r , + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error_r , + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error_r , + output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error_r , + + output reg [NUM_DQ_PINS-1:0] dq_r0_bit_error_r, + output reg [NUM_DQ_PINS-1:0] dq_f0_bit_error_r, + output reg [NUM_DQ_PINS-1:0] dq_r1_bit_error_r, + output reg [NUM_DQ_PINS-1:0] dq_f1_bit_error_r, + + + output reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_r, + output reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_r, + output [31:0] error_addr_o + + + ); + + wire gen_rdy; + wire gen_valid; + wire [31:0] gen_addr; + wire [BL_WIDTH-1:0] gen_bl; + + wire cmp_rdy; + wire cmp_valid; + wire [31:0] cmp_addr; + wire [5:0] cmp_bl; + + reg data_error; + wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data; + wire [31:0] tg_st_addr_o; + reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data_r1,cmp_data_r2; + reg last_word_rd; + reg [5:0] bl_counter; + wire cmd_rdy; + wire user_bl_cnt_is_1; + wire data_rdy; + reg [DWIDTH:0] delayed_data; + wire rd_mdata_en; + reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r1; + reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r2; + reg force_wrcmd_gen; + reg wait_bl_end; + reg wait_bl_end_r1; +reg l_data_error ; +reg u_data_error; +reg v6_data_cmp_valid; +wire [DWIDTH -1 :0] rd_v6_mdata; +reg [DWIDTH -1 :0] cmpdata_r; +wire [DWIDTH -1 :0] rd_mdata; + reg cmp_data_en; + +localparam ER_WIDTH = ( MEM_TYPE == "QDR2PLUS" && nCK_PER_CLK == 2) ? (NUM_DQ_PINS*MEM_BURST_LEN)/9 : + ( MEM_TYPE != "QDR2PLUS" && nCK_PER_CLK == 2) ? NUM_DQ_PINS/2 : NUM_DQ_PINS; + +reg [ER_WIDTH - 1:0] error_byte; +reg [ER_WIDTH - 1:0] error_byte_r1; + +reg [NUM_DQ_PINS*nCK_PER_CLK*2 - 1:0] error_bit; +reg [NUM_DQ_PINS*nCK_PER_CLK*2 -1:0] error_bit_r1; + +wire [NUM_DQ_PINS-1:0] dq_bit_error; +wire [NUM_DQ_PINS-1:0] cumlative_dq_bit_error_c; + +wire [ NUM_DQ_PINS/8-1:0] dq_lane_error; +reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r1; +reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r2; +reg [NUM_DQ_PINS-1:0] dq_bit_error_r1; +wire [NUM_DQ_PINS-1:0] cumlative_dq_r0_bit_error_c; +wire [NUM_DQ_PINS-1:0] cumlative_dq_f0_bit_error_c; +wire [NUM_DQ_PINS-1:0] cumlative_dq_r1_bit_error_c; +wire [NUM_DQ_PINS-1:0] cumlative_dq_f1_bit_error_c; + + +wire [ NUM_DQ_PINS/8-1:0] cum_dq_lane_error_mask; +wire [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_c; +reg [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_reg; + + + reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_rdlay1; + reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_rdlay1; + wire [NUM_DQ_PINS-1:0] dq_r0_bit_error ; + wire [NUM_DQ_PINS-1:0] dq_f0_bit_error ; + wire [NUM_DQ_PINS-1:0] dq_r1_bit_error ; + wire [NUM_DQ_PINS-1:0] dq_f1_bit_error ; + reg [31:0] error_addr_r1; + reg [31:0] error_addr_r2; + reg [31:0] error_addr_r3; + reg data_valid_r1; + reg data_valid_r2; + wire cmd_start_i; + + + + always @ (posedge clk_i) begin + wait_bl_end_r1 <= #TCQ wait_bl_end; + rd_data_r1 <= #TCQ data_i; + rd_data_r2 <= #TCQ rd_data_r1; + end + + reg [7:0] force_wrcmd_timeout_cnts ; + + always @ (posedge clk_i) begin + if (rst_i[0]) + force_wrcmd_gen <= #TCQ 1'b0; + else if ((wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111) + force_wrcmd_gen <= #TCQ 1'b0; + + else if ((cmd_valid_i && bl_i > 16) || wait_bl_end ) + force_wrcmd_gen <= #TCQ 1'b1; + end + + + always @ (posedge clk_i) begin + if (rst_i[0]) + force_wrcmd_timeout_cnts <= #TCQ 'b0; + else if (wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) + force_wrcmd_timeout_cnts <= #TCQ 'b0; + + else if (force_wrcmd_gen) + force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1'b1; + end + + always @ (posedge clk_i) + if (rst_i[0]) + wait_bl_end <= #TCQ 1'b0; + else if (force_wrcmd_timeout_cnts == 8'b11111111) + wait_bl_end <= #TCQ 1'b0; + + else if (gen_rdy && gen_valid && gen_bl > 16) + wait_bl_end <= #TCQ 1'b1; + else if (wait_bl_end && user_bl_cnt_is_1) + wait_bl_end <= #TCQ 1'b0; + + + assign cmd_rdy_o = cmd_rdy; + mig_7series_v4_2_read_posted_fifo # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .nCK_PER_CLK (nCK_PER_CLK), + .MEM_BURST_LEN (MEM_BURST_LEN), + .ADDR_WIDTH (32), + .BL_WIDTH (BL_WIDTH) + ) + read_postedfifo( + .clk_i (clk_i), + .rst_i (rst_i[0]), + .cmd_rdy_o (cmd_rdy ), + .cmd_valid_i (cmd_valid_i ), + .data_valid_i (data_rdy ), // input to + .addr_i (addr_i ), + .bl_i (bl_i ), + .cmd_start_i (cmd_start), + .cmd_sent (cmd_sent), + .bl_sent (bl_sent ), + .cmd_en_i (cmd_en_i), + .memc_cmd_full_i (memc_cmd_full_i), + .gen_valid_o (gen_valid ), + .gen_addr_o (gen_addr ), + .gen_bl_o (gen_bl ), + .rd_mdata_en (rd_mdata_en) + ); + + + + + mig_7series_v4_2_rd_data_gen # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + + .BL_WIDTH (BL_WIDTH), + .nCK_PER_CLK (nCK_PER_CLK), + + .MEM_BURST_LEN (MEM_BURST_LEN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .START_ADDR (START_ADDR), + + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH(DWIDTH), + .COLUMN_WIDTH (MEM_COL_WIDTH) + + ) + rd_datagen( + .clk_i (clk_i ), + .rst_i (rst_i[4:0]), + .prbs_fseed_i (prbs_fseed_i), + .data_mode_i (data_mode_i ), + .vio_instr_mode_value (vio_instr_mode_value), + + .cmd_rdy_o (gen_rdy ), + .cmd_valid_i (gen_valid ), + .mode_load_i (mode_load_i), + .cmd_start_o (cmd_start), + // .m_addr_i (m_addr_i ), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + + .fixed_data_i (fixed_data_i), + + .addr_i (gen_addr ), + .bl_i (gen_bl ), + .user_bl_cnt_is_1_o (user_bl_cnt_is_1), + .data_rdy_i (data_valid_i ), // input to + .data_valid_o (cmp_valid ), + .tg_st_addr_o (tg_st_addr_o), + .data_o (cmp_data ) + ); + + mig_7series_v4_2_afifo # + ( + .TCQ (TCQ), + .DSIZE (DWIDTH), + .FIFO_DEPTH (32), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_mdata_fifo + ( + .wr_clk (clk_i), + .rst (rst_i[0]), + .wr_en (data_valid_i), + .wr_data (data_i), + .rd_en (rd_mdata_en), + .rd_clk (clk_i), + .rd_data (rd_v6_mdata), + .full (), + .empty (), + .almost_full () + ); + +always @ (posedge clk_i) +begin +// delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data}; + cmp_data_r1 <= #TCQ cmp_data; + cmp_data_r2 <= #TCQ cmp_data_r1; +end +assign rd_mdata_o = rd_mdata; + +assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r1: + (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata: + rd_data_r2; + +assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en : + (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i; + + + + +assign cmp_data_o = cmp_data_r2; +assign cmp_addr_o = tg_st_addr_o;//gen_addr; +assign cmp_bl_o = gen_bl[5:0]; + + + +assign data_rdy_o = data_rdy; +assign data_rdy = cmp_valid & data_valid_i; + + always @ (posedge clk_i) + v6_data_cmp_valid <= #TCQ rd_mdata_en; + + + always @ (posedge clk_i) + cmp_data_en <= #TCQ data_rdy; + + +genvar i; + + generate + if (FAMILY == "SPARTAN6") + begin: gen_error_sp6 + always @ (posedge clk_i) + begin + if (cmp_data_en) + l_data_error <= #TCQ (rd_data_r1[DWIDTH/2-1:0] != cmp_data_r1[DWIDTH/2-1:0]); + else + l_data_error <= #TCQ 1'b0; + + if (cmp_data_en) + u_data_error <= #TCQ (rd_data_r1[DWIDTH-1:DWIDTH/2] != cmp_data_r1[DWIDTH-1:DWIDTH/2]); + else + u_data_error <= #TCQ 1'b0; + + data_error <= #TCQ l_data_error | u_data_error; + //synthesis translate_off + if (data_error) + $display ("ERROR at time %t" , $time); + //synthesis translate_on + + end + +end +else +// if (FAMILY == "VIRTEX6" ) + begin: gen_error_v7 + if (nCK_PER_CLK == 2) + begin + if (MEM_TYPE == "QDR2PLUS") + begin: qdr_design + for (i = 0; i < (NUM_DQ_PINS*MEM_BURST_LEN)/9; i = i + 1) + begin: gen_cmp_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_byte[i] <= (data_i[9*(i+1)-1:9*i] !== cmp_data[9*(i+1)-1:9*i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_byte[i] <= (data_i[9*(i+1)-1:9*i] != cmp_data[9*(i+1)-1:9*i]) ; + else + error_byte[i] <= 1'b0; + end + for (i = 0; i < NUM_DQ_PINS*MEM_BURST_LEN; i = i + 1) + begin: gen_cmp_bit_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_bit[i] <= (data_i[i] !== cmp_data[i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_bit[i] <= (data_i[i] != cmp_data[i]) ; + else + error_bit[i] <= 1'b0; + end + end + else + begin: ddr_design + for (i = 0; i < NUM_DQ_PINS/2; i = i + 1) + begin: gen_cmp_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ; + else + error_byte[i] <= 1'b0; + end + for (i = 0; i < NUM_DQ_PINS*4; i = i + 1) + begin: gen_cmp_bit_2 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_bit[i] <= ( (data_i[i] !== cmp_data[i]) ) ; + else + //synthesis translate_on + if (data_valid_i) + error_bit[i] <= ( (data_i[i] != cmp_data[i]) ) ; + else + error_bit[i] <= 1'b0; + end + end + end + else //nCK_PER_CLK == 4 + begin + for (i = 0; i < NUM_DQ_PINS; i = i + 1) + begin: gen_cmp_4 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ; + else + error_byte[i] <= 1'b0; + end + + for (i = 0; i < NUM_DQ_PINS*8; i = i + 1) + begin: gen_cmp_bit_4 + always @ (posedge clk_i) + //synthesis translate_off + if (data_valid_i & (SIMULATION=="TRUE")) + error_bit[i] <= (data_i[i] !== cmp_data[i]) ; + else + //synthesis translate_on + if (data_valid_i) + error_bit[i] <= (data_i[i] != cmp_data[i]) ; + else + error_bit[i] <= 1'b0; + end + end + +always @ (posedge clk_i) +begin + dq_r0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*1 - 1:0]; + dq_f0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1]; + dq_r1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2]; + dq_f1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3]; + + dq_r0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*1 - 1:0]; + dq_f0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1]; + dq_r1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2]; + dq_f1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3]; + + dq_r0_read_bit_r <= #TCQ dq_r0_read_bit_rdlay1 ; + dq_f0_read_bit_r <= #TCQ dq_f0_read_bit_rdlay1 ; + dq_r1_read_bit_r <= #TCQ dq_r1_read_bit_rdlay1 ; + dq_f1_read_bit_r <= #TCQ dq_f1_read_bit_rdlay1 ; + + dq_r0_expect_bit_r <= #TCQ dq_r0_expect_bit_rdlay1; + dq_f0_expect_bit_r <= #TCQ dq_f0_expect_bit_rdlay1; + dq_r1_expect_bit_r <= #TCQ dq_r1_expect_bit_rdlay1; + dq_f1_expect_bit_r <= #TCQ dq_f1_expect_bit_rdlay1; + + + + + +end +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + + error_byte_r1 <= #TCQ 'b0; + error_bit_r1 <= #TCQ 'b0; + + end + else if (data_valid_r1) begin + + error_byte_r1 <= #TCQ error_byte; + error_bit_r1 <= #TCQ error_bit; + end + else + begin + error_byte_r1 <= #TCQ 'b0; + error_bit_r1 <= #TCQ 'b0; + end +end +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) + data_error <= #TCQ 1'b0; + else if (data_valid_r2) + data_error <= #TCQ | error_byte_r1; + else + data_error <= #TCQ 1'b0; + + //synthesis translate_off + if (data_error) + $display ("ERROR: Expected data=%h, Received data=%h @ %t" ,cmp_data_r2, rd_data_r2, $time); + //synthesis translate_on + + end + +localparam NUM_OF_DQS = (MEM_TYPE == "QDR2PLUS") ? 9 : 8 ; + + if (MEM_TYPE == "QDR2PLUS") begin: qdr_design_error_calc + + if (MEM_BURST_LEN == 4) begin: bl4_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end else begin: bl2_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end + + end else begin: ddr_design_error_calc + + if (nCK_PER_CLK == 4) begin: ck_4to1_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*4/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*5/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*6/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*7/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end else if (nCK_PER_CLK == 2) begin: ck_2to1_design + for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | + error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] | + error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ; + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + end + end + + // mapped the user bits error to dq bits error + + // mapper the error to rising 0 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_r0_error_mapbit + assign dq_r0_bit_error[i] = (error_bit_r1[i]); + assign cumlative_dq_r0_bit_error_c[i] = cumlative_dq_r0_bit_error_r[i] | dq_r0_bit_error[i]; + + end + // mapper the error to falling 0 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_f0_error_mapbit + assign dq_f0_bit_error[i] = (error_bit_r1[i+NUM_DQ_PINS*1] ); + assign cumlative_dq_f0_bit_error_c[i] = cumlative_dq_f0_bit_error_r[i] | dq_f0_bit_error[i]; + + end + + // mapper the error to rising 1 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_r1_error_mapbit + assign dq_r1_bit_error[i] = (error_bit_r1[i+ (NUM_DQ_PINS*2)]); + assign cumlative_dq_r1_bit_error_c[i] = cumlative_dq_r1_bit_error_r[i] | dq_r1_bit_error[i]; + + end + + // mapper the error to falling 1 + for ( i = 0; i < NUM_DQ_PINS; i = i+1) + begin: gen_dq_f1_error_mapbit + assign dq_f1_bit_error[i] = ( error_bit_r1[i+ (NUM_DQ_PINS*3)]); + assign cumlative_dq_f1_bit_error_c[i] = cumlative_dq_f1_bit_error_r[i] | dq_f1_bit_error[i]; + end +reg COuta; +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + dq_bit_error_r1 <= #TCQ 'b0; + dq_lane_error_r1 <= #TCQ 'b0; + dq_lane_error_r2 <= #TCQ 'b0; + data_valid_r1 <= #TCQ 1'b0; + data_valid_r2 <= #TCQ 1'b0; + dq_r0_bit_error_r <= #TCQ 'b0; + dq_f0_bit_error_r <= #TCQ 'b0; + dq_r1_bit_error_r <= #TCQ 'b0; + dq_f1_bit_error_r <= #TCQ 'b0; + + cumlative_dq_lane_error_reg <= #TCQ 'b0; + cumlative_dq_r0_bit_error_r <= #TCQ 'b0; + cumlative_dq_f0_bit_error_r <= #TCQ 'b0; + cumlative_dq_r1_bit_error_r <= #TCQ 'b0; + cumlative_dq_f1_bit_error_r <= #TCQ 'b0; + error_addr_r1 <= #TCQ 'b0; + error_addr_r2 <= #TCQ 'b0; + error_addr_r3 <= #TCQ 'b0; + + end + else begin + data_valid_r1 <= #TCQ data_valid_i; + data_valid_r2 <= #TCQ data_valid_r1; + dq_lane_error_r1 <= #TCQ dq_lane_error; + dq_bit_error_r1 <= #TCQ dq_bit_error; + + cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c; + cumlative_dq_r0_bit_error_r <= #TCQ cumlative_dq_r0_bit_error_c; + + cumlative_dq_f0_bit_error_r <= #TCQ cumlative_dq_f0_bit_error_c; + cumlative_dq_r1_bit_error_r <= #TCQ cumlative_dq_r1_bit_error_c; + cumlative_dq_f1_bit_error_r <= #TCQ cumlative_dq_f1_bit_error_c; + dq_r0_bit_error_r <= #TCQ dq_r0_bit_error; + dq_f0_bit_error_r <= #TCQ dq_f0_bit_error; + dq_r1_bit_error_r <= #TCQ dq_r1_bit_error; + dq_f1_bit_error_r <= #TCQ dq_f1_bit_error; + error_addr_r2 <= #TCQ error_addr_r1; + error_addr_r3 <= #TCQ error_addr_r2; + + if (rd_mdata_en) + error_addr_r1 <= #TCQ gen_addr; + else if (data_valid_i) + {COuta,error_addr_r1} <= #TCQ error_addr_r1 + 4; + + end +end + +end +endgenerate + +assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg; +assign dq_error_bytelane_cmp = dq_lane_error_r1; +assign data_error_o = data_error; +assign error_addr_o = error_addr_r3; + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v new file mode 100644 index 0000000..5c5aec5 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_read_posted_fifo.v @@ -0,0 +1,251 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: read_posted_fifo.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module instantiated by read_data_path module and sits between +// mcb_flow_control module and read_data_gen module to buffer up the +// commands that has sent to memory controller. +//Reference: +//Revision History: 3/14/2012 Adding support for "nCK_PER_CLK == 2" abd MEM_BURST_LEN == 2 " +//***************************************************************************** +`timescale 1ps/1ps + + module mig_7series_v4_2_read_posted_fifo # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter nCK_PER_CLK = 4, + parameter MEM_BURST_LEN = 4, + + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6 + ) + ( + input clk_i, + input rst_i, + output reg cmd_rdy_o, + input memc_cmd_full_i, + input cmd_valid_i, + input data_valid_i, + input cmd_start_i, + input [ADDR_WIDTH-1:0] addr_i, + input [BL_WIDTH-1:0] bl_i, + input [2:0] cmd_sent, + input [5:0] bl_sent , + input cmd_en_i , + + + output gen_valid_o, + output [ADDR_WIDTH-1:0] gen_addr_o, + output [BL_WIDTH-1:0] gen_bl_o, + output rd_mdata_en + + ); + +//reg empty_r; + reg rd_en_r; + wire full; + wire empty; + wire wr_en; + reg mcb_rd_fifo_port_almost_full; + reg [6:0] buf_avail_r; + reg [6:0] rd_data_received_counts; + reg [6:0] rd_data_counts_asked; + + reg dfifo_has_enough_room; + reg [1:0] wait_cnt; + reg wait_done; + + assign rd_mdata_en = rd_en_r; + + generate + if (FAMILY == "SPARTAN6") + begin: gen_sp6_cmd_rdy + + always @ (posedge clk_i) + cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done; + end + +// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") || +// (FAMILY == "VIRTEX6") ) + else + begin: gen_v6_cmd_rdy + + always @ (posedge clk_i) + cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room; + end + endgenerate + + always @ (posedge clk_i) + begin + if (rst_i) + wait_cnt <= #TCQ 'b0; + else if (cmd_rdy_o && cmd_valid_i) + wait_cnt <= #TCQ 2'b10; + else if (wait_cnt > 0) + wait_cnt <= #TCQ wait_cnt - 1'b1; + + end + + always @(posedge clk_i) + begin + if (rst_i) + wait_done <= #TCQ 1'b1; + else if (cmd_rdy_o && cmd_valid_i) + wait_done <= #TCQ 1'b0; + else if (wait_cnt == 0) + wait_done <= #TCQ 1'b1; + else + wait_done <= #TCQ 1'b0; + + end + + reg dfifo_has_enough_room_d1; + always @ (posedge clk_i) + begin + dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0; + dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ; + end + + // remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop + // sending more read commands but still accepting it if there is one coming. + assign wr_en = cmd_valid_i & !full & wait_done; + + + + always @ (posedge clk_i) + begin + if (rst_i) begin + rd_data_counts_asked <= #TCQ 'b0; + end + else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin + if (FAMILY == "SPARTAN6") + rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ; + else + // if (nCK_PER_CLK == 2 ) + // rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ; + // else + // rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ; + + if (nCK_PER_CLK == 4 || (nCK_PER_CLK == 2 && (MEM_BURST_LEN == 4 || MEM_BURST_LEN == 2 ) )) + rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ; + else if (nCK_PER_CLK == 2 && MEM_BURST_LEN == 8) + rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ; + + + + end + end + + always @ (posedge clk_i) + begin + if (rst_i) begin + rd_data_received_counts <= #TCQ 'b0; + end + else if (data_valid_i) begin + rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1; + end + end + + // calculate how many buf still available + always @ (posedge clk_i) + if (rd_data_received_counts[6] == rd_data_counts_asked[6]) + buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 ); + + else + buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] ); + + + always @ (posedge clk_i) begin + rd_en_r <= #TCQ cmd_start_i; + end + + + + assign gen_valid_o = !empty; + mig_7series_v4_2_afifo # + ( + .TCQ (TCQ), + .DSIZE (BL_WIDTH+ADDR_WIDTH), + .FIFO_DEPTH (16), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_fifo + ( + .wr_clk (clk_i), + .rst (rst_i), + .wr_en (wr_en), + .wr_data ({bl_i,addr_i}), + .rd_en (rd_en_r), + .rd_clk (clk_i), + .rd_data ({gen_bl_o,gen_addr_o}), + .full (full), + .empty (empty), + .almost_full () + + ); + + + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_s7ven_data_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_s7ven_data_gen.v new file mode 100644 index 0000000..39cf9ab --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_s7ven_data_gen.v @@ -0,0 +1,1047 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MEMC +// / / Filename: mcb_traffic_gen.v +// /___/ /\ Date Last Modified: $Date: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Virtex7 +//Design Name: s7ven_data_gen +//Purpose: This is top level module of memory traffic generator which can +// generate different CMD_PATTERN and DATA_PATTERN to Virtex 7 +// hard memory controller core. +// Supported Data pattern: 0 : Reserved. +// 1 : FIXED_DATA_MODE. +// 2 : ADDR_DATA_MODE +// 3 : HAMMER_DATA_MODE +// 4 : NEIGHBOR_DATA_MODE +// 5 : WALKING1_DATA_MODE +// 6 : WALKING0_DATA_MODE +// 7 : TRUE_PRBS_MODE +// +// +//Reference: +//Revision History: 1.1 +// 06/2011 Rewrite PRBS code. + +//***************************************************************************** + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + +module mig_7series_v4_2_s7ven_data_gen # + +( parameter DMODE = "WRITE", + parameter nCK_PER_CLK = 2, // 2: Memc core speed 1/2 of memory clock speed. + // User data bus width = 4 x DQs data width. + // 4: memc core speed 1/4 of memory clock speed. + // User data bus width = 8 x DQs data width. + parameter MEM_TYPE = "DDR3", + + parameter TCQ = 100, + parameter BL_WIDTH = 6, // USER_Interface Command Burst Length + parameter FAMILY = "SPARTAN6", + + parameter EYE_TEST = "FALSE", + parameter ADDR_WIDTH = 32, + parameter MEM_BURST_LEN = 8, + parameter START_ADDR = 32'h00000000, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 72, + parameter COLUMN_WIDTH = 10, + parameter SEL_VICTIM_LINE = 3 // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern +// parameter [287:0] ALL_1 = {288{1'b1}}, +// parameter [287:0] ALL_0 = {288{1'b0}} + + + ) + ( + input clk_i, // + input rst_i, + input [31:0] prbs_fseed_i, + input mode_load_i, + input mem_init_done_i, + input wr_data_mask_gen_i, + input [3:0] data_mode_i, // "00" = bram; + input data_rdy_i, + input cmd_startA, + input cmd_startB, + input cmd_startC, + input cmd_startD, + input cmd_startE, + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern. + input [31:0] fixed_data_i, + + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH:0] user_burst_cnt, // generated burst length for control the burst data + + input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen + // connect from mcb_rd_empty when used as rd_data_gen + // When both data_rdy and data_valid is asserted, the ouput data is valid. + // input [(DWIDTH/8)-1:0] wr_mask_count; + output [(NUM_DQ_PINS*nCK_PER_CLK*2/8)-1:0] data_mask_o, + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o , // generated data pattern + output reg [31:0] tg_st_addr_o, + output bram_rd_valid_o +); +// + +localparam PRBS_WIDTH = 8;//BL_WIDTH; +localparam TAPS_VALUE = (BL_WIDTH == 8) ? 8'b10001110 : + // (BL_WIDTH == 10) ? 10'b1000000100: + 8'b10001110 ; + + +wire [31:0] prbs_data; +reg [35:0] acounts; + +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] fdata; +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] bdata; +wire [31:0] bram_data; + +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata_tmp; +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata; + +wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] hammer_data; + +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data; +reg [NUM_DQ_PINS*2-1:0] hdata; + +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w0data; +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data; + +reg burst_count_reached2; + +reg data_valid; +reg [2:0] walk_cnt; +reg [ADDR_WIDTH-1:0] user_address; +reg [ADDR_WIDTH-1:0] m_addr_r; // generated address used to determine data pattern. +reg sel_w1gen_logic; +//reg [7:0] BLANK; +reg [4*NUM_DQ_PINS -1 :0] sel_victimline_r; +reg data_clk_en,data_clk_en2 /* synthesis syn_maxfan = 10 */; +wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] full_prbs_data2; +wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] psuedo_prbs_data; + +wire [127:0] prbs_shift_value; +reg next_calib_data; +reg [2*nCK_PER_CLK*NUM_DQ_PINS-1:0 ] calib_data; +wire [2*nCK_PER_CLK*NUM_DQ_PINS/8 -1:0] w1data_group; +wire [31:0] mcb_prbs_data; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_0; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_0; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_1; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_1; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_2; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_2; +wire [NUM_DQ_PINS-1:0] prbsdata_rising_3; +wire [NUM_DQ_PINS-1:0] prbsdata_falling_3 ; + +wire [BL_WIDTH-1:0] prbs_o0,prbs_o1,prbs_o2,prbs_o3,prbs_o4,prbs_o5,prbs_o6,prbs_o7; +wire [BL_WIDTH-1:0] prbs_o8,prbs_o9,prbs_o10,prbs_o11,prbs_o12,prbs_o13,prbs_o14,prbs_o15; + + +//wire [nCK_PER_CLK * 32 -1 :0] prbs_shift_value; + +wire [32*NUM_DQ_PINS-1:0] ReSeedcounter; + + +reg [3:0] htstpoint ; +reg data_clk_en2_r; +reg [NUM_DQ_PINS-1:0] wdatamask_ripplecnt; +//wire [4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] ALL_1 = +reg mode_load_r; +reg user_burst_cnt_larger_1_r; +reg user_burst_cnt_larger_bram; + + +integer i,j,k; + +localparam NUM_WIDTH = 2*nCK_PER_CLK*NUM_DQ_PINS; +localparam USER_BUS_DWIDTH = (nCK_PER_CLK == 2) ? NUM_DQ_PINS*4 : NUM_DQ_PINS*8; + +// MODIFIED richc 061711 +//wire [PRBS_WIDTH-1:0] prbs_seed; + wire [2*nCK_PER_CLK-1:0] prbs_out [NUM_DQ_PINS-1:0]; + wire [PRBS_WIDTH-1:0] prbs_seed [NUM_DQ_PINS-1:0]; +//********************************************************************************************* +localparam BRAM_DATAL_MODE = 4'b0000; +localparam FIXED_DATA_MODE = 4'b0001; +localparam ADDR_DATA_MODE = 4'b0010; +localparam HAMMER_DATA_MODE = 4'b0011; +localparam NEIGHBOR_DATA_MODE = 4'b0100; +localparam WALKING1_DATA_MODE = 4'b0101; +localparam WALKING0_DATA_MODE = 4'b0110; +localparam PRBS_DATA_MODE = 4'b0111; + +assign data_o = data; +generate +if (nCK_PER_CLK == 4) +begin: full_prbs_data64 +//always @ (prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0) + assign full_prbs_data2 = {prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0}; +end +else +begin: full_prbs_data32 + assign full_prbs_data2 = {prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0}; +end +endgenerate +generate + +genvar p; + +for (p = 0; p < NUM_DQ_PINS*nCK_PER_CLK*2/32; p = p+1) +begin + assign psuedo_prbs_data[p*32+31:p*32] = mcb_prbs_data; + +end +endgenerate + + + +reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data_o; +reg [3:0] data_mode_rr_a; +reg [3:0] data_mode_rr_c; + +// write data mask generation. +// Only support data pattern = address data mode. +// When wdatamask_ripple_cnt is asserted, the corresponding wr_data word will be jammed with 8'hff. + +assign data_mask_o = (wr_data_mask_gen_i == 1'b1 && mem_init_done_i) ? wdatamask_ripplecnt :{ NUM_DQ_PINS*nCK_PER_CLK*2/8{1'b0}}; + +always @ (posedge clk_i) +begin +if (rst_i || ~wr_data_mask_gen_i || ~mem_init_done_i) + wdatamask_ripplecnt <= 'b0; +else if (cmd_startA) + //wdatamask_ripplecnt <= {15'd0,1'b1}; + wdatamask_ripplecnt <= {{NUM_DQ_PINS-1{1'b0}},1'b1}; + +else if (user_burst_cnt_larger_1_r && data_rdy_i) + wdatamask_ripplecnt <= {wdatamask_ripplecnt[NUM_DQ_PINS-2:0],wdatamask_ripplecnt[NUM_DQ_PINS-1]}; + + +end + + +generate +genvar n; +for (n = 0; n < NUM_DQ_PINS*nCK_PER_CLK*2/8; n = n+1) +begin + + if (MEM_TYPE == "QDR2PLUS") + assign adata = adata_tmp;// QDR not supporting masking + else + assign adata[n*8+7:n*8] = adata_tmp[n*8+7:n*8]| {8{wdatamask_ripplecnt[NUM_DQ_PINS-1]}}; + +end +endgenerate + + +always @ (posedge clk_i) +begin + data_mode_rr_a <= #TCQ data_mode_i; + data_mode_rr_c <= #TCQ data_mode_i; + +end + + + +assign bdata = {USER_BUS_DWIDTH/32{bram_data[31:0]}}; + +// selected data pattern go through "data" mux to user data bus. +// 72 pin 1: failed +always @ (bdata,calib_data,hammer_data,adata,data_mode_rr_a,w1data,full_prbs_data2,psuedo_prbs_data) +begin + case(data_mode_rr_a) // + // Simple Data Pattern for bring up + // 0: Reserved + // 1: 32 bits fixed_data from user defined inputs. + // The data from this static pattern is concatenated together multiple times + // to make up the required number of bits as needed. + // 2: 32 bits address as data + // The data from this pattern is concatenated together multiple times + // to make up the required number of bits as needed. + // 4: simple 8data pattern and repeats every 8 words. The pattern is embedded in RAM. + // 5,6: Walkign 1,0 data. + // a Calibration data pattern + + // 0,1,2,3,4,9: use bram to implemnt. + 4'b0000,4'b0001,4'b0100,4'b1001: data = bdata; + 4'b0010: data = adata; // address as data + + 4'b0011: data = hammer_data; + + + 4'b0101, 4'b110: data = w1data; // walking 1 or walking 0 data + // when vio_instr_mode_value set to 4'hf,the init_mem_pattern_ctr module + // will automatically set the data_mode_o to 0x8 + 4'b1010: data =calib_data; + + + // Characterization Mode + // 2: Address as data + // 3: hammer data with option to select VICTIM line which output is always high. + // 7: Hammer PRBS. Only valid in V6,V7 family + // 9: Slow 2 MHz hammer pattern. + 4'b0111: data = full_prbs_data2;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs + 4'b1000: data = psuedo_prbs_data;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs + + default : begin + // for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) begin: neighbor_data + // data = begin + // for ( + data = adata; + end + endcase +end + +// phy calibration data pattern +// +generate +if (nCK_PER_CLK == 2) +begin: calib_data32 +always @ (posedge clk_i) +if (rst_i) begin + next_calib_data <= 1'b0; + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}}; + end +else if (cmd_startA) + begin + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}}; + next_calib_data <=#TCQ 1'b1; +// calib_data <= 'b0; + end + else if (fifo_rdy_i) + begin + next_calib_data <= #TCQ ~next_calib_data; + if (next_calib_data ) + + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h66}},{(NUM_DQ_PINS/8){8'h99}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h55}}}; + else + calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}}; + end +end +else +begin: calib_data64 // when nCK_PER_LK =4 has not verified +always @ (posedge clk_i) + +if (rst_i) begin + next_calib_data <= 1'b0; + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}}; + end +else if (cmd_startA) + begin + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}}; + next_calib_data <=#TCQ 1'b1; +// calib_data <= 'b0; + end + else if (fifo_rdy_i) + begin + next_calib_data <= #TCQ ~next_calib_data; + if (next_calib_data ) + + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h6666}},{(NUM_DQ_PINS/8){16'h9999}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h5555}}}; + else + calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}}; + end + + +end +endgenerate +/* + +always @ (posedge clk_i) +begin calib_data <= 'b0; + +end +*/ +//************************************************************************** +// Pattern bram generates fixed input, hammer, simple 8 repeat data pattern. +//************************************************************************** + +function integer logb2; + input [31:0] number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end +endfunction + + + +mig_7series_v4_2_vio_init_pattern_bram # +( .MEM_BURST_LEN (MEM_BURST_LEN), + .START_ADDR (START_ADDR), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE) + +) +vio_init_pattern_bram +( + .clk_i (clk_i ), + .rst_i (rst_i ), + // BL8 : least 3 address bits are always zero. + // BL4 " least 2 address bits are always zero. + // for walking 1's or 0's, the least 8 address bits are always zero. + .cmd_addr (addr_i), + .cmd_start (cmd_startB), + .mode_load_i (mode_load_i), + .data_mode_i (data_mode_rr_a), + //.w1data (w1data), + .data0 (simple_data0 ), + .data1 (simple_data1 ), + .data2 (simple_data2 ), + .data3 (simple_data3 ), + .data4 (simple_data4 ), + .data5 (simple_data5 ), + .data6 (simple_data6 ), + .data7 (simple_data7 ), + .data8 (fixed_data_i ), + + .bram_rd_valid_o (bram_rd_valid_o), + .bram_rd_rdy_i (user_burst_cnt_larger_bram & (data_rdy_i | cmd_startB)), + .dout_o (bram_data) + + ); + + + +//************************************************************** +// Functions to be used byg Walking 1 and Walking 0 circuits. +//************************************************************** + + +function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_Gen (input integer i ); + integer j; + begin + j = i/2; + Data_Gen = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b0}}; + if(i %2 == 1) begin + if (nCK_PER_CLK == 2) begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + end + else begin + + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + + end + end else begin + if (nCK_PER_CLK == 2) begin + if (MEM_TYPE == "QDR2PLUS") begin + //QDR sends the high order data bit out first to memory. + + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + end else begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + end + end + else begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + + end + + + + + + end + + + end +endfunction + + + +function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_GenW0 (input integer i); + integer j; + begin + j = i/2; + Data_GenW0 = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b1}}; + + if(i %2 == 1) begin + if (nCK_PER_CLK == 2) begin + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + + end + else begin + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + + Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + + end + end else begin + if (nCK_PER_CLK == 2) begin + + + if (MEM_TYPE == "QDR2PLUS") begin + //QDR sends the high order data bit out first to memory. + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + end else begin + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + end + + end + else begin + + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + + end + end + + + end +endfunction + +always @ (posedge clk_i) begin + if (data_mode_rr_c[2:0] == 3'b101 || data_mode_rr_c[2:0] == 3'b100 || data_mode_rr_c[2:0] == 3'b110) // WALKING ONES + sel_w1gen_logic <= #TCQ 1'b1; + else + sel_w1gen_logic <= #TCQ 1'b0; +end + + + +generate +genvar m; + for (m=0; m < (2*nCK_PER_CLK*NUM_DQ_PINS/8) - 1; m= m+1) + begin: w1_gp + assign w1data_group[m] = ( (w1data[(m*8+7):m*8]) != 8'h00); + end +endgenerate + + + + generate + if ((NUM_DQ_PINS == 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) + begin : WALKING_ONE_8_PATTERN + if (nCK_PER_CLK == 2) begin : WALKING_ONE_8_PATTERN_NCK_2 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end // end of always + end // end of nCK_PER_CLK == 2 + else + begin: WALKING_ONE_8_PATTERN_NCK_4 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i ) begin + w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS ]; + w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS ]; + w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS ]; + w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS ]; + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS ]; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS ]; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS ]; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS ]; + end + end // end of always + end // end of nCK_PER_CLK == 4 + end + + else if ((NUM_DQ_PINS != 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) + begin : WALKING_ONE_64_PATTERN + if (nCK_PER_CLK == 2) begin : WALKING_ONE_64_PATTERN_NCK_2 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end // end of always + end //end of nCK_PER_CLK == 2 + else + begin: WALKING_ONE_64_PATTERN_NCK_4 + always @ (posedge clk_i) begin + if( (fifo_rdy_i) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32'b0); + else + w1data <= #TCQ Data_GenW0(32'b0); + end + end + else if (fifo_rdy_i) begin + w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ {w1data[8*NUM_DQ_PINS - 9:7*NUM_DQ_PINS ],w1data[8*NUM_DQ_PINS - 1:8*NUM_DQ_PINS - 8]}; + w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ {w1data[7*NUM_DQ_PINS - 9:6*NUM_DQ_PINS ],w1data[7*NUM_DQ_PINS - 1:7*NUM_DQ_PINS - 8]}; + w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ {w1data[6*NUM_DQ_PINS - 9:5*NUM_DQ_PINS ],w1data[6*NUM_DQ_PINS - 1:6*NUM_DQ_PINS - 8]}; + w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ {w1data[5*NUM_DQ_PINS - 9:4*NUM_DQ_PINS ],w1data[5*NUM_DQ_PINS - 1:5*NUM_DQ_PINS - 8]}; + + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 9:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 8]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 9:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 8]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 9:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 8]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 9:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 8]}; + end + end // end of always + end //end of nCK_PER_CLK == 4 + end + + else + begin: NO_WALKING_PATTERN + always @ (posedge clk_i) + w1data <= 'b0; + end + endgenerate + + +// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine +// the position of the pin driving oppsite polarity +// addr_i[6:2] = 5'h0f ; 32 bit data port +// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111 +// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 + +// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level. +always @ (posedge clk_i) +begin + for (i= 0; i <= 2*NUM_DQ_PINS - 1; i= i+1) //begin: hammer_data + + if ( i >= NUM_DQ_PINS ) + if (SEL_VICTIM_LINE == NUM_DQ_PINS) + hdata[i] <= 1'b0; + else if ( + ((i == SEL_VICTIM_LINE-1) || + (i-NUM_DQ_PINS) == SEL_VICTIM_LINE ))//|| + + hdata[i] <= 1'b1; + else + hdata[i] <= 1'b0; + + else + + hdata[i] <= 1'b1; + + +end +generate +if (nCK_PER_CLK == 2) +begin : HAMMER_2 + assign hammer_data = {2{hdata[2*NUM_DQ_PINS - 1:0]}}; +end +else +begin : HAMMER_4 + assign hammer_data = {4{hdata[2*NUM_DQ_PINS - 1:0]}}; +end +endgenerate + + +// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 32'h12345678, burst length 8 +// => the 1st data pattern : 32'h12345680 +// => the 2nd data pattern : 32'h12345688 +// => the 3rd data pattern : 32'h12345690 +// => the 4th data pattern : 32'h12345698 +generate + +reg COut_a; +if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL") +begin : ADDRESS_PATTERN + always @ (posedge clk_i) + begin + if (cmd_startD) + /// 35:0 + acounts <= #TCQ {4'b0000,addr_i} ; + else if (user_burst_cnt_larger_1_r && data_rdy_i ) begin + if (nCK_PER_CLK == 2) + if (FAMILY == "VIRTEX6") + if (MEM_TYPE == "QDR2PLUS") + {COut_a,acounts} <= #TCQ acounts + 1; + else + {COut_a,acounts} <= #TCQ acounts + 4; + + else begin // "SPARTAN6" + if (DWIDTH == 32) + {COut_a,acounts} <= #TCQ acounts + 4; + else if (DWIDTH == 64) + {COut_a,acounts} <= #TCQ acounts + 8; + else if (DWIDTH == 64) + {COut_a,acounts} <= #TCQ acounts + 16; + end + else + {COut_a,acounts} <= #TCQ acounts + 8; + end + else + acounts <= #TCQ acounts; + + end + + assign adata_tmp = {USER_BUS_DWIDTH/32{acounts[31:0]}}; + + end +else +begin: NO_ADDRESS_PATTERN + assign adata_tmp = 'b0; +end +endgenerate + + always @ (posedge clk_i) + begin + if (cmd_startD) + tg_st_addr_o <= addr_i; + end + +// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4 +// + +// this user_burst_cnt_larger_bram is used by vio_init_pattern_bram module +// only +always @ (posedge clk_i) + if (user_burst_cnt > 6'd1 || cmd_startE) + user_burst_cnt_larger_bram <= 1'b1; + else + user_burst_cnt_larger_bram <= 1'b0; + + +generate +if (DMODE == "WRITE") +begin: wr_ubr + always @ (posedge clk_i) + if (user_burst_cnt > 6'd1 || cmd_startE) + user_burst_cnt_larger_1_r <= 1'b1; + else + user_burst_cnt_larger_1_r <= 1'b0; +end +else +begin: rd_ubr + + always @ (posedge clk_i) + if (user_burst_cnt >= 6'd1 || cmd_startE) + user_burst_cnt_larger_1_r <= 1'b1; + else if (ReSeedcounter[31:0] == 255) + user_burst_cnt_larger_1_r <= 1'b0; +end +endgenerate + + +generate +// When doing eye_test, traffic gen only does write and want to +// keep the prbs random and address is fixed at a location. +if (EYE_TEST == "TRUE") +begin : d_clk_en1 +always @(data_clk_en) + data_clk_en = 1'b1;//fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1; +end +else if (DMODE == "WRITE") + begin: wr_dataclken + always @ (data_rdy_i , user_burst_cnt_larger_1_r,ReSeedcounter[31:0]) + +begin + + if ( data_rdy_i && (user_burst_cnt_larger_1_r || ReSeedcounter[31:0] == 255 )) + data_clk_en = 1'b1; +else + data_clk_en = 1'b0; +end + +always @ (data_rdy_i , user_burst_cnt_larger_1_r,ReSeedcounter) +begin + + if ( data_rdy_i && (user_burst_cnt_larger_1_r || ReSeedcounter[31:0] == 255 )) + data_clk_en2 = 1'b1; + else + data_clk_en2 = 1'b0; + end + end else // (DMODE == "READ") + begin: rd_dataclken + always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r) + begin + if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r ) + data_clk_en <= 1'b1; + else + data_clk_en <= 1'b0; + end + always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r) + begin + if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r ) + data_clk_en2 <= 1'b1; +else + data_clk_en2 <= 1'b0; +end + +end +endgenerate + +generate +if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL") +begin : PSUEDO_PRBS_PATTERN + +// PRBS DATA GENERATION +// xor all the tap positions before feedback to 1st stage. + always @ (posedge clk_i) + m_addr_r <= m_addr_i; + + + mig_7series_v4_2_data_prbs_gen # + ( + .PRBS_WIDTH (32), + .SEED_WIDTH (32), + .EYE_TEST (EYE_TEST) + ) + data_prbs_gen + ( + .clk_i (clk_i), + .rst_i (rst_i), + .clk_en (data_clk_en), + + .prbs_seed_init (cmd_startE), + .prbs_seed_i (m_addr_i[31:0]), + .prbs_o (mcb_prbs_data) + + ); +end +else +begin:NO_PSUEDO_PRBS_PATTERN + assign mcb_prbs_data = 'b0; +end +endgenerate + + //*************************************************************************** + // "Full pseudo-PRBS" data generation + //*************************************************************************** + + genvar r; + + // Assign initial seed (used for 1st data bit); use alternating 1/0 pat + assign prbs_seed[0] = {(PRBS_WIDTH/2){2'b10}}; + + // Generate seeds for all other data bits, each one is staggered in time + // by one LFSR shift from the preceeding bit + + + + + + + + + + + generate + if (PRBS_WIDTH == 8) begin: gen_seed_prbs8 + for (r = 1; r < NUM_DQ_PINS; r = r + 1) begin: gen_loop_seed_prbs + // PRBS 8 - feedback uses taps [7,5,4,3] + assign prbs_seed[r] = {prbs_seed[r-1][PRBS_WIDTH-2:0], + ~(prbs_seed[r-1][7] ^ prbs_seed[r-1][5] ^ + prbs_seed[r-1][4] ^ prbs_seed[r-1][3])}; + end + end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10 + // PRBS 10 - feedback uses taps [9,6] + for (r = 1; r < NUM_DQ_PINS; r = r + 1) begin: gen_loop_seed_prbs + assign prbs_seed[r] = {prbs_seed[r-1][PRBS_WIDTH-2:0], + ~(prbs_seed[r-1][9] ^ prbs_seed[r-1][6])}; + end + end + endgenerate + + // Instantiate one PRBS per data bit. Note this is only temporary - + // eventually it will be far more efficient to use a large shift register + // that is initialized with 2*CK_PER_CLK*NUM_DQ_PINS worth of LFSR cycles + // rather than individual PRBS generators. For now this is done because + // not sure if current logic allows for the initial delay required to fill + // this large shift register + generate + for (r = 0; r < NUM_DQ_PINS; r = r + 1) begin: gen_prbs_modules + mig_7series_v4_2_tg_prbs_gen # + (.nCK_PER_CLK (nCK_PER_CLK), + .TCQ (TCQ), + .PRBS_WIDTH (PRBS_WIDTH) + ) + u_data_prbs_gen + ( + .clk_i (clk_i), + .rst_i (rst_i), + .clk_en_i (data_clk_en), + .prbs_seed_i (prbs_seed[r]), + .prbs_o (prbs_out[r]), + .ReSeedcounter_o (ReSeedcounter[32*r+:32]) + ); + end + endgenerate + + generate + for (r = 0; r < NUM_DQ_PINS; r = r + 1) begin: gen_prbs_rise_fall_data + if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 + assign prbsdata_rising_0[r] = prbs_out[r][0]; + assign prbsdata_falling_0[r] = prbs_out[r][1]; + assign prbsdata_rising_1[r] = prbs_out[r][2]; + assign prbsdata_falling_1[r] = prbs_out[r][3]; + end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign prbsdata_rising_0[r] = prbs_out[r][0]; + assign prbsdata_falling_0[r] = prbs_out[r][1]; + assign prbsdata_rising_1[r] = prbs_out[r][2]; + assign prbsdata_falling_1[r] = prbs_out[r][3]; + assign prbsdata_rising_2[r] = prbs_out[r][4]; + assign prbsdata_falling_2[r] = prbs_out[r][5]; + assign prbsdata_rising_3[r] = prbs_out[r][6]; + assign prbsdata_falling_3[r] = prbs_out[r][7]; + end + end + endgenerate + + //*************************************************************************** + +//***debug PRBS in ddr3 hware +//assign dbg_prbs_tpts[15:0] = {prbs_shift_value3 ,prbs_shift_value2,prbs_shift_value1,prbs_shift_value0}; +//assign dbg_prbs_tpts[21:16] = prbs_mux_counter[5:0]; +//assign dbg_prbs_tpts[22] = data_clk_en2; +//assign dbg_prbs_tpts[23] = mode_load_r1 ; +//assign dbg_prbs_tpts[24] = mode_has_loaded; +//fifo_rdy_i && data_rdy_i +//assign dbg_prbs_tpts[25] = data_rdy_i; +//assign dbg_prbs_tpts[26] = fifo_rdy_i; + +//assign dbg_prbs_tpts[31:27] = 'b0; + +//assign dbg_prbs_tpts[63:32] = ReSeedcounter[31:0]; +//assign dbg_prbs_tpts[64+:10] = user_burst_cnt[9:0]; +//assign dbg_prbs_tpts[74] = user_burst_cnt_larger_1_r; + +//assign dbg_prbs_tpts[127:75] = 'b0; + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v new file mode 100644 index 0000000..a4cf47e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_prbs_gen.v @@ -0,0 +1,246 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: tb_cmd_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: 7 Series +//Design Name: PRBS_Generator +//Purpose: +// Overview: +// Implements a "pseudo-PRBS" generator. Basically this is a standard +// PRBS generator (using an linear feedback shift register) along with +// logic to force the repetition of the sequence after 2^PRBS_WIDTH +// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design +// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains +// are supported in this code +// Parameter Requirements: +// 1. PRBS_WIDTH = 8 or 10 +// 2. PRBS_WIDTH >= 2*nCK_PER_CLK +// Output notes: +// The output of this module consists of 2*nCK_PER_CLK bits, these contain +// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note +// that prbs_o[0] contains the bit value for the "earliest" bit time. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_tg_prbs_gen # + ( + parameter TCQ = 100, // clk->out delay (sim only) + parameter PRBS_WIDTH = 10, // LFSR shift register length + parameter nCK_PER_CLK = 4 // output:internal clock freq ratio + ) + ( + input clk_i, // input clock + input clk_en_i, // clock enable + input rst_i, // synchronous reset + input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed + output [2*nCK_PER_CLK-1:0] prbs_o, // generated address + // ReSeedcounter used to indicate when pseudo-PRBS sequence has reached + // the end of it's cycle. May not be needed, but for now included to + // maintain compatibility with current TG code + output [31:0] ReSeedcounter_o + ); + + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + + // Number of internal clock cycles before the PRBS sequence will repeat + localparam PRBS_SEQ_LEN_CYCLES = (2**PRBS_WIDTH) / (2*nCK_PER_CLK); + localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES); + + reg [PRBS_WIDTH-1:0] lfsr_reg_r; + wire [PRBS_WIDTH-1:0] next_lfsr_reg; + reg [PRBS_WIDTH-1:0] reseed_cnt_r; + reg reseed_prbs_r; + reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r; + + genvar i; + + //*************************************************************************** + + assign ReSeedcounter_o = {{(32-PRBS_WIDTH){1'b0}}, reseed_cnt_r}; + always @ (posedge clk_i) + if (rst_i) + reseed_cnt_r <= 'b0; + else if (clk_en_i) + if (reseed_cnt_r == {PRBS_WIDTH {1'b1}}) + reseed_cnt_r <= 'b0; + else + reseed_cnt_r <= reseed_cnt_r + 1; + + //*************************************************************************** + + // Generate PRBS reset signal to ensure that PRBS sequence repeats after + // every 2**PRBS_WIDTH samples. Basically what happens is that we let the + // LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1 + // samples have past. Once that extra cycle is finished, we reseed the LFSR + always @(posedge clk_i) + if (rst_i) begin + sample_cnt_r <= #TCQ 'b0; + reseed_prbs_r <= #TCQ 1'b0; + end else if (clk_en_i) begin + // The rollver count should always be [(power of 2) - 1] + sample_cnt_r <= #TCQ sample_cnt_r + 1; + // Assert PRBS reset signal so that it is simultaneously with the + // last sample of the sequence + if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2) + reseed_prbs_r <= #TCQ 1'b1; + else + reseed_prbs_r <= #TCQ 1'b0; + end + + // Load initial seed or update LFSR contents + always @(posedge clk_i) + if (rst_i) + lfsr_reg_r <= #TCQ prbs_seed_i; + else if (clk_en_i) + if (reseed_prbs_r) + lfsr_reg_r <= #TCQ prbs_seed_i; + else begin + lfsr_reg_r <= #TCQ next_lfsr_reg; + end + + // Calculate next set of nCK_PER_CLK samplse for LFSR + // Basically we calculate all PRBS_WIDTH samples in parallel, rather + // than serially shifting the LFSR to determine future sample values. + // Shifting is possible, but requires multiple shift registers to be + // instantiated because the fabric clock frequency is running at a + // fraction of the output clock frequency + generate + if (PRBS_WIDTH == 8) begin: gen_next_lfsr_prbs8 + if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 + assign next_lfsr_reg[7] = lfsr_reg_r[3]; + assign next_lfsr_reg[6] = lfsr_reg_r[2]; + assign next_lfsr_reg[5] = lfsr_reg_r[1]; + assign next_lfsr_reg[4] = lfsr_reg_r[0]; + assign next_lfsr_reg[3] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^ + lfsr_reg_r[4] ^ lfsr_reg_r[3]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^ + lfsr_reg_r[3] ^ lfsr_reg_r[2]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^ + lfsr_reg_r[2] ^ lfsr_reg_r[1]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^ + lfsr_reg_r[1] ^ lfsr_reg_r[0]); + end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign next_lfsr_reg[7] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^ + lfsr_reg_r[4] ^ lfsr_reg_r[3]); + assign next_lfsr_reg[6] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^ + lfsr_reg_r[3] ^ lfsr_reg_r[2]) ; + assign next_lfsr_reg[5] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^ + lfsr_reg_r[2] ^ lfsr_reg_r[1]); + assign next_lfsr_reg[4] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^ + lfsr_reg_r[1] ^ lfsr_reg_r[0]); + assign next_lfsr_reg[3] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[1] ^ + lfsr_reg_r[0] ^ next_lfsr_reg[7]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[2] ^ lfsr_reg_r[0] ^ + next_lfsr_reg[7] ^ next_lfsr_reg[6]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[1] ^ next_lfsr_reg[7] ^ + next_lfsr_reg[6] ^ next_lfsr_reg[5]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[0] ^ next_lfsr_reg[6] ^ + next_lfsr_reg[5] ^ next_lfsr_reg[4]); + end + end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10 + if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2 + assign next_lfsr_reg[9] = lfsr_reg_r[5]; + assign next_lfsr_reg[8] = lfsr_reg_r[4]; + assign next_lfsr_reg[7] = lfsr_reg_r[3]; + assign next_lfsr_reg[6] = lfsr_reg_r[2]; + assign next_lfsr_reg[5] = lfsr_reg_r[1]; + assign next_lfsr_reg[4] = lfsr_reg_r[0]; + assign next_lfsr_reg[3] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]); + end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 + assign next_lfsr_reg[9] = lfsr_reg_r[1]; + assign next_lfsr_reg[8] = lfsr_reg_r[0]; + assign next_lfsr_reg[7] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]); + assign next_lfsr_reg[6] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]); + assign next_lfsr_reg[5] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]); + assign next_lfsr_reg[4] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]); + assign next_lfsr_reg[3] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[2]); + assign next_lfsr_reg[2] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[1]); + assign next_lfsr_reg[1] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[0]); + assign next_lfsr_reg[0] = ~(lfsr_reg_r[2] ^ next_lfsr_reg[7]); + end + end + endgenerate + + // Output highest (2*nCK_PER_CLK) taps of LFSR - note that the "earliest" + // tap is highest tap (e.g. for an 8-bit LFSR, tap[7] contains the first + // data sent out the shift register), therefore tap[PRBS_WIDTH-1] must be + // routed to bit[0] of the output, tap[PRBS_WIDTH-2] to bit[1] of the + // output, etc. + generate + for (i = 0; i < 2*nCK_PER_CLK; i = i + 1) begin: gen_prbs_transpose + assign prbs_o[i] = lfsr_reg_r[PRBS_WIDTH-1-i]; + end + endgenerate + + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_status.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_status.v new file mode 100644 index 0000000..8ef66fd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_tg_status.v @@ -0,0 +1,127 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: tg_status.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. +// Error signal will be asserted if the comparsion is not equal. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + + +module mig_7series_v4_2_tg_status #( + parameter TCQ = 100, + + parameter DWIDTH = 32 + ) + ( + + + input clk_i , + input rst_i , + input manual_clear_error, + input data_error_i , + input [DWIDTH-1:0] cmp_data_i, + input [DWIDTH-1:0] rd_data_i , + input [31:0] cmp_addr_i , + input [5:0] cmp_bl_i , + input mcb_cmd_full_i , + input mcb_wr_full_i, + input mcb_rd_empty_i, + output reg [64 + (2*DWIDTH - 1):0] error_status, + output error + ); + +reg data_error_r; +reg error_set; +assign error = error_set; + +always @ (posedge clk_i) + data_error_r <= #TCQ data_error_i; + +always @ (posedge clk_i) +begin + +if (rst_i || manual_clear_error) begin + error_status <= #TCQ 'b0; + error_set <= #TCQ 1'b0; +end +else begin + // latch the first error only + if (data_error_i && ~data_error_r && ~error_set ) begin + error_status[31:0] <= #TCQ cmp_addr_i; + error_status[37:32] <= #TCQ cmp_bl_i; + error_status[40] <= #TCQ mcb_cmd_full_i; + error_status[41] <= #TCQ mcb_wr_full_i; + error_status[42] <= #TCQ mcb_rd_empty_i; + error_set <= #TCQ 1'b1; + error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; + error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; + + end + + error_status[39:38] <= #TCQ 'b0; // reserved + error_status[63:43] <= #TCQ 'b0; // reserved + + +end end + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v new file mode 100644 index 0000000..f3ede28 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_traffic_gen_top.v @@ -0,0 +1,627 @@ +//***************************************************************************** +// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Application : MIG +// \ \ Filename : traffic_gen_top.v +// / / Date Last Modified : $Date: 2011/06/02 08:37:25 $ +// /___/ /\ Date Created : Fri Mar 26 2010 +// \ \ / \ +// \___\/\___\ +// +//Device : Virtex-7 +//Design Name : DDR/DDR2/DDR3/LPDDR +//Purpose : This Traffic Gen supports both nCK_PER_CLK x4 mode and nCK_PER_CLK x2 mode for +// 7series MC UI Interface. The user bus datawidth has a equation: 2*nCK_PER_CLK*DQ_WIDTH. +// +//Reference : +//Revision History : 11/17/2011 Adding CMD_GAP_DELAY to allow control of next command generation after current +// completion of burst command in user interface port. +// 1/4/2012 Added vio_percent_write in memc_traffic_gen module to let user specify percentage +// of write commands out of mix write/read commands. User can +// modify this file and bring the signals to top level to use it. +// The value is between 1(10 percent) through 10 (100 percent). +// The signal value is only used if vio_instr_mode_value == 4. +// 5/21/2012 Removed BL_WIDTH parameter and forced internally to 10. +// +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_traffic_gen_top #( + parameter TCQ = 100, // SIMULATION tCQ delay. + + parameter SIMULATION = "FALSE", + parameter FAMILY = "VIRTEX7", // "VIRTEX6", "VIRTEX7" + parameter MEM_TYPE = "DDR3", + + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands: + // "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE" + // "R_W_INSTR_MODE", "RP_WP_INSTR_MODE + // "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE" + // ******************************* + // Virtex 6 Available commands: + // "R_W_INSTR_MODE" + // "FIXED_INSTR_R_MODE" - Only Read commands will be generated. + // "FIXED_INSTR_W_MODE" -- Only Write commands will be generated. + // "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated + // with lower 10 bits address in sequential increment. + // This mode is for Read Eye measurement. + + // parameter BL_WIDTH = 10, // Define User Interface Burst length width. + // // For a maximum 128 continuous back_to_back command, set this to 8. + parameter nCK_PER_CLK = 4, // Memory Clock ratio to fabric clock. + parameter NUM_DQ_PINS = 8, // Total number of memory dq pins in the design. + parameter MEM_BURST_LEN = 8, // MEMROY Burst Length + parameter MEM_COL_WIDTH = 10, // Memory component column width. + parameter DATA_WIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, // User Interface Data Width + parameter ADDR_WIDTH = 29, // Command Address Bus width + parameter MASK_SIZE = DATA_WIDTH/8, // + parameter DATA_MODE = 4'b0010, // Default Data mode is set to Address as Data pattern. + + // parameters define the address range + parameter BEGIN_ADDRESS = 32'h00000100, + parameter END_ADDRESS = 32'h000002ff, + parameter PRBS_EADDR_MASK_POS = 32'hfffffc00, + // debug parameters + parameter CMDS_GAP_DELAY = 6'd0, // CMDS_GAP_DELAY is used in memc_flow_vcontrol module to insert delay between + // each sucessive burst commands. The maximum delay is 32 clock cycles + // after the last command. + parameter SEL_VICTIM_LINE = NUM_DQ_PINS, // VICTIM LINE is one of the DQ pins is selected to be always asserted when + // DATA MODE is hammer pattern. No VICTIM_LINE will be selected if + // SEL_VICTIM_LINE = NUM_DQ_PINS. + parameter CMD_WDT = 'h3FF, + parameter WR_WDT = 'h1FFF, + parameter RD_WDT = 'hFF, + + parameter EYE_TEST = "FALSE", + // S6 Only parameters + parameter PORT_MODE = "BI_MODE", + parameter DATA_PATTERN = "DGEN_ALL", // Default is to generate all data pattern circuits. + parameter CMD_PATTERN = "CGEN_ALL" // Default is to generate all commands pattern circuits. + + ) + ( + input clk, + input rst, + input tg_only_rst, + input manual_clear_error, + input memc_init_done, + + input memc_cmd_full, + output memc_cmd_en, + output [2:0] memc_cmd_instr, + output [5:0] memc_cmd_bl, + output [31:0] memc_cmd_addr, + + output memc_wr_en, + output memc_wr_end, + + output [DATA_WIDTH/8 - 1:0] memc_wr_mask, + output [DATA_WIDTH - 1:0] memc_wr_data, + input memc_wr_full, + + output memc_rd_en, + input [DATA_WIDTH - 1:0] memc_rd_data, + input memc_rd_empty, + + // interface to qdr interface + output qdr_wr_cmd_o, + output qdr_rd_cmd_o, + + + // Signal declarations that can be connected to vio module + input vio_pause_traffic, // Pause traffic on the fly. + input vio_modify_enable, + input [3:0] vio_data_mode_value, + input [2:0] vio_addr_mode_value, + input [3:0] vio_instr_mode_value, + input [1:0] vio_bl_mode_value, + input [9:0] vio_fixed_bl_value, + input [2:0] vio_fixed_instr_value, // Allows upper level control write only or read only + // on the fly. + // Set the vio_instr_mode_value to "0001" . + // User has control of the type of commands to be generated + // after memory has been filled with selected data pattern. + // vio_fixed_instr_value = 3'b000: Write command + // vio_fixed_instr_value = 3'b001: Read command + input vio_data_mask_gen, // data_mask generation is only supported + // when data mode = address as data . + // + input [31:0] fixed_addr_i, + + // User Specific data pattern interface that used when vio_data_mode vale = 1.4.9. + input [31:0] fixed_data_i, + input [31:0] simple_data0, + input [31:0] simple_data1, + input [31:0] simple_data2, + input [31:0] simple_data3, + input [31:0] simple_data4, + input [31:0] simple_data5, + input [31:0] simple_data6, + input [31:0] simple_data7, + input wdt_en_i, + + // BRAM interface. + // bram bus formats: + // Only SP6 has been tested. + input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}} + input bram_valid_i, + output bram_rdy_o, // + + + // status feedback + output [DATA_WIDTH-1:0] cmp_data, + output cmp_data_valid, + output cmp_error, + output [47:0] wr_data_counts, + output [47:0] rd_data_counts, + output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, + output error, // asserted whenever the read back data is not correct. + output [64 + (2*DATA_WIDTH - 1):0] error_status, + output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error, + output reg cmd_wdt_err_o, + output reg wr_wdt_err_o, + output reg rd_wdt_err_o, + + output mem_pattern_init_done + + ); + + + + +//p0 wire declarations + wire tg_run_traffic; + wire tg_data_mask_gen; + wire run_traffic; + wire [31:0] tg_start_addr; + wire [31:0] tg_end_addr; + wire [31:0] tg_cmd_seed; + wire [31:0] tg_data_seed; + wire tg_load_seed; + wire [2:0] tg_addr_mode; + wire [3:0] tg_instr_mode; + wire [1:0] tg_bl_mode; + wire [3:0] tg_data_mode; + wire tg_mode_load; + wire [9:0] tg_fixed_bl; + wire [2:0] tg_fixed_instr; + wire tg_addr_order; + wire [5:0] cmds_gap_delay_value; + wire tg_memc_wr_en; + wire [63:0] mem_tg_tstpoints; + wire [9:0] lcl_v_fixed_bl_value; + + wire single_operation; + wire [3:0] tg_instr_mode_value; + wire [3:0] instr_mode_value; + reg tg_rst; + localparam ADDR_WIDTH_MASK = {{31-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH-1{1'b1}}}; + localparam ADDR_WIDTH_MASK_1 = {{30-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH{1'b1}}}; + localparam BEGIN_ADDRESS_MASK = ADDR_WIDTH_MASK & BEGIN_ADDRESS; + localparam END_ADDRESS_MASK = ADDR_WIDTH_MASK_1 & END_ADDRESS; + + localparam SHIFT_COUNT = (31-ADDR_WIDTH) ; + localparam BEGIN_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (BEGIN_ADDRESS >> SHIFT_COUNT) : BEGIN_ADDRESS_MASK ; + localparam END_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (END_ADDRESS >> SHIFT_COUNT) : END_ADDRESS_MASK ; + localparam TG_INIT_DATA_MODE = (DATA_PATTERN == "DGEN_ADDR") ? 4'b0010 : + (DATA_PATTERN == "DGEN_HAMMER") ? 4'b0011 : + (DATA_PATTERN == "DGEN_WALKING1") ? 4'b0101 : + (DATA_PATTERN == "DGEN_WALKING0") ? 4'b0110 : + (DATA_PATTERN == "DGEN_PRBS") ? 4'b0111 : + DATA_MODE ; + +assign single_operation = 1'b0; // Disable this for 13.3 release + + +// cmds_gap_delay_value is used in memc_flow_vcontrol module to insert delay between +// each sucessive burst commands. The maximum delay is 32 clock cycles after the last command. + function integer clogb2 (input integer size); + begin + size = size - 1; + for (clogb2=1; size>1; clogb2=clogb2+1) + size = size >> 1; + end + endfunction + + localparam CMD_WDT_WIDTH = clogb2(CMD_WDT); + localparam RD_WDT_WIDTH = clogb2(RD_WDT); + localparam WR_WDT_WIDTH = clogb2(WR_WDT); + +assign cmds_gap_delay_value = CMDS_GAP_DELAY; + +localparam TG_FAMILY = ((FAMILY == "VIRTEX6") || (FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") + || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ) ? "VIRTEX6" : "SPARTAN6"; + +assign tg_memc_wr_en = (TG_FAMILY == "VIRTEX6") ?memc_cmd_en & ~memc_cmd_full : memc_wr_en ; +assign lcl_v_fixed_bl_value = (vio_data_mode_value == 4) ? 32:vio_fixed_bl_value; +assign tg_run_traffic = (run_traffic & ((vio_modify_enable == 1'b1) ? ~vio_pause_traffic : 1'b1)) ; +assign tg_data_mask_gen = (vio_modify_enable == 1'b1) ? vio_data_mask_gen : 1'b0 ; +assign instr_mode_value = (vio_modify_enable == 1'b1) ? vio_instr_mode_value : 4'b0010; +assign tg_instr_mode_value = (single_operation == 1'b1) ? 4'b0111: instr_mode_value; + +reg [CMD_WDT_WIDTH-1 : 0] cmd_wdt; +reg [RD_WDT_WIDTH-1 : 0] rd_wdt; +reg [WR_WDT_WIDTH-1 : 0] wr_wdt; + +// The following 'generate' statement activates the traffic generator for + // init_mem_pattern_ctr module instantiation for Port-0 + mig_7series_v4_2_init_mem_pattern_ctr # + ( + .TCQ (TCQ), + .DWIDTH (DATA_WIDTH), + + .TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE), + .nCK_PER_CLK (nCK_PER_CLK), + .MEM_BURST_LEN (MEM_BURST_LEN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .MEM_TYPE (MEM_TYPE), + + .FAMILY (TG_FAMILY), + .BL_WIDTH (10), + .ADDR_WIDTH (ADDR_WIDTH), + .BEGIN_ADDRESS (BEGIN_ADDRESS_INT), + .END_ADDRESS (END_ADDRESS_INT), + .CMD_SEED_VALUE (32'h56456783), + .DATA_SEED_VALUE (32'h12345678), + .DATA_MODE (TG_INIT_DATA_MODE), + .PORT_MODE (PORT_MODE) + ) + u_init_mem_pattern_ctr + ( + .clk_i (clk), + .rst_i (tg_rst), + .memc_cmd_en_i (memc_cmd_en), + .memc_wr_en_i (tg_memc_wr_en), + .single_write_button (1'b0), // tie off these group of signals for 13.3 + .single_read_button (1'b0), + .slow_write_read_button (1'b0), + .single_operation (1'b0), + .vio_modify_enable (vio_modify_enable), + .vio_instr_mode_value (tg_instr_mode_value), + .vio_data_mode_value (vio_data_mode_value), + .vio_addr_mode_value (vio_addr_mode_value), + .vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode + .vio_fixed_bl_value (lcl_v_fixed_bl_value), // always set to 64 in order to run PRBS data pattern + .vio_data_mask_gen (vio_data_mask_gen), + .vio_fixed_instr_value (vio_fixed_instr_value), + .memc_init_done_i (memc_init_done), + .cmp_error (error), + .run_traffic_o (run_traffic), + .start_addr_o (tg_start_addr), + .end_addr_o (tg_end_addr), + .cmd_seed_o (tg_cmd_seed), + .data_seed_o (tg_data_seed), + .load_seed_o (tg_load_seed), + .addr_mode_o (tg_addr_mode), + .instr_mode_o (tg_instr_mode), + .bl_mode_o (tg_bl_mode), + .data_mode_o (tg_data_mode), + .mode_load_o (tg_mode_load), + .fixed_bl_o (tg_fixed_bl), + .fixed_instr_o (tg_fixed_instr), + .mem_pattern_init_done_o (mem_pattern_init_done) + ); + + // traffic generator instantiation for Port-0 + mig_7series_v4_2_memc_traffic_gen # + ( + .TCQ (TCQ), + .MEM_BURST_LEN (MEM_BURST_LEN), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .nCK_PER_CLK (nCK_PER_CLK), + + .PORT_MODE (PORT_MODE), + .DWIDTH (DATA_WIDTH), + .FAMILY (TG_FAMILY), + .MEM_TYPE (MEM_TYPE), + .SIMULATION (SIMULATION), + .DATA_PATTERN (DATA_PATTERN), + .CMD_PATTERN (CMD_PATTERN ), + .ADDR_WIDTH (ADDR_WIDTH), + .BL_WIDTH (10), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .PRBS_SADDR_MASK_POS (BEGIN_ADDRESS_INT), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), + .PRBS_SADDR (BEGIN_ADDRESS_INT), + .PRBS_EADDR (END_ADDRESS_INT), + .EYE_TEST (EYE_TEST) + ) + u_memc_traffic_gen + ( + .clk_i (clk), + .rst_i (tg_rst), + .run_traffic_i (tg_run_traffic), + .manual_clear_error (manual_clear_error), + .cmds_gap_delay_value (cmds_gap_delay_value), + .vio_instr_mode_value (tg_instr_mode_value), + .vio_percent_write ('b0), // bring this to top if want to specify percentage of write commands + // instr_mode_i has to be == 4 if want to use this command pattern + // runtime parameter + .mem_pattern_init_done_i (mem_pattern_init_done), + .single_operation (1'b0), + + .start_addr_i (tg_start_addr), + .end_addr_i (tg_end_addr), + .cmd_seed_i (tg_cmd_seed), + .data_seed_i (tg_data_seed), + .load_seed_i (tg_load_seed), + .addr_mode_i (tg_addr_mode), + .instr_mode_i (tg_instr_mode), + .bl_mode_i (tg_bl_mode), + .data_mode_i (tg_data_mode), + .mode_load_i (tg_mode_load), + .wr_data_mask_gen_i (tg_data_mask_gen), + // fixed pattern inputs interface + .fixed_bl_i (tg_fixed_bl), + .fixed_instr_i (tg_fixed_instr), + .fixed_addr_i (fixed_addr_i), + .fixed_data_i (fixed_data_i), + // BRAM interface. + .bram_cmd_i (bram_cmd_i), + // .bram_addr_i (bram_addr_i ), + // .bram_instr_i ( bram_instr_i), + .bram_valid_i (bram_valid_i), + .bram_rdy_o (bram_rdy_o), + + // MCB INTERFACE + .memc_cmd_en_o (memc_cmd_en), + .memc_cmd_instr_o (memc_cmd_instr), + .memc_cmd_bl_o (memc_cmd_bl), + .memc_cmd_addr_o (memc_cmd_addr), + .memc_cmd_full_i (memc_cmd_full), + + .memc_wr_en_o (memc_wr_en), + .memc_wr_data_end_o (memc_wr_end), + .memc_wr_mask_o (memc_wr_mask), + .memc_wr_data_o (memc_wr_data), + .memc_wr_full_i (memc_wr_full), + + .memc_rd_en_o (memc_rd_en), + .memc_rd_data_i (memc_rd_data), + .memc_rd_empty_i (memc_rd_empty), + + .qdr_wr_cmd_o (qdr_wr_cmd_o), + .qdr_rd_cmd_o (qdr_rd_cmd_o), + // status feedback + .counts_rst (tg_rst), + .wr_data_counts (wr_data_counts), + .rd_data_counts (rd_data_counts), + .error (error), // asserted whenever the read back data is not correct. + .error_status (error_status), // TBD how signals mapped + .cmp_data (cmp_data), + .cmp_data_valid (cmp_data_valid), + .cmp_error (cmp_error), + .mem_rd_data (), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .dq_error_bytelane_cmp (dq_error_bytelane_cmp), + .cumlative_dq_lane_error (cumlative_dq_lane_error), + .cumlative_dq_r0_bit_error (), + .cumlative_dq_f0_bit_error (), + .cumlative_dq_r1_bit_error (), + .cumlative_dq_f1_bit_error (), + .dq_r0_bit_error_r (), + .dq_f0_bit_error_r (), + .dq_r1_bit_error_r (), + .dq_f1_bit_error_r (), + .dq_r0_read_bit (), + .dq_f0_read_bit (), + .dq_r1_read_bit (), + .dq_f1_read_bit (), + .dq_r0_expect_bit (), + .dq_f0_expect_bit (), + .dq_r1_expect_bit (), + .dq_f1_expect_bit (), + .error_addr () + ); + + reg [8:0] wr_cmd_cnt; + reg [8:0] dat_cmd_cnt; + reg rst_remem; + reg [2:0] app_cmd1; + reg [2:0] app_cmd2; + reg [2:0] app_cmd3; + reg [2:0] app_cmd4; + + reg [8:0] rst_cntr; + + always @(posedge clk) begin + if (rst) begin + rst_remem <= 1'b0; + end else if (tg_only_rst) begin + rst_remem <= 1'b1; + end else if (rst_cntr == 9'h0) begin + rst_remem <= 1'b0; + end + end + + + always @(posedge clk) begin + if (rst) begin + tg_rst <= 1'b1; + end else begin + tg_rst <= (rst_cntr != 9'h1ff); + end + end + + always @ (posedge clk) + begin + if (rst) + rst_cntr <= 9'h1ff; + else if (rst_remem & (wr_cmd_cnt==dat_cmd_cnt) & (app_cmd3==3'h1) & (app_cmd4==3'h0)) + rst_cntr <= 9'h0; + else if (rst_cntr != 9'h1ff) + rst_cntr <= rst_cntr + 1'b1; + end + + always @(posedge clk) begin + if (rst | tg_rst) begin + wr_cmd_cnt <= 1'b0; + end else if (memc_cmd_en & (!memc_cmd_full)& (memc_cmd_instr == 3'h0)) begin + wr_cmd_cnt <= wr_cmd_cnt + 1'b1; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + dat_cmd_cnt <= 1'b0; + end else if (memc_wr_en & (!memc_wr_full)) begin + dat_cmd_cnt <= dat_cmd_cnt + 1'b1; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + app_cmd1 <= 'b0; + app_cmd2 <= 'b0; + app_cmd3 <= 'b0; + app_cmd4 <= 'b0; + end else if (memc_cmd_en & (!memc_cmd_full)) begin + app_cmd1 <= memc_cmd_instr; + app_cmd2 <= app_cmd1; + app_cmd3 <= app_cmd2; + app_cmd4 <= app_cmd3; + end + end + always @(posedge clk) begin + if (rst| tg_rst) begin + cmd_wdt <= 1'b0; + end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (memc_cmd_full | (!memc_cmd_en)) & wdt_en_i) begin + // init_calib_done !app_rdy app_en + cmd_wdt <= cmd_wdt + 1'b1; +// end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (!memc_cmd_full) & memc_cmd_en & wdt_en_w) begin + end else if ((!memc_cmd_full) & memc_cmd_en) begin + // init_calib_done !app_rdy app_en + cmd_wdt <= 'b0; + end + end + + + always @(posedge clk) begin + if (rst| tg_rst) begin + rd_wdt <= 1'b0; + end else if (mem_pattern_init_done & (rd_wdt != RD_WDT) & (memc_rd_empty) & wdt_en_i) begin + // !app_rd_data_valid + rd_wdt <= rd_wdt + 1'b1; + end else if (!memc_rd_empty) begin + // !app_rd_data_valid + rd_wdt <= 'b0; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + wr_wdt <= 1'b0; + end else if (mem_pattern_init_done & (wr_wdt != WR_WDT) & (!memc_wr_en) & wdt_en_i) begin + // app_wdf_wren + wr_wdt <= wr_wdt + 1'b1; + end else if (memc_wr_en) begin + // app_wdf_wren + wr_wdt <= 'b0; + end + end + + always @(posedge clk) begin + if (rst| tg_rst) begin + cmd_wdt_err_o <= 'b0; + rd_wdt_err_o <= 'b0; + wr_wdt_err_o <= 'b0; + end else begin + cmd_wdt_err_o <= cmd_wdt == CMD_WDT; + rd_wdt_err_o <= rd_wdt == RD_WDT; + wr_wdt_err_o <= wr_wdt == WR_WDT; + end + end + + +//synthesis translate_off +initial +begin +@ (posedge cmd_wdt_err_o); +$display ("ERROR: COMMAND Watch Dog Timer Expired"); +repeat (20) @ (posedge clk); +$finish; +end + +initial +begin +@ (posedge rd_wdt_err_o); +$display ("ERROR: READ Watch Dog Timer Expired"); +repeat (20) @ (posedge clk); +$finish; +end + +initial +begin +@ (posedge wr_wdt_err_o) +$display ("ERROR: WRITE Watch Dog Timer Expired"); +repeat (20) @ (posedge clk); +$finish; +end + +initial +begin +@ (posedge error) +repeat (20) @ (posedge clk); +$finish; +end +//synthesis translate_on + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v new file mode 100644 index 0000000..12cd0cb --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_vio_init_pattern_bram.v @@ -0,0 +1,397 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: tb_cmd_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:25 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Fuji +//Design Name: vio_init_pattern_bram +//Purpose: This moduel takes external defined data inputs as its bram init pattern. +// It allows users to change simple test data pattern withoug recompilation. +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif +module mig_7series_v4_2_vio_init_pattern_bram # + ( + parameter TCQ = 100, + parameter START_ADDR = 32'h00000000, + parameter MEM_BURST_LEN = 8, + parameter ADDR_WIDTH = 4, + parameter DEPTH = 16, + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = NUM_DQ_PINS // possible value : 0 to NUM_DQ_PINS + + ) + ( + input clk_i, + input rst_i, + input cmd_start, + input [31:0] cmd_addr, // + input mode_load_i, // signal to initialze internal bram + // with input data1 through data9. + input [3:0] data_mode_i, // selection of data pattern. + input [31:0] data0, // data1 through data8 are + input [31:0] data1, // used as simple traffic data + input [31:0] data2, // pattern that repeats continuously + input [31:0] data3, + input [31:0] data4, + input [31:0] data5, + input [31:0] data6, + input [31:0] data7, + input [31:0] data8, // used a fixed input data + + output reg bram_rd_valid_o, + input bram_rd_rdy_i, + output [31:0] dout_o + ); + + function integer logb2; + input [31:0] number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end + endfunction + + reg [ADDR_WIDTH - 1:0] wr_addr /* synthesis syn_maxfan = 8 */; + reg [ADDR_WIDTH - 1:0] rd_addr /* synthesis syn_maxfan = 8 */; + reg init_write; + reg mode_load_r1; + reg mode_load_r2; + reg [31:0] data_in0; + reg [31:0] data_in1; + reg [31:0] data_in2; + reg [31:0] data_in3; + reg [31:0] data_in4; + reg [31:0] data_in5; + reg [31:0] data_in6; + reg [31:0] data_in7; + reg [31:0] data_in8; + reg [31:0] data_in9; + reg [31:0] data_in10; + reg [31:0] data_in11; + reg [31:0] data_in12; + reg [31:0] data_in13; + reg [31:0] data_in14; + reg [31:0] data_in15; + reg [31:0] hdata; + reg [7:0] mem_0 [0:DEPTH - 1]; + reg [7:0] mem_1 [0:DEPTH - 1]; + reg [7:0] mem_2 [0:DEPTH - 1]; + reg [7:0] mem_3 [0:DEPTH - 1]; + reg [31:0] data_in; + reg wr_en; + reg cmd_addr_r9; + integer i,j,k; + + always @ (posedge clk_i) + begin + mode_load_r1 <= mode_load_i; + mode_load_r2 <= mode_load_r1; + end + + always @ (posedge clk_i) + begin + if (rst_i) + init_write <= 'b0; + else if (wr_addr == {4'b0111}) + init_write <= 'b1; + else if (mode_load_r1 && ~mode_load_r2 && data_mode_i != 4'b0010) + init_write <= 'b1; + end + +// generate a mutil_cycle control siganl to improve timing. + always @ (posedge clk_i) + begin + if (rst_i) + wr_en <= 1'b1; + else if (init_write && data_mode_i != 4'b0010) + wr_en <= 1'b1; + end + + always @ (posedge clk_i) + begin + if (rst_i) + wr_addr <= 'b0; + else if (data_mode_i == 4'h1) + wr_addr <= 4'b1000; + else if (data_mode_i == 4'b0011) + wr_addr <= 4'b1001; + else if (~init_write && data_mode_i == 4'b0100) + wr_addr <= 4'b0000; + else if (init_write && wr_en && data_mode_i != 4'b0010 && wr_addr != 15) + wr_addr <= wr_addr + 1'b1; + end + +// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. +// The incoming addr_i[5:2] determine the position of the pin driving oppsite polarity +// addr_i[6:2] = 5'h0f ; 32 bit data port +// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111 +// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 + +// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level. + always @ (posedge clk_i) + begin + for (i= 0; i <= 31; i= i+1) //begin: hammer_data + if (i >= NUM_DQ_PINS) begin + if (SEL_VICTIM_LINE == NUM_DQ_PINS) + hdata[i] <= 1'b0; + else if ( + ((i == SEL_VICTIM_LINE-1) || (i-NUM_DQ_PINS) == SEL_VICTIM_LINE || + (i-(NUM_DQ_PINS*2)) == SEL_VICTIM_LINE || + (i-(NUM_DQ_PINS*3)) == SEL_VICTIM_LINE)) + hdata[i] <= 1'b1; + else + hdata[i] <= 1'b0; + end + else + hdata[i] <= 1'b1; + end + +// content formats +// {burst length, instruction, address} + initial begin + mem_0[0] = {2'b00,6'h00}; + mem_1[0] = 8'h0; + mem_2[0] = 8'h0; + mem_3[0] = 8'h0; + mem_0[1] = {2'b00,6'h04}; + mem_1[1] = 8'h0; + mem_2[1] = 8'h0; + mem_3[1] = 8'h0; + mem_0[2] = {2'b00,6'h08}; + mem_1[2] = 8'h0; + mem_2[2] = 8'h0; + mem_3[2] = 8'h0; + mem_0[3] = {2'b00,6'h0c}; + mem_1[3] = 8'h0; + mem_2[3] = 8'h0; + mem_3[3] = 8'h0; + mem_0[4] = {2'b00,6'h10}; + mem_1[4] = 8'h0; + mem_2[4] = 8'h0; + mem_3[4] = 8'h0; + mem_0[5] = {2'b00,6'h14}; + mem_1[5] = 8'h0; + mem_2[5] = 8'h0; + mem_3[5] = 8'h0; + mem_0[6] = {2'b00,6'h18}; + mem_1[6] = 8'h0; + mem_2[6] = 8'h0; + mem_3[6] = 8'h0; + mem_0[7] = {2'b00,6'h1c}; + mem_1[7] = 8'h0; + mem_2[7] = 8'h0; + mem_3[7] = 8'h0; + mem_0[8] = {2'b00,6'h20}; + mem_1[8] = 8'h0; + mem_2[8] = 8'h0; + mem_3[8] = 8'h0; + mem_0[9] = {2'b00,6'h24}; + mem_1[9] = 8'h0; + mem_2[9] = 8'h0; + mem_3[9] = 8'h0; + mem_0[10] = 8'hff; + mem_1[10] = 8'hff; + mem_2[10] = 8'hff; + mem_3[10] = 8'hff; + mem_0[11] = 8'h0; + mem_1[11] = 8'h0; + mem_2[11] = 8'h0; + mem_3[11] = 8'h0; + mem_0[12] = {2'b00,6'h30}; + mem_1[12] = 8'h0; + mem_2[12] = 8'h0; + mem_3[12] = 8'h0; + mem_0[13] = {2'b00,6'h34}; + mem_1[13] = 8'h0; + mem_2[13] = 8'h0; + mem_3[13] = 8'h0; + mem_0[14] = {2'b00,6'h38}; + mem_1[14] = 8'h0; + mem_2[14] = 8'h0; + mem_3[14] = 8'h0; + mem_0[15] = {2'b00,6'h3c}; + mem_1[15] = 8'h0; + mem_2[15] = 8'h0; + mem_3[15] = 8'h0; + end + +// address is one cycle earlier. + always @ (posedge clk_i) + begin + if (rst_i) + data_in <= #TCQ data0; + else begin + case(wr_addr) + 0: if (init_write) + data_in <= #TCQ data_in1; + else + data_in <= #TCQ data_in0; + 1: data_in <= #TCQ data_in2; + 2: data_in <= #TCQ data_in3; + 3: data_in <= #TCQ data_in4; + 4: data_in <= #TCQ data_in5; + 5: data_in <= #TCQ data_in6; + 6: data_in <= #TCQ data_in7; + 7: data_in <= #TCQ data_in7; + 8: data_in <= #TCQ data_in8; + 9: data_in <= #TCQ data_in9; + 10: data_in <= #TCQ data_in10; + 11: data_in <= #TCQ data_in11; + 12: data_in <= #TCQ data_in12; + 13: data_in <= #TCQ data_in13; + 14: data_in <= #TCQ data_in14; + 15: data_in <= #TCQ data_in15; + default: data_in <= data8; + endcase + end + end + + always @(posedge clk_i) begin + mem_0[wr_addr] <= data_in[7:0]; + mem_1[wr_addr] <= data_in[15:8]; + mem_2[wr_addr] <= data_in[23:16]; + mem_3[wr_addr] <= data_in[31:24]; + end + + always @ (data_mode_i, data0,data1,data2,data3,data4,data5,data6,data7,data8,hdata) + begin + data_in0[31:0] = #TCQ data0; + data_in1[31:0] = #TCQ data1; + data_in2[31:0] = #TCQ data2; + data_in3[31:0] = #TCQ data3; + data_in4[31:0] = #TCQ data4; + data_in5[31:0] = #TCQ data5; + data_in6[31:0] = #TCQ data6; + data_in7[31:0] = #TCQ data7; + data_in8[31:0] = #TCQ data8; + data_in9[31:0] = #TCQ hdata; + data_in10[31:0] = #TCQ 32'hffffffff; + data_in11[31:0] = #TCQ 32'h00000000; + data_in12[31:0] = #TCQ 'b0; + data_in13[31:0] = #TCQ 'b0; + data_in14[31:0] = #TCQ 'b0; + data_in15[31:0] = #TCQ 'b0; + end + + always @ (posedge clk_i) + begin + if (cmd_start) + cmd_addr_r9 <= cmd_addr[9]; + end + + always @ (posedge clk_i) + if (rst_i) + bram_rd_valid_o <= 1'b0; + else if (wr_addr[3:0] == {ADDR_WIDTH - 1{1'b1}} || data_mode_i == 2 || data_mode_i == 3) + bram_rd_valid_o <= 1'b1; + +// rd_address generation depending on data pattern mode. + always @ (posedge clk_i) + begin + if (rst_i) begin + if (data_mode_i == 9) begin + rd_addr[3:1] <= #TCQ 3'b101; + rd_addr[0] <= #TCQ cmd_addr[9]; + end + else if (data_mode_i == 1) + rd_addr[3:0] <= #TCQ 8; + else if (data_mode_i == 3) // address as data pattern + rd_addr <= #TCQ 9; + else + rd_addr <= #TCQ 0; + end + else if (cmd_start) begin + if (data_mode_i == 3) + rd_addr[3:0] <= #TCQ 9; + else if (data_mode_i == 1) + rd_addr[3:0] <= #TCQ 8; + else if (data_mode_i == 9) begin + rd_addr[3:1] <= #TCQ 3'b101; + rd_addr[0] <= #TCQ cmd_addr[9]; + end + else + rd_addr[3:0] <= #TCQ 0; + end + else if (bram_rd_rdy_i) begin + case (data_mode_i) + 4'h2: rd_addr <= #TCQ 0; + 4'h4: if (rd_addr == 7) + rd_addr <= #TCQ 0; + else + rd_addr <= #TCQ rd_addr+ 1'b1; + 4'h1: rd_addr <= #TCQ 8; + 4'h3: rd_addr <= #TCQ 9; + 4'h9: begin + rd_addr[3:1] <= #TCQ 3'b101; + rd_addr[0] <= #TCQ cmd_addr_r9; + end + default: rd_addr <= #TCQ 0; + endcase + end + end + +// need to infer distributed RAM to meet output timing +// in upper level +assign dout_o = {mem_3[rd_addr],mem_2[rd_addr],mem_1[rd_addr],mem_0[rd_addr]}; // + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_wr_data_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_wr_data_gen.v new file mode 100644 index 0000000..dd5e408 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_wr_data_gen.v @@ -0,0 +1,433 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: wr_data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: +//Reference: +//Revision History: 5/2/2012 Fixed data_wr_end_r logic which didn't hold its state when data_rdy_i was deasserted and +// data_valid was asserted. +// +//***************************************************************************** + +`timescale 1ps/1ps + +module mig_7series_v4_2_wr_data_gen # + +( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6" + parameter MEM_BURST_LEN = 8, + parameter START_ADDR = 32'h00000000, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + parameter MEM_TYPE = "DDR3", + + parameter MODE = "WR", //"WR", "RD" + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter COLUMN_WIDTH = 10, + parameter EYE_TEST = "FALSE" + + ) + ( + input clk_i, // + input [4:0] rst_i, + input [31:0] prbs_fseed_i, + input mode_load_i, + + input [3:0] data_mode_i, // "00" = bram; + input mem_init_done_i, + input wr_data_mask_gen_i, + + output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. + // And then it should reasserted when + // it is generating the last_word. + input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. + input cmd_validB_i, + input cmd_validC_i, + + output last_word_o, + + // input [5:0] port_data_counts_i,// connect to data port fifo counts + // input [ADDR_WIDTH-1:0] m_addr_i, + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [31:0] fixed_data_i, + + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data + input memc_cmd_full_i, + + input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen + // connect from mcb_rd_empty when used as rd_data_gen + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output data_valid_o, // connect to wr_en or rd_en and is asserted whenever the + // pattern is available. + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, // generated data pattern + output data_wr_end_o, + output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o + + + +); +// + + +reg [DWIDTH-1:0] data; + + + +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF; +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF; + + + + +reg burst_count_reached2; + +reg data_valid; +reg [BL_WIDTH:0]user_burst_cnt; +reg [2:0] walk_cnt; +wire fifo_not_full; +integer i,j; +reg [31:0] w3data; +reg data_wr_end_r; +wire data_wr_end; +wire bram_rd_valid_o; + +function integer logb2; + input [31:0] number; + integer i; + begin + i = number; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end +endfunction + + +assign fifo_not_full = data_rdy_i; + + +// data_wr_end_r is used in nCK_PER_CLK == 2; when nCK_PER_CLK = 4, data_wr_end_o == data_valid_o; + +always @(posedge clk_i) +begin + if (~user_burst_cnt[0] && data_valid && data_rdy_i && MEM_BURST_LEN == 8) + data_wr_end_r <= #TCQ 1'b1; + else if (data_rdy_i) // keep the data_wr_end_r asserted if data_rdy_i is deasserted because of mc's write + // data fifo full. + data_wr_end_r <= #TCQ 1'b0; +end + +//assign data_wr_end_o = data_wr_end_r && fifo_not_full; */ +assign data_wr_end_o = (nCK_PER_CLK == 4 || nCK_PER_CLK == 2 && MEM_BURST_LEN == 4) ? data_valid_o :data_wr_end_r ;//(MEM_BURST_LEN == 8) ? user_burst_cnt[0] & data_valid_o : + +assign data_valid_o = data_valid ;//& ~memc_cmd_full_i;// (nCK_PER_CLK == 4)?data_valid_r: data_valid ;//& fifo_not_full; + +//assign data_wr_end_o = data_wr_end_r; + + +always @ (posedge clk_i) +begin +cmd_start <= #TCQ cmd_validC_i & cmd_rdyC ; +cmd_startB <= #TCQ cmd_valid_i & cmd_rdyB; +cmd_startC <= #TCQ cmd_validB_i & cmd_rdyC; +cmd_startD <= #TCQ cmd_validB_i & cmd_rdyD; +cmd_startE <= #TCQ cmd_validB_i & cmd_rdyE; +cmd_startF <= #TCQ cmd_validB_i & cmd_rdyF; +end + + +// counter to count user burst length +// verilint STARC-2.2.3.3 off +always @( posedge clk_i) +begin + if ( rst_i[0] ) + user_burst_cnt <= #TCQ 'd0; + else if(cmd_start) + // if (FAMILY == "SPARTAN6") begin + // SPATAN6 has maximum of burst length of 64. + if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000) + // user_burst_cnt <= #TCQ 7'b1000000; + begin + user_burst_cnt[6:0] <= #TCQ 7'd64; + user_burst_cnt[BL_WIDTH:7] <= 'b0; + end + else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}}) + user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}}; + + else + user_burst_cnt <= #TCQ {1'b0,bl_i}; + + // else + // user_burst_cnt <= #TCQ bl_i; +// else if(fifo_not_full && data_valid && ~memc_cmd_full_i) +// verilint STARC-2.2.3.3 on + else if(fifo_not_full && data_valid ) + + if (user_burst_cnt != 6'd0) + user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; + else + user_burst_cnt <=#TCQ 'd0; + +end + +reg u_bcount_2; +wire last_word_t; +always @ (posedge clk_i) +begin +if ((user_burst_cnt == 2 && fifo_not_full )|| (cmd_startC && bl_i == 1)) + u_bcount_2 <= #TCQ 1'b1; +else if (last_word_o) + u_bcount_2 <= #TCQ 1'b0; +end + + +assign last_word_o = u_bcount_2 & fifo_not_full; + +// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i +// is assert and reassert during the last data + +assign cmd_rdy_o = cmd_rdy & fifo_not_full; + + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdy <= #TCQ 1'b1; // the state should be '0' for bram_interface during reset. + else if (bram_rd_valid_o) // need work here. + cmd_rdy <= #TCQ 1'b1; + + else if (cmd_start) + if (bl_i == 1) + cmd_rdy <= #TCQ 1'b1; + else + cmd_rdy <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + cmd_rdy <= #TCQ bram_rd_valid_o;//1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i [0]) + cmd_rdyB <= #TCQ 1'b1; + else if (cmd_startB) + if (bl_i == 1) + cmd_rdyB <= #TCQ 1'b1; + else + cmd_rdyB <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyB <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyC <= #TCQ 1'b1; + else if (cmd_startC) + if (bl_i == 1) + cmd_rdyC <= #TCQ 1'b1; + else + cmd_rdyC <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyC <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyD <= #TCQ 1'b1; + else if (cmd_startD) + if (bl_i == 1) + cmd_rdyD <= #TCQ 1'b1; + else + cmd_rdyD <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyD <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyE <= #TCQ 1'b1; + else if (cmd_startE) + if (bl_i == 1) + cmd_rdyE <= #TCQ 1'b1; + else + cmd_rdyE <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyE <= #TCQ 1'b1; + + +end + + + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyF <= #TCQ 1'b1; + else if (cmd_startF) + if (bl_i == 1) + cmd_rdyF <= #TCQ 1'b1; + else + cmd_rdyF <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + cmd_rdyF <= #TCQ 1'b1; + + +end + + +reg dvalid; + +always @ (posedge clk_i) +begin + if (rst_i[1]) + data_valid <= #TCQ 'd0; + else if(cmd_start) + data_valid <= #TCQ 1'b1; + else if (fifo_not_full && user_burst_cnt <= 6'd1) + data_valid <= #TCQ 1'b0; + + // data_valid <= dvalid ; +end + +mig_7series_v4_2_s7ven_data_gen # + ( + .TCQ (TCQ), + .ADDR_WIDTH (32 ), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + .BL_WIDTH (BL_WIDTH), + .DWIDTH (DWIDTH), + .MEM_BURST_LEN (MEM_BURST_LEN), + .nCK_PER_CLK (nCK_PER_CLK), + .START_ADDR (START_ADDR), + .DATA_PATTERN (DATA_PATTERN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .COLUMN_WIDTH (COLUMN_WIDTH), + .EYE_TEST (EYE_TEST) + ) + s7ven_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .prbs_fseed_i (prbs_fseed_i), + .mem_init_done_i (mem_init_done_i), + .mode_load_i (mode_load_i), + .wr_data_mask_gen_i (wr_data_mask_gen_i), + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_startB ), + .cmd_startC (cmd_startC ), + .cmd_startD (cmd_startD ), + .cmd_startE (cmd_startE ), + .m_addr_i (addr_i ), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (fifo_not_full ), + .data_o (data_o ), + .data_mask_o (data_mask_o), + .bram_rd_valid_o (bram_rd_valid_o), + .tg_st_addr_o () + ); + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_write_data_path.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_write_data_path.v new file mode 100644 index 0000000..97a1d28 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/ddr_ctrl/traffic_gen/mig_7series_v4_2_write_data_path.v @@ -0,0 +1,193 @@ +//***************************************************************************** +// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: write_data_path.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This is top level of write path . + +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + + +module mig_7series_v4_2_write_data_path #( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter MEM_TYPE = "DDR3", + + parameter ADDR_WIDTH = 32, + parameter START_ADDR = 32'h00000000, + parameter BL_WIDTH = 6, + parameter nCK_PER_CLK = 4, // DRAM clock : MC clock + parameter MEM_BURST_LEN = 8, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter MEM_COL_WIDTH = 10, + parameter EYE_TEST = "FALSE" + + ) + ( + + input clk_i, + input [9:0] rst_i, + output cmd_rdy_o, + input cmd_valid_i, + input cmd_validB_i, + input cmd_validC_i, + input [31:0] prbs_fseed_i, + input [3:0] data_mode_i, + input mem_init_done_i, + input wr_data_mask_gen_i, + // input [31:0] m_addr_i, + + input [31:0] simple_data0 , + input [31:0] simple_data1 , + input [31:0] simple_data2 , + input [31:0] simple_data3 , + input [31:0] simple_data4 , + input [31:0] simple_data5 , + input [31:0] simple_data6 , + input [31:0] simple_data7 , + + input [31:0] fixed_data_i, + input mode_load_i, + + input [31:0] addr_i, + input [BL_WIDTH-1:0] bl_i, + +// input [5:0] port_data_counts_i,// connect to data port fifo counts + input memc_cmd_full_i, + input data_rdy_i, + output data_valid_o, + output last_word_wr_o, + output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, + output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o, + output data_wr_end_o + + ); + +wire data_valid; +reg cmd_rdy; + + assign data_valid_o = data_valid;// & data_rdy_i; + + + mig_7series_v4_2_wr_data_gen # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .MEM_TYPE (MEM_TYPE), + .NUM_DQ_PINS (NUM_DQ_PINS), + .MEM_BURST_LEN (MEM_BURST_LEN), + .BL_WIDTH (BL_WIDTH), + .START_ADDR (START_ADDR), + .nCK_PER_CLK (nCK_PER_CLK), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .COLUMN_WIDTH (MEM_COL_WIDTH), + .EYE_TEST (EYE_TEST) + + ) + wr_data_gen( + .clk_i (clk_i ), + .rst_i (rst_i[9:5]), + .prbs_fseed_i (prbs_fseed_i), + .wr_data_mask_gen_i (wr_data_mask_gen_i), + .mem_init_done_i (mem_init_done_i), + .data_mode_i (data_mode_i ), + .cmd_rdy_o (cmd_rdy_o ), + .cmd_valid_i (cmd_valid_i ), + .cmd_validB_i (cmd_validB_i ), + .cmd_validC_i (cmd_validC_i ), + + .last_word_o (last_word_wr_o ), + // .port_data_counts_i (port_data_counts_i), + // .m_addr_i (m_addr_i ), + .fixed_data_i (fixed_data_i), + .simple_data0 (simple_data0), + .simple_data1 (simple_data1), + .simple_data2 (simple_data2), + .simple_data3 (simple_data3), + .simple_data4 (simple_data4), + .simple_data5 (simple_data5), + .simple_data6 (simple_data6), + .simple_data7 (simple_data7), + + + .mode_load_i (mode_load_i), + + .addr_i (addr_i ), + .bl_i (bl_i ), + .memc_cmd_full_i (memc_cmd_full_i), + + .data_rdy_i (data_rdy_i ), + .data_valid_o ( data_valid ), + .data_o (data_o ), + .data_wr_end_o (data_wr_end_o), + .data_mask_o (data_mask_o) + ); + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/io_test/io_test.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/io_test/io_test.v new file mode 100644 index 0000000..fe1cfa2 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/io_test/io_test.v @@ -0,0 +1,28 @@ + +module io_test + ( + //-- + input rst_n, + input clk, + output reg io_sig + ); +reg[27:0]cnt; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + cnt <= 28'd0; + else if(cnt == 28'd50000000) //--50Mhz 1s ÖÓÑ­»·¼ÆÊý + cnt <= 28'b0; + else + cnt <= cnt + 1'b1; +end +reg io_test_r; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + io_test_r <= 1'b0; + else if(cnt == 28'd50000000) + io_test_r <= ~io_test_r; +end +always @ (posedge clk )begin + io_sig <= io_test_r; +end +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/led_ctrl/led_ctrl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/led_ctrl/led_ctrl.v new file mode 100644 index 0000000..174d39a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/led_ctrl/led_ctrl.v @@ -0,0 +1,59 @@ + +module led_ctrl + ( + //-- + input rst_n , + input clk , + //*********************************************************** + //DDR Test + //*********************************************************** + input init_calib_complete , + input tg_compare_error , + output reg[ 1:0] led + ); +//******************************************************************* +//-- +//******************************************************************* +reg[27:0] cnt ; +reg led_r ; +//******************************************************************* +//--1S Time +//******************************************************************* +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + cnt <= 28'd0; + else if(cnt == 28'd50000000) //--50Mhz 1s 钟循环计数 + cnt <= 28'b0; + else + cnt <= cnt + 1'b1; +end +//******************************************************************* +//--1s 钟循环控制 +//******************************************************************* +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + led_r <= 1'b0; + else if(cnt == 28'd50000000) + led_r <= ~led_r; +end +//******************************************************************* +//--LED0 +//******************************************************************* +always @ (*)begin + led[0] = led_r; +end +//******************************************************************* +//--LED1 +//******************************************************************* +always @ (*)begin + if(init_calib_complete==1'b1)begin + if(tg_compare_error==1'b0) + led[1] = ~led_r;//åˆå§‹åŒ–æˆåŠŸ 自检正确 + else + led[1] = 1'b1; //åˆå§‹åŒ–æˆåŠŸ 自检错误 + end + else + led[1] = 1'b0; //åˆå§‹åŒ–错误 +end +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/rst_ctrl/rst_ctrl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/rst_ctrl/rst_ctrl.v new file mode 100644 index 0000000..94c7a64 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/rst_ctrl/rst_ctrl.v @@ -0,0 +1,65 @@ + + +module rst_ctrl + ( + input sys_clk , + input sys_rst_n , + //*********************************************************** + //Clock Locked + //*********************************************************** + input [1:0] clk_locked , + //*********************************************************** + //Reset Out + //*********************************************************** + output rst_n + ); +//******************************************************************* +//-- +//******************************************************************* +reg [27:0] rst_cnt ; +reg rst_n_r ; +reg rst_n_temp ; + +//******************************************************************* +//--Clock Locked Gen 1.0S Reset +//******************************************************************* +always @ (posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n) + rst_cnt <= 28'd0; + else if(clk_locked==2'b11)begin + if(rst_cnt<=28'd50000000) + rst_cnt <= rst_cnt + 1'b1; + else + rst_cnt <= rst_cnt; + end + else + rst_cnt <= 28'd0; +end + +//******************************************************************* +//--1.0S Time +//******************************************************************* +always @ (posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n) + rst_n_r <= 1'b0; + else if(rst_cnt<=28'd50000000) + rst_n_r <= 1'b0; + else + rst_n_r <= 1'b1; +end +always @ (posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n) + rst_n_temp <= 1'b0; + else + rst_n_temp <= rst_n_r; +end + +BUFGCE BUFGCE_inst ( + .O (rst_n ), // 1-bit output: Clock output + .CE (1'b1 ), // 1-bit input: Clock enable input for I0 + .I (rst_n_temp ) // 1-bit input: Primary clock + ); + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/top.v new file mode 100644 index 0000000..44d2177 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/top.v @@ -0,0 +1,200 @@ + + +module top + ( + //*********************************************************** + //--Clock + //*********************************************************** + input sys_clk , + //*********************************************************** + //--DDR3 Interface + //*********************************************************** + // Inouts + inout [15:0] ddr3_dq , + inout [1:0] ddr3_dqs_n , + inout [1:0] ddr3_dqs_p , + // Outputs + output [14:0] ddr3_addr , + output [2:0] ddr3_ba , + output ddr3_ras_n , + output ddr3_cas_n , + output ddr3_we_n , + output ddr3_reset_n , + output [0:0] ddr3_ck_p , + output [0:0] ddr3_ck_n , + output [0:0] ddr3_cke , + output [1:0] ddr3_dm , + output [0:0] ddr3_odt , + //*********************************************************** + //--KEY + //*********************************************************** + input key , // Low Active + //*********************************************************** + //--LED + //*********************************************************** + output [1:0] led , + //*********************************************************** + //--UART + //*********************************************************** + input rxd , + output txd , + //*********************************************************** + //--IO + //*********************************************************** + output [IO_NUM-1:0] o_sig + ); + +//******************************************************************* +//-- +//******************************************************************* +parameter IO_NUM = 161 ; + +assign sys_rst_n = 1'b1 ; + +//******************************************************************* +//-- +//******************************************************************* +wire clk_200M ; +wire clk_50M ; +wire ddr3_clk ; +(* MARK_DEBUG="true" *) +wire [1:0] clk_locked ; +wire rst_n ; +//******************************************************************* +//--DDR3 +//******************************************************************* +(* MARK_DEBUG="true" *) +wire init_calib_complete ; +(* MARK_DEBUG="true" *) +wire tg_compare_error ; +(* MARK_DEBUG="true" *) +wire [47:0] tg_wr_data_counts ; +(* MARK_DEBUG="true" *) +wire [47:0] tg_rd_data_counts ; +wire [11:0] device_temp ; +//*********************************************************** +//--Clock Ctrl +//*********************************************************** +clk_ctrl UU1 ( + .clk (sys_clk ), + .rst_n (sys_rst_n ), + //******************************************************* + //-- + //******************************************************* + .clk_200M (clk_200M ), + .clk_50M (clk_50M ), + .ddr3_clk (ddr3_clk ), + //******************************************************* + //Clock Locked + //******************************************************* + .clk_locked (clk_locked ) + ); + +//*********************************************************** +//--Reset Ctrl +//*********************************************************** +rst_ctrl UU2 ( + .sys_clk (clk_50M ), + .sys_rst_n (sys_rst_n ), + .clk_locked (clk_locked ), + //******************************************************* + //-- + //******************************************************* + .rst_n (rst_n ) + ); + +//*********************************************************** +//DDR3 +//*********************************************************** +example_top UU3 + ( + .ddr3_dq (ddr3_dq ), + .ddr3_dqs_n (ddr3_dqs_n ), + .ddr3_dqs_p (ddr3_dqs_p ), + .ddr3_addr (ddr3_addr ), + .ddr3_ba (ddr3_ba ), + .ddr3_ras_n (ddr3_ras_n ), + .ddr3_cas_n (ddr3_cas_n ), + .ddr3_we_n (ddr3_we_n ), + .ddr3_reset_n (ddr3_reset_n ), + .ddr3_ck_p (ddr3_ck_p ), + .ddr3_ck_n (ddr3_ck_n ), + .ddr3_cke (ddr3_cke ), + .ddr3_dm (ddr3_dm ), + .ddr3_odt (ddr3_odt ), + .sys_clk_i (ddr3_clk ), + .clk_ref_i (clk_200M ), + .init_calib_complete (init_calib_complete ), + .tg_compare_error (tg_compare_error ), + .tg_wr_data_counts (tg_wr_data_counts ), + .tg_rd_data_counts (tg_rd_data_counts ), + .device_temp_i (device_temp ), + .sys_rst (rst_n ) + ); +//*********************************************************** +//--LED +//*********************************************************** +led_ctrl UU4( + .rst_n (rst_n ), + .clk (clk_50M ), + //******************************************************* + //DDR Test + //******************************************************* + .init_calib_complete (init_calib_complete ), + .tg_compare_error (tg_compare_error ), + .led (led ) + ); +//******************************************************************* +//XADC +//******************************************************************* +xadc_temp UU5 +( + .clk (clk_50M ), + .xadc_clk (clk_200M ), + .rst (~rst_n ), + .device_temp (device_temp ) +); +//*********************************************************** +//--UART +//*********************************************************** +uart_top UU6 ( + .rst_n (rst_n ), + .clk (clk_50M ), + //******************************************************* + //DDR Test + //******************************************************* + .init_calib_complete (init_calib_complete ), + .tg_compare_error (tg_compare_error ), + .w_code_rate (tg_wr_data_counts ), + .r_code_rate (tg_rd_data_counts ), + //******************************************************* + //--Temp + //******************************************************* + .device_temp (device_temp ), + //******************************************************* + //LED Test + //******************************************************* + .led (led ), + //******************************************************* + //--KEY + //******************************************************* + .key (key ), + //******************************************************* + //--UART + //******************************************************* + .uart_rxd (rxd ), + .uart_txd (txd ) + ); +//*********************************************************** +//--IO Test +//*********************************************************** +io_test UU7( + .rst_n (rst_n ), + .clk (clk_50M ), + .io_sig (io_sig ) + ); +assign o_sig = {IO_NUM{io_sig}}; + +endmodule + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/ascii_code.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/ascii_code.v new file mode 100644 index 0000000..2a67720 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/ascii_code.v @@ -0,0 +1,50 @@ +`timescale 1ns / 1ps + +module ascii_code + # + ( + parameter DATA_IN_WIDTH = 48, + parameter DATA_OUT_WIDTH = DATA_IN_WIDTH*2, + parameter NUM = DATA_IN_WIDTH/4 + ) + ( + //-- + input rst_n , + input clk , + //*********************************************************** + //--UART Interface + //*********************************************************** + input d_in_en , + input [DATA_IN_WIDTH-1 :0] d_in , + output reg[DATA_OUT_WIDTH-1:0] d_out + ); +genvar i; + generate + for (i=0; i < NUM; i=i+1) + begin: REG + always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + d_out[(i+1)*8-1:i*8] <= 8'b0; + else if(d_in_en==1'b1)case(d_in[(i+1)*4-1:i*4]) + 4'h0 : d_out[(i+1)*8-1:i*8] <= 8'h30; + 4'h1 : d_out[(i+1)*8-1:i*8] <= 8'h31; + 4'h2 : d_out[(i+1)*8-1:i*8] <= 8'h32; + 4'h3 : d_out[(i+1)*8-1:i*8] <= 8'h33; + 4'h4 : d_out[(i+1)*8-1:i*8] <= 8'h34; + 4'h5 : d_out[(i+1)*8-1:i*8] <= 8'h35; + 4'h6 : d_out[(i+1)*8-1:i*8] <= 8'h36; + 4'h7 : d_out[(i+1)*8-1:i*8] <= 8'h37; + 4'h8 : d_out[(i+1)*8-1:i*8] <= 8'h38; + 4'h9 : d_out[(i+1)*8-1:i*8] <= 8'h39; + 4'hA : d_out[(i+1)*8-1:i*8] <= 8'h41; + 4'hB : d_out[(i+1)*8-1:i*8] <= 8'h42; + 4'hC : d_out[(i+1)*8-1:i*8] <= 8'h43; + 4'hD : d_out[(i+1)*8-1:i*8] <= 8'h44; + 4'hE : d_out[(i+1)*8-1:i*8] <= 8'h45; + 4'hF : d_out[(i+1)*8-1:i*8] <= 8'h46; + default : d_out[(i+1)*8-1:i*8] <= 8'h20; + endcase + end + end + endgenerate +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/device_temp_ascii_dis.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/device_temp_ascii_dis.v new file mode 100644 index 0000000..cd72fdd --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/device_temp_ascii_dis.v @@ -0,0 +1,179 @@ +`timescale 1ns / 1ps + +module device_temp_ascii_dis + ( + //-- + input rst_n , + input clk , + //*********************************************************** + //-- Interface + //*********************************************************** + input d_in_en , + input [7 :0] d_in , + output reg[23:0] d_out + ); + +always @(posedge clk or negedge rst_n) +begin + if(rst_n == 1'b0) + d_out <= {24{1'b0}}; + else if(d_in_en==1'b1)case(d_in) + //--0 + 8'd0 : d_out <= {8'h20,8'h20,8'h30}; + 8'd1 : d_out <= {8'h20,8'h20,8'h31}; + 8'd2 : d_out <= {8'h20,8'h20,8'h32}; + 8'd3 : d_out <= {8'h20,8'h20,8'h33}; + 8'd4 : d_out <= {8'h20,8'h20,8'h34}; + 8'd5 : d_out <= {8'h20,8'h20,8'h35}; + 8'd6 : d_out <= {8'h20,8'h20,8'h36}; + 8'd7 : d_out <= {8'h20,8'h20,8'h37}; + 8'd8 : d_out <= {8'h20,8'h20,8'h38}; + 8'd9 : d_out <= {8'h20,8'h20,8'h39}; + //--10 + 8'd10 : d_out <= {8'h20,8'h31,8'h30}; + 8'd11 : d_out <= {8'h20,8'h31,8'h31}; + 8'd12 : d_out <= {8'h20,8'h31,8'h32}; + 8'd13 : d_out <= {8'h20,8'h31,8'h33}; + 8'd14 : d_out <= {8'h20,8'h31,8'h34}; + 8'd15 : d_out <= {8'h20,8'h31,8'h35}; + 8'd16 : d_out <= {8'h20,8'h31,8'h36}; + 8'd17 : d_out <= {8'h20,8'h31,8'h37}; + 8'd18 : d_out <= {8'h20,8'h31,8'h38}; + 8'd19 : d_out <= {8'h20,8'h31,8'h39}; + //--20 + 8'd20 : d_out <= {8'h20,8'h32,8'h30}; + 8'd21 : d_out <= {8'h20,8'h32,8'h31}; + 8'd22 : d_out <= {8'h20,8'h32,8'h32}; + 8'd23 : d_out <= {8'h20,8'h32,8'h33}; + 8'd24 : d_out <= {8'h20,8'h32,8'h34}; + 8'd25 : d_out <= {8'h20,8'h32,8'h35}; + 8'd26 : d_out <= {8'h20,8'h32,8'h36}; + 8'd27 : d_out <= {8'h20,8'h32,8'h37}; + 8'd28 : d_out <= {8'h20,8'h32,8'h38}; + 8'd29 : d_out <= {8'h20,8'h32,8'h39}; + //--30 + 8'd30 : d_out <= {8'h20,8'h33,8'h30}; + 8'd31 : d_out <= {8'h20,8'h33,8'h31}; + 8'd32 : d_out <= {8'h20,8'h33,8'h32}; + 8'd33 : d_out <= {8'h20,8'h33,8'h33}; + 8'd34 : d_out <= {8'h20,8'h33,8'h34}; + 8'd35 : d_out <= {8'h20,8'h33,8'h35}; + 8'd36 : d_out <= {8'h20,8'h33,8'h36}; + 8'd37 : d_out <= {8'h20,8'h33,8'h37}; + 8'd38 : d_out <= {8'h20,8'h33,8'h38}; + 8'd39 : d_out <= {8'h20,8'h33,8'h39}; + //--40 + 8'd40 : d_out <= {8'h20,8'h34,8'h30}; + 8'd41 : d_out <= {8'h20,8'h34,8'h31}; + 8'd42 : d_out <= {8'h20,8'h34,8'h32}; + 8'd43 : d_out <= {8'h20,8'h34,8'h33}; + 8'd44 : d_out <= {8'h20,8'h34,8'h34}; + 8'd45 : d_out <= {8'h20,8'h34,8'h35}; + 8'd46 : d_out <= {8'h20,8'h34,8'h36}; + 8'd47 : d_out <= {8'h20,8'h34,8'h37}; + 8'd48 : d_out <= {8'h20,8'h34,8'h38}; + 8'd49 : d_out <= {8'h20,8'h34,8'h39}; + //--50 + 8'd50 : d_out <= {8'h20,8'h35,8'h30}; + 8'd51 : d_out <= {8'h20,8'h35,8'h31}; + 8'd52 : d_out <= {8'h20,8'h35,8'h32}; + 8'd53 : d_out <= {8'h20,8'h35,8'h33}; + 8'd54 : d_out <= {8'h20,8'h35,8'h34}; + 8'd55 : d_out <= {8'h20,8'h35,8'h35}; + 8'd56 : d_out <= {8'h20,8'h35,8'h36}; + 8'd57 : d_out <= {8'h20,8'h35,8'h37}; + 8'd58 : d_out <= {8'h20,8'h35,8'h38}; + 8'd59 : d_out <= {8'h20,8'h35,8'h39}; + //--60 + 8'd60 : d_out <= {8'h20,8'h36,8'h30}; + 8'd61 : d_out <= {8'h20,8'h36,8'h31}; + 8'd62 : d_out <= {8'h20,8'h36,8'h32}; + 8'd63 : d_out <= {8'h20,8'h36,8'h33}; + 8'd64 : d_out <= {8'h20,8'h36,8'h34}; + 8'd65 : d_out <= {8'h20,8'h36,8'h35}; + 8'd66 : d_out <= {8'h20,8'h36,8'h36}; + 8'd67 : d_out <= {8'h20,8'h36,8'h37}; + 8'd68 : d_out <= {8'h20,8'h36,8'h38}; + 8'd69 : d_out <= {8'h20,8'h36,8'h39}; + //--70 + 8'd70 : d_out <= {8'h20,8'h37,8'h30}; + 8'd71 : d_out <= {8'h20,8'h37,8'h31}; + 8'd72 : d_out <= {8'h20,8'h37,8'h32}; + 8'd73 : d_out <= {8'h20,8'h37,8'h33}; + 8'd74 : d_out <= {8'h20,8'h37,8'h34}; + 8'd75 : d_out <= {8'h20,8'h37,8'h35}; + 8'd76 : d_out <= {8'h20,8'h37,8'h36}; + 8'd77 : d_out <= {8'h20,8'h37,8'h37}; + 8'd78 : d_out <= {8'h20,8'h37,8'h38}; + 8'd79 : d_out <= {8'h20,8'h37,8'h39}; + //--80 + 8'd80 : d_out <= {8'h20,8'h38,8'h30}; + 8'd81 : d_out <= {8'h20,8'h38,8'h31}; + 8'd82 : d_out <= {8'h20,8'h38,8'h32}; + 8'd83 : d_out <= {8'h20,8'h38,8'h33}; + 8'd84 : d_out <= {8'h20,8'h38,8'h34}; + 8'd85 : d_out <= {8'h20,8'h38,8'h35}; + 8'd86 : d_out <= {8'h20,8'h38,8'h36}; + 8'd87 : d_out <= {8'h20,8'h38,8'h37}; + 8'd88 : d_out <= {8'h20,8'h38,8'h38}; + 8'd89 : d_out <= {8'h20,8'h38,8'h39}; + //--90 + 8'd90 : d_out <= {8'h20,8'h39,8'h30}; + 8'd91 : d_out <= {8'h20,8'h39,8'h31}; + 8'd92 : d_out <= {8'h20,8'h39,8'h32}; + 8'd93 : d_out <= {8'h20,8'h39,8'h33}; + 8'd94 : d_out <= {8'h20,8'h39,8'h34}; + 8'd95 : d_out <= {8'h20,8'h39,8'h35}; + 8'd96 : d_out <= {8'h20,8'h39,8'h36}; + 8'd97 : d_out <= {8'h20,8'h39,8'h37}; + 8'd98 : d_out <= {8'h20,8'h39,8'h38}; + 8'd99 : d_out <= {8'h20,8'h39,8'h39}; + //--100 + 8'd100 : d_out <= {8'h31,8'h30,8'h30}; + 8'd101 : d_out <= {8'h31,8'h30,8'h31}; + 8'd102 : d_out <= {8'h31,8'h30,8'h32}; + 8'd103 : d_out <= {8'h31,8'h30,8'h33}; + 8'd104 : d_out <= {8'h31,8'h30,8'h34}; + 8'd105 : d_out <= {8'h31,8'h30,8'h35}; + 8'd106 : d_out <= {8'h31,8'h30,8'h36}; + 8'd107 : d_out <= {8'h31,8'h30,8'h37}; + 8'd108 : d_out <= {8'h31,8'h30,8'h38}; + 8'd109 : d_out <= {8'h31,8'h30,8'h39}; + //--110 + 8'd110 : d_out <= {8'h31,8'h31,8'h30}; + 8'd111 : d_out <= {8'h31,8'h31,8'h31}; + 8'd112 : d_out <= {8'h31,8'h31,8'h32}; + 8'd113 : d_out <= {8'h31,8'h31,8'h33}; + 8'd114 : d_out <= {8'h31,8'h31,8'h34}; + 8'd115 : d_out <= {8'h31,8'h31,8'h35}; + 8'd116 : d_out <= {8'h31,8'h31,8'h36}; + 8'd117 : d_out <= {8'h31,8'h31,8'h37}; + 8'd118 : d_out <= {8'h31,8'h31,8'h38}; + 8'd119 : d_out <= {8'h31,8'h31,8'h39}; + //--120 + 8'd120 : d_out <= {8'h31,8'h32,8'h30}; + 8'd121 : d_out <= {8'h31,8'h32,8'h31}; + 8'd122 : d_out <= {8'h31,8'h32,8'h32}; + 8'd123 : d_out <= {8'h31,8'h32,8'h33}; + 8'd124 : d_out <= {8'h31,8'h32,8'h34}; + 8'd125 : d_out <= {8'h31,8'h32,8'h35}; + 8'd126 : d_out <= {8'h31,8'h32,8'h36}; + 8'd127 : d_out <= {8'h31,8'h32,8'h37}; + 8'd128 : d_out <= {8'h31,8'h32,8'h38}; + 8'd129 : d_out <= {8'h31,8'h32,8'h39}; + //--130 + 8'd130 : d_out <= {8'h31,8'h33,8'h30}; + 8'd131 : d_out <= {8'h31,8'h33,8'h31}; + 8'd132 : d_out <= {8'h31,8'h33,8'h32}; + 8'd133 : d_out <= {8'h31,8'h33,8'h33}; + 8'd134 : d_out <= {8'h31,8'h33,8'h34}; + 8'd135 : d_out <= {8'h31,8'h33,8'h35}; + 8'd136 : d_out <= {8'h31,8'h33,8'h36}; + 8'd137 : d_out <= {8'h31,8'h33,8'h37}; + 8'd138 : d_out <= {8'h31,8'h33,8'h38}; + 8'd139 : d_out <= {8'h31,8'h33,8'h39}; + default : d_out <= d_out; + endcase +end + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/reset_bridge.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/reset_bridge.v new file mode 100644 index 0000000..e774c62 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/reset_bridge.v @@ -0,0 +1,71 @@ +//----------------------------------------------------------------------------- +// +// Copyright (c) 2008 Xilinx Inc. +// +// Project : Programmable Wave Generator +// Module : reset_bridge.v +// Parent : Various +// Children : None +// +// Description: +// This is a specialized metastability hardener intended for use in the +// reset path. The reset will assert ASYNCHRONOUSLY when the input reset is +// asserted, but will deassert synchronously. +// +// In designs with asynchronous reset flip-flops, this generates a reset +// that can meet the "recovery time" requirement of the flip-flop (be sure +// to enable the recovery time arc checking - ENABLE=reg_sr_r). +// +// In designs with synchronous resets, it ensures that the reset is +// available before the first valid clock pulse arrives. +// +// Parameters: +// None +// +// Notes : +// +// Multicycle and False Paths, Timing Exceptions +// A tighter timing constraint should be placed between the rst_meta +// and rst_dst flip-flops to allow for meta-stability settling time +// + +`timescale 1ns/1ps + + +module reset_bridge ( + input clk, // Destination clock + input rst_n, // Asynchronous reset signal + output reg rst_dst // Synchronized reset signal +); + + +//*************************************************************************** +// Register declarations +//*************************************************************************** + + reg rst_meta; // After sampling the async rst, this has + // a high probability of being metastable. + // The second sampling (rst_dst) has + // a much lower probability of being + // metastable + +//*************************************************************************** +// Code +//*************************************************************************** + + always @(posedge clk or negedge rst_n) + begin + if (!rst_n) + begin + rst_meta <= 1'b1; + rst_dst <= 1'b1; + end + else // if !rst_n + begin + rst_meta <= 1'b0; + rst_dst <= rst_meta; + end // if rst_n + end // always + +endmodule + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_state.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_state.v new file mode 100644 index 0000000..a3480b9 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_state.v @@ -0,0 +1,516 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:33:33 02/27/2016 +// Design Name: +// Module Name: uart_state +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module uart_state( + //-- + input rst_n , + input clk , + //************************************************* + //--DDR + //************************************************* + input init_calib_complete , + input tg_compare_error , + input [ 47: 0] w_code_rate , + input [ 47: 0] r_code_rate , + //*********************************************************** + //--Temp + //*********************************************************** + input [11:0] device_temp , + //*********************************************************** + //--LED + //*********************************************************** + input [ 1 : 0] led , + //*********************************************************** + //--KEY + //*********************************************************** + input key , + //*********************************************************** + //--UART + //*********************************************************** + output reg char_fifo_empty , // Empty signal from char FIFO (FWFT) + output reg[ 7 : 0] char_fifo_dout , // Data from the char FIFO + input char_fifo_rd_en // Pop signal to the char FIFO + ); + + +wire [12*2-1:0] device_temp_h_r ; +wire [8*1-1:0] device_temp_l_r ; +wire [20:0] device_temp_mul ; +wire [8:0] device_temp_div ; +wire [7:0] device_temp_del ; + +reg d_in_en ; +//******************************************************************* +// +//******************************************************************* +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + d_in_en <= 1'b0; + else if(time_cnt == 28'd1) + d_in_en <= 1'b1; + else + d_in_en <= 1'b0; +end +//******************************************************************* +//--LED +//******************************************************************* +reg[7:0]led_r1[0:1]; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n)begin + led_r1[0] <= 8'b0;led_r1[1] <= 8'b0; + end + else if(led[1]==1'b1)begin + led_r1[0] <= 8'hA1;led_r1[1] <= 8'hEE;//--¡î + end + else begin + led_r1[0] <= 8'hA1;led_r1[1] <= 8'hEF;//--¡ï + end +end +reg[7:0]led_r2[0:1]; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n)begin + led_r2[0] <= 8'b0;led_r2[1] <= 8'b0; + end + else if(led[0]==1'b1)begin + led_r2[0] <= 8'hA1;led_r2[1] <= 8'hEE;//--¡î + end + else begin + led_r2[0] <= 8'hA1;led_r2[1] <= 8'hEF;//--¡ï + end +end +//******************************************************************* +//--KYE +//******************************************************************* +reg[7:0]key_r1[0:5]; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n)begin + key_r1[0] <= 8'b0;key_r1[1] <= 8'b0; + key_r1[2] <= 8'b0;key_r1[3] <= 8'b0; + key_r1[4] <= 8'b0;key_r1[5] <= 8'b0; + end + else if(key==1'b1)begin + key_r1[0] <= 8'hB8;key_r1[1] <= 8'hDF; //¸ß + key_r1[2] <= 8'hB5;key_r1[3] <= 8'hE7; //µç + key_r1[4] <= 8'hC6;key_r1[5] <= 8'hBD; //ƽ + end + else begin + key_r1[0] <= 8'hB5;key_r1[1] <= 8'hCD; //µÍ + key_r1[2] <= 8'hB5;key_r1[3] <= 8'hE7; //µç + key_r1[4] <= 8'hC6;key_r1[5] <= 8'hBD; //ƽ + end +end +//******************************************************************* +//--Temp +//******************************************************************* +assign device_temp_mul = device_temp * 504; +assign device_temp_div = device_temp_mul[20:12]; +assign device_temp_del = device_temp_div - 273; +device_temp_ascii_dis device_temp_h + ( + //-- + .rst_n (rst_n ), + .clk (clk ), + .d_in_en (d_in_en ), + .d_in (device_temp_del ), + .d_out (device_temp_h_r ) + ); +ascii_code # + ( + .DATA_IN_WIDTH (4 ), + .DATA_OUT_WIDTH (4*2 ) + ) + device_temp_l + ( + .rst_n (rst_n ), + .clk (clk ), + .d_in_en (d_in_en ), + .d_in ({1'b0,device_temp_mul[11:9]}), + .d_out (device_temp_l_r ) + ); +//******************************************************************* +//--DDR³õʼ»¯ +//--³É¹¦£ºB3 C9 B9 A6 +//--ʧ°Ü£ºCA A7 B0 DC +//******************************************************************* +reg [7:0] ddr_init_state[0:3] ; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n)begin + ddr_init_state[0] <= 8'b0;ddr_init_state[1] <= 8'b0; + ddr_init_state[2] <= 8'b0;ddr_init_state[3] <= 8'b0; + end + else if(init_calib_complete==1'b1)begin + ddr_init_state[0] <= 8'hB3;ddr_init_state[1] <= 8'hC9;//--³É + ddr_init_state[2] <= 8'hB9;ddr_init_state[3] <= 8'hA6;//--¹¦ + end + else begin + ddr_init_state[0] <= 8'hCA;ddr_init_state[1] <= 8'hA7;//--ʧ + ddr_init_state[2] <= 8'hB0;ddr_init_state[3] <= 8'hDC;//--°Ü + end +end +//******************************************************************* +//--DDR×Ô¼ì +//--ÕýÈ·£ºD5 FD C8 B7 +//--´íÎó£ºB4 ED CE F3 +//******************************************************************* +reg [7:0] ddr_rw_state[0:3] ; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n)begin + ddr_rw_state[0] <= 8'b0;ddr_rw_state[1] <= 8'b0; + ddr_rw_state[2] <= 8'b0;ddr_rw_state[3] <= 8'b0; + end + else if(init_calib_complete==1'b1 && tg_compare_error==1'b0)begin + ddr_rw_state[0] <= 8'hD5;ddr_rw_state[1] <= 8'hFD;//--Õý + ddr_rw_state[2] <= 8'hC8;ddr_rw_state[3] <= 8'hB7;//--È· + end + else begin + ddr_rw_state[0] <= 8'hB4;ddr_rw_state[1] <= 8'hED;//--Îó + ddr_rw_state[2] <= 8'hCE;ddr_rw_state[3] <= 8'hF3;//--´í + end +end + +//************************************* +//--DDRдÂëÂÊ16½øÖÆ ¡ª¡ª> ×Ö·û +//************************************* +wire[48*2-1:0]w_code_rate_r; +ascii_code # + ( + .DATA_IN_WIDTH (48 ), + .DATA_OUT_WIDTH (48*2 ) + ) + DDR_WR + ( + .rst_n (rst_n ), + .clk (clk ), + .d_in_en (d_in_en ), + .d_in (w_code_rate ), + .d_out (w_code_rate_r ) + ); +//************************************* +//--DDR¶ÁÂëÂÊ16½øÖÆ ¡ª¡ª> ×Ö·û +//************************************* +wire[48*2-1:0]r_code_rate_r; +ascii_code # + ( + .DATA_IN_WIDTH (48 ), + .DATA_OUT_WIDTH (48*2 ) + ) + DDR_RD + ( + .rst_n (rst_n ), + .clk (clk ), + .d_in_en (d_in_en ), + .d_in (r_code_rate ), + .d_out (r_code_rate_r ) + ); +//************************************************************************* +//²½½ø²ÎÊý¶¨Òå +//************************************************************************* +localparam I1 = 0; +localparam I2 = I1 + 50; +localparam I3 = I2 + 30; +localparam I4 = I3 + 30; +localparam I5 = I4 + 20; +localparam I6 = I5 + 20; +localparam I7 = I6 + 30; +localparam I8 = I7 + 30; +localparam I9 = I8 + 30 + 1; +//************************************************************************* +//--ºÚ:BADA Ó¥:D3A5 FP:4650 GA:4741 ¿ª:BFAA ·¢:B7A2 °å:B0E5 +//************************************************************************* +wire[7:0]uart_info[0:I9]; +assign uart_info[I1+0] = 8'h02; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+1] = 8'h0D; +assign uart_info[I1+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I1+3] = 8'h0D; +assign uart_info[I1+4] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I1+5] = 8'h0D; +assign uart_info[I1+6] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I1+7] = 8'h20; +assign uart_info[I1+8] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+9] = 8'h20; +assign uart_info[I1+10] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+11] = 8'h20; +assign uart_info[I1+12] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+13] = 8'h0D; +assign uart_info[I1+14] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I1+15] = 8'h20; +assign uart_info[I1+16] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+17] = 8'h20; +assign uart_info[I1+18] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+19] = 8'h20; +assign uart_info[I1+20] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+21] = 8'h20; +assign uart_info[I1+22] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+23] = 8'h20; +assign uart_info[I1+24] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+25] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I1+26] = 8'hBA; +assign uart_info[I1+27] = 8'hDA; //--ºÚ +assign uart_info[I1+28] = 8'hD3; +assign uart_info[I1+29] = 8'hA5; //--Ó¥ +assign uart_info[I1+30] = 8'h46; +assign uart_info[I1+31] = 8'h50; //--FP +assign uart_info[I1+32] = 8'h47; +assign uart_info[I1+33] = 8'h41; //--GA +assign uart_info[I1+34] = 8'hBF; +assign uart_info[I1+35] = 8'hAA; //--¿ª +assign uart_info[I1+36] = 8'hB7; +assign uart_info[I1+37] = 8'hA2; //--·¢ +assign uart_info[I1+38] = 8'hB0; +assign uart_info[I1+39] = 8'hE5; //--°å +assign uart_info[I1+40] = 8'h41; +assign uart_info[I1+41] = 8'h37; //--A7 +assign uart_info[I1+42] = 8'h30; +assign uart_info[I1+43] = 8'h34; //--04 +assign uart_info[I1+44] = 8'h20; +assign uart_info[I1+45] = 8'h20; +assign uart_info[I1+46] = 8'h20; +assign uart_info[I1+47] = 8'h20; +assign uart_info[I1+48] = 8'h20; +assign uart_info[I1+49] = 8'h0D; +assign uart_info[I1+50] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +//************************************************************************* +//--״̬µÆ£ºD7B4CCACB5C6 +//************************************************************************* +assign uart_info[I2+1] = 8'h0D; +assign uart_info[I2+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I2+3] = 8'hD7; +assign uart_info[I2+4] = 8'hB4; //--×´ +assign uart_info[I2+5] = 8'hCC; +assign uart_info[I2+6] = 8'hAC; //--̬ +assign uart_info[I2+7] = 8'hB5; +assign uart_info[I2+8] = 8'hC6; //--µÆ +assign uart_info[I2+9] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I2+10] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I2+11] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I2+12] = 8'h3A; //--:<×Ö·û> +assign uart_info[I2+13] = 8'h20; +assign uart_info[I2+14] = 8'h20; +assign uart_info[I2+15] = 8'h20; +assign uart_info[I2+16] = 8'h20; +assign uart_info[I2+17] = 8'h20; +assign uart_info[I2+18] = 8'h20; +assign uart_info[I2+19] = 8'h20; +assign uart_info[I2+20] = 8'h20; +assign uart_info[I2+21] = 8'h20; +assign uart_info[I2+22] = 8'h20; +assign uart_info[I2+23] = led_r1[0]; +assign uart_info[I2+24] = led_r1[1]; +assign uart_info[I2+25] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I2+26] = led_r2[0]; +assign uart_info[I2+27] = led_r2[1]; +assign uart_info[I2+28] = 8'h20; +assign uart_info[I2+29] = 8'h20; +assign uart_info[I2+30] = 8'h20; +//******************************************************************* +//--FPGAζÈ:46 50 47 41 CE C2 B6 C8 ¡ãC :A1E343 +//******************************************************************* +assign uart_info[I3+1] = 8'h0D; assign uart_info[I3+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I3+3] = 8'h0D; assign uart_info[I3+4] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I3+5] = 8'h46; assign uart_info[I3+6] = 8'h50; //--FP +assign uart_info[I3+7] = 8'h47; assign uart_info[I3+8] = 8'h41; //--GA +assign uart_info[I3+9] = 8'hCE; assign uart_info[I3+10] = 8'hC2; //--Π+assign uart_info[I3+11] = 8'hB6; assign uart_info[I3+12] = 8'hC8; //--¶È +assign uart_info[I3+13] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+14] = 8'h3A; //--:<×Ö·û> +assign uart_info[I3+15] = device_temp_h_r[(2 +1)*8-1:2 *8]; +assign uart_info[I3+16] = device_temp_h_r[(1 +1)*8-1:1 *8]; +assign uart_info[I3+17] = device_temp_h_r[(0 +1)*8-1:0 *8]; +assign uart_info[I3+18] = 8'h2E; //--.<×Ö·û> +assign uart_info[I3+19] = {4'h3,device_temp_l_r[3:0]}; +assign uart_info[I3+20] = 8'hA1; +assign uart_info[I3+21] = 8'hE3; +assign uart_info[I3+22] = 8'h43; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+23] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+24] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+25] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+26] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+27] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+28] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+29] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I3+30] = 8'h20; //--¿Õ¸ñ<×Ö·û> +//******************************************************************* +//--DDR³õʼ»¯:44 44 52 B3 F5 CA BC BB AF +//******************************************************************* +assign uart_info[I4+1] = 8'h0D; assign uart_info[I4+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I4+3] = 8'h0D; assign uart_info[I4+4] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I4+5] = 8'h44; assign uart_info[I4+6] = 8'h44; assign uart_info[I4+7] = 8'h52;//--DDR +assign uart_info[I4+8] = 8'hB3; assign uart_info[I4+9] = 8'hF5; //--³õ +assign uart_info[I4+10] = 8'hCA; assign uart_info[I4+11] = 8'hBC; //--ʼ +assign uart_info[I4+12] = 8'hBB; assign uart_info[I4+13] = 8'hAF; //--»¯ +assign uart_info[I4+14] = 8'h3A; //--:<×Ö·û> +assign uart_info[I4+15] = ddr_init_state[0]; +assign uart_info[I4+16] = ddr_init_state[1]; +assign uart_info[I4+17] = ddr_init_state[2]; +assign uart_info[I4+18] = ddr_init_state[3]; +assign uart_info[I4+19] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I4+20] = 8'h20; //--¿Õ¸ñ<×Ö·û> +//******************************************************************* +//--DDR×Ô¼ì:44 44 52 D7 D4 BC EC +//******************************************************************* +assign uart_info[I5+1] = 8'h0D; assign uart_info[I5+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I5+3] = 8'h0D; assign uart_info[I5+4] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I5+5] = 8'h44; assign uart_info[I5+6] = 8'h44; assign uart_info[I5+7] = 8'h52;//--DDR +assign uart_info[I5+8] = 8'hD7; assign uart_info[I5+9] = 8'hD4; //--×Ô +assign uart_info[I5+10] = 8'hBC; assign uart_info[I5+11] = 8'hEC; //--¼ì +assign uart_info[I5+12] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I5+13] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I5+14] = 8'h3A; //--:<×Ö·û> +assign uart_info[I5+15] = ddr_rw_state[0]; +assign uart_info[I5+16] = ddr_rw_state[1]; +assign uart_info[I5+17] = ddr_rw_state[2]; +assign uart_info[I5+18] = ddr_rw_state[3]; +assign uart_info[I5+19] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I5+20] = 8'h20; //--¿Õ¸ñ<×Ö·û> +//******************************************************************* +//--DDRдÂëÂÊ:44 44 52 D0 B4 C2 EB C2 CA 3A +//*******************************************************************1 +assign uart_info[I6+1] = 8'h0D; assign uart_info[I6+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I6+3] = 8'h0D; assign uart_info[I6+4] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I6+5] = 8'h44; assign uart_info[I6+6] = 8'h44; assign uart_info[I6+7] = 8'h52;//--DDR +assign uart_info[I6+8] = 8'hD0; assign uart_info[I6+9] = 8'hB4; //--д +assign uart_info[I6+10] = 8'hCD; assign uart_info[I6+11] = 8'hB3; //--ͳ +assign uart_info[I6+12] = 8'hBC; assign uart_info[I6+13] = 8'hC6; //--¼Æ +assign uart_info[I6+14] = 8'h3A; //--:<×Ö·û> +assign uart_info[I6+15] = w_code_rate_r[(11+1)*8-1:11*8]; +assign uart_info[I6+16] = w_code_rate_r[(10+1)*8-1:10*8]; +assign uart_info[I6+17] = w_code_rate_r[(9 +1)*8-1:9 *8]; +assign uart_info[I6+18] = w_code_rate_r[(8 +1)*8-1:8 *8]; +assign uart_info[I6+19] = w_code_rate_r[(7 +1)*8-1:7 *8]; +assign uart_info[I6+20] = w_code_rate_r[(6 +1)*8-1:6 *8]; +assign uart_info[I6+21] = w_code_rate_r[(5 +1)*8-1:5 *8]; +assign uart_info[I6+22] = w_code_rate_r[(4 +1)*8-1:4 *8]; +assign uart_info[I6+23] = w_code_rate_r[(3 +1)*8-1:3 *8]; +assign uart_info[I6+24] = w_code_rate_r[(2 +1)*8-1:2 *8]; +assign uart_info[I6+25] = w_code_rate_r[(1 +1)*8-1:1 *8]; +assign uart_info[I6+26] = w_code_rate_r[(0 +1)*8-1:0 *8]; +assign uart_info[I6+27] = 8'h20; +assign uart_info[I6+28] = 8'h20; +assign uart_info[I6+29] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I6+30] = 8'h20; //--¿Õ¸ñ<×Ö·û> +//******************************************************************* +//--DDR¶ÁÂëÂÊ:44 44 52 B6 C1 C2 EB C2 CA +//******************************************************************* +assign uart_info[I7+1] = 8'h0D; assign uart_info[I7+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I7+3] = 8'h0D; assign uart_info[I7+4] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I7+5] = 8'h44; assign uart_info[I7+6] = 8'h44; assign uart_info[I7+7] = 8'h52;//--DDR +assign uart_info[I7+8] = 8'hB6; assign uart_info[I7+9] = 8'hC1; //--¶Á +assign uart_info[I7+10] = 8'hCD; assign uart_info[I7+11] = 8'hB3; //--ͳ +assign uart_info[I7+12] = 8'hBC; assign uart_info[I7+13] = 8'hC6; //--¼Æ +assign uart_info[I7+14] = 8'h3A; //--:<×Ö·û> +assign uart_info[I7+15] = r_code_rate_r[(11+1)*8-1:11*8]; +assign uart_info[I7+16] = r_code_rate_r[(10+1)*8-1:10*8]; +assign uart_info[I7+17] = r_code_rate_r[(9 +1)*8-1:9 *8]; +assign uart_info[I7+18] = r_code_rate_r[(8 +1)*8-1:8 *8]; +assign uart_info[I7+19] = r_code_rate_r[(7 +1)*8-1:7 *8]; +assign uart_info[I7+20] = r_code_rate_r[(6 +1)*8-1:6 *8]; +assign uart_info[I7+21] = r_code_rate_r[(5 +1)*8-1:5 *8]; +assign uart_info[I7+22] = r_code_rate_r[(4 +1)*8-1:4 *8]; +assign uart_info[I7+23] = r_code_rate_r[(3 +1)*8-1:3 *8]; +assign uart_info[I7+24] = r_code_rate_r[(2 +1)*8-1:2 *8]; +assign uart_info[I7+25] = r_code_rate_r[(1 +1)*8-1:1 *8]; +assign uart_info[I7+26] = r_code_rate_r[(0 +1)*8-1:0 *8]; +assign uart_info[I7+27] = 8'h20; +assign uart_info[I7+28] = 8'h20; +assign uart_info[I7+29] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I7+30] = 8'h20; //--¿Õ¸ñ<×Ö·û> +//******************************************************************* +//--°´:BC FC ¼ü:OD OA 1:31 +//******************************************************************* +assign uart_info[I8+1] = 8'h0D; assign uart_info[I8+2] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I8+3] = 8'h0D; assign uart_info[I8+4] = 8'h0A; //--»Ø³µ»»ÐÐ<×Ö·û> +assign uart_info[I8+5] = 8'hB0; assign uart_info[I8+6] = 8'hB4; //--°´ +assign uart_info[I8+7] = 8'hBC; assign uart_info[I8+8] = 8'hFC; //--¼ü +assign uart_info[I8+9] = 8'h20; +assign uart_info[I8+10] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+11] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+12] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+13] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+14] = 8'h3A; //--:<×Ö·û> +assign uart_info[I8+15] = key_r1[0]; +assign uart_info[I8+16] = key_r1[1]; +assign uart_info[I8+17] = key_r1[2]; +assign uart_info[I8+18] = key_r1[3]; +assign uart_info[I8+19] = key_r1[4]; +assign uart_info[I8+20] = key_r1[5]; +assign uart_info[I8+21] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+22] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+23] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+24] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+25] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+26] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+27] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+28] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+29] = 8'h20; //--¿Õ¸ñ<×Ö·û> +assign uart_info[I8+30] = 8'h20; //--¿Õ¸ñ<×Ö·û> +//************************************* +//--1s ¶¨Ê±¼ÆÊýÆ÷ +//************************************* +reg[27:0]time_cnt; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + time_cnt <= 28'd0; + else if(time_cnt == 28'd50000000) //--50Mhz 1s ¶¨Ê±¼ÆÊýÆ÷ + time_cnt <= 28'b0; + else + time_cnt <= time_cnt + 1'b1; +end +//-- +reg char_fifo_rd_en_1r; +reg char_fifo_rd_en_2r; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n)begin + char_fifo_rd_en_1r <= 1'd0; + char_fifo_rd_en_2r <= 1'd0; + end + else begin + char_fifo_rd_en_1r <= char_fifo_rd_en; + char_fifo_rd_en_2r <= char_fifo_rd_en_1r; + end +end +wire char_fifo_rd_en_pos = (char_fifo_rd_en_1r==1'b1 && char_fifo_rd_en_2r==1'b0) ? 1'b1 :1'b0; +reg[8:0]req_cnt; +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + req_cnt <= 9'd0; + else if(time_cnt == 28'd50000000) + req_cnt <= 9'b0; + else if(char_fifo_rd_en_pos==1'b1) + req_cnt <= req_cnt + 1'b1; +end +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + char_fifo_dout <= 8'd0; + else + char_fifo_dout <= uart_info[req_cnt]; +end +always @ (posedge clk or negedge rst_n)begin + if(!rst_n) + char_fifo_empty <= 1'b1; + else if(req_cnt>=I9) + char_fifo_empty <= 1'b1; + else + char_fifo_empty <= 1'b0; +end + +endmodule + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_top.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_top.v new file mode 100644 index 0000000..dd903f4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_top.v @@ -0,0 +1,86 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:25:31 02/27/2016 +// Design Name: +// Module Name: uart_top +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module uart_top( + //-- + input rst_n , + input clk , + //*********************************************************** + //--DDR + //*********************************************************** + input init_calib_complete , + input tg_compare_error , + input [ 47: 0] w_code_rate , + input [ 47: 0] r_code_rate , + //*********************************************************** + //--Temp + //*********************************************************** + input [11:0] device_temp , + //*********************************************************** + //--LED + //*********************************************************** + input [ 1 : 0] led , + //*********************************************************** + //--KYE + //*********************************************************** + input key , + //*********************************************************** + //--UART Interface + //*********************************************************** + input uart_rxd , + output uart_txd + ); +wire[7:0]char_fifo_dout; + +uart_state uart_state ( + .rst_n (rst_n ), + .clk (clk ), + .init_calib_complete (init_calib_complete ), + .tg_compare_error (tg_compare_error ), + .w_code_rate (w_code_rate ), + .r_code_rate (r_code_rate ), + //*********************************************************** + //--Temp + //*********************************************************** + .device_temp (device_temp ), + .led (led ), + .key (key ), + .char_fifo_empty (char_fifo_empty ), + .char_fifo_dout (char_fifo_dout ), + .char_fifo_rd_en (char_fifo_rd_en ) + ); +reset_bridge reset_bridge_clk_tx ( + .clk (clk ), + .rst_n (rst_n ), + .rst_dst (rst_clk_tx ) + ); + +uart_tx uart_tx ( + .clk_tx (clk ), + .rst_clk_tx (rst_clk_tx ), + .char_fifo_empty (char_fifo_empty ), + .char_fifo_dout (char_fifo_dout ), + .char_fifo_rd_en (char_fifo_rd_en ), + .txd_tx (uart_txd ) + ); + + + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_baud_gen.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_baud_gen.v new file mode 100644 index 0000000..ccf9bdb --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_baud_gen.v @@ -0,0 +1,133 @@ +//----------------------------------------------------------------------------- +// +// Copyright (c) 2008 Xilinx Inc. +// +// Project : Programmable Wave Generator +// Module : uart_baud_gen.v +// Parent : uart_rx and uart_tx +// Children : None +// +// Description: +// Generates a 16x Baud enable. This signal is generated 16 times per bit +// at the correct baud rate as determined by the parameters for the system +// clock frequency and the Baud rate +// +// Parameters: +// BAUD_RATE : Baud rate - set to 57,600bps by default +// CLOCK_RATE: Clock rate - set to 50MHz by default +// +// Local Parameters: +// OVERSAMPLE_RATE: The oversampling rate - 16 x BAUD_RATE +// DIVIDER : The number of clocks per baud_x16_en +// CNT_WIDTH : Width of the counter +// +// Notes : +// 1) Divider must be at least 2 (thus CLOCK_RATE must be at least 32x +// BAUD_RATE) +// +// Multicycle and False Paths +// None +// + +`timescale 1ns/1ps + + +module uart_baud_gen ( + // Write side inputs + input clk, // Clock input + input rst, // Active HIGH reset - synchronous to clk + output baud_x16_en // Oversampled Baud rate enable +); + + +//*************************************************************************** +// Constant Functions +//*************************************************************************** + // Generate the ceiling of the log base 2 - i.e. the number of bits + // required to hold N values. A vector of size clogb2(N) will hold the + // values 0 to N-1 + function integer clogb2; + input [31:0] value; + reg [31:0] my_value; + begin + my_value = value - 1; + for (clogb2 = 0; my_value > 0; clogb2 = clogb2 + 1) + my_value = my_value >> 1; + end + endfunction + // +//*************************************************************************** +// Parameter definitions +//*************************************************************************** + + parameter BAUD_RATE = 57_600; // Baud rate + parameter CLOCK_RATE = 50_000_000; + + // The OVERSAMPLE_RATE is the BAUD_RATE times 16 + localparam OVERSAMPLE_RATE = BAUD_RATE * 16; + + // The divider is the CLOCK_RATE / OVERSAMPLE_RATE - rounded up + // (so add 1/2 of the OVERSAMPLE_RATE before the integer division) + localparam DIVIDER = (CLOCK_RATE+OVERSAMPLE_RATE/2) / OVERSAMPLE_RATE; + + // The value to reload the counter is DIVIDER-1; + localparam OVERSAMPLE_VALUE = DIVIDER - 1; + + // The required width of the counter is the ceiling of the base 2 logarithm + // of the DIVIDER + localparam CNT_WID = clogb2(DIVIDER); + + +//*************************************************************************** +// Reg declarations +//*************************************************************************** + + reg [CNT_WID-1:0] internal_count; + reg baud_x16_en_reg; + + +//*************************************************************************** +// Wire declarations +//*************************************************************************** + + wire [CNT_WID-1:0] internal_count_m_1; // Count minus 1 + + +//*************************************************************************** +// Code +//*************************************************************************** + + assign internal_count_m_1 = internal_count - 1'b1; + + // Count from DIVIDER-1 to 0, setting baud_x16_en_reg when internal_count=0. + // The signal baud_x16_en_reg must come from a flop (since it is a module + // output) so schedule it to be set when the next count is 1 (i.e. when + // internal_count_m_1 is 0). + always @(posedge clk) + begin + if (rst) + begin + internal_count <= OVERSAMPLE_VALUE; + baud_x16_en_reg <= 1'b0; + end + else + begin + // Assert baud_x16_en_reg in the next clock when internal_count will be + // zero in that clock (thus when internal_count_m_1 is 0). + baud_x16_en_reg <= (internal_count_m_1 == {CNT_WID{1'b0}}); + + // Count from OVERSAMPLE_VALUE down to 0 repeatedly + if (internal_count == {CNT_WID{1'b0}}) + begin + internal_count <= OVERSAMPLE_VALUE; + end + else // internal_count is not 0 + begin + internal_count <= internal_count_m_1; + end + end // if rst + end // always + + assign baud_x16_en = baud_x16_en_reg; + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx.v new file mode 100644 index 0000000..397d8c4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx.v @@ -0,0 +1,91 @@ +//----------------------------------------------------------------------------- +// +// Copyright (c) 2009 Xilinx Inc. +// +// Project : Programmable Wave Generator +// Module : uart_tx.v +// Parent : wave_gen.v +// Children : uart_tx_ctl.v uart_baud_gen.v .v +// +// Description: +// Top level of the UART transmitter. +// Brings together the baudrate generator and the actual UART transmit +// controller +// +// Parameters: +// BAUD_RATE : Baud rate - set to 57,600bps by default +// CLOCK_RATE: Clock rate - set to 50MHz by default +// +// Local Parameters: +// +// Notes : +// +// Multicycle and False Paths +// The uart_baud_gen module generates a 1-in-N pulse (where N is +// determined by the baud rate and the system clock frequency), which +// enables all flip-flops in the uart_tx_ctl module. Therefore, all paths +// within uart_tx_ctl are multicycle paths, as long as N > 2 (which it +// will be for all reasonable combinations of Baud rate and system +// frequency). +// + +`timescale 1ns/1ps + + +module uart_tx ( + input clk_tx, // Clock input + input rst_clk_tx, // Active HIGH reset - synchronous to clk_tx + + input char_fifo_empty, // Empty signal from char FIFO (FWFT) + input [7:0] char_fifo_dout, // Data from the char FIFO + output char_fifo_rd_en, // Pop signal to the char FIFO + + output txd_tx // The transmit serial signal +); + + +//*************************************************************************** +// Parameter definitions +//*************************************************************************** + + parameter BAUD_RATE = 57_600; // Baud rate + + parameter CLOCK_RATE = 50_000_000; + +//*************************************************************************** +// Reg declarations +//*************************************************************************** + +//*************************************************************************** +// Wire declarations +//*************************************************************************** + + wire baud_x16_en; // 1-in-N enable for uart_rx_ctl FFs + +//*************************************************************************** +// Code +//*************************************************************************** + + uart_baud_gen # + ( .BAUD_RATE (BAUD_RATE), + .CLOCK_RATE (CLOCK_RATE) + ) uart_baud_gen_tx_i0 ( + .clk (clk_tx), + .rst (rst_clk_tx), + .baud_x16_en (baud_x16_en) + ); + + uart_tx_ctl uart_tx_ctl_i0 ( + .clk_tx (clk_tx), // Clock input + .rst_clk_tx (rst_clk_tx), // Active HIGH reset + + .baud_x16_en (baud_x16_en), // 16x oversample enable + + .char_fifo_empty (char_fifo_empty), // Empty signal from char FIFO (FWFT) + .char_fifo_dout (char_fifo_dout), // Data from the char FIFO + .char_fifo_rd_en (char_fifo_rd_en), // Pop signal to the char FIFO + + .txd_tx (txd_tx) // The transmit serial signal + ); + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx_ctl.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx_ctl.v new file mode 100644 index 0000000..105c73d --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/uart_ctrl/uart_tx/uart_tx_ctl.v @@ -0,0 +1,262 @@ +//----------------------------------------------------------------------------- +// +// Copyright (c) 2009 Xilinx Inc. +// +// Project : Programmable Wave Generator +// Module : uart_tx_ctl.v +// Parent : uart_tx +// Children : none +// +// Description: +// UART transmit controller +// Implements the state machines for doing RS232 transmission. +// +// Whenever a character is ready for transmission (as indicated by the +// empty signal from the character FIFO), this module will transmit the +// character. +// +// The basis of this design is a simple state machine. When in IDLE, it +// waits for the character FIFO to indicate that a character is available, +// at which time, it immediately starts transmition. It spends 16 +// baud_x16_en periods in the START state, transmitting the START +// condition (1'b0), then tranisitions to the DATA state, where it sends +// the 8 data bits (LSbit first), each lasting 16 baud_x16_en periods, and +// finally going to the STOP state for 16 periods, where it transmits the +// STOP value (1'b1). +// +// On the last baud_x16_en period of the last data bit (in the DATA +// state), it issues the POP signal to the character FIFO. Since the SM is +// only enabled when baud_x16_en is asserted, the resulting pop signal +// must then be ANDed with baud_x16_en to ensure that only one character +// is popped at a time. +// +// On the last baud_x16_en period of the STOP state, the empty indication +// from the character FIFO is inspected; if asserted, the SM returns to +// the IDLE state, otherwise it transitions directly to the START state to +// start the transmission of the next character. +// +// There are two internal counters - one which counts off the 16 pulses of +// baud_x16_en, and a second which counts the 8 bits of data. +// +// The generation of the output (txd_tx) follows one complete baud_x16_en +// period after the state machine and other internal counters. +// +// Parameters: +// None +// +// Local Parameters: +// +// Notes : +// +// Multicycle and False Paths +// All flip-flops within this module share the same chip enable, generated +// by the Baud rate generator. Hence, all paths from FFs to FFs in this +// module are multicycle paths. +// + +`timescale 1ns/1ps + + +module uart_tx_ctl ( + input clk_tx, // Clock input + input rst_clk_tx, // Active HIGH reset - synchronous to clk_tx + + input baud_x16_en, // 16x bit oversampling pulse + + input char_fifo_empty, // Empty signal from char FIFO (FWFT) + input [7:0] char_fifo_dout, // Data from the char FIFO + output char_fifo_rd_en, // Pop signal to the char FIFO + + output reg txd_tx // The transmit serial signal +); + + +//*************************************************************************** +// Parameter definitions +//*************************************************************************** + + // State encoding for main FSM + localparam + IDLE = 2'b00, + START = 2'b01, + DATA = 2'b10, + STOP = 2'b11; + + +//*************************************************************************** +// Reg declarations +//*************************************************************************** + + reg [1:0] state; // Main state machine + reg [3:0] over_sample_cnt; // Oversample counter - 16 per bit + reg [2:0] bit_cnt; // Bit counter - which bit are we RXing + reg char_fifo_pop; // POP indication to FIFO + // ANDed with baud_x16_en before module + // output + +//*************************************************************************** +// Wire declarations +//*************************************************************************** + + wire over_sample_cnt_done; // We are in the middle of a bit + wire bit_cnt_done; // This is the last data bit + +//*************************************************************************** +// Code +//*************************************************************************** + + // Main state machine + always @(posedge clk_tx) + begin + if (rst_clk_tx) + begin + state <= IDLE; + char_fifo_pop <= 1'b0; + end + else + begin + if (baud_x16_en) + begin + char_fifo_pop <= 1'b0; + case (state) + IDLE: begin + // When the character FIFO is not empty, transition to the START + // state + if (!char_fifo_empty) + begin + state <= START; + end + end // IDLE state + + START: begin + if (over_sample_cnt_done) + begin + state <= DATA; + end // if over_sample_cnt_done + end // START state + + DATA: begin + // Once the last bit has been transmitted, send the stop bit + // Also, we need to POP the FIFO + if (over_sample_cnt_done && bit_cnt_done) + begin + char_fifo_pop <= 1'b1; + state <= STOP; + end + end // DATA state + + STOP: begin + if (over_sample_cnt_done) + begin + // If there is no new character to start, return to IDLE, else + // start it right away + if (char_fifo_empty) + begin + state <= IDLE; + end + else + begin + state <= START; + end + end + end // STOP state + endcase + end // if baud_x16_en + end // if rst_clk_tx + end // always + + // Assert the rd_en to the FIFO for only ONE clock period + assign char_fifo_rd_en = char_fifo_pop && baud_x16_en; + + + // Oversample counter + // Pre-load whenever we are starting a new character (in IDLE or in STOP), + // or whenever we are within a character (when we are in START or DATA). + always @(posedge clk_tx) + begin + if (rst_clk_tx) + begin + over_sample_cnt <= 4'd0; + end + else + begin + if (baud_x16_en) + begin + if (!over_sample_cnt_done) + begin + over_sample_cnt <= over_sample_cnt - 1'b1; + end + else + begin + if (((state == IDLE) && !char_fifo_empty) || + (state == START) || + (state == DATA) || + ((state == STOP) && !char_fifo_empty)) + begin + over_sample_cnt <= 4'd15; + end + end + end // if baud_x16_en + end // if rst_clk_tx + end // always + + assign over_sample_cnt_done = (over_sample_cnt == 4'd0); + + // Track which bit we are about to transmit + // Set to 0 in the START state + // Increment in all DATA states + always @(posedge clk_tx) + begin + if (rst_clk_tx) + begin + bit_cnt <= 3'b0; + end + else + begin + if (baud_x16_en) + begin + if (over_sample_cnt_done) + begin + if (state == START) + begin + bit_cnt <= 3'd0; + end + else if (state == DATA) + begin + bit_cnt <= bit_cnt + 1'b1; + end + end // if over_sample_cnt_done + end // if baud_x16_en + end // if rst_clk_tx + end // always + + assign bit_cnt_done = (bit_cnt == 3'd7); + + // Generate the output + always @(posedge clk_tx) + begin + if (rst_clk_tx) + begin + txd_tx <= 1'b1; + end + else + begin + if (baud_x16_en) + begin + if ((state == STOP) || (state == IDLE)) + begin + txd_tx <= 1'b1; + end + else if (state == START) + begin + txd_tx <= 1'b0; + end + else // we are in DATA + begin + txd_tx <= char_fifo_dout[bit_cnt]; + end + end // if baud_x16_en + end // if rst + end // always + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/xadc_temp/xadc_temp.v b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/xadc_temp/xadc_temp.v new file mode 100644 index 0000000..506b45a --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/RTL/xadc_temp/xadc_temp.v @@ -0,0 +1,380 @@ +//***************************************************************************** +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : %version +// \ \ Application : MIG +// / / Filename : mig_7series_v2_4_tempmon.v +// /___/ /\ Date Last Modified : $date$ +// \ \ / \ Date Created : Jul 25 2012 +// \___\/\___\ +// +//Device : 7 Series +//Design Name : DDR3 SDRAM +//Purpose : Monitors chip temperature via the XADC and adjusts the +// stage 2 tap values as appropriate. +//Reference : +//Revision History : +//***************************************************************************** + +`timescale 1 ps / 1 ps + +module xadc_temp # +( + parameter TCQ = 100, // Register delay (sim only) + parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source + parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) + parameter tTEMPSAMPLE = 10000000 // ps (10 us) +) +( + input clk, // Fabric clock + input xadc_clk, + input rst, // System reset + output [11:0] device_temp // Sampled temperature +); + + //*************************************************************************** + // Function cdiv + // Description: + // This function performs ceiling division (divide and round-up) + // Inputs: + // num: integer to be divided + // div: divisor + // Outputs: + // cdiv: result of ceiling division (num/div, rounded up) + //*************************************************************************** + + function integer cdiv (input integer num, input integer div); + begin + // perform division, then add 1 if and only if remainder is non-zero + cdiv = (num/div) + (((num%div)>0) ? 1 : 0); + end + endfunction // cdiv + + //*************************************************************************** + // Function clogb2 + // Description: + // This function performs binary logarithm and rounds up + // Inputs: + // size: integer to perform binary log upon + // Outputs: + // clogb2: result of binary logarithm, rounded up + //*************************************************************************** + + function integer clogb2 (input integer size); + begin + + size = size - 1; + + // increment clogb2 from 1 for each bit in size + for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) + size = size >> 1; + + end + + endfunction // clogb2 + + // Synchronization registers + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; + + // Output register + (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; + + wire [11:0] device_temp_lcl; + reg [3:0] sync_cntr = 4'b0000; + reg device_temp_sync_r4_neq_r3; + + // (* ASYNC_REG = "TRUE" *) reg rst_r1; + // (* ASYNC_REG = "TRUE" *) reg rst_r2; + + // // Synchronization rst to XADC clock domain + // always @(posedge xadc_clk) begin + // rst_r1 <= rst; + // rst_r2 <= rst_r1; + // end + + // Synchronization counter + always @(posedge clk) begin + + device_temp_sync_r1 <= #TCQ device_temp_lcl; + device_temp_sync_r2 <= #TCQ device_temp_sync_r1; + device_temp_sync_r3 <= #TCQ device_temp_sync_r2; + device_temp_sync_r4 <= #TCQ device_temp_sync_r3; + device_temp_sync_r5 <= #TCQ device_temp_sync_r4; + + device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; + + end + + always @(posedge clk) + if(rst || (device_temp_sync_r4_neq_r3)) + sync_cntr <= #TCQ 4'b0000; + else if(~&sync_cntr) + sync_cntr <= #TCQ sync_cntr + 4'b0001; + + always @(posedge clk) + if(&sync_cntr) + device_temp_r <= #TCQ device_temp_sync_r5; + + assign device_temp = device_temp_r; + + generate + + if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature + + assign device_temp_lcl = 0; + + end else begin : xadc_supplied_temperature + + // calculate polling timer width and limit + localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); + localparam nTEMPSAMP_CLKS = nTEMPSAMP; + localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; + localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); + + // Temperature sampler FSM encoding + localparam INIT_IDLE = 2'b00; + localparam REQUEST_READ_TEMP = 2'b01; + localparam WAIT_FOR_READ = 2'b10; + localparam READ = 2'b11; + + // polling timer and tick + reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; + reg sample_timer_en = 1'b0; + reg sample_timer_clr = 1'b0; + reg sample_en = 1'b0; + + // Temperature sampler state + reg [2:0] tempmon_state = INIT_IDLE; + reg [2:0] tempmon_next_state = INIT_IDLE; + + // XADC interfacing + reg xadc_den = 1'b0; + wire xadc_drdy; + wire [15:0] xadc_do; + reg xadc_drdy_r = 1'b0; + reg [15:0] xadc_do_r = 1'b0; + + // Temperature storage + reg [11:0] temperature = 12'b0; + + // Reset sync + (* ASYNC_REG = "TRUE" *) reg rst_r1; + (* ASYNC_REG = "TRUE" *) reg rst_r2; + + // Synchronization rst to XADC clock domain + always @(posedge xadc_clk) begin + rst_r1 <= rst; + rst_r2 <= rst_r1; + end + + // XADC polling interval timer + always @ (posedge xadc_clk) + if(rst_r2 || sample_timer_clr) + sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; + else if(sample_timer_en) + sample_timer <= #TCQ sample_timer + 1'b1; + + // XADC sampler state transition + always @(posedge xadc_clk) + if(rst_r2) + tempmon_state <= #TCQ INIT_IDLE; + else + tempmon_state <= #TCQ tempmon_next_state; + + // Sample enable + always @(posedge xadc_clk) + sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; + + // XADC sampler next state transition + always @(tempmon_state or sample_en or xadc_drdy_r) begin + + tempmon_next_state = tempmon_state; + + case(tempmon_state) + + INIT_IDLE: + if(sample_en) + tempmon_next_state = REQUEST_READ_TEMP; + + REQUEST_READ_TEMP: + tempmon_next_state = WAIT_FOR_READ; + + WAIT_FOR_READ: + if(xadc_drdy_r) + tempmon_next_state = READ; + + READ: + tempmon_next_state = INIT_IDLE; + + default: + tempmon_next_state = INIT_IDLE; + + endcase + + end + + // Sample timer clear + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) + sample_timer_clr <= #TCQ 1'b0; + else if(tempmon_state == REQUEST_READ_TEMP) + sample_timer_clr <= #TCQ 1'b1; + + // Sample timer enable + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) + sample_timer_en <= #TCQ 1'b0; + else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) + sample_timer_en <= #TCQ 1'b1; + + // XADC enable + always @(posedge xadc_clk) + if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) + xadc_den <= #TCQ 1'b0; + else if(tempmon_state == REQUEST_READ_TEMP) + xadc_den <= #TCQ 1'b1; + + // Register XADC outputs + always @(posedge xadc_clk) + if(rst_r2) begin + xadc_drdy_r <= #TCQ 1'b0; + xadc_do_r <= #TCQ 16'b0; + end + else begin + xadc_drdy_r <= #TCQ xadc_drdy; + xadc_do_r <= #TCQ xadc_do; + end + + // Store current read value + always @(posedge xadc_clk) + if(rst_r2) + temperature <= #TCQ 12'b0; + else if(tempmon_state == READ) + temperature <= #TCQ xadc_do_r[15:4]; + + assign device_temp_lcl = temperature; + + // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter + // 7 Series + // Xilinx HDL Libraries Guide, version 14.1 + XADC #( + // INIT_40 - INIT_42: XADC configuration registers + .INIT_40(16'h1000), // config reg 0 + .INIT_41(16'h2fff), // config reg 1 + .INIT_42(16'h0800), // config reg 2 + // INIT_48 - INIT_4F: Sequence Registers + .INIT_48(16'h0101), // Sequencer channel selection + .INIT_49(16'h0000), // Sequencer channel selection + .INIT_4A(16'h0100), // Sequencer Average selection + .INIT_4B(16'h0000), // Sequencer Average selection + .INIT_4C(16'h0000), // Sequencer Bipolar selection + .INIT_4D(16'h0000), // Sequencer Bipolar selection + .INIT_4E(16'h0000), // Sequencer Acq time selection + .INIT_4F(16'h0000), // Sequencer Acq time selection + // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers + .INIT_50(16'hb5ed), // Temp alarm trigger + .INIT_51(16'h57e4), // Vccint upper alarm limit + .INIT_52(16'ha147), // Vccaux upper alarm limit + .INIT_53(16'hca33), // Temp alarm OT upper + .INIT_54(16'ha93a), // Temp alarm reset + .INIT_55(16'h52c6), // Vccint lower alarm limit + .INIT_56(16'h9555), // Vccaux lower alarm limit + .INIT_57(16'hae4e), // Temp alarm OT reset + .INIT_58(16'h5999), // VBRAM upper alarm limit + .INIT_5C(16'h5111), // VBRAM lower alarm limit + // Simulation attributes: Set for proepr simulation behavior + .SIM_DEVICE("7SERIES") // Select target device (values) + ) + XADC_inst ( + // ALARMS: 8-bit (each) output: ALM, OT + .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram + .OT(), // 1-bit output: Over-Temperature alarm + // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports + .DO(xadc_do), // 16-bit output: DRP output data bus + .DRDY(xadc_drdy), // 1-bit output: DRP data ready + // STATUS: 1-bit (each) output: XADC status ports + .BUSY(), // 1-bit output: ADC busy output + .CHANNEL(), // 5-bit output: Channel selection outputs + .EOC(), // 1-bit output: End of Conversion + .EOS(), // 1-bit output: End of Sequence + .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output + .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock + .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred + .MUXADDR(), // 5-bit output: External MUX channel decode + // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] + .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input + .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input + // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs + .CONVST(1'b0), // 1-bit input: Convert start input + .CONVSTCLK(1'b0), // 1-bit input: Convert start input + .RESET(1'b0), // 1-bit input: Active-high reset + // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN + .VN(1'b0), // 1-bit input: N-side analog input + .VP(1'b0), // 1-bit input: P-side analog input + // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports + .DADDR(7'b0), // 7-bit input: DRP address bus + .DCLK(xadc_clk), // 1-bit input: DRP clock + .DEN(xadc_den), // 1-bit input: DRP enable signal + .DI(16'b0), // 16-bit input: DRP input data bus + .DWE(1'b0) // 1-bit input: DRP write enable + ); + + // End of XADC_inst instantiation + + end + + endgenerate + +endmodule diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/debug_nets.ltx b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/debug_nets.ltx new file mode 100644 index 0000000..5bba7d4 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/debug_nets.ltx @@ -0,0 +1,413 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "83333326" + }, + { + "type": "ILA_V3", + "name": "u_ila_0", + "spec": "labtools_ila_v6", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "23e7d65a79bc59f7bc47406c1714dfae", + "pins": [ + { + "name": "probe0", + "id": 0, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "clk_locked", + "isBus": true, + "subnets": [ + { + "name": "clk_locked[1]" + }, + { + "name": "clk_locked[0]" + } + ] + } + ] + }, + { + "name": "probe1", + "id": 1, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 47, + "portIndex": 1, + "nets": [ + { + "name": "tg_rd_data_counts", + "isBus": true, + "subnets": [ + { + "name": "tg_rd_data_counts[47]" + }, + { + "name": "tg_rd_data_counts[46]" + }, + { + "name": "tg_rd_data_counts[45]" + }, + { + "name": "tg_rd_data_counts[44]" + }, + { + "name": "tg_rd_data_counts[43]" + }, + { + "name": "tg_rd_data_counts[42]" + }, + { + "name": "tg_rd_data_counts[41]" + }, + { + "name": "tg_rd_data_counts[40]" + }, + { + "name": "tg_rd_data_counts[39]" + }, + { + "name": "tg_rd_data_counts[38]" + }, + { + "name": "tg_rd_data_counts[37]" + }, + { + "name": "tg_rd_data_counts[36]" + }, + { + "name": "tg_rd_data_counts[35]" + }, + { + "name": "tg_rd_data_counts[34]" + }, + { + "name": "tg_rd_data_counts[33]" + }, + { + "name": "tg_rd_data_counts[32]" + }, + { + "name": "tg_rd_data_counts[31]" + }, + { + "name": "tg_rd_data_counts[30]" + }, + { + "name": "tg_rd_data_counts[29]" + }, + { + "name": "tg_rd_data_counts[28]" + }, + { + "name": "tg_rd_data_counts[27]" + }, + { + "name": "tg_rd_data_counts[26]" + }, + { + "name": "tg_rd_data_counts[25]" + }, + { + "name": "tg_rd_data_counts[24]" + }, + { + "name": "tg_rd_data_counts[23]" + }, + { + "name": "tg_rd_data_counts[22]" + }, + { + "name": "tg_rd_data_counts[21]" + }, + { + "name": "tg_rd_data_counts[20]" + }, + { + "name": "tg_rd_data_counts[19]" + }, + { + "name": "tg_rd_data_counts[18]" + }, + { + "name": "tg_rd_data_counts[17]" + }, + { + "name": "tg_rd_data_counts[16]" + }, + { + "name": "tg_rd_data_counts[15]" + }, + { + "name": "tg_rd_data_counts[14]" + }, + { + "name": "tg_rd_data_counts[13]" + }, + { + "name": "tg_rd_data_counts[12]" + }, + { + "name": "tg_rd_data_counts[11]" + }, + { + "name": "tg_rd_data_counts[10]" + }, + { + "name": "tg_rd_data_counts[9]" + }, + { + "name": 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+:1072200020000000200000002000000020000000DE +:1072300020000000200000002000000020000000CE +:1072400020000000200000002000000020000000BE +:1072500020000000200000002000000020000000AE +:10726000200000002000000020000000200000009E +:10727000200000002000000020000000200000008E +:0C728000200000002000000020000000A2 +:00000001FF diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/top.prm b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/top.prm new file mode 100644 index 0000000..995a745 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/Result/top.prm @@ -0,0 +1,11 @@ +=================================== +Configuration Memory information +=================================== +File Format BIN +Interface SPIX4 +Size 128M +Start Address 0x00000000 +End Address 0x07FFFFFF + +Addr1 Addr2 Date File(s) +0x00000000 0x0021728B Feb 5 19:43:24 2025 J:/work/HY/Xilinx/A704/V1.0/PRJ/TCL/../Project/top.runs/impl_1/top.bit diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/bitgen_compress.tcl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/bitgen_compress.tcl new file mode 100644 index 0000000..642cea7 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/bitgen_compress.tcl @@ -0,0 +1 @@ +set_property BITSTREAM.GENERAL.COMPRESS TRUE [get_designs] diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/write_cfgmem.tcl b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/write_cfgmem.tcl new file mode 100644 index 0000000..783271e --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/TCL/write_cfgmem.tcl @@ -0,0 +1,13 @@ + +set tcl_Dir [file dirname [info script]] + +set pj_name top +set top_name top +set mcs_width SPIx4 +set flash_size 128 + +write_cfgmem -format mcs -interface $mcs_width -size $flash_size -loadbit "up 0x0 $tcl_Dir/../Project/${pj_name}.runs/impl_1/${top_name}.bit" -force -file $tcl_Dir/../Result/${top_name}.mcs +write_cfgmem -format bin -interface $mcs_width -size $flash_size -loadbit "up 0x0 $tcl_Dir/../Project/${pj_name}.runs/impl_1/${top_name}.bit" -force -file $tcl_Dir/../Result/${top_name}.bin + +file copy -force $tcl_Dir/../Project/${pj_name}.runs/impl_1/${top_name}.bit $tcl_Dir/../Result/ + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/debug.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/debug.xdc new file mode 100644 index 0000000..cdcd2b8 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/debug.xdc @@ -0,0 +1,35 @@ + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list UU3/u_ddr3/u_ddr3_mig/u_ddr3_infrastructure/CLK]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 2 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {clk_locked[0]} {clk_locked[1]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 48 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {tg_rd_data_counts[0]} {tg_rd_data_counts[1]} {tg_rd_data_counts[2]} {tg_rd_data_counts[3]} {tg_rd_data_counts[4]} {tg_rd_data_counts[5]} {tg_rd_data_counts[6]} {tg_rd_data_counts[7]} {tg_rd_data_counts[8]} {tg_rd_data_counts[9]} {tg_rd_data_counts[10]} {tg_rd_data_counts[11]} {tg_rd_data_counts[12]} {tg_rd_data_counts[13]} {tg_rd_data_counts[14]} {tg_rd_data_counts[15]} {tg_rd_data_counts[16]} {tg_rd_data_counts[17]} {tg_rd_data_counts[18]} {tg_rd_data_counts[19]} {tg_rd_data_counts[20]} {tg_rd_data_counts[21]} {tg_rd_data_counts[22]} {tg_rd_data_counts[23]} {tg_rd_data_counts[24]} {tg_rd_data_counts[25]} {tg_rd_data_counts[26]} {tg_rd_data_counts[27]} {tg_rd_data_counts[28]} {tg_rd_data_counts[29]} {tg_rd_data_counts[30]} {tg_rd_data_counts[31]} {tg_rd_data_counts[32]} {tg_rd_data_counts[33]} {tg_rd_data_counts[34]} {tg_rd_data_counts[35]} {tg_rd_data_counts[36]} {tg_rd_data_counts[37]} {tg_rd_data_counts[38]} {tg_rd_data_counts[39]} {tg_rd_data_counts[40]} {tg_rd_data_counts[41]} {tg_rd_data_counts[42]} {tg_rd_data_counts[43]} {tg_rd_data_counts[44]} {tg_rd_data_counts[45]} {tg_rd_data_counts[46]} {tg_rd_data_counts[47]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 48 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {tg_wr_data_counts[0]} {tg_wr_data_counts[1]} {tg_wr_data_counts[2]} {tg_wr_data_counts[3]} {tg_wr_data_counts[4]} {tg_wr_data_counts[5]} {tg_wr_data_counts[6]} {tg_wr_data_counts[7]} {tg_wr_data_counts[8]} {tg_wr_data_counts[9]} {tg_wr_data_counts[10]} {tg_wr_data_counts[11]} {tg_wr_data_counts[12]} {tg_wr_data_counts[13]} {tg_wr_data_counts[14]} {tg_wr_data_counts[15]} {tg_wr_data_counts[16]} {tg_wr_data_counts[17]} {tg_wr_data_counts[18]} {tg_wr_data_counts[19]} {tg_wr_data_counts[20]} {tg_wr_data_counts[21]} {tg_wr_data_counts[22]} {tg_wr_data_counts[23]} {tg_wr_data_counts[24]} {tg_wr_data_counts[25]} {tg_wr_data_counts[26]} {tg_wr_data_counts[27]} {tg_wr_data_counts[28]} {tg_wr_data_counts[29]} {tg_wr_data_counts[30]} {tg_wr_data_counts[31]} {tg_wr_data_counts[32]} {tg_wr_data_counts[33]} {tg_wr_data_counts[34]} {tg_wr_data_counts[35]} {tg_wr_data_counts[36]} {tg_wr_data_counts[37]} {tg_wr_data_counts[38]} {tg_wr_data_counts[39]} {tg_wr_data_counts[40]} {tg_wr_data_counts[41]} {tg_wr_data_counts[42]} {tg_wr_data_counts[43]} {tg_wr_data_counts[44]} {tg_wr_data_counts[45]} {tg_wr_data_counts[46]} {tg_wr_data_counts[47]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 1 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list init_calib_complete]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 1 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list tg_compare_error]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets u_ila_0_CLK] diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/io_test.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/io_test.xdc new file mode 100644 index 0000000..0d53e8f --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/io_test.xdc @@ -0,0 +1,164 @@ + +set_property PACKAGE_PIN J21 [get_ports {o_sig[0]}] +set_property PACKAGE_PIN G20 [get_ports {o_sig[1]}] +set_property PACKAGE_PIN H19 [get_ports {o_sig[2]}] +set_property PACKAGE_PIN H18 [get_ports {o_sig[3]}] +set_property PACKAGE_PIN G18 [get_ports {o_sig[4]}] +set_property PACKAGE_PIN G16 [get_ports {o_sig[5]}] +set_property PACKAGE_PIN H15 [get_ports {o_sig[6]}] +set_property PACKAGE_PIN H14 [get_ports {o_sig[7]}] +set_property PACKAGE_PIN G13 [get_ports {o_sig[8]}] +set_property PACKAGE_PIN G22 [get_ports {o_sig[9]}] +set_property PACKAGE_PIN D21 [get_ports {o_sig[10]}] +set_property PACKAGE_PIN D22 [get_ports {o_sig[11]}] +set_property PACKAGE_PIN F20 [get_ports {o_sig[12]}] +set_property PACKAGE_PIN C20 [get_ports {o_sig[13]}] +set_property PACKAGE_PIN B22 [get_ports {o_sig[14]}] +set_property PACKAGE_PIN AA5 [get_ports {o_sig[15]}] +set_property PACKAGE_PIN E18 [get_ports {o_sig[16]}] +set_property PACKAGE_PIN A21 [get_ports {o_sig[17]}] +set_property PACKAGE_PIN C17 [get_ports {o_sig[18]}] +set_property PACKAGE_PIN D16 [get_ports {o_sig[19]}] +set_property PACKAGE_PIN B18 [get_ports {o_sig[20]}] +set_property PACKAGE_PIN C15 [get_ports {o_sig[21]}] +set_property PACKAGE_PIN E14 [get_ports {o_sig[22]}] +set_property PACKAGE_PIN A20 [get_ports {o_sig[23]}] +set_property PACKAGE_PIN E17 [get_ports {o_sig[24]}] +set_property PACKAGE_PIN B16 [get_ports {o_sig[25]}] +set_property PACKAGE_PIN F14 [get_ports {o_sig[26]}] +set_property PACKAGE_PIN B13 [get_ports {o_sig[27]}] +set_property PACKAGE_PIN D15 [get_ports {o_sig[28]}] +set_property PACKAGE_PIN A19 [get_ports {o_sig[29]}] +set_property PACKAGE_PIN A16 [get_ports {o_sig[30]}] +set_property PACKAGE_PIN A14 [get_ports {o_sig[31]}] +set_property PACKAGE_PIN J20 [get_ports {o_sig[32]}] +set_property PACKAGE_PIN H20 [get_ports {o_sig[33]}] +set_property PACKAGE_PIN J19 [get_ports {o_sig[34]}] +set_property PACKAGE_PIN H17 [get_ports {o_sig[35]}] +set_property PACKAGE_PIN G17 [get_ports {o_sig[36]}] +set_property PACKAGE_PIN G15 [get_ports {o_sig[37]}] +set_property PACKAGE_PIN J15 [get_ports {o_sig[38]}] +set_property PACKAGE_PIN J14 [get_ports {o_sig[39]}] +set_property PACKAGE_PIN H13 [get_ports {o_sig[40]}] +set_property PACKAGE_PIN G21 [get_ports {o_sig[41]}] +set_property PACKAGE_PIN E21 [get_ports {o_sig[42]}] +set_property PACKAGE_PIN E22 [get_ports {o_sig[43]}] +set_property PACKAGE_PIN F19 [get_ports {o_sig[44]}] +set_property PACKAGE_PIN D20 [get_ports {o_sig[45]}] +set_property PACKAGE_PIN C22 [get_ports {o_sig[46]}] +set_property PACKAGE_PIN E19 [get_ports {o_sig[47]}] +set_property PACKAGE_PIN F18 [get_ports {o_sig[48]}] +set_property PACKAGE_PIN B21 [get_ports {o_sig[49]}] +set_property PACKAGE_PIN D17 [get_ports {o_sig[50]}] +set_property PACKAGE_PIN E16 [get_ports {o_sig[51]}] +set_property PACKAGE_PIN B17 [get_ports {o_sig[52]}] +set_property PACKAGE_PIN C14 [get_ports {o_sig[53]}] +set_property PACKAGE_PIN E13 [get_ports {o_sig[54]}] +set_property PACKAGE_PIN B20 [get_ports {o_sig[55]}] +set_property PACKAGE_PIN F16 [get_ports {o_sig[56]}] +set_property PACKAGE_PIN B15 [get_ports {o_sig[57]}] +set_property PACKAGE_PIN F13 [get_ports {o_sig[58]}] +set_property PACKAGE_PIN C13 [get_ports {o_sig[59]}] +set_property PACKAGE_PIN D14 [get_ports {o_sig[60]}] +set_property PACKAGE_PIN A18 [get_ports {o_sig[61]}] +set_property PACKAGE_PIN A15 [get_ports {o_sig[62]}] +set_property PACKAGE_PIN A13 [get_ports {o_sig[63]}] +set_property PACKAGE_PIN M22 [get_ports {o_sig[64]}] +set_property PACKAGE_PIN M20 [get_ports {o_sig[65]}] +set_property PACKAGE_PIN L20 [get_ports {o_sig[66]}] +set_property PACKAGE_PIN N19 [get_ports {o_sig[67]}] +set_property PACKAGE_PIN K19 [get_ports {o_sig[68]}] +set_property PACKAGE_PIN L18 [get_ports {o_sig[69]}] +set_property PACKAGE_PIN M16 [get_ports {o_sig[70]}] +set_property PACKAGE_PIN W22 [get_ports {o_sig[71]}] +set_property PACKAGE_PIN V20 [get_ports {o_sig[72]}] +set_property PACKAGE_PIN U21 [get_ports {o_sig[73]}] +set_property PACKAGE_PIN Y22 [get_ports {o_sig[74]}] +set_property PACKAGE_PIN AA21 [get_ports {o_sig[75]}] +set_property PACKAGE_PIN R19 [get_ports {o_sig[76]}] +set_property PACKAGE_PIN AB22 [get_ports {o_sig[77]}] +set_property PACKAGE_PIN W20 [get_ports {o_sig[78]}] +set_property PACKAGE_PIN AB20 [get_ports {o_sig[79]}] +set_property PACKAGE_PIN T18 [get_ports {o_sig[80]}] +set_property PACKAGE_PIN Y19 [get_ports {o_sig[81]}] +set_property PACKAGE_PIN P17 [get_ports {o_sig[82]}] +set_property PACKAGE_PIN R17 [get_ports {o_sig[83]}] +set_property PACKAGE_PIN V19 [get_ports {o_sig[84]}] +set_property PACKAGE_PIN R16 [get_ports {o_sig[85]}] +set_property PACKAGE_PIN R14 [get_ports {o_sig[86]}] +set_property PACKAGE_PIN W17 [get_ports {o_sig[87]}] +set_property PACKAGE_PIN N14 [get_ports {o_sig[88]}] +set_property PACKAGE_PIN U18 [get_ports {o_sig[89]}] +set_property PACKAGE_PIN AB18 [get_ports {o_sig[90]}] +set_property PACKAGE_PIN V8 [get_ports {o_sig[91]}] +set_property PACKAGE_PIN Y9 [get_ports {o_sig[92]}] +set_property PACKAGE_PIN Y7 [get_ports {o_sig[93]}] +set_property PACKAGE_PIN AB8 [get_ports {o_sig[94]}] +set_property PACKAGE_PIN AB6 [get_ports {o_sig[95]}] +set_property PACKAGE_PIN N22 [get_ports {o_sig[96]}] +set_property PACKAGE_PIN N20 [get_ports {o_sig[97]}] +set_property PACKAGE_PIN L19 [get_ports {o_sig[98]}] +set_property PACKAGE_PIN N18 [get_ports {o_sig[99]}] +set_property PACKAGE_PIN K18 [get_ports {o_sig[100]}] +set_property PACKAGE_PIN M18 [get_ports {o_sig[101]}] +set_property PACKAGE_PIN M15 [get_ports {o_sig[102]}] +set_property PACKAGE_PIN W21 [get_ports {o_sig[103]}] +set_property PACKAGE_PIN U20 [get_ports {o_sig[104]}] +set_property PACKAGE_PIN T21 [get_ports {o_sig[105]}] +set_property PACKAGE_PIN Y21 [get_ports {o_sig[106]}] +set_property PACKAGE_PIN AA20 [get_ports {o_sig[107]}] +set_property PACKAGE_PIN P19 [get_ports {o_sig[108]}] +set_property PACKAGE_PIN AB21 [get_ports {o_sig[109]}] +set_property PACKAGE_PIN W19 [get_ports {o_sig[110]}] +set_property PACKAGE_PIN AA19 [get_ports {o_sig[111]}] +set_property PACKAGE_PIN R18 [get_ports {o_sig[112]}] +set_property PACKAGE_PIN Y18 [get_ports {o_sig[113]}] +set_property PACKAGE_PIN N17 [get_ports {o_sig[114]}] +set_property PACKAGE_PIN P16 [get_ports {o_sig[115]}] +set_property PACKAGE_PIN V18 [get_ports {o_sig[116]}] +set_property PACKAGE_PIN P15 [get_ports {o_sig[117]}] +set_property PACKAGE_PIN P14 [get_ports {o_sig[118]}] +set_property PACKAGE_PIN V17 [get_ports {o_sig[119]}] +set_property PACKAGE_PIN N13 [get_ports {o_sig[120]}] +set_property PACKAGE_PIN U17 [get_ports {o_sig[121]}] +set_property PACKAGE_PIN AA18 [get_ports {o_sig[122]}] +set_property PACKAGE_PIN V9 [get_ports {o_sig[123]}] +set_property PACKAGE_PIN W9 [get_ports {o_sig[124]}] +set_property PACKAGE_PIN Y8 [get_ports {o_sig[125]}] +set_property PACKAGE_PIN AA8 [get_ports {o_sig[126]}] +set_property PACKAGE_PIN AB7 [get_ports {o_sig[127]}] +set_property PACKAGE_PIN W7 [get_ports {o_sig[128]}] +set_property PACKAGE_PIN AB5 [get_ports {o_sig[129]}] +set_property PACKAGE_PIN AA6 [get_ports {o_sig[130]}] +set_property PACKAGE_PIN W5 [get_ports {o_sig[131]}] +set_property PACKAGE_PIN V5 [get_ports {o_sig[132]}] +set_property PACKAGE_PIN AB2 [get_ports {o_sig[133]}] +set_property PACKAGE_PIN AA4 [get_ports {o_sig[134]}] +set_property PACKAGE_PIN AA3 [get_ports {o_sig[135]}] +set_property PACKAGE_PIN Y1 [get_ports {o_sig[136]}] +set_property PACKAGE_PIN AB1 [get_ports {o_sig[137]}] +set_property PACKAGE_PIN V3 [get_ports {o_sig[138]}] +set_property PACKAGE_PIN W4 [get_ports {o_sig[139]}] +set_property PACKAGE_PIN Y2 [get_ports {o_sig[140]}] +set_property PACKAGE_PIN T6 [get_ports {o_sig[141]}] +set_property PACKAGE_PIN U5 [get_ports {o_sig[142]}] +set_property PACKAGE_PIN V2 [get_ports {o_sig[143]}] +set_property PACKAGE_PIN R2 [get_ports {o_sig[144]}] +set_property PACKAGE_PIN R3 [get_ports {o_sig[145]}] +set_property PACKAGE_PIN U2 [get_ports {o_sig[146]}] +set_property PACKAGE_PIN T5 [get_ports {o_sig[147]}] +set_property PACKAGE_PIN R6 [get_ports {o_sig[148]}] +set_property PACKAGE_PIN W2 [get_ports {o_sig[149]}] +set_property PACKAGE_PIN V4 [get_ports {o_sig[150]}] +set_property PACKAGE_PIN U3 [get_ports {o_sig[151]}] +set_property PACKAGE_PIN AA1 [get_ports {o_sig[152]}] +set_property PACKAGE_PIN W1 [get_ports {o_sig[153]}] +set_property PACKAGE_PIN Y3 [get_ports {o_sig[154]}] +set_property PACKAGE_PIN Y4 [get_ports {o_sig[155]}] +set_property PACKAGE_PIN AB3 [get_ports {o_sig[156]}] +set_property PACKAGE_PIN U6 [get_ports {o_sig[157]}] +set_property PACKAGE_PIN W6 [get_ports {o_sig[158]}] +set_property PACKAGE_PIN Y6 [get_ports {o_sig[159]}] +set_property PACKAGE_PIN V7 [get_ports {o_sig[160]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {o_sig[*]}] diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/pin.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/pin.xdc new file mode 100644 index 0000000..260b4c0 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/pin.xdc @@ -0,0 +1,32 @@ + +################################################################################################# +## PIN +################################################################################################# +set_property PACKAGE_PIN R4 [get_ports sys_clk] +set_property PACKAGE_PIN T1 [get_ports {led[1]}] +set_property PACKAGE_PIN U1 [get_ports {led[0]}] +set_property PACKAGE_PIN P20 [get_ports rxd] +set_property PACKAGE_PIN T20 [get_ports txd] +set_property PACKAGE_PIN T3 [get_ports key] +################################################################################################# +## IOSTANDARD +################################################################################################# +set_property IOSTANDARD LVCMOS33 [get_ports sys_clk] +set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports rxd] +set_property IOSTANDARD LVCMOS33 [get_ports txd] +set_property IOSTANDARD LVCMOS33 [get_ports key] +################################################################################################# +## SLEW +################################################################################################# + + +################################################################################################# +# +################################################################################################# +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design] + + + diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/timing.xdc b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/timing.xdc new file mode 100644 index 0000000..b1ba674 --- /dev/null +++ b/fpga/rando_a7/XC7A35T Artix7 core board/Reference program/A704_XC7A35T_VVD2020.2_V1.0.7/XDC/timing.xdc @@ -0,0 +1,16 @@ + +########################################################################################## +## Period +########################################################################################## +#create_clock -period 20.000 -name T_sys_clk -waveform {0.000 10.000} [get_ports sys_clk] + + + +set_max_delay -datapath_only -from [get_pins UU7/io_sig_reg/C] -to * 20.0 +set_max_delay -datapath_only -from [get_pins UU2/rst_n_temp_reg/C] -to * 10.0 + + +set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins UU1/U0_sys_clk/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins UU1/U0_sys_clk/inst/mmcm_adv_inst/CLKOUT1]] 10.0 +set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins UU1/U0_sys_clk/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins UU1/U0_sys_clk/inst/mmcm_adv_inst/CLKOUT0]] 10.0 +set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins UU1/U0_sys_clk/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins UU3/u_ddr3/u_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] 10.0 +set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins UU3/u_ddr3/u_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] -to [get_clocks -of_objects [get_pins UU1/U0_sys_clk/inst/mmcm_adv_inst/CLKOUT1]] 10.0 diff --git a/fpga/rando_a7/XC7A35T Artix7 core board/SCH/XILINX ARTIX-7 FPGA A704 V10 Schematics.pdf b/fpga/rando_a7/XC7A35T Artix7 core board/SCH/XILINX ARTIX-7 FPGA A704 V10 Schematics.pdf new file mode 100644 index 0000000..abc8e56 Binary files /dev/null and b/fpga/rando_a7/XC7A35T Artix7 core board/SCH/XILINX ARTIX-7 FPGA A704 V10 Schematics.pdf differ -- cgit v1.2.3