From d27f19b99a155bc9a758776426e16c39dfec1ff4 Mon Sep 17 00:00:00 2001 From: James McKenzie Date: Thu, 1 May 2025 00:01:51 +0100 Subject: tidy up smh-ac415 --- .../examples/05_rs232/rs232/doc/rs232.vsdx | Bin 547632 -> 0 bytes .../examples/05_rs232/rs232/quartus_prj/rs232.qpf | 30 - .../examples/05_rs232/rs232/quartus_prj/rs232.qsf | 92 - .../examples/05_rs232/rs232/quartus_prj/rs232.qws | Bin 1327 -> 0 bytes .../quartus_prj/rs232_assignment_defaults.qdf | 805 ------ .../quartus_prj/simulation/modelsim/rs232.sft | 6 - .../rs232/quartus_prj/simulation/modelsim/rs232.vo | 2836 -------------------- .../simulation/modelsim/rs232_8_1200mv_0c_slow.vo | 2836 -------------------- .../modelsim/rs232_8_1200mv_0c_v_slow.sdo | 2275 ---------------- .../simulation/modelsim/rs232_8_1200mv_85c_slow.vo | 2836 -------------------- .../modelsim/rs232_8_1200mv_85c_v_slow.sdo | 2275 ---------------- .../modelsim/rs232_min_1200mv_0c_fast.vo | 2836 -------------------- .../modelsim/rs232_min_1200mv_0c_v_fast.sdo | 2275 ---------------- .../simulation/modelsim/rs232_modelsim.xrf | 157 -- .../quartus_prj/simulation/modelsim/rs232_v.sdo | 2275 ---------------- .../examples/05_rs232/rs232/rtl/rs232.v | 75 - .../examples/05_rs232/rs232/rtl/uart_rx.v | 154 -- .../examples/05_rs232/rs232/rtl/uart_tx.v | 104 - .../examples/05_rs232/rs232/sim/tb_rs232.v | 98 - .../examples/05_rs232/rs232/sim/tb_uart_rx.v | 103 - .../examples/05_rs232/rs232/sim/tb_uart_tx.v | 117 - ...56\236\351\252\214\347\216\260\350\261\241.txt" | 2 - 22 files changed, 22187 deletions(-) delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/doc/rs232.vsdx delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qpf delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qsf delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qws delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232_assignment_defaults.qdf delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.sft delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.vo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_slow.vo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_v_slow.sdo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_slow.vo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_v_slow.sdo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_fast.vo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_v_fast.sdo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_modelsim.xrf delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_v.sdo delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/rs232.v delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_rx.v delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_tx.v delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_rs232.v delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_rx.v delete mode 100644 fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_tx.v delete mode 100644 "fpga/smh-ac415-fpga/examples/05_rs232/\345\256\236\351\252\214\347\216\260\350\261\241.txt" (limited to 'fpga/smh-ac415-fpga/examples/05_rs232') diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/doc/rs232.vsdx b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/doc/rs232.vsdx deleted file mode 100644 index 195deeb..0000000 Binary files a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/doc/rs232.vsdx and /dev/null differ diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qpf b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qpf deleted file mode 100644 index 6f228f9..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 17:20:04 March 05, 2020 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.0" -DATE = "17:20:04 March 05, 2020" - -# Revisions - -PROJECT_REVISION = "rs232" diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qsf b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qsf deleted file mode 100644 index 6d675f3..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qsf +++ /dev/null @@ -1,92 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 17:20:04 March 05, 2020 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# rs232_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name DEVICE EP4CE15F23C8 -set_global_assignment -name TOP_LEVEL_ENTITY rs232 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:20:04 MARCH 05, 2020" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation -set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_rs232 -section_id eda_simulation -set_global_assignment -name EDA_TEST_BENCH_NAME tb_rs232 -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_rs232 -set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_rs232 -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_rs232 -section_id tb_rs232 -set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_rs232.v -section_id tb_rs232 -set_global_assignment -name EDA_TEST_BENCH_NAME tb_uart_rx -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_uart_rx -set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_uart_rx -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_uart_rx -section_id tb_uart_rx -set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_uart_rx.v -section_id tb_uart_rx -set_global_assignment -name EDA_TEST_BENCH_NAME tb_uart_tx -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_uart_tx -set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_uart_tx -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_uart_tx -section_id tb_uart_tx -set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_uart_tx.v -section_id tb_uart_tx - - -set_location_assignment PIN_T22 -to sys_clk -set_location_assignment PIN_U20 -to sys_rst_n - -set_location_assignment PIN_V1 -to rx -set_location_assignment PIN_U1 -to tx - -#set_location_assignment PIN_N6 -to rx -#set_location_assignment PIN_N5 -to tx - -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" -set_global_assignment -name VERILOG_FILE ../sim/tb_uart_tx.v -set_global_assignment -name VERILOG_FILE ../sim/tb_uart_rx.v -set_global_assignment -name VERILOG_FILE ../sim/tb_rs232.v -set_global_assignment -name VERILOG_FILE ../rtl/uart_tx.v -set_global_assignment -name VERILOG_FILE ../rtl/uart_rx.v -set_global_assignment -name VERILOG_FILE ../rtl/rs232.v -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qws b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qws deleted file mode 100644 index 55fe5d0..0000000 Binary files a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qws and /dev/null differ diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232_assignment_defaults.qdf b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232_assignment_defaults.qdf deleted file mode 100644 index 3d59196..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232_assignment_defaults.qdf +++ /dev/null @@ -1,805 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 02:59:42 June 02, 2023 -# -# -------------------------------------------------------------------------- # -# -# Note: -# -# 1) Do not modify this file. This file was generated -# automatically by the Quartus II software and is used -# to preserve global assignments across Quartus II versions. -# -# -------------------------------------------------------------------------- # - -set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On -set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off -set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off -set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db -set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off -set_global_assignment -name SMART_RECOMPILE Off -set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off -set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off -set_global_assignment -name HC_OUTPUT_DIR hc_output -set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off -set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off -set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On -set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off -set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" -set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On -set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On -set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off -set_global_assignment -name REVISION_TYPE Base -set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" -set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On -set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On -set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On -set_global_assignment -name DO_COMBINED_ANALYSIS Off -set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off -set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On -set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II" -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix -set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" -set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix -set_global_assignment -name MUX_RESTRUCTURE Auto -set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off -set_global_assignment -name ENABLE_IP_DEBUG Off -set_global_assignment -name SAVE_DISK_SPACE On -set_global_assignment -name DISABLE_OCP_HW_EVAL Off -set_global_assignment -name DEVICE_FILTER_PACKAGE Any -set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name FAMILY "Cyclone IV GX" -set_global_assignment -name TRUE_WYSIWYG_FLOW Off -set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off -set_global_assignment -name STATE_MACHINE_PROCESSING Auto -set_global_assignment -name SAFE_STATE_MACHINE Off -set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On -set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On -set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off -set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 -set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 -set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On -set_global_assignment -name PARALLEL_SYNTHESIS On -set_global_assignment -name DSP_BLOCK_BALANCING Auto -set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" -set_global_assignment -name NOT_GATE_PUSH_BACK On -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On -set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off -set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On -set_global_assignment -name IGNORE_CARRY_BUFFERS Off -set_global_assignment -name IGNORE_CASCADE_BUFFERS Off -set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off -set_global_assignment -name IGNORE_LCELL_BUFFERS Off -set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO -set_global_assignment -name IGNORE_SOFT_BUFFERS On -set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off -set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off -set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On -set_global_assignment -name AUTO_GLOBAL_OE_MAX On -set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off -set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut -set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area -set_global_assignment -name ALLOW_XOR_GATE_USAGE On -set_global_assignment -name AUTO_LCELL_INSERTION On -set_global_assignment -name CARRY_CHAIN_LENGTH 48 -set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 -set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 -set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 -set_global_assignment -name CASCADE_CHAIN_LENGTH 2 -set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 -set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 -set_global_assignment -name AUTO_CARRY_CHAINS On -set_global_assignment -name AUTO_CASCADE_CHAINS On -set_global_assignment -name AUTO_PARALLEL_EXPANDERS On -set_global_assignment -name AUTO_OPEN_DRAIN_PINS On -set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off -set_global_assignment -name AUTO_ROM_RECOGNITION On -set_global_assignment -name AUTO_RAM_RECOGNITION On -set_global_assignment -name AUTO_DSP_RECOGNITION On -set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto -set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On -set_global_assignment -name STRICT_RAM_RECOGNITION Off -set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On -set_global_assignment -name FORCE_SYNCH_CLEAR Off -set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off -set_global_assignment -name AUTO_RESOURCE_SHARING Off -set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off -set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off -set_global_assignment -name MAX7000_FANIN_PER_CELL 100 -set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On -set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" -set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" -set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off -set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria VI" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix VI" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" -set_global_assignment -name REPORT_PARAMETER_SETTINGS On -set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On -set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On -set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix VI" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria VI" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II" -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix -set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" -set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" -set_global_assignment -name HDL_MESSAGE_LEVEL Level2 -set_global_assignment -name USE_HIGH_SPEED_ADDER Auto -set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 -set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 -set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 -set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On -set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off -set_global_assignment -name BLOCK_DESIGN_NAMING Auto -set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off -set_global_assignment -name SYNTHESIS_EFFORT Auto -set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On -set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off -set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium -set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria VI" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix VI" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix -set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" -set_global_assignment -name MAX_LABS "-1 (Unlimited)" -set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On -set_global_assignment -name SYNTHESIS_SEED 1 -set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" -set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Off -set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off -set_global_assignment -name AUTO_MERGE_PLLS On -set_global_assignment -name IGNORE_MODE_FOR_MERGE Off -set_global_assignment -name TXPMA_SLEW_RATE Low -set_global_assignment -name ADCE_ENABLED Auto -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 -set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 -set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off -set_global_assignment -name DEVICE AUTO -set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off -set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off -set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On -set_global_assignment -name ENABLE_NCEO_OUTPUT Off -set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name STRATIXIII_UPDATE_MODE Standard -set_global_assignment -name STRATIX_UPDATE_MODE Standard -set_global_assignment -name CVP_MODE Off -set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" -set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" -set_global_assignment -name USER_START_UP_CLOCK Off -set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC -set_global_assignment -name ENABLE_VREFA_PIN Off -set_global_assignment -name ENABLE_VREFB_PIN Off -set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off -set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off -set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" -set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off -set_global_assignment -name INIT_DONE_OPEN_DRAIN On -set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" -set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" -set_global_assignment -name CRC_ERROR_CHECKING Off -set_global_assignment -name INTERNAL_SCRUBBING Off -set_global_assignment -name PR_ERROR_OPEN_DRAIN On -set_global_assignment -name PR_READY_OPEN_DRAIN On -set_global_assignment -name ENABLE_CVP_CONFDONE Off -set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria VI" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix VI" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix -set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix VI" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Arria VI" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix -set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto -set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care -set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 -set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" -set_global_assignment -name OPTIMIZE_SSN Off -set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" -set_global_assignment -name ECO_OPTIMIZE_TIMING Off -set_global_assignment -name ECO_REGENERATE_REPORT Off -set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal -set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off -set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically -set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically -set_global_assignment -name SEED 1 -set_global_assignment -name SLOW_SLEW_RATE Off -set_global_assignment -name PCI_IO Off -set_global_assignment -name TURBO_BIT On -set_global_assignment -name WEAK_PULL_UP_RESISTOR Off -set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off -set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off -set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO -set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO -set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto -set_global_assignment -name AUTO_PACKED_REGISTERS Off -set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO -set_global_assignment -name NORMAL_LCELL_INSERT On -set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On -set_global_assignment -name AUTO_DELAY_CHAINS On -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off -set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off -set_global_assignment -name AUTO_TURBO_BIT ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off -set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On -set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off -set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off -set_global_assignment -name FITTER_EFFORT "Auto Fit" -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal -set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO -set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO -set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off -set_global_assignment -name AUTO_GLOBAL_CLOCK On -set_global_assignment -name AUTO_GLOBAL_OE On -set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic -set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off -set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off -set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off -set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off -set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off -set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" -set_global_assignment -name ENABLE_HOLD_BACK_OFF On -set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto -set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off -set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix VI" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria VI" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" -set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria VI" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix VI" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" -set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" -set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off -set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On -set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off -set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off -set_global_assignment -name PR_DONE_OPEN_DRAIN On -set_global_assignment -name NCEO_OPEN_DRAIN On -set_global_assignment -name ENABLE_CRC_ERROR_PIN Off -set_global_assignment -name ENABLE_PR_PINS Off -set_global_assignment -name PR_PINS_OPEN_DRAIN Off -set_global_assignment -name CLAMPING_DIODE Off -set_global_assignment -name TRI_STATE_SPI_PINS Off -set_global_assignment -name UNUSED_TSD_PINS_GND Off -set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off -set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off -set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM -set_global_assignment -name EDA_SIMULATION_TOOL "" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "" -set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On -set_global_assignment -name COMPRESSION_MODE Off -set_global_assignment -name CLOCK_SOURCE Internal -set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" -set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 -set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off -set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On -set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF -set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F -set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name USE_CHECKSUM_AS_USERCODE On -set_global_assignment -name SECURITY_BIT Off -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" -set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" -set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix -set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto -set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto -set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto -set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto -set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF -set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off -set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On -set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off -set_global_assignment -name GENERATE_TTF_FILE Off -set_global_assignment -name GENERATE_RBF_FILE Off -set_global_assignment -name GENERATE_HEX_FILE Off -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 -set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" -set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off -set_global_assignment -name AUTO_RESTART_CONFIGURATION On -set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off -set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On -set_global_assignment -name ENABLE_OCT_DONE Off -set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF -set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off -set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off -set_global_assignment -name START_TIME 0ns -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On -set_global_assignment -name SETUP_HOLD_DETECTION Off -set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -set_global_assignment -name CHECK_OUTPUTS Off -set_global_assignment -name SIMULATION_COVERAGE On -set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On -set_global_assignment -name GLITCH_DETECTION Off -set_global_assignment -name GLITCH_INTERVAL 1ns -set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off -set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On -set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off -set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On -set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE -set_global_assignment -name SIMULATION_NETLIST_VIEWER Off -set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT -set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off -set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO -set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO -set_global_assignment -name DRC_TOP_FANOUT 50 -set_global_assignment -name DRC_FANOUT_EXCEEDING 30 -set_global_assignment -name DRC_GATED_CLOCK_FEED 30 -set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY -set_global_assignment -name ENABLE_DRC_SETTINGS Off -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 -set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 -set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 -set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 -set_global_assignment -name MERGE_HEX_FILE Off -set_global_assignment -name GENERATE_SVF_FILE Off -set_global_assignment -name GENERATE_ISC_FILE Off -set_global_assignment -name GENERATE_JAM_FILE Off -set_global_assignment -name GENERATE_JBC_FILE Off -set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off -set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off -set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On -set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off -set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" -set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off -set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off -set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% -set_global_assignment -name POWER_USE_PVA On -set_global_assignment -name POWER_USE_INPUT_FILE "No File" -set_global_assignment -name POWER_USE_INPUT_FILES Off -set_global_assignment -name POWER_VCD_FILTER_GLITCHES On -set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off -set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off -set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL -set_global_assignment -name POWER_AUTO_COMPUTE_TJ On -set_global_assignment -name POWER_TJ_VALUE 25 -set_global_assignment -name POWER_USE_TA_VALUE 25 -set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off -set_global_assignment -name POWER_BOARD_TEMPERATURE 25 -set_global_assignment -name POWER_HPS_ENABLE Off -set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 -set_global_assignment -name IGNORE_PARTITIONS Off -set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off -set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" -set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On -set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On -set_global_assignment -name RTLV_GROUP_RELATED_NODES On -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off -set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off -set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On -set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On -set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On -set_global_assignment -name EQC_BBOX_MERGE On -set_global_assignment -name EQC_LVDS_MERGE On -set_global_assignment -name EQC_RAM_UNMERGING On -set_global_assignment -name EQC_DFF_SS_EMULATION On -set_global_assignment -name EQC_RAM_REGISTER_UNPACK On -set_global_assignment -name EQC_MAC_REGISTER_UNPACK On -set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On -set_global_assignment -name EQC_STRUCTURE_MATCHING On -set_global_assignment -name EQC_AUTO_BREAK_CONE On -set_global_assignment -name EQC_POWER_UP_COMPARE Off -set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On -set_global_assignment -name EQC_AUTO_INVERSION On -set_global_assignment -name EQC_AUTO_TERMINATE On -set_global_assignment -name EQC_SUB_CONE_REPORT Off -set_global_assignment -name EQC_RENAMING_RULES On -set_global_assignment -name EQC_PARAMETER_CHECK On -set_global_assignment -name EQC_AUTO_PORTSWAP On -set_global_assignment -name EQC_DETECT_DONT_CARES On -set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off -set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? -set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? -set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? -set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? -set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? -set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? -set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? -set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? -set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? -set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? -set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? -set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? -set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? -set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? -set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? -set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? -set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? -set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? -set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? -set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? -set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? -set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? -set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? -set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? -set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? -set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? -set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? -set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? -set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? -set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? -set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? -set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? -set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? -set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? -set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? -set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? -set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? -set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? -set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? -set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? -set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? -set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? -set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? -set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? -set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? -set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? -set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? -set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.sft b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.sft deleted file mode 100644 index ad21f32..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.sft +++ /dev/null @@ -1,6 +0,0 @@ -set tool_name "ModelSim (Verilog)" -set corner_file_list { - {{"Slow -8 1.2V 85 Model"} {rs232_8_1200mv_85c_slow.vo rs232_8_1200mv_85c_v_slow.sdo}} - {{"Slow -8 1.2V 0 Model"} {rs232_8_1200mv_0c_slow.vo rs232_8_1200mv_0c_v_slow.sdo}} - {{"Fast -M 1.2V 0 Model"} {rs232_min_1200mv_0c_fast.vo rs232_min_1200mv_0c_v_fast.sdo}} -} diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.vo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.vo deleted file mode 100644 index 396965f..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.vo +++ /dev/null @@ -1,2836 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - -// VENDOR "Altera" -// PROGRAM "Quartus II 64-Bit" -// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" - -// DATE "06/02/2023 03:03:50" - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This Verilog file should be used for ModelSim (Verilog) only -// - -`timescale 1 ps/ 1 ps - -module rs232 ( - sys_clk, - sys_rst_n, - rx, - tx); -input sys_clk; -input sys_rst_n; -input rx; -output tx; - -// Design Ports Information -// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default -// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default -// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default -// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default - - -wire gnd; -wire vcc; -wire unknown; - -assign gnd = 1'b0; -assign vcc = 1'b1; -assign unknown = 1'bx; - -tri1 devclrn; -tri1 devpor; -tri1 devoe; -// synopsys translate_off -initial $sdf_annotate("rs232_v.sdo"); -// synopsys translate_on - -wire \uart_tx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[0]~13_combout ; -wire \uart_rx_inst|baud_cnt[0]~14 ; -wire \uart_rx_inst|baud_cnt[1]~15_combout ; -wire \uart_rx_inst|baud_cnt[1]~16 ; -wire \uart_rx_inst|baud_cnt[2]~17_combout ; -wire \uart_rx_inst|baud_cnt[2]~18 ; -wire \uart_rx_inst|baud_cnt[3]~19_combout ; -wire \uart_rx_inst|baud_cnt[3]~20 ; -wire \uart_rx_inst|baud_cnt[4]~21_combout ; -wire \uart_rx_inst|baud_cnt[4]~22 ; -wire \uart_rx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[5]~24 ; -wire \uart_rx_inst|baud_cnt[6]~25_combout ; -wire \uart_rx_inst|baud_cnt[6]~26 ; -wire \uart_rx_inst|baud_cnt[7]~27_combout ; -wire \uart_rx_inst|baud_cnt[7]~28 ; -wire \uart_rx_inst|baud_cnt[8]~29_combout ; -wire \uart_rx_inst|baud_cnt[8]~30 ; -wire \uart_rx_inst|baud_cnt[9]~31_combout ; -wire \uart_rx_inst|baud_cnt[9]~32 ; -wire \uart_rx_inst|baud_cnt[10]~33_combout ; -wire \uart_rx_inst|baud_cnt[10]~34 ; -wire \uart_rx_inst|baud_cnt[11]~35_combout ; -wire \uart_rx_inst|baud_cnt[11]~36 ; -wire \uart_rx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal2~0_combout ; -wire \uart_tx_inst|Add1~0_combout ; -wire \uart_tx_inst|Add1~1_combout ; -wire \uart_rx_inst|bit_flag~q ; -wire \uart_rx_inst|Equal1~0_combout ; -wire \uart_rx_inst|Equal2~0_combout ; -wire \uart_rx_inst|Equal2~1_combout ; -wire \uart_rx_inst|Equal2~2_combout ; -wire \uart_rx_inst|work_en~q ; -wire \uart_rx_inst|Equal1~1_combout ; -wire \uart_rx_inst|Equal1~2_combout ; -wire \uart_rx_inst|Equal1~3_combout ; -wire \uart_rx_inst|always5~0_combout ; -wire \uart_rx_inst|start_nedge~q ; -wire \uart_rx_inst|work_en~0_combout ; -wire \uart_rx_inst|always3~0_combout ; -wire \tx~output_o ; -wire \sys_clk~input_o ; -wire \sys_clk~inputclkctrl_outclk ; -wire \uart_rx_inst|Add1~0_combout ; -wire \uart_rx_inst|bit_cnt~1_combout ; -wire \sys_rst_n~input_o ; -wire \uart_rx_inst|Add1~1 ; -wire \uart_rx_inst|Add1~2_combout ; -wire \uart_rx_inst|Add1~3 ; -wire \uart_rx_inst|Add1~4_combout ; -wire \uart_rx_inst|always4~0_combout ; -wire \uart_rx_inst|Add1~5 ; -wire \uart_rx_inst|Add1~6_combout ; -wire \uart_rx_inst|bit_cnt~0_combout ; -wire \uart_rx_inst|always4~1_combout ; -wire \uart_rx_inst|rx_flag~feeder_combout ; -wire \uart_rx_inst|rx_flag~q ; -wire \uart_rx_inst|po_flag~feeder_combout ; -wire \uart_rx_inst|po_flag~q ; -wire \uart_tx_inst|work_en~0_combout ; -wire \uart_tx_inst|work_en~q ; -wire \uart_tx_inst|baud_cnt[0]~13_combout ; -wire \uart_tx_inst|baud_cnt[10]~34 ; -wire \uart_tx_inst|baud_cnt[11]~35_combout ; -wire \uart_tx_inst|Equal1~0_combout ; -wire \uart_tx_inst|Equal1~1_combout ; -wire \uart_tx_inst|baud_cnt[11]~36 ; -wire \uart_tx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal1~3_combout ; -wire \uart_tx_inst|baud_cnt[2]~17_combout ; -wire \uart_tx_inst|baud_cnt[4]~21_combout ; -wire \uart_tx_inst|Equal1~2_combout ; -wire \uart_tx_inst|always1~0_combout ; -wire \uart_tx_inst|baud_cnt[0]~14 ; -wire \uart_tx_inst|baud_cnt[1]~15_combout ; -wire \uart_tx_inst|baud_cnt[1]~16 ; -wire \uart_tx_inst|baud_cnt[2]~18 ; -wire \uart_tx_inst|baud_cnt[3]~19_combout ; -wire \uart_tx_inst|baud_cnt[3]~20 ; -wire \uart_tx_inst|baud_cnt[4]~22 ; -wire \uart_tx_inst|baud_cnt[5]~24 ; -wire \uart_tx_inst|baud_cnt[6]~25_combout ; -wire \uart_tx_inst|baud_cnt[6]~26 ; -wire \uart_tx_inst|baud_cnt[7]~27_combout ; -wire \uart_tx_inst|baud_cnt[7]~28 ; -wire \uart_tx_inst|baud_cnt[8]~29_combout ; -wire \uart_tx_inst|baud_cnt[8]~30 ; -wire \uart_tx_inst|baud_cnt[9]~31_combout ; -wire \uart_tx_inst|baud_cnt[9]~32 ; -wire \uart_tx_inst|baud_cnt[10]~33_combout ; -wire \uart_tx_inst|Equal2~1_combout ; -wire \uart_tx_inst|bit_flag~q ; -wire \uart_tx_inst|always3~0_combout ; -wire \uart_tx_inst|bit_cnt[2]~2_combout ; -wire \uart_tx_inst|bit_cnt[3]~4_combout ; -wire \uart_tx_inst|always0~0_combout ; -wire \uart_tx_inst|always0~1_combout ; -wire \uart_tx_inst|bit_cnt[0]~5_combout ; -wire \rx~input_o ; -wire \uart_rx_inst|rx_reg1~0_combout ; -wire \uart_rx_inst|rx_reg1~q ; -wire \uart_rx_inst|rx_reg2~feeder_combout ; -wire \uart_rx_inst|rx_reg2~q ; -wire \uart_rx_inst|rx_reg3~feeder_combout ; -wire \uart_rx_inst|rx_reg3~q ; -wire \uart_rx_inst|rx_data[7]~0_combout ; -wire \uart_rx_inst|always8~0_combout ; -wire \uart_tx_inst|bit_cnt[1]~3_combout ; -wire \uart_tx_inst|tx~2_combout ; -wire \uart_tx_inst|tx~5_combout ; -wire \uart_rx_inst|rx_data[6]~feeder_combout ; -wire \uart_rx_inst|po_data[5]~feeder_combout ; -wire \uart_rx_inst|po_data[4]~feeder_combout ; -wire \uart_tx_inst|Mux0~0_combout ; -wire \uart_tx_inst|Mux0~1_combout ; -wire \uart_rx_inst|rx_data[2]~feeder_combout ; -wire \uart_rx_inst|rx_data[1]~feeder_combout ; -wire \uart_rx_inst|rx_data[0]~feeder_combout ; -wire \uart_tx_inst|tx~3_combout ; -wire \uart_tx_inst|tx~4_combout ; -wire \uart_tx_inst|tx~6_combout ; -wire \uart_tx_inst|tx~7_combout ; -wire \uart_tx_inst|tx~q ; -wire [7:0] \uart_rx_inst|rx_data ; -wire [7:0] \uart_rx_inst|po_data ; -wire [3:0] \uart_rx_inst|bit_cnt ; -wire [12:0] \uart_rx_inst|baud_cnt ; -wire [3:0] \uart_tx_inst|bit_cnt ; -wire [12:0] \uart_tx_inst|baud_cnt ; - - -// Location: FF_X6_Y9_N13 -dffeas \uart_tx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[4]~22 ), - .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_tx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; -defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X10_Y9_N5 -dffeas \uart_rx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N7 -dffeas \uart_rx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N19 -dffeas \uart_rx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N21 -dffeas \uart_rx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N11 -dffeas \uart_rx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N15 -dffeas \uart_rx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N9 -dffeas \uart_rx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N13 -dffeas \uart_rx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N23 -dffeas \uart_rx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N27 -dffeas \uart_rx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N17 -dffeas \uart_rx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N25 -dffeas \uart_rx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N29 -dffeas \uart_rx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) -// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_rx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[0]~14 ), - .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_rx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) -// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[1]~16 ), - .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_rx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) - - .dataa(\uart_rx_inst|baud_cnt [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[2]~18 ), - .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_rx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) -// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[3]~20 ), - .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_rx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[4]~22 ), - .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_rx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) -// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[5]~24 ), - .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_rx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[6]~26 ), - .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_rx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) -// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[7]~28 ), - .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_rx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[8]~30 ), - .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_rx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) -// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [10]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[9]~32 ), - .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_rx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) - - .dataa(\uart_rx_inst|baud_cnt [11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[10]~34 ), - .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_rx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|baud_cnt [12]), - .cin(\uart_rx_inst|baud_cnt[11]~36 ), - .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; -defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y9_N23 -dffeas \uart_rx_inst|po_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [2]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( -// Equation(s): -// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [6]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; -defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( -// Equation(s): -// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(gnd), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; -defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( -// Equation(s): -// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|bit_cnt [1]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; -defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N11 -dffeas \uart_rx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Equal2~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( -// Equation(s): -// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(\uart_rx_inst|baud_cnt [0]), - .datad(\uart_rx_inst|baud_cnt [8]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( -// Equation(s): -// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) - - .dataa(\uart_rx_inst|baud_cnt [5]), - .datab(\uart_rx_inst|baud_cnt [3]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( -// Equation(s): -// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) - - .dataa(\uart_rx_inst|baud_cnt [9]), - .datab(\uart_rx_inst|baud_cnt [11]), - .datac(\uart_rx_inst|baud_cnt [6]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( -// Equation(s): -// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) - - .dataa(\uart_rx_inst|Equal2~1_combout ), - .datab(\uart_rx_inst|baud_cnt [12]), - .datac(\uart_rx_inst|Equal1~0_combout ), - .datad(\uart_rx_inst|Equal2~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; -defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X9_Y9_N17 -dffeas \uart_rx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_rx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( -// Equation(s): -// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( -// Equation(s): -// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|baud_cnt [11]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; -defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( -// Equation(s): -// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) - - .dataa(\uart_rx_inst|baud_cnt [12]), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(\uart_rx_inst|baud_cnt [9]), - .datad(\uart_rx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; -defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|always5~0 ( -// Equation(s): -// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|Equal1~0_combout ), - .datac(\uart_rx_inst|Equal1~1_combout ), - .datad(\uart_rx_inst|Equal1~3_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always5~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; -defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N13 -dffeas \uart_rx_inst|start_nedge ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|always3~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|start_nedge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; -defparam \uart_rx_inst|start_nedge .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( -// Equation(s): -// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|start_nedge~q ), - .datac(\uart_rx_inst|work_en~q ), - .datad(\uart_rx_inst|always4~1_combout ), - .cin(gnd), - .combout(\uart_rx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|always3~0 ( -// Equation(s): -// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) - - .dataa(gnd), - .datab(\uart_rx_inst|rx_reg2~q ), - .datac(\uart_rx_inst|rx_reg3~q ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; -defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOOBUF_X0_Y9_N16 -cycloneive_io_obuf \tx~output ( - .i(!\uart_tx_inst|tx~q ), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(\tx~output_o ), - .obar()); -// synopsys translate_off -defparam \tx~output .bus_hold = "false"; -defparam \tx~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y15_N22 -cycloneive_io_ibuf \sys_clk~input ( - .i(sys_clk), - .ibar(gnd), - .o(\sys_clk~input_o )); -// synopsys translate_off -defparam \sys_clk~input .bus_hold = "false"; -defparam \sys_clk~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G8 -cycloneive_clkctrl \sys_clk~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\sys_clk~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\sys_clk~inputclkctrl_outclk )); -// synopsys translate_off -defparam \sys_clk~inputclkctrl .clock_type = "global clock"; -defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( -// Equation(s): -// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) -// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|Add1~0_combout ), - .cout(\uart_rx_inst|Add1~1 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; -defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(\uart_rx_inst|Add1~0_combout ), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; -defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y4_N1 -cycloneive_io_ibuf \sys_rst_n~input ( - .i(sys_rst_n), - .ibar(gnd), - .o(\sys_rst_n~input_o )); -// synopsys translate_off -defparam \sys_rst_n~input .bus_hold = "false"; -defparam \sys_rst_n~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X8_Y9_N5 -dffeas \uart_rx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( -// Equation(s): -// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) -// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~1 ), - .combout(\uart_rx_inst|Add1~2_combout ), - .cout(\uart_rx_inst|Add1~3 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N19 -dffeas \uart_rx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( -// Equation(s): -// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) -// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~3 ), - .combout(\uart_rx_inst|Add1~4_combout ), - .cout(\uart_rx_inst|Add1~5 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N21 -dffeas \uart_rx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|always4~0 ( -// Equation(s): -// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(\uart_rx_inst|bit_cnt [0]), - .datad(\uart_rx_inst|bit_cnt [2]), - .cin(gnd), - .combout(\uart_rx_inst|always4~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; -defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( -// Equation(s): -// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(\uart_rx_inst|Add1~5 ), - .combout(\uart_rx_inst|Add1~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; -defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(\uart_rx_inst|bit_cnt [3]), - .datad(\uart_rx_inst|Add1~6_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; -defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N1 -dffeas \uart_rx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|always4~1 ( -// Equation(s): -// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always4~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; -defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( -// Equation(s): -// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|always4~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N15 -dffeas \uart_rx_inst|rx_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( -// Equation(s): -// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_flag~q ), - .cin(gnd), - .combout(\uart_rx_inst|po_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N31 -dffeas \uart_rx_inst|po_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( -// Equation(s): -// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|po_flag~q ), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N15 -dffeas \uart_tx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_tx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) -// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_tx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) -// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) - - .dataa(\uart_tx_inst|baud_cnt [10]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[9]~32 ), - .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_tx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [11]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[10]~34 ), - .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_tx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N25 -dffeas \uart_tx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( -// Equation(s): -// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(\uart_tx_inst|baud_cnt [3]), - .datad(\uart_tx_inst|baud_cnt [7]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; -defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N0 -cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( -// Equation(s): -// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) - - .dataa(\uart_tx_inst|baud_cnt [9]), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(\uart_tx_inst|baud_cnt [11]), - .datad(\uart_tx_inst|Equal1~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; -defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) - - .dataa(\uart_tx_inst|baud_cnt [12]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\uart_tx_inst|baud_cnt[11]~36 ), - .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; -defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N27 -dffeas \uart_tx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( -// Equation(s): -// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [12]), - .datac(gnd), - .datad(\uart_tx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) -// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) - - .dataa(\uart_tx_inst|baud_cnt [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[1]~16 ), - .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_tx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N7 -dffeas \uart_tx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) -// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[3]~20 ), - .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_tx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N11 -dffeas \uart_tx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( -// Equation(s): -// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) - - .dataa(\uart_tx_inst|baud_cnt [6]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; -defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N30 -cycloneive_lcell_comb \uart_tx_inst|always1~0 ( -// Equation(s): -// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|Equal1~1_combout ), - .datac(\uart_tx_inst|Equal1~3_combout ), - .datad(\uart_tx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; -defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X6_Y9_N3 -dffeas \uart_tx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[0]~14 ), - .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_tx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N5 -dffeas \uart_tx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [3]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[2]~18 ), - .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_tx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N9 -dffeas \uart_tx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) -// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[5]~24 ), - .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_tx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N15 -dffeas \uart_tx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[6]~26 ), - .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_tx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N17 -dffeas \uart_tx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) -// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[7]~28 ), - .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_tx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N19 -dffeas \uart_tx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[8]~30 ), - .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_tx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N21 -dffeas \uart_tx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X6_Y9_N23 -dffeas \uart_tx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( -// Equation(s): -// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) - - .dataa(\uart_tx_inst|Equal2~0_combout ), - .datab(\uart_tx_inst|baud_cnt [10]), - .datac(\uart_tx_inst|Equal1~1_combout ), - .datad(\uart_tx_inst|baud_cnt [12]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; -defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N21 -dffeas \uart_tx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|Equal2~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|always3~0 ( -// Equation(s): -// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; -defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) - - .dataa(\uart_tx_inst|Add1~0_combout ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; -defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N27 -dffeas \uart_tx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[2]~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) - - .dataa(\uart_tx_inst|Add1~1_combout ), - .datab(\uart_tx_inst|always3~0_combout ), - .datac(\uart_tx_inst|bit_cnt [3]), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; -defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[3]~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|always0~0 ( -// Equation(s): -// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) - - .dataa(gnd), - .datab(\uart_tx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|always0~1 ( -// Equation(s): -// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; -defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [0]), - .datad(\uart_tx_inst|work_en~q ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; -defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[0]~5_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y8_N1 -cycloneive_io_ibuf \rx~input ( - .i(rx), - .ibar(gnd), - .o(\rx~input_o )); -// synopsys translate_off -defparam \rx~input .bus_hold = "false"; -defparam \rx~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( -// Equation(s): -// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\rx~input_o ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N19 -dffeas \uart_rx_inst|rx_reg1 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg1~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg1~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg2~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N1 -dffeas \uart_rx_inst|rx_reg2 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg2~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg2~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N27 -dffeas \uart_rx_inst|rx_reg3 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg3~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( -// Equation(s): -// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg3~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|always8~0 ( -// Equation(s): -// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|always8~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; -defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N29 -dffeas \uart_rx_inst|rx_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[7]~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N5 -dffeas \uart_rx_inst|po_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [7]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [1]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; -defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N7 -dffeas \uart_tx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[1]~3_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|tx~2 ( -// Equation(s): -// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [7]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; -defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|tx~5 ( -// Equation(s): -// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) - - .dataa(\uart_tx_inst|tx~q ), - .datab(\uart_tx_inst|tx~2_combout ), - .datac(\uart_tx_inst|bit_flag~q ), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|tx~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; -defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [7]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N3 -dffeas \uart_rx_inst|rx_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[6]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N7 -dffeas \uart_rx_inst|rx_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [5]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N21 -dffeas \uart_rx_inst|po_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[5]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N15 -dffeas \uart_rx_inst|po_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N31 -dffeas \uart_rx_inst|rx_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [5]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [4]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N1 -dffeas \uart_rx_inst|po_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[4]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N23 -dffeas \uart_rx_inst|rx_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [4]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N25 -dffeas \uart_rx_inst|po_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [3]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( -// Equation(s): -// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [4]), - .datac(\uart_rx_inst|po_data [3]), - .datad(\uart_tx_inst|bit_cnt [0]), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; -defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( -// Equation(s): -// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & -// (((\uart_tx_inst|Mux0~0_combout )))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [5]), - .datac(\uart_rx_inst|po_data [6]), - .datad(\uart_tx_inst|Mux0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; -defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [3]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N9 -dffeas \uart_rx_inst|rx_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[2]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [2]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N27 -dffeas \uart_rx_inst|rx_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[1]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N19 -dffeas \uart_rx_inst|po_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [1]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [1]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N13 -dffeas \uart_rx_inst|rx_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[0]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N29 -dffeas \uart_rx_inst|po_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [0]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|tx~3 ( -// Equation(s): -// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) - - .dataa(\uart_rx_inst|po_data [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [0]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; -defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|tx~4 ( -// Equation(s): -// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [1]), - .datad(\uart_tx_inst|tx~3_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; -defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|tx~6 ( -// Equation(s): -// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|bit_cnt [2]), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~4_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; -defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|tx~7 ( -// Equation(s): -// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # -// (!\uart_tx_inst|tx~6_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|tx~5_combout ), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~6_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~7_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; -defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N13 -dffeas \uart_tx_inst|tx ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|tx~7_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|tx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|tx .is_wysiwyg = "true"; -defparam \uart_tx_inst|tx .power_up = "low"; -// synopsys translate_on - -assign tx = \tx~output_o ; - -endmodule diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_slow.vo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_slow.vo deleted file mode 100644 index bba2871..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_slow.vo +++ /dev/null @@ -1,2836 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - -// VENDOR "Altera" -// PROGRAM "Quartus II 64-Bit" -// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" - -// DATE "06/02/2023 03:03:50" - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This Verilog file should be used for ModelSim (Verilog) only -// - -`timescale 1 ps/ 1 ps - -module rs232 ( - sys_clk, - sys_rst_n, - rx, - tx); -input sys_clk; -input sys_rst_n; -input rx; -output tx; - -// Design Ports Information -// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default -// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default -// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default -// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default - - -wire gnd; -wire vcc; -wire unknown; - -assign gnd = 1'b0; -assign vcc = 1'b1; -assign unknown = 1'bx; - -tri1 devclrn; -tri1 devpor; -tri1 devoe; -// synopsys translate_off -initial $sdf_annotate("rs232_8_1200mv_0c_v_slow.sdo"); -// synopsys translate_on - -wire \uart_tx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[0]~13_combout ; -wire \uart_rx_inst|baud_cnt[0]~14 ; -wire \uart_rx_inst|baud_cnt[1]~15_combout ; -wire \uart_rx_inst|baud_cnt[1]~16 ; -wire \uart_rx_inst|baud_cnt[2]~17_combout ; -wire \uart_rx_inst|baud_cnt[2]~18 ; -wire \uart_rx_inst|baud_cnt[3]~19_combout ; -wire \uart_rx_inst|baud_cnt[3]~20 ; -wire \uart_rx_inst|baud_cnt[4]~21_combout ; -wire \uart_rx_inst|baud_cnt[4]~22 ; -wire \uart_rx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[5]~24 ; -wire \uart_rx_inst|baud_cnt[6]~25_combout ; -wire \uart_rx_inst|baud_cnt[6]~26 ; -wire \uart_rx_inst|baud_cnt[7]~27_combout ; -wire \uart_rx_inst|baud_cnt[7]~28 ; -wire \uart_rx_inst|baud_cnt[8]~29_combout ; -wire \uart_rx_inst|baud_cnt[8]~30 ; -wire \uart_rx_inst|baud_cnt[9]~31_combout ; -wire \uart_rx_inst|baud_cnt[9]~32 ; -wire \uart_rx_inst|baud_cnt[10]~33_combout ; -wire \uart_rx_inst|baud_cnt[10]~34 ; -wire \uart_rx_inst|baud_cnt[11]~35_combout ; -wire \uart_rx_inst|baud_cnt[11]~36 ; -wire \uart_rx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal2~0_combout ; -wire \uart_tx_inst|Add1~0_combout ; -wire \uart_tx_inst|Add1~1_combout ; -wire \uart_rx_inst|bit_flag~q ; -wire \uart_rx_inst|Equal1~0_combout ; -wire \uart_rx_inst|Equal2~0_combout ; -wire \uart_rx_inst|Equal2~1_combout ; -wire \uart_rx_inst|Equal2~2_combout ; -wire \uart_rx_inst|work_en~q ; -wire \uart_rx_inst|Equal1~1_combout ; -wire \uart_rx_inst|Equal1~2_combout ; -wire \uart_rx_inst|Equal1~3_combout ; -wire \uart_rx_inst|always5~0_combout ; -wire \uart_rx_inst|start_nedge~q ; -wire \uart_rx_inst|work_en~0_combout ; -wire \uart_rx_inst|always3~0_combout ; -wire \tx~output_o ; -wire \sys_clk~input_o ; -wire \sys_clk~inputclkctrl_outclk ; -wire \uart_rx_inst|Add1~0_combout ; -wire \uart_rx_inst|bit_cnt~1_combout ; -wire \sys_rst_n~input_o ; -wire \uart_rx_inst|Add1~1 ; -wire \uart_rx_inst|Add1~2_combout ; -wire \uart_rx_inst|Add1~3 ; -wire \uart_rx_inst|Add1~4_combout ; -wire \uart_rx_inst|always4~0_combout ; -wire \uart_rx_inst|Add1~5 ; -wire \uart_rx_inst|Add1~6_combout ; -wire \uart_rx_inst|bit_cnt~0_combout ; -wire \uart_rx_inst|always4~1_combout ; -wire \uart_rx_inst|rx_flag~feeder_combout ; -wire \uart_rx_inst|rx_flag~q ; -wire \uart_rx_inst|po_flag~feeder_combout ; -wire \uart_rx_inst|po_flag~q ; -wire \uart_tx_inst|work_en~0_combout ; -wire \uart_tx_inst|work_en~q ; -wire \uart_tx_inst|baud_cnt[0]~13_combout ; -wire \uart_tx_inst|baud_cnt[10]~34 ; -wire \uart_tx_inst|baud_cnt[11]~35_combout ; -wire \uart_tx_inst|Equal1~0_combout ; -wire \uart_tx_inst|Equal1~1_combout ; -wire \uart_tx_inst|baud_cnt[11]~36 ; -wire \uart_tx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal1~3_combout ; -wire \uart_tx_inst|baud_cnt[2]~17_combout ; -wire \uart_tx_inst|baud_cnt[4]~21_combout ; -wire \uart_tx_inst|Equal1~2_combout ; -wire \uart_tx_inst|always1~0_combout ; -wire \uart_tx_inst|baud_cnt[0]~14 ; -wire \uart_tx_inst|baud_cnt[1]~15_combout ; -wire \uart_tx_inst|baud_cnt[1]~16 ; -wire \uart_tx_inst|baud_cnt[2]~18 ; -wire \uart_tx_inst|baud_cnt[3]~19_combout ; -wire \uart_tx_inst|baud_cnt[3]~20 ; -wire \uart_tx_inst|baud_cnt[4]~22 ; -wire \uart_tx_inst|baud_cnt[5]~24 ; -wire \uart_tx_inst|baud_cnt[6]~25_combout ; -wire \uart_tx_inst|baud_cnt[6]~26 ; -wire \uart_tx_inst|baud_cnt[7]~27_combout ; -wire \uart_tx_inst|baud_cnt[7]~28 ; -wire \uart_tx_inst|baud_cnt[8]~29_combout ; -wire \uart_tx_inst|baud_cnt[8]~30 ; -wire \uart_tx_inst|baud_cnt[9]~31_combout ; -wire \uart_tx_inst|baud_cnt[9]~32 ; -wire \uart_tx_inst|baud_cnt[10]~33_combout ; -wire \uart_tx_inst|Equal2~1_combout ; -wire \uart_tx_inst|bit_flag~q ; -wire \uart_tx_inst|always3~0_combout ; -wire \uart_tx_inst|bit_cnt[2]~2_combout ; -wire \uart_tx_inst|bit_cnt[3]~4_combout ; -wire \uart_tx_inst|always0~0_combout ; -wire \uart_tx_inst|always0~1_combout ; -wire \uart_tx_inst|bit_cnt[0]~5_combout ; -wire \rx~input_o ; -wire \uart_rx_inst|rx_reg1~0_combout ; -wire \uart_rx_inst|rx_reg1~q ; -wire \uart_rx_inst|rx_reg2~feeder_combout ; -wire \uart_rx_inst|rx_reg2~q ; -wire \uart_rx_inst|rx_reg3~feeder_combout ; -wire \uart_rx_inst|rx_reg3~q ; -wire \uart_rx_inst|rx_data[7]~0_combout ; -wire \uart_rx_inst|always8~0_combout ; -wire \uart_tx_inst|bit_cnt[1]~3_combout ; -wire \uart_tx_inst|tx~2_combout ; -wire \uart_tx_inst|tx~5_combout ; -wire \uart_rx_inst|rx_data[6]~feeder_combout ; -wire \uart_rx_inst|po_data[5]~feeder_combout ; -wire \uart_rx_inst|po_data[4]~feeder_combout ; -wire \uart_tx_inst|Mux0~0_combout ; -wire \uart_tx_inst|Mux0~1_combout ; -wire \uart_rx_inst|rx_data[2]~feeder_combout ; -wire \uart_rx_inst|rx_data[1]~feeder_combout ; -wire \uart_rx_inst|rx_data[0]~feeder_combout ; -wire \uart_tx_inst|tx~3_combout ; -wire \uart_tx_inst|tx~4_combout ; -wire \uart_tx_inst|tx~6_combout ; -wire \uart_tx_inst|tx~7_combout ; -wire \uart_tx_inst|tx~q ; -wire [7:0] \uart_rx_inst|rx_data ; -wire [7:0] \uart_rx_inst|po_data ; -wire [3:0] \uart_rx_inst|bit_cnt ; -wire [12:0] \uart_rx_inst|baud_cnt ; -wire [3:0] \uart_tx_inst|bit_cnt ; -wire [12:0] \uart_tx_inst|baud_cnt ; - - -// Location: FF_X6_Y9_N13 -dffeas \uart_tx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[4]~22 ), - .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_tx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; -defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X10_Y9_N5 -dffeas \uart_rx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N7 -dffeas \uart_rx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N19 -dffeas \uart_rx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N21 -dffeas \uart_rx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N11 -dffeas \uart_rx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N15 -dffeas \uart_rx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N9 -dffeas \uart_rx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N13 -dffeas \uart_rx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N23 -dffeas \uart_rx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N27 -dffeas \uart_rx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N17 -dffeas \uart_rx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N25 -dffeas \uart_rx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N29 -dffeas \uart_rx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) -// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_rx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[0]~14 ), - .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_rx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) -// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[1]~16 ), - .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_rx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) - - .dataa(\uart_rx_inst|baud_cnt [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[2]~18 ), - .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_rx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) -// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[3]~20 ), - .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_rx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[4]~22 ), - .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_rx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) -// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[5]~24 ), - .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_rx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[6]~26 ), - .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_rx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) -// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[7]~28 ), - .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_rx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[8]~30 ), - .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_rx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) -// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [10]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[9]~32 ), - .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_rx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) - - .dataa(\uart_rx_inst|baud_cnt [11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[10]~34 ), - .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_rx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|baud_cnt [12]), - .cin(\uart_rx_inst|baud_cnt[11]~36 ), - .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; -defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y9_N23 -dffeas \uart_rx_inst|po_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [2]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( -// Equation(s): -// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [6]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; -defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( -// Equation(s): -// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(gnd), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; -defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( -// Equation(s): -// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|bit_cnt [1]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; -defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N11 -dffeas \uart_rx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Equal2~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( -// Equation(s): -// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(\uart_rx_inst|baud_cnt [0]), - .datad(\uart_rx_inst|baud_cnt [8]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( -// Equation(s): -// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) - - .dataa(\uart_rx_inst|baud_cnt [5]), - .datab(\uart_rx_inst|baud_cnt [3]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( -// Equation(s): -// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) - - .dataa(\uart_rx_inst|baud_cnt [9]), - .datab(\uart_rx_inst|baud_cnt [11]), - .datac(\uart_rx_inst|baud_cnt [6]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( -// Equation(s): -// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) - - .dataa(\uart_rx_inst|Equal2~1_combout ), - .datab(\uart_rx_inst|baud_cnt [12]), - .datac(\uart_rx_inst|Equal1~0_combout ), - .datad(\uart_rx_inst|Equal2~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; -defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X9_Y9_N17 -dffeas \uart_rx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_rx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( -// Equation(s): -// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( -// Equation(s): -// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|baud_cnt [11]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; -defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( -// Equation(s): -// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) - - .dataa(\uart_rx_inst|baud_cnt [12]), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(\uart_rx_inst|baud_cnt [9]), - .datad(\uart_rx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; -defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|always5~0 ( -// Equation(s): -// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|Equal1~0_combout ), - .datac(\uart_rx_inst|Equal1~1_combout ), - .datad(\uart_rx_inst|Equal1~3_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always5~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; -defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N13 -dffeas \uart_rx_inst|start_nedge ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|always3~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|start_nedge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; -defparam \uart_rx_inst|start_nedge .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( -// Equation(s): -// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|start_nedge~q ), - .datac(\uart_rx_inst|work_en~q ), - .datad(\uart_rx_inst|always4~1_combout ), - .cin(gnd), - .combout(\uart_rx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|always3~0 ( -// Equation(s): -// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) - - .dataa(gnd), - .datab(\uart_rx_inst|rx_reg2~q ), - .datac(\uart_rx_inst|rx_reg3~q ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; -defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOOBUF_X0_Y9_N16 -cycloneive_io_obuf \tx~output ( - .i(!\uart_tx_inst|tx~q ), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(\tx~output_o ), - .obar()); -// synopsys translate_off -defparam \tx~output .bus_hold = "false"; -defparam \tx~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y15_N22 -cycloneive_io_ibuf \sys_clk~input ( - .i(sys_clk), - .ibar(gnd), - .o(\sys_clk~input_o )); -// synopsys translate_off -defparam \sys_clk~input .bus_hold = "false"; -defparam \sys_clk~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G8 -cycloneive_clkctrl \sys_clk~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\sys_clk~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\sys_clk~inputclkctrl_outclk )); -// synopsys translate_off -defparam \sys_clk~inputclkctrl .clock_type = "global clock"; -defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( -// Equation(s): -// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) -// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|Add1~0_combout ), - .cout(\uart_rx_inst|Add1~1 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; -defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(\uart_rx_inst|Add1~0_combout ), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; -defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y4_N1 -cycloneive_io_ibuf \sys_rst_n~input ( - .i(sys_rst_n), - .ibar(gnd), - .o(\sys_rst_n~input_o )); -// synopsys translate_off -defparam \sys_rst_n~input .bus_hold = "false"; -defparam \sys_rst_n~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X8_Y9_N5 -dffeas \uart_rx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( -// Equation(s): -// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) -// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~1 ), - .combout(\uart_rx_inst|Add1~2_combout ), - .cout(\uart_rx_inst|Add1~3 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N19 -dffeas \uart_rx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( -// Equation(s): -// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) -// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~3 ), - .combout(\uart_rx_inst|Add1~4_combout ), - .cout(\uart_rx_inst|Add1~5 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N21 -dffeas \uart_rx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|always4~0 ( -// Equation(s): -// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(\uart_rx_inst|bit_cnt [0]), - .datad(\uart_rx_inst|bit_cnt [2]), - .cin(gnd), - .combout(\uart_rx_inst|always4~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; -defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( -// Equation(s): -// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(\uart_rx_inst|Add1~5 ), - .combout(\uart_rx_inst|Add1~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; -defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(\uart_rx_inst|bit_cnt [3]), - .datad(\uart_rx_inst|Add1~6_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; -defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N1 -dffeas \uart_rx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|always4~1 ( -// Equation(s): -// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always4~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; -defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( -// Equation(s): -// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|always4~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N15 -dffeas \uart_rx_inst|rx_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( -// Equation(s): -// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_flag~q ), - .cin(gnd), - .combout(\uart_rx_inst|po_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N31 -dffeas \uart_rx_inst|po_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( -// Equation(s): -// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|po_flag~q ), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N15 -dffeas \uart_tx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_tx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) -// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_tx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) -// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) - - .dataa(\uart_tx_inst|baud_cnt [10]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[9]~32 ), - .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_tx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [11]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[10]~34 ), - .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_tx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N25 -dffeas \uart_tx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( -// Equation(s): -// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(\uart_tx_inst|baud_cnt [3]), - .datad(\uart_tx_inst|baud_cnt [7]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; -defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N0 -cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( -// Equation(s): -// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) - - .dataa(\uart_tx_inst|baud_cnt [9]), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(\uart_tx_inst|baud_cnt [11]), - .datad(\uart_tx_inst|Equal1~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; -defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) - - .dataa(\uart_tx_inst|baud_cnt [12]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\uart_tx_inst|baud_cnt[11]~36 ), - .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; -defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N27 -dffeas \uart_tx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( -// Equation(s): -// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [12]), - .datac(gnd), - .datad(\uart_tx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) -// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) - - .dataa(\uart_tx_inst|baud_cnt [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[1]~16 ), - .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_tx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N7 -dffeas \uart_tx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) -// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[3]~20 ), - .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_tx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N11 -dffeas \uart_tx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( -// Equation(s): -// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) - - .dataa(\uart_tx_inst|baud_cnt [6]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; -defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N30 -cycloneive_lcell_comb \uart_tx_inst|always1~0 ( -// Equation(s): -// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|Equal1~1_combout ), - .datac(\uart_tx_inst|Equal1~3_combout ), - .datad(\uart_tx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; -defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X6_Y9_N3 -dffeas \uart_tx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[0]~14 ), - .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_tx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N5 -dffeas \uart_tx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [3]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[2]~18 ), - .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_tx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N9 -dffeas \uart_tx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) -// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[5]~24 ), - .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_tx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N15 -dffeas \uart_tx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[6]~26 ), - .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_tx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N17 -dffeas \uart_tx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) -// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[7]~28 ), - .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_tx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N19 -dffeas \uart_tx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[8]~30 ), - .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_tx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N21 -dffeas \uart_tx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X6_Y9_N23 -dffeas \uart_tx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( -// Equation(s): -// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) - - .dataa(\uart_tx_inst|Equal2~0_combout ), - .datab(\uart_tx_inst|baud_cnt [10]), - .datac(\uart_tx_inst|Equal1~1_combout ), - .datad(\uart_tx_inst|baud_cnt [12]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; -defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N21 -dffeas \uart_tx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|Equal2~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|always3~0 ( -// Equation(s): -// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; -defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) - - .dataa(\uart_tx_inst|Add1~0_combout ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; -defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N27 -dffeas \uart_tx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[2]~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) - - .dataa(\uart_tx_inst|Add1~1_combout ), - .datab(\uart_tx_inst|always3~0_combout ), - .datac(\uart_tx_inst|bit_cnt [3]), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; -defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[3]~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|always0~0 ( -// Equation(s): -// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) - - .dataa(gnd), - .datab(\uart_tx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|always0~1 ( -// Equation(s): -// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; -defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [0]), - .datad(\uart_tx_inst|work_en~q ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; -defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[0]~5_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y8_N1 -cycloneive_io_ibuf \rx~input ( - .i(rx), - .ibar(gnd), - .o(\rx~input_o )); -// synopsys translate_off -defparam \rx~input .bus_hold = "false"; -defparam \rx~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( -// Equation(s): -// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\rx~input_o ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N19 -dffeas \uart_rx_inst|rx_reg1 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg1~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg1~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg2~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N1 -dffeas \uart_rx_inst|rx_reg2 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg2~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg2~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N27 -dffeas \uart_rx_inst|rx_reg3 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg3~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( -// Equation(s): -// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg3~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|always8~0 ( -// Equation(s): -// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|always8~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; -defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N29 -dffeas \uart_rx_inst|rx_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[7]~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N5 -dffeas \uart_rx_inst|po_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [7]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [1]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; -defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N7 -dffeas \uart_tx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[1]~3_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|tx~2 ( -// Equation(s): -// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [7]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; -defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|tx~5 ( -// Equation(s): -// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) - - .dataa(\uart_tx_inst|tx~q ), - .datab(\uart_tx_inst|tx~2_combout ), - .datac(\uart_tx_inst|bit_flag~q ), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|tx~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; -defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [7]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N3 -dffeas \uart_rx_inst|rx_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[6]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N7 -dffeas \uart_rx_inst|rx_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [5]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N21 -dffeas \uart_rx_inst|po_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[5]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N15 -dffeas \uart_rx_inst|po_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N31 -dffeas \uart_rx_inst|rx_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [5]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [4]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N1 -dffeas \uart_rx_inst|po_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[4]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N23 -dffeas \uart_rx_inst|rx_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [4]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N25 -dffeas \uart_rx_inst|po_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [3]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( -// Equation(s): -// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [4]), - .datac(\uart_rx_inst|po_data [3]), - .datad(\uart_tx_inst|bit_cnt [0]), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; -defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( -// Equation(s): -// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & -// (((\uart_tx_inst|Mux0~0_combout )))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [5]), - .datac(\uart_rx_inst|po_data [6]), - .datad(\uart_tx_inst|Mux0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; -defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [3]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N9 -dffeas \uart_rx_inst|rx_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[2]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [2]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N27 -dffeas \uart_rx_inst|rx_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[1]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N19 -dffeas \uart_rx_inst|po_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [1]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [1]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N13 -dffeas \uart_rx_inst|rx_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[0]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N29 -dffeas \uart_rx_inst|po_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [0]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|tx~3 ( -// Equation(s): -// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) - - .dataa(\uart_rx_inst|po_data [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [0]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; -defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|tx~4 ( -// Equation(s): -// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [1]), - .datad(\uart_tx_inst|tx~3_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; -defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|tx~6 ( -// Equation(s): -// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|bit_cnt [2]), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~4_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; -defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|tx~7 ( -// Equation(s): -// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # -// (!\uart_tx_inst|tx~6_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|tx~5_combout ), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~6_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~7_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; -defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N13 -dffeas \uart_tx_inst|tx ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|tx~7_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|tx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|tx .is_wysiwyg = "true"; -defparam \uart_tx_inst|tx .power_up = "low"; -// synopsys translate_on - -assign tx = \tx~output_o ; - -endmodule diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_v_slow.sdo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_v_slow.sdo deleted file mode 100644 index 4c542b2..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_v_slow.sdo +++ /dev/null @@ -1,2275 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This file contains Slow Corner delays for the design using part EP4CE15F23C8, -// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius -// - -// -// This SDF file should be used for ModelSim (Verilog) only -// - -(DELAYFILE - (SDFVERSION "2.1") - (DESIGN "rs232") - (DATE "06/02/2023 03:03:50") - (VENDOR "Altera") - (PROGRAM "Quartus II 64-Bit") - (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") - (DIVIDER .) - (TIMESCALE 1 ps) - - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (393:393:393)) - (IOPATH dataa combout (414:414:414) (444:444:444)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1643:1643:1643) (1662:1662:1662)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5313:5313:5313) (5387:5387:5387)) - (PORT sclr (845:845:845) (900:900:900)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (546:546:546) (526:526:526)) - (PORT datab (325:325:325) (382:382:382)) - (IOPATH dataa combout (408:408:408) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datab combout (415:415:415) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (392:392:392)) - (IOPATH dataa combout (414:414:414) (444:444:444)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (347:347:347) (405:405:405)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (349:349:349) (411:411:411)) - (IOPATH dataa combout (414:414:414) (444:444:444)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (351:351:351) (416:416:416)) - (IOPATH dataa combout (435:435:435) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (349:349:349) (407:407:407)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (340:340:340) (396:396:396)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (384:384:384)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (325:325:325) (382:382:382)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (533:533:533) (518:518:518)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (340:340:340) (395:395:395)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (365:365:365) (425:425:425)) - (IOPATH dataa combout (414:414:414) (444:444:444)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT datad (514:514:514) (500:500:500)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT asdata (1249:1249:1249) (1141:1141:1141)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (615:615:615) (569:569:569)) - (PORT datab (559:559:559) (535:535:535)) - (PORT datac (510:510:510) (500:500:500)) - (PORT datad (520:520:520) (500:500:500)) - (IOPATH dataa combout (404:404:404) (450:450:450)) - (IOPATH datab combout (406:406:406) (453:453:453)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (367:367:367) (439:439:439)) - (PORT datab (409:409:409) (479:479:479)) - (PORT datad (353:353:353) (433:433:433)) - (IOPATH dataa combout (435:435:435) (425:425:425)) - (IOPATH datab combout (384:384:384) (398:398:398)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (631:631:631) (581:581:581)) - (PORT datab (552:552:552) (527:527:527)) - (PORT datac (555:555:555) (525:525:525)) - (PORT datad (309:309:309) (368:368:368)) - (IOPATH dataa combout (394:394:394) (400:400:400)) - (IOPATH datab combout (400:400:400) (398:398:398)) - (IOPATH datac combout (305:305:305) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (329:329:329) (392:392:392)) - (PORT datab (328:328:328) (386:386:386)) - (PORT datac (283:283:283) (349:349:349)) - (PORT datad (287:287:287) (345:345:345)) - (IOPATH dataa combout (420:420:420) (371:371:371)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datac combout (305:305:305) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (824:824:824) (736:736:736)) - (PORT datab (556:556:556) (541:541:541)) - (PORT datac (561:561:561) (532:532:532)) - (PORT datad (834:834:834) (717:717:717)) - (IOPATH dataa combout (408:408:408) (425:425:425)) - (IOPATH datab combout (415:415:415) (425:425:425)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (863:863:863) (757:757:757)) - (PORT datab (889:889:889) (770:770:770)) - (PORT datac (855:855:855) (742:742:742)) - (PORT datad (557:557:557) (537:537:537)) - (IOPATH dataa combout (408:408:408) (425:425:425)) - (IOPATH datab combout (415:415:415) (425:425:425)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (487:487:487) (431:431:431)) - (PORT datab (861:861:861) (762:762:762)) - (PORT datac (775:775:775) (623:623:623)) - (PORT datad (479:479:479) (407:407:407)) - (IOPATH dataa combout (377:377:377) (371:371:371)) - (IOPATH datab combout (384:384:384) (398:398:398)) - (IOPATH datac combout (301:301:301) (285:285:285)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5311:5311:5311) (5384:5384:5384)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (354:354:354) (418:418:418)) - (PORT datab (350:350:350) (409:409:409)) - (PORT datac (308:308:308) (375:375:375)) - (PORT datad (310:310:310) (371:371:371)) - (IOPATH dataa combout (420:420:420) (371:371:371)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datac combout (305:305:305) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT datac (799:799:799) (710:710:710)) - (PORT datad (557:557:557) (538:538:538)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (876:876:876) (757:757:757)) - (PORT datab (559:559:559) (549:549:549)) - (PORT datac (819:819:819) (718:718:718)) - (PORT datad (226:226:226) (233:233:233)) - (IOPATH dataa combout (349:349:349) (371:371:371)) - (IOPATH datab combout (354:354:354) (380:380:380)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (548:548:548) (528:528:528)) - (PORT datab (290:290:290) (298:298:298)) - (PORT datac (230:230:230) (245:245:245)) - (PORT datad (428:428:428) (359:359:359)) - (IOPATH dataa combout (428:428:428) (450:450:450)) - (IOPATH datab combout (357:357:357) (380:380:380)) - (IOPATH datac combout (301:301:301) (285:285:285)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|start_nedge) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5084:5084:5084) (5071:5071:5071)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (834:834:834) (727:727:727)) - (PORT datad (451:451:451) (388:388:388)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datab (327:327:327) (385:385:385)) - (PORT datac (300:300:300) (364:364:364)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datac combout (301:301:301) (283:283:283)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_obuf") - (INSTANCE tx\~output) - (DELAY - (ABSOLUTE - (PORT i (677:677:677) (772:772:772)) - (IOPATH i o (2961:2961:2961) (3013:3013:3013)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_clk\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (788:788:788) (813:813:813)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE sys_clk\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (175:175:175) (172:172:172)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (358:358:358) (435:435:435)) - (PORT datab (326:326:326) (384:384:384)) - (IOPATH dataa combout (408:408:408) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datab combout (415:415:415) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (437:437:437)) - (PORT datab (341:341:341) (404:404:404)) - (PORT datac (441:441:441) (375:375:375)) - (PORT datad (255:255:255) (273:273:273)) - (IOPATH dataa combout (374:374:374) (392:392:392)) - (IOPATH datab combout (384:384:384) (398:398:398)) - (IOPATH datac combout (305:305:305) (285:285:285)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_rst_n\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (748:748:748) (773:773:773)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (383:383:383)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~4) - (DELAY - (ABSOLUTE - (PORT datab (325:325:325) (382:382:382)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~0) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (384:384:384)) - (PORT datac (286:286:286) (352:352:352)) - (PORT datad (285:285:285) (344:344:344)) - (IOPATH datab combout (438:438:438) (455:455:455)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datad (304:304:304) (370:370:370)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (360:360:360) (437:437:437)) - (PORT datab (297:297:297) (313:313:313)) - (PORT datad (437:437:437) (371:371:371)) - (IOPATH dataa combout (394:394:394) (400:400:400)) - (IOPATH datab combout (400:400:400) (398:398:398)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (361:361:361) (438:438:438)) - (PORT datab (348:348:348) (411:411:411)) - (PORT datad (249:249:249) (266:266:266)) - (IOPATH dataa combout (351:351:351) (371:371:371)) - (IOPATH datab combout (357:357:357) (380:380:380)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (249:249:249) (266:266:266)) - (IOPATH datac combout (305:305:305) (285:285:285)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_flag) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (853:853:853) (737:737:737)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_flag) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (524:524:524) (501:501:501)) - (PORT datad (462:462:462) (399:399:399)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5084:5084:5084) (5071:5071:5071)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (571:571:571) (558:558:558)) - (PORT datab (323:323:323) (380:380:380)) - (IOPATH dataa combout (408:408:408) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datab combout (415:415:415) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (403:403:403)) - (IOPATH dataa combout (435:435:435) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (340:340:340) (395:395:395)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (330:330:330) (394:394:394)) - (PORT datab (329:329:329) (386:386:386)) - (PORT datac (285:285:285) (351:351:351)) - (PORT datad (285:285:285) (344:344:344)) - (IOPATH dataa combout (428:428:428) (449:449:449)) - (IOPATH datab combout (437:437:437) (407:407:407)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (559:559:559) (540:540:540)) - (PORT datab (329:329:329) (386:386:386)) - (PORT datac (517:517:517) (503:503:503)) - (PORT datad (230:230:230) (238:238:238)) - (IOPATH dataa combout (349:349:349) (377:377:377)) - (IOPATH datab combout (354:354:354) (380:380:380)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (404:404:404)) - (IOPATH dataa combout (428:428:428) (450:450:450)) - (IOPATH cin combout (549:549:549) (519:519:519)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT datab (617:617:617) (577:577:577)) - (PORT datad (556:556:556) (536:536:536)) - (IOPATH datab combout (380:380:380) (380:380:380)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (401:401:401)) - (IOPATH dataa combout (435:435:435) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (342:342:342) (402:402:402)) - (IOPATH dataa combout (435:435:435) (425:425:425)) - (IOPATH dataa cout (486:486:486) (375:375:375)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (545:545:545)) - (PORT datab (560:560:560) (536:536:536)) - (PORT datac (510:510:510) (500:500:500)) - (PORT datad (548:548:548) (519:519:519)) - (IOPATH dataa combout (351:351:351) (371:371:371)) - (IOPATH datab combout (357:357:357) (380:380:380)) - (IOPATH datac combout (301:301:301) (285:285:285)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (574:574:574) (561:561:561)) - (PORT datab (295:295:295) (303:303:303)) - (PORT datac (441:441:441) (377:377:377)) - (PORT datad (446:446:446) (387:387:387)) - (IOPATH dataa combout (428:428:428) (450:450:450)) - (IOPATH datab combout (357:357:357) (380:380:380)) - (IOPATH datac combout (301:301:301) (285:285:285)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT datab (339:339:339) (394:394:394)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT datab (325:325:325) (382:382:382)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (340:340:340) (396:396:396)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (326:326:326) (383:383:383)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (327:327:327) (384:384:384)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (340:340:340) (396:396:396)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datab cout (497:497:497) (381:381:381)) - (IOPATH datad combout (167:167:167) (143:143:143)) - (IOPATH cin combout (549:549:549) (519:519:519)) - (IOPATH cin cout (63:63:63) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1645:1645:1645) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5091:5091:5091) (5076:5076:5076)) - (PORT sclr (850:850:850) (911:911:911)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD sclr (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (806:806:806) (638:638:638)) - (PORT datab (619:619:619) (579:579:579)) - (PORT datac (514:514:514) (445:445:445)) - (PORT datad (557:557:557) (537:537:537)) - (IOPATH dataa combout (420:420:420) (371:371:371)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datac combout (305:305:305) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5084:5084:5084) (5071:5071:5071)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datac (299:299:299) (363:363:363)) - (PORT datad (305:305:305) (364:364:364)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (749:749:749) (610:610:610)) - (PORT datab (310:310:310) (323:323:323)) - (PORT datad (504:504:504) (435:435:435)) - (IOPATH dataa combout (435:435:435) (407:407:407)) - (IOPATH datab combout (438:438:438) (455:455:455)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (285:285:285)) - (PORT datab (294:294:294) (302:302:302)) - (PORT datad (461:461:461) (398:398:398)) - (IOPATH dataa combout (435:435:435) (407:407:407)) - (IOPATH datab combout (438:438:438) (455:455:455)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5084:5084:5084) (5071:5071:5071)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~0) - (DELAY - (ABSOLUTE - (PORT datab (345:345:345) (403:403:403)) - (PORT datad (307:307:307) (365:365:365)) - (IOPATH datab combout (380:380:380) (380:380:380)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (392:392:392) (474:474:474)) - (PORT datab (404:404:404) (474:474:474)) - (PORT datac (328:328:328) (404:404:404)) - (PORT datad (478:478:478) (406:406:406)) - (IOPATH dataa combout (373:373:373) (380:380:380)) - (IOPATH datab combout (377:377:377) (380:380:380)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (581:581:581) (577:577:577)) - (PORT datab (307:307:307) (320:320:320)) - (PORT datad (816:816:816) (723:723:723)) - (IOPATH dataa combout (375:375:375) (371:371:371)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE rx\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (778:778:778) (803:803:803)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg1\~0) - (DELAY - (ABSOLUTE - (PORT datad (3220:3220:3220) (3254:3254:3254)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg1) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5084:5084:5084) (5071:5071:5071)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg2\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (280:280:280) (335:335:335)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg2) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5084:5084:5084) (5071:5071:5071)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (289:289:289) (348:348:348)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg3) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5084:5084:5084) (5071:5071:5071)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT datad (794:794:794) (704:704:704)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (359:359:359) (436:436:436)) - (PORT datab (295:295:295) (310:310:310)) - (PORT datad (300:300:300) (365:365:365)) - (IOPATH dataa combout (435:435:435) (407:407:407)) - (IOPATH datab combout (438:438:438) (455:455:455)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT asdata (1210:1210:1210) (1123:1123:1123)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (642:642:642) (591:591:591)) - (PORT datab (307:307:307) (321:321:321)) - (PORT datad (507:507:507) (438:438:438)) - (IOPATH dataa combout (435:435:435) (419:419:419)) - (IOPATH datab combout (438:438:438) (455:455:455)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (445:445:445)) - (PORT datab (401:401:401) (472:472:472)) - (PORT datad (347:347:347) (427:427:427)) - (IOPATH dataa combout (435:435:435) (407:407:407)) - (IOPATH datab combout (437:437:437) (407:407:407)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~5) - (DELAY - (ABSOLUTE - (PORT dataa (343:343:343) (403:403:403)) - (PORT datab (269:269:269) (276:276:276)) - (PORT datac (532:532:532) (534:534:534)) - (PORT datad (517:517:517) (502:502:502)) - (IOPATH dataa combout (428:428:428) (450:450:450)) - (IOPATH datab combout (380:380:380) (380:380:380)) - (IOPATH datac combout (301:301:301) (285:285:285)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (303:303:303) (359:359:359)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT asdata (1212:1212:1212) (1107:1107:1107)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (800:800:800) (702:702:702)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT asdata (1225:1225:1225) (1128:1128:1128)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT asdata (1179:1179:1179) (1099:1099:1099)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (798:798:798) (704:704:704)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT asdata (1175:1175:1175) (1097:1097:1097)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT asdata (1553:1553:1553) (1357:1357:1357)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (478:478:478)) - (PORT datab (320:320:320) (375:375:375)) - (PORT datad (367:367:367) (442:442:442)) - (IOPATH dataa combout (414:414:414) (444:444:444)) - (IOPATH datab combout (380:380:380) (380:380:380)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (393:393:393) (476:476:476)) - (PORT datab (318:318:318) (373:373:373)) - (PORT datad (228:228:228) (235:235:235)) - (IOPATH dataa combout (408:408:408) (425:425:425)) - (IOPATH datab combout (415:415:415) (425:425:425)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (301:301:301) (365:365:365)) - (IOPATH datac combout (305:305:305) (285:285:285)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (497:497:497) (480:480:480)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT asdata (1246:1246:1246) (1145:1145:1145)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (300:300:300) (364:364:364)) - (IOPATH datac combout (305:305:305) (285:285:285)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1644:1644:1644) (1663:1663:1663)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (5097:5097:5097) (5081:5081:5081)) - (PORT ena (968:968:968) (937:937:937)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT asdata (1236:1236:1236) (1138:1138:1138)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (PORT ena (1637:1637:1637) (1491:1491:1491)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (195:195:195)) - (HOLD ena (posedge clk) (195:195:195)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~3) - (DELAY - (ABSOLUTE - (PORT dataa (320:320:320) (379:379:379)) - (PORT datab (410:410:410) (481:481:481)) - (PORT datad (354:354:354) (434:434:434)) - (IOPATH dataa combout (351:351:351) (371:371:371)) - (IOPATH datab combout (423:423:423) (391:391:391)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~4) - (DELAY - (ABSOLUTE - (PORT dataa (395:395:395) (478:478:478)) - (PORT datab (407:407:407) (478:478:478)) - (PORT datad (227:227:227) (234:234:234)) - (IOPATH dataa combout (420:420:420) (371:371:371)) - (IOPATH datab combout (423:423:423) (451:451:451)) - (IOPATH datac combout (415:415:415) (429:429:429)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~6) - (DELAY - (ABSOLUTE - (PORT dataa (578:578:578) (575:575:575)) - (PORT datab (558:558:558) (545:545:545)) - (PORT datac (234:234:234) (252:252:252)) - (PORT datad (228:228:228) (235:235:235)) - (IOPATH dataa combout (394:394:394) (400:400:400)) - (IOPATH datab combout (437:437:437) (425:425:425)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~7) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (446:446:446)) - (PORT datab (269:269:269) (276:276:276)) - (PORT datac (234:234:234) (253:253:253)) - (PORT datad (227:227:227) (234:234:234)) - (IOPATH dataa combout (408:408:408) (425:425:425)) - (IOPATH datab combout (423:423:423) (453:453:453)) - (IOPATH datac combout (301:301:301) (283:283:283)) - (IOPATH datad combout (167:167:167) (143:143:143)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|tx) - (DELAY - (ABSOLUTE - (PORT clk (1646:1646:1646) (1665:1665:1665)) - (PORT d (90:90:90) (101:101:101)) - (PORT clrn (4857:4857:4857) (4790:4790:4790)) - (IOPATH (posedge clk) q (240:240:240) (240:240:240)) - (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (195:195:195)) - ) - ) -) diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_slow.vo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_slow.vo deleted file mode 100644 index b3f326c..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_slow.vo +++ /dev/null @@ -1,2836 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - -// VENDOR "Altera" -// PROGRAM "Quartus II 64-Bit" -// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" - -// DATE "06/02/2023 03:03:50" - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This Verilog file should be used for ModelSim (Verilog) only -// - -`timescale 1 ps/ 1 ps - -module rs232 ( - sys_clk, - sys_rst_n, - rx, - tx); -input sys_clk; -input sys_rst_n; -input rx; -output tx; - -// Design Ports Information -// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default -// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default -// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default -// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default - - -wire gnd; -wire vcc; -wire unknown; - -assign gnd = 1'b0; -assign vcc = 1'b1; -assign unknown = 1'bx; - -tri1 devclrn; -tri1 devpor; -tri1 devoe; -// synopsys translate_off -initial $sdf_annotate("rs232_8_1200mv_85c_v_slow.sdo"); -// synopsys translate_on - -wire \uart_tx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[0]~13_combout ; -wire \uart_rx_inst|baud_cnt[0]~14 ; -wire \uart_rx_inst|baud_cnt[1]~15_combout ; -wire \uart_rx_inst|baud_cnt[1]~16 ; -wire \uart_rx_inst|baud_cnt[2]~17_combout ; -wire \uart_rx_inst|baud_cnt[2]~18 ; -wire \uart_rx_inst|baud_cnt[3]~19_combout ; -wire \uart_rx_inst|baud_cnt[3]~20 ; -wire \uart_rx_inst|baud_cnt[4]~21_combout ; -wire \uart_rx_inst|baud_cnt[4]~22 ; -wire \uart_rx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[5]~24 ; -wire \uart_rx_inst|baud_cnt[6]~25_combout ; -wire \uart_rx_inst|baud_cnt[6]~26 ; -wire \uart_rx_inst|baud_cnt[7]~27_combout ; -wire \uart_rx_inst|baud_cnt[7]~28 ; -wire \uart_rx_inst|baud_cnt[8]~29_combout ; -wire \uart_rx_inst|baud_cnt[8]~30 ; -wire \uart_rx_inst|baud_cnt[9]~31_combout ; -wire \uart_rx_inst|baud_cnt[9]~32 ; -wire \uart_rx_inst|baud_cnt[10]~33_combout ; -wire \uart_rx_inst|baud_cnt[10]~34 ; -wire \uart_rx_inst|baud_cnt[11]~35_combout ; -wire \uart_rx_inst|baud_cnt[11]~36 ; -wire \uart_rx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal2~0_combout ; -wire \uart_tx_inst|Add1~0_combout ; -wire \uart_tx_inst|Add1~1_combout ; -wire \uart_rx_inst|bit_flag~q ; -wire \uart_rx_inst|Equal1~0_combout ; -wire \uart_rx_inst|Equal2~0_combout ; -wire \uart_rx_inst|Equal2~1_combout ; -wire \uart_rx_inst|Equal2~2_combout ; -wire \uart_rx_inst|work_en~q ; -wire \uart_rx_inst|Equal1~1_combout ; -wire \uart_rx_inst|Equal1~2_combout ; -wire \uart_rx_inst|Equal1~3_combout ; -wire \uart_rx_inst|always5~0_combout ; -wire \uart_rx_inst|start_nedge~q ; -wire \uart_rx_inst|work_en~0_combout ; -wire \uart_rx_inst|always3~0_combout ; -wire \tx~output_o ; -wire \sys_clk~input_o ; -wire \sys_clk~inputclkctrl_outclk ; -wire \uart_rx_inst|Add1~0_combout ; -wire \uart_rx_inst|bit_cnt~1_combout ; -wire \sys_rst_n~input_o ; -wire \uart_rx_inst|Add1~1 ; -wire \uart_rx_inst|Add1~2_combout ; -wire \uart_rx_inst|Add1~3 ; -wire \uart_rx_inst|Add1~4_combout ; -wire \uart_rx_inst|always4~0_combout ; -wire \uart_rx_inst|Add1~5 ; -wire \uart_rx_inst|Add1~6_combout ; -wire \uart_rx_inst|bit_cnt~0_combout ; -wire \uart_rx_inst|always4~1_combout ; -wire \uart_rx_inst|rx_flag~feeder_combout ; -wire \uart_rx_inst|rx_flag~q ; -wire \uart_rx_inst|po_flag~feeder_combout ; -wire \uart_rx_inst|po_flag~q ; -wire \uart_tx_inst|work_en~0_combout ; -wire \uart_tx_inst|work_en~q ; -wire \uart_tx_inst|baud_cnt[0]~13_combout ; -wire \uart_tx_inst|baud_cnt[10]~34 ; -wire \uart_tx_inst|baud_cnt[11]~35_combout ; -wire \uart_tx_inst|Equal1~0_combout ; -wire \uart_tx_inst|Equal1~1_combout ; -wire \uart_tx_inst|baud_cnt[11]~36 ; -wire \uart_tx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal1~3_combout ; -wire \uart_tx_inst|baud_cnt[2]~17_combout ; -wire \uart_tx_inst|baud_cnt[4]~21_combout ; -wire \uart_tx_inst|Equal1~2_combout ; -wire \uart_tx_inst|always1~0_combout ; -wire \uart_tx_inst|baud_cnt[0]~14 ; -wire \uart_tx_inst|baud_cnt[1]~15_combout ; -wire \uart_tx_inst|baud_cnt[1]~16 ; -wire \uart_tx_inst|baud_cnt[2]~18 ; -wire \uart_tx_inst|baud_cnt[3]~19_combout ; -wire \uart_tx_inst|baud_cnt[3]~20 ; -wire \uart_tx_inst|baud_cnt[4]~22 ; -wire \uart_tx_inst|baud_cnt[5]~24 ; -wire \uart_tx_inst|baud_cnt[6]~25_combout ; -wire \uart_tx_inst|baud_cnt[6]~26 ; -wire \uart_tx_inst|baud_cnt[7]~27_combout ; -wire \uart_tx_inst|baud_cnt[7]~28 ; -wire \uart_tx_inst|baud_cnt[8]~29_combout ; -wire \uart_tx_inst|baud_cnt[8]~30 ; -wire \uart_tx_inst|baud_cnt[9]~31_combout ; -wire \uart_tx_inst|baud_cnt[9]~32 ; -wire \uart_tx_inst|baud_cnt[10]~33_combout ; -wire \uart_tx_inst|Equal2~1_combout ; -wire \uart_tx_inst|bit_flag~q ; -wire \uart_tx_inst|always3~0_combout ; -wire \uart_tx_inst|bit_cnt[2]~2_combout ; -wire \uart_tx_inst|bit_cnt[3]~4_combout ; -wire \uart_tx_inst|always0~0_combout ; -wire \uart_tx_inst|always0~1_combout ; -wire \uart_tx_inst|bit_cnt[0]~5_combout ; -wire \rx~input_o ; -wire \uart_rx_inst|rx_reg1~0_combout ; -wire \uart_rx_inst|rx_reg1~q ; -wire \uart_rx_inst|rx_reg2~feeder_combout ; -wire \uart_rx_inst|rx_reg2~q ; -wire \uart_rx_inst|rx_reg3~feeder_combout ; -wire \uart_rx_inst|rx_reg3~q ; -wire \uart_rx_inst|rx_data[7]~0_combout ; -wire \uart_rx_inst|always8~0_combout ; -wire \uart_tx_inst|bit_cnt[1]~3_combout ; -wire \uart_tx_inst|tx~2_combout ; -wire \uart_tx_inst|tx~5_combout ; -wire \uart_rx_inst|rx_data[6]~feeder_combout ; -wire \uart_rx_inst|po_data[5]~feeder_combout ; -wire \uart_rx_inst|po_data[4]~feeder_combout ; -wire \uart_tx_inst|Mux0~0_combout ; -wire \uart_tx_inst|Mux0~1_combout ; -wire \uart_rx_inst|rx_data[2]~feeder_combout ; -wire \uart_rx_inst|rx_data[1]~feeder_combout ; -wire \uart_rx_inst|rx_data[0]~feeder_combout ; -wire \uart_tx_inst|tx~3_combout ; -wire \uart_tx_inst|tx~4_combout ; -wire \uart_tx_inst|tx~6_combout ; -wire \uart_tx_inst|tx~7_combout ; -wire \uart_tx_inst|tx~q ; -wire [7:0] \uart_rx_inst|rx_data ; -wire [7:0] \uart_rx_inst|po_data ; -wire [3:0] \uart_rx_inst|bit_cnt ; -wire [12:0] \uart_rx_inst|baud_cnt ; -wire [3:0] \uart_tx_inst|bit_cnt ; -wire [12:0] \uart_tx_inst|baud_cnt ; - - -// Location: FF_X6_Y9_N13 -dffeas \uart_tx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[4]~22 ), - .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_tx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; -defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X10_Y9_N5 -dffeas \uart_rx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N7 -dffeas \uart_rx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N19 -dffeas \uart_rx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N21 -dffeas \uart_rx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N11 -dffeas \uart_rx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N15 -dffeas \uart_rx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N9 -dffeas \uart_rx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N13 -dffeas \uart_rx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N23 -dffeas \uart_rx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N27 -dffeas \uart_rx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N17 -dffeas \uart_rx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N25 -dffeas \uart_rx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N29 -dffeas \uart_rx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) -// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_rx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[0]~14 ), - .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_rx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) -// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[1]~16 ), - .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_rx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) - - .dataa(\uart_rx_inst|baud_cnt [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[2]~18 ), - .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_rx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) -// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[3]~20 ), - .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_rx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[4]~22 ), - .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_rx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) -// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[5]~24 ), - .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_rx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[6]~26 ), - .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_rx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) -// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[7]~28 ), - .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_rx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[8]~30 ), - .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_rx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) -// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [10]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[9]~32 ), - .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_rx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) - - .dataa(\uart_rx_inst|baud_cnt [11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[10]~34 ), - .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_rx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|baud_cnt [12]), - .cin(\uart_rx_inst|baud_cnt[11]~36 ), - .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; -defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y9_N23 -dffeas \uart_rx_inst|po_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [2]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( -// Equation(s): -// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [6]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; -defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( -// Equation(s): -// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(gnd), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; -defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( -// Equation(s): -// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|bit_cnt [1]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; -defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N11 -dffeas \uart_rx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Equal2~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( -// Equation(s): -// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(\uart_rx_inst|baud_cnt [0]), - .datad(\uart_rx_inst|baud_cnt [8]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( -// Equation(s): -// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) - - .dataa(\uart_rx_inst|baud_cnt [5]), - .datab(\uart_rx_inst|baud_cnt [3]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( -// Equation(s): -// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) - - .dataa(\uart_rx_inst|baud_cnt [9]), - .datab(\uart_rx_inst|baud_cnt [11]), - .datac(\uart_rx_inst|baud_cnt [6]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( -// Equation(s): -// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) - - .dataa(\uart_rx_inst|Equal2~1_combout ), - .datab(\uart_rx_inst|baud_cnt [12]), - .datac(\uart_rx_inst|Equal1~0_combout ), - .datad(\uart_rx_inst|Equal2~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; -defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X9_Y9_N17 -dffeas \uart_rx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_rx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( -// Equation(s): -// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( -// Equation(s): -// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|baud_cnt [11]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; -defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( -// Equation(s): -// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) - - .dataa(\uart_rx_inst|baud_cnt [12]), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(\uart_rx_inst|baud_cnt [9]), - .datad(\uart_rx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; -defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|always5~0 ( -// Equation(s): -// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|Equal1~0_combout ), - .datac(\uart_rx_inst|Equal1~1_combout ), - .datad(\uart_rx_inst|Equal1~3_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always5~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; -defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N13 -dffeas \uart_rx_inst|start_nedge ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|always3~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|start_nedge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; -defparam \uart_rx_inst|start_nedge .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( -// Equation(s): -// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|start_nedge~q ), - .datac(\uart_rx_inst|work_en~q ), - .datad(\uart_rx_inst|always4~1_combout ), - .cin(gnd), - .combout(\uart_rx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|always3~0 ( -// Equation(s): -// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) - - .dataa(gnd), - .datab(\uart_rx_inst|rx_reg2~q ), - .datac(\uart_rx_inst|rx_reg3~q ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; -defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOOBUF_X0_Y9_N16 -cycloneive_io_obuf \tx~output ( - .i(!\uart_tx_inst|tx~q ), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(\tx~output_o ), - .obar()); -// synopsys translate_off -defparam \tx~output .bus_hold = "false"; -defparam \tx~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y15_N22 -cycloneive_io_ibuf \sys_clk~input ( - .i(sys_clk), - .ibar(gnd), - .o(\sys_clk~input_o )); -// synopsys translate_off -defparam \sys_clk~input .bus_hold = "false"; -defparam \sys_clk~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G8 -cycloneive_clkctrl \sys_clk~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\sys_clk~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\sys_clk~inputclkctrl_outclk )); -// synopsys translate_off -defparam \sys_clk~inputclkctrl .clock_type = "global clock"; -defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( -// Equation(s): -// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) -// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|Add1~0_combout ), - .cout(\uart_rx_inst|Add1~1 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; -defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(\uart_rx_inst|Add1~0_combout ), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; -defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y4_N1 -cycloneive_io_ibuf \sys_rst_n~input ( - .i(sys_rst_n), - .ibar(gnd), - .o(\sys_rst_n~input_o )); -// synopsys translate_off -defparam \sys_rst_n~input .bus_hold = "false"; -defparam \sys_rst_n~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X8_Y9_N5 -dffeas \uart_rx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( -// Equation(s): -// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) -// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~1 ), - .combout(\uart_rx_inst|Add1~2_combout ), - .cout(\uart_rx_inst|Add1~3 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N19 -dffeas \uart_rx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( -// Equation(s): -// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) -// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~3 ), - .combout(\uart_rx_inst|Add1~4_combout ), - .cout(\uart_rx_inst|Add1~5 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N21 -dffeas \uart_rx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|always4~0 ( -// Equation(s): -// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(\uart_rx_inst|bit_cnt [0]), - .datad(\uart_rx_inst|bit_cnt [2]), - .cin(gnd), - .combout(\uart_rx_inst|always4~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; -defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( -// Equation(s): -// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(\uart_rx_inst|Add1~5 ), - .combout(\uart_rx_inst|Add1~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; -defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(\uart_rx_inst|bit_cnt [3]), - .datad(\uart_rx_inst|Add1~6_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; -defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N1 -dffeas \uart_rx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|always4~1 ( -// Equation(s): -// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always4~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; -defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( -// Equation(s): -// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|always4~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N15 -dffeas \uart_rx_inst|rx_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( -// Equation(s): -// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_flag~q ), - .cin(gnd), - .combout(\uart_rx_inst|po_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N31 -dffeas \uart_rx_inst|po_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( -// Equation(s): -// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|po_flag~q ), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N15 -dffeas \uart_tx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_tx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) -// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_tx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) -// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) - - .dataa(\uart_tx_inst|baud_cnt [10]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[9]~32 ), - .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_tx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [11]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[10]~34 ), - .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_tx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N25 -dffeas \uart_tx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( -// Equation(s): -// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(\uart_tx_inst|baud_cnt [3]), - .datad(\uart_tx_inst|baud_cnt [7]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; -defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N0 -cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( -// Equation(s): -// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) - - .dataa(\uart_tx_inst|baud_cnt [9]), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(\uart_tx_inst|baud_cnt [11]), - .datad(\uart_tx_inst|Equal1~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; -defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) - - .dataa(\uart_tx_inst|baud_cnt [12]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\uart_tx_inst|baud_cnt[11]~36 ), - .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; -defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N27 -dffeas \uart_tx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( -// Equation(s): -// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [12]), - .datac(gnd), - .datad(\uart_tx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) -// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) - - .dataa(\uart_tx_inst|baud_cnt [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[1]~16 ), - .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_tx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N7 -dffeas \uart_tx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) -// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[3]~20 ), - .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_tx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N11 -dffeas \uart_tx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( -// Equation(s): -// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) - - .dataa(\uart_tx_inst|baud_cnt [6]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; -defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N30 -cycloneive_lcell_comb \uart_tx_inst|always1~0 ( -// Equation(s): -// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|Equal1~1_combout ), - .datac(\uart_tx_inst|Equal1~3_combout ), - .datad(\uart_tx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; -defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X6_Y9_N3 -dffeas \uart_tx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[0]~14 ), - .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_tx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N5 -dffeas \uart_tx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [3]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[2]~18 ), - .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_tx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N9 -dffeas \uart_tx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) -// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[5]~24 ), - .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_tx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N15 -dffeas \uart_tx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[6]~26 ), - .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_tx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N17 -dffeas \uart_tx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) -// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[7]~28 ), - .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_tx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N19 -dffeas \uart_tx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[8]~30 ), - .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_tx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N21 -dffeas \uart_tx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X6_Y9_N23 -dffeas \uart_tx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( -// Equation(s): -// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) - - .dataa(\uart_tx_inst|Equal2~0_combout ), - .datab(\uart_tx_inst|baud_cnt [10]), - .datac(\uart_tx_inst|Equal1~1_combout ), - .datad(\uart_tx_inst|baud_cnt [12]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; -defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N21 -dffeas \uart_tx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|Equal2~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|always3~0 ( -// Equation(s): -// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; -defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) - - .dataa(\uart_tx_inst|Add1~0_combout ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; -defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N27 -dffeas \uart_tx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[2]~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) - - .dataa(\uart_tx_inst|Add1~1_combout ), - .datab(\uart_tx_inst|always3~0_combout ), - .datac(\uart_tx_inst|bit_cnt [3]), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; -defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[3]~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|always0~0 ( -// Equation(s): -// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) - - .dataa(gnd), - .datab(\uart_tx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|always0~1 ( -// Equation(s): -// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; -defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [0]), - .datad(\uart_tx_inst|work_en~q ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; -defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[0]~5_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y8_N1 -cycloneive_io_ibuf \rx~input ( - .i(rx), - .ibar(gnd), - .o(\rx~input_o )); -// synopsys translate_off -defparam \rx~input .bus_hold = "false"; -defparam \rx~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( -// Equation(s): -// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\rx~input_o ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N19 -dffeas \uart_rx_inst|rx_reg1 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg1~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg1~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg2~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N1 -dffeas \uart_rx_inst|rx_reg2 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg2~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg2~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N27 -dffeas \uart_rx_inst|rx_reg3 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg3~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( -// Equation(s): -// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg3~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|always8~0 ( -// Equation(s): -// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|always8~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; -defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N29 -dffeas \uart_rx_inst|rx_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[7]~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N5 -dffeas \uart_rx_inst|po_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [7]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [1]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; -defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N7 -dffeas \uart_tx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[1]~3_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|tx~2 ( -// Equation(s): -// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [7]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; -defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|tx~5 ( -// Equation(s): -// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) - - .dataa(\uart_tx_inst|tx~q ), - .datab(\uart_tx_inst|tx~2_combout ), - .datac(\uart_tx_inst|bit_flag~q ), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|tx~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; -defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [7]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N3 -dffeas \uart_rx_inst|rx_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[6]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N7 -dffeas \uart_rx_inst|rx_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [5]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N21 -dffeas \uart_rx_inst|po_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[5]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N15 -dffeas \uart_rx_inst|po_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N31 -dffeas \uart_rx_inst|rx_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [5]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [4]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N1 -dffeas \uart_rx_inst|po_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[4]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N23 -dffeas \uart_rx_inst|rx_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [4]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N25 -dffeas \uart_rx_inst|po_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [3]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( -// Equation(s): -// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [4]), - .datac(\uart_rx_inst|po_data [3]), - .datad(\uart_tx_inst|bit_cnt [0]), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; -defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( -// Equation(s): -// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & -// (((\uart_tx_inst|Mux0~0_combout )))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [5]), - .datac(\uart_rx_inst|po_data [6]), - .datad(\uart_tx_inst|Mux0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; -defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [3]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N9 -dffeas \uart_rx_inst|rx_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[2]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [2]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N27 -dffeas \uart_rx_inst|rx_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[1]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N19 -dffeas \uart_rx_inst|po_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [1]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [1]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N13 -dffeas \uart_rx_inst|rx_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[0]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N29 -dffeas \uart_rx_inst|po_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [0]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|tx~3 ( -// Equation(s): -// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) - - .dataa(\uart_rx_inst|po_data [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [0]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; -defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|tx~4 ( -// Equation(s): -// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [1]), - .datad(\uart_tx_inst|tx~3_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; -defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|tx~6 ( -// Equation(s): -// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|bit_cnt [2]), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~4_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; -defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|tx~7 ( -// Equation(s): -// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # -// (!\uart_tx_inst|tx~6_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|tx~5_combout ), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~6_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~7_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; -defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N13 -dffeas \uart_tx_inst|tx ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|tx~7_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|tx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|tx .is_wysiwyg = "true"; -defparam \uart_tx_inst|tx .power_up = "low"; -// synopsys translate_on - -assign tx = \tx~output_o ; - -endmodule diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_v_slow.sdo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_v_slow.sdo deleted file mode 100644 index 588ece3..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_v_slow.sdo +++ /dev/null @@ -1,2275 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This file contains Slow Corner delays for the design using part EP4CE15F23C8, -// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius -// - -// -// This SDF file should be used for ModelSim (Verilog) only -// - -(DELAYFILE - (SDFVERSION "2.1") - (DESIGN "rs232") - (DATE "06/02/2023 03:03:50") - (VENDOR "Altera") - (PROGRAM "Quartus II 64-Bit") - (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") - (DIVIDER .) - (TIMESCALE 1 ps) - - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (590:590:590)) - (PORT datab (341:341:341) (422:422:422)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (367:367:367) (448:448:448)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (457:457:457)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (461:461:461)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (368:368:368) (452:452:452)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (422:422:422)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (543:543:543) (580:580:580)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (471:471:471)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT datad (533:533:533) (560:560:560)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1301:1301:1301) (1261:1261:1261)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (642:642:642)) - (PORT datab (577:577:577) (601:601:601)) - (PORT datac (526:526:526) (560:560:560)) - (PORT datad (541:541:541) (560:560:560)) - (IOPATH dataa combout (456:456:456) (486:486:486)) - (IOPATH datab combout (457:457:457) (489:489:489)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (487:487:487)) - (PORT datab (429:429:429) (538:538:538)) - (PORT datad (372:372:372) (479:479:479)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH datab combout (435:435:435) (433:433:433)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (654:654:654)) - (PORT datab (570:570:570) (590:590:590)) - (PORT datac (573:573:573) (591:591:591)) - (PORT datad (330:330:330) (407:407:407)) - (IOPATH dataa combout (432:432:432) (446:446:446)) - (IOPATH datab combout (437:437:437) (436:436:436)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (434:434:434)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (301:301:301) (385:385:385)) - (PORT datad (304:304:304) (381:381:381)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (830:830:830)) - (PORT datab (575:575:575) (601:601:601)) - (PORT datac (579:579:579) (594:594:594)) - (PORT datad (851:851:851) (810:810:810)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (854:854:854)) - (PORT datab (901:901:901) (869:869:869)) - (PORT datac (872:872:872) (840:840:840)) - (PORT datad (577:577:577) (599:599:599)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (485:485:485)) - (PORT datab (878:878:878) (859:859:859)) - (PORT datac (783:783:783) (700:700:700)) - (PORT datad (485:485:485) (457:457:457)) - (IOPATH dataa combout (405:405:405) (398:398:398)) - (IOPATH datab combout (432:432:432) (433:433:433)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1854:1854:1854)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6063:6063:6063) (5936:5936:5936)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (464:464:464)) - (PORT datab (370:370:370) (454:454:454)) - (PORT datac (330:330:330) (415:415:415)) - (PORT datad (331:331:331) (408:408:408)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT datac (822:822:822) (795:795:795)) - (PORT datad (577:577:577) (600:600:600)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (854:854:854)) - (PORT datab (579:579:579) (612:612:612)) - (PORT datac (827:827:827) (807:807:807)) - (PORT datad (237:237:237) (255:255:255)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (592:592:592)) - (PORT datab (304:304:304) (328:328:328)) - (PORT datac (240:240:240) (267:267:267)) - (PORT datad (433:433:433) (406:406:406)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|start_nedge) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (849:849:849) (813:813:813)) - (PORT datad (461:461:461) (436:436:436)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datab (345:345:345) (425:425:425)) - (PORT datac (323:323:323) (401:401:401)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_obuf") - (INSTANCE tx\~output) - (DELAY - (ABSOLUTE - (PORT i (758:758:758) (794:794:794)) - (IOPATH i o (3336:3336:3336) (3399:3399:3399)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_clk\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (806:806:806) (852:852:852)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE sys_clk\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (200:200:200) (189:189:189)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (482:482:482)) - (PORT datab (342:342:342) (423:423:423)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (484:484:484)) - (PORT datab (360:360:360) (449:449:449)) - (PORT datac (448:448:448) (419:419:419)) - (PORT datad (267:267:267) (303:303:303)) - (IOPATH dataa combout (420:420:420) (428:428:428)) - (IOPATH datab combout (432:432:432) (433:433:433)) - (IOPATH datac combout (327:327:327) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_rst_n\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (766:766:766) (812:812:812)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (424:424:424)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~4) - (DELAY - (ABSOLUTE - (PORT datab (343:343:343) (422:422:422)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~0) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (PORT datac (303:303:303) (388:388:388)) - (PORT datad (303:303:303) (379:379:379)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datad (323:323:323) (410:410:410)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (484:484:484)) - (PORT datab (308:308:308) (347:347:347)) - (PORT datad (441:441:441) (417:417:417)) - (IOPATH dataa combout (432:432:432) (446:446:446)) - (IOPATH datab combout (437:437:437) (436:436:436)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (485:485:485)) - (PORT datab (366:366:366) (456:456:456)) - (PORT datad (261:261:261) (295:295:295)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (265:265:265) (290:290:290)) - (IOPATH datac combout (327:327:327) (316:316:316)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_flag) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (866:866:866) (834:834:834)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_flag) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (535:535:535) (562:562:562)) - (PORT datad (475:475:475) (448:448:448)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (629:629:629)) - (PORT datab (339:339:339) (421:421:421)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (447:447:447)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (436:436:436)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (302:302:302) (387:387:387)) - (PORT datad (302:302:302) (379:379:379)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (472:472:472) (452:452:452)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (604:604:604)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (538:538:538) (561:561:561)) - (PORT datad (241:241:241) (260:260:260)) - (IOPATH dataa combout (392:392:392) (407:407:407)) - (IOPATH datab combout (393:393:393) (412:412:412)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (449:449:449)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH cin combout (607:607:607) (577:577:577)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT datab (635:635:635) (646:646:646)) - (PORT datad (575:575:575) (598:598:598)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (446:446:446)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (446:446:446)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (613:613:613)) - (PORT datab (578:578:578) (602:602:602)) - (PORT datac (526:526:526) (560:560:560)) - (PORT datad (560:560:560) (584:584:584)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (633:633:633)) - (PORT datab (308:308:308) (333:333:333)) - (PORT datac (450:450:450) (425:425:425)) - (PORT datad (454:454:454) (432:432:432)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (435:435:435)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (421:421:421)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (343:343:343) (422:422:422)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (726:726:726)) - (PORT datab (636:636:636) (648:648:648)) - (PORT datac (524:524:524) (497:497:497)) - (PORT datad (576:576:576) (598:598:598)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datac (321:321:321) (399:399:399)) - (PORT datad (329:329:329) (402:402:402)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (756:756:756) (694:694:694)) - (PORT datab (322:322:322) (359:359:359)) - (PORT datad (517:517:517) (486:486:486)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (315:315:315)) - (PORT datab (308:308:308) (332:332:332)) - (PORT datad (474:474:474) (447:447:447)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~0) - (DELAY - (ABSOLUTE - (PORT datab (367:367:367) (446:446:446)) - (PORT datad (330:330:330) (403:403:403)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (528:528:528)) - (PORT datab (425:425:425) (533:533:533)) - (PORT datac (346:346:346) (445:445:445)) - (PORT datad (485:485:485) (457:457:457)) - (IOPATH dataa combout (421:421:421) (418:418:418)) - (IOPATH datab combout (407:407:407) (408:408:408)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (643:643:643)) - (PORT datab (320:320:320) (356:356:356)) - (PORT datad (836:836:836) (817:817:817)) - (IOPATH dataa combout (404:404:404) (398:398:398)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE rx\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (796:796:796) (842:842:842)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg1\~0) - (DELAY - (ABSOLUTE - (PORT datad (3626:3626:3626) (3787:3787:3787)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg1) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg2\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (298:298:298) (368:368:368)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg2) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (307:307:307) (384:384:384)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg3) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT datad (819:819:819) (787:787:787)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (483:483:483)) - (PORT datab (306:306:306) (344:344:344)) - (PORT datad (318:318:318) (405:405:405)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1271:1271:1271) (1242:1242:1242)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (663:663:663)) - (PORT datab (320:320:320) (357:357:357)) - (PORT datad (520:520:520) (490:490:490)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (492:492:492)) - (PORT datab (423:423:423) (530:530:530)) - (PORT datad (367:367:367) (473:473:473)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (472:472:472) (452:452:452)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~5) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (448:448:448)) - (PORT datab (278:278:278) (304:304:304)) - (PORT datac (549:549:549) (592:592:592)) - (PORT datad (538:538:538) (558:558:558)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (325:325:325) (396:396:396)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT asdata (1261:1261:1261) (1233:1233:1233)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (791:791:791)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1280:1280:1280) (1251:1251:1251)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT asdata (1244:1244:1244) (1213:1213:1213)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (809:809:809) (792:792:792)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT asdata (1240:1240:1240) (1212:1212:1212)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1606:1606:1606) (1505:1505:1505)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (532:532:532)) - (PORT datab (336:336:336) (413:413:413)) - (PORT datad (389:389:389) (495:495:495)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (529:529:529)) - (PORT datab (335:335:335) (411:411:411)) - (PORT datad (238:238:238) (257:257:257)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (323:323:323) (402:402:402)) - (IOPATH datac combout (327:327:327) (316:316:316)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (511:511:511) (537:537:537)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1299:1299:1299) (1269:1269:1269)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (323:323:323) (401:401:401)) - (IOPATH datac combout (327:327:327) (316:316:316)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1290:1290:1290) (1262:1262:1262)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~3) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (420:420:420)) - (PORT datab (431:431:431) (540:540:540)) - (PORT datad (374:374:374) (481:481:481)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (455:455:455) (436:436:436)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~4) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (531:531:531)) - (PORT datab (429:429:429) (537:537:537)) - (PORT datad (238:238:238) (256:256:256)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~6) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (641:641:641)) - (PORT datab (580:580:580) (608:608:608)) - (PORT datac (245:245:245) (276:276:276)) - (PORT datad (239:239:239) (257:257:257)) - (IOPATH dataa combout (432:432:432) (446:446:446)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~7) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (493:493:493)) - (PORT datab (278:278:278) (303:303:303)) - (PORT datac (245:245:245) (277:277:277)) - (PORT datad (238:238:238) (256:256:256)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (473:473:473) (489:489:489)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|tx) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) -) diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_fast.vo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_fast.vo deleted file mode 100644 index c7cf150..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_fast.vo +++ /dev/null @@ -1,2836 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - -// VENDOR "Altera" -// PROGRAM "Quartus II 64-Bit" -// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" - -// DATE "06/02/2023 03:03:50" - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This Verilog file should be used for ModelSim (Verilog) only -// - -`timescale 1 ps/ 1 ps - -module rs232 ( - sys_clk, - sys_rst_n, - rx, - tx); -input sys_clk; -input sys_rst_n; -input rx; -output tx; - -// Design Ports Information -// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default -// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default -// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default -// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default - - -wire gnd; -wire vcc; -wire unknown; - -assign gnd = 1'b0; -assign vcc = 1'b1; -assign unknown = 1'bx; - -tri1 devclrn; -tri1 devpor; -tri1 devoe; -// synopsys translate_off -initial $sdf_annotate("rs232_min_1200mv_0c_v_fast.sdo"); -// synopsys translate_on - -wire \uart_tx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[0]~13_combout ; -wire \uart_rx_inst|baud_cnt[0]~14 ; -wire \uart_rx_inst|baud_cnt[1]~15_combout ; -wire \uart_rx_inst|baud_cnt[1]~16 ; -wire \uart_rx_inst|baud_cnt[2]~17_combout ; -wire \uart_rx_inst|baud_cnt[2]~18 ; -wire \uart_rx_inst|baud_cnt[3]~19_combout ; -wire \uart_rx_inst|baud_cnt[3]~20 ; -wire \uart_rx_inst|baud_cnt[4]~21_combout ; -wire \uart_rx_inst|baud_cnt[4]~22 ; -wire \uart_rx_inst|baud_cnt[5]~23_combout ; -wire \uart_rx_inst|baud_cnt[5]~24 ; -wire \uart_rx_inst|baud_cnt[6]~25_combout ; -wire \uart_rx_inst|baud_cnt[6]~26 ; -wire \uart_rx_inst|baud_cnt[7]~27_combout ; -wire \uart_rx_inst|baud_cnt[7]~28 ; -wire \uart_rx_inst|baud_cnt[8]~29_combout ; -wire \uart_rx_inst|baud_cnt[8]~30 ; -wire \uart_rx_inst|baud_cnt[9]~31_combout ; -wire \uart_rx_inst|baud_cnt[9]~32 ; -wire \uart_rx_inst|baud_cnt[10]~33_combout ; -wire \uart_rx_inst|baud_cnt[10]~34 ; -wire \uart_rx_inst|baud_cnt[11]~35_combout ; -wire \uart_rx_inst|baud_cnt[11]~36 ; -wire \uart_rx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal2~0_combout ; -wire \uart_tx_inst|Add1~0_combout ; -wire \uart_tx_inst|Add1~1_combout ; -wire \uart_rx_inst|bit_flag~q ; -wire \uart_rx_inst|Equal1~0_combout ; -wire \uart_rx_inst|Equal2~0_combout ; -wire \uart_rx_inst|Equal2~1_combout ; -wire \uart_rx_inst|Equal2~2_combout ; -wire \uart_rx_inst|work_en~q ; -wire \uart_rx_inst|Equal1~1_combout ; -wire \uart_rx_inst|Equal1~2_combout ; -wire \uart_rx_inst|Equal1~3_combout ; -wire \uart_rx_inst|always5~0_combout ; -wire \uart_rx_inst|start_nedge~q ; -wire \uart_rx_inst|work_en~0_combout ; -wire \uart_rx_inst|always3~0_combout ; -wire \tx~output_o ; -wire \sys_clk~input_o ; -wire \sys_clk~inputclkctrl_outclk ; -wire \uart_rx_inst|Add1~0_combout ; -wire \uart_rx_inst|bit_cnt~1_combout ; -wire \sys_rst_n~input_o ; -wire \uart_rx_inst|Add1~1 ; -wire \uart_rx_inst|Add1~2_combout ; -wire \uart_rx_inst|Add1~3 ; -wire \uart_rx_inst|Add1~4_combout ; -wire \uart_rx_inst|always4~0_combout ; -wire \uart_rx_inst|Add1~5 ; -wire \uart_rx_inst|Add1~6_combout ; -wire \uart_rx_inst|bit_cnt~0_combout ; -wire \uart_rx_inst|always4~1_combout ; -wire \uart_rx_inst|rx_flag~feeder_combout ; -wire \uart_rx_inst|rx_flag~q ; -wire \uart_rx_inst|po_flag~feeder_combout ; -wire \uart_rx_inst|po_flag~q ; -wire \uart_tx_inst|work_en~0_combout ; -wire \uart_tx_inst|work_en~q ; -wire \uart_tx_inst|baud_cnt[0]~13_combout ; -wire \uart_tx_inst|baud_cnt[10]~34 ; -wire \uart_tx_inst|baud_cnt[11]~35_combout ; -wire \uart_tx_inst|Equal1~0_combout ; -wire \uart_tx_inst|Equal1~1_combout ; -wire \uart_tx_inst|baud_cnt[11]~36 ; -wire \uart_tx_inst|baud_cnt[12]~37_combout ; -wire \uart_tx_inst|Equal1~3_combout ; -wire \uart_tx_inst|baud_cnt[2]~17_combout ; -wire \uart_tx_inst|baud_cnt[4]~21_combout ; -wire \uart_tx_inst|Equal1~2_combout ; -wire \uart_tx_inst|always1~0_combout ; -wire \uart_tx_inst|baud_cnt[0]~14 ; -wire \uart_tx_inst|baud_cnt[1]~15_combout ; -wire \uart_tx_inst|baud_cnt[1]~16 ; -wire \uart_tx_inst|baud_cnt[2]~18 ; -wire \uart_tx_inst|baud_cnt[3]~19_combout ; -wire \uart_tx_inst|baud_cnt[3]~20 ; -wire \uart_tx_inst|baud_cnt[4]~22 ; -wire \uart_tx_inst|baud_cnt[5]~24 ; -wire \uart_tx_inst|baud_cnt[6]~25_combout ; -wire \uart_tx_inst|baud_cnt[6]~26 ; -wire \uart_tx_inst|baud_cnt[7]~27_combout ; -wire \uart_tx_inst|baud_cnt[7]~28 ; -wire \uart_tx_inst|baud_cnt[8]~29_combout ; -wire \uart_tx_inst|baud_cnt[8]~30 ; -wire \uart_tx_inst|baud_cnt[9]~31_combout ; -wire \uart_tx_inst|baud_cnt[9]~32 ; -wire \uart_tx_inst|baud_cnt[10]~33_combout ; -wire \uart_tx_inst|Equal2~1_combout ; -wire \uart_tx_inst|bit_flag~q ; -wire \uart_tx_inst|always3~0_combout ; -wire \uart_tx_inst|bit_cnt[2]~2_combout ; -wire \uart_tx_inst|bit_cnt[3]~4_combout ; -wire \uart_tx_inst|always0~0_combout ; -wire \uart_tx_inst|always0~1_combout ; -wire \uart_tx_inst|bit_cnt[0]~5_combout ; -wire \rx~input_o ; -wire \uart_rx_inst|rx_reg1~0_combout ; -wire \uart_rx_inst|rx_reg1~q ; -wire \uart_rx_inst|rx_reg2~feeder_combout ; -wire \uart_rx_inst|rx_reg2~q ; -wire \uart_rx_inst|rx_reg3~feeder_combout ; -wire \uart_rx_inst|rx_reg3~q ; -wire \uart_rx_inst|rx_data[7]~0_combout ; -wire \uart_rx_inst|always8~0_combout ; -wire \uart_tx_inst|bit_cnt[1]~3_combout ; -wire \uart_tx_inst|tx~2_combout ; -wire \uart_tx_inst|tx~5_combout ; -wire \uart_rx_inst|rx_data[6]~feeder_combout ; -wire \uart_rx_inst|po_data[5]~feeder_combout ; -wire \uart_rx_inst|po_data[4]~feeder_combout ; -wire \uart_tx_inst|Mux0~0_combout ; -wire \uart_tx_inst|Mux0~1_combout ; -wire \uart_rx_inst|rx_data[2]~feeder_combout ; -wire \uart_rx_inst|rx_data[1]~feeder_combout ; -wire \uart_rx_inst|rx_data[0]~feeder_combout ; -wire \uart_tx_inst|tx~3_combout ; -wire \uart_tx_inst|tx~4_combout ; -wire \uart_tx_inst|tx~6_combout ; -wire \uart_tx_inst|tx~7_combout ; -wire \uart_tx_inst|tx~q ; -wire [7:0] \uart_rx_inst|rx_data ; -wire [7:0] \uart_rx_inst|po_data ; -wire [3:0] \uart_rx_inst|bit_cnt ; -wire [12:0] \uart_rx_inst|baud_cnt ; -wire [3:0] \uart_tx_inst|bit_cnt ; -wire [12:0] \uart_tx_inst|baud_cnt ; - - -// Location: FF_X6_Y9_N13 -dffeas \uart_tx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[4]~22 ), - .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_tx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; -defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X10_Y9_N5 -dffeas \uart_rx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N7 -dffeas \uart_rx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N19 -dffeas \uart_rx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N21 -dffeas \uart_rx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N11 -dffeas \uart_rx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N15 -dffeas \uart_rx_inst|baud_cnt[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[5]~23_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N9 -dffeas \uart_rx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N13 -dffeas \uart_rx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N23 -dffeas \uart_rx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N27 -dffeas \uart_rx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N17 -dffeas \uart_rx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N25 -dffeas \uart_rx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X10_Y9_N29 -dffeas \uart_rx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_rx_inst|always5~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) -// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_rx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[0]~14 ), - .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_rx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) -// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[1]~16 ), - .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_rx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) - - .dataa(\uart_rx_inst|baud_cnt [3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[2]~18 ), - .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_rx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) -// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[3]~20 ), - .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_rx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) -// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[4]~22 ), - .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), - .cout(\uart_rx_inst|baud_cnt[5]~24 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) -// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[5]~24 ), - .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_rx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[6]~26 ), - .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_rx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) -// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[7]~28 ), - .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_rx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[8]~30 ), - .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_rx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) -// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) - - .dataa(gnd), - .datab(\uart_rx_inst|baud_cnt [10]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[9]~32 ), - .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_rx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) - - .dataa(\uart_rx_inst|baud_cnt [11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|baud_cnt[10]~34 ), - .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_rx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; -defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|baud_cnt [12]), - .cin(\uart_rx_inst|baud_cnt[11]~36 ), - .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; -defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X4_Y9_N23 -dffeas \uart_rx_inst|po_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [2]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( -// Equation(s): -// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [6]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; -defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( -// Equation(s): -// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(gnd), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; -defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( -// Equation(s): -// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|bit_cnt [1]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|Add1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; -defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N11 -dffeas \uart_rx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Equal2~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( -// Equation(s): -// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) - - .dataa(\uart_rx_inst|baud_cnt [1]), - .datab(\uart_rx_inst|baud_cnt [7]), - .datac(\uart_rx_inst|baud_cnt [0]), - .datad(\uart_rx_inst|baud_cnt [8]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( -// Equation(s): -// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) - - .dataa(\uart_rx_inst|baud_cnt [5]), - .datab(\uart_rx_inst|baud_cnt [3]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( -// Equation(s): -// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) - - .dataa(\uart_rx_inst|baud_cnt [9]), - .datab(\uart_rx_inst|baud_cnt [11]), - .datac(\uart_rx_inst|baud_cnt [6]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; -defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N10 -cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( -// Equation(s): -// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) - - .dataa(\uart_rx_inst|Equal2~1_combout ), - .datab(\uart_rx_inst|baud_cnt [12]), - .datac(\uart_rx_inst|Equal1~0_combout ), - .datad(\uart_rx_inst|Equal2~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal2~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; -defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X9_Y9_N17 -dffeas \uart_rx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_rx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( -// Equation(s): -// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) - - .dataa(\uart_rx_inst|baud_cnt [4]), - .datab(\uart_rx_inst|baud_cnt [5]), - .datac(\uart_rx_inst|baud_cnt [2]), - .datad(\uart_rx_inst|baud_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; -defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( -// Equation(s): -// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|baud_cnt [11]), - .datad(\uart_rx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; -defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( -// Equation(s): -// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) - - .dataa(\uart_rx_inst|baud_cnt [12]), - .datab(\uart_rx_inst|baud_cnt [6]), - .datac(\uart_rx_inst|baud_cnt [9]), - .datad(\uart_rx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_rx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; -defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X10_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|always5~0 ( -// Equation(s): -// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) - - .dataa(\uart_rx_inst|work_en~q ), - .datab(\uart_rx_inst|Equal1~0_combout ), - .datac(\uart_rx_inst|Equal1~1_combout ), - .datad(\uart_rx_inst|Equal1~3_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always5~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; -defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N13 -dffeas \uart_rx_inst|start_nedge ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|always3~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|start_nedge~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; -defparam \uart_rx_inst|start_nedge .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X9_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( -// Equation(s): -// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|start_nedge~q ), - .datac(\uart_rx_inst|work_en~q ), - .datad(\uart_rx_inst|always4~1_combout ), - .cin(gnd), - .combout(\uart_rx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|always3~0 ( -// Equation(s): -// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) - - .dataa(gnd), - .datab(\uart_rx_inst|rx_reg2~q ), - .datac(\uart_rx_inst|rx_reg3~q ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; -defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOOBUF_X0_Y9_N16 -cycloneive_io_obuf \tx~output ( - .i(!\uart_tx_inst|tx~q ), - .oe(vcc), - .seriesterminationcontrol(16'b0000000000000000), - .devoe(devoe), - .o(\tx~output_o ), - .obar()); -// synopsys translate_off -defparam \tx~output .bus_hold = "false"; -defparam \tx~output .open_drain_output = "false"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y15_N22 -cycloneive_io_ibuf \sys_clk~input ( - .i(sys_clk), - .ibar(gnd), - .o(\sys_clk~input_o )); -// synopsys translate_off -defparam \sys_clk~input .bus_hold = "false"; -defparam \sys_clk~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: CLKCTRL_G8 -cycloneive_clkctrl \sys_clk~inputclkctrl ( - .ena(vcc), - .inclk({vcc,vcc,vcc,\sys_clk~input_o }), - .clkselect(2'b00), - .devclrn(devclrn), - .devpor(devpor), - .outclk(\sys_clk~inputclkctrl_outclk )); -// synopsys translate_off -defparam \sys_clk~inputclkctrl .clock_type = "global clock"; -defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N16 -cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( -// Equation(s): -// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) -// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_rx_inst|Add1~0_combout ), - .cout(\uart_rx_inst|Add1~1 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; -defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N4 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(\uart_rx_inst|Add1~0_combout ), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; -defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: IOIBUF_X41_Y4_N1 -cycloneive_io_ibuf \sys_rst_n~input ( - .i(sys_rst_n), - .ibar(gnd), - .o(\sys_rst_n~input_o )); -// synopsys translate_off -defparam \sys_rst_n~input .bus_hold = "false"; -defparam \sys_rst_n~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: FF_X8_Y9_N5 -dffeas \uart_rx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( -// Equation(s): -// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) -// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~1 ), - .combout(\uart_rx_inst|Add1~2_combout ), - .cout(\uart_rx_inst|Add1~3 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; -defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N19 -dffeas \uart_rx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( -// Equation(s): -// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) -// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [2]), - .datac(gnd), - .datad(vcc), - .cin(\uart_rx_inst|Add1~3 ), - .combout(\uart_rx_inst|Add1~4_combout ), - .cout(\uart_rx_inst|Add1~5 )); -// synopsys translate_off -defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; -defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X8_Y9_N21 -dffeas \uart_rx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|Add1~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N24 -cycloneive_lcell_comb \uart_rx_inst|always4~0 ( -// Equation(s): -// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) - - .dataa(gnd), - .datab(\uart_rx_inst|bit_cnt [1]), - .datac(\uart_rx_inst|bit_cnt [0]), - .datad(\uart_rx_inst|bit_cnt [2]), - .cin(gnd), - .combout(\uart_rx_inst|always4~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; -defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N22 -cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( -// Equation(s): -// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(\uart_rx_inst|Add1~5 ), - .combout(\uart_rx_inst|Add1~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; -defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( -// Equation(s): -// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(\uart_rx_inst|bit_cnt [3]), - .datad(\uart_rx_inst|Add1~6_combout ), - .cin(gnd), - .combout(\uart_rx_inst|bit_cnt~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; -defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N1 -dffeas \uart_rx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|bit_cnt~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|always4~1 ( -// Equation(s): -// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_rx_inst|always4~0_combout ), - .cin(gnd), - .combout(\uart_rx_inst|always4~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; -defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N14 -cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( -// Equation(s): -// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|always4~1_combout ), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N15 -dffeas \uart_rx_inst|rx_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N30 -cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( -// Equation(s): -// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_flag~q ), - .cin(gnd), - .combout(\uart_rx_inst|po_flag~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N31 -dffeas \uart_rx_inst|po_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_flag~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( -// Equation(s): -// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) - - .dataa(gnd), - .datab(\uart_rx_inst|po_flag~q ), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|work_en~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; -defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N15 -dffeas \uart_tx_inst|work_en ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|work_en~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|work_en~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; -defparam \uart_tx_inst|work_en .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) -// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), - .cout(\uart_tx_inst|baud_cnt[0]~14 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; -defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N22 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) -// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) - - .dataa(\uart_tx_inst|baud_cnt [10]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[9]~32 ), - .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), - .cout(\uart_tx_inst|baud_cnt[10]~34 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) -// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [11]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[10]~34 ), - .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), - .cout(\uart_tx_inst|baud_cnt[11]~36 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N25 -dffeas \uart_tx_inst|baud_cnt[11] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[11]~35_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [11]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( -// Equation(s): -// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) - - .dataa(\uart_tx_inst|baud_cnt [5]), - .datab(\uart_tx_inst|baud_cnt [0]), - .datac(\uart_tx_inst|baud_cnt [3]), - .datad(\uart_tx_inst|baud_cnt [7]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; -defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N0 -cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( -// Equation(s): -// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) - - .dataa(\uart_tx_inst|baud_cnt [9]), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(\uart_tx_inst|baud_cnt [11]), - .datad(\uart_tx_inst|Equal1~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; -defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) - - .dataa(\uart_tx_inst|baud_cnt [12]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\uart_tx_inst|baud_cnt[11]~36 ), - .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; -defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N27 -dffeas \uart_tx_inst|baud_cnt[12] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[12]~37_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [12]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( -// Equation(s): -// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [12]), - .datac(gnd), - .datad(\uart_tx_inst|baud_cnt [10]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) -// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) - - .dataa(\uart_tx_inst|baud_cnt [2]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[1]~16 ), - .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), - .cout(\uart_tx_inst|baud_cnt[2]~18 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N7 -dffeas \uart_tx_inst|baud_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[2]~17_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) -// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) - - .dataa(\uart_tx_inst|baud_cnt [4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[3]~20 ), - .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), - .cout(\uart_tx_inst|baud_cnt[4]~22 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; -defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N11 -dffeas \uart_tx_inst|baud_cnt[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[4]~21_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X7_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( -// Equation(s): -// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) - - .dataa(\uart_tx_inst|baud_cnt [6]), - .datab(\uart_tx_inst|baud_cnt [2]), - .datac(\uart_tx_inst|baud_cnt [1]), - .datad(\uart_tx_inst|baud_cnt [4]), - .cin(gnd), - .combout(\uart_tx_inst|Equal1~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; -defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N30 -cycloneive_lcell_comb \uart_tx_inst|always1~0 ( -// Equation(s): -// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) - - .dataa(\uart_tx_inst|work_en~q ), - .datab(\uart_tx_inst|Equal1~1_combout ), - .datac(\uart_tx_inst|Equal1~3_combout ), - .datad(\uart_tx_inst|Equal1~2_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; -defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X6_Y9_N3 -dffeas \uart_tx_inst|baud_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[0]~13_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) -// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [1]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[0]~14 ), - .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), - .cout(\uart_tx_inst|baud_cnt[1]~16 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N5 -dffeas \uart_tx_inst|baud_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[1]~15_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) -// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [3]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[2]~18 ), - .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), - .cout(\uart_tx_inst|baud_cnt[3]~20 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N9 -dffeas \uart_tx_inst|baud_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[3]~19_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) -// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [6]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[5]~24 ), - .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), - .cout(\uart_tx_inst|baud_cnt[6]~26 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N15 -dffeas \uart_tx_inst|baud_cnt[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[6]~25_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) -// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [7]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[6]~26 ), - .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), - .cout(\uart_tx_inst|baud_cnt[7]~28 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N17 -dffeas \uart_tx_inst|baud_cnt[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[7]~27_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) -// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [8]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[7]~28 ), - .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), - .cout(\uart_tx_inst|baud_cnt[8]~30 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; -defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N19 -dffeas \uart_tx_inst|baud_cnt[8] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[8]~29_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [8]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X6_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( -// Equation(s): -// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) -// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) - - .dataa(gnd), - .datab(\uart_tx_inst|baud_cnt [9]), - .datac(gnd), - .datad(vcc), - .cin(\uart_tx_inst|baud_cnt[8]~30 ), - .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), - .cout(\uart_tx_inst|baud_cnt[9]~32 )); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; -defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X6_Y9_N21 -dffeas \uart_tx_inst|baud_cnt[9] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[9]~31_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [9]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X6_Y9_N23 -dffeas \uart_tx_inst|baud_cnt[10] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|baud_cnt[10]~33_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(\uart_tx_inst|always1~0_combout ), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|baud_cnt [10]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; -defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N20 -cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( -// Equation(s): -// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) - - .dataa(\uart_tx_inst|Equal2~0_combout ), - .datab(\uart_tx_inst|baud_cnt [10]), - .datac(\uart_tx_inst|Equal1~1_combout ), - .datad(\uart_tx_inst|baud_cnt [12]), - .cin(gnd), - .combout(\uart_tx_inst|Equal2~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; -defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N21 -dffeas \uart_tx_inst|bit_flag ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|Equal2~1_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_flag~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_flag .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|always3~0 ( -// Equation(s): -// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) - - .dataa(gnd), - .datab(gnd), - .datac(\uart_tx_inst|work_en~q ), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always3~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; -defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N26 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) - - .dataa(\uart_tx_inst|Add1~0_combout ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; -defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N27 -dffeas \uart_tx_inst|bit_cnt[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[2]~2_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) - - .dataa(\uart_tx_inst|Add1~1_combout ), - .datab(\uart_tx_inst|always3~0_combout ), - .datac(\uart_tx_inst|bit_cnt [3]), - .datad(\uart_tx_inst|always0~1_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; -defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[3]~4_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|always0~0 ( -// Equation(s): -// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) - - .dataa(gnd), - .datab(\uart_tx_inst|bit_cnt [3]), - .datac(gnd), - .datad(\uart_tx_inst|bit_flag~q ), - .cin(gnd), - .combout(\uart_tx_inst|always0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; -defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N8 -cycloneive_lcell_comb \uart_tx_inst|always0~1 ( -// Equation(s): -// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_tx_inst|bit_cnt [2]), - .datad(\uart_tx_inst|always0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|always0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; -defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N2 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [0]), - .datad(\uart_tx_inst|work_en~q ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; -defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N3 -dffeas \uart_tx_inst|bit_cnt[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[0]~5_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; -// synopsys translate_on - -// Location: IOIBUF_X0_Y8_N1 -cycloneive_io_ibuf \rx~input ( - .i(rx), - .ibar(gnd), - .o(\rx~input_o )); -// synopsys translate_off -defparam \rx~input .bus_hold = "false"; -defparam \rx~input .simulate_z_as = "z"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N18 -cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( -// Equation(s): -// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\rx~input_o ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg1~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N19 -dffeas \uart_rx_inst|rx_reg1 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg1~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg1~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg1 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg1~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg2~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N1 -dffeas \uart_rx_inst|rx_reg2 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg2~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg2~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg2 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X5_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( -// Equation(s): -// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg2~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_reg3~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X5_Y9_N27 -dffeas \uart_rx_inst|rx_reg3 ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_reg3~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_reg3~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_reg3 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N28 -cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( -// Equation(s): -// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_reg3~q ), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[7]~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; -defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N6 -cycloneive_lcell_comb \uart_rx_inst|always8~0 ( -// Equation(s): -// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) - - .dataa(\uart_rx_inst|bit_flag~q ), - .datab(\uart_rx_inst|always4~0_combout ), - .datac(gnd), - .datad(\uart_rx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_rx_inst|always8~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; -defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N29 -dffeas \uart_rx_inst|rx_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[7]~0_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N5 -dffeas \uart_rx_inst|po_data[7] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [7]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [7]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N6 -cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( -// Equation(s): -// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) - - .dataa(\uart_tx_inst|bit_cnt [0]), - .datab(\uart_tx_inst|always0~1_combout ), - .datac(\uart_tx_inst|bit_cnt [1]), - .datad(\uart_tx_inst|always3~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; -defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N7 -dffeas \uart_tx_inst|bit_cnt[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|bit_cnt[1]~3_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|bit_cnt [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; -defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N4 -cycloneive_lcell_comb \uart_tx_inst|tx~2 ( -// Equation(s): -// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [7]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~2_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; -defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N16 -cycloneive_lcell_comb \uart_tx_inst|tx~5 ( -// Equation(s): -// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) - - .dataa(\uart_tx_inst|tx~q ), - .datab(\uart_tx_inst|tx~2_combout ), - .datac(\uart_tx_inst|bit_flag~q ), - .datad(\uart_tx_inst|bit_cnt [3]), - .cin(gnd), - .combout(\uart_tx_inst|tx~5_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; -defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N2 -cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [7]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N3 -dffeas \uart_rx_inst|rx_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[6]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N7 -dffeas \uart_rx_inst|rx_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N20 -cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [5]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[5]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N21 -dffeas \uart_rx_inst|po_data[5] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[5]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [5]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[5] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N15 -dffeas \uart_rx_inst|po_data[6] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [6]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [6]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[6] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N31 -dffeas \uart_rx_inst|rx_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [5]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N0 -cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( -// Equation(s): -// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [4]), - .cin(gnd), - .combout(\uart_rx_inst|po_data[4]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N1 -dffeas \uart_rx_inst|po_data[4] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|po_data[4]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [4]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[4] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X8_Y9_N23 -dffeas \uart_rx_inst|rx_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [4]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N25 -dffeas \uart_rx_inst|po_data[3] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [3]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [3]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N24 -cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( -// Equation(s): -// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [4]), - .datac(\uart_rx_inst|po_data [3]), - .datad(\uart_tx_inst|bit_cnt [0]), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~0_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; -defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N14 -cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( -// Equation(s): -// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & -// (((\uart_tx_inst|Mux0~0_combout )))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_rx_inst|po_data [5]), - .datac(\uart_rx_inst|po_data [6]), - .datad(\uart_tx_inst|Mux0~0_combout ), - .cin(gnd), - .combout(\uart_tx_inst|Mux0~1_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; -defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N8 -cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [3]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N9 -dffeas \uart_rx_inst|rx_data[2] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[2]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [2]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N26 -cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(\uart_rx_inst|rx_data [2]), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; -defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N27 -dffeas \uart_rx_inst|rx_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[1]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N19 -dffeas \uart_rx_inst|po_data[1] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [1]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [1]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X8_Y9_N12 -cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( -// Equation(s): -// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] - - .dataa(gnd), - .datab(gnd), - .datac(\uart_rx_inst|rx_data [1]), - .datad(gnd), - .cin(gnd), - .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), - .cout()); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; -defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X8_Y9_N13 -dffeas \uart_rx_inst|rx_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_rx_inst|rx_data[0]~feeder_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(\uart_rx_inst|always8~0_combout ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|rx_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|rx_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: FF_X4_Y9_N29 -dffeas \uart_rx_inst|po_data[0] ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(gnd), - .asdata(\uart_rx_inst|rx_data [0]), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(vcc), - .ena(\uart_rx_inst|rx_flag~q ), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_rx_inst|po_data [0]), - .prn(vcc)); -// synopsys translate_off -defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; -defparam \uart_rx_inst|po_data[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N28 -cycloneive_lcell_comb \uart_tx_inst|tx~3 ( -// Equation(s): -// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) - - .dataa(\uart_rx_inst|po_data [2]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [0]), - .datad(\uart_tx_inst|bit_cnt [1]), - .cin(gnd), - .combout(\uart_tx_inst|tx~3_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; -defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N18 -cycloneive_lcell_comb \uart_tx_inst|tx~4 ( -// Equation(s): -// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) - - .dataa(\uart_tx_inst|bit_cnt [1]), - .datab(\uart_tx_inst|bit_cnt [0]), - .datac(\uart_rx_inst|po_data [1]), - .datad(\uart_tx_inst|tx~3_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~4_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; -defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N10 -cycloneive_lcell_comb \uart_tx_inst|tx~6 ( -// Equation(s): -// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) - - .dataa(\uart_tx_inst|bit_flag~q ), - .datab(\uart_tx_inst|bit_cnt [2]), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~4_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~6_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; -defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X4_Y9_N12 -cycloneive_lcell_comb \uart_tx_inst|tx~7 ( -// Equation(s): -// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # -// (!\uart_tx_inst|tx~6_combout ))) - - .dataa(\uart_tx_inst|bit_cnt [2]), - .datab(\uart_tx_inst|tx~5_combout ), - .datac(\uart_tx_inst|Mux0~1_combout ), - .datad(\uart_tx_inst|tx~6_combout ), - .cin(gnd), - .combout(\uart_tx_inst|tx~7_combout ), - .cout()); -// synopsys translate_off -defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; -defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X4_Y9_N13 -dffeas \uart_tx_inst|tx ( - .clk(\sys_clk~inputclkctrl_outclk ), - .d(\uart_tx_inst|tx~7_combout ), - .asdata(vcc), - .clrn(\sys_rst_n~input_o ), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\uart_tx_inst|tx~q ), - .prn(vcc)); -// synopsys translate_off -defparam \uart_tx_inst|tx .is_wysiwyg = "true"; -defparam \uart_tx_inst|tx .power_up = "low"; -// synopsys translate_on - -assign tx = \tx~output_o ; - -endmodule diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_v_fast.sdo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_v_fast.sdo deleted file mode 100644 index ac7de7e..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_v_fast.sdo +++ /dev/null @@ -1,2275 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This file contains Fast Corner delays for the design using part EP4CE15F23C8, -// with speed grade M, core voltage 1.2V, and temperature 0 Celsius -// - -// -// This SDF file should be used for ModelSim (Verilog) only -// - -(DELAYFILE - (SDFVERSION "2.1") - (DESIGN "rs232") - (DATE "06/02/2023 03:03:50") - (VENDOR "Altera") - (PROGRAM "Quartus II 64-Bit") - (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") - (DIVIDER .) - (TIMESCALE 1 ps) - - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (188:188:188)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (869:869:869) (875:875:875)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2997:2997:2997) (2689:2689:2689)) - (PORT sclr (319:319:319) (370:370:370)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (208:208:208) (267:267:267)) - (PORT datab (135:135:135) (185:185:185)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (189:189:189)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (146:146:146) (196:196:196)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (147:147:147) (198:198:198)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (148:148:148) (200:200:200)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (146:146:146) (197:197:197)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (183:183:183)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (205:205:205) (263:263:263)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (155:155:155) (205:205:205)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT datad (203:203:203) (248:248:248)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT asdata (489:489:489) (548:548:548)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (233:233:233) (289:289:289)) - (PORT datab (216:216:216) (270:270:270)) - (PORT datac (200:200:200) (249:249:249)) - (PORT datad (205:205:205) (249:249:249)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (158:158:158) (215:215:215)) - (PORT datab (183:183:183) (241:241:241)) - (PORT datad (161:161:161) (212:212:212)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (240:240:240) (294:294:294)) - (PORT datab (213:213:213) (265:265:265)) - (PORT datac (212:212:212) (264:264:264)) - (PORT datad (136:136:136) (176:176:176)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (182:182:182) (181:181:181)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (136:136:136) (190:190:190)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (121:121:121) (164:164:164)) - (PORT datad (124:124:124) (164:164:164)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (318:318:318) (381:381:381)) - (PORT datab (214:214:214) (271:271:271)) - (PORT datac (213:213:213) (265:265:265)) - (PORT datad (311:311:311) (369:369:369)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (324:324:324) (394:394:394)) - (PORT datab (338:338:338) (400:400:400)) - (PORT datac (321:321:321) (385:385:385)) - (PORT datad (217:217:217) (269:269:269)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (177:177:177) (220:220:220)) - (PORT datab (329:329:329) (399:399:399)) - (PORT datac (285:285:285) (322:322:322)) - (PORT datad (173:173:173) (205:205:205)) - (IOPATH dataa combout (166:166:166) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2994:2994:2994) (2686:2686:2686)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (150:150:150) (204:204:204)) - (PORT datab (149:149:149) (199:199:199)) - (PORT datac (135:135:135) (179:179:179)) - (PORT datad (136:136:136) (176:176:176)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT datac (313:313:313) (366:366:366)) - (PORT datad (218:218:218) (270:270:270)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (331:331:331) (393:393:393)) - (PORT datab (218:218:218) (277:277:277)) - (PORT datac (309:309:309) (370:370:370)) - (PORT datad (90:90:90) (108:108:108)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (209:209:209) (268:268:268)) - (PORT datab (115:115:115) (144:144:144)) - (PORT datac (93:93:93) (116:116:116)) - (PORT datad (157:157:157) (182:182:182)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|start_nedge) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2865:2865:2865) (2564:2564:2564)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (316:316:316) (377:377:377)) - (PORT datad (169:169:169) (194:194:194)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (186:186:186)) - (PORT datac (130:130:130) (172:172:172)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_obuf") - (INSTANCE tx\~output) - (DELAY - (ABSOLUTE - (PORT i (344:344:344) (297:297:297)) - (IOPATH i o (1755:1755:1755) (1782:1782:1782)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_clk\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (358:358:358) (738:738:738)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE sys_clk\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (97:97:97) (82:82:82)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (213:213:213)) - (PORT datab (136:136:136) (187:187:187)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (212:212:212)) - (PORT datab (142:142:142) (196:196:196)) - (PORT datac (162:162:162) (189:189:189)) - (PORT datad (107:107:107) (132:132:132)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_rst_n\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (318:318:318) (698:698:698)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~4) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (184:184:184)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~0) - (DELAY - (ABSOLUTE - (PORT datab (136:136:136) (185:185:185)) - (PORT datac (123:123:123) (167:167:167)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datad (134:134:134) (178:178:178)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (213:213:213)) - (PORT datab (122:122:122) (157:157:157)) - (PORT datad (163:163:163) (189:189:189)) - (IOPATH dataa combout (181:181:181) (180:180:180)) - (IOPATH datab combout (182:182:182) (181:181:181)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (156:156:156) (215:215:215)) - (PORT datab (149:149:149) (204:204:204)) - (PORT datad (101:101:101) (125:125:125)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (104:104:104) (126:126:126)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_flag) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (319:319:319) (384:384:384)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_flag) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (197:197:197) (253:253:253)) - (PORT datad (177:177:177) (202:202:202)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2865:2865:2865) (2564:2564:2564)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (224:224:224) (283:283:283)) - (PORT datab (133:133:133) (183:183:183)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (138:138:138) (191:191:191)) - (PORT datab (138:138:138) (189:189:189)) - (PORT datac (123:123:123) (167:167:167)) - (PORT datad (122:122:122) (161:161:161)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (216:216:216) (272:272:272)) - (PORT datab (137:137:137) (188:188:188)) - (PORT datac (204:204:204) (251:251:251)) - (PORT datad (94:94:94) (112:112:112)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT datab (234:234:234) (292:292:292)) - (PORT datad (216:216:216) (267:267:267)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (218:218:218) (275:275:275)) - (PORT datab (216:216:216) (270:270:270)) - (PORT datac (201:201:201) (249:249:249)) - (PORT datad (210:210:210) (260:260:260)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (226:226:226) (285:285:285)) - (PORT datab (120:120:120) (149:149:149)) - (PORT datac (161:161:161) (190:190:190)) - (PORT datad (166:166:166) (195:195:195)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (161:161:161) (167:167:167)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT datab (141:141:141) (190:190:190)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (184:184:184)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (134:134:134) (184:184:184)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (135:135:135) (185:185:185)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (877:877:877)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2871:2871:2871) (2569:2569:2569)) - (PORT sclr (321:321:321) (376:376:376)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD sclr (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (293:293:293) (341:341:341)) - (PORT datab (234:234:234) (292:292:292)) - (PORT datac (190:190:190) (225:225:225)) - (PORT datad (215:215:215) (266:266:266)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (119:119:119) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2865:2865:2865) (2564:2564:2564)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datac (129:129:129) (171:171:171)) - (PORT datad (133:133:133) (171:171:171)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (273:273:273) (320:320:320)) - (PORT datab (128:128:128) (161:161:161)) - (PORT datad (188:188:188) (219:219:219)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (119:119:119) (148:148:148)) - (PORT datad (176:176:176) (201:201:201)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (188:188:188) (177:177:177)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2865:2865:2865) (2564:2564:2564)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~0) - (DELAY - (ABSOLUTE - (PORT datab (145:145:145) (195:195:195)) - (PORT datad (135:135:135) (174:174:174)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (171:171:171) (233:233:233)) - (PORT datab (178:178:178) (236:236:236)) - (PORT datac (146:146:146) (195:195:195)) - (PORT datad (172:172:172) (205:205:205)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (166:166:166) (158:158:158)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (229:229:229) (293:293:293)) - (PORT datab (125:125:125) (157:157:157)) - (PORT datad (314:314:314) (374:374:374)) - (IOPATH dataa combout (165:165:165) (159:159:159)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE rx\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (348:348:348) (728:728:728)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg1\~0) - (DELAY - (ABSOLUTE - (PORT datad (1703:1703:1703) (1891:1891:1891)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg1) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2865:2865:2865) (2564:2564:2564)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg2\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (119:119:119) (156:156:156)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg2) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2865:2865:2865) (2564:2564:2564)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (125:125:125) (165:165:165)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg3) - (DELAY - (ABSOLUTE - (PORT clk (871:871:871) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2865:2865:2865) (2564:2564:2564)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT datad (306:306:306) (360:360:360)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (153:153:153) (212:212:212)) - (PORT datab (120:120:120) (156:156:156)) - (PORT datad (129:129:129) (173:173:173)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (161:161:161) (176:176:176)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT asdata (482:482:482) (537:537:537)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (296:296:296)) - (PORT datab (126:126:126) (158:158:158)) - (PORT datad (191:191:191) (223:223:223)) - (IOPATH dataa combout (192:192:192) (184:184:184)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (162:162:162) (222:222:222)) - (PORT datab (176:176:176) (234:234:234)) - (PORT datad (155:155:155) (206:206:206)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~5) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (195:195:195)) - (PORT datab (105:105:105) (134:134:134)) - (PORT datac (211:211:211) (266:266:266)) - (PORT datad (203:203:203) (249:249:249)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (167:167:167) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (132:132:132) (170:170:170)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT asdata (469:469:469) (529:529:529)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (304:304:304) (366:366:366)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT asdata (480:480:480) (543:543:543)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT asdata (467:467:467) (521:521:521)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (308:308:308) (368:368:368)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT asdata (465:465:465) (518:518:518)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT asdata (597:597:597) (660:660:660)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (176:176:176) (239:239:239)) - (PORT datab (133:133:133) (182:182:182)) - (PORT datad (169:169:169) (218:218:218)) - (IOPATH dataa combout (166:166:166) (159:159:159)) - (IOPATH datab combout (167:167:167) (158:158:158)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (173:173:173) (236:236:236)) - (PORT datab (131:131:131) (179:179:179)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (130:130:130) (172:172:172)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (193:193:193) (240:240:240)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT asdata (491:491:491) (549:549:549)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (130:130:130) (172:172:172)) - (IOPATH datac combout (119:119:119) (124:124:124)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (870:870:870) (876:876:876)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2876:2876:2876) (2574:2574:2574)) - (PORT ena (406:406:406) (424:424:424)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT asdata (483:483:483) (546:546:546)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (PORT ena (652:652:652) (727:727:727)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (84:84:84)) - (HOLD ena (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~3) - (DELAY - (ABSOLUTE - (PORT dataa (131:131:131) (182:182:182)) - (PORT datab (184:184:184) (243:243:243)) - (PORT datad (162:162:162) (213:213:213)) - (IOPATH dataa combout (159:159:159) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~4) - (DELAY - (ABSOLUTE - (PORT dataa (175:175:175) (237:237:237)) - (PORT datab (182:182:182) (241:241:241)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~6) - (DELAY - (ABSOLUTE - (PORT dataa (228:228:228) (292:292:292)) - (PORT datab (217:217:217) (276:276:276)) - (PORT datac (94:94:94) (117:117:117)) - (PORT datad (91:91:91) (109:109:109)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (168:168:168) (167:167:167)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~7) - (DELAY - (ABSOLUTE - (PORT dataa (161:161:161) (221:221:221)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (94:94:94) (118:118:118)) - (PORT datad (91:91:91) (108:108:108)) - (IOPATH dataa combout (170:170:170) (163:163:163)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|tx) - (DELAY - (ABSOLUTE - (PORT clk (872:872:872) (878:878:878)) - (PORT d (37:37:37) (50:50:50)) - (PORT clrn (2734:2734:2734) (2452:2452:2452)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) -) diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_modelsim.xrf b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_modelsim.xrf deleted file mode 100644 index a2e17de..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_modelsim.xrf +++ /dev/null @@ -1,157 +0,0 @@ -vendor_name = ModelSim -source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/sim/tb_uart_tx.v -source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/sim/tb_uart_rx.v -source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/sim/tb_rs232.v -source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/rtl/uart_tx.v -source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/rtl/uart_rx.v -source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/rtl/rs232.v -source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/quartus_prj/db/rs232.cbx.xml -design_name = rs232 -instance = comp, \uart_tx_inst|baud_cnt[5] , uart_tx_inst|baud_cnt[5], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[5]~23 , uart_tx_inst|baud_cnt[5]~23, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[0] , uart_rx_inst|baud_cnt[0], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[1] , uart_rx_inst|baud_cnt[1], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[7] , uart_rx_inst|baud_cnt[7], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[8] , uart_rx_inst|baud_cnt[8], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[3] , uart_rx_inst|baud_cnt[3], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[5] , uart_rx_inst|baud_cnt[5], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[2] , uart_rx_inst|baud_cnt[2], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[4] , uart_rx_inst|baud_cnt[4], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[9] , uart_rx_inst|baud_cnt[9], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[11] , uart_rx_inst|baud_cnt[11], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[6] , uart_rx_inst|baud_cnt[6], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[10] , uart_rx_inst|baud_cnt[10], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[12] , uart_rx_inst|baud_cnt[12], rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[0]~13 , uart_rx_inst|baud_cnt[0]~13, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[1]~15 , uart_rx_inst|baud_cnt[1]~15, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[2]~17 , uart_rx_inst|baud_cnt[2]~17, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[3]~19 , uart_rx_inst|baud_cnt[3]~19, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[4]~21 , uart_rx_inst|baud_cnt[4]~21, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[5]~23 , uart_rx_inst|baud_cnt[5]~23, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[6]~25 , uart_rx_inst|baud_cnt[6]~25, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[7]~27 , uart_rx_inst|baud_cnt[7]~27, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[8]~29 , uart_rx_inst|baud_cnt[8]~29, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[9]~31 , uart_rx_inst|baud_cnt[9]~31, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[10]~33 , uart_rx_inst|baud_cnt[10]~33, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[11]~35 , uart_rx_inst|baud_cnt[11]~35, rs232, 1 -instance = comp, \uart_rx_inst|baud_cnt[12]~37 , uart_rx_inst|baud_cnt[12]~37, rs232, 1 -instance = comp, \uart_rx_inst|po_data[2] , uart_rx_inst|po_data[2], rs232, 1 -instance = comp, \uart_tx_inst|Equal2~0 , uart_tx_inst|Equal2~0, rs232, 1 -instance = comp, \uart_tx_inst|Add1~0 , uart_tx_inst|Add1~0, rs232, 1 -instance = comp, \uart_tx_inst|Add1~1 , uart_tx_inst|Add1~1, rs232, 1 -instance = comp, \uart_rx_inst|bit_flag , uart_rx_inst|bit_flag, rs232, 1 -instance = comp, \uart_rx_inst|Equal1~0 , uart_rx_inst|Equal1~0, rs232, 1 -instance = comp, \uart_rx_inst|Equal2~0 , uart_rx_inst|Equal2~0, rs232, 1 -instance = comp, \uart_rx_inst|Equal2~1 , uart_rx_inst|Equal2~1, rs232, 1 -instance = comp, \uart_rx_inst|Equal2~2 , uart_rx_inst|Equal2~2, rs232, 1 -instance = comp, \uart_rx_inst|work_en , uart_rx_inst|work_en, rs232, 1 -instance = comp, \uart_rx_inst|Equal1~1 , uart_rx_inst|Equal1~1, rs232, 1 -instance = comp, \uart_rx_inst|Equal1~2 , uart_rx_inst|Equal1~2, rs232, 1 -instance = comp, \uart_rx_inst|Equal1~3 , uart_rx_inst|Equal1~3, rs232, 1 -instance = comp, \uart_rx_inst|always5~0 , uart_rx_inst|always5~0, rs232, 1 -instance = comp, \uart_rx_inst|start_nedge , uart_rx_inst|start_nedge, rs232, 1 -instance = comp, \uart_rx_inst|work_en~0 , uart_rx_inst|work_en~0, rs232, 1 -instance = comp, \uart_rx_inst|always3~0 , uart_rx_inst|always3~0, rs232, 1 -instance = comp, \tx~output , tx~output, rs232, 1 -instance = comp, \sys_clk~input , sys_clk~input, rs232, 1 -instance = comp, \sys_clk~inputclkctrl , sys_clk~inputclkctrl, rs232, 1 -instance = comp, \uart_rx_inst|Add1~0 , uart_rx_inst|Add1~0, rs232, 1 -instance = comp, \uart_rx_inst|bit_cnt~1 , uart_rx_inst|bit_cnt~1, rs232, 1 -instance = comp, \sys_rst_n~input , sys_rst_n~input, rs232, 1 -instance = comp, \uart_rx_inst|bit_cnt[0] , uart_rx_inst|bit_cnt[0], rs232, 1 -instance = comp, \uart_rx_inst|Add1~2 , uart_rx_inst|Add1~2, rs232, 1 -instance = comp, \uart_rx_inst|bit_cnt[1] , uart_rx_inst|bit_cnt[1], rs232, 1 -instance = comp, \uart_rx_inst|Add1~4 , uart_rx_inst|Add1~4, rs232, 1 -instance = comp, \uart_rx_inst|bit_cnt[2] , uart_rx_inst|bit_cnt[2], rs232, 1 -instance = comp, \uart_rx_inst|always4~0 , uart_rx_inst|always4~0, rs232, 1 -instance = comp, \uart_rx_inst|Add1~6 , uart_rx_inst|Add1~6, rs232, 1 -instance = comp, \uart_rx_inst|bit_cnt~0 , uart_rx_inst|bit_cnt~0, rs232, 1 -instance = comp, \uart_rx_inst|bit_cnt[3] , uart_rx_inst|bit_cnt[3], rs232, 1 -instance = comp, \uart_rx_inst|always4~1 , uart_rx_inst|always4~1, rs232, 1 -instance = comp, \uart_rx_inst|rx_flag~feeder , uart_rx_inst|rx_flag~feeder, rs232, 1 -instance = comp, \uart_rx_inst|rx_flag , uart_rx_inst|rx_flag, rs232, 1 -instance = comp, \uart_rx_inst|po_flag~feeder , uart_rx_inst|po_flag~feeder, rs232, 1 -instance = comp, \uart_rx_inst|po_flag , uart_rx_inst|po_flag, rs232, 1 -instance = comp, \uart_tx_inst|work_en~0 , uart_tx_inst|work_en~0, rs232, 1 -instance = comp, \uart_tx_inst|work_en , uart_tx_inst|work_en, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[0]~13 , uart_tx_inst|baud_cnt[0]~13, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[10]~33 , uart_tx_inst|baud_cnt[10]~33, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[11]~35 , uart_tx_inst|baud_cnt[11]~35, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[11] , uart_tx_inst|baud_cnt[11], rs232, 1 -instance = comp, \uart_tx_inst|Equal1~0 , uart_tx_inst|Equal1~0, rs232, 1 -instance = comp, \uart_tx_inst|Equal1~1 , uart_tx_inst|Equal1~1, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[12]~37 , uart_tx_inst|baud_cnt[12]~37, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[12] , uart_tx_inst|baud_cnt[12], rs232, 1 -instance = comp, \uart_tx_inst|Equal1~3 , uart_tx_inst|Equal1~3, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[2]~17 , uart_tx_inst|baud_cnt[2]~17, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[2] , uart_tx_inst|baud_cnt[2], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[4]~21 , uart_tx_inst|baud_cnt[4]~21, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[4] , uart_tx_inst|baud_cnt[4], rs232, 1 -instance = comp, \uart_tx_inst|Equal1~2 , uart_tx_inst|Equal1~2, rs232, 1 -instance = comp, \uart_tx_inst|always1~0 , uart_tx_inst|always1~0, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[0] , uart_tx_inst|baud_cnt[0], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[1]~15 , uart_tx_inst|baud_cnt[1]~15, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[1] , uart_tx_inst|baud_cnt[1], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[3]~19 , uart_tx_inst|baud_cnt[3]~19, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[3] , uart_tx_inst|baud_cnt[3], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[6]~25 , uart_tx_inst|baud_cnt[6]~25, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[6] , uart_tx_inst|baud_cnt[6], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[7]~27 , uart_tx_inst|baud_cnt[7]~27, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[7] , uart_tx_inst|baud_cnt[7], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[8]~29 , uart_tx_inst|baud_cnt[8]~29, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[8] , uart_tx_inst|baud_cnt[8], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[9]~31 , uart_tx_inst|baud_cnt[9]~31, rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[9] , uart_tx_inst|baud_cnt[9], rs232, 1 -instance = comp, \uart_tx_inst|baud_cnt[10] , uart_tx_inst|baud_cnt[10], rs232, 1 -instance = comp, \uart_tx_inst|Equal2~1 , uart_tx_inst|Equal2~1, rs232, 1 -instance = comp, \uart_tx_inst|bit_flag , uart_tx_inst|bit_flag, rs232, 1 -instance = comp, \uart_tx_inst|always3~0 , uart_tx_inst|always3~0, rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[2]~2 , uart_tx_inst|bit_cnt[2]~2, rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[2] , uart_tx_inst|bit_cnt[2], rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[3]~4 , uart_tx_inst|bit_cnt[3]~4, rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[3] , uart_tx_inst|bit_cnt[3], rs232, 1 -instance = comp, \uart_tx_inst|always0~0 , uart_tx_inst|always0~0, rs232, 1 -instance = comp, \uart_tx_inst|always0~1 , uart_tx_inst|always0~1, rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[0]~5 , uart_tx_inst|bit_cnt[0]~5, rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[0] , uart_tx_inst|bit_cnt[0], rs232, 1 -instance = comp, \rx~input , rx~input, rs232, 1 -instance = comp, \uart_rx_inst|rx_reg1~0 , uart_rx_inst|rx_reg1~0, rs232, 1 -instance = comp, \uart_rx_inst|rx_reg1 , uart_rx_inst|rx_reg1, rs232, 1 -instance = comp, \uart_rx_inst|rx_reg2~feeder , uart_rx_inst|rx_reg2~feeder, rs232, 1 -instance = comp, \uart_rx_inst|rx_reg2 , uart_rx_inst|rx_reg2, rs232, 1 -instance = comp, \uart_rx_inst|rx_reg3~feeder , uart_rx_inst|rx_reg3~feeder, rs232, 1 -instance = comp, \uart_rx_inst|rx_reg3 , uart_rx_inst|rx_reg3, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[7]~0 , uart_rx_inst|rx_data[7]~0, rs232, 1 -instance = comp, \uart_rx_inst|always8~0 , uart_rx_inst|always8~0, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[7] , uart_rx_inst|rx_data[7], rs232, 1 -instance = comp, \uart_rx_inst|po_data[7] , uart_rx_inst|po_data[7], rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[1]~3 , uart_tx_inst|bit_cnt[1]~3, rs232, 1 -instance = comp, \uart_tx_inst|bit_cnt[1] , uart_tx_inst|bit_cnt[1], rs232, 1 -instance = comp, \uart_tx_inst|tx~2 , uart_tx_inst|tx~2, rs232, 1 -instance = comp, \uart_tx_inst|tx~5 , uart_tx_inst|tx~5, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[6]~feeder , uart_rx_inst|rx_data[6]~feeder, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[6] , uart_rx_inst|rx_data[6], rs232, 1 -instance = comp, \uart_rx_inst|rx_data[5] , uart_rx_inst|rx_data[5], rs232, 1 -instance = comp, \uart_rx_inst|po_data[5]~feeder , uart_rx_inst|po_data[5]~feeder, rs232, 1 -instance = comp, \uart_rx_inst|po_data[5] , uart_rx_inst|po_data[5], rs232, 1 -instance = comp, \uart_rx_inst|po_data[6] , uart_rx_inst|po_data[6], rs232, 1 -instance = comp, \uart_rx_inst|rx_data[4] , uart_rx_inst|rx_data[4], rs232, 1 -instance = comp, \uart_rx_inst|po_data[4]~feeder , uart_rx_inst|po_data[4]~feeder, rs232, 1 -instance = comp, \uart_rx_inst|po_data[4] , uart_rx_inst|po_data[4], rs232, 1 -instance = comp, \uart_rx_inst|rx_data[3] , uart_rx_inst|rx_data[3], rs232, 1 -instance = comp, \uart_rx_inst|po_data[3] , uart_rx_inst|po_data[3], rs232, 1 -instance = comp, \uart_tx_inst|Mux0~0 , uart_tx_inst|Mux0~0, rs232, 1 -instance = comp, \uart_tx_inst|Mux0~1 , uart_tx_inst|Mux0~1, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[2]~feeder , uart_rx_inst|rx_data[2]~feeder, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[2] , uart_rx_inst|rx_data[2], rs232, 1 -instance = comp, \uart_rx_inst|rx_data[1]~feeder , uart_rx_inst|rx_data[1]~feeder, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[1] , uart_rx_inst|rx_data[1], rs232, 1 -instance = comp, \uart_rx_inst|po_data[1] , uart_rx_inst|po_data[1], rs232, 1 -instance = comp, \uart_rx_inst|rx_data[0]~feeder , uart_rx_inst|rx_data[0]~feeder, rs232, 1 -instance = comp, \uart_rx_inst|rx_data[0] , uart_rx_inst|rx_data[0], rs232, 1 -instance = comp, \uart_rx_inst|po_data[0] , uart_rx_inst|po_data[0], rs232, 1 -instance = comp, \uart_tx_inst|tx~3 , uart_tx_inst|tx~3, rs232, 1 -instance = comp, \uart_tx_inst|tx~4 , uart_tx_inst|tx~4, rs232, 1 -instance = comp, \uart_tx_inst|tx~6 , uart_tx_inst|tx~6, rs232, 1 -instance = comp, \uart_tx_inst|tx~7 , uart_tx_inst|tx~7, rs232, 1 -instance = comp, \uart_tx_inst|tx , uart_tx_inst|tx, rs232, 1 diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_v.sdo b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_v.sdo deleted file mode 100644 index 588ece3..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_v.sdo +++ /dev/null @@ -1,2275 +0,0 @@ -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - - -// -// Device: Altera EP4CE15F23C8 Package FBGA484 -// - -// -// This file contains Slow Corner delays for the design using part EP4CE15F23C8, -// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius -// - -// -// This SDF file should be used for ModelSim (Verilog) only -// - -(DELAYFILE - (SDFVERSION "2.1") - (DESIGN "rs232") - (DATE "06/02/2023 03:03:50") - (VENDOR "Altera") - (PROGRAM "Quartus II 64-Bit") - (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") - (DIVIDER .) - (TIMESCALE 1 ps) - - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1841:1841:1841) (1853:1853:1853)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6066:6066:6066) (5939:5939:5939)) - (PORT sclr (903:903:903) (966:966:966)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (590:590:590)) - (PORT datab (341:341:341) (422:422:422)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT dataa (344:344:344) (434:434:434)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT datab (367:367:367) (448:448:448)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (457:457:457)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (461:461:461)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) - (DELAY - (ABSOLUTE - (PORT datab (368:368:368) (452:452:452)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (422:422:422)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (543:543:543) (580:580:580)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT dataa (387:387:387) (471:471:471)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT datad (533:533:533) (560:560:560)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1301:1301:1301) (1261:1261:1261)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (630:630:630) (642:642:642)) - (PORT datab (577:577:577) (601:601:601)) - (PORT datac (526:526:526) (560:560:560)) - (PORT datad (541:541:541) (560:560:560)) - (IOPATH dataa combout (456:456:456) (486:486:486)) - (IOPATH datab combout (457:457:457) (489:489:489)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (386:386:386) (487:487:487)) - (PORT datab (429:429:429) (538:538:538)) - (PORT datad (372:372:372) (479:479:479)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH datab combout (435:435:435) (433:433:433)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Add1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (647:647:647) (654:654:654)) - (PORT datab (570:570:570) (590:590:590)) - (PORT datac (573:573:573) (591:591:591)) - (PORT datad (330:330:330) (407:407:407)) - (IOPATH dataa combout (432:432:432) (446:446:446)) - (IOPATH datab combout (437:437:437) (436:436:436)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (345:345:345) (434:434:434)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (301:301:301) (385:385:385)) - (PORT datad (304:304:304) (381:381:381)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~0) - (DELAY - (ABSOLUTE - (PORT dataa (844:844:844) (830:830:830)) - (PORT datab (575:575:575) (601:601:601)) - (PORT datac (579:579:579) (594:594:594)) - (PORT datad (851:851:851) (810:810:810)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (870:870:870) (854:854:854)) - (PORT datab (901:901:901) (869:869:869)) - (PORT datac (872:872:872) (840:840:840)) - (PORT datad (577:577:577) (599:599:599)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal2\~2) - (DELAY - (ABSOLUTE - (PORT dataa (493:493:493) (485:485:485)) - (PORT datab (878:878:878) (859:859:859)) - (PORT datac (783:783:783) (700:700:700)) - (PORT datad (485:485:485) (457:457:457)) - (IOPATH dataa combout (405:405:405) (398:398:398)) - (IOPATH datab combout (432:432:432) (433:433:433)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1854:1854:1854)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (6063:6063:6063) (5936:5936:5936)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (464:464:464)) - (PORT datab (370:370:370) (454:454:454)) - (PORT datac (330:330:330) (415:415:415)) - (PORT datad (331:331:331) (408:408:408)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT datac (822:822:822) (795:795:795)) - (PORT datad (577:577:577) (600:600:600)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT dataa (891:891:891) (854:854:854)) - (PORT datab (579:579:579) (612:612:612)) - (PORT datac (827:827:827) (807:807:807)) - (PORT datad (237:237:237) (255:255:255)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always5\~0) - (DELAY - (ABSOLUTE - (PORT dataa (562:562:562) (592:592:592)) - (PORT datab (304:304:304) (328:328:328)) - (PORT datac (240:240:240) (267:267:267)) - (PORT datad (433:433:433) (406:406:406)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|start_nedge) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (849:849:849) (813:813:813)) - (PORT datad (461:461:461) (436:436:436)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datab (345:345:345) (425:425:425)) - (PORT datac (323:323:323) (401:401:401)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_obuf") - (INSTANCE tx\~output) - (DELAY - (ABSOLUTE - (PORT i (758:758:758) (794:794:794)) - (IOPATH i o (3336:3336:3336) (3399:3399:3399)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_clk\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (806:806:806) (852:852:852)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_clkctrl") - (INSTANCE sys_clk\~inputclkctrl) - (DELAY - (ABSOLUTE - (PORT inclk[0] (200:200:200) (189:189:189)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (482:482:482)) - (PORT datab (342:342:342) (423:423:423)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~1) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (484:484:484)) - (PORT datab (360:360:360) (449:449:449)) - (PORT datac (448:448:448) (419:419:419)) - (PORT datad (267:267:267) (303:303:303)) - (IOPATH dataa combout (420:420:420) (428:428:428)) - (IOPATH datab combout (432:432:432) (433:433:433)) - (IOPATH datac combout (327:327:327) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE sys_rst_n\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (766:766:766) (812:812:812)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~2) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (424:424:424)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~4) - (DELAY - (ABSOLUTE - (PORT datab (343:343:343) (422:422:422)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~0) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (PORT datac (303:303:303) (388:388:388)) - (PORT datad (303:303:303) (379:379:379)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|Add1\~6) - (DELAY - (ABSOLUTE - (PORT datad (323:323:323) (410:410:410)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|bit_cnt\~0) - (DELAY - (ABSOLUTE - (PORT dataa (372:372:372) (484:484:484)) - (PORT datab (308:308:308) (347:347:347)) - (PORT datad (441:441:441) (417:417:417)) - (IOPATH dataa combout (432:432:432) (446:446:446)) - (IOPATH datab combout (437:437:437) (436:436:436)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always4\~1) - (DELAY - (ABSOLUTE - (PORT dataa (373:373:373) (485:485:485)) - (PORT datab (366:366:366) (456:456:456)) - (PORT datad (261:261:261) (295:295:295)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (265:265:265) (290:290:290)) - (IOPATH datac combout (327:327:327) (316:316:316)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_flag) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_flag\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (866:866:866) (834:834:834)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_flag) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|work_en\~0) - (DELAY - (ABSOLUTE - (PORT datab (535:535:535) (562:562:562)) - (PORT datad (475:475:475) (448:448:448)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|work_en) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) - (DELAY - (ABSOLUTE - (PORT dataa (593:593:593) (629:629:629)) - (PORT datab (339:339:339) (421:421:421)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (363:363:363) (447:447:447)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (346:346:346) (436:436:436)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (302:302:302) (387:387:387)) - (PORT datad (302:302:302) (379:379:379)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (472:472:472) (452:452:452)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~1) - (DELAY - (ABSOLUTE - (PORT dataa (576:576:576) (604:604:604)) - (PORT datab (344:344:344) (427:427:427)) - (PORT datac (538:538:538) (561:561:561)) - (PORT datad (241:241:241) (260:260:260)) - (IOPATH dataa combout (392:392:392) (407:407:407)) - (IOPATH datab combout (393:393:393) (412:412:412)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (449:449:449)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH cin combout (607:607:607) (577:577:577)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~3) - (DELAY - (ABSOLUTE - (PORT datab (635:635:635) (646:646:646)) - (PORT datad (575:575:575) (598:598:598)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (446:446:446)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) - (DELAY - (ABSOLUTE - (PORT dataa (362:362:362) (446:446:446)) - (IOPATH dataa combout (471:471:471) (472:472:472)) - (IOPATH dataa cout (552:552:552) (416:416:416)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal1\~2) - (DELAY - (ABSOLUTE - (PORT dataa (584:584:584) (613:613:613)) - (PORT datab (578:578:578) (602:602:602)) - (PORT datac (526:526:526) (560:560:560)) - (PORT datad (560:560:560) (584:584:584)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always1\~0) - (DELAY - (ABSOLUTE - (PORT dataa (596:596:596) (633:633:633)) - (PORT datab (308:308:308) (333:333:333)) - (PORT datac (450:450:450) (425:425:425)) - (PORT datad (454:454:454) (432:432:432)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (393:393:393) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) - (DELAY - (ABSOLUTE - (PORT datab (359:359:359) (435:435:435)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) - (DELAY - (ABSOLUTE - (PORT datab (341:341:341) (421:421:421)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) - (DELAY - (ABSOLUTE - (PORT datab (343:343:343) (422:422:422)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) - (DELAY - (ABSOLUTE - (PORT datab (342:342:342) (425:425:425)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) - (DELAY - (ABSOLUTE - (PORT datab (360:360:360) (437:437:437)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datab cout (565:565:565) (421:421:421)) - (IOPATH datad combout (177:177:177) (155:155:155)) - (IOPATH cin combout (607:607:607) (577:577:577)) - (IOPATH cin cout (73:73:73) (73:73:73)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|baud_cnt\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1843:1843:1843) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5811:5811:5811) (5620:5620:5620)) - (PORT sclr (909:909:909) (977:977:977)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD sclr (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Equal2\~1) - (DELAY - (ABSOLUTE - (PORT dataa (807:807:807) (726:726:726)) - (PORT datab (636:636:636) (648:648:648)) - (PORT datac (524:524:524) (497:497:497)) - (PORT datad (576:576:576) (598:598:598)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (327:327:327) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_flag) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always3\~0) - (DELAY - (ABSOLUTE - (PORT datac (321:321:321) (399:399:399)) - (PORT datad (329:329:329) (402:402:402)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) - (DELAY - (ABSOLUTE - (PORT dataa (756:756:756) (694:694:694)) - (PORT datab (322:322:322) (359:359:359)) - (PORT datad (517:517:517) (486:486:486)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) - (DELAY - (ABSOLUTE - (PORT dataa (283:283:283) (315:315:315)) - (PORT datab (308:308:308) (332:332:332)) - (PORT datad (474:474:474) (447:447:447)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~0) - (DELAY - (ABSOLUTE - (PORT datab (367:367:367) (446:446:446)) - (PORT datad (330:330:330) (403:403:403)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|always0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (413:413:413) (528:528:528)) - (PORT datab (425:425:425) (533:533:533)) - (PORT datac (346:346:346) (445:445:445)) - (PORT datad (485:485:485) (457:457:457)) - (IOPATH dataa combout (421:421:421) (418:418:418)) - (IOPATH datab combout (407:407:407) (408:408:408)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) - (DELAY - (ABSOLUTE - (PORT dataa (597:597:597) (643:643:643)) - (PORT datab (320:320:320) (356:356:356)) - (PORT datad (836:836:836) (817:817:817)) - (IOPATH dataa combout (404:404:404) (398:398:398)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_io_ibuf") - (INSTANCE rx\~input) - (DELAY - (ABSOLUTE - (IOPATH i o (796:796:796) (842:842:842)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg1\~0) - (DELAY - (ABSOLUTE - (PORT datad (3626:3626:3626) (3787:3787:3787)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg1) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg2\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (298:298:298) (368:368:368)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg2) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_reg3\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (307:307:307) (384:384:384)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_reg3) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5805:5805:5805) (5615:5615:5615)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) - (DELAY - (ABSOLUTE - (PORT datad (819:819:819) (787:787:787)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|always8\~0) - (DELAY - (ABSOLUTE - (PORT dataa (371:371:371) (483:483:483)) - (PORT datab (306:306:306) (344:344:344)) - (PORT datad (318:318:318) (405:405:405)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1271:1271:1271) (1242:1242:1242)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) - (DELAY - (ABSOLUTE - (PORT dataa (657:657:657) (663:663:663)) - (PORT datab (320:320:320) (357:357:357)) - (PORT datad (520:520:520) (490:490:490)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (494:494:494) (496:496:496)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|bit_cnt\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~2) - (DELAY - (ABSOLUTE - (PORT dataa (390:390:390) (492:492:492)) - (PORT datab (423:423:423) (530:530:530)) - (PORT datad (367:367:367) (473:473:473)) - (IOPATH dataa combout (471:471:471) (453:453:453)) - (IOPATH datab combout (472:472:472) (452:452:452)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~5) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (448:448:448)) - (PORT datab (278:278:278) (304:304:304)) - (PORT datac (549:549:549) (592:592:592)) - (PORT datad (538:538:538) (558:558:558)) - (IOPATH dataa combout (481:481:481) (491:491:491)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datac combout (324:324:324) (316:316:316)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (325:325:325) (396:396:396)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT asdata (1261:1261:1261) (1233:1233:1233)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (812:812:812) (791:791:791)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1280:1280:1280) (1251:1251:1251)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT asdata (1244:1244:1244) (1213:1213:1213)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (809:809:809) (792:792:792)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT asdata (1240:1240:1240) (1212:1212:1212)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1606:1606:1606) (1505:1505:1505)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~0) - (DELAY - (ABSOLUTE - (PORT dataa (417:417:417) (532:532:532)) - (PORT datab (336:336:336) (413:413:413)) - (PORT datad (389:389:389) (495:495:495)) - (IOPATH dataa combout (461:461:461) (481:481:481)) - (IOPATH datab combout (410:410:410) (408:408:408)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|Mux0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (414:414:414) (529:529:529)) - (PORT datab (335:335:335) (411:411:411)) - (PORT datad (238:238:238) (257:257:257)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (454:454:454) (473:473:473)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (323:323:323) (402:402:402)) - (IOPATH datac combout (327:327:327) (316:316:316)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[2\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datad (511:511:511) (537:537:537)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[1\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1299:1299:1299) (1269:1269:1269)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) - (DELAY - (ABSOLUTE - (PORT datac (323:323:323) (401:401:401)) - (IOPATH datac combout (327:327:327) (316:316:316)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|rx_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1842:1842:1842) (1855:1855:1855)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5817:5817:5817) (5626:5626:5626)) - (PORT ena (1037:1037:1037) (1013:1013:1013)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_rx_inst\|po_data\[0\]) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT asdata (1290:1290:1290) (1262:1262:1262)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (PORT ena (1708:1708:1708) (1649:1649:1649)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD asdata (posedge clk) (212:212:212)) - (HOLD ena (posedge clk) (212:212:212)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~3) - (DELAY - (ABSOLUTE - (PORT dataa (337:337:337) (420:420:420)) - (PORT datab (431:431:431) (540:540:540)) - (PORT datad (374:374:374) (481:481:481)) - (IOPATH dataa combout (392:392:392) (398:398:398)) - (IOPATH datab combout (455:455:455) (436:436:436)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~4) - (DELAY - (ABSOLUTE - (PORT dataa (416:416:416) (531:531:531)) - (PORT datab (429:429:429) (537:537:537)) - (PORT datad (238:238:238) (256:256:256)) - (IOPATH dataa combout (453:453:453) (413:413:413)) - (IOPATH datab combout (473:473:473) (487:487:487)) - (IOPATH datac combout (462:462:462) (482:482:482)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~6) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (641:641:641)) - (PORT datab (580:580:580) (608:608:608)) - (PORT datac (245:245:245) (276:276:276)) - (PORT datad (239:239:239) (257:257:257)) - (IOPATH dataa combout (432:432:432) (446:446:446)) - (IOPATH datab combout (472:472:472) (473:473:473)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE uart_tx_inst\|tx\~7) - (DELAY - (ABSOLUTE - (PORT dataa (391:391:391) (493:493:493)) - (PORT datab (278:278:278) (303:303:303)) - (PORT datac (245:245:245) (277:277:277)) - (PORT datad (238:238:238) (256:256:256)) - (IOPATH dataa combout (448:448:448) (472:472:472)) - (IOPATH datab combout (473:473:473) (489:489:489)) - (IOPATH datac combout (324:324:324) (315:315:315)) - (IOPATH datad combout (177:177:177) (155:155:155)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE uart_tx_inst\|tx) - (DELAY - (ABSOLUTE - (PORT clk (1844:1844:1844) (1856:1856:1856)) - (PORT d (99:99:99) (115:115:115)) - (PORT clrn (5544:5544:5544) (5322:5322:5322)) - (IOPATH (posedge clk) q (261:261:261) (261:261:261)) - (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (212:212:212)) - ) - ) -) diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/rs232.v b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/rs232.v deleted file mode 100644 index 15f9b9d..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/rs232.v +++ /dev/null @@ -1,75 +0,0 @@ -`timescale 1ns/1ns -//////////////////////////////////////////////////////////////////////// -// Author : EmbedFire -// Create Date : 2019/06/12 -// Module Name : rs232 -// Project Name : rs232 -// Target Devices: Altera EP4CE10F17C8N -// Tool Versions : Quartus 13.0 -// Description : RS232顶层模块 -// -// Revision : V1.0 -// Additional Comments: -// -// 实验平台: 野火_征途Pro_FPGA开发板 -// 公司 : http://www.embedfire.com -// 论坛 : http://www.firebbs.cn -// 淘宝 : https://fire-stm32.taobao.com -//////////////////////////////////////////////////////////////////////// - -module rs232 -( - input wire sys_clk , //系统时钟50MHz - input wire sys_rst_n , //全局复位 - input wire rx , //串口接收数据 - - output wire tx //串口发送数据 -); - -//********************************************************************// -//****************** Parameter and Internal Signal *******************// -//********************************************************************// -//parameter define -parameter UART_BPS = 14'd9600 , //比特率 - CLK_FREQ = 26'd50_000_000 ; //时钟频率 - -//wire define -wire [7:0] po_data; -wire po_flag; - -//********************************************************************// -//*************************** Instantiation **************************// -//********************************************************************// -//------------------------ uart_rx_inst ------------------------ -uart_rx -#( - .UART_BPS (UART_BPS ), //串口波特率 - .CLK_FREQ (CLK_FREQ ) //时钟频率 -) -uart_rx_inst -( - .sys_clk (sys_clk ), //input sys_clk - .sys_rst_n (sys_rst_n ), //input sys_rst_n - .rx (rx ), //input rx - - .po_data (po_data ), //output [7:0] po_data - .po_flag (po_flag ) //output po_flag -); - -//------------------------ uart_tx_inst ------------------------ -uart_tx -#( - .UART_BPS (UART_BPS ), //串口波特率 - .CLK_FREQ (CLK_FREQ ) //时钟频率 -) -uart_tx_inst -( - .sys_clk (sys_clk ), //input sys_clk - .sys_rst_n (sys_rst_n ), //input sys_rst_n - .pi_data (po_data ), //input [7:0] pi_data - .pi_flag (po_flag ), //input pi_flag - - .tx (tx ) //output tx -); - -endmodule diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_rx.v b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_rx.v deleted file mode 100644 index 5ebbaba..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_rx.v +++ /dev/null @@ -1,154 +0,0 @@ -`timescale 1ns/1ns -//////////////////////////////////////////////////////////////////////// -// Author : EmbedFire -//Create Date : 2019/06/12 -// Module Name : uart_rx -// Project Name : rs232 -// Target Devices: Altera EP4CE10F17C8N -// Tool Versions : Quartus 13.0 -// Description : -// -// Revision : V1.0 -// Additional Comments: -// -// 实验平台: 野火_征途Pro_FPGA开发板 -// 公司 : http://www.embedfire.com -// 论坛 : http://www.firebbs.cn -// 淘宝 : https://fire-stm32.taobao.com -//////////////////////////////////////////////////////////////////////// - -module uart_rx -#( - parameter UART_BPS = 'd9600, //串口波特率 - parameter CLK_FREQ = 'd50_000_000 //时钟频率 -) -( - input wire sys_clk , //系统时钟50MHz - input wire sys_rst_n , //全局复位 - input wire rx , //串口接收数据 - - output reg [7:0] po_data , //串转并后的8bit数据 - output reg po_flag //串转并后的数据有效标志信号 -); - -//********************************************************************// -//****************** Parameter and Internal Signal *******************// -//********************************************************************// -//localparam define -localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; - -//reg define -reg rx_reg1 ; -reg rx_reg2 ; -reg rx_reg3 ; -reg start_nedge ; -reg work_en ; -reg [12:0] baud_cnt ; -reg bit_flag ; -reg [3:0] bit_cnt ; -reg [7:0] rx_data ; -reg rx_flag ; - -//********************************************************************// -//***************************** Main Code ****************************// -//********************************************************************// -//插入两级寄存器进行数据同步，用来消除亚稳态 -//rx_reg1:第一级寄存器，寄存器空闲状态复位为1 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - rx_reg1 <= 1'b1; - else - rx_reg1 <= rx; - -//rx_reg2:第二级寄存器，寄存器空闲状态复位为1 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - rx_reg2 <= 1'b1; - else - rx_reg2 <= rx_reg1; - -//rx_reg3:第三级寄存器和第二级寄存器共同构成下降沿检测 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - rx_reg3 <= 1'b1; - else - rx_reg3 <= rx_reg2; - -//start_nedge:检测到下降沿时start_nedge产生一个时钟的高电平 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - start_nedge <= 1'b0; - else if((~rx_reg2) && (rx_reg3)) - start_nedge <= 1'b1; - else - start_nedge <= 1'b0; - -//work_en:接收数据工作使能信号 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - work_en <= 1'b0; - else if(start_nedge == 1'b1) - work_en <= 1'b1; - else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) - work_en <= 1'b0; - -//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - baud_cnt <= 13'b0; - else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) - baud_cnt <= 13'b0; - else if(work_en == 1'b1) - baud_cnt <= baud_cnt + 1'b1; - -//bit_flag:当baud_cnt计数器计数到中间数时采样的数据最稳定， -//此时拉高一个标志信号表示数据可以被取走 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - bit_flag <= 1'b0; - else if(baud_cnt == BAUD_CNT_MAX/2 - 1) - bit_flag <= 1'b1; - else - bit_flag <= 1'b0; - -//bit_cnt:有效数据个数计数器，当8个有效数据（不含起始位和停止位） -//都接收完成后计数器清零 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - bit_cnt <= 4'b0; - else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) - bit_cnt <= 4'b0; - else if(bit_flag ==1'b1) - bit_cnt <= bit_cnt + 1'b1; - -//rx_data:输入数据进行移位 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - rx_data <= 8'b0; - else if((bit_cnt >= 4'd1)&&(bit_cnt <= 4'd8)&&(bit_flag == 1'b1)) - rx_data <= {rx_reg3, rx_data[7:1]}; - -//rx_flag:输入数据移位完成时rx_flag拉高一个时钟的高电平 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - rx_flag <= 1'b0; - else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) - rx_flag <= 1'b1; - else - rx_flag <= 1'b0; - -//po_data:输出完整的8位有效数据 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - po_data <= 8'b0; - else if(rx_flag == 1'b1) - po_data <= rx_data; - -//po_flag:输出数据有效标志（比rx_flag延后一个时钟周期，为了和po_data同步） -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - po_flag <= 1'b0; - else - po_flag <= rx_flag; - -endmodule diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_tx.v b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_tx.v deleted file mode 100644 index cf80fdf..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_tx.v +++ /dev/null @@ -1,104 +0,0 @@ -`timescale 1ns/1ns -//////////////////////////////////////////////////////////////////////// -// Author : EmbedFire -// Create Date : 2019/06/12 -// Module Name : uart_tx -// Project Name : rs232 -// Target Devices: Altera EP4CE10F17C8N -// Tool Versions : Quartus 13.0 -// Description : -// -// Revision : V1.0 -// Additional Comments: -// -// 实验平台: 野火_征途Pro_FPGA开发板 -// 公司 : http://www.embedfire.com -// 论坛 : http://www.firebbs.cn -// 淘宝 : https://fire-stm32.taobao.com -//////////////////////////////////////////////////////////////////////// - -module uart_tx -#( - parameter UART_BPS = 'd9600, //串口波特率 - parameter CLK_FREQ = 'd50_000_000 //时钟频率 -) -( - input wire sys_clk , //系统时钟50MHz - input wire sys_rst_n , //全局复位 - input wire [7:0] pi_data , //模块输入的8bit数据 - input wire pi_flag , //并行数据有效标志信号 - - output reg tx //串转并后的1bit数据 -); - -//********************************************************************// -//****************** Parameter and Internal Signal *******************// -//********************************************************************// -//localparam define -localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; - -//reg define -reg [12:0] baud_cnt; -reg bit_flag; -reg [3:0] bit_cnt ; -reg work_en ; - -//********************************************************************// -//***************************** Main Code ****************************// -//********************************************************************// -//work_en:接收数据工作使能信号 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - work_en <= 1'b0; - else if(pi_flag == 1'b1) - work_en <= 1'b1; - else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) - work_en <= 1'b0; - -//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - baud_cnt <= 13'b0; - else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) - baud_cnt <= 13'b0; - else if(work_en == 1'b1) - baud_cnt <= baud_cnt + 1'b1; - -//bit_flag:当baud_cnt计数器计数到1时让bit_flag拉高一个时钟的高电平 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - bit_flag <= 1'b0; - else if(baud_cnt == 13'd1) - bit_flag <= 1'b1; - else - bit_flag <= 1'b0; - -//bit_cnt:数据位数个数计数，10个有效数据（含起始位和停止位）到来后计数器清零 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - bit_cnt <= 4'b0; - else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) - bit_cnt <= 4'b0; - else if((bit_flag == 1'b1) && (work_en == 1'b1)) - bit_cnt <= bit_cnt + 1'b1; - -//tx:输出数据在满足rs232协议（起始位为0，停止位为1）的情况下一位一位输出 -always@(posedge sys_clk or negedge sys_rst_n) - if(sys_rst_n == 1'b0) - tx <= 1'b1; //空闲状态时为高电平 - else if(bit_flag == 1'b1) - case(bit_cnt) - 0 : tx <= 1'b0; - 1 : tx <= pi_data[0]; - 2 : tx <= pi_data[1]; - 3 : tx <= pi_data[2]; - 4 : tx <= pi_data[3]; - 5 : tx <= pi_data[4]; - 6 : tx <= pi_data[5]; - 7 : tx <= pi_data[6]; - 8 : tx <= pi_data[7]; - 9 : tx <= 1'b1; - default : tx <= 1'b1; - endcase - -endmodule diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_rs232.v b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_rs232.v deleted file mode 100644 index 1cc87c8..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_rs232.v +++ /dev/null @@ -1,98 +0,0 @@ -`timescale 1ns/1ns -//////////////////////////////////////////////////////////////////////// -// Author : EmbedFire -// Create Date : 2019/06/12 -// Module Name : tb_rs232 -// Project Name : rs232 -// Target Devices: Altera EP4CE10F17C8N -// Tool Versions : Quartus 13.0 -// Description : -// -// Revision : V1.0 -// Additional Comments: -// -// 实验平台: 野火_征途Pro_FPGA开发板 -// 公司 : http://www.embedfire.com -// 论坛 : http://www.firebbs.cn -// 淘宝 : https://fire-stm32.taobao.com -//////////////////////////////////////////////////////////////////////// - -module tb_rs232(); - -//********************************************************************// -//****************** Parameter and Internal Signal *******************// -//********************************************************************// -//wire define -wire tx ; - -//reg define -reg sys_clk ; -reg sys_rst_n ; -reg rx ; - -//********************************************************************// -//***************************** Main Code ****************************// -//********************************************************************// -//初始化系统时钟、全局复位和输入信号 -initial begin - sys_clk = 1'b1; - sys_rst_n <= 1'b0; - rx <= 1'b1; - #20; - sys_rst_n <= 1'b1; -end - -//调用任务rx_byte -initial begin - #200 - rx_byte(); -end - -//sys_clk:每10ns电平翻转一次，产生一个50MHz的时钟信号 -always #10 sys_clk = ~sys_clk; - -//创建任务rx_byte，本次任务调用rx_bit任务，发送8次数据，分别为0~7 -task rx_byte(); //因为不需要外部传递参数，所以括号中没有输入 - integer j; - for(j=0; j<8; j=j+1) //调用8次rx_bit任务，每次发送的值从0变化7 - rx_bit(j); -endtask - -//创建任务rx_bit，每次发送的数据有10位，data的值分别为0到7由j的值传递进来 -task rx_bit( - input [7:0] data -); - integer i; - for(i=0; i<10; i=i+1) begin - case(i) - 0: rx <= 1'b0; - 1: rx <= data[0]; - 2: rx <= data[1]; - 3: rx <= data[2]; - 4: rx <= data[3]; - 5: rx <= data[4]; - 6: rx <= data[5]; - 7: rx <= data[6]; - 8: rx <= data[7]; - 9: rx <= 1'b1; - endcase - #(5208*20); //每发送1位数据延时5208个时钟周期 - end -endtask - -//********************************************************************// -//*************************** Instantiation **************************// -//********************************************************************// -//------------------------ rs232_inst ------------------------ -rs232 rs232_inst -( - .sys_clk (sys_clk ), //input sys_clk - .sys_rst_n (sys_rst_n ), //input sys_rst_n - .rx (rx ), //input rx - - .tx (tx ) //output tx -); - -endmodule - - diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_rx.v b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_rx.v deleted file mode 100644 index 8c0c390..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_rx.v +++ /dev/null @@ -1,103 +0,0 @@ -`timescale 1ns/1ns -//////////////////////////////////////////////////////////////////////// -// Author : EmbedFire -// Create Date : 2019/06/12 -// Module Name : tb_uart_rx -// Project Name : rs232 -// Target Devices: Altera EP4CE10F17C8N -// Tool Versions : Quartus 13.0 -// Description : -// -// Revision : V1.0 -// Additional Comments: -// -// 实验平台: 野火_征途Pro_FPGA开发板 -// 公司 : http://www.embedfire.com -// 论坛 : http://www.firebbs.cn -// 淘宝 : https://fire-stm32.taobao.com -//////////////////////////////////////////////////////////////////////// - -module tb_uart_rx(); - -//********************************************************************// -//****************** Parameter and Internal Signal *******************// -//********************************************************************// -//reg define -reg sys_clk; -reg sys_rst_n; -reg rx; - -//wire define -wire [7:0] po_data; -wire po_flag; - -//********************************************************************// -//***************************** Main Code ****************************// -//********************************************************************// -//初始化系统时钟、全局复位和输入信号 -initial begin - sys_clk = 1'b1; - sys_rst_n <= 1'b0; - rx <= 1'b1; - #20; - sys_rst_n <= 1'b1; -end - -//模拟发送8次数据，分别为0~7 -initial begin - #200 - rx_bit(8'd0); //任务的调用，任务名+括号中要传递进任务的参数 - rx_bit(8'd1); - rx_bit(8'd2); - rx_bit(8'd3); - rx_bit(8'd4); - rx_bit(8'd5); - rx_bit(8'd6); - rx_bit(8'd7); -end - -//sys_clk:每10ns电平翻转一次，产生一个50MHz的时钟信号 -always #10 sys_clk = ~sys_clk; - -//定义一个名为rx_bit的任务，每次发送的数据有10位 -//data的值分别为0~7由j的值传递进来 -//任务以task开头，后面紧跟着的是任务名，调用时使用 -task rx_bit( - //传递到任务中的参数，调用任务的时候从外部传进来一个8位的值 - input [7:0] data -); - integer i; //定义一个常量 -//用for循环产生一帧数据，for括号中最后执行的内容只能写i=i+1 -//不可以写成C语言i=i++的形式 - for(i=0; i<10; i=i+1) begin - case(i) - 0: rx <= 1'b0; - 1: rx <= data[0]; - 2: rx <= data[1]; - 3: rx <= data[2]; - 4: rx <= data[3]; - 5: rx <= data[4]; - 6: rx <= data[5]; - 7: rx <= data[6]; - 8: rx <= data[7]; - 9: rx <= 1'b1; - endcase - #(5208*20); //每发送1位数据延时5208个时钟周期 - end -endtask //任务以endtask结束 - -//********************************************************************// -//*************************** Instantiation **************************// -//********************************************************************// -//------------------------uart_rx_inst------------------------ -uart_rx uart_rx_inst( - .sys_clk (sys_clk ), //input sys_clk - .sys_rst_n (sys_rst_n ), //input sys_rst_n - .rx (rx ), //input rx - - .po_data (po_data ), //output [7:0] po_data - .po_flag (po_flag ) //output po_flag -); - -endmodule - diff --git a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_tx.v b/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_tx.v deleted file mode 100644 index b0ecf1c..0000000 --- a/fpga/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_tx.v +++ /dev/null @@ -1,117 +0,0 @@ -`timescale 1ns/1ns -///////////////////////////////////////////////////////////////////////// -// Author : EmbedFire -// Create Date : 2019/06/12 -// Module Name : tb_uart_tx -// Project Name : rs232 -// Target Devices: Altera EP4CE10F17C8N -// Tool Versions : Quartus 13.0 -// Description : -// -// Revision : V1.0 -// Additional Comments: -// -// 实验平台: 野火_征途Pro_FPGA开发板 -// 公司 : http://www.embedfire.com -// 论坛 : http://www.firebbs.cn -// 淘宝 : https://fire-stm32.taobao.com -//////////////////////////////////////////////////////////////////////// - -module tb_uart_tx(); - -//********************************************************************// -//****************** Parameter and Internal Signal *******************// -//********************************************************************// -//reg define -reg sys_clk; -reg sys_rst_n; -reg [7:0] pi_data; -reg pi_flag; - -//wire define -wire tx; - -//********************************************************************// -//***************************** Main Code ****************************// -//********************************************************************// -//初始化系统时钟、全局复位 -initial begin - sys_clk = 1'b1; - sys_rst_n <= 1'b0; - #20; - sys_rst_n <= 1'b1; -end - -//模拟发送7次数据，分别为0~7 -initial begin - pi_data <= 8'b0; - pi_flag <= 1'b0; - #200 - //发送数据0 - pi_data <= 8'd0; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; -//每发送1bit数据需要5208个时钟周期，一帧数据为10bit -//所以需要数据延时(5208*20*10)后再产生下一个数据 - #(5208*20*10); - //发送数据1 - pi_data <= 8'd1; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; - #(5208*20*10); - //发送数据2 - pi_data <= 8'd2; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; - #(5208*20*10); - //发送数据3 - pi_data <= 8'd3; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; - #(5208*20*10); - //发送数据4 - pi_data <= 8'd4; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; - #(5208*20*10); - //发送数据5 - pi_data <= 8'd5; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; - #(5208*20*10); - //发送数据6 - pi_data <= 8'd6; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; - #(5208*20*10); - //发送数据7 - pi_data <= 8'd7; - pi_flag <= 1'b1; - #20 - pi_flag <= 1'b0; -end - -//sys_clk:每10ns电平翻转一次，产生一个50MHz的时钟信号 -always #10 sys_clk = ~sys_clk; - -//********************************************************************// -//*************************** Instantiation **************************// -//********************************************************************// -//------------------------uart_rx_inst------------------------ -uart_tx uart_tx_inst( - .sys_clk (sys_clk ), //input sys_clk - .sys_rst_n (sys_rst_n ), //input sys_rst_n - .pi_data (pi_data ), //output [7:0] pi_data - .pi_flag (pi_flag ), //output pi_flag - - .tx (tx ) //input tx -); - -endmodule diff --git "a/fpga/smh-ac415-fpga/examples/05_rs232/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/fpga/smh-ac415-fpga/examples/05_rs232/\345\256\236\351\252\214\347\216\260\350\261\241.txt" deleted file mode 100644 index 33456c5..0000000 --- "a/fpga/smh-ac415-fpga/examples/05_rs232/\345\256\236\351\252\214\347\216\260\350\261\241.txt" +++ /dev/null @@ -1,2 +0,0 @@ -现象：把usb插入电脑，预先安装ch340串口驱动，打开某个串口软件，波特率选择9600，接收发送均选择hex，发送框输入“1234567890abefcd”，接收框会显示“12 34 56 78 90 AB EF CD ”，此例程参考野火fpga例程修改而来。具体可参考野火教程。 -测试：可以测试串口ch340是否正常。 \ No newline at end of file -- cgit v1.2.3