From 5aaf9d42ebe4767b7a076a2c615406549b4529f4 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 1 May 2025 21:07:24 +0100 Subject: tidyingup --- fpga/hp_lcd_driver/delay.vhdl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/hp_lcd_driver/delay.vhdl') diff --git a/fpga/hp_lcd_driver/delay.vhdl b/fpga/hp_lcd_driver/delay.vhdl index 2e777b6..66c5c5d 100644 --- a/fpga/hp_lcd_driver/delay.vhdl +++ b/fpga/hp_lcd_driver/delay.vhdl @@ -9,7 +9,7 @@ entity delay is end delay; architecture Behavioral of delay is - signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); + signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); begin o <= flipflops(flipflops'high); -- cgit v1.2.3