From 4c3c9419ec26b863ee22e56730f036254d09d16a Mon Sep 17 00:00:00 2001 From: root Date: Thu, 1 May 2025 20:10:08 +0100 Subject: tidying --- fpga/hp_lcd_driver/delay.vhdl | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 fpga/hp_lcd_driver/delay.vhdl (limited to 'fpga/hp_lcd_driver/delay.vhdl') diff --git a/fpga/hp_lcd_driver/delay.vhdl b/fpga/hp_lcd_driver/delay.vhdl new file mode 100644 index 0000000..2e777b6 --- /dev/null +++ b/fpga/hp_lcd_driver/delay.vhdl @@ -0,0 +1,24 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity delay is + generic (stages : natural := 2); + port (clk : in std_logic; + i : in std_logic; + o : out std_logic); +end delay; + +architecture Behavioral of delay is + signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); +begin + + o <= flipflops(flipflops'high); + + clk_proc : process(clk, flipflops, i) + begin + if rising_edge(clk) then + flipflops <= flipflops(flipflops'high-1 downto 0) & i; + end if; + end process; + +end Behavioral; -- cgit v1.2.3