From dafbdab96bcaf604ada97260fccefdd6aca60335 Mon Sep 17 00:00:00 2001
From: root <root@new-fish.medaka.james.internal>
Date: Wed, 6 Aug 2025 05:59:30 +0100
Subject: merged a7

---
 fpga/hp_lcd_driver/artix7.mk | 51 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 fpga/hp_lcd_driver/artix7.mk

(limited to 'fpga/hp_lcd_driver/artix7.mk')

diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk
new file mode 100644
index 0000000..578468c
--- /dev/null
+++ b/fpga/hp_lcd_driver/artix7.mk
@@ -0,0 +1,51 @@
+BUILD=build_${BOARD}
+
+IP= \
+	artix7_ip/blk_mem_gen_0.tcl \
+	artix7_ip/mmcm_0.tcl \
+	artix7_ip/mmcm_1.tcl 
+
+
+BIT=${BUILD}/out/hp_lcd_driver.bit
+
+IP_STAMP=${IP:artix7_ip/%.tcl=${BUILD}/ip/%/stamp}
+SRCS= ${IP} \
+	artix7_config.tcl \
+	artix7_hp_lcd_driver.tcl \
+	${BOARD}.tcl \
+	${BOARD}.xdc \
+	clkgen_artix7.vhdl \
+	debounce.vhdl \
+	delay.vhdl \
+	edge_det.vhdl \
+	hp_lcd_driver.vhdl \
+	input_formatter.vhdl \
+	input_stage.vhdl \
+	output_analog.vhdl \
+	output_formatter.vhdl \
+	output_stage.vhdl \
+	synchronizer.vhdl \
+	tmds_encoder.vhdl \
+	tmds_encode.vhdl \
+	tmds_output_artix7.vhdl \
+	tmds_phy_artix7.vhdl \
+	vram_artix7.vhdl
+
+
+
+OPENOCD=openocd -f openocd/${BOARD}.cfg
+
+default:  ${BUILD}/build.stamp
+
+${BUILD}/build.stamp:${SRCS} ${IP_STAMP}
+	mkdir -p ${BUILD}
+	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch  -source ../artix7_hp_lcd_driver.tcl)
+	touch $@
+
+${BUILD}/ip/%/stamp:artix7_ip/%.tcl
+	mkdir -p ${BUILD}/ip
+	/bin/rm -rf $(dir $@)
+	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@
+
+
+${BIT}: ${BUILD}/build.stamp
-- 
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