From cf579b99036b7c9f492332d763cd0b843cf340c4 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 4 Sep 2025 01:36:10 +0100 Subject: ebaz4205 --- .../ebaz4205_fpga/src/hdl/.system_wrapper.vhd.swp | Bin 0 -> 16384 bytes fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py | 6 + .../ebaz4205_fpga/src/hdl/ebaz4205_top.vhd | 257 ++++++++ .../ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl | 99 +++ .../ebaz4205_fpga/src/hdl/system_wrapper.vhd | 389 ++++++++++++ .../ebaz4205_fpga/src/xilinx/bd/system.tcl | 693 +++++++++++++++++++++ .../ebaz4205_fpga/src/xilinx/xdc/bitstream.xdc | 31 + .../ebaz4205_fpga/src/xilinx/xdc/general.xdc | 29 + .../ebaz4205_fpga/src/xilinx/xdc/pinout.xdc | 54 ++ 9 files changed, 1558 insertions(+) create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/hdl/.system_wrapper.vhd.swp create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/hdl/system_wrapper.vhd create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/bitstream.xdc create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/general.xdc create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/pinout.xdc (limited to 'fpga/ebaz4205/ebaz4205_fpga/src') diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/.system_wrapper.vhd.swp b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/.system_wrapper.vhd.swp new file mode 100644 index 0000000..dc6cc6a Binary files /dev/null and b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/.system_wrapper.vhd.swp differ diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py new file mode 100644 index 0000000..c25a02e --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py @@ -0,0 +1,6 @@ +files = [ + "ebaz4205_top.vhd", + "system_wrapper.vhd", + "fifo_to_axi.vhdl" +] + diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd new file mode 100644 index 0000000..3f97d97 --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd @@ -0,0 +1,257 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2020 - embed-me +-- +-- Lukas Lichtl +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License v2 as published by +-- the Free Software Foundation. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- +-------------------------------------------------------------------------------- +-- Function description: +-- +-------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity ebaz4205_top is + + port ( + -- ddr + ddr_addr_io : inout std_logic_vector (14 downto 0); + ddr_ba_io : inout std_logic_vector (2 downto 0); + ddr_cas_n_io : inout std_logic; + ddr_ck_n_io : inout std_logic; + ddr_ck_p_io : inout std_logic; + ddr_cke_io : inout std_logic; + ddr_cs_n_io : inout std_logic; + ddr_dm_io : inout std_logic_vector (3 downto 0); + ddr_dq_io : inout std_logic_vector (31 downto 0); + ddr_dqs_n_io : inout std_logic_vector (3 downto 0); + ddr_dqs_p_io : inout std_logic_vector (3 downto 0); + ddr_odt_io : inout std_logic; + ddr_ras_n_io : inout std_logic; + ddr_reset_n_io : inout std_logic; + ddr_we_n_io : inout std_logic; + -- eth0 + eth0_clk_o : out std_logic; -- alternative clock, only used when Oscillator is missing on the PCB + eth0_gmii_rx_clk_i : in std_logic; + eth0_gmii_rx_dv_i : in std_logic; + eth0_gmii_rxd_i : in std_logic_vector (3 downto 0); + eth0_gmii_tx_clk_i : in std_logic; + eth0_gmii_tx_en_o : out std_logic_vector (0 to 0); + eth0_gmii_txd_o : out std_logic_vector (3 downto 0); + eth0_mdio_mdc_o : out std_logic; + eth0_mdio_mdio_io : inout std_logic; + -- ios + fixed_io_ddr_vrn_io : inout std_logic; + fixed_io_ddr_vrp_io : inout std_logic; + fixed_io_mio_io : inout std_logic_vector (53 downto 0); + fixed_io_ps_clk_io : inout std_logic; + fixed_io_ps_porb_io : inout std_logic; + fixed_io_ps_srstb_io : inout std_logic; + green_led : out std_logic; + red_led : out std_logic); + +end entity ebaz4205_top; + + + +architecture arch of ebaz4205_top is + + signal eth0_gmii_txd : std_logic_vector(7 downto 0); + signal eth0_gmii_rxd : std_logic_vector(7 downto 0); + + signal emio_i : std_logic_vector(63 downto 0); + signal emio_o : std_logic_vector(63 downto 0); + signal emio_t : std_logic_vector(63 downto 0); + + +signal hp0_aclk:std_logic; +signal hp0_nrst:std_logic; +signal hp0_arvalid:std_logic; +signal hp0_araddr:std_logic_vector(31 downto 0); +signal hp0_arready:std_logic; +signal hp0_awaddr:std_logic_vector(31 downto 0); +signal hp0_awready:std_logic; +signal hp0_awvalid:std_logic; +signal hp0_bready:std_logic; +signal hp0_bvalid:std_logic; +signal hp0_rdata:std_logic_vector(63 downto 0); +signal hp0_wdata:std_logic_vector(63 downto 0); +signal hp0_rready:std_logic; +signal hp0_rvalid:std_logic; +signal hp0_wready:std_logic; +signal hp0_wvalid:std_logic; +signal hp0_wstrb:std_logic_vector(7 downto 0); + +signal tc:natural; +signal dowrite:std_logic; + +signal fifo_pointer:std_logic_vector(31 downto 0); +signal fifo_data:std_logic_vector(63 downto 0); + + + +begin + + ----------------------------------------------------------------------------- + -- Component Instatiations + ----------------------------------------------------------------------------- + + system_wrapper_i : entity work.system_wrapper + port map ( + ddr_addr => ddr_addr_io, + ddr_ba => ddr_ba_io, + ddr_cas_n => ddr_cas_n_io, + ddr_ck_n => ddr_ck_n_io, + ddr_ck_p => ddr_ck_p_io, + ddr_cke => ddr_cke_io, + ddr_cs_n => ddr_cs_n_io, + ddr_dm => ddr_dm_io, + ddr_dq => ddr_dq_io, + ddr_dqs_n => ddr_dqs_n_io, + ddr_dqs_p => ddr_dqs_p_io, + ddr_odt => ddr_odt_io, + ddr_ras_n => ddr_ras_n_io, + ddr_reset_n => ddr_reset_n_io, + ddr_we_n => ddr_we_n_io, + eth0_clk => eth0_clk_o, + eth0_gmii_rx_clk => eth0_gmii_rx_clk_i, + eth0_gmii_rx_dv => eth0_gmii_rx_dv_i, + eth0_gmii_rxd => eth0_gmii_rxd, + eth0_gmii_tx_clk => eth0_gmii_tx_clk_i, + eth0_gmii_tx_en => eth0_gmii_tx_en_o, + eth0_gmii_txd => eth0_gmii_txd, + eth0_mdio_mdc => eth0_mdio_mdc_o, + eth0_mdio_mdio_io => eth0_mdio_mdio_io, + fixed_io_ddr_vrn => fixed_io_ddr_vrn_io, + fixed_io_ddr_vrp => fixed_io_ddr_vrp_io, + fixed_io_mio => fixed_io_mio_io, + fixed_io_ps_clk => fixed_io_ps_clk_io, + fixed_io_ps_porb => fixed_io_ps_porb_io, + fixed_io_ps_srstb => fixed_io_ps_srstb_io, + emio_i => emio_i, + emio_o => emio_o, + emio_t => emio_t, + + m_axi_gp0_arready => '0', + m_axi_gp0_awready => '0', + m_axi_gp0_bid => (others => '0'), + m_axi_gp0_bresp => (others=>'0'), + m_axi_gp0_bvalid => '0', + m_axi_gp0_rdata => (others =>'0'), + m_axi_gp0_rid => (others => '0'), + m_axi_gp0_rlast => '1', + m_axi_gp0_rresp => (others =>'0'), + m_axi_gp0_rvalid => '0', + m_axi_gp0_wready => '0', + + + s_axi_hp0_aclk => hp0_aclk, + s_axi_hp0_nrst => hp0_nrst, + s_axi_hp0_araddr => hp0_araddr, + s_axi_hp0_arburst => "01", + s_axi_hp0_arcache => "0001", + s_axi_hp0_arid => (others=>'0'), + s_axi_hp0_arlen => "0000", + s_axi_hp0_arlock => "00", + s_axi_hp0_arprot => "000", + s_axi_hp0_arqos => "0000", -- not present in AXI3 which is this + s_axi_hp0_arready => hp0_arready, + s_axi_hp0_arsize =>"011", -- 8 bytes ?? + s_axi_hp0_arvalid =>hp0_arvalid, + s_axi_hp0_awaddr => hp0_awaddr, + s_axi_hp0_awburst => "01", + s_axi_hp0_awcache =>"0001", + s_axi_hp0_awid => (others=>'0'), + s_axi_hp0_awlen => "0000", + s_axi_hp0_awlock => "00", + s_axi_hp0_awprot =>"000", + s_axi_hp0_awqos => "0000", -- not present in AXI3 which this is + s_axi_hp0_awready => hp0_awready, + s_axi_hp0_awsize =>"011", -- 8 bytes? + s_axi_hp0_awvalid => hp0_awvalid, + s_axi_hp0_bid =>open, + s_axi_hp0_bready => hp0_bready, + s_axi_hp0_bresp => open, + s_axi_hp0_bvalid => hp0_bvalid, + s_axi_hp0_rdata => hp0_rdata, + s_axi_hp0_rid => open, + s_axi_hp0_rlast =>open, + s_axi_hp0_rready => hp0_rready, + s_axi_hp0_rresp => open, + s_axi_hp0_rvalid => hp0_rvalid, + s_axi_hp0_wdata => hp0_wdata, + s_axi_hp0_wid => "000000", + s_axi_hp0_wlast =>'1', + s_axi_hp0_wready =>hp0_wready, + s_axi_hp0_wstrb => hp0_wstrb, + s_axi_hp0_wvalid =>hp0_wvalid + ); + + + fifo_to_axi_i : entity work.fifo_to_axi + port map( + aclk => hp0_aclk, + aresetn => hp0_nrst, + axi_awaddr => hp0_awaddr, + axi_awvalid => hp0_awvalid, + axi_awready => hp0_awready, + axi_wdata => hp0_wdata, + axi_wstrb => hp0_wstrb, + axi_wvalid => hp0_wvalid, + axi_wready => hp0_wready, + axi_bvalid => hp0_bvalid, + axi_bready => hp0_bready, + + pointer => fifo_pointer, + fifo_empty =>dowrite, + fifo_rdata=> fifo_data, + fifo_rd_en => open + ); + + + hp0_araddr<=(others=>'0'); + hp0_arvalid <='0'; + hp0_rready <='0'; + + fifo_data <= fifo_pointer & fifo_pointer; + + process (hp0_aclk) begin + if rising_edge(hp0_aclk) then + if tc < 4 then + tc <= tc + 1; + dowrite <= '0'; + else + tc <= 0; + dowrite <='1'; + end if; + end if; + end process; + + + ----------------------------------------------------------------------------- + -- IOs + ----------------------------------------------------------------------------- + + eth0_gmii_txd_o <= eth0_gmii_txd(eth0_gmii_txd_o'range); + eth0_gmii_rxd <= b"0000" & eth0_gmii_rxd_i; + + red_led <= emio_o(0); + green_led <= emio_o(1); + + +end architecture arch; diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl new file mode 100644 index 0000000..fcd6385 --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl @@ -0,0 +1,99 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity fifo_to_axi is + generic ( + ADDR_WIDTH : integer := 32; + START : unsigned(31 downto 0) := x"FFFC0000"; + SIZE : unsigned(31 downto 0) := x"00040000" + ); + port ( + aclk : in std_logic; + aresetn : in std_logic; + + pointer : out std_logic_vector(ADDR_WIDTH-1 downto 0); + + fifo_empty : in std_logic; + fifo_rdata : in std_logic_vector(63 downto 0); + fifo_rd_en : out std_logic; + + axi_awaddr : out std_logic_vector (ADDR_WIDTH-1 downto 0); + axi_awvalid : out std_logic; + axi_awready : in std_logic; + axi_wdata : out std_logic_vector (63 downto 0); + axi_wstrb : out std_logic_vector (7 downto 0); + axi_wvalid : out std_logic; + axi_wready : in std_logic; + axi_bvalid : in std_logic; + axi_bready : out std_logic + ); +end entity fifo_to_axi; + +architecture Behavioral of fifo_to_axi is + + --signal lazy : std_logic_vector(63 downto 0); + signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := std_logic_vector(START); + signal data : std_logic_vector(63 downto 0); + signal do_bus_cycle : std_logic; + +begin + + --lazy <= (ADDR_WIDTH-4 downto 0 => addr(ADDR_WIDTH-1 downto 3), others => '0'); + --pointer <= lazy(pointer'length -1 downto 0); + pointer <= addr; + + + axi_bready <= do_bus_cycle; + axi_wdata <= data; + axi_wstrb <= (others => '1'); + axi_awaddr <= addr; + + --XXX this is moderately budget, it could do with a tonne of pipelining + + process + begin + if rising_edge(aclk) then + if aresetn = '0' then + axi_awvalid <= '0'; + axi_wvalid <= '0'; + do_bus_cycle <= '0'; + fifo_rd_en <= '0'; + addr<= std_logic_vector(START); + elsif do_bus_cycle = '1' then + fifo_rd_en <= '0'; + + if axi_bvalid = '1' then + do_bus_cycle <= '0'; + if addr = std_logic_vector(START+SIZE-to_unsigned(8,ADDR_WIDTH)) then + addr<= std_logic_vector(START); + else + addr <= std_logic_vector(unsigned(addr) +to_unsigned(8,ADDR_WIDTH)); + end if; + axi_awvalid <= '0'; + axi_wvalid <= '0'; + end if; + if axi_awready = '1' then + axi_awvalid <= '0'; + end if; + if axi_wready = '1' then + axi_wvalid <= '0'; + end if; + elsif do_bus_cycle = '0' then + + if fifo_empty = '0' then + data <= fifo_rdata; + fifo_rd_en <= '1'; + do_bus_cycle <= '1'; + axi_awvalid <= '1'; + axi_wvalid <= '1'; + end if; + end if; + + end if; + + end process; + +end Behavioral; + + diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/system_wrapper.vhd b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/system_wrapper.vhd new file mode 100644 index 0000000..1ffaa12 --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/system_wrapper.vhd @@ -0,0 +1,389 @@ +--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------- +--Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022 +--Date : Wed Sep 3 22:49:27 2025 +--Host : new-fish.medaka.james.internal running 64-bit Fedora release 30 (Thirty) +--Command : generate_target system_wrapper.bd +--Design : system_wrapper +--Purpose : IP block netlist +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity system_wrapper is + port ( + ddr_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr_cas_n : inout STD_LOGIC; + ddr_ck_n : inout STD_LOGIC; + ddr_ck_p : inout STD_LOGIC; + ddr_cke : inout STD_LOGIC; + ddr_cs_n : inout STD_LOGIC; + ddr_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + ddr_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + ddr_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + ddr_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + ddr_odt : inout STD_LOGIC; + ddr_ras_n : inout STD_LOGIC; + ddr_reset_n : inout STD_LOGIC; + ddr_we_n : inout STD_LOGIC; + emio_i : in STD_LOGIC_VECTOR ( 63 downto 0 ); + emio_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); + emio_t : out STD_LOGIC_VECTOR ( 63 downto 0 ); + eth0_clk : out STD_LOGIC; + eth0_gmii_rx_clk : in STD_LOGIC; + eth0_gmii_rx_dv : in STD_LOGIC; + eth0_gmii_rxd : in STD_LOGIC_VECTOR ( 7 downto 0 ); + eth0_gmii_tx_clk : in STD_LOGIC; + eth0_gmii_tx_en : out STD_LOGIC_VECTOR ( 0 to 0 ); + eth0_gmii_txd : out STD_LOGIC_VECTOR ( 7 downto 0 ); + eth0_mdio_mdc : out STD_LOGIC; + eth0_mdio_mdio_io : inout STD_LOGIC; + fixed_io_ddr_vrn : inout STD_LOGIC; + fixed_io_ddr_vrp : inout STD_LOGIC; + fixed_io_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + fixed_io_ps_clk : inout STD_LOGIC; + fixed_io_ps_porb : inout STD_LOGIC; + fixed_io_ps_srstb : inout STD_LOGIC; + m_axi_gp0_aclk : out STD_LOGIC; + m_axi_gp0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_gp0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_arready : in STD_LOGIC; + m_axi_gp0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_arvalid : out STD_LOGIC; + m_axi_gp0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_gp0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_awready : in STD_LOGIC; + m_axi_gp0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_awvalid : out STD_LOGIC; + m_axi_gp0_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_bready : out STD_LOGIC; + m_axi_gp0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_bvalid : in STD_LOGIC; + m_axi_gp0_nrst : out STD_LOGIC; + m_axi_gp0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_gp0_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_rlast : in STD_LOGIC; + m_axi_gp0_rready : out STD_LOGIC; + m_axi_gp0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_rvalid : in STD_LOGIC; + m_axi_gp0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_gp0_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_wlast : out STD_LOGIC; + m_axi_gp0_wready : in STD_LOGIC; + m_axi_gp0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_wvalid : out STD_LOGIC; + s_axi_hp0_aclk : out STD_LOGIC; + s_axi_hp0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_hp0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arready : out STD_LOGIC; + s_axi_hp0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_arvalid : in STD_LOGIC; + s_axi_hp0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_hp0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awready : out STD_LOGIC; + s_axi_hp0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awvalid : in STD_LOGIC; + s_axi_hp0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_bready : in STD_LOGIC; + s_axi_hp0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_bvalid : out STD_LOGIC; + s_axi_hp0_nrst : out STD_LOGIC; + s_axi_hp0_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_hp0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_rlast : out STD_LOGIC; + s_axi_hp0_rready : in STD_LOGIC; + s_axi_hp0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_rvalid : out STD_LOGIC; + s_axi_hp0_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_hp0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_wlast : in STD_LOGIC; + s_axi_hp0_wready : out STD_LOGIC; + s_axi_hp0_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ); + s_axi_hp0_wvalid : in STD_LOGIC + ); +end system_wrapper; + +architecture STRUCTURE of system_wrapper is + component system is + port ( + emio_i : in STD_LOGIC_VECTOR ( 63 downto 0 ); + emio_o : out STD_LOGIC_VECTOR ( 63 downto 0 ); + emio_t : out STD_LOGIC_VECTOR ( 63 downto 0 ); + eth0_clk : out STD_LOGIC; + eth0_gmii_rx_clk : in STD_LOGIC; + eth0_gmii_rx_dv : in STD_LOGIC; + eth0_gmii_rxd : in STD_LOGIC_VECTOR ( 7 downto 0 ); + eth0_gmii_tx_clk : in STD_LOGIC; + eth0_gmii_tx_en : out STD_LOGIC_VECTOR ( 0 to 0 ); + eth0_gmii_txd : out STD_LOGIC_VECTOR ( 7 downto 0 ); + m_axi_gp0_aclk : out STD_LOGIC; + m_axi_gp0_nrst : out STD_LOGIC; + s_axi_hp0_aclk : out STD_LOGIC; + s_axi_hp0_nrst : out STD_LOGIC; + ddr_cas_n : inout STD_LOGIC; + ddr_cke : inout STD_LOGIC; + ddr_ck_n : inout STD_LOGIC; + ddr_ck_p : inout STD_LOGIC; + ddr_cs_n : inout STD_LOGIC; + ddr_reset_n : inout STD_LOGIC; + ddr_odt : inout STD_LOGIC; + ddr_ras_n : inout STD_LOGIC; + ddr_we_n : inout STD_LOGIC; + ddr_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + ddr_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + ddr_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + ddr_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + ddr_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + ddr_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + fixed_io_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + fixed_io_ddr_vrn : inout STD_LOGIC; + fixed_io_ddr_vrp : inout STD_LOGIC; + fixed_io_ps_srstb : inout STD_LOGIC; + fixed_io_ps_clk : inout STD_LOGIC; + fixed_io_ps_porb : inout STD_LOGIC; + eth0_mdio_mdc : out STD_LOGIC; + eth0_mdio_mdio_o : out STD_LOGIC; + eth0_mdio_mdio_t : out STD_LOGIC; + eth0_mdio_mdio_i : in STD_LOGIC; + m_axi_gp0_arvalid : out STD_LOGIC; + m_axi_gp0_awvalid : out STD_LOGIC; + m_axi_gp0_bready : out STD_LOGIC; + m_axi_gp0_rready : out STD_LOGIC; + m_axi_gp0_wlast : out STD_LOGIC; + m_axi_gp0_wvalid : out STD_LOGIC; + m_axi_gp0_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); + m_axi_gp0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_gp0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_gp0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axi_gp0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); + m_axi_gp0_arready : in STD_LOGIC; + m_axi_gp0_awready : in STD_LOGIC; + m_axi_gp0_bvalid : in STD_LOGIC; + m_axi_gp0_rlast : in STD_LOGIC; + m_axi_gp0_rvalid : in STD_LOGIC; + m_axi_gp0_wready : in STD_LOGIC; + m_axi_gp0_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); + m_axi_gp0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); + m_axi_gp0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_hp0_arready : out STD_LOGIC; + s_axi_hp0_awready : out STD_LOGIC; + s_axi_hp0_bvalid : out STD_LOGIC; + s_axi_hp0_rlast : out STD_LOGIC; + s_axi_hp0_rvalid : out STD_LOGIC; + s_axi_hp0_wready : out STD_LOGIC; + s_axi_hp0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_hp0_arvalid : in STD_LOGIC; + s_axi_hp0_awvalid : in STD_LOGIC; + s_axi_hp0_bready : in STD_LOGIC; + s_axi_hp0_rready : in STD_LOGIC; + s_axi_hp0_wlast : in STD_LOGIC; + s_axi_hp0_wvalid : in STD_LOGIC; + s_axi_hp0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); + s_axi_hp0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + s_axi_hp0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_hp0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + s_axi_hp0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); + s_axi_hp0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); + s_axi_hp0_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 ); + s_axi_hp0_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 ) + ); + end component system; + component IOBUF is + port ( + I : in STD_LOGIC; + O : out STD_LOGIC; + T : in STD_LOGIC; + IO : inout STD_LOGIC + ); + end component IOBUF; + signal eth0_mdio_mdio_i : STD_LOGIC; + signal eth0_mdio_mdio_o : STD_LOGIC; + signal eth0_mdio_mdio_t : STD_LOGIC; +begin +eth0_mdio_mdio_iobuf: component IOBUF + port map ( + I => eth0_mdio_mdio_o, + IO => eth0_mdio_mdio_io, + O => eth0_mdio_mdio_i, + T => eth0_mdio_mdio_t + ); +system_i: component system + port map ( + ddr_addr(14 downto 0) => ddr_addr(14 downto 0), + ddr_ba(2 downto 0) => ddr_ba(2 downto 0), + ddr_cas_n => ddr_cas_n, + ddr_ck_n => ddr_ck_n, + ddr_ck_p => ddr_ck_p, + ddr_cke => ddr_cke, + ddr_cs_n => ddr_cs_n, + ddr_dm(3 downto 0) => ddr_dm(3 downto 0), + ddr_dq(31 downto 0) => ddr_dq(31 downto 0), + ddr_dqs_n(3 downto 0) => ddr_dqs_n(3 downto 0), + ddr_dqs_p(3 downto 0) => ddr_dqs_p(3 downto 0), + ddr_odt => ddr_odt, + ddr_ras_n => ddr_ras_n, + ddr_reset_n => ddr_reset_n, + ddr_we_n => ddr_we_n, + emio_i(63 downto 0) => emio_i(63 downto 0), + emio_o(63 downto 0) => emio_o(63 downto 0), + emio_t(63 downto 0) => emio_t(63 downto 0), + eth0_clk => eth0_clk, + eth0_gmii_rx_clk => eth0_gmii_rx_clk, + eth0_gmii_rx_dv => eth0_gmii_rx_dv, + eth0_gmii_rxd(7 downto 0) => eth0_gmii_rxd(7 downto 0), + eth0_gmii_tx_clk => eth0_gmii_tx_clk, + eth0_gmii_tx_en(0) => eth0_gmii_tx_en(0), + eth0_gmii_txd(7 downto 0) => eth0_gmii_txd(7 downto 0), + eth0_mdio_mdc => eth0_mdio_mdc, + eth0_mdio_mdio_i => eth0_mdio_mdio_i, + eth0_mdio_mdio_o => eth0_mdio_mdio_o, + eth0_mdio_mdio_t => eth0_mdio_mdio_t, + fixed_io_ddr_vrn => fixed_io_ddr_vrn, + fixed_io_ddr_vrp => fixed_io_ddr_vrp, + fixed_io_mio(53 downto 0) => fixed_io_mio(53 downto 0), + fixed_io_ps_clk => fixed_io_ps_clk, + fixed_io_ps_porb => fixed_io_ps_porb, + fixed_io_ps_srstb => fixed_io_ps_srstb, + m_axi_gp0_aclk => m_axi_gp0_aclk, + m_axi_gp0_araddr(31 downto 0) => m_axi_gp0_araddr(31 downto 0), + m_axi_gp0_arburst(1 downto 0) => m_axi_gp0_arburst(1 downto 0), + m_axi_gp0_arcache(3 downto 0) => m_axi_gp0_arcache(3 downto 0), + m_axi_gp0_arid(11 downto 0) => m_axi_gp0_arid(11 downto 0), + m_axi_gp0_arlen(3 downto 0) => m_axi_gp0_arlen(3 downto 0), + m_axi_gp0_arlock(1 downto 0) => m_axi_gp0_arlock(1 downto 0), + m_axi_gp0_arprot(2 downto 0) => m_axi_gp0_arprot(2 downto 0), + m_axi_gp0_arqos(3 downto 0) => m_axi_gp0_arqos(3 downto 0), + m_axi_gp0_arready => m_axi_gp0_arready, + m_axi_gp0_arsize(2 downto 0) => m_axi_gp0_arsize(2 downto 0), + m_axi_gp0_arvalid => m_axi_gp0_arvalid, + m_axi_gp0_awaddr(31 downto 0) => m_axi_gp0_awaddr(31 downto 0), + m_axi_gp0_awburst(1 downto 0) => m_axi_gp0_awburst(1 downto 0), + m_axi_gp0_awcache(3 downto 0) => m_axi_gp0_awcache(3 downto 0), + m_axi_gp0_awid(11 downto 0) => m_axi_gp0_awid(11 downto 0), + m_axi_gp0_awlen(3 downto 0) => m_axi_gp0_awlen(3 downto 0), + m_axi_gp0_awlock(1 downto 0) => m_axi_gp0_awlock(1 downto 0), + m_axi_gp0_awprot(2 downto 0) => m_axi_gp0_awprot(2 downto 0), + m_axi_gp0_awqos(3 downto 0) => m_axi_gp0_awqos(3 downto 0), + m_axi_gp0_awready => m_axi_gp0_awready, + m_axi_gp0_awsize(2 downto 0) => m_axi_gp0_awsize(2 downto 0), + m_axi_gp0_awvalid => m_axi_gp0_awvalid, + m_axi_gp0_bid(11 downto 0) => m_axi_gp0_bid(11 downto 0), + m_axi_gp0_bready => m_axi_gp0_bready, + m_axi_gp0_bresp(1 downto 0) => m_axi_gp0_bresp(1 downto 0), + m_axi_gp0_bvalid => m_axi_gp0_bvalid, + m_axi_gp0_nrst => m_axi_gp0_nrst, + m_axi_gp0_rdata(31 downto 0) => m_axi_gp0_rdata(31 downto 0), + m_axi_gp0_rid(11 downto 0) => m_axi_gp0_rid(11 downto 0), + m_axi_gp0_rlast => m_axi_gp0_rlast, + m_axi_gp0_rready => m_axi_gp0_rready, + m_axi_gp0_rresp(1 downto 0) => m_axi_gp0_rresp(1 downto 0), + m_axi_gp0_rvalid => m_axi_gp0_rvalid, + m_axi_gp0_wdata(31 downto 0) => m_axi_gp0_wdata(31 downto 0), + m_axi_gp0_wid(11 downto 0) => m_axi_gp0_wid(11 downto 0), + m_axi_gp0_wlast => m_axi_gp0_wlast, + m_axi_gp0_wready => m_axi_gp0_wready, + m_axi_gp0_wstrb(3 downto 0) => m_axi_gp0_wstrb(3 downto 0), + m_axi_gp0_wvalid => m_axi_gp0_wvalid, + s_axi_hp0_aclk => s_axi_hp0_aclk, + s_axi_hp0_araddr(31 downto 0) => s_axi_hp0_araddr(31 downto 0), + s_axi_hp0_arburst(1 downto 0) => s_axi_hp0_arburst(1 downto 0), + s_axi_hp0_arcache(3 downto 0) => s_axi_hp0_arcache(3 downto 0), + s_axi_hp0_arid(5 downto 0) => s_axi_hp0_arid(5 downto 0), + s_axi_hp0_arlen(3 downto 0) => s_axi_hp0_arlen(3 downto 0), + s_axi_hp0_arlock(1 downto 0) => s_axi_hp0_arlock(1 downto 0), + s_axi_hp0_arprot(2 downto 0) => s_axi_hp0_arprot(2 downto 0), + s_axi_hp0_arqos(3 downto 0) => s_axi_hp0_arqos(3 downto 0), + s_axi_hp0_arready => s_axi_hp0_arready, + s_axi_hp0_arsize(2 downto 0) => s_axi_hp0_arsize(2 downto 0), + s_axi_hp0_arvalid => s_axi_hp0_arvalid, + s_axi_hp0_awaddr(31 downto 0) => s_axi_hp0_awaddr(31 downto 0), + s_axi_hp0_awburst(1 downto 0) => s_axi_hp0_awburst(1 downto 0), + s_axi_hp0_awcache(3 downto 0) => s_axi_hp0_awcache(3 downto 0), + s_axi_hp0_awid(5 downto 0) => s_axi_hp0_awid(5 downto 0), + s_axi_hp0_awlen(3 downto 0) => s_axi_hp0_awlen(3 downto 0), + s_axi_hp0_awlock(1 downto 0) => s_axi_hp0_awlock(1 downto 0), + s_axi_hp0_awprot(2 downto 0) => s_axi_hp0_awprot(2 downto 0), + s_axi_hp0_awqos(3 downto 0) => s_axi_hp0_awqos(3 downto 0), + s_axi_hp0_awready => s_axi_hp0_awready, + s_axi_hp0_awsize(2 downto 0) => s_axi_hp0_awsize(2 downto 0), + s_axi_hp0_awvalid => s_axi_hp0_awvalid, + s_axi_hp0_bid(5 downto 0) => s_axi_hp0_bid(5 downto 0), + s_axi_hp0_bready => s_axi_hp0_bready, + s_axi_hp0_bresp(1 downto 0) => s_axi_hp0_bresp(1 downto 0), + s_axi_hp0_bvalid => s_axi_hp0_bvalid, + s_axi_hp0_nrst => s_axi_hp0_nrst, + s_axi_hp0_rdata(63 downto 0) => s_axi_hp0_rdata(63 downto 0), + s_axi_hp0_rid(5 downto 0) => s_axi_hp0_rid(5 downto 0), + s_axi_hp0_rlast => s_axi_hp0_rlast, + s_axi_hp0_rready => s_axi_hp0_rready, + s_axi_hp0_rresp(1 downto 0) => s_axi_hp0_rresp(1 downto 0), + s_axi_hp0_rvalid => s_axi_hp0_rvalid, + s_axi_hp0_wdata(63 downto 0) => s_axi_hp0_wdata(63 downto 0), + s_axi_hp0_wid(5 downto 0) => s_axi_hp0_wid(5 downto 0), + s_axi_hp0_wlast => s_axi_hp0_wlast, + s_axi_hp0_wready => s_axi_hp0_wready, + s_axi_hp0_wstrb(7 downto 0) => s_axi_hp0_wstrb(7 downto 0), + s_axi_hp0_wvalid => s_axi_hp0_wvalid + ); +end STRUCTURE; diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl new file mode 100644 index 0000000..8c94f99 --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl @@ -0,0 +1,693 @@ + +################################################################ +# This is a generated script based on design: system +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2022.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source system_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z010clg400-1 +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name system + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:processing_system7:5.5\ +" + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr ] + + set eth0_mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth0_mdio ] + + set fixed_io [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io ] + + set m_axi_gp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_gp0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.PROTOCOL {AXI3} \ + ] $m_axi_gp0 + + set s_axi_hp0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_hp0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {6} \ + CONFIG.MAX_BURST_LENGTH {16} \ + CONFIG.NUM_READ_OUTSTANDING {8} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {8} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI3} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axi_hp0 + + + # Create ports + set emio_i [ create_bd_port -dir I -from 63 -to 0 emio_i ] + set emio_o [ create_bd_port -dir O -from 63 -to 0 emio_o ] + set emio_t [ create_bd_port -dir O -from 63 -to 0 emio_t ] + set eth0_clk [ create_bd_port -dir O -type clk eth0_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {25000000} \ + ] $eth0_clk + set eth0_gmii_rx_clk [ create_bd_port -dir I -type clk eth0_gmii_rx_clk ] + set eth0_gmii_rx_dv [ create_bd_port -dir I eth0_gmii_rx_dv ] + set eth0_gmii_rxd [ create_bd_port -dir I -from 7 -to 0 eth0_gmii_rxd ] + set eth0_gmii_tx_clk [ create_bd_port -dir I -type clk eth0_gmii_tx_clk ] + set eth0_gmii_tx_en [ create_bd_port -dir O -from 0 -to 0 eth0_gmii_tx_en ] + set eth0_gmii_txd [ create_bd_port -dir O -from 7 -to 0 eth0_gmii_txd ] + set m_axi_gp0_aclk [ create_bd_port -dir O -type clk m_axi_gp0_aclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axi_gp0} \ + CONFIG.ASSOCIATED_PORT {} \ + CONFIG.ASSOCIATED_RESET {m_axi_gp0_nrst} \ + ] $m_axi_gp0_aclk + set m_axi_gp0_nrst [ create_bd_port -dir O -type rst m_axi_gp0_nrst ] + set s_axi_hp0_aclk [ create_bd_port -dir O -type clk s_axi_hp0_aclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {s_axi_hp0} \ + CONFIG.ASSOCIATED_RESET {s_axi_hp0_nrst} \ + ] $s_axi_hp0_aclk + set s_axi_hp0_nrst [ create_bd_port -dir O -type rst s_axi_hp0_nrst ] + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {25.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {25.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {250.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {20.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CLK0_FREQ {25000000} \ + CONFIG.PCW_CLK1_FREQ {250000000} \ + CONFIG.PCW_CLK2_FREQ {100000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x0FFFFFFF} \ + CONFIG.PCW_ENET0_ENET0_IO {EMIO} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {EMIO} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {1} \ + CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_EN_CLK0_PORT {1} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ + CONFIG.PCW_EN_CLK2_PORT {1} \ + CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_ENET0 {1} \ + CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_I2C0 {0} \ + CONFIG.PCW_EN_ENET0 {1} \ + CONFIG.PCW_EN_GPIO {1} \ + CONFIG.PCW_EN_I2C0 {1} \ + CONFIG.PCW_EN_RST1_PORT {1} \ + CONFIG.PCW_EN_RST2_PORT {1} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SMC {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {8} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {25} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {250} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \ + CONFIG.PCW_I2C0_I2C0_IO {MIO 26 .. 27} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_I2C_RESET_ENABLE {1} \ + CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ + CONFIG.PCW_MIO_0_DIRECTION {out} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_10_DIRECTION {inout} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_10_PULLUP {enabled} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_DIRECTION {inout} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_11_PULLUP {enabled} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_DIRECTION {inout} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_12_PULLUP {enabled} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_DIRECTION {inout} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_13_PULLUP {enabled} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_14_DIRECTION {in} \ + CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_14_PULLUP {enabled} \ + CONFIG.PCW_MIO_14_SLEW {slow} \ + CONFIG.PCW_MIO_15_DIRECTION {inout} \ + CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_15_PULLUP {enabled} \ + CONFIG.PCW_MIO_15_SLEW {slow} \ + CONFIG.PCW_MIO_16_DIRECTION {inout} \ + CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_16_PULLUP {enabled} \ + CONFIG.PCW_MIO_16_SLEW {slow} \ + CONFIG.PCW_MIO_17_DIRECTION {inout} \ + CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_17_PULLUP {enabled} \ + CONFIG.PCW_MIO_17_SLEW {slow} \ + CONFIG.PCW_MIO_18_DIRECTION {inout} \ + CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_18_PULLUP {enabled} \ + CONFIG.PCW_MIO_18_SLEW {slow} \ + CONFIG.PCW_MIO_19_DIRECTION {inout} \ + CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_19_PULLUP {enabled} \ + CONFIG.PCW_MIO_19_SLEW {slow} \ + CONFIG.PCW_MIO_1_DIRECTION {inout} \ + CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_1_PULLUP {enabled} \ + CONFIG.PCW_MIO_1_SLEW {slow} \ + CONFIG.PCW_MIO_20_DIRECTION {inout} \ + CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_20_PULLUP {enabled} \ + CONFIG.PCW_MIO_20_SLEW {slow} \ + CONFIG.PCW_MIO_21_DIRECTION {inout} \ + CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_21_PULLUP {enabled} \ + CONFIG.PCW_MIO_21_SLEW {slow} \ + CONFIG.PCW_MIO_22_DIRECTION {inout} \ + CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_22_PULLUP {enabled} \ + CONFIG.PCW_MIO_22_SLEW {slow} \ + CONFIG.PCW_MIO_23_DIRECTION {inout} \ + CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_23_PULLUP {enabled} \ + CONFIG.PCW_MIO_23_SLEW {slow} \ + CONFIG.PCW_MIO_24_DIRECTION {out} \ + CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_24_PULLUP {enabled} \ + CONFIG.PCW_MIO_24_SLEW {slow} \ + CONFIG.PCW_MIO_25_DIRECTION {in} \ + CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_25_PULLUP {enabled} \ + CONFIG.PCW_MIO_25_SLEW {slow} \ + CONFIG.PCW_MIO_26_DIRECTION {inout} \ + CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_26_PULLUP {enabled} \ + CONFIG.PCW_MIO_26_SLEW {slow} \ + CONFIG.PCW_MIO_27_DIRECTION {inout} \ + CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_27_PULLUP {enabled} \ + CONFIG.PCW_MIO_27_SLEW {slow} \ + CONFIG.PCW_MIO_28_DIRECTION {inout} \ + CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_28_PULLUP {enabled} \ + CONFIG.PCW_MIO_28_SLEW {slow} \ + CONFIG.PCW_MIO_29_DIRECTION {inout} \ + CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_29_PULLUP {enabled} \ + CONFIG.PCW_MIO_29_SLEW {slow} \ + CONFIG.PCW_MIO_2_DIRECTION {out} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_30_DIRECTION {inout} \ + CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_30_PULLUP {enabled} \ + CONFIG.PCW_MIO_30_SLEW {slow} \ + CONFIG.PCW_MIO_31_DIRECTION {inout} \ + CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_31_PULLUP {enabled} \ + CONFIG.PCW_MIO_31_SLEW {slow} \ + CONFIG.PCW_MIO_32_DIRECTION {inout} \ + CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_32_PULLUP {enabled} \ + CONFIG.PCW_MIO_32_SLEW {slow} \ + CONFIG.PCW_MIO_33_DIRECTION {inout} \ + CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_33_PULLUP {enabled} \ + CONFIG.PCW_MIO_33_SLEW {slow} \ + CONFIG.PCW_MIO_34_DIRECTION {in} \ + CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_34_PULLUP {enabled} \ + CONFIG.PCW_MIO_34_SLEW {slow} \ + CONFIG.PCW_MIO_35_DIRECTION {inout} \ + CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_35_PULLUP {enabled} \ + CONFIG.PCW_MIO_35_SLEW {slow} \ + CONFIG.PCW_MIO_36_DIRECTION {inout} \ + CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_36_PULLUP {enabled} \ + CONFIG.PCW_MIO_36_SLEW {slow} \ + CONFIG.PCW_MIO_37_DIRECTION {inout} \ + CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_37_PULLUP {enabled} \ + CONFIG.PCW_MIO_37_SLEW {slow} \ + CONFIG.PCW_MIO_38_DIRECTION {inout} \ + CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_38_PULLUP {enabled} \ + CONFIG.PCW_MIO_38_SLEW {slow} \ + CONFIG.PCW_MIO_39_DIRECTION {inout} \ + CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_39_PULLUP {enabled} \ + CONFIG.PCW_MIO_39_SLEW {slow} \ + CONFIG.PCW_MIO_3_DIRECTION {out} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_40_DIRECTION {inout} \ + CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_40_PULLUP {enabled} \ + CONFIG.PCW_MIO_40_SLEW {slow} \ + CONFIG.PCW_MIO_41_DIRECTION {inout} \ + CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_41_PULLUP {enabled} \ + CONFIG.PCW_MIO_41_SLEW {slow} \ + CONFIG.PCW_MIO_42_DIRECTION {inout} \ + CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_42_PULLUP {enabled} \ + CONFIG.PCW_MIO_42_SLEW {slow} \ + CONFIG.PCW_MIO_43_DIRECTION {inout} \ + CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_43_PULLUP {enabled} \ + CONFIG.PCW_MIO_43_SLEW {slow} \ + CONFIG.PCW_MIO_44_DIRECTION {inout} \ + CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_44_PULLUP {enabled} \ + CONFIG.PCW_MIO_44_SLEW {slow} \ + CONFIG.PCW_MIO_45_DIRECTION {inout} \ + CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_45_PULLUP {enabled} \ + CONFIG.PCW_MIO_45_SLEW {slow} \ + CONFIG.PCW_MIO_46_DIRECTION {inout} \ + CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_46_PULLUP {enabled} \ + CONFIG.PCW_MIO_46_SLEW {slow} \ + CONFIG.PCW_MIO_47_DIRECTION {inout} \ + CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_47_PULLUP {enabled} \ + CONFIG.PCW_MIO_47_SLEW {slow} \ + CONFIG.PCW_MIO_48_DIRECTION {inout} \ + CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_48_PULLUP {enabled} \ + CONFIG.PCW_MIO_48_SLEW {slow} \ + CONFIG.PCW_MIO_49_DIRECTION {inout} \ + CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_49_PULLUP {enabled} \ + CONFIG.PCW_MIO_49_SLEW {slow} \ + CONFIG.PCW_MIO_4_DIRECTION {inout} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_50_DIRECTION {inout} \ + CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_50_PULLUP {enabled} \ + CONFIG.PCW_MIO_50_SLEW {slow} \ + CONFIG.PCW_MIO_51_DIRECTION {inout} \ + CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_51_PULLUP {enabled} \ + CONFIG.PCW_MIO_51_SLEW {slow} \ + CONFIG.PCW_MIO_52_DIRECTION {inout} \ + CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_52_PULLUP {enabled} \ + CONFIG.PCW_MIO_52_SLEW {slow} \ + CONFIG.PCW_MIO_53_DIRECTION {inout} \ + CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_53_PULLUP {enabled} \ + CONFIG.PCW_MIO_53_SLEW {slow} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_DIRECTION {inout} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_7_DIRECTION {out} \ + CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_7_PULLUP {disabled} \ + CONFIG.PCW_MIO_7_SLEW {slow} \ + CONFIG.PCW_MIO_8_DIRECTION {out} \ + CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_8_PULLUP {disabled} \ + CONFIG.PCW_MIO_8_SLEW {slow} \ + CONFIG.PCW_MIO_9_DIRECTION {inout} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {NAND Flash#GPIO#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 1#UART 1#I2C 0#I2C 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO} \ + CONFIG.PCW_MIO_TREE_SIGNALS {cs#gpio[1]#ale#we_b#data[2]#data[0]#data[1]#cle#re_b#data[4]#data[5]#data[6]#data[7]#data[3]#busy#gpio[15]#gpio[16]#gpio[17]#gpio[18]#gpio[19]#gpio[20]#gpio[21]#gpio[22]#gpio[23]#tx#rx#scl#sda#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#cd#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#gpio[50]#gpio[51]#gpio[52]#gpio[53]} \ + CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ + CONFIG.PCW_NAND_NAND_IO {MIO 0 2.. 14} \ + CONFIG.PCW_NAND_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ + CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ + CONFIG.PCW_SD0_GRP_CD_IO {MIO 34} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {50} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {20} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_SMC_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 24 .. 25} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 HA-15E} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {45.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_USB0_RESET_ENABLE {0} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USE_EXPANDED_IOP {0} \ + CONFIG.PCW_USE_HIGH_OCM {1} \ + CONFIG.PCW_USE_M_AXI_GP0 {1} \ + CONFIG.PCW_USE_S_AXI_HP0 {1} \ + ] $processing_system7_0 + + # Create interface connections + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports ddr] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports fixed_io] [get_bd_intf_pins processing_system7_0/FIXED_IO] + connect_bd_intf_net -intf_net processing_system7_0_MDIO_ETHERNET_0 [get_bd_intf_ports eth0_mdio] [get_bd_intf_pins processing_system7_0/MDIO_ETHERNET_0] + connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_ports m_axi_gp0] [get_bd_intf_pins processing_system7_0/M_AXI_GP0] + connect_bd_intf_net -intf_net s_axi_hp0_1 [get_bd_intf_ports s_axi_hp0] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] + + # Create port connections + connect_bd_net -net ENET0_GMII_RXD_0_1 [get_bd_ports eth0_gmii_rxd] [get_bd_pins processing_system7_0/ENET0_GMII_RXD] + connect_bd_net -net ENET0_GMII_RX_CLK_0_1 [get_bd_ports eth0_gmii_rx_clk] [get_bd_pins processing_system7_0/ENET0_GMII_RX_CLK] + connect_bd_net -net ENET0_GMII_RX_DV_0_1 [get_bd_ports eth0_gmii_rx_dv] [get_bd_pins processing_system7_0/ENET0_GMII_RX_DV] + connect_bd_net -net ENET0_GMII_TX_CLK_0_1 [get_bd_ports eth0_gmii_tx_clk] [get_bd_pins processing_system7_0/ENET0_GMII_TX_CLK] + connect_bd_net -net GPIO_I_0_1 [get_bd_ports emio_i] [get_bd_pins processing_system7_0/GPIO_I] + connect_bd_net -net processing_system7_0_ENET0_GMII_TXD [get_bd_ports eth0_gmii_txd] [get_bd_pins processing_system7_0/ENET0_GMII_TXD] + connect_bd_net -net processing_system7_0_ENET0_GMII_TX_EN [get_bd_ports eth0_gmii_tx_en] [get_bd_pins processing_system7_0/ENET0_GMII_TX_EN] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports eth0_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports m_axi_gp0_aclk] [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_ports s_axi_hp0_aclk] [get_bd_pins processing_system7_0/FCLK_CLK2] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] + connect_bd_net -net processing_system7_0_FCLK_RESET1_N [get_bd_ports m_axi_gp0_nrst] [get_bd_pins processing_system7_0/FCLK_RESET1_N] + connect_bd_net -net processing_system7_0_FCLK_RESET2_N [get_bd_ports s_axi_hp0_nrst] [get_bd_pins processing_system7_0/FCLK_RESET2_N] + connect_bd_net -net processing_system7_0_GPIO_O [get_bd_ports emio_o] [get_bd_pins processing_system7_0/GPIO_O] + connect_bd_net -net processing_system7_0_GPIO_T [get_bd_ports emio_t] [get_bd_pins processing_system7_0/GPIO_T] + + # Create address segments + assign_bd_address -offset 0x43C00000 -range 0x00100000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_gp0/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/bitstream.xdc b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/bitstream.xdc new file mode 100644 index 0000000..8350dc3 --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/bitstream.xdc @@ -0,0 +1,31 @@ +# ------------------------------------------------------------------------------ +# Copyright (C) 2020 - embed-me +# +# Lukas Lichtl +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License v2 as published by +# the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# ------------------------------------------------------------------------------ +# Function description: +# +# ------------------------------------------------------------------------------ + + +# --------------------------------------------------------- +# Bitstream configuration (UG908) +# --------------------------------------------------------- + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] +set_property BITSTREAM.CONFIG.USERID 32'hf00dbabe [current_design] diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/general.xdc b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/general.xdc new file mode 100644 index 0000000..e644867 --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/general.xdc @@ -0,0 +1,29 @@ +# ------------------------------------------------------------------------------ +# Copyright (C) 2020 - embed-me +# +# Lukas Lichtl +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License v2 as published by +# the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# ------------------------------------------------------------------------------ +# Function description: +# +# ------------------------------------------------------------------------------ + + +# --------------------------------------------------------- +# Bank 0 Configuration (UG912) +# --------------------------------------------------------- + +set_property CONFIG_VOLTAGE {3.3} [current_design] +set_property CFGBVS VCCO [current_design] diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/pinout.xdc b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/pinout.xdc new file mode 100644 index 0000000..161f0bf --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/xdc/pinout.xdc @@ -0,0 +1,54 @@ +# ------------------------------------------------------------------------------ +# Copyright (C) 2020 - embed-me +# +# Lukas Lichtl +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License v2 as published by +# the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# +# ------------------------------------------------------------------------------ +# Function description: +# +# ------------------------------------------------------------------------------ + + +# --------------------------------------------------------- +# Ethernet 0 +# --------------------------------------------------------- + +set_property PACKAGE_PIN U18 [get_ports {eth0_clk_o}] +set_property PACKAGE_PIN U14 [get_ports {eth0_gmii_rx_clk_i}] +set_property PACKAGE_PIN U15 [get_ports {eth0_gmii_tx_clk_i}] +set_property PACKAGE_PIN W19 [get_ports {eth0_gmii_tx_en_o[0]}] +set_property PACKAGE_PIN W18 [get_ports {eth0_gmii_txd_o[0]}] +set_property PACKAGE_PIN Y18 [get_ports {eth0_gmii_txd_o[1]}] +set_property PACKAGE_PIN V18 [get_ports {eth0_gmii_txd_o[2]}] +set_property PACKAGE_PIN Y19 [get_ports {eth0_gmii_txd_o[3]}] +set_property PACKAGE_PIN W16 [get_ports {eth0_gmii_rx_dv_i}] +set_property PACKAGE_PIN W15 [get_ports {eth0_mdio_mdc_o}] +set_property PACKAGE_PIN Y14 [get_ports {eth0_mdio_mdio_io}] +set_property PACKAGE_PIN Y16 [get_ports {eth0_gmii_rxd_i[0]}] +set_property PACKAGE_PIN V16 [get_ports {eth0_gmii_rxd_i[1]}] +set_property PACKAGE_PIN V17 [get_ports {eth0_gmii_rxd_i[2]}] +set_property PACKAGE_PIN Y17 [get_ports {eth0_gmii_rxd_i[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports eth0_*] + + +# --------------------------------------------------------- +# LEDs +# --------------------------------------------------------- + +set_property PACKAGE_PIN W13 [get_ports {green_led}] +set_property PACKAGE_PIN W14 [get_ports {red_led}] + +set_property IOSTANDARD LVCMOS33 [get_ports *_led] -- cgit v1.2.3