From a26678ba457c91b54f90a4a8588a2572fa6417c3 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 4 Sep 2025 18:20:23 +0100 Subject: ebaz4205 working with generic build system --- fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py | 3 ++- .../ebaz4205_fpga/src/hdl/ebaz4205_top.vhd | 8 ++++++- .../ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl | 17 ++++++++++++-- .../ebaz4205_fpga/src/hdl/synchronizer.vhdl | 26 ++++++++++++++++++++++ .../ebaz4205_fpga/src/xilinx/bd/system.tcl | 1 + 5 files changed, 51 insertions(+), 4 deletions(-) create mode 100644 fpga/ebaz4205/ebaz4205_fpga/src/hdl/synchronizer.vhdl (limited to 'fpga/ebaz4205/ebaz4205_fpga/src') diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py index c25a02e..7eed044 100644 --- a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/Manifest.py @@ -1,6 +1,7 @@ files = [ "ebaz4205_top.vhd", "system_wrapper.vhd", - "fifo_to_axi.vhdl" + "fifo_to_axi.vhdl", + "synchronizer.vhdl" ] diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd index 3f97d97..fbc5b90 100644 --- a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/ebaz4205_top.vhd @@ -103,6 +103,8 @@ signal dowrite:std_logic; signal fifo_pointer:std_logic_vector(31 downto 0); signal fifo_data:std_logic_vector(63 downto 0); +signal run:std_logic; + begin @@ -218,6 +220,8 @@ begin axi_bready => hp0_bready, pointer => fifo_pointer, + run => run, + fifo_empty =>dowrite, fifo_rdata=> fifo_data, fifo_rd_en => open @@ -250,8 +254,10 @@ begin eth0_gmii_txd_o <= eth0_gmii_txd(eth0_gmii_txd_o'range); eth0_gmii_rxd <= b"0000" & eth0_gmii_rxd_i; - red_led <= emio_o(0); + --red_led <= emio_o(0); green_led <= emio_o(1); + run <= emio_o(2); + red_led <= emio_o(2); end architecture arch; diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl index fcd6385..6129f50 100644 --- a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/fifo_to_axi.vhdl @@ -12,6 +12,8 @@ entity fifo_to_axi is aclk : in std_logic; aresetn : in std_logic; + run: in std_logic; + pointer : out std_logic_vector(ADDR_WIDTH-1 downto 0); fifo_empty : in std_logic; @@ -36,9 +38,20 @@ architecture Behavioral of fifo_to_axi is signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := std_logic_vector(START); signal data : std_logic_vector(63 downto 0); signal do_bus_cycle : std_logic; + signal s_run : std_logic; begin + + run_sync : entity work.synchronizer + generic map(stages => 2) + port map ( + clk => aclk, + i => run, + o => s_run + ); + + --lazy <= (ADDR_WIDTH-4 downto 0 => addr(ADDR_WIDTH-1 downto 3), others => '0'); --pointer <= lazy(pointer'length -1 downto 0); pointer <= addr; @@ -51,7 +64,7 @@ begin --XXX this is moderately budget, it could do with a tonne of pipelining - process + process (aclk) begin if rising_edge(aclk) then if aresetn = '0' then @@ -60,7 +73,7 @@ begin do_bus_cycle <= '0'; fifo_rd_en <= '0'; addr<= std_logic_vector(START); - elsif do_bus_cycle = '1' then + elsif run='1' and do_bus_cycle = '1' then fifo_rd_en <= '0'; if axi_bvalid = '1' then diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/hdl/synchronizer.vhdl b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/synchronizer.vhdl new file mode 100644 index 0000000..302cef9 --- /dev/null +++ b/fpga/ebaz4205/ebaz4205_fpga/src/hdl/synchronizer.vhdl @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity synchronizer is + generic (stages : natural := 2); + port (clk : in std_logic; + i : in std_logic; + o : out std_logic); +end synchronizer; + +architecture Behavioral of synchronizer is + signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0'); + attribute ASYNC_REG : string; + attribute ASYNC_REG of flipflops : signal is "true"; +begin + + o <= flipflops(flipflops'high); + + clk_proc : process(clk, flipflops, i) + begin + if rising_edge(clk) then + flipflops <= flipflops(flipflops'high-1 downto 0) & i; + end if; + end process; + +end Behavioral; diff --git a/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl index 8c94f99..8ecaec4 100644 --- a/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl +++ b/fpga/ebaz4205/ebaz4205_fpga/src/xilinx/bd/system.tcl @@ -673,6 +673,7 @@ proc create_root_design { parentCell } { # Create address segments assign_bd_address -offset 0x43C00000 -range 0x00100000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs m_axi_gp0/Reg] -force assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force + assign_bd_address -offset 0xFFFC0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_HIGH_OCM] -force # Restore current instance -- cgit v1.2.3