From 788356527b3a27f3f690415b01a1c7f256ef97d0 Mon Sep 17 00:00:00 2001 From: James McKenzie Date: Mon, 28 Apr 2025 11:38:06 +0100 Subject: move vram to module --- spartan6/hp_lcd_driver/Makefile.spartan6 | 4 +- spartan6/hp_lcd_driver/serdes_n_to_1.vhdl | 118 --------------------- spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl | 118 +++++++++++++++++++++ spartan6/hp_lcd_driver/tmds_phy.vhdl | 67 ------------ spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl | 67 ++++++++++++ spartan6/hp_lcd_driver/vram.xco | 108 ------------------- spartan6/hp_lcd_driver/vram_spartan6.vhdl | 36 +++++++ spartan6/hp_lcd_driver/vram_spartan6_impl.xco | 108 +++++++++++++++++++ 8 files changed, 331 insertions(+), 295 deletions(-) delete mode 100644 spartan6/hp_lcd_driver/serdes_n_to_1.vhdl create mode 100644 spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl delete mode 100644 spartan6/hp_lcd_driver/tmds_phy.vhdl create mode 100644 spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl delete mode 100644 spartan6/hp_lcd_driver/vram.xco create mode 100644 spartan6/hp_lcd_driver/vram_spartan6.vhdl create mode 100644 spartan6/hp_lcd_driver/vram_spartan6_impl.xco diff --git a/spartan6/hp_lcd_driver/Makefile.spartan6 b/spartan6/hp_lcd_driver/Makefile.spartan6 index 83a389e..0d0f90e 100644 --- a/spartan6/hp_lcd_driver/Makefile.spartan6 +++ b/spartan6/hp_lcd_driver/Makefile.spartan6 @@ -5,10 +5,10 @@ export XILINXD_LICENSE_FILE PART=xc6slx9-2-tqg144 TOP=hp_lcd_driver BUILD=build_spartan6 -VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1.vhdl tmds_encoder.vhdl tmds_phy.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl +VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl serdes_n_to_1_spartan6.vhdl tmds_encoder.vhdl tmds_phy_spartan6.vhdl tmds_encode.vhdl tmds_output_spartan6.vhdl vram_spartan6.vhdl output_stage.vhdl clkgen_spartan6.vhdl hp_lcd_driver.vhdl UCF=hp_lcd_driver.ucf UT=hp_lcd_driver.ut -IPSRCS=vram.xco +IPSRCS=vram_spartan6_impl.xco DESIGN_NAME=${TOP} DS_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS ISE_HOME=${DS_HOME}/ISE diff --git a/spartan6/hp_lcd_driver/serdes_n_to_1.vhdl b/spartan6/hp_lcd_driver/serdes_n_to_1.vhdl deleted file mode 100644 index dec3c9a..0000000 --- a/spartan6/hp_lcd_driver/serdes_n_to_1.vhdl +++ /dev/null @@ -1,118 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - -library UNISIM; -use UNISIM.vcomponents.all; - - -entity serdes_n_to_1 is - generic ( - SF : natural := 8 - ); - port ( - - ioclk : in std_logic; - serdesstrobe : in std_logic; - reset : in std_logic; - gclk : in std_logic; - datain : in std_logic_vector(SF-1 downto 0); - iob_data_out : out std_logic - ); -end serdes_n_to_1; - - -architecture beh of serdes_n_to_1 is - - signal cascade_di : std_logic; - signal cascade_do : std_logic; - signal cascade_ti : std_logic; - signal cascade_to : std_logic; - signal mdatain : std_logic_vector(8 downto 0); - -begin - - datain_for_1 : for b in 0 to SF -1 generate - mdatain(b) <= datain(b); - end generate; - - datain_for_2 : for b in SF to 8 generate - mdatain(b) <= '0'; - end generate; - --- mdatain <= ( SF-1 downto 0 => datain, others =>'0'); - - oserdes_m : OSERDES2 - generic map ( - DATA_WIDTH => SF, - DATA_RATE_OQ => "SDR", - DATA_RATE_OT => "SDR", - SERDES_MODE => "MASTER", - OUTPUT_MODE => "DIFFERENTIAL" - ) - port map ( - OQ => iob_data_out, - OCE => '1', - CLK0 => ioclk, - CLK1 => '0', - IOCE => serdesstrobe, - RST => reset, - CLKDIV => gclk, - D4 => mdatain(7), - D3 => mdatain(6), - D2 => mdatain(5), - D1 => mdatain(4), --- TQ => , - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TRAIN => '0', - TCE => '1', - SHIFTIN1 => '1', -- Dummy input in Master - SHIFTIN2 => '1', -- Dummy input in Master - SHIFTIN3 => cascade_do, -- Cascade output D data from slave - SHIFTIN4 => cascade_to, -- Cascade output T data from slave - SHIFTOUT1 => cascade_di, -- Cascade input D data to slave - SHIFTOUT2 => cascade_ti -- Cascade input T data to slave --- SHIFTOUT3 => , -- Dummy output in Master --- SHIFTOUT4 => -- Dummy output in Master - ); - - oserdes_s : OSERDES2 - generic map ( - DATA_WIDTH => SF, -- SERDES word width. This should match the setting is BUFPLL - DATA_RATE_OQ => "SDR", -- , DDR - DATA_RATE_OT => "SDR", -- , DDR - SERDES_MODE => "SLAVE", -- , MASTER, SLAVE - OUTPUT_MODE => "DIFFERENTIAL" - ) - port map ( --- OQ => , - OCE => '1', - CLK0 => ioclk, - CLK1 => '0', - IOCE => serdesstrobe, - RST => reset, - CLKDIV => gclk, - D4 => mdatain(3), - D3 => mdatain(2), - D2 => mdatain(1), - D1 => mdatain(0), --- TQ => , - T1 => '0', - T2 => '0', - T3 => '0', - T4 => '0', - TRAIN => '0', - TCE => '1', - SHIFTIN1 => cascade_di, -- Cascade input D from Master - SHIFTIN2 => cascade_ti, -- Cascade input T from Master - SHIFTIN3 => '1', -- Dummy input in Slave - SHIFTIN4 => '1', -- Dummy input in Slave --- SHIFTOUT1 => , -- Dummy output in Slave --- SHIFTOUT2 => , -- Dummy output in Slave - SHIFTOUT3 => cascade_do, -- Cascade output D data to Master - SHIFTOUT4 => cascade_to); -- Cascade output T data to Master - -end beh; diff --git a/spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl b/spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl new file mode 100644 index 0000000..dec3c9a --- /dev/null +++ b/spartan6/hp_lcd_driver/serdes_n_to_1_spartan6.vhdl @@ -0,0 +1,118 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; + +library UNISIM; +use UNISIM.vcomponents.all; + + +entity serdes_n_to_1 is + generic ( + SF : natural := 8 + ); + port ( + + ioclk : in std_logic; + serdesstrobe : in std_logic; + reset : in std_logic; + gclk : in std_logic; + datain : in std_logic_vector(SF-1 downto 0); + iob_data_out : out std_logic + ); +end serdes_n_to_1; + + +architecture beh of serdes_n_to_1 is + + signal cascade_di : std_logic; + signal cascade_do : std_logic; + signal cascade_ti : std_logic; + signal cascade_to : std_logic; + signal mdatain : std_logic_vector(8 downto 0); + +begin + + datain_for_1 : for b in 0 to SF -1 generate + mdatain(b) <= datain(b); + end generate; + + datain_for_2 : for b in SF to 8 generate + mdatain(b) <= '0'; + end generate; + +-- mdatain <= ( SF-1 downto 0 => datain, others =>'0'); + + oserdes_m : OSERDES2 + generic map ( + DATA_WIDTH => SF, + DATA_RATE_OQ => "SDR", + DATA_RATE_OT => "SDR", + SERDES_MODE => "MASTER", + OUTPUT_MODE => "DIFFERENTIAL" + ) + port map ( + OQ => iob_data_out, + OCE => '1', + CLK0 => ioclk, + CLK1 => '0', + IOCE => serdesstrobe, + RST => reset, + CLKDIV => gclk, + D4 => mdatain(7), + D3 => mdatain(6), + D2 => mdatain(5), + D1 => mdatain(4), +-- TQ => , + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TRAIN => '0', + TCE => '1', + SHIFTIN1 => '1', -- Dummy input in Master + SHIFTIN2 => '1', -- Dummy input in Master + SHIFTIN3 => cascade_do, -- Cascade output D data from slave + SHIFTIN4 => cascade_to, -- Cascade output T data from slave + SHIFTOUT1 => cascade_di, -- Cascade input D data to slave + SHIFTOUT2 => cascade_ti -- Cascade input T data to slave +-- SHIFTOUT3 => , -- Dummy output in Master +-- SHIFTOUT4 => -- Dummy output in Master + ); + + oserdes_s : OSERDES2 + generic map ( + DATA_WIDTH => SF, -- SERDES word width. This should match the setting is BUFPLL + DATA_RATE_OQ => "SDR", -- , DDR + DATA_RATE_OT => "SDR", -- , DDR + SERDES_MODE => "SLAVE", -- , MASTER, SLAVE + OUTPUT_MODE => "DIFFERENTIAL" + ) + port map ( +-- OQ => , + OCE => '1', + CLK0 => ioclk, + CLK1 => '0', + IOCE => serdesstrobe, + RST => reset, + CLKDIV => gclk, + D4 => mdatain(3), + D3 => mdatain(2), + D2 => mdatain(1), + D1 => mdatain(0), +-- TQ => , + T1 => '0', + T2 => '0', + T3 => '0', + T4 => '0', + TRAIN => '0', + TCE => '1', + SHIFTIN1 => cascade_di, -- Cascade input D from Master + SHIFTIN2 => cascade_ti, -- Cascade input T from Master + SHIFTIN3 => '1', -- Dummy input in Slave + SHIFTIN4 => '1', -- Dummy input in Slave +-- SHIFTOUT1 => , -- Dummy output in Slave +-- SHIFTOUT2 => , -- Dummy output in Slave + SHIFTOUT3 => cascade_do, -- Cascade output D data to Master + SHIFTOUT4 => cascade_to); -- Cascade output T data to Master + +end beh; diff --git a/spartan6/hp_lcd_driver/tmds_phy.vhdl b/spartan6/hp_lcd_driver/tmds_phy.vhdl deleted file mode 100644 index 9b31e58..0000000 --- a/spartan6/hp_lcd_driver/tmds_phy.vhdl +++ /dev/null @@ -1,67 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.all; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity tmds_phy is - port ( - reset : in std_logic; - pclk_x2 : in std_logic; - ioclk : in std_logic; - serdesstrobe : in std_logic; - din : in std_logic_vector(9 downto 0); - upper : in std_logic; - tmds_out_p : out std_logic; - tmds_out_n : out std_logic - ); -end tmds_phy; - - -architecture beh of tmds_phy is - - signal din_s : std_logic_vector(9 downto 0); - signal p5_n : std_logic_vector(4 downto 0); - signal p5 : std_logic_vector(4 downto 0); - signal s : std_logic; - - - -begin - - process (pclk_x2) - begin - if rising_edge(pclk_x2) then - if upper = '1' then - din_s <= din; - p5 <= din_s(9 downto 5); - p5_n <= din_s(4 downto 0); - else - p5 <= p5_n; - end if; - end if; - end process; - - - serdes : entity work.serdes_n_to_1 - generic map(SF => 5) - port map ( - ioclk => ioclk, - serdesstrobe => serdesstrobe, - reset => reset, - gclk => pclk_x2, - datain => p5, - iob_data_out => s - ); - - obuf : OBUFDS - generic map (IOSTANDARD => "TMDS_33") - port map ( - I => s, - O => tmds_out_p, - OB => tmds_out_n - ); - - -end beh; diff --git a/spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl b/spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl new file mode 100644 index 0000000..9b31e58 --- /dev/null +++ b/spartan6/hp_lcd_driver/tmds_phy_spartan6.vhdl @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; +use IEEE.NUMERIC_STD.all; + +library UNISIM; +use UNISIM.vcomponents.all; + +entity tmds_phy is + port ( + reset : in std_logic; + pclk_x2 : in std_logic; + ioclk : in std_logic; + serdesstrobe : in std_logic; + din : in std_logic_vector(9 downto 0); + upper : in std_logic; + tmds_out_p : out std_logic; + tmds_out_n : out std_logic + ); +end tmds_phy; + + +architecture beh of tmds_phy is + + signal din_s : std_logic_vector(9 downto 0); + signal p5_n : std_logic_vector(4 downto 0); + signal p5 : std_logic_vector(4 downto 0); + signal s : std_logic; + + + +begin + + process (pclk_x2) + begin + if rising_edge(pclk_x2) then + if upper = '1' then + din_s <= din; + p5 <= din_s(9 downto 5); + p5_n <= din_s(4 downto 0); + else + p5 <= p5_n; + end if; + end if; + end process; + + + serdes : entity work.serdes_n_to_1 + generic map(SF => 5) + port map ( + ioclk => ioclk, + serdesstrobe => serdesstrobe, + reset => reset, + gclk => pclk_x2, + datain => p5, + iob_data_out => s + ); + + obuf : OBUFDS + generic map (IOSTANDARD => "TMDS_33") + port map ( + I => s, + O => tmds_out_p, + OB => tmds_out_n + ); + + +end beh; diff --git a/spartan6/hp_lcd_driver/vram.xco b/spartan6/hp_lcd_driver/vram.xco deleted file mode 100644 index f4624c4..0000000 --- a/spartan6/hp_lcd_driver/vram.xco +++ /dev/null @@ -1,108 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version 14.7 -# Date: Sat Apr 26 13:15:00 2025 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 -# -############################################################## -# -# BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx9 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = tqg144 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -2 -SET verilogsim = false -SET vhdlsim = true -# END Project Options -# BEGIN Select -SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 -# END Select -# BEGIN Parameters -CSET additional_inputs_for_power_estimation=false -CSET algorithm=Minimum_Area -CSET assume_synchronous_clk=false -CSET axi_id_width=4 -CSET axi_slave_type=Memory_Slave -CSET axi_type=AXI4_Full -CSET byte_size=9 -CSET coe_file=no_coe_file_loaded -CSET collision_warnings=ALL -CSET component_name=vram -CSET disable_collision_warnings=false -CSET disable_out_of_range_warnings=false -CSET ecc=false -CSET ecctype=No_ECC -CSET enable_32bit_address=false -CSET enable_a=Always_Enabled -CSET enable_b=Always_Enabled -CSET error_injection_type=Single_Bit_Error_Injection -CSET fill_remaining_memory_locations=false -CSET interface_type=Native -CSET load_init_file=false -CSET mem_file=no_Mem_file_loaded -CSET memory_type=Simple_Dual_Port_RAM -CSET operating_mode_a=WRITE_FIRST -CSET operating_mode_b=WRITE_FIRST -CSET output_reset_value_a=0 -CSET output_reset_value_b=0 -CSET pipeline_stages=0 -CSET port_a_clock=100 -CSET port_a_enable_rate=100 -CSET port_a_write_rate=50 -CSET port_b_clock=100 -CSET port_b_enable_rate=100 -CSET port_b_write_rate=0 -CSET primitive=8kx2 -CSET read_width_a=2 -CSET read_width_b=2 -CSET register_porta_input_of_softecc=false -CSET register_porta_output_of_memory_core=false -CSET register_porta_output_of_memory_primitives=false -CSET register_portb_output_of_memory_core=false -CSET register_portb_output_of_memory_primitives=false -CSET register_portb_output_of_softecc=false -CSET remaining_memory_locations=0 -CSET reset_memory_latch_a=false -CSET reset_memory_latch_b=false -CSET reset_priority_a=CE -CSET reset_priority_b=CE -CSET reset_type=SYNC -CSET softecc=false -CSET use_axi_id=false -CSET use_bram_block=Stand_Alone -CSET use_byte_write_enable=false -CSET use_error_injection_pins=false -CSET use_regcea_pin=false -CSET use_regceb_pin=false -CSET use_rsta_pin=false -CSET use_rstb_pin=false -CSET write_depth_a=228096 -CSET write_width_a=2 -CSET write_width_b=2 -# END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T16:22:25Z -# END Extra information -GENERATE -# CRC: 74d82cad diff --git a/spartan6/hp_lcd_driver/vram_spartan6.vhdl b/spartan6/hp_lcd_driver/vram_spartan6.vhdl new file mode 100644 index 0000000..05a8eae --- /dev/null +++ b/spartan6/hp_lcd_driver/vram_spartan6.vhdl @@ -0,0 +1,36 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY vram IS + generic ( + addr_width:natural :=17; + video_width:natural :=2 + ); + PORT ( + wr_clk: in std_logic; + wr_en : in std_logic; + wr_addr : in STD_LOGIC_VECTOR(addr_width-1 downto 0); + wr_data : in std_logic_vector(video_width-1 downto 0); + rd_clk : in std_logic; + rd_addr : in STD_LOGIC_VECTOR(addr_width-1 downto 0); + rd_data : out std_logic_vector(video_width-1 downto 0) + ); +END vram; + +ARCHITECTURE beh OF vram IS +signal wr_en_v : std_logic_vector(0 downto 0); +BEGIN + +wr_en_v(0)<=wr_en; + +vram_impl0: entity work.vram_spartan6_impl + port map ( + clka => wr_clk, + wea => wr_en_v, + addra => wr_addr, + dina => wr_data, + clkb => rd_clk, + doutb => rd_data, + addrb => rd_addr + ); +END beh; diff --git a/spartan6/hp_lcd_driver/vram_spartan6_impl.xco b/spartan6/hp_lcd_driver/vram_spartan6_impl.xco new file mode 100644 index 0000000..f4624c4 --- /dev/null +++ b/spartan6/hp_lcd_driver/vram_spartan6_impl.xco @@ -0,0 +1,108 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Sat Apr 26 13:15:00 2025 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = tqg144 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=vram +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET mem_file=no_Mem_file_loaded +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=2 +CSET read_width_b=2 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_bram_block=Stand_Alone +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=228096 +CSET write_width_a=2 +CSET write_width_b=2 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T16:22:25Z +# END Extra information +GENERATE +# CRC: 74d82cad -- cgit v1.2.3