diff options
Diffstat (limited to 'spartan6/hp_lcd_driver/Makefile')
| -rw-r--r-- | spartan6/hp_lcd_driver/Makefile | 56 |
1 files changed, 31 insertions, 25 deletions
diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile index d526ede..b3ae3ea 100644 --- a/spartan6/hp_lcd_driver/Makefile +++ b/spartan6/hp_lcd_driver/Makefile @@ -3,13 +3,14 @@ include relpath.mk PART=xc6slx9-2-tqg144 TOP=hp_lcd_driver BUILD=build -VSRCS=hp_lcd_driver.vhd +VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl output_stage.vhdl hp_lcd_driver.vhdl UCF=hp_lcd_driver.ucf UT=hp_lcd_driver.ut -IPSRCS=vram.xco - +IPSRCS= pll_50_80.xco pll_50_91_18.xco vram.xco DESIGN_NAME=${TOP} -ISE_BINDIR=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64 +ISE_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE +ISE_BINDIR_32=${ISE_HOME}/bin/lin +ISE_BINDIR_64=${ISE_HOME}/bin/lin64 INTSTYLE= XST_FLAGS=${INTSTYLE} @@ -54,7 +55,7 @@ ${PRJ}: ${VSRCS} ${GEN_VSRCS} done ; ${NGC}:${XST} - (cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD})) + (cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR_64}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD})) ${XST}: ${PRJ} ${DESIGN_NAME}.xst_template rm -f $@ @@ -67,19 +68,19 @@ ${XST}: ${PRJ} ${DESIGN_NAME}.xst_template echo "-top ${TOP}" >> $@ ${NGD}:${NGC} ${UCF} - (cd ${BUILD} && ${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD})) + (cd ${BUILD} && ${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD})) ${MAP_NCD} ${PCF}:${NGD} - (cd ${BUILD} && ${ISE_BINDIR}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD}) $(call relpath,${PCF},${BUILD})) + (cd ${BUILD} && ${ISE_BINDIR_64}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD}) $(call relpath,${PCF},${BUILD})) ${NCD}: ${MAP_NCD} ${PCF} - (cd ${BUILD} && ${ISE_BINDIR}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD})) + (cd ${BUILD} && ${ISE_BINDIR_64}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD})) ${TWR} ${TWX}: ${NCD} ${PCF} - (cd ${BUILD} && ${ISE_BINDIR}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD})) + (cd ${BUILD} && ${ISE_BINDIR_64}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD})) ${BIT}:${NCD} ${UT} - (cd ${BUILD} && ${ISE_BINDIR}/bitgen ${BITGEN_FLAGS} -f $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD})) + (cd ${BUILD} && ${ISE_BINDIR_64}/bitgen ${BITGEN_FLAGS} -f $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD})) ${SVF}:${BIT} ( cd ${BUILD} && \ @@ -88,12 +89,17 @@ ${SVF}:${BIT} addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\ program -p 1 \n\ quit \n" > impact.run &&\ - ${ISE_BINDIR}/impact -batch impact.run) + ${ISE_BINDIR_64}/impact -batch impact.run) ${BUILD}/%.vhd:%.xco mkdir -p ${BUILD} - (cd ${BUILD} && touch empty.prj && ${ISE_BINDIR}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj) + (cd ${BUILD} && touch empty.prj && ${ISE_BINDIR_32}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj) + + +tidy: + git diff --exit-code -s source + for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done # @@ -191,33 +197,33 @@ ${BUILD}/%.vhd:%.xco # "-p $(PART)" \ # "-top $(TOP_NAME)" \ # > $(PROJNAV_DIR)/tmp.xst -# ${ISE_BINDIR}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr +# ${ISE_BINDIR_64}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr # ## Take the output of the synthesizer and create the NGD file. This rule ## will also be triggered if constraints file is changed. #%.ngd: %.ngc %.ucf -# ${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd +# ${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd # ## Map the NGD file and physical-constraints to the FPGA to create the mapped NCD file. #%_map.ncd %.pcf: %.ngd -# ${ISE_BINDIR}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf +# ${ISE_BINDIR_64}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf # ## Place & route the mapped NCD file to create the final NCD file. #%.ncd: %_map.ncd %.pcf -# ${ISE_BINDIR}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf +# ${ISE_BINDIR_64}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf # ## Take the final NCD file and create an FPGA bitstream file. This rule will also be ## triggered if the bit generation options file is changed. #%.bit: %.ncd $(BITGEN_OPTIONS_FILE) -# ${ISE_BINDIR}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd +# ${ISE_BINDIR_64}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd # ## Convert a bitstream file into an MCS hex file that can be stored into Flash memory. #%.mcs: %.bit -# ${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs +# ${ISE_BINDIR_64}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs # ## Convert a bitstream file into an EXO hex file that can be stored into Flash memory. #%.exo: %.bit -# ${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p exo +# ${ISE_BINDIR_64}/promgen $(PROMGEN_FLAGS) $*.bit -p exo # ## Use .config suffix to trigger creation of a bit/svf file ## depending upon whether an FPGA is the target device. @@ -225,7 +231,7 @@ ${BUILD}/%.vhd:%.xco # ## Create the FPGA timing report after place & route. #%.twr: %.ncd %.pcf -# ${ISE_BINDIR}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf +# ${ISE_BINDIR_64}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf # ## Use .timing suffix to trigger timing report creation. #%.timing: %.twr ; @@ -258,20 +264,20 @@ ${BUILD}/%.vhd:%.xco # assignFile -p 1 -file $(DESIGN_NAME).bit \n\ # program -p 1 \n\ # quit \n" > impact.run -# ${ISE_BINDIR}/impact -batch impact.run +# ${ISE_BINDIR_64}/impact -batch impact.run # ##Simulation using ModelSIM #setlib: -# ${ISE_BINDIR}/vlib work +# ${ISE_BINDIR_64}/vlib work # #vsim-compile: setlib $(SIM_FILES) $(HDL_FILES) -# ${ISE_BINDIR}/vcom $(HDL_FILES) $(SIM_FILES) +# ${ISE_BINDIR_64}/vcom $(HDL_FILES) $(SIM_FILES) # #vsim: vsim-compile -# ${ISE_BINDIR}/vsim $(TESTBENCH_NAME) +# ${ISE_BINDIR_64}/vsim $(TESTBENCH_NAME) # #vsim-run: vsim-compile -# ${ISE_BINDIR}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME) +# ${ISE_BINDIR_64}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME) # ## ## Default targets for FPGA compilations. |