diff options
| -rw-r--r-- | fpga/hp_lcd_driver/hp_lcd_driver.vhdl | 40 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/input_formatter.vhdl | 45 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/output_formatter.vhdl | 14 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/output_stage.vhdl | 6 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/rando_a7.tcl | 2 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/vram_artix7.vhdl | 14 |
6 files changed, 43 insertions, 78 deletions
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl index ec170c9..d55c34d 100644 --- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl @@ -53,7 +53,6 @@ architecture Behavioral of hp_lcd_driver is signal rd_addr : std_logic_vector(addr_width-1 downto 0); signal rd_data : std_logic_vector(video_width-1 downto 0); - signal rd_field : std_logic; signal r : std_logic_vector(7 downto 0); signal g : std_logic_vector(7 downto 0); @@ -102,7 +101,15 @@ begin ); -video_lut<= (video(0),video(1),video(2) xor video(3),video(4),video(5),video(6) xor video(7)); +video_lut <= "1111" when video(0)='1' else + "1011" when video(1)='1' else + "1100" when video(2)='1' else + "1010" when video(3)='1' else + "0011" when video(4)='1' else + "1110" when video(5)='1' else + "1001" when video(6)='1' else + "1101" when video(7)='1' else + "0000"; hdmi_vcc <='1'; @@ -226,18 +233,22 @@ hdmi_vcc <='1'; -- b<=x"00"; - r<= x"ff" when rd_data(0)='1' and rd_field='0' else - x"ff" when rd_data(3)='1' and rd_field='1' else - x"00"; - - g<= x"ff" when rd_data(1)='1' and rd_field='0' else - x"ff" when rd_data(4)='1' and rd_field='1' else - x"00"; - - b<= x"ff" when rd_data(2)='1' and rd_field='0' else - x"ff" when rd_data(5)='1' and rd_field='1' else - x"00"; - + + + r<=x"ff" when rd_data(0)='1' else + x"00"; + +-- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else +-- x"80" when rd_data(0)='1' else +-- x"00"; + + g<=x"ff" when rd_data(1)='1' and rd_data(3)='1' else + x"80" when rd_data(1)='1' else + x"00"; + b<=x"ff" when rd_data(2)='1' and rd_data(3)='1' else + x"80" when rd_data(2)='1' else + x"00"; + --"ff" when rd_data(1) = '1' else @@ -319,7 +330,6 @@ hdmi_vcc <='1'; g_in => g, b_in => b, addr_out => rd_addr, - field_out => rd_field, r_out => r_out, g_out => g_out, b_out => b_out, diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl index 7dbd07a..f8b27c2 100644 --- a/fpga/hp_lcd_driver/input_formatter.vhdl +++ b/fpga/hp_lcd_driver/input_formatter.vhdl @@ -37,6 +37,7 @@ end input_formatter; architecture beh of input_formatter is + signal row_addr : std_logic_vector(addr_width-1 downto 0); signal addr : std_logic_vector(addr_width-1 downto 0); signal wren : std_logic; @@ -54,14 +55,6 @@ architecture beh of input_formatter is signal h_div : natural; signal phase_accum : natural; - signal ix:natural; - signal iy:natural; - signal ox:natural; - signal oy:natural; - signal oz:natural; - signal ow:natural; - - begin @@ -85,11 +78,14 @@ begin + addr_out <= addr; process (sys_rst_n, clk, hsync_pe, vsync) begin if sys_rst_n = '0' then + row_addr <= (others => '0'); + addr <= (others => '0'); h_div <= 0; h_active_counter <= 0; h_fp_counter <= 0; @@ -100,21 +96,21 @@ begin if hsync_pe = '1' then --if v_active_counter = 0 and v_fp_counter=0 then if vsync = '1' then + row_addr <= std_logic_vector(to_unsigned(frame_start, addr_width)); v_fp_counter <= v_front_porch; v_active_counter <= v_active; - iy<=0; elsif v_fp_counter /= 0 then v_fp_counter <= v_fp_counter -1; elsif v_active_counter /= 0 then v_active_counter <= v_active_counter -1; - iy<=iy+1; h_fp_counter <= h_front_porch * clk_multiple + phase; h_active_counter <= h_active; phase_accum <= phase_slip; h_div <= 0; - ix<=0; + addr <= row_addr; + row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); end if; elsif h_fp_counter /= 0 then h_fp_counter <= h_fp_counter -1; @@ -140,37 +136,12 @@ begin if wren = '1' then h_active_counter <= h_active_counter -1; - ix<=ix+1; + addr <= std_logic_vector(unsigned(addr)+h_stride); end if; end if; end if; end process; - - ow<=(ix+4*iy) mod 640; - oz<=0 when ow<320 - else 1; - ox<=ow mod 320; - oy<=iy*2 +oz; - - - - - process (sys_rst_n, clk, hsync_pe, vsync) - begin - if sys_rst_n = '0' then - addr<=( others =>'0'); - elsif rising_edge(clk) then - if oy<384 then - addr<= std_logic_vector(to_unsigned((ox*384) + (383-oy) ,addr'length)); - else - addr <= (others =>'0'); - end if; - end if; - end process; - - - addr_out <= addr; wren_out <= wren; diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl index 771c397..1f9e89f 100644 --- a/fpga/hp_lcd_driver/output_formatter.vhdl +++ b/fpga/hp_lcd_driver/output_formatter.vhdl @@ -26,8 +26,7 @@ entity output_formatter is blank_out : out std_logic; vsync_out : out std_logic; hsync_out : out std_logic; - grid_out : out std_logic; - field_out : out std_logic + grid_out : out std_logic ); end output_formatter; @@ -47,7 +46,6 @@ architecture beh of output_formatter is signal vsync : std_logic; signal hsync : std_logic; signal grid : std_logic; - signal field : std_logic; begin @@ -91,7 +89,6 @@ begin vsync <= '0'; hsync <= '0'; grid <='0'; - field<='0'; elsif rising_edge(clk) then if h = 0 then if v = 0 then @@ -100,7 +97,6 @@ begin --addr <= std_logic_vector(to_unsigned(h_stride, addr'length)); blank <= '0'; vblank <= '0'; - field <='0'; elsif v = v_active then vblank <= '1'; elsif v = v_sync_start then @@ -109,13 +105,8 @@ begin vsync <= '0'; else blank <= vblank; + row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); addr <= row_addr; - if field='0' then - field<='1'; - else - row_addr <= std_logic_vector(unsigned(row_addr)+v_stride); - field <='0'; - end if; --addr <= std_logic_vector(unsigned(row_addr)+h_stride); end if; elsif h = h_active then @@ -148,7 +139,6 @@ begin hsync_out <= hsync; vsync_out <= vsync; grid_out <= grid; - field_out <= field; end beh; diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl index 8583179..b43dc50 100644 --- a/fpga/hp_lcd_driver/output_stage.vhdl +++ b/fpga/hp_lcd_driver/output_stage.vhdl @@ -30,7 +30,6 @@ entity output_stage is vsync_in : in std_logic; addr_out : out std_logic_vector(addr_width - 1 downto 0); - field_out : out std_logic; r_in : in std_logic_vector(7 downto 0); g_in : in std_logic_vector(7 downto 0); @@ -71,7 +70,6 @@ architecture beh of output_stage is signal grid_d : std_logic; signal addr : std_logic_vector(addr_width - 1 downto 0); - signal field: std_logic; signal r : std_logic_vector(7 downto 0); signal g : std_logic_vector(7 downto 0); @@ -126,13 +124,11 @@ begin blank_out => blank, vsync_out => vsync, hsync_out => hsync, - grid_out => grid, - field_out => field + grid_out => grid ); addr_out <= addr; - field_out <= field; dg : entity work.delay generic map(stages => 2) diff --git a/fpga/hp_lcd_driver/rando_a7.tcl b/fpga/hp_lcd_driver/rando_a7.tcl index 11ca3b0..cb14260 100644 --- a/fpga/hp_lcd_driver/rando_a7.tcl +++ b/fpga/hp_lcd_driver/rando_a7.tcl @@ -3,4 +3,4 @@ set part_num "xc7a35tfgg484-2" set normal_xdc "../rando_a7.xdc" set use_pclk 1 set input_video_width 8 -set video_width 6 +set video_width 4 diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl index 470895d..6e4c171 100644 --- a/fpga/hp_lcd_driver/vram_artix7.vhdl +++ b/fpga/hp_lcd_driver/vram_artix7.vhdl @@ -19,12 +19,12 @@ end vram; architecture beh of vram is signal wr_en_v : std_logic_vector(0 downto 0); --- signal wr_data_6 : std_logic_vector(5 downto 0); --- signal rd_data_6 : std_logic_vector(5 downto 0); + signal wr_data_6 : std_logic_vector(5 downto 0); + signal rd_data_6 : std_logic_vector(5 downto 0); begin --- wr_data_6 <= "00" & wr_data; --- rd_data <= rd_data_6(3 downto 0); + wr_data_6 <= "00" & wr_data; + rd_data <= rd_data_6(3 downto 0); wr_en_v(0) <= wr_en; @@ -36,11 +36,9 @@ begin clka => wr_clk, wea => wr_en_v, addra => wr_addr, --- dina => wr_data_6, - dina => wr_data, + dina => wr_data_6, clkb => rd_clk, --- doutb => rd_data_6, - doutb => rd_data, + doutb => rd_data_6, addrb => rd_addr ); end beh; |