From fb71edfb6bc0702aa2ee1cc73d0822bbc37674ad Mon Sep 17 00:00:00 2001
From: fishsoupisgood <github@madingley.org>
Date: Sun, 24 Jan 2021 09:23:12 +0000
Subject: working-ish sensor

---
 humidity_sensors/app/uart.c | 142 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 142 insertions(+)
 create mode 100644 humidity_sensors/app/uart.c

(limited to 'humidity_sensors/app/uart.c')

diff --git a/humidity_sensors/app/uart.c b/humidity_sensors/app/uart.c
new file mode 100644
index 0000000..78eafc4
--- /dev/null
+++ b/humidity_sensors/app/uart.c
@@ -0,0 +1,142 @@
+#include "project.h"
+static void
+_uart_deinit (void)
+{
+  /* Clear the Idle Line Detected bit in the status register by a read
+     to the UART1_SR register followed by a Read to the UART1_DR register */
+  (void) UART1->SR;
+  (void) UART1->DR;
+
+  UART1->BRR2 = UART1_BRR2_RESET_VALUE; /* Set UART1_BRR2 to reset value 0x00 */
+  UART1->BRR1 = UART1_BRR1_RESET_VALUE; /* Set UART1_BRR1 to reset value 0x00 */
+
+  UART1->CR1 = UART1_CR1_RESET_VALUE; /* Set UART1_CR1 to reset value 0x00 */
+  UART1->CR2 = UART1_CR2_RESET_VALUE; /* Set UART1_CR2 to reset value 0x00 */
+  UART1->CR3 = UART1_CR3_RESET_VALUE; /* Set UART1_CR3 to reset value 0x00 */
+  UART1->CR4 = UART1_CR4_RESET_VALUE; /* Set UART1_CR4 to reset value 0x00 */
+  UART1->CR5 = UART1_CR5_RESET_VALUE; /* Set UART1_CR5 to reset value 0x00 */
+
+  UART1->GTR = UART1_GTR_RESET_VALUE;
+  UART1->PSCR = UART1_PSCR_RESET_VALUE;
+}
+
+static void
+_uart_init (u32 BaudRate, UART1_WordLength_TypeDef WordLength,
+            UART1_StopBits_TypeDef StopBits, UART1_Parity_TypeDef Parity,
+            UART1_SyncMode_TypeDef SyncMode, UART1_Mode_TypeDef Mode)
+{
+  u32 BaudRate_Mantissa = 0, BaudRate_Mantissa100 = 0;
+
+  /* Clear the word length bit */
+  UART1->CR1 &= (u8) (~UART1_CR1_M);
+
+  /* Set the word length bit according to UART1_WordLength value */
+  UART1->CR1 |= (u8) WordLength;
+
+  /* Clear the STOP bits */
+  UART1->CR3 &= (u8) (~UART1_CR3_STOP);
+  /* Set the STOP bits number according to UART1_StopBits value  */
+  UART1->CR3 |= (u8) StopBits;
+
+  /* Clear the Parity Control bit */
+  UART1->CR1 &= (u8) (~ (UART1_CR1_PCEN | UART1_CR1_PS));
+  /* Set the Parity Control bit to UART1_Parity value */
+  UART1->CR1 |= (u8) Parity;
+
+  /* Clear the LSB mantissa of UART1DIV  */
+  UART1->BRR1 &= (u8) (~UART1_BRR1_DIVM);
+  /* Clear the MSB mantissa of UART1DIV  */
+  UART1->BRR2 &= (u8) (~UART1_BRR2_DIVM);
+  /* Clear the Fraction bits of UART1DIV */
+  UART1->BRR2 &= (u8) (~UART1_BRR2_DIVF);
+
+  /* Set the UART1 BaudRates in BRR1 and BRR2 registers according to UART1_BaudRate value */
+  BaudRate_Mantissa = ((u32) CLK_GetClockFreq() / (BaudRate << 4));
+  BaudRate_Mantissa100 =
+    (((u32) CLK_GetClockFreq() * 100) / (BaudRate << 4));
+  /* Set the fraction of UART1DIV  */
+  UART1->BRR2 |=
+    (u8) ((u8)
+          (((BaudRate_Mantissa100 -
+             (BaudRate_Mantissa * 100)) << 4) / 100) & (u8) 0x0F);
+  /* Set the MSB mantissa of UART1DIV  */
+  UART1->BRR2 |= (u8) ((BaudRate_Mantissa >> 4) & (u8) 0xF0);
+  /* Set the LSB mantissa of UART1DIV  */
+  UART1->BRR1 |= (u8) BaudRate_Mantissa;
+
+  /* Disable the Transmitter and Receiver before setting the LBCL, CPOL and CPHA bits */
+  UART1->CR2 &= (u8) ~ (UART1_CR2_TEN | UART1_CR2_REN);
+  /* Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
+  UART1->CR3 &=
+    (u8) ~ (UART1_CR3_CPOL | UART1_CR3_CPHA | UART1_CR3_LBCL);
+  /* Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
+  UART1->CR3 |= (u8) ((u8) SyncMode & (u8) (UART1_CR3_CPOL |
+                      UART1_CR3_CPHA |
+                      UART1_CR3_LBCL));
+
+  if ((u8) (Mode & UART1_MODE_TX_ENABLE)) {
+    /* Set the Transmitter Enable bit */
+    UART1->CR2 |= (u8) UART1_CR2_TEN;
+  } else {
+    /* Clear the Transmitter Disable bit */
+    UART1->CR2 &= (u8) (~UART1_CR2_TEN);
+  }
+
+  if ((u8) (Mode & UART1_MODE_RX_ENABLE)) {
+    /* Set the Receiver Enable bit */
+    UART1->CR2 |= (u8) UART1_CR2_REN;
+  } else {
+    /* Clear the Receiver Disable bit */
+    UART1->CR2 &= (u8) (~UART1_CR2_REN);
+  }
+
+  /* Set the Clock Enable bit, lock Polarity, lock Phase and Last Bit Clock
+     pulse bits according to UART1_Mode value */
+  if ((u8) (SyncMode & UART1_SYNCMODE_CLOCK_DISABLE)) {
+    /* Clear the Clock Enable bit */
+    UART1->CR3 &= (u8) (~UART1_CR3_CKEN);
+  } else
+    UART1->CR3 |= (u8) ((u8) SyncMode & UART1_CR3_CKEN);
+}
+
+void
+uart_tx (u8 d)
+{
+  while (! (UART1->SR & UART1_FLAG_TXE));
+
+  UART1->DR = d;
+}
+
+int
+uart_rx (u8 *d)
+{
+  if (UART1->SR & UART1_FLAG_RXNE) {
+    *d = UART1->DR;
+    return 0;
+  }
+
+  return -1;
+}
+
+
+void
+uart_init (void)
+{
+  CLK_PeripheralClockConfig (CLK_PERIPHERAL_UART1, ENABLE);
+
+  _uart_deinit();
+
+  /* UART1 configuration ------------------------------------------------------ */
+  /* UART1 configured as follow:
+     - BaudRate = 115200 baud
+     - Word Length = 8 Bits
+     - One Stop Bit
+     - No parity
+     - Receive and transmit enabled
+     - UART1 Clock disabled
+   */
+  _uart_init ((u32) 115200, UART1_WORDLENGTH_8D, UART1_STOPBITS_1,
+              UART1_PARITY_NO, UART1_SYNCMODE_CLOCK_DISABLE,
+              UART1_MODE_TXRX_ENABLE);
+
+}
-- 
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