/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "kernel/yosys.h" #include "kernel/sigtools.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool memcells_cmp(Cell *a, Cell *b) { if (a->type == "$memrd" && b->type == "$memrd") return a->name < b->name; if (a->type == "$memrd" || b->type == "$memrd") return (a->type == "$memrd") < (b->type == "$memrd"); return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); } Cell *handle_memory(Module *module, RTLIL::Memory *memory) { log("Collecting $memrd, $memwr and $meminit for memory `%s' in module `%s':\n", memory->name.c_str(), module->name.c_str()); Const init_data(State::Sx, memory->size * memory->width); SigMap sigmap(module); int wr_ports = 0; SigSpec sig_wr_clk; SigSpec sig_wr_clk_enable; SigSpec sig_wr_clk_polarity; SigSpec sig_wr_addr; SigSpec sig_wr_data; SigSpec sig_wr_en; int rd_ports = 0; SigSpec sig_rd_clk; SigSpec sig_rd_clk_enable; SigSpec sig_rd_clk_polarity; SigSpec sig_rd_transparent; SigSpec sig_rd_addr; SigSpec sig_rd_data; SigSpec sig_rd_en; int addr_bits = 0; std::vector memcells; for (auto &cell_it : module->cells_) { Cell *cell = cell_it.second; if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) { SigSpec addr = sigmap(cell->getPort("\\ADDR")); for (int i = 0; i < GetSize(addr); i++) if (addr[i] != State::S0) addr_bits = std::max(addr_bits, i+1); memcells.push_back(cell); } } if (memory->start_offset == 0 && addr_bits < 30 && (1 << addr_bits) < memory->size) memory->size = 1 << addr_bits; if (memory->start_offset >= 0) addr_bits = std::min(addr_bits, ceil_log2(memory->size + memory->start_offset)); addr_bits = std::max(addr_bits, 1); if (memcells.empty()) { log(" no cells found. removing memory.\n"); return nullptr; } std::sort(memcells.begin(), memcells.end(), memcells_cmp); for (auto cell : memcells) { log(" %s (%s)\n", log_id(cell), log_id(cell->type)); if (cell->type == "$meminit") { SigSpec addr = sigmap(cell->getPort("\\ADDR")); SigSpec data = sigmap(cell->getPort("\\DATA")); if (!addr.is_fully_const()) log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell)); if (!data.is_fully_const()) log_error("Non-constant data %s in memory initialization %s.\n", log_signal(data), log_id(cell)); int offset = (addr.as_int() - memory->start_offset) * memory->width; if (offset < 0 || offset + GetSize(data) > GetSize(init_data)) log_warning("Address %s in memory initialization %s is out-of-bounds.\n", log_signal(addr), log_id(cell)); for (int i = 0; i < GetSize(data); i++) if (0 <= i+offset && i+offset < GetSize(init_data)) init_data.bits[i+offset] = data[i].data; continue; } if (cell->type == "$memwr") { SigSpec clk = sigmap(cell->getPort("\\CLK")); SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]); SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]); SigSpec addr = sigmap(cell->getPort("\\ADDR")); SigSpec data = sigmap(cell->getPort(

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