From d69daefa9348fcf8fae41c99bfedcb9ce5d38ce7 Mon Sep 17 00:00:00 2001 From: Mike Stirling Date: Sat, 16 Jul 2011 19:03:20 +0100 Subject: Added top-level, PLL, MOS ROM and CRTC. CRTC seems to behave strangely although the design is passing timing. --- bbc_micro_de1.vhd | 563 +++++++++++++++++++++++++++++++++++++++++++++++++++ bbc_micro_de1_tb.vhd | 262 ++++++++++++++++++++++++ os12.qip | 3 + os12.vhd | 168 +++++++++++++++ pll32.ppf | 11 + pll32.qip | 4 + pll32.vhd | 365 +++++++++++++++++++++++++++++++++ seg7.vhd | 31 +++ 8 files changed, 1407 insertions(+) create mode 100644 bbc_micro_de1.vhd create mode 100644 bbc_micro_de1_tb.vhd create mode 100644 os12.qip create mode 100644 os12.vhd create mode 100644 pll32.ppf create mode 100644 pll32.qip create mode 100644 pll32.vhd create mode 100644 seg7.vhd diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd new file mode 100644 index 0000000..78f18a4 --- /dev/null +++ b/bbc_micro_de1.vhd @@ -0,0 +1,563 @@ +-- BBC B Micro +-- +-- Terasic DE1 top-level +-- +-- (C) 2011 Mike Stirling + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Generic top-level entity for Altera DE1 board +entity bbc_micro_de1 is +port ( + -- Clocks + CLOCK_24 : in std_logic_vector(1 downto 0); + CLOCK_27 : in std_logic_vector(1 downto 0); + CLOCK_50 : in std_logic; + EXT_CLOCK : in std_logic; + + -- Switches + SW : in std_logic_vector(9 downto 0); + -- Buttons + KEY : in std_logic_vector(3 downto 0); + + -- 7 segment displays + HEX0 : out std_logic_vector(6 downto 0); + HEX1 : out std_logic_vector(6 downto 0); + HEX2 : out std_logic_vector(6 downto 0); + HEX3 : out std_logic_vector(6 downto 0); + -- Red LEDs + LEDR : out std_logic_vector(9 downto 0); + -- Green LEDs + LEDG : out std_logic_vector(7 downto 0); + + -- VGA + VGA_R : out std_logic_vector(3 downto 0); + VGA_G : out std_logic_vector(3 downto 0); + VGA_B : out std_logic_vector(3 downto 0); + VGA_HS : out std_logic; + VGA_VS : out std_logic; + + -- Serial + UART_RXD : in std_logic; + UART_TXD : out std_logic; + + -- PS/2 Keyboard + PS2_CLK : inout std_logic; + PS2_DAT : inout std_logic; + + -- I2C + I2C_SCLK : inout std_logic; + I2C_SDAT : inout std_logic; + + -- Audio + AUD_XCK : out std_logic; + AUD_BCLK : out std_logic; + AUD_ADCLRCK : out std_logic; + AUD_ADCDAT : in std_logic; + AUD_DACLRCK : out std_logic; + AUD_DACDAT : out std_logic; + + -- SRAM + SRAM_ADDR : out std_logic_vector(17 downto 0); + SRAM_DQ : inout std_logic_vector(15 downto 0); + SRAM_CE_N : out std_logic; + SRAM_OE_N : out std_logic; + SRAM_WE_N : out std_logic; + SRAM_UB_N : out std_logic; + SRAM_LB_N : out std_logic; + + -- SDRAM + DRAM_ADDR : out std_logic_vector(11 downto 0); + DRAM_DQ : inout std_logic_vector(15 downto 0); + DRAM_BA_0 : in std_logic; + DRAM_BA_1 : in std_logic; + DRAM_CAS_N : in std_logic; + DRAM_CKE : in std_logic; + DRAM_CLK : in std_logic; + DRAM_CS_N : in std_logic; + DRAM_LDQM : in std_logic; + DRAM_RAS_N : in std_logic; + DRAM_UDQM : in std_logic; + DRAM_WE_N : in std_logic; + + -- Flash + FL_ADDR : out std_logic_vector(21 downto 0); + FL_DQ : inout std_logic_vector(7 downto 0); + FL_RST_N : in std_logic; + FL_OE_N : in std_logic; + FL_WE_N : in std_logic; + + -- GPIO + GPIO_0 : inout std_logic_vector(35 downto 0); + GPIO_1 : inout std_logic_vector(35 downto 0) + ); +end entity; + +architecture rtl of bbc_micro_de1 is + +------------------------------ +-- PLL (32 MHz master clock) +------------------------------ + +component pll32 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; + +----------------------- +-- 7 segment display +----------------------- + +component seg7 is +port ( + D : in std_logic_vector(3 downto 0); + Q : out std_logic_vector(6 downto 0) +); +end component; + +--------- +-- CPU +--------- + +component T65 is + port( + Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 + Res_n : in std_logic; + Enable : in std_logic; + Clk : in std_logic; + Rdy : in std_logic; + Abort_n : in std_logic; + IRQ_n : in std_logic; + NMI_n : in std_logic; + SO_n : in std_logic; + R_W_n : out std_logic; + Sync : out std_logic; + EF : out std_logic; + MF : out std_logic; + XF : out std_logic; + ML_n : out std_logic; + VP_n : out std_logic; + VDA : out std_logic; + VPA : out std_logic; + A : out std_logic_vector(23 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end component; + +----------------- +-- MC6845 CRTC +----------------- + +component mc6845 is +port ( + CLOCK : in std_logic; + CLKEN : in std_logic; + nRESET : in std_logic; + + -- Bus interface + ENABLE : in std_logic; + R_nW : in std_logic; + RS : in std_logic; + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + + -- Display interface + VSYNC : out std_logic; + HSYNC : out std_logic; + DE : out std_logic; + CURSOR : out std_logic; + LPSTB : in std_logic; + + -- Memory interface + MA : out std_logic_vector(13 downto 0); + RA : out std_logic_vector(4 downto 0) + ); +end component; + +------------------------- +-- "VIDPROC" Video ULA +------------------------- + +component vidproc is +port ( + CLOCK : in std_logic; + -- Clock enable qualifies display cycles (interleaved with CPU cycles) + CLKEN : in std_logic; + nRESET : in std_logic; + + -- Clock enable output to CRTC + CLKEN_CRTC : out std_logic; + + -- Bus interface + ENABLE : in std_logic; + A0 : in std_logic; + -- CPU data bus (for register writes) + DI_CPU : in std_logic_vector(7 downto 0); + -- Display RAM data bus (for display data fetch) + DI_RAM : in std_logic_vector(7 downto 0); + + -- Control interface + nINVERT : in std_logic; + DISEN : in std_logic; + CURSOR : in std_logic; + + -- Video in (teletext mode) + R_IN : in std_logic; + G_IN : in std_logic; + B_IN : in std_logic; + + -- Video out + R : out std_logic; + G : out std_logic; + B : out std_logic + ); +end component; + +------------- +-- MOS ROM +------------- + +component os12 IS + PORT + ( + address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; + +------------- +-- Signals +------------- + +-- Master clock - 32 MHz +signal pll_reset : std_logic; +signal pll_locked : std_logic; +signal clock : std_logic; +signal reset_n : std_logic; + +-- Clock enable counter +-- CPU and video cycles are interleaved. The CPU runs at 2 MHz (every 16th +-- cycle) and the video subsystem is enabled on every odd cycle. +signal clken_counter : unsigned(3 downto 0); +signal slomo_counter : unsigned(17 downto 0); +signal cpu_clken : std_logic; +signal vid_clken : std_logic; + +-- CPU signals +signal cpu_mode : std_logic_vector(1 downto 0); +signal cpu_ready : std_logic; +signal cpu_abort_n : std_logic; +signal cpu_irq_n : std_logic; +signal cpu_nmi_n : std_logic; +signal cpu_so_n : std_logic; +signal cpu_r_nw : std_logic; +signal cpu_sync : std_logic; +signal cpu_ef : std_logic; +signal cpu_mf : std_logic; +signal cpu_xf : std_logic; +signal cpu_ml_n : std_logic; +signal cpu_vp_n : std_logic; +signal cpu_vda : std_logic; +signal cpu_vpa : std_logic; +signal cpu_a : std_logic_vector(23 downto 0); +signal cpu_di : std_logic_vector(7 downto 0); +signal cpu_do : std_logic_vector(7 downto 0); + +-- CRTC signals +signal crtc_clken : std_logic; +signal crtc_do : std_logic_vector(7 downto 0); +signal crtc_vsync : std_logic; +signal crtc_hsync : std_logic; +signal crtc_de : std_logic; +signal crtc_cursor : std_logic; +signal crtc_lpstb : std_logic; +signal crtc_ma : std_logic_vector(13 downto 0); +signal crtc_ra : std_logic_vector(4 downto 0); + +-- "VIDPROC" signals +signal vidproc_invert_n : std_logic; +signal r_in : std_logic; +signal g_in : std_logic; +signal b_in : std_logic; +signal r_out : std_logic; +signal g_out : std_logic; +signal b_out : std_logic; + +-- MOS ROM signals +signal mos_d : std_logic_vector(7 downto 0); + +-- Memory enables +signal ram_enable : std_logic; -- 0x0000 +signal rom_enable : std_logic; -- 0x8000 (BASIC/sideways ROMs) +signal mos_enable : std_logic; -- 0xC000 +-- IO region enables +signal io_fred : std_logic; -- 0xFC00 (1 MHz bus) +signal io_jim : std_logic; -- 0xFD00 (1 MHz bus) +signal io_sheila : std_logic; -- 0xFE00 (System peripherals) +-- SHIELA +signal crtc_enable : std_logic; -- 0xFE00-FE07 +signal acia_enable : std_logic; -- 0xFE08-FE0F +signal serproc_enable : std_logic; -- 0xFE10-FE1F +signal vidproc_enable : std_logic; -- 0xFE20-FE2F +signal romsel_enable : std_logic; -- 0xFE30-FE3F +signal sys_via_enable : std_logic; -- 0xFE40-FE5F +signal user_via_enable : std_logic; -- 0xFE60-FE7F +signal fddc_enable : std_logic; -- 0xFE80-FE9F +signal adlc_enable : std_logic; -- 0xFEA0-FEBF (Econet) +signal adc_enable : std_logic; -- 0xFEC0-FEDF +signal tube_enable : std_logic; -- 0xFEE0-FEFF + +begin + ------------------------- + -- COMPONENT INSTANCES + ------------------------- + + -- 32 MHz master clock + pll: pll32 port map ( + pll_reset, + CLOCK_24(0), + clock, + pll_locked ); + + -- Display of address bus + addr3 : seg7 port map (cpu_a(15 downto 12), HEX3); + addr2 : seg7 port map (cpu_a(11 downto 8), HEX2); + addr1 : seg7 port map (cpu_a(7 downto 4), HEX1); + addr0 : seg7 port map (cpu_a(3 downto 0), HEX0); + + -- 6502 CPU + cpu : T65 port map ( + cpu_mode, + reset_n, + cpu_clken, + clock, + cpu_ready, + cpu_abort_n, + cpu_irq_n, + cpu_nmi_n, + cpu_so_n, + cpu_r_nw, + cpu_sync, + cpu_ef, + cpu_mf, + cpu_xf, + cpu_ml_n, + cpu_vp_n, + cpu_vda, + cpu_vpa, + cpu_a, + cpu_di, + cpu_do ); + + crtc : mc6845 port map ( + clock, + crtc_clken, + reset_n, + crtc_enable, + cpu_r_nw, + cpu_a(0), + cpu_do, + crtc_do, + crtc_vsync, + crtc_hsync, + crtc_de, + crtc_cursor, + crtc_lpstb, + crtc_ma, + crtc_ra ); + + video_ula : vidproc port map ( + clock, + vid_clken, + reset_n, + crtc_clken, + vidproc_enable, + cpu_a(0), + cpu_do, + SRAM_DQ(7 downto 0), + vidproc_invert_n, + crtc_de, + crtc_cursor, + r_in, g_in, b_in, + r_out, g_out, b_out + ); + + -- MOS ROM + mos : os12 port map ( + cpu_a(13 downto 0), + clock, + mos_d ); + + -- Asynchronous reset + pll_reset <= not SW(9); + reset_n <= not (pll_reset or not pll_locked); + + -- Clock enable generation + cpu_clken <= '1' when clken_counter = 0 and (SW(8) = '1' or slomo_counter = 0) else '0'; + vid_clken <= clken_counter(0); + process(clock,reset_n) + begin + if reset_n = '0' then + clken_counter <= (others => '0'); + slomo_counter <= (others => '0'); + elsif rising_edge(clock) then + clken_counter <= clken_counter + 1; + if clken_counter = 0 then + slomo_counter <= slomo_counter + 1; + end if; + end if; + end process; + + -- CPU configuration and fixed signals + cpu_mode <= "00"; -- 6502 + cpu_ready <= '1'; + cpu_abort_n <= '1'; + cpu_irq_n <= '1'; + cpu_nmi_n <= '1'; + cpu_so_n <= '1'; + + -- Address decoding + -- 0x0000 = 32 KB SRAM + -- 0x8000 = 16 KB BASIC/Sideways ROMs + -- 0xC000 = 16 KB MOS ROM + -- + -- IO regions are mapped into a hole in the MOS. There are three regions: + -- 0xFC00 = FRED + -- 0xFD00 = JIM + -- 0xFE00 = SHEILA + ram_enable <= not cpu_a(15); + rom_enable <= cpu_a(15) and not cpu_a(14); + mos_enable <= cpu_a(15) and cpu_a(14) and not (io_fred or io_jim or io_sheila); + io_fred <= '1' when cpu_a(15 downto 8) = "11111100" else '0'; + io_jim <= '1' when cpu_a(15 downto 8) = "11111101" else '0'; + io_sheila <= '1' when cpu_a(15 downto 8) = "11111110" else '0'; + + -- SHEILA address demux + -- All the system peripherals are mapped into this page as follows: + -- 0xFE00 - 0xFE07 = MC6845 CRTC + -- 0xFE08 - 0xFE0F = MC6850 ACIA (Serial/Tape) + -- 0xFE10 - 0xFE1F = Serial ULA + -- 0xFE20 - 0xFE2F = Video ULA + -- 0xFE30 - 0xFE3F = Paged ROM select latch + -- 0xFE40 - 0xFE5F = System VIA (6522) + -- 0xFE60 - 0xFE7F = User VIA (6522) + -- 0xFE80 - 0xFE9F = 8271 Floppy disc controller + -- 0xFEA0 - 0xFEBF = 68B54 ADLC for Econet + -- 0xFEC0 - 0xFEDF = uPD7002 ADC + -- 0xFEE0 - 0xFEFF = Tube ULA + process(cpu_a,io_sheila) + begin + -- All regions normally de-selected + crtc_enable <= '0'; + acia_enable <= '0'; + serproc_enable <= '0'; + vidproc_enable <= '0'; + romsel_enable <= '0'; + sys_via_enable <= '0'; + user_via_enable <= '0'; + fddc_enable <= '0'; + adlc_enable <= '0'; + adc_enable <= '0'; + tube_enable <= '0'; + + if io_sheila = '1' then + case cpu_a(7 downto 5) is + when "000" => + -- 0xFE00 + if cpu_a(4) = '0' then + if cpu_a(3) = '0' then + -- 0xFE00 + crtc_enable <= '1'; + else + -- 0xFE08 + acia_enable <= '1'; + end if; + else + -- 0xFE10 + serproc_enable <= '1'; + end if; + when "001" => + -- 0xFE20 + if cpu_a(4) = '0' then + -- 0xFE20 + vidproc_enable <= '1'; + else + -- 0xFE30 + romsel_enable <= '1'; + end if; + when "010" => sys_via_enable <= '1'; -- 0xFE40 + when "011" => user_via_enable <= '1'; -- 0xFE60 + when "100" => fddc_enable <= '1'; -- 0xFE80 + when "101" => adlc_enable <= '1'; -- 0xFEA0 + when "110" => adc_enable <= '1'; -- 0xFEC0 + when "111" => tube_enable <= '1'; -- 0xFEE0 + end case; + end if; + end process; + + -- CPU data bus mux + cpu_di <= + mos_d when mos_enable = '1' else + "11111111" when rom_enable = '1' else + crtc_do when crtc_enable = '1' else + SRAM_DQ(7 downto 0); + + -- SRAM bus + SRAM_UB_N <= '1'; + SRAM_LB_N <= '0'; + SRAM_CE_N <= '0'; + SRAM_OE_N <= '0'; + SRAM_DQ(15 downto 8) <= (others => '0'); + + -- Synchronous outputs to SRAM + process(clock,reset_n) + variable ram_write : std_logic; + begin + ram_write := ram_enable and not cpu_r_nw; + + if reset_n = '0' then + SRAM_WE_N <= '1'; + SRAM_DQ(7 downto 0) <= (others => 'Z'); + elsif rising_edge(clock) then + -- Default to inputs + SRAM_DQ(7 downto 0) <= (others => 'Z'); + + -- Register SRAM signals to outputs (clock must be at least 2x CPU clock) + if cpu_clken = '0' then + -- Fetch data from previous CPU cycle + SRAM_WE_N <= not ram_write; + SRAM_ADDR <= "00" & cpu_a(15 downto 0); + if ram_write = '1' then + SRAM_DQ(7 downto 0) <= cpu_do; + end if; + else + -- Fetch data from previous display cycle + SRAM_WE_N <= '1'; + SRAM_ADDR <= "001" & crtc_ma(11 downto 0) & crtc_ra(2 downto 0); + end if; + end if; + end process; + + -- VIDPROC + vidproc_invert_n <= '1'; + r_in <= '0'; + g_in <= '0'; + b_in <= '0'; + + -- CRTC drives video out (CSYNC on HSYNC output, VSYNC high) + VGA_HS <= not (crtc_hsync xor crtc_vsync); + VGA_VS <= '1'; + VGA_R <= r_out & r_out & r_out & r_out; + VGA_G <= g_out & g_out & g_out & g_out; + VGA_B <= b_out & b_out & b_out & b_out; + +end architecture; diff --git a/bbc_micro_de1_tb.vhd b/bbc_micro_de1_tb.vhd new file mode 100644 index 0000000..39df39b --- /dev/null +++ b/bbc_micro_de1_tb.vhd @@ -0,0 +1,262 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity bbc_micro_tb is +end entity; + +architecture tb of bbc_micro_tb is +component bbc_micro_de1 is +port ( + -- Clocks + CLOCK_24 : in std_logic_vector(1 downto 0); + CLOCK_27 : in std_logic_vector(1 downto 0); + CLOCK_50 : in std_logic; + EXT_CLOCK : in std_logic; + + -- Switches + SW : in std_logic_vector(9 downto 0); + -- Buttons + KEY : in std_logic_vector(3 downto 0); + + -- 7 segment displays + HEX0 : out std_logic_vector(6 downto 0); + HEX1 : out std_logic_vector(6 downto 0); + HEX2 : out std_logic_vector(6 downto 0); + HEX3 : out std_logic_vector(6 downto 0); + -- Red LEDs + LEDR : out std_logic_vector(9 downto 0); + -- Green LEDs + LEDG : out std_logic_vector(7 downto 0); + + -- VGA + VGA_R : out std_logic_vector(3 downto 0); + VGA_G : out std_logic_vector(3 downto 0); + VGA_B : out std_logic_vector(3 downto 0); + VGA_HS : out std_logic; + VGA_VS : out std_logic; + + -- Serial + UART_RXD : in std_logic; + UART_TXD : out std_logic; + + -- PS/2 Keyboard + PS2_CLK : inout std_logic; + PS2_DAT : inout std_logic; + + -- I2C + I2C_SCLK : inout std_logic; + I2C_SDAT : inout std_logic; + + -- Audio + AUD_XCK : out std_logic; + AUD_BCLK : out std_logic; + AUD_ADCLRCK : out std_logic; + AUD_ADCDAT : in std_logic; + AUD_DACLRCK : out std_logic; + AUD_DACDAT : out std_logic; + + -- SRAM + SRAM_ADDR : out std_logic_vector(17 downto 0); + SRAM_DQ : inout std_logic_vector(15 downto 0); + SRAM_CE_N : out std_logic; + SRAM_OE_N : out std_logic; + SRAM_WE_N : out std_logic; + SRAM_UB_N : out std_logic; + SRAM_LB_N : out std_logic; + + -- SDRAM + DRAM_ADDR : out std_logic_vector(11 downto 0); + DRAM_DQ : inout std_logic_vector(15 downto 0); + DRAM_BA_0 : in std_logic; + DRAM_BA_1 : in std_logic; + DRAM_CAS_N : in std_logic; + DRAM_CKE : in std_logic; + DRAM_CLK : in std_logic; + DRAM_CS_N : in std_logic; + DRAM_LDQM : in std_logic; + DRAM_RAS_N : in std_logic; + DRAM_UDQM : in std_logic; + DRAM_WE_N : in std_logic; + + -- Flash + FL_ADDR : out std_logic_vector(21 downto 0); + FL_DQ : inout std_logic_vector(7 downto 0); + FL_RST_N : in std_logic; + FL_OE_N : in std_logic; + FL_WE_N : in std_logic; + + -- GPIO + GPIO_0 : inout std_logic_vector(35 downto 0); + GPIO_1 : inout std_logic_vector(35 downto 0) + ); +end component; + + +signal clock_24 : std_logic_vector(1 downto 0) := "00"; +signal clock_27 : std_logic_vector(1 downto 0) := "00"; +signal clock_50 : std_logic := '0'; +signal ext_clock : std_logic := '0'; +signal sw : std_logic_vector(9 downto 0); +signal key : std_logic_vector(3 downto 0); +signal hex0 : std_logic_vector(6 downto 0); +signal hex1 : std_logic_vector(6 downto 0); +signal hex2 : std_logic_vector(6 downto 0); +signal hex3 : std_logic_vector(6 downto 0); +signal ledr : std_logic_vector(9 downto 0); +signal ledg : std_logic_vector(7 downto 0); +signal vga_r : std_logic_vector(3 downto 0); +signal vga_g : std_logic_vector(3 downto 0); +signal vga_b : std_logic_vector(3 downto 0); +signal vga_hs : std_logic; +signal vga_vs : std_logic; +signal uart_rxd : std_logic; +signal uart_txd : std_logic; +signal ps2_clk : std_logic; +signal ps2_dat : std_logic; +signal i2c_sclk : std_logic; +signal i2c_sdat : std_logic; +signal aud_xck : std_logic; +signal aud_bclk : std_logic; +signal aud_adclrck : std_logic; +signal aud_adcdat : std_logic; +signal aud_daclrck : std_logic; +signal aud_dacdat : std_logic; +signal sram_addr : std_logic_vector(17 downto 0); +signal sram_dq : std_logic_vector(15 downto 0); +signal sram_ce_n : std_logic; +signal sram_oe_n : std_logic; +signal sram_we_n : std_logic; +signal sram_ub_n : std_logic; +signal sram_lb_n : std_logic; +signal dram_addr : std_logic_vector(11 downto 0); +signal dram_dq : std_logic_vector(15 downto 0); +signal dram_ba_0 : std_logic; +signal dram_ba_1 : std_logic; +signal dram_cas_n : std_logic; +signal dram_cke : std_logic; +signal dram_clk : std_logic; +signal dram_cs_n : std_logic; +signal dram_ldqm : std_logic; +signal dram_ras_n : std_logic; +signal dram_udqm : std_logic; +signal dram_we_n : std_logic; +signal fl_addr : std_logic_vector(21 downto 0); +signal fl_dq : std_logic_vector(7 downto 0); +signal fl_rst_n : std_logic; +signal fl_oe_n : std_logic; +signal fl_we_n : std_logic; +signal gpio_0 : std_logic_vector(35 downto 0); +signal gpio_1 : std_logic_vector(35 downto 0); + +signal n_reset : std_logic := '0'; +signal slow : std_logic := '0'; + +type ram_t is array(0 to 65535) of std_logic_vector(15 downto 0); +signal ram : ram_t; +signal ram_a : std_logic_vector(15 downto 0); +begin + + uut: bbc_micro_de1 port map ( + clock_24, + clock_27, + clock_50, + ext_clock, + sw, + key, + hex0, + hex1, + hex2, + hex3, + ledr, + ledg, + vga_r, + vga_g, + vga_b, + vga_hs, + vga_vs, + uart_rxd, + uart_txd, + ps2_clk, + ps2_dat, + i2c_sclk, + i2c_sdat, + aud_xck, + aud_bclk, + aud_adclrck, + aud_adcdat, + aud_daclrck, + aud_dacdat, + sram_addr, + sram_dq, + sram_ce_n, + sram_oe_n, + sram_we_n, + sram_ub_n, + sram_lb_n, + dram_addr, + dram_dq, + dram_ba_0, + dram_ba_1, + dram_cas_n, + dram_cke, + dram_clk, + dram_cs_n, + dram_ldqm, + dram_ras_n, + dram_udqm, + dram_we_n, + fl_addr, + fl_dq, + fl_rst_n, + fl_oe_n, + fl_we_n, + gpio_0, + gpio_1 + ); + + sw <= n_reset & slow & "00000000"; + clock_50 <= not clock_50 after 10 ns; + clock_27(0) <= not clock_27(0) after 18.5 ns; + clock_27(1) <= not clock_27(1) after 18.5 ns; + clock_24(0) <= not clock_24(0) after 20.8 ns; + clock_24(1) <= not clock_24(1) after 20.8 ns; + + reset: process + begin + wait for 100 ns; + n_reset <= '1'; + end process; + + sram: process(sram_addr,sram_dq,sram_ce_n,sram_oe_n,sram_we_n,sram_ub_n,sram_lb_n) + begin + if sram_ce_n = '0' then + if sram_oe_n = '0' and sram_we_n = '1' then + if sram_ub_n = '0' then + sram_dq(15 downto 8) <= ram(to_integer(unsigned(sram_addr(15 downto 0))))(15 downto 8); + else + sram_dq(15 downto 8) <= (others => 'Z'); + end if; + if sram_lb_n = '0' then + sram_dq(7 downto 0) <= ram(to_integer(unsigned(sram_addr(15 downto 0))))(7 downto 0); + else + sram_dq(7 downto 0) <= (others => 'Z'); + end if; + else + sram_dq(15 downto 0) <= (others => 'Z'); + if sram_we_n = '0' then + if sram_ub_n = '0' then + ram(to_integer(unsigned(sram_addr(15 downto 0))))(15 downto 8) <= sram_dq(15 downto 8); + end if; + if sram_lb_n = '0' then + ram(to_integer(unsigned(sram_addr(15 downto 0))))(7 downto 0) <= sram_dq(7 downto 0); + end if; + end if; + end if; + else + sram_dq <= (others => 'Z'); + end if; + end process; + + +end architecture; diff --git a/os12.qip b/os12.qip new file mode 100644 index 0000000..23dadcc --- /dev/null +++ b/os12.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "os12.vhd"] diff --git a/os12.vhd b/os12.vhd new file mode 100644 index 0000000..d463a45 --- /dev/null +++ b/os12.vhd @@ -0,0 +1,168 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: os12.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY os12 IS + PORT + ( + address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END os12; + + +ARCHITECTURE SYN OF os12 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "./roms/os12.hex", + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 16384, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + widthad_a => 14, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + clock0 => clock, + address_a => address, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/os12.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/os12.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0] +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL os12.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL os12.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL os12.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL os12.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL os12_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL os12_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL os12_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/pll32.ppf b/pll32.ppf new file mode 100644 index 0000000..1ba6b2c --- /dev/null +++ b/pll32.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/pll32.qip b/pll32.qip new file mode 100644 index 0000000..f78bd93 --- /dev/null +++ b/pll32.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll32.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll32.ppf"] diff --git a/pll32.vhd b/pll32.vhd new file mode 100644 index 0000000..3c9f397 --- /dev/null +++ b/pll32.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll32.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll32 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll32; + + +ARCHITECTURE SYN OF pll32 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + gate_lock_signal : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 25, + clk0_duty_cycle => 50, + clk0_multiply_by => 16, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + gate_lock_signal => "NO", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone II", + invalid_lock_multiplier => 5, + lpm_hint => "CBX_MODULE_PREFIX=pll32", + lpm_type => "altpll", + operation_mode => "NORMAL", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + valid_lock_multiplier => 1 + ) + PORT MAP ( + inclk => sub_wire4, + areset => areset, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll32.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll32_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/seg7.vhd b/seg7.vhd new file mode 100644 index 0000000..e4e4744 --- /dev/null +++ b/seg7.vhd @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; + +-- Convert BCD to 7-segment display characters +entity seg7 is +port ( + D : in std_logic_vector(3 downto 0); + Q : out std_logic_vector(6 downto 0) +); +end seg7; + +architecture seg7_arch of seg7 is +begin + Q <= "1000000" when D = "0000" else + "1111001" when D = "0001" else + "0100100" when D = "0010" else + "0110000" when D = "0011" else + "0011001" when D = "0100" else + "0010010" when D = "0101" else + "0000010" when D = "0110" else + "1111000" when D = "0111" else + "0000000" when D = "1000" else + "0010000" when D = "1001" else + "0001000" when D = "1010" else + "0000011" when D = "1011" else + "1000110" when D = "1100" else + "0100001" when D = "1101" else + "0000110" when D = "1110" else + "0001110"; +end seg7_arch; + -- cgit v1.2.3