From 7ed3fd28942ce4eb7027a1d45cb5f84bcac31957 Mon Sep 17 00:00:00 2001 From: Mike Stirling Date: Sun, 7 Aug 2011 22:17:41 +0100 Subject: Switched to external MOS ROM (in flash) and removed MOS and EHBASIC ROMs from project --- bbc_micro_de1.vhd | 40 +------------ ehbasic.qip | 3 - ehbasic.vhd | 168 ------------------------------------------------------ os12.qip | 3 - os12.vhd | 168 ------------------------------------------------------ 5 files changed, 1 insertion(+), 381 deletions(-) delete mode 100644 ehbasic.qip delete mode 100644 ehbasic.vhd delete mode 100644 os12.qip delete mode 100644 os12.vhd diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd index 03e5a65..3cdb112 100644 --- a/bbc_micro_de1.vhd +++ b/bbc_micro_de1.vhd @@ -282,32 +282,6 @@ port ( ); end component; -------------- --- MOS ROM -------------- - -component os12 IS - PORT - ( - address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -end component; - --------------- --- Test ROM --------------- - -component ehbasic IS - PORT - ( - address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -end component; - -------------- -- 6522 VIA -------------- @@ -616,9 +590,6 @@ signal ttxt_g : std_logic; signal ttxt_b : std_logic; signal ttxt_y : std_logic; --- MOS ROM signals -signal mos_d : std_logic_vector(7 downto 0); - -- System VIA signals signal sys_via_do : std_logic_vector(7 downto 0); signal sys_via_do_oe_n : std_logic; @@ -827,15 +798,6 @@ begin ttxt_r, ttxt_g, ttxt_b, ttxt_y ); - -- MOS ROM - mos : os12 port map ( - cpu_a(13 downto 0), - clock, - mos_d ); --- test_rom : ehbasic port map ( --- cpu_a(13 downto 0), --- clock, mos_d ); - -- System VIA system_via : m6522 port map ( cpu_a(3 downto 0), @@ -1094,7 +1056,7 @@ begin cpu_di <= SRAM_DQ(7 downto 0) when ram_enable = '1' else FL_DQ when rom_enable = '1' else - mos_d when mos_enable = '1' else + FL_DQ when mos_enable = '1' else crtc_do when crtc_enable = '1' else "00000010" when acia_enable = '1' else sys_via_do when sys_via_enable = '1' else diff --git a/ehbasic.qip b/ehbasic.qip deleted file mode 100644 index 3221c1f..0000000 --- a/ehbasic.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "9.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ehbasic.vhd"] diff --git a/ehbasic.vhd b/ehbasic.vhd deleted file mode 100644 index 1ab195b..0000000 --- a/ehbasic.vhd +++ /dev/null @@ -1,168 +0,0 @@ --- megafunction wizard: %ROM: 1-PORT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altsyncram - --- ============================================================ --- File Name: ehbasic.vhd --- Megafunction Name(s): --- altsyncram --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 222 10/21/2009 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY ehbasic IS - PORT - ( - address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -END ehbasic; - - -ARCHITECTURE SYN OF ehbasic IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(7 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => "./roms/asm/basic/ehbasic.hex", - intended_device_family => "Cyclone II", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 16384, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - widthad_a => 14, - width_a => 8, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" --- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" --- Retrieval info: PRIVATE: AclrByte NUMERIC "0" --- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: Clken NUMERIC "0" --- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" --- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "./roms/asm/basic/ehbasic.hex" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: RegAddr NUMERIC "1" --- Retrieval info: PRIVATE: RegOutput NUMERIC "0" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: SingleClock NUMERIC "1" --- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" --- Retrieval info: PRIVATE: WidthData NUMERIC "8" --- Retrieval info: PRIVATE: rden NUMERIC "0" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/asm/basic/ehbasic.hex" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" --- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0] --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] --- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: GEN_FILE: TYPE_NORMAL ehbasic.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ehbasic.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ehbasic.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ehbasic.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ehbasic_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ehbasic_waveforms.html FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ehbasic_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/os12.qip b/os12.qip deleted file mode 100644 index 23dadcc..0000000 --- a/os12.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "9.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "os12.vhd"] diff --git a/os12.vhd b/os12.vhd deleted file mode 100644 index d463a45..0000000 --- a/os12.vhd +++ /dev/null @@ -1,168 +0,0 @@ --- megafunction wizard: %ROM: 1-PORT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altsyncram - --- ============================================================ --- File Name: os12.vhd --- Megafunction Name(s): --- altsyncram --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 222 10/21/2009 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY os12 IS - PORT - ( - address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); -END os12; - - -ARCHITECTURE SYN OF os12 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(7 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => "./roms/os12.hex", - intended_device_family => "Cyclone II", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 16384, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => "UNREGISTERED", - widthad_a => 14, - width_a => 8, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" --- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" --- Retrieval info: PRIVATE: AclrByte NUMERIC "0" --- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: Clken NUMERIC "0" --- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" --- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "./roms/os12.hex" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: RegAddr NUMERIC "1" --- Retrieval info: PRIVATE: RegOutput NUMERIC "0" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: SingleClock NUMERIC "1" --- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" --- Retrieval info: PRIVATE: WidthData NUMERIC "8" --- Retrieval info: PRIVATE: rden NUMERIC "0" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/os12.hex" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" --- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0] --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] --- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: GEN_FILE: TYPE_NORMAL os12.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL os12.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL os12.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL os12.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL os12_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL os12_waveforms.html FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL os12_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf -- cgit v1.2.3