diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd
index 2788103..fa7b2e8 100644
--- a/bbc_micro_de1.vhd
+++ b/bbc_micro_de1.vhd
@@ -70,7 +70,7 @@ generic (
 	-- 5 Not used
 	-- 6 Not used
 	-- 7 MOS
-	ROM_OFFSET			:	std_logic_vector(7 downto 0) := "00001000"
+	ROM_OFFSET			:	std_logic_vector(21 downto 0) := std_logic_vector(to_unsigned(16#20000#,22))
 	);
 port (
 	-- Clocks
@@ -663,6 +663,7 @@ signal sys_via_ca2_out	:	std_logic;
 signal sys_via_ca2_oe_n	:	std_logic;
 signal sys_via_pa_in	:	std_logic_vector(7 downto 0);
 signal sys_via_pa_out	:	std_logic_vector(7 downto 0);
+signal effective_sys_via_pa_out	:	std_logic_vector(7 downto 0);
 signal sys_via_pa_oe_n	:	std_logic_vector(7 downto 0);
 signal sys_via_cb1_in	:	std_logic := '0';
 signal sys_via_cb1_out	:	std_logic;
@@ -745,6 +746,9 @@ signal romsel			:	std_logic_vector(3 downto 0);
 
 signal mhz1_enable		:	std_logic;		-- Set for access to any 1 MHz peripheral
 
+signal video_data 	: std_logic_vector (7 downto 0);
+signal cpu_ram_di 	: std_logic_vector (7 downto 0);
+
 begin
 	-------------------------
 	-- COMPONENT INSTANCES
@@ -800,6 +804,8 @@ begin
 		cpu_a,
 		cpu_di,
 		cpu_do );
+
+	crtc_lpstb <='0';
 		
 	crtc : mc6845 port map (
 		clock,
@@ -826,7 +832,7 @@ begin
 		vidproc_enable,
 		cpu_a(0),
 		cpu_do,
-		SRAM_DQ(7 downto 0),
+		video_data,
 		vidproc_invert_n,
 		vidproc_disen,
 		crtc_cursor,
@@ -850,7 +856,7 @@ begin
 		reset_n,
 		clock, -- Data input is synchronised from the bus clock domain
 		vid_clken,
-		SRAM_DQ(6 downto 0),
+		video_data(6 downto 0),
 		ttxt_glr,
 		ttxt_dew,
 		ttxt_crs,
@@ -889,6 +895,8 @@ begin
 		mhz4_clken,
 		clock
 		);
+
+	effective_sys_via_pa_out <= sys_via_pa_out or sys_via_pa_oe_n;
 	
 	-- User VIA
 	user_via : m6522 port map (
@@ -1118,7 +1126,7 @@ begin
 	
 	-- CPU data bus mux and interrupts
 	cpu_di <=
-		SRAM_DQ(7 downto 0) when ram_enable = '1' else
+		cpu_ram_di	when ram_enable = '1' else
 		FL_DQ		when rom_enable = '1' else
 		FL_DQ		when mos_enable = '1' else
 		crtc_do		when crtc_enable = '1' else
@@ -1137,19 +1145,17 @@ begin
 	FL_CE_N <= '0';
 	FL_OE_N <= '0';
 	FL_WE_N <= '1';
-	FL_ADDR(21 downto 17) <= ROM_OFFSET(7 downto 3);
-	FL_ADDR(16 downto 14) <=
-		"111" when mos_enable = '1' else
-		"0" & romsel(1 downto 0);
+	FL_ADDR(21 downto 17) <= ROM_OFFSET(21 downto 17);
+	FL_ADDR(16 downto 14) <= "111" when mos_enable = '1' else "0" &  romsel(1 downto 0);
 	FL_ADDR(13 downto 0) <= cpu_a(13 downto 0);		
 		
 	-- SRAM bus
 	SRAM_UB_N <= '1';
 	SRAM_LB_N <= '0';
-	SRAM_CE_N <= '0';
+	SRAM_CE_N <= clock;
 	SRAM_OE_N <= '0';
-	SRAM_DQ(15 downto 8) <= (others => '0');
-	
+	video_data <= SRAM_DQ(7 downto 0);
+
 	-- Synchronous outputs to SRAM
 	process(clock,reset_n)
 	variable ram_write : std_logic;
@@ -1158,23 +1164,25 @@ begin
 	
 		if reset_n = '0' then
 			SRAM_WE_N <= '1';
-			SRAM_DQ(7 downto 0) <= (others => 'Z');
+			SRAM_DQ(15 downto 0) <= (others => 'Z');
 		elsif rising_edge(clock) then
-			-- Default to inputs
-			SRAM_DQ(7 downto 0) <= (others => 'Z');
-			
 			-- Register SRAM signals to outputs (clock must be at least 2x CPU clock)
 			if vid_clken = '1' then
-				-- Fetch data from previous CPU cycle
+				-- set up bus for CPU cycle
 				SRAM_WE_N <= not ram_write;
 				SRAM_ADDR <= "00" & cpu_a(15 downto 0);
 				if ram_write = '1' then
+					SRAM_DQ(15 downto 8) <=(others =>'0');
 					SRAM_DQ(7 downto 0) <= cpu_do;
+				else
+					SRAM_DQ(15 downto 0) <= (others => 'Z');
 				end if;
 			else
-				-- Fetch data from previous display cycle
+				cpu_ram_di <= SRAM_DQ(7 downto 0);
+				-- setup crtc cycle 
 				SRAM_WE_N <= '1';
 				SRAM_ADDR <= "000" & display_a;
+				SRAM_DQ(15 downto 0) <= (others => 'Z');
 			end if;
 		end if;
 	end process;
@@ -1242,24 +1250,25 @@ begin
 	
 	-- Connections to System VIA
 	-- ADC
-	sys_via_cb1_in <= '1'; -- /EOC
+	sys_via_cb1_in <= '0'; -- EOC
 	-- CRTC
 	sys_via_ca1_in <= crtc_vsync;
 	sys_via_cb2_in <= crtc_lpstb;
 	-- Keyboard
 	sys_via_ca2_in <= keyb_int;
 	sys_via_pa_in(7) <= keyb_out;
-	sys_via_pa_in(6 downto 0) <= sys_via_pa_out(6 downto 0); -- Must loop back output pins or keyboard won't work
-	keyb_column <= sys_via_pa_out(3 downto 0);
-	keyb_row <= sys_via_pa_out(6 downto 4);
+	sys_via_pa_in(6 downto 0) <= effective_sys_via_pa_out(6 downto 0); -- Must loop back output pins or keyboard won't work
+	keyb_column <= effective_sys_via_pa_out(3 downto 0);
+	keyb_row <= effective_sys_via_pa_out(6 downto 4);
 	-- Sound
-	sound_di <= sys_via_pa_out;
+	sound_di <= effective_sys_via_pa_out;
 	-- Others (idle until missing bits implemented)
 	sys_via_pb_in(7 downto 4) <= (others => '1');
 	
 	-- Connections to User VIA (user port is output on green LEDs)
 	user_via_ca1_in <= '1'; -- Pulled up
 	--LEDG <= user_via_pb_out;
+        --LEDG(7 downto 2) <= (others => '0');
 	
 	-- MMBEEB
 	user_via_cb1_in <= user_via_pb_out(1);
@@ -1290,15 +1299,15 @@ begin
 	disp_addr_offs <= ic32(5 downto 4);
 	caps_lock_led_n <= ic32(6);
 	shift_lock_led_n <= ic32(7);
+
 	
 	process(clock,reset_n)
 	variable bit_num : integer;
 	begin
 		bit_num := to_integer(unsigned(sys_via_pb_out(2 downto 0)));
-	
 		if reset_n = '0' then
-			ic32 <= (others => '0');
-		elsif rising_edge(clock) then
+			ic32 <= (others => '1');
+		elsif rising_edge(clock) then -- the real beep latches this on the 1MHz bus clock exactly once per sys_via_enable
 			ic32(bit_num) <= sys_via_pb_out(3);
 		end if;
 	end process;
@@ -1311,6 +1320,9 @@ begin
 	-- DEBUG STUFF
 	-----------------
 	
+	DRAM_DQ <= (others => 'Z');
+	DRAM_DQ <= (others => 'Z');
+
 	GPIO_0(0) <= not (crtc_hsync xor crtc_vsync);
 	GPIO_0(1) <= crtc_de;