From 1575d4f53805f177474b5bb96daebede9b2dfb73 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 24 Feb 2021 23:45:58 +0000 Subject: base --- de1/fpga-bbc-pq/master/other-floating-pins.patch | 57 ++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 de1/fpga-bbc-pq/master/other-floating-pins.patch (limited to 'de1/fpga-bbc-pq/master/other-floating-pins.patch') diff --git a/de1/fpga-bbc-pq/master/other-floating-pins.patch b/de1/fpga-bbc-pq/master/other-floating-pins.patch new file mode 100644 index 0000000..2eb6ee7 --- /dev/null +++ b/de1/fpga-bbc-pq/master/other-floating-pins.patch @@ -0,0 +1,57 @@ +diff --git a/bbc_micro_de1.vhd b/bbc_micro_de1.vhd +index fa7b2e8..991fb40 100644 +--- a/bbc_micro_de1.vhd ++++ b/bbc_micro_de1.vhd +@@ -781,6 +781,8 @@ begin + LEDR(2) -- WATCHPOINT + ); + ++ debug_aux <= (others => '0'); ++ + -- 6502 CPU + cpu : T65 port map ( + cpu_mode, +@@ -929,7 +931,10 @@ begin + mhz4_clken, + clock + ); +- ++ ++ user_via_ca2_in <='0'; ++ user_via_pa_in <=(others => '0'); ++ + --LEDG(0) <= not PS2_CLK; + --LEDG(1) <= not PS2_DAT; + +@@ -972,6 +977,12 @@ begin + LEDR(5), -- IS_DONE + LEDR(4) -- IS_ERROR + ); ++ AUD_ADCLRCK <= '1'; ++ ++ UART_TXD <= '0'; ++ DRAM_ADDR <= (others => '1'); ++ LEDR(9 downto 6) <= (others => '0'); ++ sys_via_pb_in(3 downto 0) <= (others => '1'); + + -- Asynchronous reset + -- PLL is reset by external reset switch +@@ -1123,6 +1134,8 @@ begin + end case; + end if; + end process; ++ ++ FL_DQ <= (others =>'Z'); + + -- CPU data bus mux and interrupts + cpu_di <= +@@ -1325,5 +1338,9 @@ begin + + GPIO_0(0) <= not (crtc_hsync xor crtc_vsync); + GPIO_0(1) <= crtc_de; ++ GPIO_0(2) <= ld_vsync; ++ GPIO_0(3) <= ld_hsync; ++ GPIO_0(35 downto 4) <= (others => '0'); ++ GPIO_1 <= (others => '0'); + + end architecture; -- cgit v1.2.3