From 6f64e80f219273967d6ac7096f3ca3d7db5a0e79 Mon Sep 17 00:00:00 2001 From: Christian Starkjohann Date: Thu, 28 Nov 2013 11:56:15 +0100 Subject: Added long-pending 18 MHz module without CRC. This module was contributed by Lukas Schrittwieser as a complement to the 18 MHz module including a CRC check. It is useful for boot loaders on boards which run on 18 MHz because they use the CRC module in the main code. --- tests/Makefile | 4 +- tests/usbconfig.h | 6 +- usbdrv/usbdrvasm.S | 6 +- usbdrv/usbdrvasm18.inc | 557 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 569 insertions(+), 4 deletions(-) create mode 100644 usbdrv/usbdrvasm18.inc diff --git a/tests/Makefile b/tests/Makefile index a800c2a..43f8da1 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -13,7 +13,7 @@ DEFINES = CFLAGS = $(DEFINES) -Iusbdrv -I. -DDEBUG_LEVEL=0 OBJECTS = usbdrv/usbdrv.o usbdrv/usbdrvasm.o usbdrv/oddebug.o main.o -COMPILE = avr-gcc -Wall -Os -DF_CPU=$(F_CPU) $(CFLAGS) -mmcu=$(DEVICE) +COMPILE = avr-gcc -Wall -Os -DF_CPU=$(F_CPU) $(CRCFLAG) $(CFLAGS) -mmcu=$(DEVICE) SIZES_TMP = /tmp/sizetmp.txt @@ -39,6 +39,8 @@ sizes sizes.txt: $(MAKE) clean; $(MAKE) main.elf F_CPU=16500000 avr-size main.elf | tail -1 | awk '{print "Minimum_with_16_5_MHz", $$1+$$2, $$3+$$2}' >>$(SIZES_TMP) $(MAKE) clean; $(MAKE) main.elf F_CPU=18000000 + avr-size main.elf | tail -1 | awk '{print "Minimum_with_18_MHz", $$1+$$2, $$3+$$2}' >>$(SIZES_TMP) + $(MAKE) clean; $(MAKE) main.elf F_CPU=18000000 CRCFLAG="-DUSE_CRC=1" avr-size main.elf | tail -1 | awk '{print "Minimum_with_18_MHz+CRC", $$1+$$2, $$3+$$2}' >>$(SIZES_TMP) $(MAKE) clean; $(MAKE) main.elf F_CPU=20000000 avr-size main.elf | tail -1 | awk '{print "Minimum_with_20_MHz", $$1+$$2, $$3+$$2}' >>$(SIZES_TMP) diff --git a/tests/usbconfig.h b/tests/usbconfig.h index 0061ee4..e079e06 100644 --- a/tests/usbconfig.h +++ b/tests/usbconfig.h @@ -22,7 +22,11 @@ features. Don't use it as a prototype, use usbconfig-prototype.h instead! #define USB_CFG_DMINUS_BIT 4 #define USB_CFG_DPLUS_BIT 2 #define USB_CFG_CLOCK_KHZ (F_CPU/1000) -#define USB_CFG_CHECK_CRC (USB_CFG_CLOCK_KHZ == 18000) +#ifdef USE_CRC +# define USB_CFG_CHECK_CRC 1 +#else +# define USB_CFG_CHECK_CRC 0 +#endif /* ----------------------- Optional Hardware Config ------------------------ */ diff --git a/usbdrv/usbdrvasm.S b/usbdrv/usbdrvasm.S index 6fa575d..3bda63c 100644 --- a/usbdrv/usbdrvasm.S +++ b/usbdrv/usbdrvasm.S @@ -366,7 +366,7 @@ usbMFTimeout: # if USB_CFG_CLOCK_KHZ == 18000 # include "usbdrvasm18-crc.inc" # else -# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!" +# error "USB_CFG_CLOCK_KHZ is not one of the supported rates for USB_CFG_CHECK_CRC!" # endif #else /* USB_CFG_CHECK_CRC */ # if USB_CFG_CLOCK_KHZ == 12000 @@ -379,9 +379,11 @@ usbMFTimeout: # include "usbdrvasm16.inc" # elif USB_CFG_CLOCK_KHZ == 16500 # include "usbdrvasm165.inc" +# elif USB_CFG_CLOCK_KHZ == 18000 +# include "usbdrvasm18.inc" # elif USB_CFG_CLOCK_KHZ == 20000 # include "usbdrvasm20.inc" # else -# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!" +# error "USB_CFG_CLOCK_KHZ is not one of the supported rates!" # endif #endif /* USB_CFG_CHECK_CRC */ diff --git a/usbdrv/usbdrvasm18.inc b/usbdrv/usbdrvasm18.inc new file mode 100644 index 0000000..e058bb9 --- /dev/null +++ b/usbdrv/usbdrvasm18.inc @@ -0,0 +1,557 @@ +/* Name: usbdrvasm18.inc + * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers + * Author: Lukas Schrittwieser (based on 20 MHz usbdrvasm20.inc by Jeroen Benschop) + * Creation Date: 2009-01-20 + * Tabsize: 4 + * Copyright: (c) 2008 by Lukas Schrittwieser and OBJECTIVE DEVELOPMENT Software GmbH + * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt) + */ + +/* Do not link this file! Link usbdrvasm.S instead, which includes the + * appropriate implementation! + */ + +/* +General Description: +This file is the 18 MHz version of the asssembler part of the USB driver. It +requires a 18 MHz crystal (not a ceramic resonator and not a calibrated RC +oscillator). + +See usbdrv.h for a description of the entire driver. + +Since almost all of this code is timing critical, don't change unless you +really know what you are doing! Many parts require not only a maximum number +of CPU cycles, but even an exact number of cycles! + +Note: This version is smaller than usbdrvasm18-crc.inc because it saves the CRC +table. It's therefore suitable for boot loaders on boards @ 18 MHz. However, it +is not as small as it could be, because loops are unrolled in the same way as in +usbdrvasm18-crc.inc. There is room for optimization. +*/ + + +;max stack usage: [ret(2), YL, SREG, YH, [sofError], bitcnt(x5), shift, x1, x2, x3, x4, cnt, ZL, ZH] = 14 bytes +;nominal frequency: 18 MHz -> 12 cycles per bit +; Numbers in brackets are clocks counted from center of last sync bit +; when instruction starts +;register use in receive loop to receive the data bytes: +; shift assembles the byte currently being received +; x1 holds the D+ and D- line state +; x2 holds the previous line state +; cnt holds the number of bytes left in the receive buffer +; x4 is used as temporary register +; x3 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further +; unstuffing calls. In the same time the corresponding bit in x3 is cleared to mark the bit as beening iverted +; zl lower crc value and crc table index +; zh used for crc table accesses + + + +macro POP_STANDARD ; 18 cycles + pop cnt + pop x5 + pop x3 + pop x2 + pop x1 + pop shift + pop x4 + endm +macro POP_RETI ; 7 cycles + pop YH + pop YL + out SREG, YL + pop YL + endm + +;macro CRC_CLEANUP_AND_CHECK +; ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor +; ; x3 is the higher crc byte, zl the lower one +; ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table +; lpm x2, Z ;[+2][+3][+4] +; ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table +; lpm ZL, Z ;[+6][+7][+8] +; eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value +; cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec) +; brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host +; cpi x2, 0xb0 ;[+10] +; brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host +; endm + + +USB_INTR_VECTOR: +;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH + push YL ;[-28] push only what is necessary to sync with edge ASAP + in YL, SREG ;[-26] + push YL ;[-25] + push YH ;[-23] +;---------------------------------------------------------------------------- +; Synchronize with sync pattern: +;---------------------------------------------------------------------------- +;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K] +;sync up with J to K edge during sync pattern -- use fastest possible loops +;The first part waits at most 1 bit long since we must be in sync pattern. +;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to +;waitForJ, ensure that this prerequisite is met. +waitForJ: + inc YL + sbis USBIN, USBMINUS + brne waitForJ ; just make sure we have ANY timeout +waitForK: +;The following code results in a sampling window of < 1/4 bit which meets the spec. + sbis USBIN, USBMINUS ;[-17] + rjmp foundK ;[-16] + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK + sbis USBIN, USBMINUS + rjmp foundK +#if USB_COUNT_SOF + lds YL, usbSofCount + inc YL + sts usbSofCount, YL +#endif /* USB_COUNT_SOF */ +#ifdef USB_SOF_HOOK + USB_SOF_HOOK +#endif + rjmp sofError +foundK: ;[-15] +;{3, 5} after falling D- edge, average delay: 4 cycles +;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample +;use 1 bit time for setup purposes, then sample again. Numbers in brackets +;are cycles from center of first sync (double K) bit after the instruction + push x4 ;[-14] +; [---] ;[-13] + lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers +; [---] ;[-11] + clr YH ;[-10] + subi YL, lo8(-(usbRxBuf));[-9] [rx loop init] + sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init] + push shift ;[-7] +; [---] ;[-6] + ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop + clc ;[-4] the carry has to be clear for receipt of pid bit 0 + sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early) + rjmp haveTwoBitsK ;[-2] + pop shift ;[-1] undo the push from before + pop x4 ;[1] + rjmp waitForK ;[3] this was not the end of sync, retry +; The entire loop from waitForK until rjmp waitForK above must not exceed two +; bit times (= 24 cycles). + +;---------------------------------------------------------------------------- +; push more registers and initialize values while we sample the first bits: +;---------------------------------------------------------------------------- +haveTwoBitsK: + push x1 ;[0] + push x2 ;[2] + push x3 ;[4] + ldi x2, 1< jump back and store the byte + ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + andi x3, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift) + eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[3] mask the interesting bits + breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[5] the next bit expects the last state to be in x1 + rjmp didunstuff0 ;[6] + ;[7] jump delay of rjmp didunstuffX + +unstuff1: ;[11] this is the jump delay of breq unstuffX + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing + andi x3, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift) + eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[4] mask the interesting bits + breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[6] the next bit expects the last state to be in x2 + nop2 ;[7] + ;[8] + rjmp didunstuff1 ;[9] + ;[10] jump delay of rjmp didunstuffX + +unstuff2: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing + andi x3, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift) + in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x1, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x1, x2 ;[4] the next bit expects the last state to be in x1 + nop2 ;[5] + ;[6] + rjmp didunstuff2 ;[7] + ;[8] jump delay of rjmp didunstuffX + +unstuff3: ;[9] this is the jump delay of breq unstuffX + ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing + andi x3, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift) + in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors + eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero + andi x2, USBMASK ;[2] mask the interesting bits + breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong + mov x2, x1 ;[4] the next bit expects the last state to be in x2 + nop2 ;[5] + ;[6] + rjmp didunstuff3 ;[7] + ;[8] jump delay of rjmp didunstuffX + + + +; the include has to be here due to branch distance restirctions +#include "asmcommon.inc" + + + +; USB spec says: +; idle = J +; J = (D+ = 0), (D- = 1) +; K = (D+ = 1), (D- = 0) +; Spec allows 7.5 bit times from EOP to SOP for replies +; 7.5 bit times is 90 cycles. ...there is plenty of time + + +sendNakAndReti: + ldi x3, USBPID_NAK ;[-18] + rjmp sendX3AndReti ;[-17] +sendAckAndReti: + ldi cnt, USBPID_ACK ;[-17] +sendCntAndReti: + mov x3, cnt ;[-16] +sendX3AndReti: + ldi YL, 20 ;[-15] x3==r20 address is 20 + ldi YH, 0 ;[-14] + ldi cnt, 2 ;[-13] +; rjmp usbSendAndReti fallthrough + +;usbSend: +;pointer to data in 'Y' +;number of bytes in 'cnt' -- including sync byte [range 2 ... 12] +;uses: x1...x4, btcnt, shift, cnt, Y +;Numbers in brackets are time since first bit of sync pattern is sent + +usbSendAndReti: ; 12 cycles until SOP + in x2, USBDDR ;[-12] + ori x2, USBMASK ;[-11] + sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups) + in x1, USBOUT ;[-8] port mirror for tx loop + out USBDDR, x2 ;[-6] <- acquire bus + ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0 + ldi x4, USBMASK ;[-5] exor mask + ldi shift, 0x80 ;[-4] sync byte is first byte sent +txByteLoop: + ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000 +txBitLoop: ; the loop sends the first 7 bits of the byte + sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state + eor x1, x4 ;[-1]=[11] + out USBOUT, x1 ;[0] + ror shift ;[1] + ror x2 ;[2] transfers the last sent bit to the stuffing history +didStuffN: + nop ;[3] + nop ;[4] + cpi x2, 0xfc ;[5] if we sent six consecutive ones + brcc bitstuffN ;[6] + lsr bitcnt ;[7] + brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount + +; transmit bit 7 + sbrs shift, 0 ;[9] + eor x1, x4 ;[10] +didStuff7: + ror shift ;[11] + out USBOUT, x1 ;[0] transfer bit 7 to the pins + ror x2 ;[1] move the bit into the stuffing history + cpi x2, 0xfc ;[2] + brcc bitstuff7 ;[3] + ld shift, y+ ;[4] get next byte to transmit + dec cnt ;[5] decrement byte counter + brne txByteLoop ;[7] if we have more bytes start next one + ;[8] branch delay + +;make SE0: + cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles] + lds x2, usbNewDeviceAddr;[9] + lsl x2 ;[11] we compare with left shifted address + out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle + subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3 + sbci YH, 0 ;[2] +;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm: +;set address only after data packet was sent, not after handshake + breq skipAddrAssign ;[3] + sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer +skipAddrAssign: +;end of usbDeviceAddress transfer + ldi x2, 1<