From 37fc27ac6bbc4dd269d941cc6fb3d48dfb0a3d35 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 3 Aug 2016 02:56:34 +0200 Subject: Adding STM32F439i-EVAL board files --- .../CubeHal/stm32f439i_raw32_ugfx.c | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_ugfx.c (limited to 'boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_ugfx.c') diff --git a/boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_ugfx.c b/boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_ugfx.c new file mode 100644 index 00000000..5251fbeb --- /dev/null +++ b/boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_ugfx.c @@ -0,0 +1,88 @@ +#include "../../../gfx.h" + +#undef Red +#undef Green +#undef Blue + +#include "stm32f4xx_hal.h" + +#if GFX_USE_OS_RAW32 + void _init() + { + } + + systemticks_t gfxSystemTicks(void) + { + return HAL_GetTick(); + } + + systemticks_t gfxMillisecondsToTicks(delaytime_t ms) + { + return ms; + } +#endif + +static void SystemClock_Config(void); + +void Raw32OSInit(void) +{ + HAL_Init(); + + SystemClock_Config(); +} + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (HSE) + * SYSCLK(Hz) = 180000000 + * HCLK(Hz) = 180000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 4 + * APB2 Prescaler = 2 + * HSE Frequency(Hz) = 25000000 + * PLL_M = 25 + * PLL_N = 360 + * PLL_P = 2 + * PLL_Q = 7 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 5 + * @param None + * @retval None + */ +static void SystemClock_Config(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable Power Control clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 360; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 7; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + HAL_PWREx_EnableOverDrive(); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); +} -- cgit v1.2.3