From 6dea259ea2dd0afc4b610961e211d77460cfd0c6 Mon Sep 17 00:00:00 2001 From: inmarket Date: Wed, 9 Jul 2014 18:47:59 +1000 Subject: Example added for FreeRTOS on Raspberry Pi --- .../example-FreeRTOS/Drivers/bcm2835_intc.h | 45 ++++++ .../RaspberryPi/example-FreeRTOS/Drivers/gpio.c | 134 +++++++++++++++++ .../RaspberryPi/example-FreeRTOS/Drivers/gpio.h | 48 ++++++ .../example-FreeRTOS/Drivers/interrupts.c | 166 +++++++++++++++++++++ .../example-FreeRTOS/Drivers/interrupts.h | 25 ++++ .../RaspberryPi/example-FreeRTOS/Drivers/mmio.h | 24 +++ .../RaspberryPi/example-FreeRTOS/Drivers/uart.c | 125 ++++++++++++++++ .../RaspberryPi/example-FreeRTOS/Drivers/uart.h | 25 ++++ 8 files changed, 592 insertions(+) create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/bcm2835_intc.h create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.c create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.h create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.c create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.h create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/mmio.h create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.c create mode 100644 boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.h (limited to 'boards/base/RaspberryPi/example-FreeRTOS/Drivers') diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/bcm2835_intc.h b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/bcm2835_intc.h new file mode 100644 index 00000000..9f87b88e --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/bcm2835_intc.h @@ -0,0 +1,45 @@ +#ifndef _BCM2835_INTC_H_ +#define _BCM2835_INTC_H_ + +//#include "bcm2835.h" + +#define BCM2835_INTC_TOTAL_IRQ 64 + 8 + +#define BCM2835_BASE_INTC (0x2000B200) +#define BCM2835_INTC_IRQ_BASIC (BCM2835_BASE_INTC + 0x00) +#define BCM2835_IRQ_PENDING1 (BCM2835_BASE_INTC + 0x04) +#define BCM2835_IRQ_PENDING2 (BCM2835_BASE_INTC + 0x08) +#define BCM2835_IRQ_FIQ_CTRL (BCM2835_BASE_INTC + 0x0C) +#define BCM2835_IRQ_ENABLE1 (BCM2835_BASE_INTC + 0x10) +#define BCM2835_IRQ_ENABLE2 (BCM2835_BASE_INTC + 0x14) +#define BCM2835_IRQ_ENABLE_BASIC (BCM2835_BASE_INTC + 0x18) +#define BCM2835_IRQ_DISABLE1 (BCM2835_BASE_INTC + 0x1C) +#define BCM2835_IRQ_DISABLE2 (BCM2835_BASE_INTC + 0x20) +#define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24) + + + + +#define BCM2835_IRQ_ID_AUX 29 +#define BCM2835_IRQ_ID_SPI_SLAVE 43 +#define BCM2835_IRQ_ID_PWA0 45 +#define BCM2835_IRQ_ID_PWA1 46 +#define BCM2835_IRQ_ID_SMI 48 +#define BCM2835_IRQ_ID_GPIO_0 49 +#define BCM2835_IRQ_ID_GPIO_1 50 +#define BCM2835_IRQ_ID_GPIO_2 51 +#define BCM2835_IRQ_ID_GPIO_3 52 +#define BCM2835_IRQ_ID_I2C 53 +#define BCM2835_IRQ_ID_SPI 54 +#define BCM2835_IRQ_ID_PCM 55 +#define BCM2835_IRQ_ID_UART 57 + + +#define BCM2835_IRQ_ID_TIMER_0 64 +#define BCM2835_IRQ_ID_MAILBOX_0 65 +#define BCM2835_IRQ_ID_DOORBELL_0 66 +#define BCM2835_IRQ_ID_DOORBELL_1 67 +#define BCM2835_IRQ_ID_GPU0_HALTED 68 + + +#endif diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.c b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.c new file mode 100644 index 00000000..485de897 --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.c @@ -0,0 +1,134 @@ +/** + * Quick and very Dirty GPIO API. + * + **/ + +#include "gpio.h" + +typedef struct { + unsigned long GPFSEL[6]; ///< Function selection registers. + unsigned long Reserved_1; + unsigned long GPSET[2]; + unsigned long Reserved_2; + unsigned long GPCLR[2]; + unsigned long Reserved_3; + unsigned long GPLEV[2]; + unsigned long Reserved_4; + unsigned long GPEDS[2]; + unsigned long Reserved_5; + unsigned long GPREN[2]; + unsigned long Reserved_6; + unsigned long GPFEN[2]; + unsigned long Reserved_7; + unsigned long GPHEN[2]; + unsigned long Reserved_8; + unsigned long GPLEN[2]; + unsigned long Reserved_9; + unsigned long GPAREN[2]; + unsigned long Reserved_A; + unsigned long GPAFEN[2]; + unsigned long Reserved_B; + unsigned long GPPUD[1]; + unsigned long GPPUDCLK[2]; + //Ignoring the reserved and test bytes +} BCM2835_GPIO_REGS; + +volatile BCM2835_GPIO_REGS * const pRegs = (BCM2835_GPIO_REGS *) (0x20200000); + + +void SetGpioFunction(unsigned int pinNum, unsigned int funcNum) { + + int offset = pinNum / 10; + + unsigned long val = pRegs->GPFSEL[offset]; // Read in the original register value. + + int item = pinNum % 10; + val &= ~(0x7 << (item * 3)); + val |= ((funcNum & 0x7) << (item * 3)); + pRegs->GPFSEL[offset] = val; +} + +void SetGpioDirection(unsigned int pinNum, enum GPIO_DIR dir) { + SetGpioFunction(pinNum,dir); +} + +void SetGpio(unsigned int pinNum, unsigned int pinVal) { + unsigned long offset=pinNum/32; + unsigned long mask=(1<<(pinNum%32)); + + if(pinVal) { + pRegs->GPSET[offset]|=mask; + } else { + pRegs->GPCLR[offset]|=mask; + } +} + +int ReadGpio(unsigned int pinNum) { + return ((pRegs->GPLEV[pinNum/32])>>(pinNum%32))&1; +} + +void EnableGpioDetect(unsigned int pinNum, enum DETECT_TYPE type) +{ + unsigned long mask=(1<GPREN[offset]|=mask; + break; + case DETECT_FALLING: + pRegs->GPFEN[offset]|=mask; + break; + case DETECT_HIGH: + pRegs->GPHEN[offset]|=mask; + break; + case DETECT_LOW: + pRegs->GPLEN[offset]|=mask; + break; + case DETECT_RISING_ASYNC: + pRegs->GPAREN[offset]|=mask; + break; + case DETECT_FALLING_ASYNC: + pRegs->GPAFEN[offset]|=mask; + break; + case DETECT_NONE: + break; + } +} + +void DisableGpioDetect(unsigned int pinNum, enum DETECT_TYPE type) +{ + unsigned long mask=~(1<<(pinNum%32)); + unsigned long offset=pinNum/32; + + switch(type) { + case DETECT_RISING: + pRegs->GPREN[offset]&=mask; + break; + case DETECT_FALLING: + pRegs->GPFEN[offset]&=mask; + break; + case DETECT_HIGH: + pRegs->GPHEN[offset]&=mask; + break; + case DETECT_LOW: + pRegs->GPLEN[offset]&=mask; + break; + case DETECT_RISING_ASYNC: + pRegs->GPAREN[offset]&=mask; + break; + case DETECT_FALLING_ASYNC: + pRegs->GPAFEN[offset]&=mask; + break; + case DETECT_NONE: + break; + } +} + +void ClearGpioInterrupt(unsigned int pinNum) +{ + unsigned long mask=(1<<(pinNum%32)); + unsigned long offset=pinNum/32; + + pRegs->GPEDS[offset]=mask; +} diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.h b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.h new file mode 100644 index 00000000..fa459707 --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/gpio.h @@ -0,0 +1,48 @@ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +/* GPIO event detect types */ +enum DETECT_TYPE { + DETECT_NONE, + DETECT_RISING, + DETECT_FALLING, + DETECT_HIGH, + DETECT_LOW, + DETECT_RISING_ASYNC, + DETECT_FALLING_ASYNC +}; + +/* GPIO pull up or down states */ +enum PULL_STATE { + PULL_DISABLE, + PULL_UP, + PULL_DOWN, + PULL_RESERVED +}; + +/* Pin data direction */ +enum GPIO_DIR { + GPIO_IN, + GPIO_OUT +}; + +/* GPIO pin setup */ +void SetGpioFunction (unsigned int pinNum, unsigned int funcNum); +/* A simple wrapper around SetGpioFunction */ +void SetGpioDirection (unsigned int pinNum, enum GPIO_DIR dir); + +/* Set GPIO output level */ +void SetGpio (unsigned int pinNum, unsigned int pinVal); + +/* Read GPIO pin level */ +int ReadGpio (unsigned int pinNum); + +/* GPIO pull up/down resistor control function (NOT YET IMPLEMENTED) */ +int PudGpio (unsigned int pinNum, enum PULL_STATE state); + +/* Interrupt related functions */ +void EnableGpioDetect (unsigned int pinNum, enum DETECT_TYPE type); +void DisableGpioDetect (unsigned int pinNum, enum DETECT_TYPE type); +void ClearGpioInterrupt (unsigned int pinNum); + +#endif diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.c b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.c new file mode 100644 index 00000000..9908b7c4 --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.c @@ -0,0 +1,166 @@ +/** + * Integrated Interrupt Controller for RaspberryPi. + * @author James Walmsley + **/ + +#include "interrupts.h" +#include "bcm2835_intc.h" + +static INTERRUPT_VECTOR g_VectorTable[BCM2835_INTC_TOTAL_IRQ]; + + +typedef struct { + unsigned long IRQBasic; // Pending 0 + unsigned long Pending1; + unsigned long Pending2; + unsigned long FIQCtrl; + unsigned long Enable1; + unsigned long Enable2; + unsigned long EnableBasic; + unsigned long Disable1; + unsigned long Disable2; + unsigned long DisableBasic; +} BCM2835_INTC_REGS; + +static volatile BCM2835_INTC_REGS * const pRegs = (BCM2835_INTC_REGS *) (BCM2835_BASE_INTC); + +/** + * Enables all IRQ's in the CPU's CPSR register. + **/ +static void irqEnable() { + __asm volatile("mrs r0,cpsr"); // Read in the cpsr register. + __asm volatile("bic r0,r0,#0x80"); // Clear bit 8, (0x80) -- Causes IRQs to be enabled. + __asm volatile("msr cpsr_c, r0"); // Write it back to the CPSR register +} + +static void irqDisable() { + __asm volatile("mrs r0,cpsr"); // Read in the cpsr register. + __asm volatile("orr r0,r0,#0x80"); // Set bit 8, (0x80) -- Causes IRQs to be disabled. + __asm volatile("msr cpsr_c, r0"); // Write it back to the CPSR register. + +} + +#define clz(a) \ + ({ unsigned long __value, __arg = (a); \ + asm ("clz\t%0, %1": "=r" (__value): "r" (__arg)); \ + __value; }) + +/** + * This is the global IRQ handler on this platform! + * It is based on the assembler code found in the Broadcom datasheet. + * + **/ +void irqHandler() { + register unsigned long ulMaskedStatus; + register unsigned long irqNumber; + + ulMaskedStatus = pRegs->IRQBasic; + + /* Bits 7 through 0 in IRQBasic represent interrupts 64-71 */ + if (ulMaskedStatus & 0xFF) { + irqNumber=64 + 31; + } + + /* Bit 8 in IRQBasic indicates interrupts in Pending1 (interrupts 31-0) */ + else if(ulMaskedStatus & 0x100) { + ulMaskedStatus = pRegs->Pending1; + irqNumber = 0 + 31; + } + + /* Bit 9 in IRQBasic indicates interrupts in Pending2 (interrupts 63-32) */ + else if(ulMaskedStatus & 0x200) { + ulMaskedStatus = pRegs->Pending2; + irqNumber = 32 + 31; + } + + else { + // No interrupt avaialbe, so just return. + return; + } + + /* Keep only least significant bit, in case multiple interrupts have occured */ + ulMaskedStatus&=-ulMaskedStatus; + /* Some magic to determine number of interrupt to serve */ + irqNumber=irqNumber-clz(ulMaskedStatus); + /* Call interrupt handler */ + g_VectorTable[irqNumber].pfnHandler(irqNumber, g_VectorTable[irqNumber].pParam); +} + + +static void stubHandler(int nIRQ, void *pParam) { + /** + * Actually if we get here, we should probably disable the IRQ, + * otherwise we could lock up this system, as there is nothing to + * ackknowledge the interrupt. + **/ +} + +int InitInterruptController() { + int i; + for(i = 0; i < BCM2835_INTC_TOTAL_IRQ; i++) { + g_VectorTable[i].pfnHandler = stubHandler; + g_VectorTable[i].pParam = (void *) 0; + } + return 0; +} + + + +int RegisterInterrupt(int nIRQ, FN_INTERRUPT_HANDLER pfnHandler, void *pParam) { + if(nIRQ<0 || nIRQ>71) + return -1; + + irqDisable(); + { + g_VectorTable[nIRQ].pfnHandler = pfnHandler; + g_VectorTable[nIRQ].pParam = pParam; + } + irqEnable(); + return 0; +} + +int EnableInterrupt(int nIRQ) { + /* Datasheet says "All other bits are unaffected", and I'm counting on that. */ + unsigned int mask=1<<(nIRQ%32); + + if(nIRQ >=0 && nIRQ <=31) { + pRegs->Enable1 = mask; + } else + if(nIRQ >=32 && nIRQ <=63){ + pRegs->Enable2 = mask; + } else + if(nIRQ >= 64 && nIRQ <= 71) { // Basic IRQ enables + pRegs->EnableBasic = mask; + } else + return -1; + + return 0; +} + +int DisableInterrupt(int nIRQ) { + /* Datasheet says "All other bits are unaffected", and I'm counting on that. */ + unsigned int mask=1<<(nIRQ%32); + + if(nIRQ >=0 && nIRQ <=31) { + pRegs->Disable1 = mask; + } else + if(nIRQ >=32 && nIRQ <=63){ + pRegs->Disable2 = mask; + } else + if(nIRQ >= 64 && nIRQ <= 71) { + pRegs->DisableBasic = mask; + } else + return -1; + + return 0; +} + +int EnableInterrupts() { + irqEnable(); + return 0; +} + +int DisableInterrupts() { + irqDisable(); + return 0; +} diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.h b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.h new file mode 100644 index 00000000..d09353a4 --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/interrupts.h @@ -0,0 +1,25 @@ +/** + * Tiny Interrupt Manager + * + * @author James Walmsley + * This code is licensed under the GNU GPLv3 license. + **/ + +#ifndef _INTERRUPTS_H_ +#define _INTERRUPTS_H_ + +typedef void (*FN_INTERRUPT_HANDLER)(int nIRQ, void *pParam); + +typedef struct { + FN_INTERRUPT_HANDLER pfnHandler; ///< Function that handles this IRQn + void *pParam; ///< A special parameter that the use can pass to the IRQ. +} INTERRUPT_VECTOR; + +int InitInterruptController (); +int RegisterInterrupt (int nIRQ, FN_INTERRUPT_HANDLER pfnHandler, void *pParam); +int EnableInterrupt (int nIRQ); +int DisableInterrupt (int nIRQ); +int EnableInterrupts (); +int DisableInterrupts (); + +#endif diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/mmio.h b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/mmio.h new file mode 100644 index 00000000..89bea700 --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/mmio.h @@ -0,0 +1,24 @@ +/* mmio.h - access to MMIO registers */ + +#ifndef MMIO_H +#define MMIO_H + +#include + +// write to MMIO register +static inline void mmio_write(uint32_t reg, uint32_t data) { + uint32_t *ptr = (uint32_t*)reg; + asm volatile("str %[data], [%[reg]]" + : : [reg]"r"(ptr), [data]"r"(data)); +} + +// read from MMIO register +static inline uint32_t mmio_read(uint32_t reg) { + uint32_t *ptr = (uint32_t*)reg; + uint32_t data; + asm volatile("ldr %[data], [%[reg]]" + : [data]"=r"(data) : [reg]"r"(ptr)); + return data; +} + +#endif // #ifndef MMIO_H diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.c b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.c new file mode 100644 index 00000000..92f837e7 --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.c @@ -0,0 +1,125 @@ +/* uart.c - UART initialization & communication */ +/* Reference material: + * http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf + * Chapter 13: UART + */ + +#include +#include +#include + +enum { + // The GPIO registers base address. + GPIO_BASE = 0x20200000, + + // The offsets for reach register. + + // Controls actuation of pull up/down to ALL GPIO pins. + GPPUD = (GPIO_BASE + 0x94), + + // Controls actuation of pull up/down for specific GPIO pin. + GPPUDCLK0 = (GPIO_BASE + 0x98), + + // The base address for UART. + UART0_BASE = 0x20201000, + + // The offsets for reach register for the UART. + UART0_DR = (UART0_BASE + 0x00), + UART0_RSRECR = (UART0_BASE + 0x04), + UART0_FR = (UART0_BASE + 0x18), + UART0_ILPR = (UART0_BASE + 0x20), + UART0_IBRD = (UART0_BASE + 0x24), + UART0_FBRD = (UART0_BASE + 0x28), + UART0_LCRH = (UART0_BASE + 0x2C), + UART0_CR = (UART0_BASE + 0x30), + UART0_IFLS = (UART0_BASE + 0x34), + UART0_IMSC = (UART0_BASE + 0x38), + UART0_RIS = (UART0_BASE + 0x3C), + UART0_MIS = (UART0_BASE + 0x40), + UART0_ICR = (UART0_BASE + 0x44), + UART0_DMACR = (UART0_BASE + 0x48), + UART0_ITCR = (UART0_BASE + 0x80), + UART0_ITIP = (UART0_BASE + 0x84), + UART0_ITOP = (UART0_BASE + 0x88), + UART0_TDR = (UART0_BASE + 0x8C), +}; + +/* + * delay function + * int32_t delay: number of cycles to delay + * + * This just loops times in a way that the compiler + * wont optimize away. + */ +static void delay(int32_t count) { + asm volatile("__delay_%=: subs %[count], %[count], #1; bne __delay_%=\n" + : : [count]"r"(count) : "cc"); +} + +/* + * Initialize UART0. + */ +void uart_init() { + // Disable UART0. + mmio_write(UART0_CR, 0x00000000); + // Setup the GPIO pin 14 && 15. + + // Disable pull up/down for all GPIO pins & delay for 150 cycles. + mmio_write(GPPUD, 0x00000000); + delay(150); + + // Disable pull up/down for pin 14,15 & delay for 150 cycles. + mmio_write(GPPUDCLK0, (1 << 14) | (1 << 15)); + delay(150); + + // Write 0 to GPPUDCLK0 to make it take effect. + mmio_write(GPPUDCLK0, 0x00000000); + + // Clear pending interrupts. + mmio_write(UART0_ICR, 0x7FF); + + // Set integer & fractional part of baud rate. + // Divider = UART_CLOCK/(16 * Baud) + // Fraction part register = (Fractional part * 64) + 0.5 + // UART_CLOCK = 3000000; Baud = 115200. + + // Divider = 3000000/(16 * 115200) = 1.627 = ~1. + // Fractional part register = (.627 * 64) + 0.5 = 40.6 = ~40. + mmio_write(UART0_IBRD, 1); + mmio_write(UART0_FBRD, 40); + + // Enable FIFO & 8 bit data transmissio (1 stop bit, no parity). + mmio_write(UART0_LCRH, (1 << 4) | (1 << 5) | (1 << 6)); + + // Mask all interrupts. + mmio_write(UART0_IMSC, (1 << 1) | (1 << 4) | (1 << 5) | + (1 << 6) | (1 << 7) | (1 << 8) | + (1 << 9) | (1 << 10)); + + // Enable UART0, receive & transfer part of UART. + mmio_write(UART0_CR, (1 << 0) | (1 << 8) | (1 << 9)); +} + +/* + * Transmit a byte via UART0. + * uint8_t Byte: byte to send. + */ +void uart_putc(uint8_t byte) { + // wait for UART to become ready to transmit + while (1) { + if (!(mmio_read(UART0_FR) & (1 << 5))) { + break; + } + } + mmio_write(UART0_DR, byte); +} + +/* + * print a string to the UART one character at a time + * const char *str: 0-terminated string + */ +void uart_puts(const char *str) { + while (*str) { + uart_putc(*str++); + } +} diff --git a/boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.h b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.h new file mode 100644 index 00000000..fe7f64aa --- /dev/null +++ b/boards/base/RaspberryPi/example-FreeRTOS/Drivers/uart.h @@ -0,0 +1,25 @@ +/* uart.h - UART initialization & communication */ + +#ifndef UART_H +#define UART_H + +#include + +/* + * Initialize UART0. + */ +void uart_init(); + +/* + * Transmit a byte via UART0. + * uint8_t Byte: byte to send. + */ +void uart_putc(uint8_t byte); + +/* + * print a string to the UART one character at a time + * const char *str: 0-terminated string + */ +void uart_puts(const char *str); + +#endif // #ifndef UART_H -- cgit v1.2.3