From 682503e672d5397da22ad2ecf9a8c08915e062be Mon Sep 17 00:00:00 2001
From: inmarket <andrewh@inmarket.com.au>
Date: Tue, 18 Aug 2015 07:39:33 +1000
Subject: Another fix to gdriver
---
src/gdriver/gdriver.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/gdriver/gdriver.c b/src/gdriver/gdriver.c
index c90ad8e3..116abd32 100644
--- a/src/gdriver/gdriver.c
+++ b/src/gdriver/gdriver.c
@@ -52,13 +52,12 @@ GDriver *gdriverRegister(const GDriverVMT *vmt, void *param) {
return 0;
}
- // Add it to the driver chain
- if (dhead) {
+ // Add it to the driver chain (at the end)
+ if (dhead)
dtail->driverchain = pd;
- dtail = pd;
- } else {
- dhead = dtail = pd;
- }
+ else
+ dhead = pd;
+ dtail = pd;
// Do the post init
if (vmt->postinit)
@@ -81,6 +80,8 @@ void gdriverUnRegister(GDriver *driver) {
for(pd = dhead; pd->driverchain; pd = pd->driverchain) {
if (pd->driverchain == driver) {
pd->driverchain = driver->driverchain;
+ if (!pd->driverchain)
+ dtail = pd;
break;
}
}
--
cgit v1.2.3
From 3f7ded913d87dc9cbbbd99ccc5ec9c11fd775aa5 Mon Sep 17 00:00:00 2001
From: Joel Bodenmann <joel@seriouslyembedded.com>
Date: Mon, 10 Aug 2015 18:54:53 +0200
Subject: Fixing include
---
src/ginput/ginput_keyboard_microcode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/ginput/ginput_keyboard_microcode.c b/src/ginput/ginput_keyboard_microcode.c
index 167ed5a4..9db0459b 100644
--- a/src/ginput/ginput_keyboard_microcode.c
+++ b/src/ginput/ginput_keyboard_microcode.c
@@ -14,7 +14,7 @@
#if GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD && !GKEYBOARD_LAYOUT_OFF
-#include "keyboard_microcode.h"
+#include "ginput_keyboard_microcode.h"
#if GKEYBOARD_LAYOUT_SCANCODE2_US
--
cgit v1.2.3
From 4c6e2433a5d7e72e037322d2e521da4d846f1aef Mon Sep 17 00:00:00 2001
From: Joel Bodenmann <joel@seriouslyembedded.com>
Date: Sat, 29 Aug 2015 16:35:34 +0200
Subject: Updating ChibiOS 3.x build system support
---
boards/base/Embest-STM32-DMSTF4BB/board.mk | 3 +-
.../Embest-STM32-DMSTF4BB/chibios_board/board.c | 108 --
.../Embest-STM32-DMSTF4BB/chibios_board/board.h | 1297 --------------------
.../Embest-STM32-DMSTF4BB/chibios_board/board.mk | 3 -
.../chibios_board/cfg/board.chcfg | 1186 ------------------
.../example_chibios_2.x/Makefile | 11 +-
.../example_chibios_2.x/board.c | 108 ++
.../example_chibios_2.x/board.h | 1297 ++++++++++++++++++++
.../example_chibios_3.x/Makefile | 60 +
.../example_chibios_3.x/chconf.h | 498 ++++++++
.../example_chibios_3.x/halconf.h | 327 +++++
.../example_chibios_3.x/mcuconf.h | 321 +++++
.../example_chibios_3.x/openocd.cfg | 81 ++
.../example_chibios_3.x/Makefile | 20 +-
.../example_chibios_3.x/chconf.h | 11 +-
.../example_chibios_3.x/halconf.h | 13 +-
.../example_chibios_3.x/mcuconf.h | 45 +-
tools/gmake_scripts/os_chibios.mk | 73 +-
tools/gmake_scripts/os_chibios_2.mk | 72 ++
tools/gmake_scripts/os_chibios_3.mk | 84 ++
20 files changed, 2908 insertions(+), 2710 deletions(-)
delete mode 100644 boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.c
delete mode 100644 boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.h
delete mode 100644 boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.mk
delete mode 100644 boards/base/Embest-STM32-DMSTF4BB/chibios_board/cfg/board.chcfg
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.c
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.h
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/chconf.h
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/halconf.h
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/mcuconf.h
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/openocd.cfg
create mode 100644 tools/gmake_scripts/os_chibios_2.mk
create mode 100644 tools/gmake_scripts/os_chibios_3.mk
diff --git a/boards/base/Embest-STM32-DMSTF4BB/board.mk b/boards/base/Embest-STM32-DMSTF4BB/board.mk
index 9deacc08..09bfaadf 100644
--- a/boards/base/Embest-STM32-DMSTF4BB/board.mk
+++ b/boards/base/Embest-STM32-DMSTF4BB/board.mk
@@ -1,8 +1,7 @@
GFXINC += $(GFXLIB)/boards/base/Embest-STM32-DMSTF4BB
GFXSRC +=
-GFXDEFS += -DGFX_USE_CHIBIOS=TRUE
+GFXDEFS += -DGFX_USE_CHIBIOS=FALSE
-include $(GFXLIB)/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.mk
include $(GFXLIB)/drivers/gdisp/SSD2119/driver.mk
include $(GFXLIB)/drivers/ginput/touch/STMPE811/driver.mk
diff --git a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.c b/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.c
deleted file mode 100644
index c892481a..00000000
--- a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
- VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
- {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
- VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
- {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
- VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
- {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
- VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
- {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
- VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
- {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
- {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
- VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
- {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
- {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- stm32_clock_init();
-}
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-/**
- * @brief SDC card detection.
- */
-bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
-
- (void)sdcp;
-
- return !palReadPad(GPIOB, GPIOB_SD_DETECT);
-}
-
-/**
- * @brief SDC card write protection detection.
- */
-bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
-
- (void)sdcp;
-
- return FALSE;
-}
-#endif /* HAL_USE_SDC */
-
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
-/**
- * @brief MMC_SPI card detection.
- */
-bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
-
- (void)mmcp;
-
- return !palReadPad(GPIOB, GPIOB_SD_DETECT);
-}
-
-/**
- * @brief MMC_SPI card write protection detection.
- */
-bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
-
- (void)mmcp;
-
- return FALSE;
-}
-#endif
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
diff --git a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.h b/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.h
deleted file mode 100644
index 599281ba..00000000
--- a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.h
+++ /dev/null
@@ -1,1297 +0,0 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for STMicroelectronics STM32F4-Discovery board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_EMBEST_DMSTF4BB
-#define BOARD_NAME "STMicroelectronics STM32F4-Discovery with Embest add-on"
-
-
-/*
- * Board oscillators-related settings.
- * NOTE: LSE not fitted.
- */
-#if !defined(STM32_LSECLK)
-#define STM32_LSECLK 32768
-#endif
-
-#if !defined(STM32_HSECLK)
-#define STM32_HSECLK 8000000
-#endif
-
-
-/*
- * Board voltages.
- * Required for performance limits calculation.
- */
-#define STM32_VDD 300
-
-/*
- * MCU type as defined in the ST header file stm32f4xx.h.
- */
-#define STM32F40_41xxx
-
-/*
- * IO pins assignments.
- */
-#define GPIOA_BUTTON 0
-#define GPIOA_PIN1 1
-#define GPIOA_PIN2 2
-#define GPIOA_PIN3 3
-#define GPIOA_LRCK 4
-#define GPIOA_SPC 5
-#define GPIOA_SDO 6
-#define GPIOA_SDI 7
-#define GPIOA_PIN8 8
-#define GPIOA_VBUS_FS 9
-#define GPIOA_OTG_FS_ID 10
-#define GPIOA_OTG_FS_DM 11
-#define GPIOA_OTG_FS_DP 12
-#define GPIOA_SWDIO 13
-#define GPIOA_SWCLK 14
-#define GPIOA_PIN15 15
-
-#define GPIOB_PIN0 0
-#define GPIOB_PIN1 1
-#define GPIOB_PIN2 2
-#define GPIOB_SWO 3
-#define GPIOB_PIN4 4
-#define GPIOB_PIN5 5
-#define GPIOB_SCL 6
-#define GPIOB_PIN7 7
-#define GPIOB_PIN8 8
-#define GPIOB_SDA 9
-#define GPIOB_CLK_IN 10
-#define GPIOB_PIN11 11
-#define GPIOB_PIN12 12
-#define GPIOB_PIN13 13
-#define GPIOB_PIN14 14
-#define GPIOB_SD_DETECT 15
-
-#define GPIOC_OTG_FS_POWER_ON 0
-#define GPIOC_PIN1 1
-#define GPIOC_PIN2 2
-#define GPIOC_PDM_OUT 3
-#define GPIOC_PIN4 4
-#define GPIOC_PIN5 5
-#define GPIOC_PIN6 6
-#define GPIOC_MCLK 7
-#define GPIOC_SD_D0 8
-#define GPIOC_SD_D1 9
-#define GPIOC_SD_D2 10
-#define GPIOC_SD_D3 11
-#define GPIOC_SD_CLK 12
-#define GPIOC_PIN13 13
-#define GPIOC_PIN14 14
-#define GPIOC_PIN15 15
-
-#define GPIOD_PIN0 0
-#define GPIOD_PIN1 1
-#define GPIOD_SD_CMD 2
-#define GPIOD_PIN3 3
-#define GPIOD_RESET 4
-#define GPIOD_OVER_CURRENT 5
-#define GPIOD_PIN6 6
-#define GPIOD_PIN7 7
-#define GPIOD_PIN8 8
-#define GPIOD_PIN9 9
-#define GPIOD_PIN10 10
-#define GPIOD_PIN11 11
-#define GPIOD_LED4 12
-#define GPIOD_LED3 13
-#define GPIOD_LED5 14
-#define GPIOD_LED6 15
-
-#define GPIOE_INT1 0
-#define GPIOE_INT2 1
-#define GPIOE_PIN2 2
-#define GPIOE_CS_SPI 3
-#define GPIOE_PIN4 4
-#define GPIOE_PIN5 5
-#define GPIOE_PIN6 6
-#define GPIOE_PIN7 7
-#define GPIOE_PIN8 8
-#define GPIOE_PIN9 9
-#define GPIOE_PIN10 10
-#define GPIOE_PIN11 11
-#define GPIOE_PIN12 12
-#define GPIOE_PIN13 13
-#define GPIOE_PIN14 14
-#define GPIOE_PIN15 15
-
-#define GPIOF_PIN0 0
-#define GPIOF_PIN1 1
-#define GPIOF_PIN2 2
-#define GPIOF_PIN3 3
-#define GPIOF_PIN4 4
-#define GPIOF_PIN5 5
-#define GPIOF_PIN6 6
-#define GPIOF_PIN7 7
-#define GPIOF_PIN8 8
-#define GPIOF_PIN9 9
-#define GPIOF_PIN10 10
-#define GPIOF_PIN11 11
-#define GPIOF_PIN12 12
-#define GPIOF_PIN13 13
-#define GPIOF_PIN14 14
-#define GPIOF_PIN15 15
-
-#define GPIOG_PIN0 0
-#define GPIOG_PIN1 1
-#define GPIOG_PIN2 2
-#define GPIOG_PIN3 3
-#define GPIOG_PIN4 4
-#define GPIOG_PIN5 5
-#define GPIOG_PIN6 6
-#define GPIOG_PIN7 7
-#define GPIOG_PIN8 8
-#define GPIOG_PIN9 9
-#define GPIOG_PIN10 10
-#define GPIOG_PIN11 11
-#define GPIOG_PIN12 12
-#define GPIOG_PIN13 13
-#define GPIOG_PIN14 14
-#define GPIOG_PIN15 15
-
-#define GPIOH_OSC_IN 0
-#define GPIOH_OSC_OUT 1
-#define GPIOH_PIN2 2
-#define GPIOH_PIN3 3
-#define GPIOH_PIN4 4
-#define GPIOH_PIN5 5
-#define GPIOH_PIN6 6
-#define GPIOH_PIN7 7
-#define GPIOH_PIN8 8
-#define GPIOH_PIN9 9
-#define GPIOH_PIN10 10
-#define GPIOH_PIN11 11
-#define GPIOH_PIN12 12
-#define GPIOH_PIN13 13
-#define GPIOH_PIN14 14
-#define GPIOH_PIN15 15
-
-#define GPIOI_PIN0 0
-#define GPIOI_PIN1 1
-#define GPIOI_PIN2 2
-#define GPIOI_PIN3 3
-#define GPIOI_PIN4 4
-#define GPIOI_PIN5 5
-#define GPIOI_PIN6 6
-#define GPIOI_PIN7 7
-#define GPIOI_PIN8 8
-#define GPIOI_PIN9 9
-#define GPIOI_PIN10 10
-#define GPIOI_PIN11 11
-#define GPIOI_PIN12 12
-#define GPIOI_PIN13 13
-#define GPIOI_PIN14 14
-#define GPIOI_PIN15 15
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- * Please refer to the STM32 Reference Manual for details.
- */
-#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
-#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
-#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
-#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
-#define PIN_ODR_LOW(n) (0U << (n))
-#define PIN_ODR_HIGH(n) (1U << (n))
-#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
-#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
-#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
-#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
-#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
-#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
-#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
-#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
-#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
-#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
-
-/*
- * GPIOA setup:
- *
- * PA0 - BUTTON (input floating).
- * PA1 - PIN1 (input pullup).
- * PA2 - PIN2 (input pullup).
- * PA3 - PIN3 (input pullup).
- * PA4 - LRCK (alternate 6).
- * PA5 - SPC (alternate 5).
- * PA6 - SDO (alternate 5).
- * PA7 - SDI (alternate 5).
- * PA8 - PIN8 (input pullup).
- * PA9 - VBUS_FS (input floating).
- * PA10 - OTG_FS_ID (alternate 10).
- * PA11 - OTG_FS_DM (alternate 10).
- * PA12 - OTG_FS_DP (alternate 10).
- * PA13 - SWDIO (alternate 0).
- * PA14 - SWCLK (alternate 0).
- * PA15 - PIN15 (input pullup).
- */
-#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
- PIN_MODE_INPUT(GPIOA_PIN1) | \
- PIN_MODE_INPUT(GPIOA_PIN2) | \
- PIN_MODE_INPUT(GPIOA_PIN3) | \
- PIN_MODE_ALTERNATE(GPIOA_LRCK) | \
- PIN_MODE_ALTERNATE(GPIOA_SPC) | \
- PIN_MODE_ALTERNATE(GPIOA_SDO) | \
- PIN_MODE_ALTERNATE(GPIOA_SDI) | \
- PIN_MODE_INPUT(GPIOA_PIN8) | \
- PIN_MODE_INPUT(GPIOA_VBUS_FS) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
- PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
- PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
- PIN_MODE_INPUT(GPIOA_PIN15))
-#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
-#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \
- PIN_OSPEED_100M(GPIOA_PIN1) | \
- PIN_OSPEED_100M(GPIOA_PIN2) | \
- PIN_OSPEED_100M(GPIOA_PIN3) | \
- PIN_OSPEED_100M(GPIOA_LRCK) | \
- PIN_OSPEED_50M(GPIOA_SPC) | \
- PIN_OSPEED_50M(GPIOA_SDO) | \
- PIN_OSPEED_50M(GPIOA_SDI) | \
- PIN_OSPEED_100M(GPIOA_PIN8) | \
- PIN_OSPEED_100M(GPIOA_VBUS_FS) | \
- PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \
- PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
- PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
- PIN_OSPEED_100M(GPIOA_SWDIO) | \
- PIN_OSPEED_100M(GPIOA_SWCLK) | \
- PIN_OSPEED_100M(GPIOA_PIN15))
-#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOA_LRCK) | \
- PIN_PUPDR_FLOATING(GPIOA_SPC) | \
- PIN_PUPDR_FLOATING(GPIOA_SDO) | \
- PIN_PUPDR_FLOATING(GPIOA_SDI) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
- PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
- PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN15))
-#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
- PIN_ODR_HIGH(GPIOA_PIN1) | \
- PIN_ODR_HIGH(GPIOA_PIN2) | \
- PIN_ODR_HIGH(GPIOA_PIN3) | \
- PIN_ODR_HIGH(GPIOA_LRCK) | \
- PIN_ODR_HIGH(GPIOA_SPC) | \
- PIN_ODR_HIGH(GPIOA_SDO) | \
- PIN_ODR_HIGH(GPIOA_SDI) | \
- PIN_ODR_HIGH(GPIOA_PIN8) | \
- PIN_ODR_HIGH(GPIOA_VBUS_FS) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
- PIN_ODR_HIGH(GPIOA_SWDIO) | \
- PIN_ODR_HIGH(GPIOA_SWCLK) | \
- PIN_ODR_HIGH(GPIOA_PIN15))
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
- PIN_AFIO_AF(GPIOA_PIN1, 0) | \
- PIN_AFIO_AF(GPIOA_PIN2, 0) | \
- PIN_AFIO_AF(GPIOA_PIN3, 0) | \
- PIN_AFIO_AF(GPIOA_LRCK, 6) | \
- PIN_AFIO_AF(GPIOA_SPC, 5) | \
- PIN_AFIO_AF(GPIOA_SDO, 5) | \
- PIN_AFIO_AF(GPIOA_SDI, 5))
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
- PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
- PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
- PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
- PIN_AFIO_AF(GPIOA_PIN15, 0))
-
-/*
- * GPIOB setup:
- *
- * PB0 - PIN0 (input pullup).
- * PB1 - PIN1 (input pullup).
- * PB2 - PIN2 (input pullup).
- * PB3 - SWO (alternate 0).
- * PB4 - PIN4 (input pullup).
- * PB5 - PIN5 (input pullup).
- * PB6 - SCL (alternate 4).
- * PB7 - PIN7 (input pullup).
- * PB8 - PIN8 (input pullup).
- * PB9 - SDA (alternate 4).
- * PB10 - CLK_IN (input pullup).
- * PB11 - PIN11 (input pullup).
- * PB12 - PIN12 (input pullup).
- * PB13 - PIN13 (input pullup).
- * PB14 - PIN14 (input pullup).
- * PB15 - SD_DETECT (input pullup).
- */
-#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
- PIN_MODE_INPUT(GPIOB_PIN1) | \
- PIN_MODE_INPUT(GPIOB_PIN2) | \
- PIN_MODE_ALTERNATE(GPIOB_SWO) | \
- PIN_MODE_INPUT(GPIOB_PIN4) | \
- PIN_MODE_INPUT(GPIOB_PIN5) | \
- PIN_MODE_ALTERNATE(GPIOB_SCL) | \
- PIN_MODE_INPUT(GPIOB_PIN7) | \
- PIN_MODE_INPUT(GPIOB_PIN8) | \
- PIN_MODE_ALTERNATE(GPIOB_SDA) | \
- PIN_MODE_INPUT(GPIOB_CLK_IN) | \
- PIN_MODE_INPUT(GPIOB_PIN11) | \
- PIN_MODE_INPUT(GPIOB_PIN12) | \
- PIN_MODE_INPUT(GPIOB_PIN13) | \
- PIN_MODE_INPUT(GPIOB_PIN14) | \
- PIN_MODE_INPUT(GPIOB_SD_DETECT))
-#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
- PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
- PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \
- PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOB_SD_DETECT))
-#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \
- PIN_OSPEED_100M(GPIOB_PIN1) | \
- PIN_OSPEED_100M(GPIOB_PIN2) | \
- PIN_OSPEED_100M(GPIOB_SWO) | \
- PIN_OSPEED_100M(GPIOB_PIN4) | \
- PIN_OSPEED_100M(GPIOB_PIN5) | \
- PIN_OSPEED_100M(GPIOB_SCL) | \
- PIN_OSPEED_100M(GPIOB_PIN7) | \
- PIN_OSPEED_100M(GPIOB_PIN8) | \
- PIN_OSPEED_100M(GPIOB_SDA) | \
- PIN_OSPEED_100M(GPIOB_CLK_IN) | \
- PIN_OSPEED_100M(GPIOB_PIN11) | \
- PIN_OSPEED_100M(GPIOB_PIN12) | \
- PIN_OSPEED_100M(GPIOB_PIN13) | \
- PIN_OSPEED_100M(GPIOB_PIN14) | \
- PIN_OSPEED_100M(GPIOB_SD_DETECT))
-#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOB_SWO) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOB_SCL) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOB_SDA) | \
- PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOB_SD_DETECT))
-#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
- PIN_ODR_HIGH(GPIOB_PIN1) | \
- PIN_ODR_HIGH(GPIOB_PIN2) | \
- PIN_ODR_HIGH(GPIOB_SWO) | \
- PIN_ODR_HIGH(GPIOB_PIN4) | \
- PIN_ODR_HIGH(GPIOB_PIN5) | \
- PIN_ODR_HIGH(GPIOB_SCL) | \
- PIN_ODR_HIGH(GPIOB_PIN7) | \
- PIN_ODR_HIGH(GPIOB_PIN8) | \
- PIN_ODR_HIGH(GPIOB_SDA) | \
- PIN_ODR_HIGH(GPIOB_CLK_IN) | \
- PIN_ODR_HIGH(GPIOB_PIN11) | \
- PIN_ODR_HIGH(GPIOB_PIN12) | \
- PIN_ODR_HIGH(GPIOB_PIN13) | \
- PIN_ODR_HIGH(GPIOB_PIN14) | \
- PIN_ODR_HIGH(GPIOB_SD_DETECT))
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
- PIN_AFIO_AF(GPIOB_PIN1, 0) | \
- PIN_AFIO_AF(GPIOB_PIN2, 0) | \
- PIN_AFIO_AF(GPIOB_SWO, 0) | \
- PIN_AFIO_AF(GPIOB_PIN4, 0) | \
- PIN_AFIO_AF(GPIOB_PIN5, 0) | \
- PIN_AFIO_AF(GPIOB_SCL, 4) | \
- PIN_AFIO_AF(GPIOB_PIN7, 0))
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
- PIN_AFIO_AF(GPIOB_SDA, 4) | \
- PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \
- PIN_AFIO_AF(GPIOB_PIN11, 0) | \
- PIN_AFIO_AF(GPIOB_PIN12, 0) | \
- PIN_AFIO_AF(GPIOB_PIN13, 0) | \
- PIN_AFIO_AF(GPIOB_PIN14, 0) | \
- PIN_AFIO_AF(GPIOB_SD_DETECT, 0))
-
-/*
- * GPIOC setup:
- *
- * PC0 - OTG_FS_POWER_ON (output pushpull maximum).
- * PC1 - PIN1 (input pullup).
- * PC2 - PIN2 (input pullup).
- * PC3 - PDM_OUT (input pullup).
- * PC4 - PIN4 (input pullup).
- * PC5 - PIN5 (input pullup).
- * PC6 - PIN6 (input pullup).
- * PC7 - MCLK (alternate 6).
- * PC8 - SD_D0 (alternate 12).
- * PC9 - SD_D1 (alternate 12).
- * PC10 - SD_D2 (alternate 12).
- * PC11 - SD_D3 (alternate 12).
- * PC12 - SD_CLK (alternate 12).
- * PC13 - PIN13 (input pullup).
- * PC14 - PIN14 (input pullup).
- * PC15 - PIN15 (input pullup).
- */
-#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\
- PIN_MODE_INPUT(GPIOC_PIN1) | \
- PIN_MODE_INPUT(GPIOC_PIN2) | \
- PIN_MODE_INPUT(GPIOC_PDM_OUT) | \
- PIN_MODE_INPUT(GPIOC_PIN4) | \
- PIN_MODE_INPUT(GPIOC_PIN5) | \
- PIN_MODE_INPUT(GPIOC_PIN6) | \
- PIN_MODE_ALTERNATE(GPIOC_MCLK) | \
- PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \
- PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \
- PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \
- PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \
- PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \
- PIN_MODE_INPUT(GPIOC_PIN13) | \
- PIN_MODE_INPUT(GPIOC_PIN14) | \
- PIN_MODE_INPUT(GPIOC_PIN15))
-#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\
- PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
-#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\
- PIN_OSPEED_100M(GPIOC_PIN1) | \
- PIN_OSPEED_100M(GPIOC_PIN2) | \
- PIN_OSPEED_100M(GPIOC_PDM_OUT) | \
- PIN_OSPEED_100M(GPIOC_PIN4) | \
- PIN_OSPEED_100M(GPIOC_PIN5) | \
- PIN_OSPEED_100M(GPIOC_PIN6) | \
- PIN_OSPEED_100M(GPIOC_MCLK) | \
- PIN_OSPEED_100M(GPIOC_SD_D0) | \
- PIN_OSPEED_100M(GPIOC_SD_D1) | \
- PIN_OSPEED_100M(GPIOC_SD_D2) | \
- PIN_OSPEED_100M(GPIOC_SD_D3) | \
- PIN_OSPEED_100M(GPIOC_SD_CLK) | \
- PIN_OSPEED_100M(GPIOC_PIN13) | \
- PIN_OSPEED_100M(GPIOC_PIN14) | \
- PIN_OSPEED_100M(GPIOC_PIN15))
-#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\
- PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOC_MCLK) | \
- PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \
- PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \
- PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \
- PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \
- PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN15))
-#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \
- PIN_ODR_HIGH(GPIOC_PIN1) | \
- PIN_ODR_HIGH(GPIOC_PIN2) | \
- PIN_ODR_HIGH(GPIOC_PDM_OUT) | \
- PIN_ODR_HIGH(GPIOC_PIN4) | \
- PIN_ODR_HIGH(GPIOC_PIN5) | \
- PIN_ODR_HIGH(GPIOC_PIN6) | \
- PIN_ODR_HIGH(GPIOC_MCLK) | \
- PIN_ODR_HIGH(GPIOC_SD_D0) | \
- PIN_ODR_HIGH(GPIOC_SD_D1) | \
- PIN_ODR_HIGH(GPIOC_SD_D2) | \
- PIN_ODR_HIGH(GPIOC_SD_D3) | \
- PIN_ODR_HIGH(GPIOC_SD_CLK) | \
- PIN_ODR_HIGH(GPIOC_PIN13) | \
- PIN_ODR_HIGH(GPIOC_PIN14) | \
- PIN_ODR_HIGH(GPIOC_PIN15))
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\
- PIN_AFIO_AF(GPIOC_PIN1, 0) | \
- PIN_AFIO_AF(GPIOC_PIN2, 0) | \
- PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \
- PIN_AFIO_AF(GPIOC_PIN4, 0) | \
- PIN_AFIO_AF(GPIOC_PIN5, 0) | \
- PIN_AFIO_AF(GPIOC_PIN6, 0) | \
- PIN_AFIO_AF(GPIOC_MCLK, 6))
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \
- PIN_AFIO_AF(GPIOC_SD_D1, 12) | \
- PIN_AFIO_AF(GPIOC_SD_D2, 12) | \
- PIN_AFIO_AF(GPIOC_SD_D3, 12) | \
- PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \
- PIN_AFIO_AF(GPIOC_PIN13, 0) | \
- PIN_AFIO_AF(GPIOC_PIN14, 0) | \
- PIN_AFIO_AF(GPIOC_PIN15, 0))
-
-/*
- * GPIOD setup:
- *
- * PD0 - PIN0 (input pullup).
- * PD1 - PIN1 (input pullup).
- * PD2 - SD_CMD (alternate 12).
- * PD3 - PIN3 (input pullup).
- * PD4 - RESET (output pushpull maximum).
- * PD5 - OVER_CURRENT (input floating).
- * PD6 - PIN6 (input pullup).
- * PD7 - PIN7 (input pullup).
- * PD8 - PIN8 (input pullup).
- * PD9 - PIN9 (input pullup).
- * PD10 - PIN10 (input pullup).
- * PD11 - PIN11 (input pullup).
- * PD12 - LED4 (output pushpull maximum).
- * PD13 - LED3 (output pushpull maximum).
- * PD14 - LED5 (output pushpull maximum).
- * PD15 - LED6 (output pushpull maximum).
- */
-#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
- PIN_MODE_INPUT(GPIOD_PIN1) | \
- PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \
- PIN_MODE_INPUT(GPIOD_PIN3) | \
- PIN_MODE_OUTPUT(GPIOD_RESET) | \
- PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \
- PIN_MODE_INPUT(GPIOD_PIN6) | \
- PIN_MODE_INPUT(GPIOD_PIN7) | \
- PIN_MODE_INPUT(GPIOD_PIN8) | \
- PIN_MODE_INPUT(GPIOD_PIN9) | \
- PIN_MODE_INPUT(GPIOD_PIN10) | \
- PIN_MODE_INPUT(GPIOD_PIN11) | \
- PIN_MODE_OUTPUT(GPIOD_LED4) | \
- PIN_MODE_OUTPUT(GPIOD_LED3) | \
- PIN_MODE_OUTPUT(GPIOD_LED5) | \
- PIN_MODE_OUTPUT(GPIOD_LED6))
-#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \
- PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\
- PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \
- PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \
- PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \
- PIN_OTYPE_PUSHPULL(GPIOD_LED6))
-#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
- PIN_OSPEED_100M(GPIOD_PIN1) | \
- PIN_OSPEED_100M(GPIOD_SD_CMD) | \
- PIN_OSPEED_100M(GPIOD_PIN3) | \
- PIN_OSPEED_100M(GPIOD_RESET) | \
- PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \
- PIN_OSPEED_100M(GPIOD_PIN6) | \
- PIN_OSPEED_100M(GPIOD_PIN7) | \
- PIN_OSPEED_100M(GPIOD_PIN8) | \
- PIN_OSPEED_100M(GPIOD_PIN9) | \
- PIN_OSPEED_100M(GPIOD_PIN10) | \
- PIN_OSPEED_100M(GPIOD_PIN11) | \
- PIN_OSPEED_100M(GPIOD_LED4) | \
- PIN_OSPEED_100M(GPIOD_LED3) | \
- PIN_OSPEED_100M(GPIOD_LED5) | \
- PIN_OSPEED_100M(GPIOD_LED6))
-#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOD_RESET) | \
- PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\
- PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOD_LED4) | \
- PIN_PUPDR_FLOATING(GPIOD_LED3) | \
- PIN_PUPDR_FLOATING(GPIOD_LED5) | \
- PIN_PUPDR_FLOATING(GPIOD_LED6))
-#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
- PIN_ODR_HIGH(GPIOD_PIN1) | \
- PIN_ODR_HIGH(GPIOD_SD_CMD) | \
- PIN_ODR_HIGH(GPIOD_PIN3) | \
- PIN_ODR_HIGH(GPIOD_RESET) | \
- PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \
- PIN_ODR_HIGH(GPIOD_PIN6) | \
- PIN_ODR_HIGH(GPIOD_PIN7) | \
- PIN_ODR_HIGH(GPIOD_PIN8) | \
- PIN_ODR_HIGH(GPIOD_PIN9) | \
- PIN_ODR_HIGH(GPIOD_PIN10) | \
- PIN_ODR_HIGH(GPIOD_PIN11) | \
- PIN_ODR_LOW(GPIOD_LED4) | \
- PIN_ODR_LOW(GPIOD_LED3) | \
- PIN_ODR_LOW(GPIOD_LED5) | \
- PIN_ODR_LOW(GPIOD_LED6))
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
- PIN_AFIO_AF(GPIOD_PIN1, 0) | \
- PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \
- PIN_AFIO_AF(GPIOD_PIN3, 0) | \
- PIN_AFIO_AF(GPIOD_RESET, 0) | \
- PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \
- PIN_AFIO_AF(GPIOD_PIN6, 0) | \
- PIN_AFIO_AF(GPIOD_PIN7, 0))
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
- PIN_AFIO_AF(GPIOD_PIN9, 0) | \
- PIN_AFIO_AF(GPIOD_PIN10, 0) | \
- PIN_AFIO_AF(GPIOD_PIN11, 0) | \
- PIN_AFIO_AF(GPIOD_LED4, 0) | \
- PIN_AFIO_AF(GPIOD_LED3, 0) | \
- PIN_AFIO_AF(GPIOD_LED5, 0) | \
- PIN_AFIO_AF(GPIOD_LED6, 0))
-
-/*
- * GPIOE setup:
- *
- * PE0 - INT1 (input floating).
- * PE1 - INT2 (input floating).
- * PE2 - PIN2 (input floating).
- * PE3 - CS_SPI (output pushpull maximum).
- * PE4 - PIN4 (input floating).
- * PE5 - PIN5 (input floating).
- * PE6 - PIN6 (input floating).
- * PE7 - PIN7 (input floating).
- * PE8 - PIN8 (input floating).
- * PE9 - PIN9 (input floating).
- * PE10 - PIN10 (input floating).
- * PE11 - PIN11 (input floating).
- * PE12 - PIN12 (input floating).
- * PE13 - PIN13 (input floating).
- * PE14 - PIN14 (input floating).
- * PE15 - PIN15 (input floating).
- */
-#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \
- PIN_MODE_INPUT(GPIOE_INT2) | \
- PIN_MODE_INPUT(GPIOE_PIN2) | \
- PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \
- PIN_MODE_INPUT(GPIOE_PIN4) | \
- PIN_MODE_INPUT(GPIOE_PIN5) | \
- PIN_MODE_INPUT(GPIOE_PIN6) | \
- PIN_MODE_INPUT(GPIOE_PIN7) | \
- PIN_MODE_INPUT(GPIOE_PIN8) | \
- PIN_MODE_INPUT(GPIOE_PIN9) | \
- PIN_MODE_INPUT(GPIOE_PIN10) | \
- PIN_MODE_INPUT(GPIOE_PIN11) | \
- PIN_MODE_INPUT(GPIOE_PIN12) | \
- PIN_MODE_INPUT(GPIOE_PIN13) | \
- PIN_MODE_INPUT(GPIOE_PIN14) | \
- PIN_MODE_INPUT(GPIOE_PIN15))
-#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \
- PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
-#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \
- PIN_OSPEED_100M(GPIOE_INT2) | \
- PIN_OSPEED_100M(GPIOE_PIN2) | \
- PIN_OSPEED_100M(GPIOE_CS_SPI) | \
- PIN_OSPEED_100M(GPIOE_PIN4) | \
- PIN_OSPEED_100M(GPIOE_PIN5) | \
- PIN_OSPEED_100M(GPIOE_PIN6) | \
- PIN_OSPEED_100M(GPIOE_PIN7) | \
- PIN_OSPEED_100M(GPIOE_PIN8) | \
- PIN_OSPEED_100M(GPIOE_PIN9) | \
- PIN_OSPEED_100M(GPIOE_PIN10) | \
- PIN_OSPEED_100M(GPIOE_PIN11) | \
- PIN_OSPEED_100M(GPIOE_PIN12) | \
- PIN_OSPEED_100M(GPIOE_PIN13) | \
- PIN_OSPEED_100M(GPIOE_PIN14) | \
- PIN_OSPEED_100M(GPIOE_PIN15))
-#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \
- PIN_PUPDR_FLOATING(GPIOE_INT2) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN15))
-#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \
- PIN_ODR_HIGH(GPIOE_INT2) | \
- PIN_ODR_HIGH(GPIOE_PIN2) | \
- PIN_ODR_HIGH(GPIOE_CS_SPI) | \
- PIN_ODR_HIGH(GPIOE_PIN4) | \
- PIN_ODR_HIGH(GPIOE_PIN5) | \
- PIN_ODR_HIGH(GPIOE_PIN6) | \
- PIN_ODR_HIGH(GPIOE_PIN7) | \
- PIN_ODR_HIGH(GPIOE_PIN8) | \
- PIN_ODR_HIGH(GPIOE_PIN9) | \
- PIN_ODR_HIGH(GPIOE_PIN10) | \
- PIN_ODR_HIGH(GPIOE_PIN11) | \
- PIN_ODR_HIGH(GPIOE_PIN12) | \
- PIN_ODR_HIGH(GPIOE_PIN13) | \
- PIN_ODR_HIGH(GPIOE_PIN14) | \
- PIN_ODR_HIGH(GPIOE_PIN15))
-#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \
- PIN_AFIO_AF(GPIOE_INT2, 0) | \
- PIN_AFIO_AF(GPIOE_PIN2, 0) | \
- PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \
- PIN_AFIO_AF(GPIOE_PIN4, 0) | \
- PIN_AFIO_AF(GPIOE_PIN5, 0) | \
- PIN_AFIO_AF(GPIOE_PIN6, 0) | \
- PIN_AFIO_AF(GPIOE_PIN7, 0))
-#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
- PIN_AFIO_AF(GPIOE_PIN9, 0) | \
- PIN_AFIO_AF(GPIOE_PIN10, 0) | \
- PIN_AFIO_AF(GPIOE_PIN11, 0) | \
- PIN_AFIO_AF(GPIOE_PIN12, 0) | \
- PIN_AFIO_AF(GPIOE_PIN13, 0) | \
- PIN_AFIO_AF(GPIOE_PIN14, 0) | \
- PIN_AFIO_AF(GPIOE_PIN15, 0))
-
-/*
- * GPIOF setup:
- *
- * PF0 - PIN0 (input floating).
- * PF1 - PIN1 (input floating).
- * PF2 - PIN2 (input floating).
- * PF3 - PIN3 (input floating).
- * PF4 - PIN4 (input floating).
- * PF5 - PIN5 (input floating).
- * PF6 - PIN6 (input floating).
- * PF7 - PIN7 (input floating).
- * PF8 - PIN8 (input floating).
- * PF9 - PIN9 (input floating).
- * PF10 - PIN10 (input floating).
- * PF11 - PIN11 (input floating).
- * PF12 - PIN12 (input floating).
- * PF13 - PIN13 (input floating).
- * PF14 - PIN14 (input floating).
- * PF15 - PIN15 (input floating).
- */
-#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
- PIN_MODE_INPUT(GPIOF_PIN1) | \
- PIN_MODE_INPUT(GPIOF_PIN2) | \
- PIN_MODE_INPUT(GPIOF_PIN3) | \
- PIN_MODE_INPUT(GPIOF_PIN4) | \
- PIN_MODE_INPUT(GPIOF_PIN5) | \
- PIN_MODE_INPUT(GPIOF_PIN6) | \
- PIN_MODE_INPUT(GPIOF_PIN7) | \
- PIN_MODE_INPUT(GPIOF_PIN8) | \
- PIN_MODE_INPUT(GPIOF_PIN9) | \
- PIN_MODE_INPUT(GPIOF_PIN10) | \
- PIN_MODE_INPUT(GPIOF_PIN11) | \
- PIN_MODE_INPUT(GPIOF_PIN12) | \
- PIN_MODE_INPUT(GPIOF_PIN13) | \
- PIN_MODE_INPUT(GPIOF_PIN14) | \
- PIN_MODE_INPUT(GPIOF_PIN15))
-#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
-#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
- PIN_OSPEED_100M(GPIOF_PIN1) | \
- PIN_OSPEED_100M(GPIOF_PIN2) | \
- PIN_OSPEED_100M(GPIOF_PIN3) | \
- PIN_OSPEED_100M(GPIOF_PIN4) | \
- PIN_OSPEED_100M(GPIOF_PIN5) | \
- PIN_OSPEED_100M(GPIOF_PIN6) | \
- PIN_OSPEED_100M(GPIOF_PIN7) | \
- PIN_OSPEED_100M(GPIOF_PIN8) | \
- PIN_OSPEED_100M(GPIOF_PIN9) | \
- PIN_OSPEED_100M(GPIOF_PIN10) | \
- PIN_OSPEED_100M(GPIOF_PIN11) | \
- PIN_OSPEED_100M(GPIOF_PIN12) | \
- PIN_OSPEED_100M(GPIOF_PIN13) | \
- PIN_OSPEED_100M(GPIOF_PIN14) | \
- PIN_OSPEED_100M(GPIOF_PIN15))
-#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN15))
-#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
- PIN_ODR_HIGH(GPIOF_PIN1) | \
- PIN_ODR_HIGH(GPIOF_PIN2) | \
- PIN_ODR_HIGH(GPIOF_PIN3) | \
- PIN_ODR_HIGH(GPIOF_PIN4) | \
- PIN_ODR_HIGH(GPIOF_PIN5) | \
- PIN_ODR_HIGH(GPIOF_PIN6) | \
- PIN_ODR_HIGH(GPIOF_PIN7) | \
- PIN_ODR_HIGH(GPIOF_PIN8) | \
- PIN_ODR_HIGH(GPIOF_PIN9) | \
- PIN_ODR_HIGH(GPIOF_PIN10) | \
- PIN_ODR_HIGH(GPIOF_PIN11) | \
- PIN_ODR_HIGH(GPIOF_PIN12) | \
- PIN_ODR_HIGH(GPIOF_PIN13) | \
- PIN_ODR_HIGH(GPIOF_PIN14) | \
- PIN_ODR_HIGH(GPIOF_PIN15))
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
- PIN_AFIO_AF(GPIOF_PIN1, 0) | \
- PIN_AFIO_AF(GPIOF_PIN2, 0) | \
- PIN_AFIO_AF(GPIOF_PIN3, 0) | \
- PIN_AFIO_AF(GPIOF_PIN4, 0) | \
- PIN_AFIO_AF(GPIOF_PIN5, 0) | \
- PIN_AFIO_AF(GPIOF_PIN6, 0) | \
- PIN_AFIO_AF(GPIOF_PIN7, 0))
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
- PIN_AFIO_AF(GPIOF_PIN9, 0) | \
- PIN_AFIO_AF(GPIOF_PIN10, 0) | \
- PIN_AFIO_AF(GPIOF_PIN11, 0) | \
- PIN_AFIO_AF(GPIOF_PIN12, 0) | \
- PIN_AFIO_AF(GPIOF_PIN13, 0) | \
- PIN_AFIO_AF(GPIOF_PIN14, 0) | \
- PIN_AFIO_AF(GPIOF_PIN15, 0))
-
-/*
- * GPIOG setup:
- *
- * PG0 - PIN0 (input floating).
- * PG1 - PIN1 (input floating).
- * PG2 - PIN2 (input floating).
- * PG3 - PIN3 (input floating).
- * PG4 - PIN4 (input floating).
- * PG5 - PIN5 (input floating).
- * PG6 - PIN6 (input floating).
- * PG7 - PIN7 (input floating).
- * PG8 - PIN8 (input floating).
- * PG9 - PIN9 (input floating).
- * PG10 - PIN10 (input floating).
- * PG11 - PIN11 (input floating).
- * PG12 - PIN12 (input floating).
- * PG13 - PIN13 (input floating).
- * PG14 - PIN14 (input floating).
- * PG15 - PIN15 (input floating).
- */
-#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
- PIN_MODE_INPUT(GPIOG_PIN1) | \
- PIN_MODE_INPUT(GPIOG_PIN2) | \
- PIN_MODE_INPUT(GPIOG_PIN3) | \
- PIN_MODE_INPUT(GPIOG_PIN4) | \
- PIN_MODE_INPUT(GPIOG_PIN5) | \
- PIN_MODE_INPUT(GPIOG_PIN6) | \
- PIN_MODE_INPUT(GPIOG_PIN7) | \
- PIN_MODE_INPUT(GPIOG_PIN8) | \
- PIN_MODE_INPUT(GPIOG_PIN9) | \
- PIN_MODE_INPUT(GPIOG_PIN10) | \
- PIN_MODE_INPUT(GPIOG_PIN11) | \
- PIN_MODE_INPUT(GPIOG_PIN12) | \
- PIN_MODE_INPUT(GPIOG_PIN13) | \
- PIN_MODE_INPUT(GPIOG_PIN14) | \
- PIN_MODE_INPUT(GPIOG_PIN15))
-#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
-#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
- PIN_OSPEED_100M(GPIOG_PIN1) | \
- PIN_OSPEED_100M(GPIOG_PIN2) | \
- PIN_OSPEED_100M(GPIOG_PIN3) | \
- PIN_OSPEED_100M(GPIOG_PIN4) | \
- PIN_OSPEED_100M(GPIOG_PIN5) | \
- PIN_OSPEED_100M(GPIOG_PIN6) | \
- PIN_OSPEED_100M(GPIOG_PIN7) | \
- PIN_OSPEED_100M(GPIOG_PIN8) | \
- PIN_OSPEED_100M(GPIOG_PIN9) | \
- PIN_OSPEED_100M(GPIOG_PIN10) | \
- PIN_OSPEED_100M(GPIOG_PIN11) | \
- PIN_OSPEED_100M(GPIOG_PIN12) | \
- PIN_OSPEED_100M(GPIOG_PIN13) | \
- PIN_OSPEED_100M(GPIOG_PIN14) | \
- PIN_OSPEED_100M(GPIOG_PIN15))
-#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN15))
-#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
- PIN_ODR_HIGH(GPIOG_PIN1) | \
- PIN_ODR_HIGH(GPIOG_PIN2) | \
- PIN_ODR_HIGH(GPIOG_PIN3) | \
- PIN_ODR_HIGH(GPIOG_PIN4) | \
- PIN_ODR_HIGH(GPIOG_PIN5) | \
- PIN_ODR_HIGH(GPIOG_PIN6) | \
- PIN_ODR_HIGH(GPIOG_PIN7) | \
- PIN_ODR_HIGH(GPIOG_PIN8) | \
- PIN_ODR_HIGH(GPIOG_PIN9) | \
- PIN_ODR_HIGH(GPIOG_PIN10) | \
- PIN_ODR_HIGH(GPIOG_PIN11) | \
- PIN_ODR_HIGH(GPIOG_PIN12) | \
- PIN_ODR_HIGH(GPIOG_PIN13) | \
- PIN_ODR_HIGH(GPIOG_PIN14) | \
- PIN_ODR_HIGH(GPIOG_PIN15))
-#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
- PIN_AFIO_AF(GPIOG_PIN1, 0) | \
- PIN_AFIO_AF(GPIOG_PIN2, 0) | \
- PIN_AFIO_AF(GPIOG_PIN3, 0) | \
- PIN_AFIO_AF(GPIOG_PIN4, 0) | \
- PIN_AFIO_AF(GPIOG_PIN5, 0) | \
- PIN_AFIO_AF(GPIOG_PIN6, 0) | \
- PIN_AFIO_AF(GPIOG_PIN7, 0))
-#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
- PIN_AFIO_AF(GPIOG_PIN9, 0) | \
- PIN_AFIO_AF(GPIOG_PIN10, 0) | \
- PIN_AFIO_AF(GPIOG_PIN11, 0) | \
- PIN_AFIO_AF(GPIOG_PIN12, 0) | \
- PIN_AFIO_AF(GPIOG_PIN13, 0) | \
- PIN_AFIO_AF(GPIOG_PIN14, 0) | \
- PIN_AFIO_AF(GPIOG_PIN15, 0))
-
-/*
- * GPIOH setup:
- *
- * PH0 - OSC_IN (input floating).
- * PH1 - OSC_OUT (input floating).
- * PH2 - PIN2 (input floating).
- * PH3 - PIN3 (input floating).
- * PH4 - PIN4 (input floating).
- * PH5 - PIN5 (input floating).
- * PH6 - PIN6 (input floating).
- * PH7 - PIN7 (input floating).
- * PH8 - PIN8 (input floating).
- * PH9 - PIN9 (input floating).
- * PH10 - PIN10 (input floating).
- * PH11 - PIN11 (input floating).
- * PH12 - PIN12 (input floating).
- * PH13 - PIN13 (input floating).
- * PH14 - PIN14 (input floating).
- * PH15 - PIN15 (input floating).
- */
-#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
- PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
- PIN_MODE_INPUT(GPIOH_PIN2) | \
- PIN_MODE_INPUT(GPIOH_PIN3) | \
- PIN_MODE_INPUT(GPIOH_PIN4) | \
- PIN_MODE_INPUT(GPIOH_PIN5) | \
- PIN_MODE_INPUT(GPIOH_PIN6) | \
- PIN_MODE_INPUT(GPIOH_PIN7) | \
- PIN_MODE_INPUT(GPIOH_PIN8) | \
- PIN_MODE_INPUT(GPIOH_PIN9) | \
- PIN_MODE_INPUT(GPIOH_PIN10) | \
- PIN_MODE_INPUT(GPIOH_PIN11) | \
- PIN_MODE_INPUT(GPIOH_PIN12) | \
- PIN_MODE_INPUT(GPIOH_PIN13) | \
- PIN_MODE_INPUT(GPIOH_PIN14) | \
- PIN_MODE_INPUT(GPIOH_PIN15))
-#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
- PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
-#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
- PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
- PIN_OSPEED_100M(GPIOH_PIN2) | \
- PIN_OSPEED_100M(GPIOH_PIN3) | \
- PIN_OSPEED_100M(GPIOH_PIN4) | \
- PIN_OSPEED_100M(GPIOH_PIN5) | \
- PIN_OSPEED_100M(GPIOH_PIN6) | \
- PIN_OSPEED_100M(GPIOH_PIN7) | \
- PIN_OSPEED_100M(GPIOH_PIN8) | \
- PIN_OSPEED_100M(GPIOH_PIN9) | \
- PIN_OSPEED_100M(GPIOH_PIN10) | \
- PIN_OSPEED_100M(GPIOH_PIN11) | \
- PIN_OSPEED_100M(GPIOH_PIN12) | \
- PIN_OSPEED_100M(GPIOH_PIN13) | \
- PIN_OSPEED_100M(GPIOH_PIN14) | \
- PIN_OSPEED_100M(GPIOH_PIN15))
-#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
- PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN15))
-#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
- PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
- PIN_ODR_HIGH(GPIOH_PIN2) | \
- PIN_ODR_HIGH(GPIOH_PIN3) | \
- PIN_ODR_HIGH(GPIOH_PIN4) | \
- PIN_ODR_HIGH(GPIOH_PIN5) | \
- PIN_ODR_HIGH(GPIOH_PIN6) | \
- PIN_ODR_HIGH(GPIOH_PIN7) | \
- PIN_ODR_HIGH(GPIOH_PIN8) | \
- PIN_ODR_HIGH(GPIOH_PIN9) | \
- PIN_ODR_HIGH(GPIOH_PIN10) | \
- PIN_ODR_HIGH(GPIOH_PIN11) | \
- PIN_ODR_HIGH(GPIOH_PIN12) | \
- PIN_ODR_HIGH(GPIOH_PIN13) | \
- PIN_ODR_HIGH(GPIOH_PIN14) | \
- PIN_ODR_HIGH(GPIOH_PIN15))
-#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
- PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
- PIN_AFIO_AF(GPIOH_PIN2, 0) | \
- PIN_AFIO_AF(GPIOH_PIN3, 0) | \
- PIN_AFIO_AF(GPIOH_PIN4, 0) | \
- PIN_AFIO_AF(GPIOH_PIN5, 0) | \
- PIN_AFIO_AF(GPIOH_PIN6, 0) | \
- PIN_AFIO_AF(GPIOH_PIN7, 0))
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
- PIN_AFIO_AF(GPIOH_PIN9, 0) | \
- PIN_AFIO_AF(GPIOH_PIN10, 0) | \
- PIN_AFIO_AF(GPIOH_PIN11, 0) | \
- PIN_AFIO_AF(GPIOH_PIN12, 0) | \
- PIN_AFIO_AF(GPIOH_PIN13, 0) | \
- PIN_AFIO_AF(GPIOH_PIN14, 0) | \
- PIN_AFIO_AF(GPIOH_PIN15, 0))
-
-/*
- * GPIOI setup:
- *
- * PI0 - PIN0 (input floating).
- * PI1 - PIN1 (input floating).
- * PI2 - PIN2 (input floating).
- * PI3 - PIN3 (input floating).
- * PI4 - PIN4 (input floating).
- * PI5 - PIN5 (input floating).
- * PI6 - PIN6 (input floating).
- * PI7 - PIN7 (input floating).
- * PI8 - PIN8 (input floating).
- * PI9 - PIN9 (input floating).
- * PI10 - PIN10 (input floating).
- * PI11 - PIN11 (input floating).
- * PI12 - PIN12 (input floating).
- * PI13 - PIN13 (input floating).
- * PI14 - PIN14 (input floating).
- * PI15 - PIN15 (input floating).
- */
-#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
- PIN_MODE_INPUT(GPIOI_PIN1) | \
- PIN_MODE_INPUT(GPIOI_PIN2) | \
- PIN_MODE_INPUT(GPIOI_PIN3) | \
- PIN_MODE_INPUT(GPIOI_PIN4) | \
- PIN_MODE_INPUT(GPIOI_PIN5) | \
- PIN_MODE_INPUT(GPIOI_PIN6) | \
- PIN_MODE_INPUT(GPIOI_PIN7) | \
- PIN_MODE_INPUT(GPIOI_PIN8) | \
- PIN_MODE_INPUT(GPIOI_PIN9) | \
- PIN_MODE_INPUT(GPIOI_PIN10) | \
- PIN_MODE_INPUT(GPIOI_PIN11) | \
- PIN_MODE_INPUT(GPIOI_PIN12) | \
- PIN_MODE_INPUT(GPIOI_PIN13) | \
- PIN_MODE_INPUT(GPIOI_PIN14) | \
- PIN_MODE_INPUT(GPIOI_PIN15))
-#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
-#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
- PIN_OSPEED_100M(GPIOI_PIN1) | \
- PIN_OSPEED_100M(GPIOI_PIN2) | \
- PIN_OSPEED_100M(GPIOI_PIN3) | \
- PIN_OSPEED_100M(GPIOI_PIN4) | \
- PIN_OSPEED_100M(GPIOI_PIN5) | \
- PIN_OSPEED_100M(GPIOI_PIN6) | \
- PIN_OSPEED_100M(GPIOI_PIN7) | \
- PIN_OSPEED_100M(GPIOI_PIN8) | \
- PIN_OSPEED_100M(GPIOI_PIN9) | \
- PIN_OSPEED_100M(GPIOI_PIN10) | \
- PIN_OSPEED_100M(GPIOI_PIN11) | \
- PIN_OSPEED_100M(GPIOI_PIN12) | \
- PIN_OSPEED_100M(GPIOI_PIN13) | \
- PIN_OSPEED_100M(GPIOI_PIN14) | \
- PIN_OSPEED_100M(GPIOI_PIN15))
-#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN15))
-#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
- PIN_ODR_HIGH(GPIOI_PIN1) | \
- PIN_ODR_HIGH(GPIOI_PIN2) | \
- PIN_ODR_HIGH(GPIOI_PIN3) | \
- PIN_ODR_HIGH(GPIOI_PIN4) | \
- PIN_ODR_HIGH(GPIOI_PIN5) | \
- PIN_ODR_HIGH(GPIOI_PIN6) | \
- PIN_ODR_HIGH(GPIOI_PIN7) | \
- PIN_ODR_HIGH(GPIOI_PIN8) | \
- PIN_ODR_HIGH(GPIOI_PIN9) | \
- PIN_ODR_HIGH(GPIOI_PIN10) | \
- PIN_ODR_HIGH(GPIOI_PIN11) | \
- PIN_ODR_HIGH(GPIOI_PIN12) | \
- PIN_ODR_HIGH(GPIOI_PIN13) | \
- PIN_ODR_HIGH(GPIOI_PIN14) | \
- PIN_ODR_HIGH(GPIOI_PIN15))
-#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
- PIN_AFIO_AF(GPIOI_PIN1, 0) | \
- PIN_AFIO_AF(GPIOI_PIN2, 0) | \
- PIN_AFIO_AF(GPIOI_PIN3, 0) | \
- PIN_AFIO_AF(GPIOI_PIN4, 0) | \
- PIN_AFIO_AF(GPIOI_PIN5, 0) | \
- PIN_AFIO_AF(GPIOI_PIN6, 0) | \
- PIN_AFIO_AF(GPIOI_PIN7, 0))
-#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
- PIN_AFIO_AF(GPIOI_PIN9, 0) | \
- PIN_AFIO_AF(GPIOI_PIN10, 0) | \
- PIN_AFIO_AF(GPIOI_PIN11, 0) | \
- PIN_AFIO_AF(GPIOI_PIN12, 0) | \
- PIN_AFIO_AF(GPIOI_PIN13, 0) | \
- PIN_AFIO_AF(GPIOI_PIN14, 0) | \
- PIN_AFIO_AF(GPIOI_PIN15, 0))
-
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
diff --git a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.mk b/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.mk
deleted file mode 100644
index e7fe9119..00000000
--- a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/board.mk
+++ /dev/null
@@ -1,3 +0,0 @@
-BOARDINC = $(GFXLIB)/boards/base/Embest-STM32-DMSTF4BB/chibios_board
-BOARDSRC = $(BOARDINC)/board.c \
-
diff --git a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/cfg/board.chcfg b/boards/base/Embest-STM32-DMSTF4BB/chibios_board/cfg/board.chcfg
deleted file mode 100644
index e30de70e..00000000
--- a/boards/base/Embest-STM32-DMSTF4BB/chibios_board/cfg/board.chcfg
+++ /dev/null
@@ -1,1186 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- STM32F4xx board Template -->
-<board
- xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
- <configuration_settings>
- <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
- <output_path>..</output_path>
- </configuration_settings>
- <board_name>STMicroelectronics STM32F4-Discovery</board_name>
- <board_id>ST_STM32F4_DISCOVERY</board_id>
- <board_functions></board_functions>
- <clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="0" VDD="300" />
- <ports>
- <GPIOA>
- <pin0
- ID="BUTTON"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID="LRCK"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="6" />
- <pin5
- ID="SPC"
- Type="PushPull"
- Level="High"
- Speed="High"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="5" />
- <pin6
- ID="SDO"
- Type="PushPull"
- Level="High"
- Speed="High"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="5" />
- <pin7
- ID="SDI"
- Type="PushPull"
- Level="High"
- Speed="High"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="5" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" ></pin8>
- <pin9
- ID="VBUS_FS"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID="OTG_FS_ID"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="10" />
- <pin11
- ID="OTG_FS_DM"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="10" />
- <pin12
- ID="OTG_FS_DP"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="10" />
- <pin13
- ID="SWDIO"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="0" />
- <pin14
- ID="SWCLK"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- </GPIOA>
- <GPIOB>
- <pin0
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID="SWO"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="0" ></pin3>
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID="SCL"
- Type="OpenDrain"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="4" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID="SDA"
- Type="OpenDrain"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="4" ></pin9>
- <pin10
- ID="CLK_IN"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- </GPIOB>
- <GPIOC>
- <pin0
- ID="OTG_FS_POWER_ON"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Output"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID="PDM_OUT"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" ></pin3>
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID="MCLK"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="6" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID="SCLK"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="6" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID="SDIN"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Alternate"
- Alternate="6" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- </GPIOC>
- <GPIOD>
- <pin0
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID="RESET"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Output"
- Alternate="0" />
- <pin5
- ID="OVER_CURRENT"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" ></pin5>
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="PullUp"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID="LED4"
- Type="PushPull"
- Level="Low"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Output"
- Alternate="0" />
- <pin13
- ID="LED3"
- Type="PushPull"
- Level="Low"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Output"
- Alternate="0" />
- <pin14
- ID="LED5"
- Type="PushPull"
- Level="Low"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Output"
- Alternate="0" ></pin14>
- <pin15
- ID="LED6"
- Type="PushPull"
- Level="Low"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Output"
- Alternate="0" />
- </GPIOD>
- <GPIOE>
- <pin0
- ID="INT1"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID="INT2"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID="CS_SPI"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Output"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOE>
- <GPIOF>
- <pin0
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOF>
- <GPIOG>
- <pin0
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOG>
- <GPIOH>
- <pin0
- ID="OSC_IN"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID="OSC_OUT"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" ></pin2>
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOH>
- <GPIOI>
- <pin0
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOI>
- </ports>
-</board>
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile
index 922282d8..4fcda523 100644
--- a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile
@@ -13,20 +13,19 @@
# uGFX settings
# See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
- GFXLIB = /path/to/your/ugfx
+ GFXLIB = ../path/to/ugfx
GFXBOARD = Embest-STM32-DMSTF4BB
GFXDEMO = modules/gdisp/basics
# ChibiOS settings
ifeq ($(OPT_OS),chibios)
- # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables
- CHIBIOS = /path/to/your/chibios
+ # See $(GFXLIB)/tools/gmake_scripts/os_chibios_x.mk for the list of variables
+ CHIBIOS = ../path/to/chibios
+ CHIBIOS_VERSION = 2
CHIBIOS_BOARD =
CHIBIOS_PLATFORM = STM32F4xx
CHIBIOS_PORT = GCC/ARMCMx/STM32F4xx
CHIBIOS_LDSCRIPT = STM32F407xG.ld
- # We define a non standard board script as this is not a standard ChibiOS supported board
- include $(GFXLIB)/boards/base/$(GFXBOARD)/chibios_board/board.mk
endif
##############################################################################################
@@ -40,7 +39,7 @@ CXXFLAGS = -fno-rtti
ASFLAGS =
LDFLAGS =
-SRC =
+SRC = board.c
OBJS =
DEFS =
LIBS =
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.c b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.c
new file mode 100644
index 00000000..48440444
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.c
@@ -0,0 +1,108 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ return !palReadPad(GPIOB, GPIOB_SD_DETECT);
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+
+ return !palReadPad(GPIOB, GPIOB_SD_DETECT);
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.h b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.h
new file mode 100644
index 00000000..a1c46d3d
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/board.h
@@ -0,0 +1,1297 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_EMBEST_DMSTF4BB
+#define BOARD_NAME "STMicroelectronics STM32F4-Discovery with Embest add-on"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000
+#endif
+
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F40_41xxx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0
+#define GPIOA_PIN1 1
+#define GPIOA_PIN2 2
+#define GPIOA_PIN3 3
+#define GPIOA_LRCK 4
+#define GPIOA_SPC 5
+#define GPIOA_SDO 6
+#define GPIOA_SDI 7
+#define GPIOA_PIN8 8
+#define GPIOA_VBUS_FS 9
+#define GPIOA_OTG_FS_ID 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_PIN15 15
+
+#define GPIOB_PIN0 0
+#define GPIOB_PIN1 1
+#define GPIOB_PIN2 2
+#define GPIOB_SWO 3
+#define GPIOB_PIN4 4
+#define GPIOB_PIN5 5
+#define GPIOB_SCL 6
+#define GPIOB_PIN7 7
+#define GPIOB_PIN8 8
+#define GPIOB_SDA 9
+#define GPIOB_CLK_IN 10
+#define GPIOB_PIN11 11
+#define GPIOB_PIN12 12
+#define GPIOB_PIN13 13
+#define GPIOB_PIN14 14
+#define GPIOB_SD_DETECT 15
+
+#define GPIOC_OTG_FS_POWER_ON 0
+#define GPIOC_PIN1 1
+#define GPIOC_PIN2 2
+#define GPIOC_PDM_OUT 3
+#define GPIOC_PIN4 4
+#define GPIOC_PIN5 5
+#define GPIOC_PIN6 6
+#define GPIOC_MCLK 7
+#define GPIOC_SD_D0 8
+#define GPIOC_SD_D1 9
+#define GPIOC_SD_D2 10
+#define GPIOC_SD_D3 11
+#define GPIOC_SD_CLK 12
+#define GPIOC_PIN13 13
+#define GPIOC_PIN14 14
+#define GPIOC_PIN15 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_SD_CMD 2
+#define GPIOD_PIN3 3
+#define GPIOD_RESET 4
+#define GPIOD_OVER_CURRENT 5
+#define GPIOD_PIN6 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_LED4 12
+#define GPIOD_LED3 13
+#define GPIOD_LED5 14
+#define GPIOD_LED6 15
+
+#define GPIOE_INT1 0
+#define GPIOE_INT2 1
+#define GPIOE_PIN2 2
+#define GPIOE_CS_SPI 3
+#define GPIOE_PIN4 4
+#define GPIOE_PIN5 5
+#define GPIOE_PIN6 6
+#define GPIOE_PIN7 7
+#define GPIOE_PIN8 8
+#define GPIOE_PIN9 9
+#define GPIOE_PIN10 10
+#define GPIOE_PIN11 11
+#define GPIOE_PIN12 12
+#define GPIOE_PIN13 13
+#define GPIOE_PIN14 14
+#define GPIOE_PIN15 15
+
+#define GPIOF_PIN0 0
+#define GPIOF_PIN1 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+#define GPIOG_PIN0 0
+#define GPIOG_PIN1 1
+#define GPIOG_PIN2 2
+#define GPIOG_PIN3 3
+#define GPIOG_PIN4 4
+#define GPIOG_PIN5 5
+#define GPIOG_PIN6 6
+#define GPIOG_PIN7 7
+#define GPIOG_PIN8 8
+#define GPIOG_PIN9 9
+#define GPIOG_PIN10 10
+#define GPIOG_PIN11 11
+#define GPIOG_PIN12 12
+#define GPIOG_PIN13 13
+#define GPIOG_PIN14 14
+#define GPIOG_PIN15 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+#define GPIOH_PIN2 2
+#define GPIOH_PIN3 3
+#define GPIOH_PIN4 4
+#define GPIOH_PIN5 5
+#define GPIOH_PIN6 6
+#define GPIOH_PIN7 7
+#define GPIOH_PIN8 8
+#define GPIOH_PIN9 9
+#define GPIOH_PIN10 10
+#define GPIOH_PIN11 11
+#define GPIOH_PIN12 12
+#define GPIOH_PIN13 13
+#define GPIOH_PIN14 14
+#define GPIOH_PIN15 15
+
+#define GPIOI_PIN0 0
+#define GPIOI_PIN1 1
+#define GPIOI_PIN2 2
+#define GPIOI_PIN3 3
+#define GPIOI_PIN4 4
+#define GPIOI_PIN5 5
+#define GPIOI_PIN6 6
+#define GPIOI_PIN7 7
+#define GPIOI_PIN8 8
+#define GPIOI_PIN9 9
+#define GPIOI_PIN10 10
+#define GPIOI_PIN11 11
+#define GPIOI_PIN12 12
+#define GPIOI_PIN13 13
+#define GPIOI_PIN14 14
+#define GPIOI_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON (input floating).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - PIN2 (input pullup).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - LRCK (alternate 6).
+ * PA5 - SPC (alternate 5).
+ * PA6 - SDO (alternate 5).
+ * PA7 - SDI (alternate 5).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - VBUS_FS (input floating).
+ * PA10 - OTG_FS_ID (alternate 10).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_PIN2) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_ALTERNATE(GPIOA_LRCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPC) | \
+ PIN_MODE_ALTERNATE(GPIOA_SDO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SDI) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_VBUS_FS) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \
+ PIN_OSPEED_100M(GPIOA_PIN1) | \
+ PIN_OSPEED_100M(GPIOA_PIN2) | \
+ PIN_OSPEED_100M(GPIOA_PIN3) | \
+ PIN_OSPEED_100M(GPIOA_LRCK) | \
+ PIN_OSPEED_50M(GPIOA_SPC) | \
+ PIN_OSPEED_50M(GPIOA_SDO) | \
+ PIN_OSPEED_50M(GPIOA_SDI) | \
+ PIN_OSPEED_100M(GPIOA_PIN8) | \
+ PIN_OSPEED_100M(GPIOA_VBUS_FS) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_100M(GPIOA_SWDIO) | \
+ PIN_OSPEED_100M(GPIOA_SWCLK) | \
+ PIN_OSPEED_100M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOA_LRCK) | \
+ PIN_PUPDR_FLOATING(GPIOA_SPC) | \
+ PIN_PUPDR_FLOATING(GPIOA_SDO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SDI) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_PIN2) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_LRCK) | \
+ PIN_ODR_HIGH(GPIOA_SPC) | \
+ PIN_ODR_HIGH(GPIOA_SDO) | \
+ PIN_ODR_HIGH(GPIOA_SDI) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_VBUS_FS) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_LRCK, 6) | \
+ PIN_AFIO_AF(GPIOA_SPC, 5) | \
+ PIN_AFIO_AF(GPIOA_SDO, 5) | \
+ PIN_AFIO_AF(GPIOA_SDI, 5))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - SCL (alternate 4).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - SDA (alternate 4).
+ * PB10 - CLK_IN (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - SD_DETECT (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_ALTERNATE(GPIOB_SCL) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_ALTERNATE(GPIOB_SDA) | \
+ PIN_MODE_INPUT(GPIOB_CLK_IN) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_SD_DETECT))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SD_DETECT))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \
+ PIN_OSPEED_100M(GPIOB_PIN1) | \
+ PIN_OSPEED_100M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_SWO) | \
+ PIN_OSPEED_100M(GPIOB_PIN4) | \
+ PIN_OSPEED_100M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_SCL) | \
+ PIN_OSPEED_100M(GPIOB_PIN7) | \
+ PIN_OSPEED_100M(GPIOB_PIN8) | \
+ PIN_OSPEED_100M(GPIOB_SDA) | \
+ PIN_OSPEED_100M(GPIOB_CLK_IN) | \
+ PIN_OSPEED_100M(GPIOB_PIN11) | \
+ PIN_OSPEED_100M(GPIOB_PIN12) | \
+ PIN_OSPEED_100M(GPIOB_PIN13) | \
+ PIN_OSPEED_100M(GPIOB_PIN14) | \
+ PIN_OSPEED_100M(GPIOB_SD_DETECT))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_SCL) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOB_SDA) | \
+ PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_SD_DETECT))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_SCL) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_SDA) | \
+ PIN_ODR_HIGH(GPIOB_CLK_IN) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_SD_DETECT))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_SDA, 4) | \
+ PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_SD_DETECT, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - OTG_FS_POWER_ON (output pushpull maximum).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PDM_OUT (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - MCLK (alternate 6).
+ * PC8 - SD_D0 (alternate 12).
+ * PC9 - SD_D1 (alternate 12).
+ * PC10 - SD_D2 (alternate 12).
+ * PC11 - SD_D3 (alternate 12).
+ * PC12 - SD_CLK (alternate 12).
+ * PC13 - PIN13 (input pullup).
+ * PC14 - PIN14 (input pullup).
+ * PC15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PDM_OUT) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOC_MCLK) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \
+ PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_OSPEED_100M(GPIOC_PIN1) | \
+ PIN_OSPEED_100M(GPIOC_PIN2) | \
+ PIN_OSPEED_100M(GPIOC_PDM_OUT) | \
+ PIN_OSPEED_100M(GPIOC_PIN4) | \
+ PIN_OSPEED_100M(GPIOC_PIN5) | \
+ PIN_OSPEED_100M(GPIOC_PIN6) | \
+ PIN_OSPEED_100M(GPIOC_MCLK) | \
+ PIN_OSPEED_100M(GPIOC_SD_D0) | \
+ PIN_OSPEED_100M(GPIOC_SD_D1) | \
+ PIN_OSPEED_100M(GPIOC_SD_D2) | \
+ PIN_OSPEED_100M(GPIOC_SD_D3) | \
+ PIN_OSPEED_100M(GPIOC_SD_CLK) | \
+ PIN_OSPEED_100M(GPIOC_PIN13) | \
+ PIN_OSPEED_100M(GPIOC_PIN14) | \
+ PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOC_MCLK) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \
+ PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PDM_OUT) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_MCLK) | \
+ PIN_ODR_HIGH(GPIOC_SD_D0) | \
+ PIN_ODR_HIGH(GPIOC_SD_D1) | \
+ PIN_ODR_HIGH(GPIOC_SD_D2) | \
+ PIN_ODR_HIGH(GPIOC_SD_D3) | \
+ PIN_ODR_HIGH(GPIOC_SD_CLK) | \
+ PIN_ODR_HIGH(GPIOC_PIN13) | \
+ PIN_ODR_HIGH(GPIOC_PIN14) | \
+ PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_MCLK, 6))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_D1, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_D2, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_D3, 12) | \
+ PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - SD_CMD (alternate 12).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - RESET (output pushpull maximum).
+ * PD5 - OVER_CURRENT (input floating).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - LED4 (output pushpull maximum).
+ * PD13 - LED3 (output pushpull maximum).
+ * PD14 - LED5 (output pushpull maximum).
+ * PD15 - LED6 (output pushpull maximum).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_OUTPUT(GPIOD_RESET) | \
+ PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_OUTPUT(GPIOD_LED4) | \
+ PIN_MODE_OUTPUT(GPIOD_LED3) | \
+ PIN_MODE_OUTPUT(GPIOD_LED5) | \
+ PIN_MODE_OUTPUT(GPIOD_LED6))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED6))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
+ PIN_OSPEED_100M(GPIOD_PIN1) | \
+ PIN_OSPEED_100M(GPIOD_SD_CMD) | \
+ PIN_OSPEED_100M(GPIOD_PIN3) | \
+ PIN_OSPEED_100M(GPIOD_RESET) | \
+ PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \
+ PIN_OSPEED_100M(GPIOD_PIN6) | \
+ PIN_OSPEED_100M(GPIOD_PIN7) | \
+ PIN_OSPEED_100M(GPIOD_PIN8) | \
+ PIN_OSPEED_100M(GPIOD_PIN9) | \
+ PIN_OSPEED_100M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_PIN11) | \
+ PIN_OSPEED_100M(GPIOD_LED4) | \
+ PIN_OSPEED_100M(GPIOD_LED3) | \
+ PIN_OSPEED_100M(GPIOD_LED5) | \
+ PIN_OSPEED_100M(GPIOD_LED6))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOD_RESET) | \
+ PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED4) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED3) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED5) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED6))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_SD_CMD) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_RESET) | \
+ PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_LOW(GPIOD_LED4) | \
+ PIN_ODR_LOW(GPIOD_LED3) | \
+ PIN_ODR_LOW(GPIOD_LED5) | \
+ PIN_ODR_LOW(GPIOD_LED6))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_RESET, 0) | \
+ PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_LED4, 0) | \
+ PIN_AFIO_AF(GPIOD_LED3, 0) | \
+ PIN_AFIO_AF(GPIOD_LED5, 0) | \
+ PIN_AFIO_AF(GPIOD_LED6, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - INT1 (input floating).
+ * PE1 - INT2 (input floating).
+ * PE2 - PIN2 (input floating).
+ * PE3 - CS_SPI (output pushpull maximum).
+ * PE4 - PIN4 (input floating).
+ * PE5 - PIN5 (input floating).
+ * PE6 - PIN6 (input floating).
+ * PE7 - PIN7 (input floating).
+ * PE8 - PIN8 (input floating).
+ * PE9 - PIN9 (input floating).
+ * PE10 - PIN10 (input floating).
+ * PE11 - PIN11 (input floating).
+ * PE12 - PIN12 (input floating).
+ * PE13 - PIN13 (input floating).
+ * PE14 - PIN14 (input floating).
+ * PE15 - PIN15 (input floating).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \
+ PIN_MODE_INPUT(GPIOE_INT2) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \
+ PIN_OSPEED_100M(GPIOE_INT2) | \
+ PIN_OSPEED_100M(GPIOE_PIN2) | \
+ PIN_OSPEED_100M(GPIOE_CS_SPI) | \
+ PIN_OSPEED_100M(GPIOE_PIN4) | \
+ PIN_OSPEED_100M(GPIOE_PIN5) | \
+ PIN_OSPEED_100M(GPIOE_PIN6) | \
+ PIN_OSPEED_100M(GPIOE_PIN7) | \
+ PIN_OSPEED_100M(GPIOE_PIN8) | \
+ PIN_OSPEED_100M(GPIOE_PIN9) | \
+ PIN_OSPEED_100M(GPIOE_PIN10) | \
+ PIN_OSPEED_100M(GPIOE_PIN11) | \
+ PIN_OSPEED_100M(GPIOE_PIN12) | \
+ PIN_OSPEED_100M(GPIOE_PIN13) | \
+ PIN_OSPEED_100M(GPIOE_PIN14) | \
+ PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \
+ PIN_PUPDR_FLOATING(GPIOE_INT2) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \
+ PIN_ODR_HIGH(GPIOE_INT2) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_CS_SPI) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \
+ PIN_AFIO_AF(GPIOE_INT2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input floating).
+ * PF1 - PIN1 (input floating).
+ * PF2 - PIN2 (input floating).
+ * PF3 - PIN3 (input floating).
+ * PF4 - PIN4 (input floating).
+ * PF5 - PIN5 (input floating).
+ * PF6 - PIN6 (input floating).
+ * PF7 - PIN7 (input floating).
+ * PF8 - PIN8 (input floating).
+ * PF9 - PIN9 (input floating).
+ * PF10 - PIN10 (input floating).
+ * PF11 - PIN11 (input floating).
+ * PF12 - PIN12 (input floating).
+ * PF13 - PIN13 (input floating).
+ * PF14 - PIN14 (input floating).
+ * PF15 - PIN15 (input floating).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
+ PIN_OSPEED_100M(GPIOF_PIN1) | \
+ PIN_OSPEED_100M(GPIOF_PIN2) | \
+ PIN_OSPEED_100M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_PIN4) | \
+ PIN_OSPEED_100M(GPIOF_PIN5) | \
+ PIN_OSPEED_100M(GPIOF_PIN6) | \
+ PIN_OSPEED_100M(GPIOF_PIN7) | \
+ PIN_OSPEED_100M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_PIN9) | \
+ PIN_OSPEED_100M(GPIOF_PIN10) | \
+ PIN_OSPEED_100M(GPIOF_PIN11) | \
+ PIN_OSPEED_100M(GPIOF_PIN12) | \
+ PIN_OSPEED_100M(GPIOF_PIN13) | \
+ PIN_OSPEED_100M(GPIOF_PIN14) | \
+ PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input floating).
+ * PG1 - PIN1 (input floating).
+ * PG2 - PIN2 (input floating).
+ * PG3 - PIN3 (input floating).
+ * PG4 - PIN4 (input floating).
+ * PG5 - PIN5 (input floating).
+ * PG6 - PIN6 (input floating).
+ * PG7 - PIN7 (input floating).
+ * PG8 - PIN8 (input floating).
+ * PG9 - PIN9 (input floating).
+ * PG10 - PIN10 (input floating).
+ * PG11 - PIN11 (input floating).
+ * PG12 - PIN12 (input floating).
+ * PG13 - PIN13 (input floating).
+ * PG14 - PIN14 (input floating).
+ * PG15 - PIN15 (input floating).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_INPUT(GPIOG_PIN11) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_INPUT(GPIOG_PIN13) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
+ PIN_OSPEED_100M(GPIOG_PIN1) | \
+ PIN_OSPEED_100M(GPIOG_PIN2) | \
+ PIN_OSPEED_100M(GPIOG_PIN3) | \
+ PIN_OSPEED_100M(GPIOG_PIN4) | \
+ PIN_OSPEED_100M(GPIOG_PIN5) | \
+ PIN_OSPEED_100M(GPIOG_PIN6) | \
+ PIN_OSPEED_100M(GPIOG_PIN7) | \
+ PIN_OSPEED_100M(GPIOG_PIN8) | \
+ PIN_OSPEED_100M(GPIOG_PIN9) | \
+ PIN_OSPEED_100M(GPIOG_PIN10) | \
+ PIN_OSPEED_100M(GPIOG_PIN11) | \
+ PIN_OSPEED_100M(GPIOG_PIN12) | \
+ PIN_OSPEED_100M(GPIOG_PIN13) | \
+ PIN_OSPEED_100M(GPIOG_PIN14) | \
+ PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input floating).
+ * PH3 - PIN3 (input floating).
+ * PH4 - PIN4 (input floating).
+ * PH5 - PIN5 (input floating).
+ * PH6 - PIN6 (input floating).
+ * PH7 - PIN7 (input floating).
+ * PH8 - PIN8 (input floating).
+ * PH9 - PIN9 (input floating).
+ * PH10 - PIN10 (input floating).
+ * PH11 - PIN11 (input floating).
+ * PH12 - PIN12 (input floating).
+ * PH13 - PIN13 (input floating).
+ * PH14 - PIN14 (input floating).
+ * PH15 - PIN15 (input floating).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_100M(GPIOH_PIN2) | \
+ PIN_OSPEED_100M(GPIOH_PIN3) | \
+ PIN_OSPEED_100M(GPIOH_PIN4) | \
+ PIN_OSPEED_100M(GPIOH_PIN5) | \
+ PIN_OSPEED_100M(GPIOH_PIN6) | \
+ PIN_OSPEED_100M(GPIOH_PIN7) | \
+ PIN_OSPEED_100M(GPIOH_PIN8) | \
+ PIN_OSPEED_100M(GPIOH_PIN9) | \
+ PIN_OSPEED_100M(GPIOH_PIN10) | \
+ PIN_OSPEED_100M(GPIOH_PIN11) | \
+ PIN_OSPEED_100M(GPIOH_PIN12) | \
+ PIN_OSPEED_100M(GPIOH_PIN13) | \
+ PIN_OSPEED_100M(GPIOH_PIN14) | \
+ PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input floating).
+ * PI1 - PIN1 (input floating).
+ * PI2 - PIN2 (input floating).
+ * PI3 - PIN3 (input floating).
+ * PI4 - PIN4 (input floating).
+ * PI5 - PIN5 (input floating).
+ * PI6 - PIN6 (input floating).
+ * PI7 - PIN7 (input floating).
+ * PI8 - PIN8 (input floating).
+ * PI9 - PIN9 (input floating).
+ * PI10 - PIN10 (input floating).
+ * PI11 - PIN11 (input floating).
+ * PI12 - PIN12 (input floating).
+ * PI13 - PIN13 (input floating).
+ * PI14 - PIN14 (input floating).
+ * PI15 - PIN15 (input floating).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
+ PIN_OSPEED_100M(GPIOI_PIN1) | \
+ PIN_OSPEED_100M(GPIOI_PIN2) | \
+ PIN_OSPEED_100M(GPIOI_PIN3) | \
+ PIN_OSPEED_100M(GPIOI_PIN4) | \
+ PIN_OSPEED_100M(GPIOI_PIN5) | \
+ PIN_OSPEED_100M(GPIOI_PIN6) | \
+ PIN_OSPEED_100M(GPIOI_PIN7) | \
+ PIN_OSPEED_100M(GPIOI_PIN8) | \
+ PIN_OSPEED_100M(GPIOI_PIN9) | \
+ PIN_OSPEED_100M(GPIOI_PIN10) | \
+ PIN_OSPEED_100M(GPIOI_PIN11) | \
+ PIN_OSPEED_100M(GPIOI_PIN12) | \
+ PIN_OSPEED_100M(GPIOI_PIN13) | \
+ PIN_OSPEED_100M(GPIOI_PIN14) | \
+ PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
new file mode 100644
index 00000000..16611673
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
@@ -0,0 +1,60 @@
+# Possible Targets: all clean Debug cleanDebug Release cleanRelease
+
+##############################################################################################
+# Settings
+#
+
+# General settings
+ # See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables
+ OPT_OS = chibios
+ OPT_THUMB = yes
+ OPT_LINK_OPTIMIZE = yes
+ OPT_CPU = stm32m4
+
+# uGFX settings
+ # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
+ GFXLIB = ../../resources/ugfx
+ GFXBOARD = STM32F429i-Discovery
+ GFXDEMO = modules/gdisp/basics
+
+# ChibiOS settings
+ifeq ($(OPT_OS),chibios)
+ # See $(GFXLIB)/tools/gmake_scripts/os_chibios_x.mk for the list of variables
+ CHIBIOS = ../../resources/chibios_3.0.1
+ CHIBIOS_VERSION = 3
+ CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
+ CHIBIOS_CPUCLASS = ARMCMx
+ CHIBIOS_PLATFORM = STM32
+ CHIBIOS_DEVICE_FAMILY = STM32F4xx
+ CHIBIOS_STARTUP = startup_stm32f4xx
+ CHIBIOS_PORT = v7m
+ CHIBIOS_LDSCRIPT = STM32F429xI.ld
+endif
+
+##############################################################################################
+# Set these for your project
+#
+
+ARCH = arm-none-eabi-
+SRCFLAGS = -ggdb -O0
+CFLAGS =
+CXXFLAGS = -fno-rtti
+ASFLAGS =
+LDFLAGS =
+
+SRC =
+OBJS =
+DEFS =
+LIBS =
+INCPATH =
+LIBPATH =
+LDSCRIPT =
+
+##############################################################################################
+# These should be at the end
+#
+
+include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk
+include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk
+include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk
+# *** EOF ***
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/chconf.h b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/chconf.h
new file mode 100644
index 00000000..53700421
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/chconf.h
@@ -0,0 +1,498 @@
+/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 10000
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop. */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM TRUE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_QUEUES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_TRACE FALSE
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/halconf.h b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/halconf.h
new file mode 100644
index 00000000..90ceebc0
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/halconf.h
@@ -0,0 +1,327 @@
+/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB TRUE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB TRUE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/mcuconf.h b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/mcuconf.h
new file mode 100644
index 00000000..c64b2740
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/mcuconf.h
@@ -0,0 +1,321 @@
+/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_USE_CAN2 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+#define STM32_GPT_TIM12_IRQ_PRIORITY 7
+#define STM32_GPT_TIM14_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define HAL_USE_I2C TRUE
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 TRUE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_SDIO_DMA_PRIORITY 3
+#define STM32_SDC_SDIO_IRQ_PRIORITY 9
+#define STM32_SDC_WRITE_TIMEOUT_MS 250
+#define STM32_SDC_READ_TIMEOUT_MS 25
+#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
+#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define HAL_USE_SPI TRUE
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_USE_SPI4 FALSE
+#define STM32_SPI_USE_SPI5 TRUE
+#define STM32_SPI_USE_SPI6 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_UART4_IRQ_PRIORITY 12
+#define STM32_UART_UART5_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 TRUE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/openocd.cfg b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/openocd.cfg
new file mode 100644
index 00000000..f8b6a6f5
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/openocd.cfg
@@ -0,0 +1,81 @@
+# This is a script file for OpenOCD 0.7.0
+#
+# It is set up for the Mikromedia-STM32M4 board using the ST-Link JTAG adaptor.
+#
+# Assuming the current directory is your project directory containing this openocd.cfg file...
+#
+# To program your device:
+#
+# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown
+#
+# To debug your device:
+#
+# openocd
+# (This will run openocd in gdb server debug mode. Leave it running in the background)
+#
+# gdb yourfile.elf
+# (To start gdb. Then run the following commands in gdb...)
+#
+# target remote 127.0.0.1:3333
+# monitor Debug
+# stepi
+# (This last stepi resynchronizes gdb).
+#
+# If you want to reprogram from within gdb:
+#
+# monitor Burn yourfile.bin
+#
+
+echo ""
+echo "##### Loading debugger..."
+source [find interface/stlink-v2.cfg]
+
+echo ""
+echo "##### Loading CPU..."
+source [find target/stm32f4x_stlink.cfg]
+
+echo ""
+echo "##### Configuring..."
+reset_config srst_only srst_nogate
+#cortex_m maskisr (auto|on|off)
+#cortex_m vector_catch [all|none|list]
+#cortex_m reset_config (srst|sysresetreq|vectreset)
+#gdb_breakpoint_override hard
+
+proc Debug { } {
+ echo ""
+ echo "##### Debug Session Connected..."
+ reset init
+ echo "Ready..."
+}
+
+proc Burn {file} {
+ echo ""
+ echo "##### Burning $file to device..."
+ halt
+ # Due to an issue with the combination of the ST-Link adapters and OpenOCD
+ # applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD!
+ # If this happens to you - use the ST-Link utility to set the option byte back to normal.
+ # If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below.
+ #stm32f2x unlock 0
+ flash protect 0 0 last off
+ reset init
+ flash write_image erase $file 0x08000000
+ verify_image $file 0x0
+ #flash protect 0 0 last on
+ reset
+ echo "Burning Complete!"
+}
+
+echo ""
+echo "##### Leaving Configuration Mode..."
+init
+reset init
+flash probe 0
+flash banks
+#flash info 0
+
+echo ""
+echo "##### Waiting for debug connections..."
+
+
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile b/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile
index 217d1d24..16611673 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile
+++ b/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile
@@ -13,20 +13,22 @@
# uGFX settings
# See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
- GFXLIB = ../uGFX
+ GFXLIB = ../../resources/ugfx
GFXBOARD = STM32F429i-Discovery
GFXDEMO = modules/gdisp/basics
# ChibiOS settings
ifeq ($(OPT_OS),chibios)
- # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables
- CHIBIOS = ../ChibiOS3
- CHIBIOS_VERSION = 3
- CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
- CHIBIOS_CPUCLASS = ARMCMx
- CHIBIOS_PLATFORM = STM32/STM32F4xx
- CHIBIOS_PORT = stm32f4xx
- CHIBIOS_LDSCRIPT = STM32F407xG.ld
+ # See $(GFXLIB)/tools/gmake_scripts/os_chibios_x.mk for the list of variables
+ CHIBIOS = ../../resources/chibios_3.0.1
+ CHIBIOS_VERSION = 3
+ CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
+ CHIBIOS_CPUCLASS = ARMCMx
+ CHIBIOS_PLATFORM = STM32
+ CHIBIOS_DEVICE_FAMILY = STM32F4xx
+ CHIBIOS_STARTUP = startup_stm32f4xx
+ CHIBIOS_PORT = v7m
+ CHIBIOS_LDSCRIPT = STM32F429xI.ld
endif
##############################################################################################
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_3.x/chconf.h b/boards/base/STM32F429i-Discovery/example_chibios_3.x/chconf.h
index 53700421..4a34b223 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_3.x/chconf.h
+++ b/boards/base/STM32F429i-Discovery/example_chibios_3.x/chconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -99,7 +99,8 @@
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread. The application @p main()
* function becomes the idle thread and must implement an
- * infinite loop. */
+ * infinite loop.
+ */
#define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
@@ -440,7 +441,7 @@
* @details This hook is invoked just before switching between threads.
*/
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
- /* System halt code here.*/ \
+ /* Context switch code here.*/ \
}
/**
@@ -449,7 +450,7 @@
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
-#define CH_CFG_IDLE_ENTER_HOOK() { \
+#define CH_CFG_IDLE_ENTER_HOOK() { \
}
/**
@@ -458,7 +459,7 @@
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
-#define CH_CFG_IDLE_LEAVE_HOOK() { \
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
}
/**
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h b/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h
index 90ceebc0..6f80a255 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h
+++ b/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -51,6 +51,13 @@
#define HAL_USE_CAN FALSE
#endif
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
/**
* @brief Enables the EXT subsystem.
*/
@@ -125,14 +132,14 @@
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL FALSE
+#define HAL_USE_SERIAL TRUE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL_USB TRUE
+#define HAL_USE_SERIAL_USB FALSE
#endif
/**
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h b/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h
index c64b2740..80417b89 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h
+++ b/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h
@@ -1,5 +1,5 @@
/*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,6 +14,9 @@
limitations under the License.
*/
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
@@ -87,6 +90,19 @@
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
/*
* EXT driver system settings.
*/
@@ -136,10 +152,9 @@
/*
* I2C driver system settings.
*/
-#define HAL_USE_I2C TRUE
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
-#define STM32_I2C_USE_I2C3 TRUE
+#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
@@ -218,7 +233,7 @@
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
-#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
@@ -233,37 +248,21 @@
/*
* SPI driver system settings.
*/
-#define HAL_USE_SPI TRUE
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
-#define STM32_SPI_USE_SPI4 FALSE
-#define STM32_SPI_USE_SPI5 TRUE
-#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
-#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
-#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
-#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
-#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
-#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
-#define STM32_SPI_SPI4_DMA_PRIORITY 1
-#define STM32_SPI_SPI5_DMA_PRIORITY 1
-#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
-#define STM32_SPI_SPI4_IRQ_PRIORITY 10
-#define STM32_SPI_SPI5_IRQ_PRIORITY 10
-#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@@ -310,8 +309,8 @@
/*
* USB driver system settings.
*/
-#define STM32_USB_USE_OTG1 FALSE
-#define STM32_USB_USE_OTG2 TRUE
+#define STM32_USB_USE_OTG1 TRUE
+#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
@@ -319,3 +318,5 @@
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+#endif /* _MCUCONF_H_ */
diff --git a/tools/gmake_scripts/os_chibios.mk b/tools/gmake_scripts/os_chibios.mk
index f583d186..536ec3f7 100644
--- a/tools/gmake_scripts/os_chibios.mk
+++ b/tools/gmake_scripts/os_chibios.mk
@@ -9,77 +9,12 @@
# Requirements:
#
-# CHIBIOS: The location of the ChibiOS code eg CHIBIOS=../chibios
-# CHIBIOS_PLATFORM The name of the ChibiOS platform eg CHIBIOS_PLATFORM=AT91SAM7
-# CHIBIOS_PORT The name of the ChibiOS port eg CHIBIOS_PORT=GCC/ARM/AT91SAM7
-# CHIBIOS_CPUCLASS The class of the CPU. Only required for ChibiOS v3 eg CHIBIOS_CPUCLASS=ARMCMx
+# CHIBIOS_VERSION Which version of ChibiOS is this (2 or 3) - default is 3
#
-# Optional:
-#
-# CHIBIOS_LDSCRIPT The name of the loader script eg CHIBIOS_LDSCRIPT=AT91SAM7X256.ld
-# CHIBIOS_BOARD The name of the ChibiOS board eg CHIBIOS_BOARD=OLIMEX_SAM7_EX256 - if not specified you must include equivalent code yourself
-# CHIBIOS_STM32LIB Use the STM32 library source for drivers instead of native drivers (yes or no) - default no
-# CHIBIOS_VERSION Which version of ChibiOS is this (2 or 3) - default is 2
-# CHIBIOS_PROCESS_STACKSIZE Size of the ChibiOS process stack. Only useful if the link script supports it - default is 0x400
-# CHIBIOS_EXCEPTIONS_STACKSIZE Size of the ChibiOS exceptopms stack. Only useful if the link script supports it - default is 0x400
-#
-
-PATHLIST += CHIBIOS
-ifeq ($(CHIBIOS_VERSION),3)
- include $(CHIBIOS)/os/hal/hal.mk
- include $(CHIBIOS)/os/hal/osal/rt/osal.mk
- include $(CHIBIOS)/os/hal/ports/$(CHIBIOS_PLATFORM)/platform.mk
- include $(CHIBIOS)/os/rt/rt.mk
- include $(CHIBIOS)/os/rt/ports/$(CHIBIOS_CPUCLASS)/compilers/GCC/mk/port_$(CHIBIOS_PORT).mk
- ifneq ($(CHIBIOS_BOARD),)
- include $(CHIBIOS)/os/hal/boards/$(CHIBIOS_BOARD)/board.mk
- endif
- LIBPATH += $(CHIBIOS)/os/common/ports/$(CHIBIOS_CPUCLASS)/compilers/GCC
+ifeq ($(CHIBIOS_VERSION),2)
+ include $(GFXLIB)/tools/gmake_scripts/os_chibios_2.mk
else
- include $(CHIBIOS)/os/hal/hal.mk
- include $(CHIBIOS)/os/hal/platforms/$(CHIBIOS_PLATFORM)/platform.mk
- include $(CHIBIOS)/os/kernel/kernel.mk
- include $(CHIBIOS)/os/ports/$(CHIBIOS_PORT)/port.mk
- ifneq ($(CHIBIOS_BOARD),)
- include $(CHIBIOS)/boards/$(CHIBIOS_BOARD)/board.mk
- endif
-endif
-
-ifeq ($(LDSCRIPT),)
- ifneq ($(CHIBIOS_LDSCRIPT),)
- LDSCRIPT= $(PORTLD)/$(CHIBIOS_LDSCRIPT)
- endif
+ include $(GFXLIB)/tools/gmake_scripts/os_chibios_3.mk
endif
-
-ifneq ($(LDSCRIPT),)
- ifeq ($(CHIBIOS_PROCESS_STACKSIZE),)
- LDFLAGS += -Wl,--defsym=__process_stack_size__=0x400
- else
- LDFLAGS += -Wl,--defsym=__process_stack_size__=$(CHIBIOS_PROCESS_STACKSIZE)
- endif
- ifeq ($(CHIBIOS_EXCEPTIONS_STACKSIZE),)
- LDFLAGS += -Wl,--defsym=__main_stack_size__=0x400
- else
- LDFLAGS += -Wl,--defsym=__main_stack_size__=$(CHIBIOS_EXCEPTIONS_STACKSIZE)
- endif
-endif
-
-ifeq ($(CHIBIOS_STM32LIB),yes)
- include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
- SRC += $(STM32SRC)
- DEFS += USE_STDPERIPH_DRIVER
- INCPATH += $(STM32INC)
-endif
-
-INCPATH += $(PORTINC) $(KERNINC) $(TESTINC) $(OSALINC) \
- $(HALINC) $(PLATFORMINC) $(BOARDINC)
-SRC += $(PORTSRC) \
- $(KERNSRC) \
- $(TESTSRC) \
- $(HALSRC) \
- $(PLATFORMSRC) \
- $(BOARDSRC) \
- $(OSALSRC) \
- $(PORTASM)
diff --git a/tools/gmake_scripts/os_chibios_2.mk b/tools/gmake_scripts/os_chibios_2.mk
new file mode 100644
index 00000000..299f42ec
--- /dev/null
+++ b/tools/gmake_scripts/os_chibios_2.mk
@@ -0,0 +1,72 @@
+#
+# This file is subject to the terms of the GFX License. If a copy of
+# the license was not distributed with this file, you can obtain one at:
+#
+# http://ugfx.org/license.html
+#
+
+# See readme.txt for the make API
+
+# Requirements:
+#
+# CHIBIOS The location of the ChibiOS code eg. CHIBIOS = ../chibios
+# CHIBIOS_PLATFORM The name of the ChibiOS platform eg. CHIBIOS_PLATFORM = AT91SAM7
+# CHIBIOS_PORT The name of the ChibiOS port eg. CHIBIOS_PORT = GCC/ARM/AT91SAM7
+#
+
+# Optional:
+#
+# CHIBIOS_LDSCRIPT The name of the loader script eg. CHIBIOS_LDSCRIPT = AT91SAM7X256.ld
+# CHIBIOS_BOARD The name of the ChibiOS board eg. CHIBIOS_BOARD = OLIMEX_SAM7_EX256 - if not specified you must include equivalent code yourself
+# CHIBIOS_VERSION Which version of ChibiOS is this (2 or 3) - default is 3
+# CHIBIOS_STM32LIB Use the STM32 library source for drivers instead of native drivers (yes or no) - default no
+# CHIBIOS_PROCESS_STACKSIZE Size of the ChibiOS process stack. Only useful if the link script supports it - default is 0x400
+# CHIBIOS_EXCEPTIONS_STACKSIZE Size of the ChibiOS exceptopms stack. Only useful if the link script supports it - default is 0x400
+#
+
+PATHLIST += CHIBIOS
+
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/platforms/$(CHIBIOS_PLATFORM)/platform.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/os/ports/$(CHIBIOS_PORT)/port.mk
+ifneq ($(CHIBIOS_BOARD),)
+ include $(CHIBIOS)/boards/$(CHIBIOS_BOARD)/board.mk
+endif
+
+ifeq ($(LDSCRIPT),)
+ ifneq ($(CHIBIOS_LDSCRIPT),)
+ LDSCRIPT= $(PORTLD)/$(CHIBIOS_LDSCRIPT)
+ endif
+endif
+
+ifneq ($(LDSCRIPT),)
+ ifeq ($(CHIBIOS_PROCESS_STACKSIZE),)
+ LDFLAGS += -Wl,--defsym=__process_stack_size__=0x400
+ else
+ LDFLAGS += -Wl,--defsym=__process_stack_size__=$(CHIBIOS_PROCESS_STACKSIZE)
+ endif
+ ifeq ($(CHIBIOS_EXCEPTIONS_STACKSIZE),)
+ LDFLAGS += -Wl,--defsym=__main_stack_size__=0x400
+ else
+ LDFLAGS += -Wl,--defsym=__main_stack_size__=$(CHIBIOS_EXCEPTIONS_STACKSIZE)
+ endif
+endif
+
+ifeq ($(CHIBIOS_STM32LIB),yes)
+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
+ SRC += $(STM32SRC)
+ DEFS += USE_STDPERIPH_DRIVER
+ INCPATH += $(STM32INC)
+endif
+
+INCPATH += $(PORTINC) $(KERNINC) $(OSALINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC)
+
+SRC += $(PORTSRC) \
+ $(KERNSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(OSALSRC) \
+ $(PORTASM)
diff --git a/tools/gmake_scripts/os_chibios_3.mk b/tools/gmake_scripts/os_chibios_3.mk
new file mode 100644
index 00000000..1a44f4b1
--- /dev/null
+++ b/tools/gmake_scripts/os_chibios_3.mk
@@ -0,0 +1,84 @@
+#
+# This file is subject to the terms of the GFX License. If a copy of
+# the license was not distributed with this file, you can obtain one at:
+#
+# http://ugfx.org/license.html
+#
+
+# See readme.txt for the make API
+
+# Requirements:
+#
+# CHIBIOS The location of the ChibiOS code. eg CHIBIOS = ../chibios
+# CHIBIOS_CPUCLASS The class of the CPU. eg CHIBIOS_CPUCLASS = ARMCMx
+# CHIBIOS_PLATFORM The name of the ChibiOS platform. eg CHIBIOS_PLATFORM = STM32
+# CHIBIOS_DEVICE_FAMILY The name of the ChibiOS device family. eg CHIBIOS_DEVICE_FAMILY = STM32F4xx
+# CHIBIOS_STARTUP The name of the ChibiOS startup files. eg CHIBIOS_STARTUP = startup_stm32f4xx
+# CHIBIOS_PORT The name of the ChibiOS port. eg CHIBIOS_PORT = v7m
+#
+
+# Optional:
+#
+# CHIBIOS_LDSCRIPT The name of the loader script eg CHIBIOS_LDSCRIPT = STM32F429xI.ld
+# CHIBIOS_BOARD The name of the ChibiOS board eg CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY - if not specified you must include equivalent code yourself
+# CHIBIOS_VERSION Which version of ChibiOS is this (2 or 3) - default is 3
+# CHIBIOS_PROCESS_STACKSIZE Size of the ChibiOS process stack. Only useful if the link script supports it - default is 0x400
+# CHIBIOS_EXCEPTIONS_STACKSIZE Size of the ChibiOS exceptopms stack. Only useful if the link script supports it - default is 0x400
+#
+
+PATHLIST += CHIBIOS
+
+
+
+include $(CHIBIOS)/os/common/ports/$(CHIBIOS_CPUCLASS)/compilers/GCC/mk/$(CHIBIOS_STARTUP).mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/ports/$(CHIBIOS_PLATFORM)/$(CHIBIOS_DEVICE_FAMILY)/platform.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/rt/ports/$(CHIBIOS_CPUCLASS)/compilers/GCC/mk/port_$(CHIBIOS_PORT).mk
+ifneq ($(CHIBIOS_BOARD),)
+ include $(CHIBIOS)/os/hal/boards/$(CHIBIOS_BOARD)/board.mk
+endif
+LIBPATH += $(CHIBIOS)/os/common/ports/$(CHIBIOS_CPUCLASS)/compilers/GCC
+
+ifeq ($(LDSCRIPT),)
+ ifneq ($(CHIBIOS_LDSCRIPT),)
+ LDSCRIPT= $(STARTUPLD)/$(CHIBIOS_LDSCRIPT)
+ endif
+endif
+
+ifneq ($(LDSCRIPT),)
+ ifeq ($(CHIBIOS_PROCESS_STACKSIZE),)
+ LDFLAGS += -Wl,--defsym=__process_stack_size__=0x400
+ else
+ LDFLAGS += -Wl,--defsym=__process_stack_size__=$(CHIBIOS_PROCESS_STACKSIZE)
+ endif
+ ifeq ($(CHIBIOS_EXCEPTIONS_STACKSIZE),)
+ LDFLAGS += -Wl,--defsym=__main_stack_size__=0x400
+ else
+ LDFLAGS += -Wl,--defsym=__main_stack_size__=$(CHIBIOS_EXCEPTIONS_STACKSIZE)
+ endif
+endif
+
+# Add include files
+INCPATH += $(STARTUPINC) \
+ $(KERNINC) \
+ $(PORTINC) \
+ $(OSALINC) \
+ $(HALINC) \
+ $(PLATFORMINC) \
+ $(BOARDINC)
+
+# Add C files
+SRC += $(STARTUPSRC) \
+ $(KERNSRC) \
+ $(PORTSRC) \
+ $(OSALSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC)
+
+# Add ASM files
+SRC += $(STARTUPASM) \
+ $(PORTASM) \
+ $(OSALASM)
--
cgit v1.2.3
From 2fc483e152203668e5b37eebb2e8455d8bc76f4c Mon Sep 17 00:00:00 2001
From: Joel Bodenmann <joel@seriouslyembedded.com>
Date: Sat, 29 Aug 2015 16:57:12 +0200
Subject: Updating ChibiOS 3.x build system support
---
.../example_chibios_3.x/Makefile | 5 +-
.../example_chibios_3.x/board.c | 124 ++
.../example_chibios_3.x/board.h | 1296 ++++++++++++++++++++
.../example_chibios_2.x/Makefile | 13 +-
4 files changed, 1429 insertions(+), 9 deletions(-)
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.c
create mode 100644 boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.h
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
index 16611673..d4cc3001 100644
--- a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
@@ -14,7 +14,7 @@
# uGFX settings
# See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
GFXLIB = ../../resources/ugfx
- GFXBOARD = STM32F429i-Discovery
+ GFXBOARD = Embest-STM32-DMSTF4BB
GFXDEMO = modules/gdisp/basics
# ChibiOS settings
@@ -22,7 +22,6 @@ ifeq ($(OPT_OS),chibios)
# See $(GFXLIB)/tools/gmake_scripts/os_chibios_x.mk for the list of variables
CHIBIOS = ../../resources/chibios_3.0.1
CHIBIOS_VERSION = 3
- CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
CHIBIOS_CPUCLASS = ARMCMx
CHIBIOS_PLATFORM = STM32
CHIBIOS_DEVICE_FAMILY = STM32F4xx
@@ -42,7 +41,7 @@ CXXFLAGS = -fno-rtti
ASFLAGS =
LDFLAGS =
-SRC =
+SRC = board.c
OBJS =
DEFS =
LIBS =
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.c b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.c
new file mode 100644
index 00000000..692cf99b
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.c
@@ -0,0 +1,124 @@
+/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.h b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.h
new file mode 100644
index 00000000..f033e5dc
--- /dev/null
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/board.h
@@ -0,0 +1,1296 @@
+/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F4_DISCOVERY
+#define BOARD_NAME "STMicroelectronics STM32F4-Discovery"
+
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 0U
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F407xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON 0U
+#define GPIOA_PIN1 1U
+#define GPIOA_PIN2 2U
+#define GPIOA_PIN3 3U
+#define GPIOA_LRCK 4U
+#define GPIOA_SPC 5U
+#define GPIOA_SDO 6U
+#define GPIOA_SDI 7U
+#define GPIOA_PIN8 8U
+#define GPIOA_VBUS_FS 9U
+#define GPIOA_OTG_FS_ID 10U
+#define GPIOA_OTG_FS_DM 11U
+#define GPIOA_OTG_FS_DP 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_PIN15 15U
+
+#define GPIOB_PIN0 0U
+#define GPIOB_PIN1 1U
+#define GPIOB_PIN2 2U
+#define GPIOB_SWO 3U
+#define GPIOB_PIN4 4U
+#define GPIOB_PIN5 5U
+#define GPIOB_SCL 6U
+#define GPIOB_PIN7 7U
+#define GPIOB_PIN8 8U
+#define GPIOB_SDA 9U
+#define GPIOB_CLK_IN 10U
+#define GPIOB_PIN11 11U
+#define GPIOB_PIN12 12U
+#define GPIOB_PIN13 13U
+#define GPIOB_PIN14 14U
+#define GPIOB_PIN15 15U
+
+#define GPIOC_OTG_FS_POWER_ON 0U
+#define GPIOC_PIN1 1U
+#define GPIOC_PIN2 2U
+#define GPIOC_PDM_OUT 3U
+#define GPIOC_PIN4 4U
+#define GPIOC_PIN5 5U
+#define GPIOC_PIN6 6U
+#define GPIOC_MCLK 7U
+#define GPIOC_PIN8 8U
+#define GPIOC_PIN9 9U
+#define GPIOC_SCLK 10U
+#define GPIOC_PIN11 11U
+#define GPIOC_SDIN 12U
+#define GPIOC_PIN13 13U
+#define GPIOC_PIN14 14U
+#define GPIOC_PIN15 15U
+
+#define GPIOD_PIN0 0U
+#define GPIOD_PIN1 1U
+#define GPIOD_PIN2 2U
+#define GPIOD_PIN3 3U
+#define GPIOD_RESET 4U
+#define GPIOD_OVER_CURRENT 5U
+#define GPIOD_PIN6 6U
+#define GPIOD_PIN7 7U
+#define GPIOD_PIN8 8U
+#define GPIOD_PIN9 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_PIN11 11U
+#define GPIOD_LED4 12U
+#define GPIOD_LED3 13U
+#define GPIOD_LED5 14U
+#define GPIOD_LED6 15U
+
+#define GPIOE_INT1 0U
+#define GPIOE_INT2 1U
+#define GPIOE_PIN2 2U
+#define GPIOE_CS_SPI 3U
+#define GPIOE_PIN4 4U
+#define GPIOE_PIN5 5U
+#define GPIOE_PIN6 6U
+#define GPIOE_PIN7 7U
+#define GPIOE_PIN8 8U
+#define GPIOE_PIN9 9U
+#define GPIOE_PIN10 10U
+#define GPIOE_PIN11 11U
+#define GPIOE_PIN12 12U
+#define GPIOE_PIN13 13U
+#define GPIOE_PIN14 14U
+#define GPIOE_PIN15 15U
+
+#define GPIOF_PIN0 0U
+#define GPIOF_PIN1 1U
+#define GPIOF_PIN2 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_PIN7 7U
+#define GPIOF_PIN8 8U
+#define GPIOF_PIN9 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_PIN12 12U
+#define GPIOF_PIN13 13U
+#define GPIOF_PIN14 14U
+#define GPIOF_PIN15 15U
+
+#define GPIOG_PIN0 0U
+#define GPIOG_PIN1 1U
+#define GPIOG_PIN2 2U
+#define GPIOG_PIN3 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_PIN6 6U
+#define GPIOG_PIN7 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_PIN9 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_PIN11 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_PIN13 13U
+#define GPIOG_PIN14 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+#define GPIOI_PIN0 0U
+#define GPIOI_PIN1 1U
+#define GPIOI_PIN2 2U
+#define GPIOI_PIN3 3U
+#define GPIOI_PIN4 4U
+#define GPIOI_PIN5 5U
+#define GPIOI_PIN6 6U
+#define GPIOI_PIN7 7U
+#define GPIOI_PIN8 8U
+#define GPIOI_PIN9 9U
+#define GPIOI_PIN10 10U
+#define GPIOI_PIN11 11U
+#define GPIOI_PIN12 12U
+#define GPIOI_PIN13 13U
+#define GPIOI_PIN14 14U
+#define GPIOI_PIN15 15U
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - BUTTON (input floating).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - PIN2 (input pullup).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - LRCK (alternate 6).
+ * PA5 - SPC (alternate 5).
+ * PA6 - SDO (alternate 5).
+ * PA7 - SDI (alternate 5).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - VBUS_FS (input floating).
+ * PA10 - OTG_FS_ID (alternate 10).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_PIN2) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_ALTERNATE(GPIOA_LRCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_SPC) | \
+ PIN_MODE_ALTERNATE(GPIOA_SDO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SDI) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_VBUS_FS) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \
+ PIN_OSPEED_100M(GPIOA_PIN1) | \
+ PIN_OSPEED_100M(GPIOA_PIN2) | \
+ PIN_OSPEED_100M(GPIOA_PIN3) | \
+ PIN_OSPEED_100M(GPIOA_LRCK) | \
+ PIN_OSPEED_50M(GPIOA_SPC) | \
+ PIN_OSPEED_50M(GPIOA_SDO) | \
+ PIN_OSPEED_50M(GPIOA_SDI) | \
+ PIN_OSPEED_100M(GPIOA_PIN8) | \
+ PIN_OSPEED_100M(GPIOA_VBUS_FS) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_100M(GPIOA_SWDIO) | \
+ PIN_OSPEED_100M(GPIOA_SWCLK) | \
+ PIN_OSPEED_100M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOA_LRCK) | \
+ PIN_PUPDR_FLOATING(GPIOA_SPC) | \
+ PIN_PUPDR_FLOATING(GPIOA_SDO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SDI) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_PIN2) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_LRCK) | \
+ PIN_ODR_HIGH(GPIOA_SPC) | \
+ PIN_ODR_HIGH(GPIOA_SDO) | \
+ PIN_ODR_HIGH(GPIOA_SDI) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_VBUS_FS) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_LRCK, 6) | \
+ PIN_AFIO_AF(GPIOA_SPC, 5) | \
+ PIN_AFIO_AF(GPIOA_SDO, 5) | \
+ PIN_AFIO_AF(GPIOA_SDI, 5))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - SCL (alternate 4).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - SDA (alternate 4).
+ * PB10 - CLK_IN (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_ALTERNATE(GPIOB_SCL) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_ALTERNATE(GPIOB_SDA) | \
+ PIN_MODE_INPUT(GPIOB_CLK_IN) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \
+ PIN_OSPEED_100M(GPIOB_PIN1) | \
+ PIN_OSPEED_100M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_SWO) | \
+ PIN_OSPEED_100M(GPIOB_PIN4) | \
+ PIN_OSPEED_100M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_SCL) | \
+ PIN_OSPEED_100M(GPIOB_PIN7) | \
+ PIN_OSPEED_100M(GPIOB_PIN8) | \
+ PIN_OSPEED_100M(GPIOB_SDA) | \
+ PIN_OSPEED_100M(GPIOB_CLK_IN) | \
+ PIN_OSPEED_100M(GPIOB_PIN11) | \
+ PIN_OSPEED_100M(GPIOB_PIN12) | \
+ PIN_OSPEED_100M(GPIOB_PIN13) | \
+ PIN_OSPEED_100M(GPIOB_PIN14) | \
+ PIN_OSPEED_100M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_SCL) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOB_SDA) | \
+ PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_SCL) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_SDA) | \
+ PIN_ODR_HIGH(GPIOB_CLK_IN) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_SCL, 4) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_SDA, 4) | \
+ PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - OTG_FS_POWER_ON (output pushpull maximum).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PDM_OUT (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - MCLK (alternate 6).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - SCLK (alternate 6).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - SDIN (alternate 6).
+ * PC13 - PIN13 (input pullup).
+ * PC14 - PIN14 (input pullup).
+ * PC15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PDM_OUT) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOC_MCLK) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_ALTERNATE(GPIOC_SCLK) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIN) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDIN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_OSPEED_100M(GPIOC_PIN1) | \
+ PIN_OSPEED_100M(GPIOC_PIN2) | \
+ PIN_OSPEED_100M(GPIOC_PDM_OUT) | \
+ PIN_OSPEED_100M(GPIOC_PIN4) | \
+ PIN_OSPEED_100M(GPIOC_PIN5) | \
+ PIN_OSPEED_100M(GPIOC_PIN6) | \
+ PIN_OSPEED_100M(GPIOC_MCLK) | \
+ PIN_OSPEED_100M(GPIOC_PIN8) | \
+ PIN_OSPEED_100M(GPIOC_PIN9) | \
+ PIN_OSPEED_100M(GPIOC_SCLK) | \
+ PIN_OSPEED_100M(GPIOC_PIN11) | \
+ PIN_OSPEED_100M(GPIOC_SDIN) | \
+ PIN_OSPEED_100M(GPIOC_PIN13) | \
+ PIN_OSPEED_100M(GPIOC_PIN14) | \
+ PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOC_MCLK) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOC_SCLK) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDIN) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PDM_OUT) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_MCLK) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_SCLK) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_SDIN) | \
+ PIN_ODR_HIGH(GPIOC_PIN13) | \
+ PIN_ODR_HIGH(GPIOC_PIN14) | \
+ PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_MCLK, 6))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOC_SCLK, 6) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOC_SDIN, 6) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - RESET (output pushpull maximum).
+ * PD5 - OVER_CURRENT (input floating).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - LED4 (output pushpull maximum).
+ * PD13 - LED3 (output pushpull maximum).
+ * PD14 - LED5 (output pushpull maximum).
+ * PD15 - LED6 (output pushpull maximum).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_OUTPUT(GPIOD_RESET) | \
+ PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_OUTPUT(GPIOD_LED4) | \
+ PIN_MODE_OUTPUT(GPIOD_LED3) | \
+ PIN_MODE_OUTPUT(GPIOD_LED5) | \
+ PIN_MODE_OUTPUT(GPIOD_LED6))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_LED6))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
+ PIN_OSPEED_100M(GPIOD_PIN1) | \
+ PIN_OSPEED_100M(GPIOD_PIN2) | \
+ PIN_OSPEED_100M(GPIOD_PIN3) | \
+ PIN_OSPEED_100M(GPIOD_RESET) | \
+ PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \
+ PIN_OSPEED_100M(GPIOD_PIN6) | \
+ PIN_OSPEED_100M(GPIOD_PIN7) | \
+ PIN_OSPEED_100M(GPIOD_PIN8) | \
+ PIN_OSPEED_100M(GPIOD_PIN9) | \
+ PIN_OSPEED_100M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_PIN11) | \
+ PIN_OSPEED_100M(GPIOD_LED4) | \
+ PIN_OSPEED_100M(GPIOD_LED3) | \
+ PIN_OSPEED_100M(GPIOD_LED5) | \
+ PIN_OSPEED_100M(GPIOD_LED6))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOD_RESET) | \
+ PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED4) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED3) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED5) | \
+ PIN_PUPDR_FLOATING(GPIOD_LED6))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_RESET) | \
+ PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_LOW(GPIOD_LED4) | \
+ PIN_ODR_LOW(GPIOD_LED3) | \
+ PIN_ODR_LOW(GPIOD_LED5) | \
+ PIN_ODR_LOW(GPIOD_LED6))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_RESET, 0) | \
+ PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_LED4, 0) | \
+ PIN_AFIO_AF(GPIOD_LED3, 0) | \
+ PIN_AFIO_AF(GPIOD_LED5, 0) | \
+ PIN_AFIO_AF(GPIOD_LED6, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - INT1 (input floating).
+ * PE1 - INT2 (input floating).
+ * PE2 - PIN2 (input floating).
+ * PE3 - CS_SPI (output pushpull maximum).
+ * PE4 - PIN4 (input floating).
+ * PE5 - PIN5 (input floating).
+ * PE6 - PIN6 (input floating).
+ * PE7 - PIN7 (input floating).
+ * PE8 - PIN8 (input floating).
+ * PE9 - PIN9 (input floating).
+ * PE10 - PIN10 (input floating).
+ * PE11 - PIN11 (input floating).
+ * PE12 - PIN12 (input floating).
+ * PE13 - PIN13 (input floating).
+ * PE14 - PIN14 (input floating).
+ * PE15 - PIN15 (input floating).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \
+ PIN_MODE_INPUT(GPIOE_INT2) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \
+ PIN_OSPEED_100M(GPIOE_INT2) | \
+ PIN_OSPEED_100M(GPIOE_PIN2) | \
+ PIN_OSPEED_100M(GPIOE_CS_SPI) | \
+ PIN_OSPEED_100M(GPIOE_PIN4) | \
+ PIN_OSPEED_100M(GPIOE_PIN5) | \
+ PIN_OSPEED_100M(GPIOE_PIN6) | \
+ PIN_OSPEED_100M(GPIOE_PIN7) | \
+ PIN_OSPEED_100M(GPIOE_PIN8) | \
+ PIN_OSPEED_100M(GPIOE_PIN9) | \
+ PIN_OSPEED_100M(GPIOE_PIN10) | \
+ PIN_OSPEED_100M(GPIOE_PIN11) | \
+ PIN_OSPEED_100M(GPIOE_PIN12) | \
+ PIN_OSPEED_100M(GPIOE_PIN13) | \
+ PIN_OSPEED_100M(GPIOE_PIN14) | \
+ PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \
+ PIN_PUPDR_FLOATING(GPIOE_INT2) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \
+ PIN_ODR_HIGH(GPIOE_INT2) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_CS_SPI) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \
+ PIN_AFIO_AF(GPIOE_INT2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input floating).
+ * PF1 - PIN1 (input floating).
+ * PF2 - PIN2 (input floating).
+ * PF3 - PIN3 (input floating).
+ * PF4 - PIN4 (input floating).
+ * PF5 - PIN5 (input floating).
+ * PF6 - PIN6 (input floating).
+ * PF7 - PIN7 (input floating).
+ * PF8 - PIN8 (input floating).
+ * PF9 - PIN9 (input floating).
+ * PF10 - PIN10 (input floating).
+ * PF11 - PIN11 (input floating).
+ * PF12 - PIN12 (input floating).
+ * PF13 - PIN13 (input floating).
+ * PF14 - PIN14 (input floating).
+ * PF15 - PIN15 (input floating).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
+ PIN_OSPEED_100M(GPIOF_PIN1) | \
+ PIN_OSPEED_100M(GPIOF_PIN2) | \
+ PIN_OSPEED_100M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_PIN4) | \
+ PIN_OSPEED_100M(GPIOF_PIN5) | \
+ PIN_OSPEED_100M(GPIOF_PIN6) | \
+ PIN_OSPEED_100M(GPIOF_PIN7) | \
+ PIN_OSPEED_100M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_PIN9) | \
+ PIN_OSPEED_100M(GPIOF_PIN10) | \
+ PIN_OSPEED_100M(GPIOF_PIN11) | \
+ PIN_OSPEED_100M(GPIOF_PIN12) | \
+ PIN_OSPEED_100M(GPIOF_PIN13) | \
+ PIN_OSPEED_100M(GPIOF_PIN14) | \
+ PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input floating).
+ * PG1 - PIN1 (input floating).
+ * PG2 - PIN2 (input floating).
+ * PG3 - PIN3 (input floating).
+ * PG4 - PIN4 (input floating).
+ * PG5 - PIN5 (input floating).
+ * PG6 - PIN6 (input floating).
+ * PG7 - PIN7 (input floating).
+ * PG8 - PIN8 (input floating).
+ * PG9 - PIN9 (input floating).
+ * PG10 - PIN10 (input floating).
+ * PG11 - PIN11 (input floating).
+ * PG12 - PIN12 (input floating).
+ * PG13 - PIN13 (input floating).
+ * PG14 - PIN14 (input floating).
+ * PG15 - PIN15 (input floating).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_INPUT(GPIOG_PIN11) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_INPUT(GPIOG_PIN13) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
+ PIN_OSPEED_100M(GPIOG_PIN1) | \
+ PIN_OSPEED_100M(GPIOG_PIN2) | \
+ PIN_OSPEED_100M(GPIOG_PIN3) | \
+ PIN_OSPEED_100M(GPIOG_PIN4) | \
+ PIN_OSPEED_100M(GPIOG_PIN5) | \
+ PIN_OSPEED_100M(GPIOG_PIN6) | \
+ PIN_OSPEED_100M(GPIOG_PIN7) | \
+ PIN_OSPEED_100M(GPIOG_PIN8) | \
+ PIN_OSPEED_100M(GPIOG_PIN9) | \
+ PIN_OSPEED_100M(GPIOG_PIN10) | \
+ PIN_OSPEED_100M(GPIOG_PIN11) | \
+ PIN_OSPEED_100M(GPIOG_PIN12) | \
+ PIN_OSPEED_100M(GPIOG_PIN13) | \
+ PIN_OSPEED_100M(GPIOG_PIN14) | \
+ PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input floating).
+ * PH3 - PIN3 (input floating).
+ * PH4 - PIN4 (input floating).
+ * PH5 - PIN5 (input floating).
+ * PH6 - PIN6 (input floating).
+ * PH7 - PIN7 (input floating).
+ * PH8 - PIN8 (input floating).
+ * PH9 - PIN9 (input floating).
+ * PH10 - PIN10 (input floating).
+ * PH11 - PIN11 (input floating).
+ * PH12 - PIN12 (input floating).
+ * PH13 - PIN13 (input floating).
+ * PH14 - PIN14 (input floating).
+ * PH15 - PIN15 (input floating).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_100M(GPIOH_PIN2) | \
+ PIN_OSPEED_100M(GPIOH_PIN3) | \
+ PIN_OSPEED_100M(GPIOH_PIN4) | \
+ PIN_OSPEED_100M(GPIOH_PIN5) | \
+ PIN_OSPEED_100M(GPIOH_PIN6) | \
+ PIN_OSPEED_100M(GPIOH_PIN7) | \
+ PIN_OSPEED_100M(GPIOH_PIN8) | \
+ PIN_OSPEED_100M(GPIOH_PIN9) | \
+ PIN_OSPEED_100M(GPIOH_PIN10) | \
+ PIN_OSPEED_100M(GPIOH_PIN11) | \
+ PIN_OSPEED_100M(GPIOH_PIN12) | \
+ PIN_OSPEED_100M(GPIOH_PIN13) | \
+ PIN_OSPEED_100M(GPIOH_PIN14) | \
+ PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input floating).
+ * PI1 - PIN1 (input floating).
+ * PI2 - PIN2 (input floating).
+ * PI3 - PIN3 (input floating).
+ * PI4 - PIN4 (input floating).
+ * PI5 - PIN5 (input floating).
+ * PI6 - PIN6 (input floating).
+ * PI7 - PIN7 (input floating).
+ * PI8 - PIN8 (input floating).
+ * PI9 - PIN9 (input floating).
+ * PI10 - PIN10 (input floating).
+ * PI11 - PIN11 (input floating).
+ * PI12 - PIN12 (input floating).
+ * PI13 - PIN13 (input floating).
+ * PI14 - PIN14 (input floating).
+ * PI15 - PIN15 (input floating).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
+ PIN_OSPEED_100M(GPIOI_PIN1) | \
+ PIN_OSPEED_100M(GPIOI_PIN2) | \
+ PIN_OSPEED_100M(GPIOI_PIN3) | \
+ PIN_OSPEED_100M(GPIOI_PIN4) | \
+ PIN_OSPEED_100M(GPIOI_PIN5) | \
+ PIN_OSPEED_100M(GPIOI_PIN6) | \
+ PIN_OSPEED_100M(GPIOI_PIN7) | \
+ PIN_OSPEED_100M(GPIOI_PIN8) | \
+ PIN_OSPEED_100M(GPIOI_PIN9) | \
+ PIN_OSPEED_100M(GPIOI_PIN10) | \
+ PIN_OSPEED_100M(GPIOI_PIN11) | \
+ PIN_OSPEED_100M(GPIOI_PIN12) | \
+ PIN_OSPEED_100M(GPIOI_PIN13) | \
+ PIN_OSPEED_100M(GPIOI_PIN14) | \
+ PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile b/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile
index 2512c62a..755b8cf9 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile
+++ b/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile
@@ -19,12 +19,13 @@
# ChibiOS settings
ifeq ($(OPT_OS),chibios)
- # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables
- CHIBIOS = ../ChibiOS
- CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
- CHIBIOS_PLATFORM = STM32F4xx
- CHIBIOS_PORT = GCC/ARMCMx/STM32F4xx
- CHIBIOS_LDSCRIPT = STM32F407xG.ld
+ # See $(GFXLIB)/tools/gmake_scripts/os_chibios_2.mk for the list of variables
+ CHIBIOS = ../ChibiOS
+ CHIBIOS_VERSION = 2
+ CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
+ CHIBIOS_PLATFORM = STM32F4xx
+ CHIBIOS_PORT = GCC/ARMCMx/STM32F4xx
+ CHIBIOS_LDSCRIPT = STM32F429xI.ld
endif
##############################################################################################
--
cgit v1.2.3
From 4eb0dbb1e3b8be7eb85c8830ef350d4dae021f87 Mon Sep 17 00:00:00 2001
From: Joel Bodenmann <joel@seriouslyembedded.com>
Date: Sat, 29 Aug 2015 17:16:21 +0200
Subject: Updating ChibiOS 3.x build system support
---
.../example_chibios_2.x/Makefile | 2 +-
.../example_chibios_3.x/Makefile | 2 +-
.../example_chibios_2.x/Makefile | 2 +-
.../example_chibios_3.x/Makefile | 6 +++---
.../example_chibios_3.x/halconf.h | 6 +++---
.../example_chibios_3.x/mcuconf.h | 21 ++++++++++++++++++---
tools/gmake_scripts/os_chibios_2.mk | 18 +++++++++++++-----
7 files changed, 40 insertions(+), 17 deletions(-)
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile
index 4fcda523..a9ba950b 100644
--- a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_2.x/Makefile
@@ -8,7 +8,7 @@
# See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables
OPT_OS = chibios
OPT_THUMB = yes
- OPT_LINK_OPTIMIZE = yes
+ OPT_LINK_OPTIMIZE = no
OPT_CPU = stm32m4
# uGFX settings
diff --git a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
index d4cc3001..31ce961c 100644
--- a/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
+++ b/boards/base/Embest-STM32-DMSTF4BB/example_chibios_3.x/Makefile
@@ -8,7 +8,7 @@
# See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables
OPT_OS = chibios
OPT_THUMB = yes
- OPT_LINK_OPTIMIZE = yes
+ OPT_LINK_OPTIMIZE = no
OPT_CPU = stm32m4
# uGFX settings
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile b/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile
index 755b8cf9..6c1bb94c 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile
+++ b/boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile
@@ -8,7 +8,7 @@
# See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables
OPT_OS = chibios
OPT_THUMB = yes
- OPT_LINK_OPTIMIZE = yes
+ OPT_LINK_OPTIMIZE = no
OPT_CPU = stm32m4
# uGFX settings
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile b/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile
index 16611673..d7ee1d20 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile
+++ b/boards/base/STM32F429i-Discovery/example_chibios_3.x/Makefile
@@ -8,19 +8,19 @@
# See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables
OPT_OS = chibios
OPT_THUMB = yes
- OPT_LINK_OPTIMIZE = yes
+ OPT_LINK_OPTIMIZE = no
OPT_CPU = stm32m4
# uGFX settings
# See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
- GFXLIB = ../../resources/ugfx
+ GFXLIB = ../path/to/ugfx
GFXBOARD = STM32F429i-Discovery
GFXDEMO = modules/gdisp/basics
# ChibiOS settings
ifeq ($(OPT_OS),chibios)
# See $(GFXLIB)/tools/gmake_scripts/os_chibios_x.mk for the list of variables
- CHIBIOS = ../../resources/chibios_3.0.1
+ CHIBIOS = ../path/to/chibios_3
CHIBIOS_VERSION = 3
CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
CHIBIOS_CPUCLASS = ARMCMx
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h b/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h
index 6f80a255..4457240f 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h
+++ b/boards/base/STM32F429i-Discovery/example_chibios_3.x/halconf.h
@@ -132,7 +132,7 @@
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL TRUE
+#define HAL_USE_SERIAL FALSE
#endif
/**
@@ -146,7 +146,7 @@
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
-#define HAL_USE_SPI FALSE
+#define HAL_USE_SPI TRUE
#endif
/**
@@ -160,7 +160,7 @@
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
-#define HAL_USE_USB TRUE
+#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
diff --git a/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h b/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h
index 80417b89..6ce56da0 100644
--- a/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h
+++ b/boards/base/STM32F429i-Discovery/example_chibios_3.x/mcuconf.h
@@ -233,7 +233,7 @@
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
-#define STM32_SERIAL_USE_USART2 TRUE
+#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
@@ -251,18 +251,33 @@
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_USE_SPI4 FALSE
+#define STM32_SPI_USE_SPI5 TRUE
+#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@@ -309,8 +324,8 @@
/*
* USB driver system settings.
*/
-#define STM32_USB_USE_OTG1 TRUE
-#define STM32_USB_USE_OTG2 FALSE
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_USE_OTG2 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
diff --git a/tools/gmake_scripts/os_chibios_2.mk b/tools/gmake_scripts/os_chibios_2.mk
index 299f42ec..ffbbc3f5 100644
--- a/tools/gmake_scripts/os_chibios_2.mk
+++ b/tools/gmake_scripts/os_chibios_2.mk
@@ -60,13 +60,21 @@ ifeq ($(CHIBIOS_STM32LIB),yes)
INCPATH += $(STM32INC)
endif
-INCPATH += $(PORTINC) $(KERNINC) $(OSALINC) \
- $(HALINC) $(PLATFORMINC) $(BOARDINC)
+# Add include files
+INCPATH += $(PORTINC) \
+ $(KERNINC) \
+ $(OSALINC) \
+ $(HALINC) \
+ $(PLATFORMINC) \
+ $(BOARDINC)
-SRC += $(PORTSRC) \
+# Add C files
+SRC += $(PORTSRC) \
$(KERNSRC) \
$(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
- $(OSALSRC) \
- $(PORTASM)
+ $(OSALSRC)
+
+# Add ASM files
+SRC += $(PORTASM)
--
cgit v1.2.3
From 0ab22283645c819dc6228356ed1b608904a6ba9a Mon Sep 17 00:00:00 2001
From: inmarket <andrewh@inmarket.com.au>
Date: Fri, 18 Sep 2015 11:17:19 +1000
Subject: Add support for SH1106 in the SSD1306 driver
---
drivers/gdisp/SSD1306/SSD1306.h | 3 +++
drivers/gdisp/SSD1306/gdisp_lld_SSD1306.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gdisp/SSD1306/SSD1306.h b/drivers/gdisp/SSD1306/SSD1306.h
index 7d7010e8..8ec8b3ad 100644
--- a/drivers/gdisp/SSD1306/SSD1306.h
+++ b/drivers/gdisp/SSD1306/SSD1306.h
@@ -44,6 +44,9 @@
#define SSD1306_EXTERNALVCC 0x1
#define SSD1306_SWITCHCAPVCC 0x2
+#define SSD1306_SETLOWCOLUMN 0x00
+#define SSD1306_SETHIGHCOLUMN 0x10
+
// Scrolling #defines
#define SSD1306_SCROLL_ACTIVATE 0x2F
#define SSD1306_SCROLL_DEACTIVATE 0x2E
diff --git a/drivers/gdisp/SSD1306/gdisp_lld_SSD1306.c b/drivers/gdisp/SSD1306/gdisp_lld_SSD1306.c
index 2313e765..5a950b0d 100644
--- a/drivers/gdisp/SSD1306/gdisp_lld_SSD1306.c
+++ b/drivers/gdisp/SSD1306/gdisp_lld_SSD1306.c
@@ -150,6 +150,12 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
write_cmd(g, SSD1306_SETSTARTLINE | 0);
while (pages--) {
+ #if SSD1306_SH1106
+ write_cmd(g, SSD1306_PAM_PAGE_START + (7 - pages));
+ write_cmd(g, SSD1306_SETLOWCOLUMN + 2);
+ write_cmd(g, SSD1306_SETHIGHCOLUMN);
+ #endif
+
write_data(g, ram, SSD1306_PAGE_WIDTH);
ram += SSD1306_PAGE_WIDTH;
}
--
cgit v1.2.3