diff options
Diffstat (limited to 'boards')
13 files changed, 2544 insertions, 85 deletions
diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk index 9386fae0..d12b4016 100644 --- a/boards/base/STM32F746-Discovery/board.mk +++ b/boards/base/STM32F746-Discovery/board.mk @@ -1,9 +1,12 @@ -GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery +GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery \ + $(STMHAL)/Inc GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c -GFXDEFS += STM32F746xx + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c \ + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c ifeq ($(OPT_OS),raw32) + HAL = $(STMHAL) + GFXDEFS += STM32F746xx GFXSRC += $(HAL)/Src/stm32f7xx_hal.c \ $(HAL)/Src/stm32f7xx_hal_cortex.c \ $(HAL)/Src/stm32f7xx_hal_flash.c \ @@ -18,13 +21,12 @@ ifeq ($(OPT_OS),raw32) GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s \ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c \ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c GFXDEFS += GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit GFX_OS_INIT_NO_WARNING=TRUE SRCFLAGS+= -std=c99 GFXINC += $(CMSIS)/Device/ST/STM32F7xx/Include \ $(CMSIS)/Include \ - $(HAL)/Inc + $(STMHAL)/Inc LDSCRIPT = $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld endif diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h index ffe28e02..1bf3dec8 100644 --- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h +++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h @@ -12,6 +12,11 @@ #include "stm32f746g_discovery_sdram.h" #include <string.h> +#if !GFX_USE_OS_CHIBIOS + #define AFRL AFR[0] + #define AFRH AFR[1] +#endif + static const ltdcConfig driverCfg = { 480, 272, // Width, Height (pixels) 41, 10, // Horizontal, Vertical sync (pixels) @@ -55,181 +60,181 @@ static void configureLcdPins(void) GPIOI->MODER |= GPIO_MODER_MODER15_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_15; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1; - GPIOI->AFR[1] |= (0b1110 << 4*7); + GPIOI->AFRH |= (0b1110 << 4*7); // PJ0: LCD_R1 GPIOJ->MODER |= GPIO_MODER_MODER0_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_0; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1; - GPIOJ->AFR[0] |= (0b1110 << 4*0); + GPIOJ->AFRL |= (0b1110 << 4*0); // PJ1: LCD_R2 GPIOJ->MODER |= GPIO_MODER_MODER1_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_1; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1; - GPIOJ->AFR[0] |= (0b1110 << 4*1); + GPIOJ->AFRL |= (0b1110 << 4*1); // PJ2: LCD_R3 GPIOJ->MODER |= GPIO_MODER_MODER2_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_2; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1; - GPIOJ->AFR[0] |= (0b1110 << 4*2); + GPIOJ->AFRL |= (0b1110 << 4*2); // PJ3: LCD_R4 GPIOJ->MODER |= GPIO_MODER_MODER3_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_3; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1; - GPIOJ->AFR[0] |= (0b1110 << 4*3); + GPIOJ->AFRL |= (0b1110 << 4*3); // PJ4: LCD_R5 GPIOJ->MODER |= GPIO_MODER_MODER4_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_4; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1; - GPIOJ->AFR[0] |= (0b1110 << 4*4); + GPIOJ->AFRL |= (0b1110 << 4*4); // PJ5: LCD_R6 GPIOJ->MODER |= GPIO_MODER_MODER5_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_5; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1; - GPIOJ->AFR[0] |= (0b1110 << 4*5); + GPIOJ->AFRL |= (0b1110 << 4*5); // PJ6: LCD_R7 GPIOJ->MODER |= GPIO_MODER_MODER6_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_6; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1; - GPIOJ->AFR[0] |= (0b1110 << 4*6); + GPIOJ->AFRL |= (0b1110 << 4*6); // PJ7: LCD_G0 GPIOJ->MODER |= GPIO_MODER_MODER7_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_7; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1; - GPIOJ->AFR[0] |= (0b1110 << 4*7); + GPIOJ->AFRL |= (0b1110 << 4*7); // PJ8: LCD_G1 GPIOJ->MODER |= GPIO_MODER_MODER8_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_8; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1; - GPIOJ->AFR[1] |= (0b1110 << 4*0); + GPIOJ->AFRH |= (0b1110 << 4*0); // PJ9: LCD_G2 GPIOJ->MODER |= GPIO_MODER_MODER9_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_9; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1; - GPIOJ->AFR[1] |= (0b1110 << 4*1); + GPIOJ->AFRH |= (0b1110 << 4*1); // PJ10: LCD_G3 GPIOJ->MODER |= GPIO_MODER_MODER10_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_10; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1; - GPIOJ->AFR[1] |= (0b1110 << 4*2); + GPIOJ->AFRH |= (0b1110 << 4*2); // PJ11: LCD_G4 GPIOJ->MODER |= GPIO_MODER_MODER11_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_11; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR11_0 | GPIO_OSPEEDER_OSPEEDR11_1; - GPIOJ->AFR[1] |= (0b1110 << 4*3); + GPIOJ->AFRH |= (0b1110 << 4*3); // PK0: LCD_G5 GPIOK->MODER |= GPIO_MODER_MODER0_0; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_0; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1; - GPIOK->AFR[0] |= (0b1110 << 4*0); + GPIOK->AFRL |= (0b1110 << 4*0); // PK1: LCD_G6 GPIOK->MODER |= GPIO_MODER_MODER1_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_1; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1; - GPIOK->AFR[0] |= (0b1110 << 4*1); + GPIOK->AFRL |= (0b1110 << 4*1); // PK2: LCD_G7 GPIOK->MODER |= GPIO_MODER_MODER2_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_2; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1; - GPIOK->AFR[0] |= (0b1110 << 4*2); + GPIOK->AFRL |= (0b1110 << 4*2); // PE4: LCD_B0 GPIOE->MODER |= GPIO_MODER_MODER4_1; GPIOE->OTYPER &=~ GPIO_OTYPER_OT_4; GPIOE->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1; - GPIOE->AFR[0] |= (0b1110 << 4*4); + GPIOE->AFRL |= (0b1110 << 4*4); // PJ13: LCD_B1 GPIOJ->MODER |= GPIO_MODER_MODER13_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_13; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1; - GPIOJ->AFR[1] |= (0b1110 << 4*5); + GPIOJ->AFRH |= (0b1110 << 4*5); // PJ14: LCD_B2 GPIOJ->MODER |= GPIO_MODER_MODER14_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_14; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1; - GPIOJ->AFR[1] |= (0b1110 << 4*6); + GPIOJ->AFRH |= (0b1110 << 4*6); // PJ15: LCD_B3 GPIOJ->MODER |= GPIO_MODER_MODER15_1; GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_15; GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1; - GPIOJ->AFR[1] |= (0b1110 << 4*7); + GPIOJ->AFRH |= (0b1110 << 4*7); // PG12: LCD_B4 GPIOG->MODER |= GPIO_MODER_MODER12_1; GPIOG->OTYPER &=~ GPIO_OTYPER_OT_12; GPIOG->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1; - GPIOG->AFR[1] |= (0b1110 << 4*4); + GPIOG->AFRH |= (0b1110 << 4*4); // PK4: LCD_B5 GPIOK->MODER |= GPIO_MODER_MODER4_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_4; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1; - GPIOK->AFR[0] |= (0b1110 << 4*4); + GPIOK->AFRL |= (0b1110 << 4*4); // PK5: LCD_B6 GPIOK->MODER |= GPIO_MODER_MODER5_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_5; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1; - GPIOK->AFR[0] |= (0b1110 << 4*5); + GPIOK->AFRL |= (0b1110 << 4*5); // PK6: LCD_B7 GPIOK->MODER |= GPIO_MODER_MODER6_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_6; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1; - GPIOK->AFR[0] |= (0b1110 << 4*6); + GPIOK->AFRL |= (0b1110 << 4*6); // PK7: LCD_DE GPIOK->MODER |= GPIO_MODER_MODER7_1; GPIOK->OTYPER &=~ GPIO_OTYPER_OT_7; GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1; - GPIOK->AFR[0] |= (0b1110 << 4*7); + GPIOK->AFRL |= (0b1110 << 4*7); // PI9: LCD_VSYNC GPIOI->MODER |= GPIO_MODER_MODER9_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_9; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1; - GPIOI->AFR[1] |= (0b1110 << 4*1); + GPIOI->AFRH |= (0b1110 << 4*1); // PI10: LCD_VSYNC GPIOI->MODER |= GPIO_MODER_MODER10_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_10; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1; - GPIOI->AFR[1] |= (0b1110 << 4*2); + GPIOI->AFRH |= (0b1110 << 4*2); // PI13: LCD_INT GPIOI->MODER |= GPIO_MODER_MODER13_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_13; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1; - GPIOI->AFR[1] |= (0b1110 << 4*5); + GPIOI->AFRH |= (0b1110 << 4*5); // PI14: LCD_CLK GPIOI->MODER |= GPIO_MODER_MODER14_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_14; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1; - GPIOI->AFR[1] |= (0b1110 << 4*6); + GPIOI->AFRH |= (0b1110 << 4*6); // PI8: ??? GPIOI->MODER |= GPIO_MODER_MODER8_1; GPIOI->OTYPER &=~ GPIO_OTYPER_OT_8; GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1; - GPIOI->AFR[1] |= (0b1110 << 4*0); + GPIOI->AFRH |= (0b1110 << 4*0); // PI12: LCD_DISP_PIN GPIOI->MODER |= GPIO_MODER_MODER12_0; @@ -270,7 +275,9 @@ static inline void init_board(GDisplay *g) { // PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz // LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz #define STM32_PLLSAIN_VALUE 192 + #undef STM32_PLLSAIQ_VALUE #define STM32_PLLSAIQ_VALUE 7 + #undef STM32_PLLSAIR_VALUE #define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER #define STM32_PLLSAIR_POST STM32_SAIR_DIV4 RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); diff --git a/boards/base/STM32F746-Discovery/example_chibios3/Makefile b/boards/base/STM32F746-Discovery/example_chibios3/Makefile new file mode 100644 index 00000000..d7414ef2 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/Makefile @@ -0,0 +1,72 @@ +# Possible Targets: all clean Debug cleanDebug Release cleanRelease + +############################################################################################## +# Settings +# + +# General settings + # See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables + OPT_OS = chibios + OPT_THUMB = yes + OPT_LINK_OPTIMIZE = no + OPT_CPU = stm32m7 + +# uGFX settings + # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables + GFXLIB = ../ugfx + GFXBOARD = STM32F746-Discovery + GFXDEMO = modules/gdisp/streaming + #GFXDRIVERS = + GFXSINGLEMAKE = no + +# ChibiOS settings +ifeq ($(OPT_OS),chibios) + # See $(GFXLIB)/tools/gmake_scripts/os_chibios_3.mk for the list of variables + CHIBIOS = ../ChibiOS-Master + CHIBIOS_VERSION = 3 + CHIBIOS_CPUCLASS = ARMCMx + CHIBIOS_PLATFORM = STM32 + CHIBIOS_DEVICE_FAMILY = STM32F7xx + CHIBIOS_STARTUP = startup_stm32f7xx + CHIBIOS_PORT = v7m + CHIBIOS_LDSCRIPT = STM32F746xG.ld + CHIBIOS_BOARD = ST_STM32F746G_DISCOVERY + #CHIBIOS_PROCESS_STACKSIZE = 0x400 + #CHIBIOS_EXCEPTIONS_STACKSIZE = 0x400 +endif + +#Special - Required for the drivers for this discovery board. +STMHAL = ../STM32/STM32F7xx_HAL_Driver + +#Special - Required for Raw32 +CMSIS = ../STM32/CMSIS + +############################################################################################## +# Set these for your project +# + +ARCH = arm-none-eabi- +SRCFLAGS = -ggdb -O1 +CFLAGS = +CXXFLAGS = -fno-rtti +ASFLAGS = +LDFLAGS = + +SRC = + +OBJS = +DEFS = GFX_OS_HEAP_SIZE=40960 +LIBS = +INCPATH = + +LIBPATH = +LDSCRIPT = + +############################################################################################## +# These should be at the end +# + +include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk +include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk +include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk +# *** EOF *** diff --git a/boards/base/STM32F746-Discovery/example_chibios3/chconf.h b/boards/base/STM32F746-Discovery/example_chibios3/chconf.h new file mode 100644 index 00000000..c19b8b90 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/chconf.h @@ -0,0 +1,501 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_TRACE FALSE + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/boards/base/STM32F746-Discovery/example_chibios3/halconf.h b/boards/base/STM32F746-Discovery/example_chibios3/halconf.h new file mode 100644 index 00000000..27dd1ac9 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/halconf.h @@ -0,0 +1,334 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/boards/base/STM32F746-Discovery/example_chibios3/mcuconf.h b/boards/base/STM32F746-Discovery/example_chibios3/mcuconf.h new file mode 100644 index 00000000..068c1764 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/mcuconf.h @@ -0,0 +1,381 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 7 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +#endif /* _MCUCONF_H_ */ diff --git a/boards/base/STM32F746-Discovery/example_chibios3/openocd.cfg b/boards/base/STM32F746-Discovery/example_chibios3/openocd.cfg new file mode 100644 index 00000000..e2d732a4 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/openocd.cfg @@ -0,0 +1,94 @@ +# This is a script file for OpenOCD ?.?.? +# +# It is set up for the STM32F749-Discovery board using the ST-Link JTAG adaptor. +# +# Assuming the current directory is your project directory containing this openocd.cfg file... +# +# To program your device: +# +# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown +# +# To debug your device: +# +# openocd +# (This will run openocd in gdb server debug mode. Leave it running in the background) +# +# gdb yourfile.elf +# (To start gdb. Then run the following commands in gdb...) +# +# target remote 127.0.0.1:3333 +# monitor Debug +# stepi +# (This last stepi resynchronizes gdb). +# +# If you want to reprogram from within gdb: +# +# monitor Burn yourfile.bin +# + +echo "" +echo "##### Loading debugger..." +source [find interface/stlink-v2-1.cfg] + +echo "" +echo "##### Loading CPU..." +source [find target/stm32f7x.cfg] + +echo "" +echo "##### Configuring..." +#reset_config srst_only srst_nogate +#cortex_m maskisr (auto|on|off) +#cortex_m vector_catch [all|none|list] +#cortex_m reset_config (srst|sysresetreq|vectreset) +#gdb_breakpoint_override hard + +proc Debug { } { + echo "" + echo "##### Debug Session Connected..." + reset init + echo "Ready..." +} + +proc Burn {file} { + echo "" + echo "##### Burning $file to device..." + halt + # Due to an issue with the combination of the ST-Link adapters and OpenOCD + # applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD! + # If this happens to you - use the ST-Link utility to set the option byte back to normal. + # If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below. + #stm32f2x unlock 0 + #flash protect 0 0 last off + reset halt + flash write_image erase $file 0 elf + verify_image $file 0x0 elf + #flash protect 0 0 last on + reset + echo "Burning Complete!" +} + +echo "" +echo "##### Leaving Configuration Mode..." +init +reset init +flash probe 0 +flash banks +#flash info 0 + +echo "" +echo "##### Waiting for debug connections..." + +##### OLD ###### +#source [find interface/stlink-v2-1.cfg] +#source [find target/stm32f7x.cfg] +# +#proc flash_chip {} { +# halt +# reset halt +# flash write_image erase main.elf 0 elf +# verify_image main.elf 0 elf +# reset +# shutdown +#} +# +#init diff --git a/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..765e1377 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h @@ -0,0 +1,418 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SDRAM_MODULE_ENABLED +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/example_raw32/Makefile b/boards/base/STM32F746-Discovery/example_raw32/Makefile index dee0f01a..b0f8344a 100644 --- a/boards/base/STM32F746-Discovery/example_raw32/Makefile +++ b/boards/base/STM32F746-Discovery/example_raw32/Makefile @@ -15,38 +15,38 @@ # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables GFXLIB = ../ugfx GFXBOARD = STM32F746-Discovery - GFXDEMO = modules/gdisp/basics + GFXDEMO = modules/gdisp/streaming #GFXDRIVERS = + GFXSINGLEMAKE = no # ChibiOS settings -# Note: not supported by ChibiOS yet! ifeq ($(OPT_OS),chibios) - # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables - CHIBIOS = ../ChibiOS - CHIBIOS_BOARD = ST_STM32F746_DISCOVERY - CHIBIOS_PLATFORM = STM32F7xx - CHIBIOS_PORT = GCC/ARMCMx/STM32F7xx - CHIBIOS_LDSCRIPT = STM32F746.ld - - #CHIBIOS = ../ChibiOS3 - #CHIBIOS_VERSION = 3 - #CHIBIOS_BOARD = ST_STM32F746_DISCOVERY - #CHIBIOS_CPUCLASS = ARMCMx - #CHIBIOS_PLATFORM = STM32/STM32F7xx - #CHIBIOS_PORT = stm32f7xx - #CHIBIOS_LDSCRIPT = STM32F746.ld + # See $(GFXLIB)/tools/gmake_scripts/os_chibios_3.mk for the list of variables + CHIBIOS = ../ChibiOS-Master + CHIBIOS_VERSION = 3 + CHIBIOS_CPUCLASS = ARMCMx + CHIBIOS_PLATFORM = STM32 + CHIBIOS_DEVICE_FAMILY = STM32F7xx + CHIBIOS_STARTUP = startup_stm32f7xx + CHIBIOS_PORT = v7m + CHIBIOS_LDSCRIPT = STM32F746xG.ld + CHIBIOS_BOARD = ST_STM32F746G_DISCOVERY + #CHIBIOS_PROCESS_STACKSIZE = 0x400 + #CHIBIOS_EXCEPTIONS_STACKSIZE = 0x400 endif -# Raw32 settings +#Special - Required for the drivers for this discovery board. +STMHAL = ../STM32/STM32F7xx_HAL_Driver + +#Special - Required for Raw32 CMSIS = ../STM32/CMSIS -HAL = ../STM32/STM32F7xx_HAL_Driver ############################################################################################## # Set these for your project # ARCH = arm-none-eabi- -SRCFLAGS = -ggdb -O0 +SRCFLAGS = -ggdb -O1 CFLAGS = CXXFLAGS = -fno-rtti ASFLAGS = @@ -55,7 +55,7 @@ LDFLAGS = SRC = OBJS = -DEFS = GFX_OS_HEAP_SIZE=40960 +DEFS = GFX_OS_HEAP_SIZE=40960 LIBS = INCPATH = diff --git a/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h index 8031eca5..1e3e6877 100644 --- a/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h +++ b/boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h @@ -25,6 +25,11 @@ // The FT5336 I2C slave address (including the R/W bit) #define FT5336_SLAVE_ADDR 0x70 +#if !GFX_USE_OS_CHIBIOS + #define AFRL AFR[0] + #define AFRH AFR[1] +#endif + static bool_t init_board(GMouse* m, unsigned instance) { (void)m; @@ -35,14 +40,14 @@ static bool_t init_board(GMouse* m, unsigned instance) GPIOH->MODER |= GPIO_MODER_MODER7_1; // Alternate function GPIOH->OTYPER |= GPIO_OTYPER_OT_7; // OpenDrain GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR7; // LowSpeed - GPIOH->AFR[0] |= (0b0100 << 4*7); // AF4 + GPIOH->AFRL |= (0b0100 << 4*7); // AF4 // I2C3_SDA GPIOH8, alternate, opendrain, highspeed RCC->AHB1ENR |= RCC_AHB1ENR_GPIOHEN; // Enable clock GPIOH->MODER |= GPIO_MODER_MODER8_1; // Alternate function GPIOH->OTYPER |= GPIO_OTYPER_OT_8; // OpenDrain GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR8; // LowSpeed - GPIOH->AFR[1] |= (0b0100 << 4*0); // AF4 + GPIOH->AFRH |= (0b0100 << 4*0); // AF4 // Initialize the I2C3 peripheral if (!(i2cInit(I2C3))) { diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c index bf22b342..6f921492 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c @@ -80,6 +80,11 @@ #include "stm32f746g_discovery_sdram.h" #include "stm32f7xx_hal_rcc.h" #include "stm32f7xx_hal_rcc_ex.h" +#include "stm32f7xx_hal_cortex.h" + +#if GFX_USE_OS_CHIBIOS + #define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7)) +#endif /** @addtogroup BSP * @{ @@ -135,6 +140,49 @@ static FMC_SDRAM_CommandTypeDef Command; * @{ */ +static HAL_StatusTypeDef _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + /* Check the SDRAM handle parameter */ + if(hsdram == NULL) + { + return HAL_ERROR; + } + + if(hsdram->State == HAL_SDRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Initialize SDRAM control Interface */ + FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + + /* Initialize SDRAM timing Interface */ + FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Configure the SDRAM registers with their reset values */ + FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + + /* Reset the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + /** * @brief Initializes the SDRAM device. * @retval SDRAM status @@ -169,7 +217,7 @@ uint8_t BSP_SDRAM_Init(void) BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ - if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) + if(_HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) { sdramstatus = SDRAM_ERROR; } @@ -194,7 +242,7 @@ uint8_t BSP_SDRAM_DeInit(void) /* SDRAM device de-initialization */ sdramHandle.Instance = FMC_SDRAM_DEVICE; - if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) + if(_HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) { sdramstatus = SDRAM_ERROR; } @@ -209,6 +257,559 @@ uint8_t BSP_SDRAM_DeInit(void) return sdramstatus; } +static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + + /* Update the SDRAM controller state state */ + if(Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + if(hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Read data from source */ + for(; BufferSize != 0; BufferSize--) + { + *pDstBuffer = *(__IO uint32_t *)pSdramAddress; + pDstBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* the FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + return HAL_ERROR; + } + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = (uint32_t)0x00000021; + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +static void _HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Transfer Error Interrupt management ***************************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); + + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + /* FIFO Error Interrupt management ******************************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + { + /* Disable the FIFO Error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE); + + /* Clear the FIFO error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + { + /* Disable the direct mode Error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME); + + /* Clear the direct mode error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) + { + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; + } + /* Current memory buffer used is Memory 1 */ + else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) + { + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Current memory buffer used is Memory 1 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == 0) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 0 */ + else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + /* Disable the transfer complete interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_NONE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY_MEM0; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } +} + +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +static HAL_StatusTypeDef _HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Process locked */ + __HAL_LOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); + + /* Enable the Half transfer complete interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + + /* Enable the transfer Error interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); + + /* Enable the FIFO Error interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE); + + /* Enable the direct mode Error interrupt */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +{ + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if(tmp == HAL_SDRAM_STATE_PRECHARGED) + { + return HAL_ERROR; + } + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + _HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Write data to memory */ + for(; BufferSize != 0; BufferSize--) + { + *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; + pSrcBuffer++; + pSdramAddress++; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +static HAL_StatusTypeDef _HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +{ + uint32_t tmp = 0; + + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Check the SDRAM controller state */ + tmp = hsdram->State; + + if(tmp == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + return HAL_ERROR; + } + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Enable the DMA Stream */ + _HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + /** * @brief Programs the SDRAM device. * @param RefreshCount: SDRAM refresh counter value @@ -225,11 +826,11 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) Command.ModeRegisterDefinition = 0; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); /* Step 2: Insert 100 us minimum delay */ /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ - HAL_Delay(1); + gfxSleepMilliseconds(1); /* Step 3: Configure a PALL (precharge all) command */ Command.CommandMode = FMC_SDRAM_CMD_PALL; @@ -238,7 +839,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) Command.ModeRegisterDefinition = 0; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); /* Step 4: Configure an Auto Refresh command */ Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; @@ -247,7 +848,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) Command.ModeRegisterDefinition = 0; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); /* Step 5: Program the external memory mode register */ tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ @@ -262,11 +863,11 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) Command.ModeRegisterDefinition = tmpmrd; /* Send the command */ - HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + _HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); /* Step 6: Set the refresh rate counter */ /* Set the device refresh rate */ - HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); + _HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); } /** @@ -278,7 +879,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) */ uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) { - if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(_HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -297,7 +898,7 @@ uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uw */ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) { - if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(_HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -316,7 +917,7 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_ */ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) { - if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(_HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -326,6 +927,37 @@ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t u } } +__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma: DMA handle + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +static void _HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +static void _HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + /** * @brief Writes an amount of data to the SDRAM memory in DMA mode. * @param uwStartAddress: Write start address @@ -335,7 +967,7 @@ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t u */ uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) { - if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + if(_HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) { return SDRAM_ERROR; } @@ -352,7 +984,7 @@ uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32 */ uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) { - if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) + if(_HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) { return SDRAM_ERROR; } @@ -362,13 +994,22 @@ uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) } } +static void _HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00; + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + /** * @brief Handles SDRAM DMA transfer interrupt request. * @retval None */ void BSP_SDRAM_DMA_IRQHandler(void) { - HAL_DMA_IRQHandler(sdramHandle.hdma); + _HAL_DMA_IRQHandler(sdramHandle.hdma); } /** @@ -452,14 +1093,14 @@ __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) __HAL_LINKDMA(hsdram, hdma, dma_handle); /* Deinitialize the stream for new transfer */ - HAL_DMA_DeInit(&dma_handle); + _HAL_DMA_DeInit(&dma_handle); /* Configure the DMA stream */ - HAL_DMA_Init(&dma_handle); + _HAL_DMA_Init(&dma_handle); /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); + _HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); + _HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); } /** @@ -473,11 +1114,11 @@ __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) static DMA_HandleTypeDef dma_handle; /* Disable NVIC configuration for DMA interrupt */ - HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); + _HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); /* Deinitialize the stream for new transfer */ dma_handle.Instance = SDRAM_DMAx_STREAM; - HAL_DMA_DeInit(&dma_handle); + _HAL_DMA_DeInit(&dma_handle); /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications by surcharging this __weak function */ diff --git a/boards/base/STM32F746-Discovery/stm32f7_i2c.c b/boards/base/STM32F746-Discovery/stm32f7_i2c.c index b0fa8163..d1e2ed28 100644 --- a/boards/base/STM32F746-Discovery/stm32f7_i2c.c +++ b/boards/base/STM32F746-Discovery/stm32f7_i2c.c @@ -1,3 +1,4 @@ +#include "gfx.h" #include "stm32f7_i2c.h" /* @@ -119,6 +120,8 @@ void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t v void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length) { + int i; + // We are currently not able to read more than 255 bytes at once if (length > 255) { return; @@ -128,7 +131,7 @@ void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length _i2cConfigTransfer(i2c, slaveAddr, length, I2C_CR2_RD_WRN | I2C_CR2_AUTOEND, I2C_CR2_START); // Transmit the whole buffer - for (int i = 0; i < length; i++) { + for (i = 0; i < length; i++) { while (!(i2c->ISR & I2C_ISR_RXNE)); data[i] = i2c->RXDR; } diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c index 38adbcae..b7995014 100644 --- a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c +++ b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c @@ -74,6 +74,7 @@ */ /* Includes ------------------------------------------------------------------*/ +#include "gfx.h" #include "stm32f7xx_hal.h" /** @addtogroup STM32F7xx_HAL_Driver @@ -677,14 +678,14 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) */ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { - uint32_t tickstart = 0; + systemticks_t tickstart = 0; /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Bank)); /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = gfxSystemTicks(); /* Wait until FIFO is empty */ while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) @@ -692,7 +693,7 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((gfxSystemTicks() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } @@ -993,7 +994,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { __IO uint32_t tmpr = 0; - uint32_t tickstart = 0; + systemticks_t tickstart = 0; /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -1012,7 +1013,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com Device->SDCMR = tmpr; /* Get tick */ - tickstart = HAL_GetTick(); + tickstart = gfxSystemTicks(); /* wait until command is send */ while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) @@ -1020,7 +1021,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0)||((gfxSystemTicks() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } |