From 173164ce426377fc31a1df30b1017c1fab52b96e Mon Sep 17 00:00:00 2001 From: Dean Camera Date: Mon, 4 Dec 2017 19:41:30 +1100 Subject: Fix AVRISP-MKII Clone Programmer PDI entry sequence (thanks to Justin Mattair). --- Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'Projects') diff --git a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c index 0455329c3..283d8f4ca 100644 --- a/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c +++ b/Projects/AVRISP-MKII/Lib/XPROG/XPROGTarget.c @@ -39,7 +39,7 @@ #if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__) /** Flag to indicate if the USART is currently in Tx or Rx mode. */ -bool IsSending; +static bool IsSending; /** Enables the target's PDI interface, holding the target in reset until PDI mode is exited. */ void XPROGTarget_EnableTargetPDI(void) @@ -50,10 +50,15 @@ void XPROGTarget_EnableTargetPDI(void) DDRD |= (1 << 5) | (1 << 3); DDRD &= ~(1 << 2); - /* Set DATA line high for at least 90ns to disable /RESET functionality */ - PORTD |= (1 << 3); + /* Set Tx (PDI CLOCK) high, DATA line low for at least 90ns to disable /RESET functionality */ + PORTD |= (1 << 5); + PORTD &= ~(1 << 3); _delay_us(100); + /* Set DATA line high (enables PDI interface after 16 PDI CLK cycles) */ + PORTD |= (1 << 3); + _delay_us(20); + /* Set up the synchronous USART for XMEGA communications - 8 data bits, even parity, 2 stop bits */ UBRR1 = ((F_CPU / 2 / XPROG_HARDWARE_SPEED) - 1); UCSR1B = (1 << TXEN1); -- cgit v1.2.3