/** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ __IO uint32_t CF

/* Copyright 2017 Jack Humbert
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef PROCESS_UNICODE_COMMON_H
#define PROCESS_UNICODE_COMMON_H

#include "quantum.h"

#ifndef UNICODE_TYPE_DELAY
#define UNICODE_TYPE_DELAY 10
#endif

__attribute__ ((unused))
static uint8_t input_mode;

void set_unicode_input_mode(uint8_t os_target);
uint8_t get_unicode_input_mode(void);
void unicode_input_mode_init(void);
void unicode_input_start(void);
void unicode_input_finish(void);
void register_hex(uint16_t hex);
void send_unicode_hex_string(const char *str);

#define UC_OSX 0  // Mac OS X
#define UC_LNX 1  // Linux
#define UC_WIN 2  // Windows 'HexNumpad'
#define UC_BSD 3  // BSD (not implemented)
#define UC_WINC 4 // WinCompose https://github.com/samhocevar/wincompose
#define UC_OSX_RALT 5 // Mac OS X using Right Alt key for Unicode Compose

#define UC_BSPC	UC(0x0008)

#define UC_SPC	UC(0x0020)

#define UC_EXLM	UC(0x0021)
#define UC_DQUT	UC(0x0022)
#define UC_HASH	UC(0x0023)
#define UC_DLR	UC(0x0024)
#define UC_PERC	UC(0x0025)
#define UC_AMPR	UC(0x0026)
#define UC_QUOT	UC(0x0027)
#define UC_LPRN	UC(0x0028)
#define UC_RPRN	UC(0x0029)
#define UC_ASTR	UC(0x002A)
#define UC_PLUS	UC(0x002B)
#define UC_COMM	UC(0x002C)
#define UC_DASH	UC(0x002D)
#define UC_DOT	UC(0x002E)
#define UC_SLSH	UC(0x002F)

#define UC_0	UC(0x0030)
#define UC_1	UC(0x0031)
#define UC_2	UC(0x0032)
#define UC_3	UC(0x0033)
#define UC_4	UC(0x0034)
#define UC_5	UC(0x0035)
#define UC_6	UC(0x0036)
#define UC_7	UC(0x0037)
#define UC_8	UC(0x0038)
#define UC_9	UC(0x0039)

#define UC_COLN UC(0x003A)
#define UC_SCLN UC(0x003B)
#define UC_LT	UC(0x003C)
#define UC_EQL	UC(0x003D)
#define UC_GT	UC(0x003E)
#define UC_QUES	UC(0x003F)
#define UC_AT 	UC(0x0040)

#define UC_A 	UC(0x0041)
#define UC_B 	UC(0x0042)
#define UC_C 	UC(0x0043)
#define UC_D 	UC(0x0044)
#define UC_E 	UC(0x0045)
#define UC_F 	UC(0x0046)
#define UC_G 	UC(0x0047)
#define UC_H 	UC(0x0048)
#define UC_I 	UC(0x0049)
#define UC_J 	UC(0x004A)
#define UC_K 	UC(0x004B)
#define UC_L 	UC(0x004C)
#define UC_M 	UC(0x004D)
#define UC_N 	UC(0x004E)
#define UC_O 	UC(0x004F)
#define UC_P 	UC(0x0050)
#define UC_Q 	UC(0x0051)
#define UC_R 	UC(0x0052)
#define UC_S 	UC(0x0053)
#define UC_T 	UC(0x0054)
#define UC_U 	UC(0x0055)
#define UC_V 	UC(0x0056)
#define UC_W 	UC(0x0057)
#define UC_X 	UC(0x0058)
#define UC_Y 	UC(0x0059)
#define UC_Z 	UC(0x005A)

#define UC_LBRC	UC(0x005B)
#define UC_BSLS	UC(0x005C)
#define UC_RBRC	UC(0x005D)
#define UC_CIRM	UC(0x005E)
#define UC_UNDR	UC(0x005F)

#define UC_GRV 	UC(0x0060)

#define UC_a 	UC(0x0061)
#define UC_b 	UC(0x0062)
#define UC_c 	UC(0x0063)
#define UC_d 	UC(0x0064)
#define UC_e 	UC(0x0065)
#define UC_f 	UC(0x0066)
#define UC_g 	UC(0x0067)
#define UC_h 	UC(0x0068)
#define UC_i 	UC(0x0069)
#define UC_j 	UC(0x006A)
#define UC_k 	UC(0x006B)
#define UC_l 	UC(0x006C)
#define UC_m 	UC(0x006D)
#define UC_n 	UC(0x006E)
#define UC_o 	UC(0x006F)
#define UC_p 	UC(0x0070)
#define UC_q 	UC(0x0071)
#define UC_r 	UC(0x0072)
#define UC_s 	UC(0x0073)
#define UC_t 	UC(0x0074)
#define UC_u 	UC(0x0075)
#define UC_v 	UC(0x0076)
#define UC_w 	UC(0x0077)
#define UC_x 	UC(0x0078)
#define UC_y 	UC(0x0079)
#define UC_z 	UC(0x007A)

#define UC_LCBR	UC(0x007B)
#define UC_PIPE	UC(0x007C)
#define UC_RCBR	UC(0x007D)
#define UC_TILD	UC(0x007E)
#define UC_DEL	UC(0x007F)

#endif

/*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ }RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ }RTC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ }SPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ }TIM_TypeDef; /** * @brief Touch Sensing Controller (TSC) */ typedef struct { __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ }TSC_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ uint16_t RESERVED1; /*!< Reserved, 0x26 */ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ uint16_t RESERVED2; /*!< Reserved, 0x2A */ }USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ }WWDG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ /*!< Peripheral memory map */ #define APBPERIPH_BASE PERIPH_BASE #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) #define TIM2_BASE (APBPERIPH_BASE + 0x00000000) #define TIM3_BASE (APBPERIPH_BASE + 0x00000400) #define TIM6_BASE (APBPERIPH_BASE + 0x00001000) #define TIM7_BASE (APBPERIPH_BASE + 0x00001400) #define TIM14_BASE (APBPERIPH_BASE + 0x00002000) #define RTC_BASE (APBPERIPH_BASE + 0x00002800) #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) #define IWDG_BASE (APBPERIPH_BASE + 0x00003000) #define SPI2_BASE (APBPERIPH_BASE + 0x00003800) #define USART2_BASE (APBPERIPH_BASE + 0x00004400) #define USART3_BASE (APBPERIPH_BASE + 0x00004800) #define USART4_BASE (APBPERIPH_BASE + 0x00004C00) #define I2C1_BASE (APBPERIPH_BASE + 0x00005400) #define I2C2_BASE (APBPERIPH_BASE + 0x00005800) #define CRS_BASE (APBPERIPH_BASE + 0x00006C00) #define PWR_BASE (APBPERIPH_BASE + 0x00007000) #define DAC_BASE (APBPERIPH_BASE + 0x00007400) #define CEC_BASE (APBPERIPH_BASE + 0x00007800) #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) #define COMP_BASE (APBPERIPH_BASE + 0x0001001C) #define EXTI_BASE (APBPERIPH_BASE + 0x00010400) #define ADC1_BASE (APBPERIPH_BASE + 0x00012400) #define ADC_BASE (APBPERIPH_BASE + 0x00012708) #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00) #define SPI1_BASE (APBPERIPH_BASE + 0x00013000) #define USART1_BASE (APBPERIPH_BASE + 0x00013800) #define TIM15_BASE (APBPERIPH_BASE + 0x00014000) #define TIM16_BASE (APBPERIPH_BASE + 0x00014400) #define TIM17_BASE (APBPERIPH_BASE + 0x00014800) #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) #define RCC_BASE (AHBPERIPH_BASE + 0x00001000) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */ #define CRC_BASE (AHBPERIPH_BASE + 0x00003000) #define TSC_BASE (AHBPERIPH_BASE + 0x00004000) #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000) #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400) #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800) #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00) #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000) #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400) /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define USART4 ((USART_TypeDef *) USART4_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define CEC ((CEC_TypeDef *) CEC_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define COMP ((COMP1_2_TypeDef *) COMP_BASE) #define COMP1 ((COMP_TypeDef *) COMP_BASE) #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002)) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define OB ((OB_TypeDef *) OB_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define TSC ((TSC_TypeDef *) TSC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers Bits Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /******************** Bits definition for ADC_ISR register ******************/ #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */ #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */ #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */ #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */ #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */ #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */ /* Old EOSEQ bit definition, maintained for legacy purpose */ #define ADC_ISR_EOS ADC_ISR_EOSEQ /******************** Bits definition for ADC_IER register ******************/ #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */ #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */ #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */ #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */ #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */ #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */ /* Old EOSEQIE bit definition, maintained for legacy purpose */ #define ADC_IER_EOSIE ADC_IER_EOSEQIE /******************** Bits definition for ADC_CR register *******************/ #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */ #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */ #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */ #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */ #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ /******************* Bits definition for ADC_CFGR1 register *****************/ #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */ #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */ #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */ #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */ #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */ #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */ #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */ #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */ #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */ #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */ #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */ #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */ #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */ #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */ #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */ #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */ #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */ #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */ #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */ #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */ /* Old WAIT bit definition, maintained for legacy purpose */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT /******************* Bits definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */ #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */ #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */ /* Old bit definition, maintained for legacy purpose */ #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */ #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */ /****************** Bit definition for ADC_SMPR register ********************/ #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */ #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */ #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */ /* Old bit definition, maintained for legacy purpose */ #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */ #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */ #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */ #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */ /******************* Bit definition for ADC_TR register ********************/ #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */ #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ /* Old bit definition, maintained for legacy purpose */ #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */ #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */ /****************** Bit definition for ADC_CHSELR register ******************/ #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */ #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */ #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */ #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */ #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */ #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */ #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */ #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */ #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */ #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */ #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */ #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */ #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */ #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */ #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */ #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */ #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */ #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */ #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ /******************* Bit definition for ADC_CCR register ********************/ #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */ #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */ #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */ /******************************************************************************/ /* */ /* HDMI-CEC (CEC) */ /* */ /******************************************************************************/ /******************* Bit definition for CEC_CR register *********************/ #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */ #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */ #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */ /******************* Bit definition for CEC_CFGR register *******************/ #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */ #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */ #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */ #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */ #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */ #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */ #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */ #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */ #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */ /******************* Bit definition for CEC_TXDR register *******************/ #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */ /******************* Bit definition for CEC_RXDR register *******************/ #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */ /******************* Bit definition for CEC_ISR register ********************/ #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */ #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */ #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */ #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */ #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */ #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */ #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */ #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */ #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */ #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */ #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */ #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */ #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */ /******************* Bit definition for CEC_IER register ********************/ #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */ #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */ #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */ #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */ #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/ #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */ #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */ #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */ #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */ #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */ #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */ #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */ #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */ /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ /* */ /******************************************************************************/ /*********************** Bit definition for COMP_CSR register ***************/ /* COMP1 bits definition */ #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */ #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */ #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */ #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */ #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */ #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */ #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */ #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */ #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */ #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */ #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */ #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */ #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */ #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */ #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */ #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */ #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */ #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */ #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */ /* COMP2 bits definition */ #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */ #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */ #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */ #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */ #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */ #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */ #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */ #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */ #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */ #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */ #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */ #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */ #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */ #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */ #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */ #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */ #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */ #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ /* COMPx bits definition */ #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */ #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */ #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */ #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */ #define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */ #define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */ #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */ #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */ #define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */ #define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */ #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */ #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */ #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */ #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */ #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */ #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */ #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/ #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */ #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */ #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */ #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */ #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */ #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */ #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */ #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */ #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */ #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */ #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */ #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */ #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */ #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */ #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */ #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */ #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */ #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */ #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */ #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */ #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */ #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */ #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */ /******************************************************************************/ /* */ /* Digital to Analog Converter (DAC) */ /* */ /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */ #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */ #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12R2 register ******************/ #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L2 register ******************/ #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R2 register ******************/ #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12RD register ******************/ #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12LD register ******************/ #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8RD register ******************/ #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */ /******************* Bit definition for DAC_DOR2 register *******************/ #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */ /******************** Bit definition for DAC_SR register ********************/ #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ /******************************************************************************/ /* */ /* Debug MCU (DBGMCU) */ /* */ /******************************************************************************/ /**************** Bit definition for DBGMCU_IDCODE register *****************/ #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ /****************** Bit definition for DBGMCU_CR register *******************/ #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ /****************** Bit definition for DBGMCU_APB1_FZ register **************/ #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */ #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */ #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */ #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */ #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */ #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */ #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */ #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */ #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ /****************** Bit definition for DBGMCU_APB2_FZ register **************/ #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */ #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */ #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */ #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */ /******************************************************************************/ /* */ /* DMA Controller (DMA) */ /* */ /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/ #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ /******************************************************************************/ /* */ /* External Interrupt/Event Controller (EXTI) */ /* */ /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 - reserved */ #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 - reserved */ #define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 - reserved */ #define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 - reserved */ #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */ /****************** Bit definition for EXTI_EMR register ********************/ #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 - reserved */ #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 - reserved */ #define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 - reserved */ #define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 - reserved */ #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */ /******************* Bit definition for EXTI_RTSR register ******************/ #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ /******************* Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ /******************* Bit definition for EXTI_SWIER register *******************/ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ /****************** Bit definition for EXTI_PR register *********************/ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */ #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */ #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */ #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */ #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */ #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */ #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */ #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */ #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */ #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */ #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */ #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */ #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */ #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */ #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */ #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */ #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */ #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */ #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */ #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */ /******************************************************************************/ /* */ /* FLASH and Option Bytes Registers */ /* */ /******************************************************************************/ /******************* Bit definition for FLASH_ACR register ******************/ #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */ #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ /****************** Bit definition for FLASH_KEYR register ******************/ #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ /***************** Bit definition for FLASH_OPTKEYR register ****************/ #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ /****************** FLASH Keys **********************************************/ #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 to unlock the write access to the FPEC. */ #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */ #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to unlock the write access to the option byte block */ /****************** Bit definition for FLASH_SR register *******************/ #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */ #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ /******************* Bit definition for FLASH_CR register *******************/ #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */ /******************* Bit definition for FLASH_AR register *******************/ #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ /****************** Bit definition for FLASH_OBR register *******************/ #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */ #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */ #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */ /* Old BOOT1 bit definition, maintained for legacy purpose */ #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 /* Old OBR_VDDA bit definition, maintained for legacy purpose */ #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR /****************** Bit definition for FLASH_WRPR register ******************/ #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */ /*----------------------------------------------------------------------------*/ /****************** Bit definition for OB_RDP register **********************/ #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ /****************** Bit definition for OB_USER register *********************/ #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ /****************** Bit definition for OB_WRP0 register *********************/ #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ /****************** Bit definition for OB_WRP1 register *********************/ #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ /****************** Bit definition for OB_WRP2 register *********************/ #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ /****************** Bit definition for OB_WRP3 register *********************/ #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ /******************************************************************************/ /* */ /* General Purpose IOs (GPIO) */ /* */ /******************************************************************************/ /******************* Bit definition for GPIO_MODER register *****************/ #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) /****************** Bit definition for GPIO_OTYPER register *****************/ #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) /**************** Bit definition for GPIO_OSPEEDR register ******************/ #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003) #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001) #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002) #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C) #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004) #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008) #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030) #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010) #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020) #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0) #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040) #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080) #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300) #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100) #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200) #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00) #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400) #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800) #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000) #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000) #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000) #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000) #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000) #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000) #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000) #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000) #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000) #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000) #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000) #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000) #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000) #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000) #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000) #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000) #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000) #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000) #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000) #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000) #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000) #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000) #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000) #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000) #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000) #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000) #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000) #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000) #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000) #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000) /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) /******************* Bit definition for GPIO_IDR register *******************/ #define GPIO_IDR_0 ((uint32_t)0x00000001) #define GPIO_IDR_1 ((uint32_t)0x00000002) #define GPIO_IDR_2 ((uint32_t)0x00000004) #define GPIO_IDR_3 ((uint32_t)0x00000008) #define GPIO_IDR_4 ((uint32_t)0x00000010) #define GPIO_IDR_5 ((uint32_t)0x00000020) #define GPIO_IDR_6 ((uint32_t)0x00000040) #define GPIO_IDR_7 ((uint32_t)0x00000080) #define GPIO_IDR_8 ((uint32_t)0x00000100) #define GPIO_IDR_9 ((uint32_t)0x00000200) #define GPIO_IDR_10 ((uint32_t)0x00000400) #define GPIO_IDR_11 ((uint32_t)0x00000800) #define GPIO_IDR_12 ((uint32_t)0x00001000) #define GPIO_IDR_13 ((uint32_t)0x00002000) #define GPIO_IDR_14 ((uint32_t)0x00004000) #define GPIO_IDR_15 ((uint32_t)0x00008000) /****************** Bit definition for GPIO_ODR register ********************/ #define GPIO_ODR_0 ((uint32_t)0x00000001) #define GPIO_ODR_1 ((uint32_t)0x00000002) #define GPIO_ODR_2 ((uint32_t)0x00000004) #define GPIO_ODR_3 ((uint32_t)0x00000008) #define GPIO_ODR_4 ((uint32_t)0x00000010) #define GPIO_ODR_5 ((uint32_t)0x00000020) #define GPIO_ODR_6 ((uint32_t)0x00000040) #define GPIO_ODR_7 ((uint32_t)0x00000080) #define GPIO_ODR_8 ((uint32_t)0x00000100) #define GPIO_ODR_9 ((uint32_t)0x00000200) #define GPIO_ODR_10 ((uint32_t)0x00000400) #define GPIO_ODR_11 ((uint32_t)0x00000800) #define GPIO_ODR_12 ((uint32_t)0x00001000) #define GPIO_ODR_13 ((uint32_t)0x00002000) #define GPIO_ODR_14 ((uint32_t)0x00004000) #define GPIO_ODR_15 ((uint32_t)0x00008000) /****************** Bit definition for GPIO_BSRR register ********************/ #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) /****************** Bit definition for GPIO_LCKR register ********************/ #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /****************** Bit definition for GPIO_AFRL register ********************/ #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) /****************** Bit definition for GPIO_AFRH register ********************/ #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) /****************** Bit definition for GPIO_BRR register *********************/ #define GPIO_BRR_BR_0 ((uint32_t)0x00000001) #define GPIO_BRR_BR_1 ((uint32_t)0x00000002) #define GPIO_BRR_BR_2 ((uint32_t)0x00000004) #define GPIO_BRR_BR_3 ((uint32_t)0x00000008) #define GPIO_BRR_BR_4 ((uint32_t)0x00000010) #define GPIO_BRR_BR_5 ((uint32_t)0x00000020) #define GPIO_BRR_BR_6 ((uint32_t)0x00000040) #define GPIO_BRR_BR_7 ((uint32_t)0x00000080) #define GPIO_BRR_BR_8 ((uint32_t)0x00000100) #define GPIO_BRR_BR_9 ((uint32_t)0x00000200) #define GPIO_BRR_BR_10 ((uint32_t)0x00000400) #define GPIO_BRR_BR_11 ((uint32_t)0x00000800) #define GPIO_BRR_BR_12 ((uint32_t)0x00001000) #define GPIO_BRR_BR_13 ((uint32_t)0x00002000) #define GPIO_BRR_BR_14 ((uint32_t)0x00004000) #define GPIO_BRR_BR_15 ((uint32_t)0x00008000) /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface (I2C) */ /* */ /******************************************************************************/ /******************* Bit definition for I2C_CR1 register *******************/ #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */ #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */ #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */ #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */ #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */ #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */ #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */ #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */ #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */ #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */ #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */ #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */ #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ /****************** Bit definition for I2C_CR2 register ********************/ #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */ #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */ #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */ #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */ #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */ #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */ #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */ #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */ #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */ /******************* Bit definition for I2C_OAR1 register ******************/ #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */ #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */ #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register ******************/ #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register ****************/ #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */ #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */ #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */ #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */ /******************* Bit definition for I2C_TIMEOUTR register ****************/ #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */ #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */ #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */ #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/ #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */ /****************** Bit definition for I2C_ISR register ********************/ #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */ #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */ #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */ #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/ #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */ #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */ #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */ #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */ #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */ #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */ #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */ #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */ #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */ #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */ #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */ #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */ #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */ /****************** Bit definition for I2C_ICR register ********************/ #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */ #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */ #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */ #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */ #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */ #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */ #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */ #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */ #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */ /****************** Bit definition for I2C_PECR register *******************/ #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */ /****************** Bit definition for I2C_RXDR register *********************/ #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */ /****************** Bit definition for I2C_TXDR register *******************/ #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */ /*****************************************************************************/ /* */ /* Independent WATCHDOG (IWDG) */ /* */ /*****************************************************************************/ /******************* Bit definition for IWDG_KR register *******************/ #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register *******************/ #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */ #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */ #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */ #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */ /******************* Bit definition for IWDG_RLR register ******************/ #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register *******************/ #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */ #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */ #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */ /******************* Bit definition for IWDG_KR register *******************/ #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */ /*****************************************************************************/ /* */ /* Power Control (PWR) */ /* */ /*****************************************************************************/ /******************** Bit definition for PWR_CR register *******************/ #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */ #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ /*!< PVD level configuration */ #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */ #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */ #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */ #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */ #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */ #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */ #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */ #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */ #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ /******************* Bit definition for PWR_CSR register *******************/ #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */ #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */ #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */ #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */ #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */ #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */ #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */ #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */ #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */ /*****************************************************************************/ /* */ /* Reset and Clock Control */ /* */ /*****************************************************************************/ /******************** Bit definition for RCC_CR register *******************/ #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!

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