TEMPLATES = [ """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_SR_{S:N|P}{R:N|P}_ (S, R, Q) //- //- A set-reset latch with {S:negative|positive} polarity SET and {R:negative|positive} polarity RESET. //- //- Truth table: S R | Q //- -----+--- //- - {R:0|1} | 0 //- {S:0|1} - | 1 //- - - | q //- module \$_SR_{S:N|P}{R:N|P}_ (S, R, Q); input S, R; output reg Q; always @* begin if (R == {R:0|1}) Q <= 0; else if (S == {S:0|1}) Q <= 1; end endmodule """, """ `ifdef SIMCELLS_FF // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_FF_ (D, Q) //- //- A D-type flip-flop that is clocked from the implicit global clock. (This cell //- type is usually only used in netlists for formal verification.) //- module \$_FF_ (D, Q); input D; output reg Q; always @($global_clock) begin Q <= D; end endmodule `endif """, """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_DFF_{C:N|P}_ (D, C, Q) //- //- A {C:negative|positive} edge D-type flip-flop. //- //- Truth table: D C | Q //- -----+--- //- d {C:\\|/} | d //- - - | q //- module \$_DFF_{C:N|P}_ (D, C, Q); input D, C; output reg Q; always @({C:neg|pos}edge C) begin Q <= D; end endmodule """, """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q) //- //- A {C:negative|positive} edge D-type flip-flop with {E:negative|positive} polarity enable. //- //- Truth table: D C E | Q //- -------+--- //- d {C:\\|/} {E:0|1} | d //- - - - | q //- module \$_DFFE_{C:N|P}{E:N|P}_ (D, C, E, Q); input D, C, E; output reg Q; always @({C:neg|pos}edge C) begin if ({E:!E|E}) Q <= D; end endmodule """, """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q) //- //- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set}. //- //- Truth table: D C R | Q //- -------+--- //- - - {R:0|1} | {V:0|1} //- d {C:\\|/} - | d //- - - - | q //- module \$_DFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q); input D, C, R; output reg Q; always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin if (R == {R:0|1}) Q <= {V:0|1}; else Q <= D; end endmodule """, """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q) //- //- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set} and {E:negative|positive} //- polarity clock enable. //- //- Truth table: D C R E | Q //- ---------+--- //- - - {R:0|1} - | {V:0|1} //- d {C:\\|/} - {E:0|1} | d //- - - - - | q //- module \$_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q); input D, C, R, E; output reg Q; always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin if (R == {R:0|1}) Q <= {V:0|1}; else if (E == {E:0|1}) Q <= D; end endmodule """, """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q) //- //- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive} //- polarity reset. //- //- Truth table: C S R D | Q //- ---------+--- //- - - {R:0|1} - | 0 //- - {S:0|1} - - | 1 //- {C:\\|/} - - d | d //- - - - - | q //- module \$_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q); input C, S, R, D; output reg Q; always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin if (R == {R:0|1}) Q <= 0; else if (S == {S:0|1}) Q <= 1; else Q <= D; end endmodule """, """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q) //- //- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set, {R:negative|positive} //- polarity reset and {E:negative|positive} polarity clock enable. //- //- Truth table: C S R E D | Q //- -----------+--- //- - - {R:0|1} - - | 0 //- - {S:0|1} - - - | 1 //- {C:\\|/} - - {E:0|1} d | d //- - - - - - | q //- module \$_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q); input C, S, R, E, D; output reg Q; always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin if (R == {R:0|1}) Q <= 0; else if (S == {S:0|1}) Q <= 1; else if (E == {E:0|1}) Q <= D; end endmodule """, """ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q) //- //- A {C:negat
/*-------------------------------------------*/
/* Integer type definitions for FatFs module */
/*-------------------------------------------*/

#ifndef _INTEGER
#define _INTEGER

#ifdef _WIN32	/* FatFs development platform */

#include <windows.h>
#include <tchar.h>

#else			/* Embedded platform */

/* These types must be 16-bit, 32-bit or larger integer */
typedef int				INT;
typedef unsigned int	UINT;

/* These types must be 8-bit integer */
typedef char			CHAR;
typedef unsigned char	UCHAR;
typedef unsigned char	BYTE;

/* These types must be 16-bit integer */
typedef short			SHORT;
typedef unsigned short	USHORT;
typedef unsigned short	WORD;
typedef unsigned short	WCHAR;

/* These types must be 32-bit integer */
typedef long			LONG;
typedef unsigned long	ULONG;
typedef unsigned long	DWORD;

#endif

#endif
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