/** ****************************************************************************** * @file stm32l152xe.h * @author MCD Application Team * @version 21-April-2017 * @date V2.2.1 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32L1xx devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32l152xe * @{ */ #ifndef __STM32L152xE_H #define __STM32L152xE_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32L1xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ typedef enum { /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ /****** STM32L specific Interrupt Numbers ***********************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ ADC1_IRQn 
/*
             LUFA Library
     Copyright (C) Dean Camera, 2017.

  dean [at] fourwalledcubicle [dot] com
           www.lufa-lib.org
*/

/*
  Copyright 2017  Dean Camera (dean [at] fourwalledcubicle [dot] com)

  Permission to use, copy, modify, distribute, and sell this
  software and its documentation for any purpose is hereby granted
  without fee, provided that the above copyright notice appear in
  all copies and that both that the copyright notice and this
  permission notice and warranty disclaimer appear in supporting
  documentation, and that the name of the author not be used in
  advertising or publicity pertaining to distribution of the
  software without specific, written prior permission.

  The author disclaims all warranties with regard to this
  software, including all implied warranties of merchantability
  and fitness.  In no event shall the author be liable for any
  special, indirect or consequential damages or any damages
  whatsoever resulting from loss of use, data or profits, whether
  in an action of contract, negligence or other tortious action,
  arising out of or in connection with the use or performance of
  this software.
*/

/** \file
 *
 *  Header file for SCSI.c.
 */

#ifndef _SCSI_H_
#define _SCSI_H_

	/* Includes: */
		#include <avr/io.h>
		#include <avr/pgmspace.h>

		#include <LUFA/Drivers/USB/USB.h>

		#include "../MassStorageKeyboard.h"
		#include "../Descriptors.h"
		#include "DataflashManager.h"
		#include "Config/AppConfig.h"

	/* Macros: */
		/** Macro to set the current SCSI sense data to the given key, additional sense code and additional sense qualifier. This
		 *  is for convenience, as it allows for all three sense values (returned upon request to the host to give information about
		 *  the last command failure) in a quick and easy manner.
		 *
		 *  \param[in] Key    New SCSI sense key to set the sense code to
		 *  \param[in] Acode  New SCSI additional sense key to set the additional sense code to
		 *  \param[in] Aqual  New SCSI additional sense key qualifier to set the additional sense qualifier code to
		 */
		#define SCSI_SET_SENSE(Key, Acode, Aqual)  do { SenseData.SenseKey                 = (Key);   \
		                                                SenseData.AdditionalSenseCode      = (Acode); \
		                                                SenseData.AdditionalSenseQualifier = (Aqual); } while (0)

		/** Macro for the \ref SCSI_Command_ReadWrite_10() function, to indicate that data is to be read from the storage medium. */
		#define DATA_READ           true

		/** Macro for the \ref SCSI_Command_ReadWrite_10() function, to indicate that data is to be written to the storage medium. */
		#define DATA_WRITE          false

		/** Value for the DeviceType entry in the SCSI_Inquiry_Response_t enum, indicating a Block Media device. */
		#define DEVICE_TYPE_BLOCK   0x00

		/** Value for the DeviceType entry in the SCSI_Inquiry_Response_t enum, indicating a CD-ROM device. */
		#define DEVICE_TYPE_CDROM   0x05

	/* Function Prototypes: */
		bool SCSI_DecodeSCSICommand(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo);

		#if defined(INCLUDE_FROM_SCSI_C)
			static bool SCSI_Command_Inquiry(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo);
			static bool SCSI_Command_Request_Sense(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo);
			static bool SCSI_Command_Read_Capacity_10(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo);
			static bool SCSI_Command_Send_Diagnostic(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo);
			static bool SCSI_Command_ReadWrite_10(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo,
			                                      const bool IsDataRead);
			static bool SCSI_Command_ModeSense_6(USB_ClassInfo_MS_Device_t* const MSInterfaceInfo);
		#endif

#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-07 16:52:05 +0000
t32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */ __IO uint32_t WRPR4; /*!< Write protection register 4, Address offset: 0x88 */ } FLASH_TypeDef; /** * @brief Option Bytes Registers */ typedef struct { __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ uint32_t RESERVED[24]; /*!< Reserved, 0x20 -> 0x7C */ __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */ __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */ } OB_TypeDef; /** * @brief Operational Amplifier (OPAMP) */ typedef struct { __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ } OPAMP_TypeDef; typedef struct { __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ } OPAMP_Common_TypeDef; /** * @brief General Purpose IO */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** * @brief SysTem Configuration */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ } SYSCFG_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ } IWDG_TypeDef; /** * @brief LCD */ typedef struct { __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ } LCD_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ } RCC_TypeDef; /** * @brief Routing Interface */ typedef struct { __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ } RI_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ uint32_t RESERVED7; /*!< Reserved, 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ } RTC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ uint32_t RESERVED12; /*!< Reserved, 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ uint32_t RESERVED17; /*!< Reserved, 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; /** * @brief Universal Serial Bus Full Speed Device */ typedef struct { __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ __IO uint16_t RESERVED2; /*!< Reserved */ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ __IO uint16_t RESERVEDC; /*!< Reserved */ } USB_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief Universal Serial Bus Full Speed Device */ /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ #define FLASH_BANK2_BASE ((uint32_t)0x08040000U) /*!< FLASH BANK2 base address in the alias region */ #define FLASH_BANK1_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH BANK1 address */ #define FLASH_BANK2_END ((uint32_t)0x0807FFFFU) /*!< Program end FLASH BANK2 address */ #define FLASH_EEPROM_END ((uint32_t)0x08083FFFU) /*!< FLASH EEPROM end address (16KB) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U) #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) #define LCD_BASE (APB1PERIPH_BASE + 0x00002400U) #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /* USB device FS */ #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /* USB device FS SRAM */ #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U) #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U) #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU) /*!< APB2 peripherals */ #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U) #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U) #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U) #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U) #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< AHB peripherals */ #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U) #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U) #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800U) #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00U) #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U) #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU) #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U) #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U) #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U) #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define LCD ((LCD_TypeDef *) LCD_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) /* USB device FS */ #define USB ((USB_TypeDef *) USB_BASE) /* USB device FS SRAM */ #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC1 ((DAC_TypeDef *) DAC_BASE) /* Legacy define */ #define DAC DAC1 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ #define RI ((RI_TypeDef *) RI_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) /* Legacy defines */ #define ADC ADC1_COMMON #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define OB ((OB_TypeDef *) OB_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers Bits Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_SR_EOCS_Pos (1U) #define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /*!< 0x00000002 */ #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ #define ADC_SR_JEOS_Pos (2U) #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_SR_JSTRT_Pos (3U) #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ #define ADC_SR_STRT_Pos (4U) #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ #define ADC_SR_OVR_Pos (5U) #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */ #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_SR_ADONS_Pos (6U) #define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /*!< 0x00000040 */ #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */ #define ADC_SR_RCNR_Pos (8U) #define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /*!< 0x00000100 */ #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */ #define ADC_SR_JCNR_Pos (9U) #define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /*!< 0x00000200 */ #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */ /* Legacy defines */ #define ADC_SR_EOC (ADC_SR_EOCS) #define ADC_SR_JEOC (ADC_SR_JEOS) /******************* Bit definition for ADC_CR1 register ********************/ #define ADC_CR1_AWDCH_Pos (0U) #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ #define ADC_CR1_EOCSIE_Pos (5U) #define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */ #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ #define ADC_CR1_AWDIE_Pos (6U) #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_CR1_JEOSIE_Pos (7U) #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_CR1_SCAN_Pos (8U) #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ #define ADC_CR1_AWDSGL_Pos (9U) #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CR1_JAUTO_Pos (10U) #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CR1_DISCEN_Pos (11U) #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CR1_JDISCEN_Pos (12U) #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CR1_DISCNUM_Pos (13U) #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ #define ADC_CR1_PDD_Pos (16U) #define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /*!< 0x00010000 */ #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */ #define ADC_CR1_PDI_Pos (17U) #define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /*!< 0x00020000 */ #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */ #define ADC_CR1_JAWDEN_Pos (22U) #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CR1_AWDEN_Pos (23U) #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CR1_RES_Pos (24U) #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */ #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */ #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */ #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */ #define ADC_CR1_OVRIE_Pos (26U) #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */ /* Legacy defines */ #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) /******************* Bit definition for ADC_CR2 register ********************/ #define ADC_CR2_ADON_Pos (0U) #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ #define ADC_CR2_CONT_Pos (1U) #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CR2_CFG_Pos (2U) #define ADC_CR2_CFG_Msk (0x1U << ADC_CR2_CFG_Pos) /*!< 0x00000004 */ #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */ #define ADC_CR2_DELS_Pos (4U) #define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /*!< 0x00000070 */ #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */ #define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /*!< 0x00000010 */ #define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /*!< 0x00000020 */ #define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /*!< 0x00000040 */ #define ADC_CR2_DMA_Pos (8U) #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ #define ADC_CR2_DDS_Pos (9U) #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */ #define ADC_CR2_EOCS_Pos (10U) #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */ #define ADC_CR2_ALIGN_Pos (11U) #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CR2_JEXTSEL_Pos (16U) #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ #define ADC_CR2_JEXTEN_Pos (20U) #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ #define ADC_CR2_JSWSTART_Pos (22U) #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR2_EXTSEL_Pos (24U) #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ #define ADC_CR2_EXTEN_Pos (28U) #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ #define ADC_CR2_SWSTART_Pos (30U) #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ /****************** Bit definition for ADC_SMPR1 register *******************/ #define ADC_SMPR1_SMP20_Pos (0U) #define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */ #define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP21_Pos (3U) #define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */ #define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP22_Pos (6U) #define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */ #define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP23_Pos (9U) #define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */ #define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP24_Pos (12U) #define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */ #define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP25_Pos (15U) #define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */ #define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP26_Pos (18U) #define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */ #define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP27_Pos (21U) #define ADC_SMPR1_SMP27_Msk (0x7U << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */ #define ADC_SMPR1_SMP27_0 (0x1U << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP27_1 (0x2U << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP27_2 (0x4U << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP28_Pos (24U) #define ADC_SMPR1_SMP28_Msk (0x7U << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */ #define ADC_SMPR1_SMP28_0 (0x1U << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP28_1 (0x2U << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP28_2 (0x4U << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP29_Pos (27U) #define ADC_SMPR1_SMP29_Msk (0x7U << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */ #define ADC_SMPR1_SMP29_0 (0x1U << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP29_1 (0x2U << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP29_2 (0x4U << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ #define ADC_SMPR2_SMP19_Pos (27U) #define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ #define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ #define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_SMPR3 register *******************/ #define ADC_SMPR3_SMP0_Pos (0U) #define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR3_SMP1_Pos (3U) #define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR3_SMP2_Pos (6U) #define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR3_SMP3_Pos (9U) #define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR3_SMP4_Pos (12U) #define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR3_SMP5_Pos (15U) #define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR3_SMP6_Pos (18U) #define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR3_SMP7_Pos (21U) #define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR3_SMP8_Pos (24U) #define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR3_SMP9_Pos (27U) #define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ #define ADC_JOFR1_JOFFSET1_Pos (0U) #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ /****************** Bit definition for ADC_JOFR2 register *******************/ #define ADC_JOFR2_JOFFSET2_Pos (0U) #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ /****************** Bit definition for ADC_JOFR3 register *******************/ #define ADC_JOFR3_JOFFSET3_Pos (0U) #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ /****************** Bit definition for ADC_JOFR4 register *******************/ #define ADC_JOFR4_JOFFSET4_Pos (0U) #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ /******************* Bit definition for ADC_HTR register ********************/ #define ADC_HTR_HT_Pos (0U) #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ /******************* Bit definition for ADC_LTR register ********************/ #define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ /******************* Bit definition for ADC_SQR1 register *******************/ #define ADC_SQR1_L_Pos (20U) #define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /*!< 0x01F00000 */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ #define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ #define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ #define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ #define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ28_Pos (15U) #define ADC_SQR1_SQ28_Msk (0x1FU << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */ #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */ #define ADC_SQR1_SQ28_0 (0x01U << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ28_1 (0x02U << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ28_2 (0x04U << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */ #define ADC_SQR1_SQ28_3 (0x08U << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ28_4 (0x10U << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ27_Pos (10U) #define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */ #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */ #define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */ #define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ26_Pos (5U) #define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */ #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */ #define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */ #define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ25_Pos (0U) #define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */ #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */ #define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */ #define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */ #define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */ #define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */ /******************* Bit definition for ADC_SQR2 register *******************/ #define ADC_SQR2_SQ19_Pos (0U) #define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */ #define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ20_Pos (5U) #define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */ #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */ #define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */ #define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ21_Pos (10U) #define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */ #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */ #define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */ #define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ22_Pos (15U) #define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */ #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */ #define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */ #define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ23_Pos (20U) #define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */ #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */ #define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */ #define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ24_Pos (25U) #define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */ #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */ #define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */ #define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ #define ADC_SQR3_SQ13_Pos (0U) #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ14_Pos (5U) #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */ #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ15_Pos (10U) #define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */ #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */ #define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ16_Pos (15U) #define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */ #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */ #define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ17_Pos (20U) #define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */ #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */ #define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */ #define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ18_Pos (25U) #define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */ #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */ #define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */ #define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR4 register *******************/ #define ADC_SQR4_SQ7_Pos (0U) #define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ8_Pos (5U) #define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */ #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */ #define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ9_Pos (10U) #define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */ #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */ #define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */ #define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */ #define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */ #define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */ #define ADC_SQR4_SQ10_Pos (15U) #define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */ #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */ #define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */ #define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */ #define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */ #define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */ #define ADC_SQR4_SQ11_Pos (20U) #define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */ #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */ #define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */ #define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */ #define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */ #define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */ #define ADC_SQR4_SQ12_Pos (25U) #define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */ #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */ #define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */ #define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */ #define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */ #define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR5 register *******************/ #define ADC_SQR5_SQ1_Pos (0U) #define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */ #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */ #define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */ #define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */ #define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */ #define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */ #define ADC_SQR5_SQ2_Pos (5U) #define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */ #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */ #define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */ #define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */ #define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */ #define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */ #define ADC_SQR5_SQ3_Pos (10U) #define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */ #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */ #define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */ #define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */ #define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */ #define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */ #define ADC_SQR5_SQ4_Pos (15U) #define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */ #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */ #define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */ #define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */ #define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */ #define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */ #define ADC_SQR5_SQ5_Pos (20U) #define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */ #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */ #define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */ #define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */ #define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */ #define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */ #define ADC_SQR5_SQ6_Pos (25U) #define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */ #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */ #define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */ #define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */ #define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */ #define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ #define ADC_JSQR_JSQ1_Pos (0U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JSQ2_Pos (5U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ3_Pos (10U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ4_Pos (15U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JL_Pos (20U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************* Bit definition for ADC_JDR2 register *******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************* Bit definition for ADC_JDR3 register *******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************* Bit definition for ADC_JDR4 register *******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ /****************** Bit definition for ADC_SMPR0 register *******************/ #define ADC_SMPR0_SMP30_Pos (0U) #define ADC_SMPR0_SMP30_Msk (0x7U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */ #define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */ #define ADC_SMPR0_SMP30_0 (0x1U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */ #define ADC_SMPR0_SMP30_1 (0x2U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */ #define ADC_SMPR0_SMP30_2 (0x4U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */ #define ADC_SMPR0_SMP31_Pos (3U) #define ADC_SMPR0_SMP31_Msk (0x7U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */ #define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */ #define ADC_SMPR0_SMP31_0 (0x1U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */ #define ADC_SMPR0_SMP31_1 (0x2U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */ #define ADC_SMPR0_SMP31_2 (0x4U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */ /******************* Bit definition for ADC_CSR register ********************/ #define ADC_CSR_AWD1_Pos (0U) #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_EOCS1_Pos (1U) #define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ #define ADC_CSR_JEOS1_Pos (2U) #define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */ #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_JSTRT1_Pos (3U) #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */ #define ADC_CSR_STRT1_Pos (4U) #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */ #define ADC_CSR_OVR1_Pos (5U) #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_ADONS1_Pos (6U) #define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */ #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */ /* Legacy defines */ #define ADC_CSR_EOC1 (ADC_CSR_EOCS1) #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) /******************* Bit definition for ADC_CCR register ********************/ #define ADC_CCR_ADCPRE_Pos (16U) #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */ #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ #define ADC_CCR_TSVREFE_Pos (23U) #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ /* */ /******************************************************************************/ /****************** Bit definition for COMP_CSR register ********************/ #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */ #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */ #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */ #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */ #define COMP_CSR_CMP1EN_Pos (4U) #define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */ #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */ #define COMP_CSR_CMP1OUT_Pos (7U) #define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */ #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */ #define COMP_CSR_SPEED_Pos (12U) #define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */ #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */ #define COMP_CSR_CMP2OUT_Pos (13U) #define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */ #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */ #define COMP_CSR_WNDWE_Pos (17U) #define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */ #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ #define COMP_CSR_INSEL_Pos (18U) #define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */ #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */ #define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */ #define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */ #define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */ #define COMP_CSR_OUTSEL_Pos (21U) #define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */ #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */ #define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */ #define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */ #define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */ /* Bits present in COMP register but not related to comparator */ /* (or partially related to comparator, in addition to other peripherals) */ #define COMP_CSR_SW1_Pos (5U) #define COMP_CSR_SW1_Msk (0x1U << COMP_CSR_SW1_Pos) /*!< 0x00000020 */ #define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */ #define COMP_CSR_VREFOUTEN_Pos (16U) #define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */ #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */ #define COMP_CSR_FCH3_Pos (26U) #define COMP_CSR_FCH3_Msk (0x1U << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */ #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */ #define COMP_CSR_FCH8_Pos (27U) #define COMP_CSR_FCH8_Msk (0x1U << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */ #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */ #define COMP_CSR_RCH13_Pos (28U) #define COMP_CSR_RCH13_Msk (0x1U << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */ #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */ #define COMP_CSR_CAIE_Pos (29U) #define COMP_CSR_CAIE_Msk (0x1U << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */ #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */ #define COMP_CSR_CAIF_Pos (30U) #define COMP_CSR_CAIF_Msk (0x1U << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */ #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */ #define COMP_CSR_TSUSP_Pos (31U) #define COMP_CSR_TSUSP_Msk (0x1U << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */ #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */ /******************************************************************************/ /* */ /* Operational Amplifier (OPAMP) */ /* */ /******************************************************************************/ /******************* Bit definition for OPAMP_CSR register ******************/ #define OPAMP_CSR_OPA1PD_Pos (0U) #define OPAMP_CSR_OPA1PD_Msk (0x1U << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */ #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */ #define OPAMP_CSR_S3SEL1_Pos (1U) #define OPAMP_CSR_S3SEL1_Msk (0x1U << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */ #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */ #define OPAMP_CSR_S4SEL1_Pos (2U) #define OPAMP_CSR_S4SEL1_Msk (0x1U << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */ #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */ #define OPAMP_CSR_S5SEL1_Pos (3U) #define OPAMP_CSR_S5SEL1_Msk (0x1U << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */ #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */ #define OPAMP_CSR_S6SEL1_Pos (4U) #define OPAMP_CSR_S6SEL1_Msk (0x1U << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */ #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */ #define OPAMP_CSR_OPA1CAL_L_Pos (5U) #define OPAMP_CSR_OPA1CAL_L_Msk (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */ #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */ #define OPAMP_CSR_OPA1CAL_H_Pos (6U) #define OPAMP_CSR_OPA1CAL_H_Msk (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */ #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */ #define OPAMP_CSR_OPA1LPM_Pos (7U) #define OPAMP_CSR_OPA1LPM_Msk (0x1U << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */ #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */ #define OPAMP_CSR_OPA2PD_Pos (8U) #define OPAMP_CSR_OPA2PD_Msk (0x1U << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */ #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */ #define OPAMP_CSR_S3SEL2_Pos (9U) #define OPAMP_CSR_S3SEL2_Msk (0x1U << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */ #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */ #define OPAMP_CSR_S4SEL2_Pos (10U) #define OPAMP_CSR_S4SEL2_Msk (0x1U << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */ #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */ #define OPAMP_CSR_S5SEL2_Pos (11U) #define OPAMP_CSR_S5SEL2_Msk (0x1U << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */ #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */ #define OPAMP_CSR_S6SEL2_Pos (12U) #define OPAMP_CSR_S6SEL2_Msk (0x1U << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */ #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */ #define OPAMP_CSR_OPA2CAL_L_Pos (13U) #define OPAMP_CSR_OPA2CAL_L_Msk (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */ #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */ #define OPAMP_CSR_OPA2CAL_H_Pos (14U) #define OPAMP_CSR_OPA2CAL_H_Msk (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */ #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */ #define OPAMP_CSR_OPA2LPM_Pos (15U) #define OPAMP_CSR_OPA2LPM_Msk (0x1U << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */ #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */ #define OPAMP_CSR_ANAWSEL1_Pos (24U) #define OPAMP_CSR_ANAWSEL1_Msk (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */ #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */ #define OPAMP_CSR_ANAWSEL2_Pos (25U) #define OPAMP_CSR_ANAWSEL2_Msk (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */ #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */ #define OPAMP_CSR_S7SEL2_Pos (27U) #define OPAMP_CSR_S7SEL2_Msk (0x1U << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */ #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */ #define OPAMP_CSR_AOP_RANGE_Pos (28U) #define OPAMP_CSR_AOP_RANGE_Msk (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */ #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */ #define OPAMP_CSR_OPA1CALOUT_Pos (29U) #define OPAMP_CSR_OPA1CALOUT_Msk (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */ #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */ #define OPAMP_CSR_OPA2CALOUT_Pos (30U) #define OPAMP_CSR_OPA2CALOUT_Msk (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */ #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */ /******************* Bit definition for OPAMP_OTR register ******************/ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U) #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U) #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U) #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U) #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ #define OPAMP_OTR_OT_USER_Pos (31U) #define OPAMP_OTR_OT_USER_Msk (0x1U << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */ #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */ /******************* Bit definition for OPAMP_LPOTR register ****************/ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U) #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U) #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */ #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U) #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U) #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */ #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ /******************************************************************************/ /* */ /* Digital to Analog Converter (DAC) */ /* */ /******************************************************************************/ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!