// SPDX-License-Identifier: GPL-2.0-only #include #include #include #include "rtl83xx.h" #define RTL838X_DRIVER_NAME "rtl838x" #define RTL8380_LED_GLB_CTRL (0xA000) #define RTL8380_LED_MODE_SEL (0x1004) #define RTL8380_LED_MODE_CTRL (0xA004) #define RTL8380_LED_P_EN_CTRL (0xA008) #define RTL8380_LED_SW_CTRL (0xA00C) #define RTL8380_LED0_SW_P_EN_CTRL (0xA010) #define RTL8380_LED1_SW_P_EN_CTRL (0xA014) #define RTL8380_LED2_SW_P_EN_CTRL (0xA018) #define RTL8380_LED_SW_P_CTRL(p) (0xA01C + (((p) << 2))) #define RTL8390_LED_GLB_CTRL (0x00E4) #define RTL8390_LED_SET_2_3_CTRL (0x00E8) #define RTL8390_LED_SET_0_1_CTRL (0x00EC) #define RTL8390_LED_COPR_SET_SEL_CTRL(p) (0x00F0 + (((p >> 4) << 2))) #define RTL8390_LED_FIB_SET_SEL_CTRL(p) (0x0100 + (((p >> 4) << 2))) #define RTL8390_LED_COPR_PMASK_CTRL(p) (0x0110 + (((p >> 5) << 2))) #define RTL8390_LED_FIB_PMASK_CTRL(p) (0x00118 + (((p >> 5) << 2))) #define RTL8390_LED_COMBO_CTRL(p) (0x0120 + (((p >> 5) << 2))) #define RTL8390_LED_SW_CTRL (0x0128) #define RTL8390_LED_SW_P_EN_CTRL(p) (0x012C + (((p / 10) << 2))) #define RTL8390_LED_SW_P_CTRL(p) (0x0144 + (((p) << 2))) #define RTL838X_MIR_QID_CTRL(grp) (0xAD44 + (((grp) << 2))) #define RTL838X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2))) #define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp) (0xAA70 + (((grp) << 2))) #define RTL838X_MIR_RSPAN_TX_CTRL (0xA350) #define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL (0xAA80) #define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL (0xAA84) #define RTL839X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2))) #define RTL839X_MIR_RSPAN_TX_CTRL (0x69b0) #define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL (0x2550) #define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL (0x2554) #define RTL839X_MIR_SAMPLE_RATE_CTRL (0x2558) int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port); void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); void rtl83xx_fast_age(struct dsa_switch *ds, int port); u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); static ssize_t rtl838x_common_read(char __user *buffer, size_t count, loff_t *ppos, unsigned int value) { char *buf; ssize_t len; if (*ppos != 0) return 0; buf = kasprintf(GFP_KERNEL, "0x%08x\n", value); if (!buf) return -ENOMEM; if (count < strlen(buf)) { kfree(buf); return -ENOSPC; } len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); kfree(buf); return len; } static ssize_t rtl838x_common_write(const char __user *buffer, size_t count, loff_t *ppos, unsigned int *value) { char b[32]; ssize_t len; int ret; if (*ppos != 0) return -EINVAL; if (count >= sizeof(b)) return -ENOSPC; len = simple_write_to_buffer(b, sizeof(b) - 1, ppos, buffer, count); if (len < 0) return len; b[len] = '\0'; ret = kstrtouint(b, 16, value); if (ret) return -EIO; return len; } static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { struct rtl838x_port *p = filp->private_data; struct dsa_switch *ds = p->dp->ds; int value = rtl83xx_port_get_stp_state(ds->priv, p->dp->index); if (value < 0) return -EINVAL; return rtl838x_common_read(buffer, count, ppos, (u32)value); } static ssize_t stp_state_write(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos) { struct rtl838x_port *p = filp->private_data; u32 value; size_t res = rtl838x_common_write(buffer, count, ppos, &value); if (res < 0) return res; rtl83xx_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value); return res; } static const struct file_operations stp_state_fops = { .owner = THIS_MODULE, .open = simple_open, .read = stp_state_read, .write = stp_state_write, }; static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { struct rtl838x_port *p = filp->private_data; struct dsa_switch *ds = p->dp->ds; struct rtl838x_switch_priv *priv = ds->priv; int value = sw_r32(priv->r->l2_port_aging_out); if (value < 0) return -EINVAL; return rtl838x_common_read(buffer, count, ppos, (u32)value); } static ssize_t age_out_write(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos) { struct rtl838x_port *p = filp->private_data; u32 value; size_t res = rtl838x_common_write(buffer, count, ppos, &value); if (res < 0) return res; rtl83xx_fast_age(p->dp->ds, p->dp->index); return res; } static const struct file_operations age_out_fops = { .owner = THIS_MODULE, .open = simple_open, .read = age_out_read, .write = age_out_write, }; static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { struct rtl838x_port *p = filp->private_data; struct dsa_switch *ds = p->dp->ds; struct rtl838x_switch_priv *priv = ds->priv; int value; if (priv->family_id == RTL8380_FAMILY_ID) value = rtl838x_get_egress_rate(priv, p->dp->index); else value = rtl839x_get_egress_rate(priv, p->dp->index); if (value < 0) return -EINVAL; return rtl838x_common_read(buffer, count, ppos, (u32)value); } static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer, size_t count, loff_t *ppos) { struct rtl838x_port *p = filp->private_data; struct dsa_switch *ds = p->dp->ds; struct rtl838x_switch_priv *priv = ds->priv; u32 value; size_t res = rtl838x_common_write(buffer, count, ppos, &value); if (res < 0) return res; if (priv->family_id == RTL8380_FAMILY_ID) rtl838x_set_egress_rate(priv, p->dp->index, value); else rtl839x_set_egress_rate(priv, p->dp->index, value); return res; } static const struct file_operations port_egress_fops = { .owner = THIS_MODULE, .open = simple_open, .read = port_egress_rate_read, .write = port_egress_rate_write, }; static const struct debugfs_reg32 port_ctrl_regs[] = { { .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), }, { .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, }, }; void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv) { debugfs_remove_recursive(priv->dbgfs_dir); // kfree(priv->dbgfs_entries); } static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv, int port) { struct dentry *port_dir; struct debugfs_regset32 *port_ctrl_regset; port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent); if (priv->family_id == RTL8380_FAMILY_ID) { debugfs_create_x32("storm_rate_uc", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port))); debugfs_create_x32("storm_rate_mc", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port))); debugfs_create_x32("storm_rate_bc", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port))); debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL + (port << 2))); } else { debugfs_create_x32("storm_rate_uc", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port))); debugfs_create_x32("storm_rate_mc", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port))); debugfs_create_x32("storm_rate_bc", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port))); debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir, (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_PORT_TAG_STS_CTRL + (port << 2))); } debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index); port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL); if (!port_ctrl_regset) return -ENOMEM; port_ctrl_regset->regs = port_ctrl_regs; port_ctrl_regset->nregs =
/*
    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#include "ch.h"
#include "hal.h"

static virtual_timer_t vt1, vt2;

static void restart(void *p) {

  (void)p;

  chSysLockFromISR();
  uartStartSendI(&UARTD1, 14, "Hello World!\r\n");
  chSysUnlockFromISR();
}

static void ledoff(void *p) {

  (void)p;
  palClearPad(GPIOB, GPIOB_LED4);
}

/*
 * This callback is invoked when a transmission buffer has been completely
 * read by the driver.
 */
static void txend1(UARTDriver *uartp) {

  (void)uartp;
  palSetPad(GPIOB, GPIOB_LED4);
}

/*
 * This callback is invoked when a transmission has physically completed.
 */
static void txend2(UARTDriver *uartp) {

  (void)uartp;
  palClearPad(GPIOB, GPIOB_LED4);
  chSysLockFromISR();
  chVTResetI(&vt1);
  chVTDoSetI(&vt1, MS2ST(5000), restart, NULL);
  chSysUnlockFromISR();
}

/*
 * This callback is invoked on a receive error, the errors mask is passed
 * as parameter.
 */
static void rxerr(UARTDriver *uartp, uartflags_t e) {

  (void)uartp;
  (void)e;
}

/*
 * This callback is invoked when a character is received but the application
 * was not ready to receive it, the character is passed as parameter.
 */
static void rxchar(UARTDriver *uartp, uint16_t c) {

  (void)uartp;
  (void)c;
  /* Flashing the LED each time a character is received.*/
  palSetPad(GPIOB, GPIOB_LED4);
  chSysLockFromISR();
  chVTResetI(&vt2);
  chVTDoSetI(&vt2, MS2ST(200), ledoff, NULL);
  chSysUnlockFromISR();
}

/*
 * This callback is invoked when a receive buffer has been completely written.
 */
static void rxend(UARTDriver *uartp) {

  (void)uartp;
}

/*
 * UART driver configuration structure.
 */
static UARTConfig uart_cfg_1 = {
  txend1,
  txend2,
  rxend,
  rxchar,
  rxerr,
  38400,
  0,
  USART_CR2_LINEN,
  0
};

/*
 * Application entry point.
 */
int main(void) {

  /*
   * System initializations.
   * - HAL initialization, this also initializes the configured device drivers
   *   and performs the board-specific initializations.
   * - Kernel initialization, the main() function becomes a thread and the
   *   RTOS is active.
   */
  halInit();
  chSysInit();

  /*
   * Activates the serial driver 1, PA9 and PA10 are routed to USART1.
   */
  uartStart(&UARTD1, &uart_cfg_1);
  palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7));
  palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7));

  /*
   * Starts the transmission, it will be handled entirely in background.
   */
  uartStartSend(&UARTD1, 13, "Starting...\r\n");

  /*
   * Normal main() thread activity, in this demo it does nothing.
   */
  while (true) {
    chThdSleepMilliseconds(500);
  }
}
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