aboutsummaryrefslogtreecommitdiffstats
path: root/testhal/STM32/STM32L1xx/PWM-ICU/mcuconf.h
blob: 5003974efdd9a947d6b01a7923af429eefd687a9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
/*
    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

#ifndef _MCUCONF_H_
#define _MCUCONF_H_

/*
 * STM32L1xx drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

#define STM32L1xx_MCUCONF

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   TRUE
#define STM32_HSE_ENABLED                   FALSE
#define STM32_LSE_ENABLED                   TRUE
#define STM32_ADC_CLOCK_ENABLED             TRUE
#define STM32_USB_CLOCK_ENABLED             TRUE
#define STM32_MSIRANGE                      STM32_MSIRANGE_2M
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSI
#define STM32_PLLMUL_VALUE                  6
#define STM32_PLLDIV_VALUE                  3
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV1
#define STM32_PPRE2                         STM32_PPRE2_DIV1
#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE                        STM32_MCOPRE_DIV1
#define STM32_RTCSEL                        STM32_RTCSEL_LSE
#define STM32_RTCPRE                        STM32_RTCPRE_DIV2
#define STM32_VOS                           STM32_VOS_1P8
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0

/*
 * ADC driver system settings.
 */
#define STM32_ADC_USE_ADC1                  FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_IRQ_PRIORITY              6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6

/*
 * EXT driver system settings.
 */
#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
#define STM32_EXT_EXTI17_IRQ_PRIORITY       6
#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
#define STM32_EXT_EXTI20_IRQ_PRIORITY       6
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY    6

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM2                  FALSE
#define STM32_GPT_USE_TIM3                  FALSE
#define STM32_GPT_USE_TIM4                  FALSE
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
#define STM32_GPT_TIM4_IRQ_PRIORITY         7

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_BUSY_TIMEOUT              50
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
#define STM32_I2C_I2C1_DMA_PRIORITY         3
#define STM32_I2C_I2C2_DMA_PRIORITY         3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM2                  FALSE
#define STM32_ICU_USE_TIM3                  TRUE
#define STM32_ICU_USE_TIM4                  FALSE
#define STM32_ICU_USE_TIM9                  FALSE
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
#define STM32_ICU_TIM9_IRQ_PRIORITY         7

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_TIM2                  TRUE
#define STM32_PWM_USE_TIM3                  FALSE
#define STM32_PWM_USE_TIM4                  FALSE
#define STM32_PWM_USE_TIM9                  FALSE
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
#define STM32_PWM_TIM9_IRQ_PRIORITY         7

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             FALSE
#define STM32_SERIAL_USE_USART2             FALSE
#define STM32_SERIAL_USE_USART3             FALSE
#define STM32_SERIAL_USART1_PRIORITY        12
#define STM32_SERIAL_USART2_PRIORITY        12
#define STM32_SERIAL_USART3_PRIORITY        12

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  FALSE
#define STM32_SPI_USE_SPI2                  FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

/*
 * ST driver system settings.
 */
#define STM32_ST_IRQ_PRIORITY               8
#define STM32_ST_USE_TIMER                  4

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USE_USART3               FALSE
#define STM32_UART_USART1_IRQ_PRIORITY      12
#define STM32_UART_USART2_IRQ_PRIORITY      12
#define STM32_UART_USART3_IRQ_PRIORITY      12
#define STM32_UART_USART1_DMA_PRIORITY      0
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART3_DMA_PRIORITY      0
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

/*
 * USB driver system settings.
 */
#define STM32_USB_USE_USB1                  FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY      13
#define STM32_USB_USB1_LP_IRQ_PRIORITY      14

#endif /* _MCUCONF_H_ */
ependent * * 2018-10-28 checked * avr-gcc 4.9.2 * avr-gcc 5.4.0 * avr-gcc 7.3.0 */ #ifndef F_CPU # define F_CPU 16000000 #endif #include <avr/io.h> #include <avr/interrupt.h> #include <util/delay.h> #include <stddef.h> #include <stdbool.h> #include "serial.h" #ifdef SOFT_SERIAL_PIN # ifdef __AVR_ATmega32U4__ // if using ATmega32U4 I2C, can not use PD0 and PD1 in soft serial. # ifdef USE_AVR_I2C # if SOFT_SERIAL_PIN == D0 || SOFT_SERIAL_PIN == D1 # error Using ATmega32U4 I2C, so can not use PD0, PD1 # endif # endif # define setPinInputHigh(pin) (DDRx_ADDRESS(pin) &= ~_BV((pin)&0xF), PORTx_ADDRESS(pin) |= _BV((pin)&0xF)) # define setPinOutput(pin) (DDRx_ADDRESS(pin) |= _BV((pin)&0xF)) # define writePinHigh(pin) (PORTx_ADDRESS(pin) |= _BV((pin)&0xF)) # define writePinLow(pin) (PORTx_ADDRESS(pin) &= ~_BV((pin)&0xF)) # define readPin(pin) ((bool)(PINx_ADDRESS(pin) & _BV((pin)&0xF))) # if SOFT_SERIAL_PIN >= D0 && SOFT_SERIAL_PIN <= D3 # if SOFT_SERIAL_PIN == D0 # define EIMSK_BIT _BV(INT0) # define EICRx_BIT (~(_BV(ISC00) | _BV(ISC01))) # define SERIAL_PIN_INTERRUPT INT0_vect # elif SOFT_SERIAL_PIN == D1 # define EIMSK_BIT _BV(INT1) # define EICRx_BIT (~(_BV(ISC10) | _BV(ISC11))) # define SERIAL_PIN_INTERRUPT INT1_vect # elif SOFT_SERIAL_PIN == D2 # define EIMSK_BIT _BV(INT2) # define EICRx_BIT (~(_BV(ISC20) | _BV(ISC21))) # define SERIAL_PIN_INTERRUPT INT2_vect # elif SOFT_SERIAL_PIN == D3 # define EIMSK_BIT _BV(INT3) # define EICRx_BIT (~(_BV(ISC30) | _BV(ISC31))) # define SERIAL_PIN_INTERRUPT INT3_vect # endif # elif SOFT_SERIAL_PIN == E6 # define EIMSK_BIT _BV(INT6) # define EICRx_BIT (~(_BV(ISC60) | _BV(ISC61))) # define SERIAL_PIN_INTERRUPT INT6_vect # else # error invalid SOFT_SERIAL_PIN value # endif # else # error serial.c now support ATmega32U4 only # endif # define ALWAYS_INLINE __attribute__((always_inline)) # define NO_INLINE __attribute__((noinline)) # define _delay_sub_us(x) __builtin_avr_delay_cycles(x) // parity check # define ODD_PARITY 1 # define EVEN_PARITY 0 # define PARITY EVEN_PARITY # ifdef SERIAL_DELAY // custom setup in config.h // #define TID_SEND_ADJUST 2 // #define SERIAL_DELAY 6 // micro sec // #define READ_WRITE_START_ADJUST 30 // cycles // #define READ_WRITE_WIDTH_ADJUST 8 // cycles # else // ============ Standard setups ============ # ifndef SELECT_SOFT_SERIAL_SPEED # define SELECT_SOFT_SERIAL_SPEED 1 // 0: about 189kbps (Experimental only) // 1: about 137kbps (default) // 2: about 75kbps // 3: about 39kbps // 4: about 26kbps // 5: about 20kbps # endif # if __GNUC__ < 6 # define TID_SEND_ADJUST 14 # else # define TID_SEND_ADJUST 2 # endif # if SELECT_SOFT_SERIAL_SPEED == 0 // Very High speed # define SERIAL_DELAY 4 // micro sec # if __GNUC__ < 6 # define READ_WRITE_START_ADJUST 33 // cycles # define READ_WRITE_WIDTH_ADJUST 3 // cycles # else # define READ_WRITE_START_ADJUST 34 // cycles # define READ_WRITE_WIDTH_ADJUST 7 // cycles # endif # elif SELECT_SOFT_SERIAL_SPEED == 1 // High speed # define SERIAL_DELAY 6 // micro sec # if __GNUC__ < 6 # define READ_WRITE_START_ADJUST 30 // cycles # define READ_WRITE_WIDTH_ADJUST 3 // cycles # else # define READ_WRITE_START_ADJUST 33 // cycles # define READ_WRITE_WIDTH_ADJUST 7 // cycles # endif # elif SELECT_SOFT_SERIAL_SPEED == 2 // Middle speed # define SERIAL_DELAY 12 // micro sec # define READ_WRITE_START_ADJUST 30 // cycles # if __GNUC__ < 6 # define READ_WRITE_WIDTH_ADJUST 3 // cycles # else # define READ_WRITE_WIDTH_ADJUST 7 // cycles # endif # elif SELECT_SOFT_SERIAL_SPEED == 3 // Low speed # define SERIAL_DELAY 24 // micro sec # define READ_WRITE_START_ADJUST 30 // cycles # if __GNUC__ < 6 # define READ_WRITE_WIDTH_ADJUST 3 // cycles # else # define READ_WRITE_WIDTH_ADJUST 7 // cycles # endif # elif SELECT_SOFT_SERIAL_SPEED == 4 // Very Low speed # define SERIAL_DELAY 36 // micro sec # define READ_WRITE_START_ADJUST 30 // cycles # if __GNUC__ < 6 # define READ_WRITE_WIDTH_ADJUST 3 // cycles # else # define READ_WRITE_WIDTH_ADJUST 7 // cycles # endif # elif SELECT_SOFT_SERIAL_SPEED == 5 // Ultra Low speed # define SERIAL_DELAY 48 // micro sec # define READ_WRITE_START_ADJUST 30 // cycles # if __GNUC__ < 6 # define READ_WRITE_WIDTH_ADJUST 3 // cycles # else # define READ_WRITE_WIDTH_ADJUST 7 // cycles # endif # else # error invalid SELECT_SOFT_SERIAL_SPEED value # endif /* SELECT_SOFT_SERIAL_SPEED */ # endif /* SERIAL_DELAY */ # define SERIAL_DELAY_HALF1 (SERIAL_DELAY / 2) # define SERIAL_DELAY_HALF2 (SERIAL_DELAY - SERIAL_DELAY / 2) # define SLAVE_INT_WIDTH_US 1 # ifndef SERIAL_USE_MULTI_TRANSACTION # define SLAVE_INT_RESPONSE_TIME SERIAL_DELAY # else # define SLAVE_INT_ACK_WIDTH_UNIT 2 # define SLAVE_INT_ACK_WIDTH 4 # endif static SSTD_t *Transaction_table = NULL; static uint8_t Transaction_table_size = 0; inline static void serial_delay(void) ALWAYS_INLINE; inline static void serial_delay(void) { _delay_us(SERIAL_DELAY); } inline static void serial_delay_half1(void) ALWAYS_INLINE; inline static void serial_delay_half1(void) { _delay_us(SERIAL_DELAY_HALF1); } inline static void serial_delay_half2(void) ALWAYS_INLINE; inline static void serial_delay_half2(void) { _delay_us(SERIAL_DELAY_HALF2); } inline static void serial_output(void) ALWAYS_INLINE; inline static void serial_output(void) { setPinOutput(SOFT_SERIAL_PIN); } // make the serial pin an input with pull-up resistor inline static void serial_input_with_pullup(void) ALWAYS_INLINE; inline static void serial_input_with_pullup(void) { setPinInputHigh(SOFT_SERIAL_PIN); } inline static uint8_t serial_read_pin(void) ALWAYS_INLINE; inline static uint8_t serial_read_pin(void) { return !!readPin(SOFT_SERIAL_PIN); } inline static void serial_low(void) ALWAYS_INLINE; inline static void serial_low(void) { writePinLow(SOFT_SERIAL_PIN); } inline static void serial_high(void) ALWAYS_INLINE; inline static void serial_high(void) { writePinHigh(SOFT_SERIAL_PIN); } void soft_serial_initiator_init(SSTD_t *sstd_table, int sstd_table_size) { Transaction_table = sstd_table; Transaction_table_size = (uint8_t)sstd_table_size; serial_output(); serial_high(); } void soft_serial_target_init(SSTD_t *sstd_table, int sstd_table_size) { Transaction_table = sstd_table; Transaction_table_size = (uint8_t)sstd_table_size; serial_input_with_pullup(); // Enable INT0-INT3,INT6 EIMSK |= EIMSK_BIT; # if SOFT_SERIAL_PIN == E6 // Trigger on falling edge of INT6 EICRB &= EICRx_BIT; # else // Trigger on falling edge of INT0-INT3 EICRA &= EICRx_BIT; # endif } // Used by the sender to synchronize timing with the reciver. static void sync_recv(void) NO_INLINE; static void sync_recv(void) { for (uint8_t i = 0; i < SERIAL_DELAY * 5 && serial_read_pin(); i++) { } // This shouldn't hang if the target disconnects because the // serial line will float to high if the target does disconnect. while (!serial_read_pin()) ; } // Used by the reciver to send a synchronization signal to the sender. static void sync_send(void) NO_INLINE; static void sync_send(void) { serial_low(); serial_delay(); serial_high(); } // Reads a byte from the serial line static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) NO_INLINE; static uint8_t serial_read_chunk(uint8_t *pterrcount, uint8_t bit) { uint8_t byte, i, p, pb; _delay_sub_us(READ_WRITE_START_ADJUST); for (i = 0, byte = 0, p = PARITY; i < bit; i++) { serial_delay_half1(); // read the middle of pulses if (serial_read_pin()) { byte = (byte << 1) | 1; p ^= 1; } else { byte = (byte << 1) | 0; p ^= 0; } _delay_sub_us(READ_WRITE_WIDTH_ADJUST); serial_delay_half2(); } /* recive parity bit */ serial_delay_half1(); // read the middle of pulses pb = serial_read_pin(); _delay_sub_us(READ_WRITE_WIDTH_ADJUST); serial_delay_half2(); *pterrcount += (p != pb) ? 1 : 0; return byte; } // Sends a byte with MSB ordering void serial_write_chunk(uint8_t data, uint8_t bit) NO_INLINE; void serial_write_chunk(uint8_t data, uint8_t bit) { uint8_t b, p; for (p = PARITY, b = 1 << (bit - 1); b; b >>= 1) { if (data & b) { serial_high(); p ^= 1; } else { serial_low(); p ^= 0; } serial_delay(); } /* send parity bit */ if (p & 1) { serial_high(); } else { serial_low(); } serial_delay(); serial_low(); // sync_send() / senc_recv() need raise edge } static void serial_send_packet(uint8_t *buffer, uint8_t size) NO_INLINE; static void serial_send_packet(uint8_t *buffer, uint8_t size) { for (uint8_t i = 0; i < size; ++i) { uint8_t data; data = buffer[i]; sync_send(); serial_write_chunk(data, 8); } } static uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) NO_INLINE; static uint8_t serial_recive_packet(uint8_t *buffer, uint8_t size) { uint8_t pecount = 0; for (uint8_t i = 0; i < size; ++i) { uint8_t data; sync_recv(); data = serial_read_chunk(&pecount, 8); buffer[i] = data; } return pecount == 0; } inline static void change_sender2reciver(void) { sync_send(); // 0 serial_delay_half1(); // 1 serial_low(); // 2 serial_input_with_pullup(); // 2 serial_delay_half1(); // 3 } inline static void change_reciver2sender(void) { sync_recv(); // 0 serial_delay(); // 1 serial_low(); // 3 serial_output(); // 3 serial_delay_half1(); // 4 } static inline uint8_t nibble_bits_count(uint8_t bits) { bits = (bits & 0x5) + (bits >> 1 & 0x5); bits = (bits & 0x3) + (bits >> 2 & 0x3); return bits; } // interrupt handle to be used by the target device ISR(SERIAL_PIN_INTERRUPT) { # ifndef SERIAL_USE_MULTI_TRANSACTION serial_low(); serial_output(); SSTD_t *trans = Transaction_table; # else // recive transaction table index uint8_t tid, bits; uint8_t pecount = 0; sync_recv(); bits = serial_read_chunk(&pecount, 7); tid = bits >> 3; bits = (bits & 7) != nibble_bits_count(tid); if (bits || pecount > 0 || tid > Transaction_table_size) { return; } serial_delay_half1(); serial_high(); // response step1 low->high serial_output(); _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT * SLAVE_INT_ACK_WIDTH); SSTD_t *trans = &Transaction_table[tid]; serial_low(); // response step2 ack high->low # endif // target send phase if (trans->target2initiator_buffer_size > 0) serial_send_packet((uint8_t *)trans->target2initiator_buffer, trans->target2initiator_buffer_size); // target switch to input change_sender2reciver(); // target recive phase if (trans->initiator2target_buffer_size > 0) { if (serial_recive_packet((uint8_t *)trans->initiator2target_buffer, trans->initiator2target_buffer_size)) { *trans->status = TRANSACTION_ACCEPTED; } else { *trans->status = TRANSACTION_DATA_ERROR; } } else { *trans->status = TRANSACTION_ACCEPTED; } sync_recv(); // weit initiator output to high } ///////// // start transaction by initiator // // int soft_serial_transaction(int sstd_index) // // Returns: // TRANSACTION_END // TRANSACTION_NO_RESPONSE // TRANSACTION_DATA_ERROR // this code is very time dependent, so we need to disable interrupts # ifndef SERIAL_USE_MULTI_TRANSACTION int soft_serial_transaction(void) { SSTD_t *trans = Transaction_table; # else int soft_serial_transaction(int sstd_index) { if (sstd_index > Transaction_table_size) return TRANSACTION_TYPE_ERROR; SSTD_t *trans = &Transaction_table[sstd_index]; # endif cli(); // signal to the target that we want to start a transaction serial_output(); serial_low(); _delay_us(SLAVE_INT_WIDTH_US); # ifndef SERIAL_USE_MULTI_TRANSACTION // wait for the target response serial_input_with_pullup(); _delay_us(SLAVE_INT_RESPONSE_TIME); // check if the target is present if (serial_read_pin()) { // target failed to pull the line low, assume not present serial_output(); serial_high(); *trans->status = TRANSACTION_NO_RESPONSE; sei(); return TRANSACTION_NO_RESPONSE; } # else // send transaction table index int tid = (sstd_index << 3) | (7 & nibble_bits_count(sstd_index)); sync_send(); _delay_sub_us(TID_SEND_ADJUST); serial_write_chunk(tid, 7); serial_delay_half1(); // wait for the target response (step1 low->high) serial_input_with_pullup(); while (!serial_read_pin()) { _delay_sub_us(2); } // check if the target is present (step2 high->low) for (int i = 0; serial_read_pin(); i++) { if (i > SLAVE_INT_ACK_WIDTH + 1) { // slave failed to pull the line low, assume not present serial_output(); serial_high(); *trans->status = TRANSACTION_NO_RESPONSE; sei(); return TRANSACTION_NO_RESPONSE; } _delay_sub_us(SLAVE_INT_ACK_WIDTH_UNIT); } # endif // initiator recive phase // if the target is present syncronize with it if (trans->target2initiator_buffer_size > 0) { if (!serial_recive_packet((uint8_t *)trans->target2initiator_buffer, trans->target2initiator_buffer_size)) { serial_output(); serial_high(); *trans->status = TRANSACTION_DATA_ERROR; sei(); return TRANSACTION_DATA_ERROR; } } // initiator switch to output change_reciver2sender(); // initiator send phase if (trans->initiator2target_buffer_size > 0) { serial_send_packet((uint8_t *)trans->initiator2target_buffer, trans->initiator2target_buffer_size); } // always, release the line when not in use sync_send(); *trans->status = TRANSACTION_END; sei(); return TRANSACTION_END; } # ifdef SERIAL_USE_MULTI_TRANSACTION int soft_serial_get_and_clean_status(int sstd_index) { SSTD_t *trans = &Transaction_table[sstd_index]; cli(); int retval = *trans->status; *trans->status = 0; ; sei(); return retval; } # endif #endif // Helix serial.c history // 2018-1-29 fork from let's split and add PD2, modify sync_recv() (#2308, bceffdefc) // 2018-6-28 bug fix master to slave comm and speed up (#3255, 1038bbef4) // (adjusted with avr-gcc 4.9.2) // 2018-7-13 remove USE_SERIAL_PD2 macro (#3374, f30d6dd78) // (adjusted with avr-gcc 4.9.2) // 2018-8-11 add support multi-type transaction (#3608, feb5e4aae) // (adjusted with avr-gcc 4.9.2) // 2018-10-21 fix serial and RGB animation conflict (#4191, 4665e4fff) // (adjusted with avr-gcc 7.3.0) // 2018-10-28 re-adjust compiler depend value of delay (#4269, 8517f8a66) // (adjusted with avr-gcc 5.4.0, 7.3.0) // 2018-12-17 copy to TOP/quantum/split_common/ and remove backward compatibility code (#4669)