/* * QEMU LSI53C895A SCSI Host Bus Adapter emulation * * Copyright (c) 2006 CodeSourcery. * Written by Paul Brook * * This code is licenced under the LGPL. */ /* ??? Need to check if the {read,write}[wl] routines work properly on big-endian targets. */ #include "vl.h" //#define DEBUG_LSI //#define DEBUG_LSI_REG #ifdef DEBUG_LSI #define DPRINTF(fmt, args...) \ do { printf("lsi_scsi: " fmt , ##args); } while (0) #define BADF(fmt, args...) \ do { fprintf(stderr, "lsi_scsi: " fmt , ##args); exit(1);} while (0) #else #define DPRINTF(fmt, args...) do {} while(0) #define BADF(fmt, args...) \ do { fprintf(stderr, "lsi_scsi: " fmt , ##args); } while (0) #endif #define LSI_SCNTL0_TRG 0x01 #define LSI_SCNTL0_AAP 0x02 #define LSI_SCNTL0_EPC 0x08 #define LSI_SCNTL0_WATN 0x10 #define LSI_SCNTL0_START 0x20 #define LSI_SCNTL1_SST 0x01 #define LSI_SCNTL1_IARB 0x02 #define LSI_SCNTL1_AESP 0x04 #define LSI_SCNTL1_RST 0x08 #define LSI_SCNTL1_CON 0x10 #define LSI_SCNTL1_DHP 0x20 #define LSI_SCNTL1_ADB 0x40 #define LSI_SCNTL1_EXC 0x80 #define LSI_SCNTL2_WSR 0x01 #define LSI_SCNTL2_VUE0 0x02 #define LSI_SCNTL2_VUE1 0x04 #define LSI_SCNTL2_WSS 0x08 #define LSI_SCNTL2_SLPHBEN 0x10 #define LSI_SCNTL2_SLPMD 0x20 #define LSI_SCNTL2_CHM 0x40 #define LSI_SCNTL2_SDU 0x80 #define LSI_ISTAT0_DIP 0x01 #define LSI_ISTAT0_SIP 0x02 #define LSI_ISTAT0_INTF 0x04 #define LSI_ISTAT0_CON 0x08 #define LSI_ISTAT0_SEM 0x10 #define LSI_ISTAT0_SIGP 0x20 #define LSI_ISTAT0_SRST 0x40 #define LSI_ISTAT0_ABRT 0x80 #define LSI_ISTAT1_SI 0x01 #define LSI_ISTAT1_SRUN 0x02 #define LSI_ISTAT1_FLSH 0x04 #define LSI_SSTAT0_SDP0 0x01 #define LSI_SSTAT0_RST 0x02 #define LSI_SSTAT0_WOA 0x04 #define LSI_SSTAT0_LOA 0x08 #define LSI_SSTAT0_AIP 0x10 #define LSI_SSTAT0_OLF 0x20 #define LSI_SSTAT0_ORF 0x40 #define LSI_SSTAT0_ILF 0x80 #define LSI_SIST0_PAR 0x01 #define LSI_SIST0_RST 0x02 #define LSI_SIST0_UDC 0x04 #define LSI_SIST0_SGE 0x08 #define LSI_SIST0_RSL 0x10 #define LSI_SIST0_SEL 0x20 #define LSI_SIST0_CMP 0x40 #define LSI_SIST0_MA 0x80 #define LSI_SIST1_HTH 0x01 #define LSI_SIST1_GEN 0x02 #define LSI_SIST1_STO 0x04 #define LSI_SIST1_SBMC 0x10 #define LSI_SOCL_IO 0x01 #define LSI_SOCL_CD 0x02 #define LSI_SOCL_MSG 0x04 #define LSI_SOCL_ATN 0x08 #define LSI_SOCL_SEL 0x10 #define LSI_SOCL_BSY 0x20 #define LSI_SOCL_ACK 0x40 #define LSI_SOCL_REQ 0x80 #define LSI_DSTAT_IID 0x01 #define LSI_DSTAT_SIR 0x04 #define LSI_DSTAT_SSI 0x08 #define LSI_DSTAT_ABRT 0x10 #define LSI_DSTAT_BF 0x20 #define LSI_DSTAT_MDPE 0x40 #define LSI_DSTAT_DFE 0x80 #define LSI_DCNTL_COM 0x01 #define LSI_DCNTL_IRQD 0x02 #define LSI_DCNTL_STD 0x04 #define LSI_DCNTL_IRQM 0x08 #define LSI_DCNTL_SSM 0x10 #define LSI_DCNTL_PFEN 0x20 #define LSI_DCNTL_PFF 0x40 #define LSI_DCNTL_CLSE 0x80 #define LSI_DMODE_MAN 0x01 #define LSI_DMODE_BOF 0x02 #define LSI_DMODE_ERMP 0x04 #define LSI_DMODE_ERL 0x08 #define LSI_DMODE_DIOM 0x10 #define LSI_DMODE_SIOM 0x20 #define LSI_CTEST2_DACK 0x01 #define LSI_CTEST2_DREQ 0x02 #define LSI_CTEST2_TEOP 0x04 #define LSI_CTEST2_PCICIE 0x08 #define LSI_CTEST2_CM 0x10 #define LSI_CTEST2_CIO 0x20 #define LSI_CTEST2_SIGP 0x40 #define LSI_CTEST2_DDIR 0x80 #define LSI_CTEST5_BL2 0x04 #define LSI_CTEST5_DDIR 0x08 #define LSI_CTEST5_MASR 0x10 #define LSI_CTEST5_DFSN 0x20 #define LSI_CTEST5_BBCK 0x40 #define LSI_CTEST5_ADCK 0x80 #define LSI_CCNTL0_DILS 0x01 #define LSI_CCNTL0_DISFC 0x10 #define LSI_CCNTL0_ENNDJ 0x20 #define LSI_CCNTL0_PMJCTL 0x40 #define LSI_CCNTL0_ENPMJ 0x80 #define PHASE_DO 0 #define PHASE_DI 1 #define PHASE_CMD 2 #define PHASE_ST 3 #define PHASE_MO 6 #define PHASE_MI 7 #define PHASE_MASK 7 /* The HBA is ID 7, so for simplicitly limit to 7 devices. */ #define LSI_MAX_DEVS 7 typedef struct { PCIDevice pci_dev; int mmio_io_addr; int ram_io_addr; uint32_t script_ram_base; uint32_t data_len; int carry; /* ??? Should this be an a visible register somewhere? */ int sense; uint8_t msg; /* Nonzero if a Wait Reselect instruction has been issued. */ int waiting; SCSIDevice *scsi_dev[LSI_MAX_DEVS]; SCSIDevice *current_dev; int current_lun; uint32_t dsa; uint32_t temp; uint32_t dnad; uint32_t dbc; uint8_t istat0; uint8_t istat1; uint8_t dcmd; uint8_t dstat; uint8_t dien; uint8_t sist0; uint8_t sist1; uint8_t sien0; uint8_t sien1; uint8_t mbox0; uint8_t mbox1; uint8_t dfifo; uint8_t ctest3; uint8_t ctest4; uint8_t ctest5; uint8_t ccntl0; uint8_t ccntl1; uint32_t dsp; uint32_t dsps; uint8_t dmode; uint8_t dcntl; uint8_t scntl0; uint8_t scntl1; uint8_t scntl2; uint8_t scntl3; uint8_t sstat0; uint8_t sstat1; uint8_t scid; uint8_t sxfer; uint8_t socl; uint8_t sdid; uint8_t sfbr; uint8_t stest1; uint8_t stest2; uint8_t stest3; uint8_t stime0; uint8_t respid0; uint8_t respid1; uint32_t mmrs; uint32_t mmws; uint32_t sfs; uint32_t drs; uint32_t sbms; uint32_t dmbs; uint32_t dnad64; uint32_t pmjad1; uint32_t pmjad2; uint32_t rbc; uint32_t ua; uint32_t ia; uint32_t sbc; uint32_t csbc; uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */ /* Script ram is stored as 32-bit words in host byteorder. */ uint32_t script_ram[2048]; } LSIState; static void lsi_soft_reset(LSIState *s) { DPRINTF("Reset\n"); s->carry = 0; s->waiting = 0; s->dsa = 0; s->dnad = 0; s->dbc = 0; s->temp = 0; memset(s->scratch, 0, sizeof(s->scratch)); s->istat0 = 0; s->istat1 = 0; s->dcmd = 0; s->dstat = 0; s->dien = 0; s->sist0 = 0; s->sist1 = 0; s->sien0 = 0; s->sien1 = 0; s->mbox0 = 0; s->mbox1 = 0; s->dfifo = 0; s->ctest3 = 0; s->ctest4 = 0; s->ctest5 = 0; s->ccntl0 = 0; s->ccntl1 = 0; s->dsp = 0; s->dsps = 0; s->dmode = 0; s->dcntl = 0; s->scntl0 = 0xc0; s->scntl1 = 0; s->scntl2 = 0; s->scntl3 = 0; s->sstat0 = 0; s->sstat1 = 0; s->scid = 7; s->sxfer = 0; s->socl = 0; s->stest1 = 0; s->stest2 = 0; s->stest3 = 0; s->stime0 = 0; s->respid0 = 0x80; s->respid1 = 0; s->mmrs = 0; s->mmws = 0; s->sfs = 0; s->drs = 0; s->sbms = 0; s->dmbs = 0; s->dnad64 = 0; s->pmjad1 = 0; s->pmjad2 = 0; s->rbc = 0; s->ua = 0; s->ia = 0; s->sbc = 0; s->csbc = 0; } static uint8_t lsi_reg_readb(LSIState *s, int offset); static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val); static inline uint32_t read_dword(LSIState *s, uint32_t addr) { uint32_t buf; /* Optimize reading from SCRIPTS RAM. */ if ((addr & 0xffffe000) == s->script_ram_base) { return s->script_ram[(addr & 0x1fff) >> 2]; } cpu_physical_memory_read(addr, (uint8_t *)&buf, 4); return cpu_to_le32(buf); } static void lsi_stop_script(LSIState *s) { s->istat1 &= ~LSI_ISTAT1_SRUN; } static void lsi_update_irq(LSIState *s) { int level; static int last_level; /* It's unclear whether the DIP/SIP bits should be cleared when the Interrupt Status Registers are cleared or when istat0 is read. We currently do the formwer, which seems to work. */ level = 0; if (s->dstat) { if (s->dstat & s->dien) level = 1; s->istat0 |= LSI_ISTAT0_DIP; } else { s->istat0 &= ~LSI_ISTAT0_DIP; } if (s->sist0 || s->sist1) { if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1)) level = 1; s->istat0 |= LSI_ISTAT0_SIP; } else { s->istat0 &= ~LSI_ISTAT0_SIP; } if (s->istat0 & LSI_ISTAT0_INTF) level = 1; if (level != last_level) { DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n", level, s->dstat, s->sist1, s->sist0); last_level = level; } pci_set_irq(&s->pci_dev, 0, level); } /* Stop SCRIPTS execution and raise a SCSI interrupt. */ static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1) { uint32_t mask0; uint32_t mask1; DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n", stat1, stat0, s->sist1, s->sist0); s->sist0 |= stat0; s->sist1 |= stat1; /* Stop processor on fatal or unmasked interrupt. As a special hack we don't stop processing when raising STO. Instead continue execution and stop at the next insn that accesses the SCSI bus. */ mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL); mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH); mask1 &= ~LSI_SIST1_STO; if (s->sist0 & mask0 || s->sist1 & mask1) { lsi_stop_script(s); } lsi_update_irq(s); } /* Stop SCRIPTS execution and raise a DMA interrupt. */ static void lsi_script_dma_interrupt(LSIState *s, int stat) { DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat); s->dstat |= stat; lsi_update_irq(s); lsi_stop_script(s); } static inline void lsi_set_phase(LSIState *s, int phase) { s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase; } static void lsi_bad_phase(LSIState *s, int out, int new_phase) { /* Trigger a phase mismatch. */ if (s->ccntl0 & LSI_CCNTL0_ENPMJ) { if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) { s->dsp = s->pmjad1; } else { s->dsp = s->pmjad2; } DPRINTF("Data phase mismatch jump to %08x\n", s->dsp); } else { DPRINTF("Phase mismatch interrupt\n"); lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0); lsi_stop_script(s); } lsi_set_phase(s, new_phase); } static void lsi_do_dma(LSIState *s, int out) { uint8_t buf[TARGET_PAGE_SIZE]; uint32_t addr; uint32_t count; int n; count = s->dbc; addr = s->dnad; DPRINTF("DMA %s addr=0x%08x len=%d avail=%d\n", out ? "out" : "in", addr, count, s->data_len); /* ??? Too long transfers are truncated. Don't know if this is the correct behavior. */ if (count > s->data_len) { /* If the DMA length is greater then the device data length then a phase mismatch 
/*
    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.
    You may obtain a copy of the License at

        http://www.apache.org/licenses/LICENSE-2.0

    Unless required by applicable law or agreed to in writing, software
    distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
*/

/*
 * STM32F30x drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

#define STM32F37x_MCUCONF

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   TRUE
#define STM32_HSE_ENABLED                   TRUE
#define STM32_LSE_ENABLED                   FALSE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSE
#define STM32_PREDIV_VALUE                  1
#define STM32_PLLMUL_VALUE                  9
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV2
#define STM32_PPRE2                         STM32_PPRE2_DIV2
#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE                        STM32_ADCPRE_DIV4
#define STM32_SDPRE                         STM32_SDPRE_DIV12
#define STM32_USART1SW                      STM32_USART1SW_PCLK
#define STM32_USART2SW                      STM32_USART2SW_PCLK
#define STM32_USART3SW                      STM32_USART3SW_PCLK
#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
#define STM32_RTCSEL                        STM32_RTCSEL_LSI
#define STM32_USB_CLOCK_REQUIRED            TRUE
#define STM32_USBPRE                        STM32_USBPRE_DIV1P5

/*
 * ADC driver system settings.
 */
#define STM32_ADC_USE_ADC1                  TRUE
#define STM32_ADC_USE_SDADC1                FALSE
#define STM32_ADC_USE_SDADC2                FALSE
#define STM32_ADC_USE_SDADC3                FALSE
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_SDADC1_DMA_PRIORITY       2
#define STM32_ADC_SDADC2_DMA_PRIORITY       2
#define STM32_ADC_SDADC3_DMA_PRIORITY       2
#define STM32_ADC_ADC1_IRQ_PRIORITY         5
#define STM32_ADC_SDADC1_IRQ_PRIORITY       5
#define STM32_ADC_SDADC2_IRQ_PRIORITY       5
#define STM32_ADC_SDADC3_IRQ_PRIORITY       5
#define STM32_ADC_SDADC1_DMA_IRQ_PRIORITY   5
#define STM32_ADC_SDADC2_DMA_IRQ_PRIORITY   5
#define STM32_ADC_SDADC3_DMA_IRQ_PRIORITY   5

/*
 * CAN driver system settings.
 */
#define STM32_CAN_USE_CAN1                  TRUE
#define STM32_CAN_CAN1_IRQ_PRIORITY         11

/*
 * EXT driver system settings.
 */
#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
#define STM32_EXT_EXTI17_IRQ_PRIORITY       6
#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
#define STM32_EXT_EXTI20_23_IRQ_PRIORITY    6
#define STM32_EXT_EXTI30_32_IRQ_PRIORITY    6
#define STM32_EXT_EXTI33_IRQ_PRIORITY       6

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM2                  FALSE
#define STM32_GPT_USE_TIM3                  FALSE
#define STM32_GPT_USE_TIM4                  FALSE
#define STM32_GPT_USE_TIM5                  FALSE
#define STM32_GPT_USE_TIM6                  FALSE
#define STM32_GPT_USE_TIM7                  FALSE
#define STM32_GPT_USE_TIM12                 FALSE
#define STM32_GPT_USE_TIM14                 FALSE
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
#define STM32_GPT_TIM4_IRQ_PRIORITY         7
#define STM32_GPT_TIM5_IRQ_PRIORITY         7
#define STM32_GPT_TIM6_IRQ_PRIORITY         7
#define STM32_GPT_TIM7_IRQ_PRIORITY         7
#define STM32_GPT_TIM12_IRQ_PRIORITY        7
#define STM32_GPT_TIM14_IRQ_PRIORITY        7

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_BUSY_TIMEOUT              50
#define STM32_I2C_I2C1_IRQ_PRIORITY         10
#define STM32_I2C_I2C2_IRQ_PRIORITY         10
#define STM32_I2C_I2C1_DMA_PRIORITY         1
#define STM32_I2C_I2C2_DMA_PRIORITY         1
#define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM2                  FALSE
#define STM32_ICU_USE_TIM3                  FALSE
#define STM32_ICU_USE_TIM4                  FALSE
#define STM32_ICU_USE_TIM5                  FALSE
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
#define STM32_ICU_TIM5_IRQ_PRIORITY         7

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_TIM2                  FALSE
#define STM32_PWM_USE_TIM3                  FALSE
#define STM32_PWM_USE_TIM4                  FALSE
#define STM32_PWM_USE_TIM5                  FALSE
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
#define STM32_PWM_TIM5_IRQ_PRIORITY         7

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             FALSE
#define STM32_SERIAL_USE_USART2             FALSE
#define STM32_SERIAL_USE_USART3             FALSE
#define STM32_SERIAL_USE_UART4              FALSE
#define STM32_SERIAL_USE_UART5              FALSE
#define STM32_SERIAL_USART1_PRIORITY        12
#define STM32_SERIAL_USART2_PRIORITY        12
#define STM32_SERIAL_USART3_PRIORITY        12
#define STM32_SERIAL_UART4_PRIORITY         12
#define STM32_SERIAL_UART5_PRIORITY         12

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  FALSE
#define STM32_SPI_USE_SPI2                  FALSE
#define STM32_SPI_USE_SPI3                  FALSE
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI3_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
#define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

/*
 * ST driver system settings.
 */
#define STM32_ST_IRQ_PRIORITY               8
#define STM32_ST_USE_TIMER                  2

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USE_USART3               FALSE
#define STM32_UART_USART1_IRQ_PRIORITY      12
#define STM32_UART_USART2_IRQ_PRIORITY      12
#define STM32_UART_USART3_IRQ_PRIORITY      12
#define STM32_UART_USART1_DMA_PRIORITY      0
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART3_DMA_PRIORITY      0
#define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

/*
 * USB driver system settings.
 */
#define STM32_USB_USE_USB1                  FALSE
#define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE
#define STM32_USB_USB1_HP_IRQ_PRIORITY      13
#define STM32_USB_USB1_LP_IRQ_PRIORITY      14
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-17 02:35:33 +0000
>sien0; case 0x41: /* SIEN1 */ return s->sien1; case 0x42: /* SIST0 */ tmp = s->sist0; s->sist0 = 0; lsi_update_irq(s); return tmp; case 0x43: /* SIST1 */ tmp = s->sist1; s->sist1 = 0; lsi_update_irq(s); return tmp; case 0x47: /* GPCNTL0 */ return 0x0f; case 0x48: /* STIME0 */ return s->stime0; case 0x4a: /* RESPID0 */ return s->respid0; case 0x4b: /* RESPID1 */ return s->respid1; case 0x4d: /* STEST1 */ return s->stest1; case 0x4e: /* STEST2 */ return s->stest2; case 0x4f: /* STEST3 */ return s->stest3; case 0x52: /* STEST4 */ return 0xe0; case 0x56: /* CCNTL0 */ return s->ccntl0; case 0x57: /* CCNTL1 */ return s->ccntl1; case 0x58: case 0x59: /* SBDL */ return 0; CASE_GET_REG32(mmrs, 0xa0) CASE_GET_REG32(mmws, 0xa4) CASE_GET_REG32(sfs, 0xa8) CASE_GET_REG32(drs, 0xac) CASE_GET_REG32(sbms, 0xb0) CASE_GET_REG32(dmbs, 0xb4) CASE_GET_REG32(dnad64, 0xb8) CASE_GET_REG32(pmjad1, 0xc0) CASE_GET_REG32(pmjad2, 0xc4) CASE_GET_REG32(rbc, 0xc8) CASE_GET_REG32(ua, 0xcc) CASE_GET_REG32(ia, 0xd4) CASE_GET_REG32(sbc, 0xd8) CASE_GET_REG32(csbc, 0xdc) } if (offset >= 0x5c && offset < 0xa0) { int n; int shift; n = (offset - 0x58) >> 2; shift = (offset & 3) * 8; return (s->scratch[n] >> shift) & 0xff; } BADF("readb 0x%x\n", offset); exit(1); #undef CASE_GET_REG32 } static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) { #define CASE_SET_REG32(name, addr) \ case addr : s->name &= 0xffffff00; s->name |= val; break; \ case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \ case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \ case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break; #ifdef DEBUG_LSI_REG DPRINTF("Write reg %x = %02x\n", offset, val); #endif switch (offset) { case 0x00: /* SCNTL0 */ s->scntl0 = val; if (val & LSI_SCNTL0_START) { BADF("Start sequence not implemented\n"); } break; case 0x01: /* SCNTL1 */ s->scntl1 = val & ~LSI_SCNTL1_SST; if (val & LSI_SCNTL1_IARB) { BADF("Immediate Arbritration not implemented\n"); } if (val & LSI_SCNTL1_RST) { s->sstat0 |= LSI_SSTAT0_RST; lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0); } else { s->sstat0 &= ~LSI_SSTAT0_RST; } break; case 0x02: /* SCNTL2 */ val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS); s->scntl3 = val; break; case 0x03: /* SCNTL3 */ s->scntl3 = val; break; case 0x04: /* SCID */ s->scid = val; break; case 0x05: /* SXFER */ s->sxfer = val; break; case 0x07: /* GPREG0 */ break; case 0x0c: case 0x0d: case 0x0e: case 0x0f: /* Linux writes to these readonly registers on startup. */ return; CASE_SET_REG32(dsa, 0x10) case 0x14: /* ISTAT0 */ s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0); if (val & LSI_ISTAT0_ABRT) { lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT); } if (val & LSI_ISTAT0_INTF) { s->istat0 &= ~LSI_ISTAT0_INTF; lsi_update_irq(s); } if (s->waiting && val & LSI_ISTAT0_SIGP) { DPRINTF("Woken by SIGP\n"); s->waiting = 0; s->dsp = s->dnad; lsi_execute_script(s); } if (val & LSI_ISTAT0_SRST) { lsi_soft_reset(s); } case 0x16: /* MBOX0 */ s->mbox0 = val; case 0x17: /* MBOX1 */ s->mbox1 = val; case 0x1b: /* CTEST3 */ s->ctest3 = val & 0x0f; break; CASE_SET_REG32(temp, 0x1c) case 0x21: /* CTEST4 */ if (val & 7) { BADF("Unimplemented CTEST4-FBL 0x%x\n", val); } s->ctest4 = val; break; case 0x22: /* CTEST5 */ if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) { BADF("CTEST5 DMA increment not implemented\n"); } s->ctest5 = val; break; case 0x2c: /* DSPS[0:7] */ s->dsp &= 0xffffff00; s->dsp |= val; break; case 0x2d: /* DSPS[8:15] */ s->dsp &= 0xffff00ff; s->dsp |= val << 8; break; case 0x2e: /* DSPS[16:23] */ s->dsp &= 0xff00ffff; s->dsp |= val << 16; break; case 0x2f: /* DSPS[14:31] */ s->dsp &= 0x00ffffff; s->dsp |= val << 24; if ((s->dmode & LSI_DMODE_MAN) == 0 && (s->istat1 & LSI_ISTAT1_SRUN) == 0) lsi_execute_script(s); break; CASE_SET_REG32(dsps, 0x30) CASE_SET_REG32(scratch[0], 0x34) case 0x38: /* DMODE */ if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) { BADF("IO mappings not implemented\n"); } s->dmode = val; break; case 0x39: /* DIEN */ s->dien = val; lsi_update_irq(s); break; case 0x3b: /* DCNTL */ s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD); if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0) lsi_execute_script(s); break; case 0x40: /* SIEN0 */ s->sien0 = val; lsi_update_irq(s); break; case 0x41: /* SIEN1 */ s->sien1 = val; lsi_update_irq(s); break; case 0x47: /* GPCNTL0 */ break; case 0x48: /* STIME0 */ s->stime0 = val; break; case 0x49: /* STIME1 */ if (val & 0xf) { DPRINTF("General purpose timer not implemented\n"); /* ??? Raising the interrupt immediately seems to be sufficient to keep the FreeBSD driver happy. */ lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN); } break; case 0x4a: /* RESPID0 */ s->respid0 = val; break; case 0x4b: /* RESPID1 */ s->respid1 = val; break; case 0x4d: /* STEST1 */ s->stest1 = val; break; case 0x4e: /* STEST2 */ if (val & 1) { BADF("Low level mode not implemented\n"); } s->stest2 = val; break; case 0x4f: /* STEST3 */ if (val & 0x41) { BADF("SCSI FIFO test mode not implemented\n"); } s->stest3 = val; break; case 0x56: /* CCNTL0 */ s->ccntl0 = val; break; case 0x57: /* CCNTL1 */ s->ccntl1 = val; break; CASE_SET_REG32(mmrs, 0xa0) CASE_SET_REG32(mmws, 0xa4) CASE_SET_REG32(sfs, 0xa8) CASE_SET_REG32(drs, 0xac) CASE_SET_REG32(sbms, 0xb0) CASE_SET_REG32(dmbs, 0xb4) CASE_SET_REG32(dnad64, 0xb8) CASE_SET_REG32(pmjad1, 0xc0) CASE_SET_REG32(pmjad2, 0xc4) CASE_SET_REG32(rbc, 0xc8) CASE_SET_REG32(ua, 0xcc) CASE_SET_REG32(ia, 0xd4) CASE_SET_REG32(sbc, 0xd8) CASE_SET_REG32(csbc, 0xdc) default: if (offset >= 0x5c && offset < 0xa0) { int n; int shift; n = (offset - 0x58) >> 2; shift = (offset & 3) * 8; s->scratch[n] &= ~(0xff << shift); s->scratch[n] |= (val & 0xff) << shift; } else { BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val); } } #undef CASE_SET_REG32 } static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; lsi_reg_writeb(s, addr & 0xff, val); } static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); } static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff); lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff); } static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr) { LSIState *s = (LSIState *)opaque; return lsi_reg_readb(s, addr & 0xff); } static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr) { LSIState *s = (LSIState *)opaque; uint32_t val; addr &= 0xff; val = lsi_reg_readb(s, addr); val |= lsi_reg_readb(s, addr + 1) << 8; return val; } static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr) { LSIState *s = (LSIState *)opaque; uint32_t val; addr &= 0xff; val = lsi_reg_readb(s, addr); val |= lsi_reg_readb(s, addr + 1) << 8; val |= lsi_reg_readb(s, addr + 2) << 16; val |= lsi_reg_readb(s, addr + 3) << 24; return val; } static CPUReadMemoryFunc *lsi_mmio_readfn[3] = { lsi_mmio_readb, lsi_mmio_readw, lsi_mmio_readl, }; static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = { lsi_mmio_writeb, lsi_mmio_writew, lsi_mmio_writel, }; static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; uint32_t newval; int shift; addr &= 0x1fff; newval = s->script_ram[addr >> 2]; shift = (addr & 3) * 8; newval &= ~(0xff << shift); newval |= val << shift; s->script_ram[addr >> 2] = newval; } static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; uint32_t newval; addr &= 0x1fff; newval = s->script_ram[addr >> 2]; if (addr & 2) { newval = (newval & 0xffff) | (val << 16); } else { newval = (newval & 0xffff0000) | val; } s->script_ram[addr >> 2] = newval; } static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; addr &= 0x1fff; s->script_ram[addr >> 2] = val; } static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr) { LSIState *s = (LSIState *)opaque; uint32_t val; addr &= 0x1fff; val = s->script_ram[addr >> 2]; val >>= (addr & 3) * 8; return val & 0xff; } static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr) { LSIState *s = (LSIState *)opaque; uint32_t val; addr &= 0x1fff; val = s->script_ram[addr >> 2]; if (addr & 2) val >>= 16; return le16_to_cpu(val); } static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr) { LSIState *s = (LSIState *)opaque; addr &= 0x1fff; return le32_to_cpu(s->script_ram[addr >> 2]); } static CPUReadMemoryFunc *lsi_ram_readfn[3] = { lsi_ram_readb, lsi_ram_readw, lsi_ram_readl, }; static CPUWriteMemoryFunc *lsi_ram_writefn[3] = { lsi_ram_writeb, lsi_ram_writew, lsi_ram_writel, }; static uint32_t lsi_io_readb(void *opaque, uint32_t addr) { LSIState *s = (LSIState *)opaque; return lsi_reg_readb(s, addr & 0xff); } static uint32_t lsi_io_readw(void *opaque, uint32_t addr) { LSIState *s = (LSIState *)opaque; uint32_t val; addr &= 0xff; val = lsi_reg_readb(s, addr); val |= lsi_reg_readb(s, addr + 1) << 8; return val; } static uint32_t lsi_io_readl(void *opaque, uint32_t addr) { LSIState *s = (LSIState *)opaque; uint32_t val; addr &= 0xff; val = lsi_reg_readb(s, addr); val |= lsi_reg_readb(s, addr + 1) << 8; val |= lsi_reg_readb(s, addr + 2) << 16; val |= lsi_reg_readb(s, addr + 3) << 24; return val; } static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; lsi_reg_writeb(s, addr & 0xff, val); } static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); } static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val) { LSIState *s = (LSIState *)opaque; addr &= 0xff; lsi_reg_writeb(s, addr, val & 0xff); lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff); lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff); lsi_reg_writeb(s, addr + 2, (val >> 24) & 0xff); } static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num, uint32_t addr, uint32_t size, int type) { LSIState *s = (LSIState *)pci_dev; DPRINTF("Mapping IO at %08x\n", addr); register_ioport_write(addr, 256, 1, lsi_io_writeb, s); register_ioport_read(addr, 256, 1, lsi_io_readb, s); register_ioport_write(addr, 256, 2, lsi_io_writew, s); register_ioport_read(addr, 256, 2, lsi_io_readw, s); register_ioport_write(addr, 256, 4, lsi_io_writel, s); register_ioport_read(addr, 256, 4, lsi_io_readl, s); } static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num, uint32_t addr, uint32_t size, int type) { LSIState *s = (LSIState *)pci_dev; DPRINTF("Mapping ram at %08x\n", addr); s->script_ram_base = addr; cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr); } static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num, uint32_t addr, uint32_t size, int type) { LSIState *s = (LSIState *)pci_dev; DPRINTF("Mapping registers at %08x\n", addr); cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr); } void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id) { LSIState *s = (LSIState *)opaque; if (id < 0) { for (id = 0; id < LSI_MAX_DEVS; id++) { if (s->scsi_dev[id] == NULL) break; } } if (id >= LSI_MAX_DEVS) { BADF("Bad Device ID %d\n", id); return; } if (s->scsi_dev[id]) { DPRINTF("Destroying device %d\n", id); scsi_disk_destroy(s->scsi_dev[id]); } DPRINTF("Attaching block device %d\n", id); s->scsi_dev[id] = scsi_disk_init(bd, lsi_command_complete, s); } void *lsi_scsi_init(PCIBus *bus, int devfn) { LSIState *s; s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA", sizeof(*s), devfn, NULL, NULL); if (s == NULL) { fprintf(stderr, "lsi-scsi: Failed to register PCI device\n"); return NULL; } s->pci_dev.config[0x00] = 0x00; s->pci_dev.config[0x01] = 0x10; s->pci_dev.config[0x02] = 0x12; s->pci_dev.config[0x03] = 0x00; s->pci_dev.config[0x0b] = 0x01; s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */ s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn, lsi_mmio_writefn, s); s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn, lsi_ram_writefn, s); pci_register_io_region((struct PCIDevice *)s, 0, 256, PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc); pci_register_io_region((struct PCIDevice *)s, 1, 0x400, PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc); pci_register_io_region((struct PCIDevice *)s, 2, 0x2000, PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc); lsi_soft_reset(s); return s; }